2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #define AR_EEPROM_MODAL_SPURS 5
23 #include <net/cfg80211.h>
24 #include "ar9003_eeprom.h"
26 #define AH_USE_EEPROM 0x1
29 #define AR5416_EEPROM_MAGIC 0x5aa5
31 #define AR5416_EEPROM_MAGIC 0xa55a
34 #define CTRY_DEBUG 0x1ff
35 #define CTRY_DEFAULT 0
37 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
38 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
39 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
40 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
41 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
42 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
43 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
44 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
45 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
47 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
48 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
49 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
50 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
51 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
52 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
54 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
55 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
57 #define AR5416_EEPROM_MAGIC_OFFSET 0x0
58 #define AR5416_EEPROM_S 2
59 #define AR5416_EEPROM_OFFSET 0x2000
60 #define AR5416_EEPROM_MAX 0xae0
62 #define AR5416_EEPROM_START_ADDR \
63 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
65 #define SD_NO_CTL 0xE0
67 #define CTL_MODE_M 0xf
76 #define EXT_ADDITIVE (0x8000)
77 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
78 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
79 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
81 #define SUB_NUM_CTL_MODES_AT_5G_40 2
82 #define SUB_NUM_CTL_MODES_AT_2G_40 3
84 #define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
85 #define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
88 * For AR9285 and later chipsets, the following bits are not being programmed
89 * in EEPROM and so need to be enabled always.
93 * Bit 2: en_fcc_dfs_ht40
95 * Bit 4: en_jap_dfs_ht40
97 #define AR9285_RDEXT_DEFAULT 0x1F
99 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
100 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
101 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
103 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
104 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
105 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
106 #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \
107 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
109 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
110 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
111 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
112 #define AR_EEPROM_RFSILENT_POLARITY_S 1
114 #define EEP_RFSILENT_ENABLED 0x0001
115 #define EEP_RFSILENT_ENABLED_S 0
116 #define EEP_RFSILENT_POLARITY 0x0002
117 #define EEP_RFSILENT_POLARITY_S 1
118 #define EEP_RFSILENT_GPIO_SEL 0x001c
119 #define EEP_RFSILENT_GPIO_SEL_S 2
121 #define AR5416_OPFLAGS_11A 0x01
122 #define AR5416_OPFLAGS_11G 0x02
123 #define AR5416_OPFLAGS_N_5G_HT40 0x04
124 #define AR5416_OPFLAGS_N_2G_HT40 0x08
125 #define AR5416_OPFLAGS_N_5G_HT20 0x10
126 #define AR5416_OPFLAGS_N_2G_HT20 0x20
128 #define AR5416_EEP_NO_BACK_VER 0x1
129 #define AR5416_EEP_VER 0xE
130 #define AR5416_EEP_VER_MINOR_MASK 0x0FFF
131 #define AR5416_EEP_MINOR_VER_2 0x2
132 #define AR5416_EEP_MINOR_VER_3 0x3
133 #define AR5416_EEP_MINOR_VER_7 0x7
134 #define AR5416_EEP_MINOR_VER_9 0x9
135 #define AR5416_EEP_MINOR_VER_16 0x10
136 #define AR5416_EEP_MINOR_VER_17 0x11
137 #define AR5416_EEP_MINOR_VER_19 0x13
138 #define AR5416_EEP_MINOR_VER_20 0x14
139 #define AR5416_EEP_MINOR_VER_21 0x15
140 #define AR5416_EEP_MINOR_VER_22 0x16
142 #define AR5416_NUM_5G_CAL_PIERS 8
143 #define AR5416_NUM_2G_CAL_PIERS 4
144 #define AR5416_NUM_5G_20_TARGET_POWERS 8
145 #define AR5416_NUM_5G_40_TARGET_POWERS 8
146 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
147 #define AR5416_NUM_2G_20_TARGET_POWERS 4
148 #define AR5416_NUM_2G_40_TARGET_POWERS 4
149 #define AR5416_NUM_CTLS 24
150 #define AR5416_NUM_BAND_EDGES 8
151 #define AR5416_NUM_PD_GAINS 4
152 #define AR5416_PD_GAINS_IN_MASK 4
153 #define AR5416_PD_GAIN_ICEPTS 5
154 #define AR5416_NUM_PDADC_VALUES 128
155 #define AR5416_BCHAN_UNUSED 0xFF
156 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
157 #define AR5416_MAX_CHAINS 3
158 #define AR9300_MAX_CHAINS 3
159 #define AR5416_PWR_TABLE_OFFSET_DB -5
161 /* Rx gain type values */
162 #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
163 #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
164 #define AR5416_EEP_RXGAIN_ORIG 2
166 /* Tx gain type values */
167 #define AR5416_EEP_TXGAIN_ORIGINAL 0
168 #define AR5416_EEP_TXGAIN_HIGH_POWER 1
170 #define AR5416_EEP4K_START_LOC 64
171 #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
172 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
173 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
174 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
175 #define AR5416_EEP4K_NUM_CTLS 12
176 #define AR5416_EEP4K_NUM_BAND_EDGES 4
177 #define AR5416_EEP4K_NUM_PD_GAINS 2
178 #define AR5416_EEP4K_MAX_CHAINS 1
180 #define AR9280_TX_GAIN_TABLE_SIZE 22
182 #define AR9287_EEP_VER 0xE
183 #define AR9287_EEP_VER_MINOR_MASK 0xFFF
184 #define AR9287_EEP_MINOR_VER_1 0x1
185 #define AR9287_EEP_MINOR_VER_2 0x2
186 #define AR9287_EEP_MINOR_VER_3 0x3
187 #define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3
188 #define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER
189 #define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1
191 #define AR9287_EEP_START_LOC 128
192 #define AR9287_HTC_EEP_START_LOC 256
193 #define AR9287_NUM_2G_CAL_PIERS 3
194 #define AR9287_NUM_2G_CCK_TARGET_POWERS 3
195 #define AR9287_NUM_2G_20_TARGET_POWERS 3
196 #define AR9287_NUM_2G_40_TARGET_POWERS 3
197 #define AR9287_NUM_CTLS 12
198 #define AR9287_NUM_BAND_EDGES 4
199 #define AR9287_PD_GAIN_ICEPTS 1
200 #define AR9287_EEPMISC_BIG_ENDIAN 0x01
201 #define AR9287_EEPMISC_WOW 0x02
202 #define AR9287_MAX_CHAINS 2
203 #define AR9287_ANT_16S 32
205 #define AR9287_DATA_SZ 32
207 #define AR9287_PWR_TABLE_OFFSET_DB -5
209 #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
211 #define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f)
212 #define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03)
214 #define LNA_CTL_BUF_MODE BIT(0)
215 #define LNA_CTL_ISEL_LO BIT(1)
216 #define LNA_CTL_ISEL_HI BIT(2)
217 #define LNA_CTL_BUF_IN BIT(3)
218 #define LNA_CTL_FEM_BAND BIT(4)
219 #define LNA_CTL_LOCAL_BIAS BIT(5)
220 #define LNA_CTL_FORCE_XPA BIT(6)
221 #define LNA_CTL_USE_ANT1 BIT(7)
250 EEP_TEMPSENSE_SLOPE_PAL_ON,
251 EEP_PWR_TABLE_OFFSET,
253 EEP_INTERNAL_REGULATOR,
258 EEP_CHAIN_MASK_REDUCE
262 rate6mb, rate9mb, rate12mb, rate18mb,
263 rate24mb, rate36mb, rate48mb, rate54mb,
264 rate1l, rate2l, rate2s, rate5_5l,
265 rate5_5s, rate11l, rate11s, rateXr,
266 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
267 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
268 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
269 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
270 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
274 enum ath9k_hal_freq_band {
275 ATH9K_HAL_FREQ_BAND_5GHZ = 0,
276 ATH9K_HAL_FREQ_BAND_2GHZ = 1
279 struct base_eep_header {
290 u16 blueToothOptions;
309 struct base_eep_header_4k {
320 u16 blueToothOptions;
334 struct modal_eep_header {
335 u32 antCtrlChain[AR5416_MAX_CHAINS];
337 u8 antennaGainCh[AR5416_MAX_CHAINS];
339 u8 txRxAttenCh[AR5416_MAX_CHAINS];
340 u8 rxTxMarginCh[AR5416_MAX_CHAINS];
343 u8 xlnaGainCh[AR5416_MAX_CHAINS];
348 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
351 u8 iqCalICh[AR5416_MAX_CHAINS];
352 u8 iqCalQCh[AR5416_MAX_CHAINS];
357 u8 pwrDecreaseFor2Chain;
358 u8 pwrDecreaseFor3Chain;
359 u8 txFrameToDataStart;
361 u8 ht40PowerIncForPdadc;
362 u8 bswAtten[AR5416_MAX_CHAINS];
363 u8 bswMargin[AR5416_MAX_CHAINS];
365 u8 xatten2Db[AR5416_MAX_CHAINS];
366 u8 xatten2Margin[AR5416_MAX_CHAINS];
371 u16 xpaBiasLvlFreq[3];
374 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
377 struct calDataPerFreqOpLoop {
384 struct modal_eep_4k_header {
385 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
387 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
389 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
390 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
393 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
398 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
401 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
402 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
404 #ifdef __BIG_ENDIAN_BITFIELD
412 u8 txFrameToDataStart;
414 u8 ht40PowerIncForPdadc;
415 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
416 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
418 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
419 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
420 #ifdef __BIG_ENDIAN_BITFIELD
426 #ifdef __BIG_ENDIAN_BITFIELD
428 u8 antdiv_ctl1:4, ob_4:4;
430 u8 antdiv_ctl2:4, db1_4:4;
432 u8 reserved:4, db2_4:4;
435 u8 ob_4:4, antdiv_ctl1:4;
437 u8 db1_4:4, antdiv_ctl2:4;
439 u8 db2_4:4, reserved:4;
442 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
445 struct base_eep_ar9287_header {
456 u16 blueToothOptions;
461 int8_t pwrTableOffset;
462 int8_t tempSensSlope;
463 int8_t tempSensSlopePalOn;
467 struct modal_eep_ar9287_header {
468 u32 antCtrlChain[AR9287_MAX_CHAINS];
470 int8_t antennaGainCh[AR9287_MAX_CHAINS];
472 u8 txRxAttenCh[AR9287_MAX_CHAINS];
473 u8 rxTxMarginCh[AR9287_MAX_CHAINS];
474 int8_t adcDesiredSize;
479 int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
482 int8_t iqCalICh[AR9287_MAX_CHAINS];
483 int8_t iqCalQCh[AR9287_MAX_CHAINS];
486 u8 txFrameToDataStart;
488 u8 ht40PowerIncForPdadc;
489 u8 bswAtten[AR9287_MAX_CHAINS];
490 u8 bswMargin[AR9287_MAX_CHAINS];
500 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
503 struct cal_data_per_freq {
504 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
505 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
508 struct cal_data_per_freq_4k {
509 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
510 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
513 struct cal_target_power_leg {
518 struct cal_target_power_ht {
523 struct cal_ctl_edges {
528 struct cal_data_op_loop_ar9287 {
535 struct cal_data_per_freq_ar9287 {
536 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
537 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
540 union cal_data_per_freq_ar9287_u {
541 struct cal_data_op_loop_ar9287 calDataOpen;
542 struct cal_data_per_freq_ar9287 calDataClose;
545 struct cal_ctl_data_ar9287 {
547 ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];
550 struct cal_ctl_data {
552 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
555 struct cal_ctl_data_4k {
557 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
560 struct ar5416_eeprom_def {
561 struct base_eep_header baseEepHeader;
563 struct modal_eep_header modalHeader[2];
564 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
565 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
566 struct cal_data_per_freq
567 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
568 struct cal_data_per_freq
569 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
570 struct cal_target_power_leg
571 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
572 struct cal_target_power_ht
573 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
574 struct cal_target_power_ht
575 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
576 struct cal_target_power_leg
577 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
578 struct cal_target_power_leg
579 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
580 struct cal_target_power_ht
581 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
582 struct cal_target_power_ht
583 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
584 u8 ctlIndex[AR5416_NUM_CTLS];
585 struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
589 struct ar5416_eeprom_4k {
590 struct base_eep_header_4k baseEepHeader;
592 struct modal_eep_4k_header modalHeader;
593 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
594 struct cal_data_per_freq_4k
595 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
596 struct cal_target_power_leg
597 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
598 struct cal_target_power_leg
599 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
600 struct cal_target_power_ht
601 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
602 struct cal_target_power_ht
603 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
604 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
605 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
609 struct ar9287_eeprom {
610 struct base_eep_ar9287_header baseEepHeader;
611 u8 custData[AR9287_DATA_SZ];
612 struct modal_eep_ar9287_header modalHeader;
613 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
614 union cal_data_per_freq_ar9287_u
615 calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
616 struct cal_target_power_leg
617 calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
618 struct cal_target_power_leg
619 calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
620 struct cal_target_power_ht
621 calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
622 struct cal_target_power_ht
623 calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
624 u8 ctlIndex[AR9287_NUM_CTLS];
625 struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];
629 enum reg_ext_bitmap {
630 REG_EXT_FCC_MIDBAND = 0,
631 REG_EXT_JAPAN_MIDBAND = 1,
632 REG_EXT_FCC_DFS_HT40 = 2,
633 REG_EXT_JAPAN_NONDFS_HT40 = 3,
634 REG_EXT_JAPAN_DFS_HT40 = 4
637 struct ath9k_country_entry {
647 int (*check_eeprom)(struct ath_hw *hw);
648 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
649 bool (*fill_eeprom)(struct ath_hw *hw);
650 int (*get_eeprom_ver)(struct ath_hw *hw);
651 int (*get_eeprom_rev)(struct ath_hw *hw);
652 void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
653 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
654 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
655 u16 cfgCtl, u8 twiceAntennaReduction,
656 u8 twiceMaxRegulatoryPower, u8 powerLimit,
658 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
661 void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val);
662 void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
664 int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
666 int16_t targetRight);
667 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
668 u16 *indexL, u16 *indexR);
669 bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data);
670 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
671 u8 *pVpdList, u16 numIntercepts,
673 void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
674 struct ath9k_channel *chan,
675 struct cal_target_power_leg *powInfo,
677 struct cal_target_power_leg *pNewPower,
678 u16 numRates, bool isExtTarget);
679 void ath9k_hw_get_target_powers(struct ath_hw *ah,
680 struct ath9k_channel *chan,
681 struct cal_target_power_ht *powInfo,
683 struct cal_target_power_ht *pNewPower,
684 u16 numRates, bool isHt40Target);
685 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
686 bool is2GHz, int num_band_edges);
687 void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
688 int ath9k_hw_eeprom_init(struct ath_hw *ah);
690 void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
691 struct ath9k_channel *chan,
693 u8 *bChans, u16 availPiers,
695 u16 *pPdGainBoundaries, u8 *pPDADCValues,
698 #define ar5416_get_ntxchains(_txchainmask) \
699 (((_txchainmask >> 2) & 1) + \
700 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
702 extern const struct eeprom_ops eep_def_ops;
703 extern const struct eeprom_ops eep_4k_ops;
704 extern const struct eeprom_ops eep_ar9287_ops;
705 extern const struct eeprom_ops eep_ar9287_ops;
706 extern const struct eeprom_ops eep_ar9300_ops;
708 #endif /* EEPROM_H */