drivers/net/wireless/ath/ath9k/ar9002_hw.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/moduleparam.h>
  18 #include "hw.h"
  19 #include "ar5008_initvals.h"
  20 #include "ar9001_initvals.h"
  21 #include "ar9002_initvals.h"
  22 #include "ar9002_phy.h"
  23
  24 /* General hardware code for the A5008/AR9001/AR9002 hadware families */
  25
  26 static int ar9002_hw_init_mode_regs(struct ath_hw *ah)
  27 {
  28         if (AR_SREV_9271(ah)) {
  29                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271);
  30                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271);
  31                 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg);
  32                 return 0;
  33         }
  34
  35         if (ah->config.pcie_clock_req)
  36                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
  37                            ar9280PciePhy_clkreq_off_L1_9280);
  38         else
  39                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
  40                            ar9280PciePhy_clkreq_always_on_L1_9280);
  41 #ifdef CONFIG_PM_SLEEP
  42                 INIT_INI_ARRAY(&ah->iniPcieSerdesWow,
  43                                ar9280PciePhy_awow);
  44 #endif
  45
  46         if (AR_SREV_9287_11_OR_LATER(ah)) {
  47                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1);
  48                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1);
  49         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
  50                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2);
  51                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2);
  52         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
  53                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2);
  54                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2);
  55
  56                 INIT_INI_ARRAY(&ah->iniModesFastClock,
  57                                ar9280Modes_fast_clock_9280_2);
  58         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
  59                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160);
  60                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160);
  61                 if (AR_SREV_9160_11(ah)) {
  62                         INIT_INI_ARRAY(&ah->iniAddac,
  63                                        ar5416Addac_9160_1_1);
  64                 } else {
  65                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160);
  66                 }
  67         } else if (AR_SREV_9100_OR_LATER(ah)) {
  68                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100);
  69                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100);
  70                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100);
  71         } else {
  72                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes);
  73                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common);
  74                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac);
  75         }
  76
  77         if (!AR_SREV_9280_20_OR_LATER(ah)) {
  78                 /* Common for AR5416, AR913x, AR9160 */
  79                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain);
  80
  81                 /* Common for AR913x, AR9160 */
  82                 if (!AR_SREV_5416(ah))
  83                         INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC_9100);
  84                 else
  85                         INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC);
  86         }
  87
  88         /* iniAddac needs to be modified for these chips */
  89         if (AR_SREV_9160(ah) || !AR_SREV_5416_22_OR_LATER(ah)) {
  90                 struct ar5416IniArray *addac = &ah->iniAddac;
  91                 u32 size = sizeof(u32) * addac->ia_rows * addac->ia_columns;
  92                 u32 *data;
  93
  94                 data = devm_kzalloc(ah->dev, size, GFP_KERNEL);
  95                 if (!data)
  96                         return -ENOMEM;
  97
  98                 memcpy(data, addac->ia_array, size);
  99                 addac->ia_array = data;
 100
 101                 if (!AR_SREV_5416_22_OR_LATER(ah)) {
 102                         /* override CLKDRV value */
 103                         INI_RA(addac, 31,1) = 0;
 104                 }
 105         }
 106         if (AR_SREV_9287_11_OR_LATER(ah)) {
 107                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 108                        ar9287Common_normal_cck_fir_coeff_9287_1_1);
 109                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 110                        ar9287Common_japan_2484_cck_fir_coeff_9287_1_1);
 111         }
 112         return 0;
 113 }
 114
 115 static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
 116 {
 117         u32 rxgain_type;
 118
 119         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
 120             AR5416_EEP_MINOR_VER_17) {
 121                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 122
 123                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 124                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 125                                        ar9280Modes_backoff_13db_rxgain_9280_2);
 126                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 127                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 128                                        ar9280Modes_backoff_23db_rxgain_9280_2);
 129                 else
 130                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 131                                        ar9280Modes_original_rxgain_9280_2);
 132         } else {
 133                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 134                                ar9280Modes_original_rxgain_9280_2);
 135         }
 136 }
 137
 138 static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type)
 139 {
 140         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
 141             AR5416_EEP_MINOR_VER_19) {
 142                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 143                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 144                                        ar9280Modes_high_power_tx_gain_9280_2);
 145                 else
 146                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 147                                        ar9280Modes_original_tx_gain_9280_2);
 148         } else {
 149                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 150                                ar9280Modes_original_tx_gain_9280_2);
 151         }
 152 }
 153
 154 static void ar9271_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type)
 155 {
 156         if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 157                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 158                                ar9271Modes_high_power_tx_gain_9271);
 159         else
 160                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 161                                ar9271Modes_normal_power_tx_gain_9271);
 162 }
 163
 164 static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
 165 {
 166         u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 167
 168         if (AR_SREV_9287_11_OR_LATER(ah))
 169                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 170                                ar9287Modes_rx_gain_9287_1_1);
 171         else if (AR_SREV_9280_20(ah))
 172                 ar9280_20_hw_init_rxgain_ini(ah);
 173
 174         if (AR_SREV_9271(ah)) {
 175                 ar9271_hw_init_txgain_ini(ah, txgain_type);
 176         } else if (AR_SREV_9287_11_OR_LATER(ah)) {
 177                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 178                                ar9287Modes_tx_gain_9287_1_1);
 179         } else if (AR_SREV_9280_20(ah)) {
 180                 ar9280_20_hw_init_txgain_ini(ah, txgain_type);
 181         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 182                 /* txgain table */
 183                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 184                         if (AR_SREV_9285E_20(ah)) {
 185                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 186                                                ar9285Modes_XE2_0_high_power);
 187                         } else {
 188                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 189                                         ar9285Modes_high_power_tx_gain_9285_1_2);
 190                         }
 191                 } else {
 192                         if (AR_SREV_9285E_20(ah)) {
 193                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 194                                                ar9285Modes_XE2_0_normal_power);
 195                         } else {
 196                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 197                                         ar9285Modes_original_tx_gain_9285_1_2);
 198                         }
 199                 }
 200         }
 201 }
 202
 203 /*
 204  * Helper for ASPM support.
 205  *
 206  * Disable PLL when in L0s as well as receiver clock when in L1.
 207  * This power saving option must be enabled through the SerDes.
 208  *
 209  * Programming the SerDes must go through the same 288 bit serial shift
 210  * register as the other analog registers.  Hence the 9 writes.
 211  */
 212 static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
 213                                          bool power_off)
 214 {
 215         u8 i;
 216         u32 val;
 217
 218         /* Nothing to do on restore for 11N */
 219         if (!power_off /* !restore */) {
 220                 if (AR_SREV_9280_20_OR_LATER(ah)) {
 221                         /*
 222                          * AR9280 2.0 or later chips use SerDes values from the
 223                          * initvals.h initialized depending on chipset during
 224                          * __ath9k_hw_init()
 225                          */
 226                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
 227                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
 228                                           INI_RA(&ah->iniPcieSerdes, i, 1));
 229                         }
 230                 } else {
 231                         ENABLE_REGWRITE_BUFFER(ah);
 232
 233                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 234                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 235
 236                         /* RX shut off when elecidle is asserted */
 237                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
 238                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
 239                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
 240
 241                         /*
 242                          * Ignore ah->ah_config.pcie_clock_req setting for
 243                          * pre-AR9280 11n
 244                          */
 245                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
 246
 247                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 248                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 249                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
 250
 251                         /* Load the new settings */
 252                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 253
 254                         REGWRITE_BUFFER_FLUSH(ah);
 255                 }
 256
 257                 udelay(1000);
 258         }
 259
 260         if (power_off) {
 261                 /* clear bit 19 to disable L1 */
 262                 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 263
 264                 val = REG_READ(ah, AR_WA);
 265
 266                 /*
 267                  * Set PCIe workaround bits
 268                  * In AR9280 and AR9285, bit 14 in WA register (disable L1)
 269                  * should only  be set when device enters D3 and be
 270                  * cleared when device comes back to D0.
 271                  */
 272                 if (ah->config.pcie_waen) {
 273                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
 274                                 val |= AR_WA_D3_L1_DISABLE;
 275                 } else {
 276                         if (((AR_SREV_9285(ah) ||
 277                               AR_SREV_9271(ah) ||
 278                               AR_SREV_9287(ah)) &&
 279                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
 280                             (AR_SREV_9280(ah) &&
 281                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
 282                                 val |= AR_WA_D3_L1_DISABLE;
 283                         }
 284                 }
 285
 286                 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
 287                         /*
 288                          * Disable bit 6 and 7 before entering D3 to
 289                          * prevent system hang.
 290                          */
 291                         val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
 292                 }
 293
 294                 if (AR_SREV_9280(ah))
 295                         val |= AR_WA_BIT22;
 296
 297                 if (AR_SREV_9285E_20(ah))
 298                         val |= AR_WA_BIT23;
 299
 300                 REG_WRITE(ah, AR_WA, val);
 301         } else {
 302                 if (ah->config.pcie_waen) {
 303                         val = ah->config.pcie_waen;
 304                         if (!power_off)
 305                                 val &= (~AR_WA_D3_L1_DISABLE);
 306                 } else {
 307                         if (AR_SREV_9285(ah) ||
 308                             AR_SREV_9271(ah) ||
 309                             AR_SREV_9287(ah)) {
 310                                 val = AR9285_WA_DEFAULT;
 311                                 if (!power_off)
 312                                         val &= (~AR_WA_D3_L1_DISABLE);
 313                         }
 314                         else if (AR_SREV_9280(ah)) {
 315                                 /*
 316                                  * For AR9280 chips, bit 22 of 0x4004
 317                                  * needs to be set.
 318                                  */
 319                                 val = AR9280_WA_DEFAULT;
 320                                 if (!power_off)
 321                                         val &= (~AR_WA_D3_L1_DISABLE);
 322                         } else {
 323                                 val = AR_WA_DEFAULT;
 324                         }
 325                 }
 326
 327                 /* WAR for ASPM system hang */
 328                 if (AR_SREV_9285(ah) || AR_SREV_9287(ah))
 329                         val |= (AR_WA_BIT6 | AR_WA_BIT7);
 330
 331                 if (AR_SREV_9285E_20(ah))
 332                         val |= AR_WA_BIT23;
 333
 334                 REG_WRITE(ah, AR_WA, val);
 335
 336                 /* set bit 19 to allow forcing of pcie core into L1 state */
 337                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 338         }
 339 }
 340
 341 static int ar9002_hw_get_radiorev(struct ath_hw *ah)
 342 {
 343         u32 val;
 344         int i;
 345
 346         ENABLE_REGWRITE_BUFFER(ah);
 347
 348         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 349         for (i = 0; i < 8; i++)
 350                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 351
 352         REGWRITE_BUFFER_FLUSH(ah);
 353
 354         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 355         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 356
 357         return ath9k_hw_reverse_bits(val, 8);
 358 }
 359
 360 int ar9002_hw_rf_claim(struct ath_hw *ah)
 361 {
 362         u32 val;
 363
 364         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 365
 366         val = ar9002_hw_get_radiorev(ah);
 367         switch (val & AR_RADIO_SREV_MAJOR) {
 368         case 0:
 369                 val = AR_RAD5133_SREV_MAJOR;
 370                 break;
 371         case AR_RAD5133_SREV_MAJOR:
 372         case AR_RAD5122_SREV_MAJOR:
 373         case AR_RAD2133_SREV_MAJOR:
 374         case AR_RAD2122_SREV_MAJOR:
 375                 break;
 376         default:
 377                 ath_err(ath9k_hw_common(ah),
 378                         "Radio Chip Rev 0x%02X not supported\n",
 379                         val & AR_RADIO_SREV_MAJOR);
 380                 return -EOPNOTSUPP;
 381         }
 382
 383         ah->hw_version.analog5GhzRev = val;
 384
 385         return 0;
 386 }
 387
 388 void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
 389 {
 390         if (AR_SREV_9287_13_OR_LATER(ah)) {
 391                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 392                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
 393                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
 394                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 395                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
 396                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 397                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
 398         }
 399 }
 400
 401 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
 402 int ar9002_hw_attach_ops(struct ath_hw *ah)
 403 {
 404         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
 405         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 406         int ret;
 407
 408         ret = ar9002_hw_init_mode_regs(ah);
 409         if (ret)
 410                 return ret;
 411
 412         priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
 413
 414         ops->config_pci_powersave = ar9002_hw_configpcipowersave;
 415
 416         ret = ar5008_hw_attach_phy_ops(ah);
 417         if (ret)
 418                 return ret;
 419
 420         if (AR_SREV_9280_20_OR_LATER(ah))
 421                 ar9002_hw_attach_phy_ops(ah);
 422
 423         ar9002_hw_attach_calib_ops(ah);
 424         ar9002_hw_attach_mac_ops(ah);
 425         return 0;
 426 }
 427
 428 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
 429 {
 430         u32 modesIndex;
 431         int i;
 432
 433         switch (chan->chanmode) {
 434         case CHANNEL_A:
 435         case CHANNEL_A_HT20:
 436                 modesIndex = 1;
 437                 break;
 438         case CHANNEL_A_HT40PLUS:
 439         case CHANNEL_A_HT40MINUS:
 440                 modesIndex = 2;
 441                 break;
 442         case CHANNEL_G:
 443         case CHANNEL_G_HT20:
 444         case CHANNEL_B:
 445                 modesIndex = 4;
 446                 break;
 447         case CHANNEL_G_HT40PLUS:
 448         case CHANNEL_G_HT40MINUS:
 449                 modesIndex = 3;
 450                 break;
 451
 452         default:
 453                 return;
 454         }
 455
 456         ENABLE_REGWRITE_BUFFER(ah);
 457
 458         for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) {
 459                 u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0);
 460                 u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex);
 461                 u32 val_orig;
 462
 463                 if (reg == AR_PHY_CCK_DETECT) {
 464                         val_orig = REG_READ(ah, reg);
 465                         val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
 466                         val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
 467
 468                         REG_WRITE(ah, reg, val|val_orig);
 469                 } else
 470                         REG_WRITE(ah, reg, val);
 471         }
 472
 473         REGWRITE_BUFFER_FLUSH(ah);
 474 }