drivers/net/wireless/ath/ath9k/ar9002_hw.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/moduleparam.h>
  18 #include "hw.h"
  19 #include "ar5008_initvals.h"
  20 #include "ar9001_initvals.h"
  21 #include "ar9002_initvals.h"
  22 #include "ar9002_phy.h"
  23
  24 int modparam_force_new_ani;
  25 module_param_named(force_new_ani, modparam_force_new_ani, int, 0444);
  26 MODULE_PARM_DESC(force_new_ani, "Force new ANI for AR5008, AR9001, AR9002");
  27
  28 /* General hardware code for the A5008/AR9001/AR9002 hadware families */
  29
  30 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
  31 {
  32         if (AR_SREV_9271(ah)) {
  33                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
  34                                ARRAY_SIZE(ar9271Modes_9271), 5);
  35                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
  36                                ARRAY_SIZE(ar9271Common_9271), 2);
  37                 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
  38                                ar9271Common_normal_cck_fir_coeff_9271,
  39                                ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
  40                 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
  41                                ar9271Common_japan_2484_cck_fir_coeff_9271,
  42                                ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
  43                 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
  44                                ar9271Modes_9271_1_0_only,
  45                                ARRAY_SIZE(ar9271Modes_9271_1_0_only), 5);
  46                 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
  47                                ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 5);
  48                 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
  49                                ar9271Modes_high_power_tx_gain_9271,
  50                                ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 5);
  51                 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
  52                                ar9271Modes_normal_power_tx_gain_9271,
  53                                ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 5);
  54                 return;
  55         }
  56
  57         if (AR_SREV_9287_11_OR_LATER(ah)) {
  58                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
  59                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 5);
  60                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
  61                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
  62                 if (ah->config.pcie_clock_req)
  63                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  64                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
  65                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
  66                 else
  67                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  68                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
  69                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
  70                                         2);
  71         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
  72
  73
  74                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
  75                                ARRAY_SIZE(ar9285Modes_9285_1_2), 5);
  76                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
  77                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
  78
  79                 if (ah->config.pcie_clock_req) {
  80                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  81                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
  82                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
  83                 } else {
  84                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  85                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
  86                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
  87                                   2);
  88                 }
  89         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
  90                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
  91                                ARRAY_SIZE(ar9280Modes_9280_2), 5);
  92                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
  93                                ARRAY_SIZE(ar9280Common_9280_2), 2);
  94
  95                 if (ah->config.pcie_clock_req) {
  96                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  97                                ar9280PciePhy_clkreq_off_L1_9280,
  98                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
  99                 } else {
 100                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 101                                ar9280PciePhy_clkreq_always_on_L1_9280,
 102                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 103                 }
 104                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 105                                ar9280Modes_fast_clock_9280_2,
 106                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 107         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 108                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 109                                ARRAY_SIZE(ar5416Modes_9160), 5);
 110                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 111                                ARRAY_SIZE(ar5416Common_9160), 2);
 112                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 113                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 114                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 115                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 116                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 117                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 118                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 119                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 120                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 121                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 122                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 123                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 124                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 125                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 126                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 127                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 128                 if (AR_SREV_9160_11(ah)) {
 129                         INIT_INI_ARRAY(&ah->iniAddac,
 130                                        ar5416Addac_9160_1_1,
 131                                        ARRAY_SIZE(ar5416Addac_9160_1_1), 2);
 132                 } else {
 133                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 134                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 135                 }
 136         } else if (AR_SREV_9100_OR_LATER(ah)) {
 137                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 138                                ARRAY_SIZE(ar5416Modes_9100), 5);
 139                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 140                                ARRAY_SIZE(ar5416Common_9100), 2);
 141                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 142                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 143                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 144                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 145                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 146                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 147                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 148                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 149                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 150                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 151                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 152                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 153                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 154                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 155                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 156                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 157                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 158                                ARRAY_SIZE(ar5416Addac_9100), 2);
 159         } else {
 160                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 161                                ARRAY_SIZE(ar5416Modes), 5);
 162                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 163                                ARRAY_SIZE(ar5416Common), 2);
 164                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 165                                ARRAY_SIZE(ar5416Bank0), 2);
 166                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 167                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 168                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 169                                ARRAY_SIZE(ar5416Bank1), 2);
 170                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 171                                ARRAY_SIZE(ar5416Bank2), 2);
 172                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 173                                ARRAY_SIZE(ar5416Bank3), 3);
 174                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 175                                ARRAY_SIZE(ar5416Bank6), 3);
 176                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 177                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 178                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 179                                ARRAY_SIZE(ar5416Bank7), 2);
 180                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 181                                ARRAY_SIZE(ar5416Addac), 2);
 182         }
 183 }
 184
 185 /* Support for Japan ch.14 (2484) spread */
 186 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
 187 {
 188         if (AR_SREV_9287_11_OR_LATER(ah)) {
 189                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 190                        ar9287Common_normal_cck_fir_coeff_9287_1_1,
 191                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_9287_1_1),
 192                        2);
 193                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 194                        ar9287Common_japan_2484_cck_fir_coeff_9287_1_1,
 195                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1),
 196                        2);
 197         }
 198 }
 199
 200 static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
 201 {
 202         u32 rxgain_type;
 203
 204         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
 205             AR5416_EEP_MINOR_VER_17) {
 206                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 207
 208                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 209                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 210                         ar9280Modes_backoff_13db_rxgain_9280_2,
 211                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 5);
 212                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 213                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 214                         ar9280Modes_backoff_23db_rxgain_9280_2,
 215                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 5);
 216                 else
 217                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 218                         ar9280Modes_original_rxgain_9280_2,
 219                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
 220         } else {
 221                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 222                         ar9280Modes_original_rxgain_9280_2,
 223                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
 224         }
 225 }
 226
 227 static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah)
 228 {
 229         u32 txgain_type;
 230
 231         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
 232             AR5416_EEP_MINOR_VER_19) {
 233                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 234
 235                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 236                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 237                         ar9280Modes_high_power_tx_gain_9280_2,
 238                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 5);
 239                 else
 240                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 241                         ar9280Modes_original_tx_gain_9280_2,
 242                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
 243         } else {
 244                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 245                 ar9280Modes_original_tx_gain_9280_2,
 246                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
 247         }
 248 }
 249
 250 static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
 251 {
 252         if (AR_SREV_9287_11_OR_LATER(ah))
 253                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 254                 ar9287Modes_rx_gain_9287_1_1,
 255                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 5);
 256         else if (AR_SREV_9280_20(ah))
 257                 ar9280_20_hw_init_rxgain_ini(ah);
 258
 259         if (AR_SREV_9287_11_OR_LATER(ah)) {
 260                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 261                 ar9287Modes_tx_gain_9287_1_1,
 262                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 5);
 263         } else if (AR_SREV_9280_20(ah)) {
 264                 ar9280_20_hw_init_txgain_ini(ah);
 265         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 266                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 267
 268                 /* txgain table */
 269                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 270                         if (AR_SREV_9285E_20(ah)) {
 271                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 272                                 ar9285Modes_XE2_0_high_power,
 273                                 ARRAY_SIZE(
 274                                   ar9285Modes_XE2_0_high_power), 5);
 275                         } else {
 276                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 277                                 ar9285Modes_high_power_tx_gain_9285_1_2,
 278                                 ARRAY_SIZE(
 279                                   ar9285Modes_high_power_tx_gain_9285_1_2), 5);
 280                         }
 281                 } else {
 282                         if (AR_SREV_9285E_20(ah)) {
 283                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 284                                 ar9285Modes_XE2_0_normal_power,
 285                                 ARRAY_SIZE(
 286                                   ar9285Modes_XE2_0_normal_power), 5);
 287                         } else {
 288                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 289                                 ar9285Modes_original_tx_gain_9285_1_2,
 290                                 ARRAY_SIZE(
 291                                   ar9285Modes_original_tx_gain_9285_1_2), 5);
 292                         }
 293                 }
 294         }
 295 }
 296
 297 /*
 298  * Helper for ASPM support.
 299  *
 300  * Disable PLL when in L0s as well as receiver clock when in L1.
 301  * This power saving option must be enabled through the SerDes.
 302  *
 303  * Programming the SerDes must go through the same 288 bit serial shift
 304  * register as the other analog registers.  Hence the 9 writes.
 305  */
 306 static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
 307                                          bool power_off)
 308 {
 309         u8 i;
 310         u32 val;
 311
 312         /* Nothing to do on restore for 11N */
 313         if (!power_off /* !restore */) {
 314                 if (AR_SREV_9280_20_OR_LATER(ah)) {
 315                         /*
 316                          * AR9280 2.0 or later chips use SerDes values from the
 317                          * initvals.h initialized depending on chipset during
 318                          * __ath9k_hw_init()
 319                          */
 320                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
 321                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
 322                                           INI_RA(&ah->iniPcieSerdes, i, 1));
 323                         }
 324                 } else {
 325                         ENABLE_REGWRITE_BUFFER(ah);
 326
 327                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 328                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 329
 330                         /* RX shut off when elecidle is asserted */
 331                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
 332                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
 333                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
 334
 335                         /*
 336                          * Ignore ah->ah_config.pcie_clock_req setting for
 337                          * pre-AR9280 11n
 338                          */
 339                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
 340
 341                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 342                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 343                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
 344
 345                         /* Load the new settings */
 346                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 347
 348                         REGWRITE_BUFFER_FLUSH(ah);
 349                 }
 350
 351                 udelay(1000);
 352         }
 353
 354         if (power_off) {
 355                 /* clear bit 19 to disable L1 */
 356                 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 357
 358                 val = REG_READ(ah, AR_WA);
 359
 360                 /*
 361                  * Set PCIe workaround bits
 362                  * In AR9280 and AR9285, bit 14 in WA register (disable L1)
 363                  * should only  be set when device enters D3 and be
 364                  * cleared when device comes back to D0.
 365                  */
 366                 if (ah->config.pcie_waen) {
 367                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
 368                                 val |= AR_WA_D3_L1_DISABLE;
 369                 } else {
 370                         if (((AR_SREV_9285(ah) ||
 371                               AR_SREV_9271(ah) ||
 372                               AR_SREV_9287(ah)) &&
 373                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
 374                             (AR_SREV_9280(ah) &&
 375                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
 376                                 val |= AR_WA_D3_L1_DISABLE;
 377                         }
 378                 }
 379
 380                 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
 381                         /*
 382                          * Disable bit 6 and 7 before entering D3 to
 383                          * prevent system hang.
 384                          */
 385                         val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
 386                 }
 387
 388                 if (AR_SREV_9280(ah))
 389                         val |= AR_WA_BIT22;
 390
 391                 if (AR_SREV_9285E_20(ah))
 392                         val |= AR_WA_BIT23;
 393
 394                 REG_WRITE(ah, AR_WA, val);
 395         } else {
 396                 if (ah->config.pcie_waen) {
 397                         val = ah->config.pcie_waen;
 398                         if (!power_off)
 399                                 val &= (~AR_WA_D3_L1_DISABLE);
 400                 } else {
 401                         if (AR_SREV_9285(ah) ||
 402                             AR_SREV_9271(ah) ||
 403                             AR_SREV_9287(ah)) {
 404                                 val = AR9285_WA_DEFAULT;
 405                                 if (!power_off)
 406                                         val &= (~AR_WA_D3_L1_DISABLE);
 407                         }
 408                         else if (AR_SREV_9280(ah)) {
 409                                 /*
 410                                  * For AR9280 chips, bit 22 of 0x4004
 411                                  * needs to be set.
 412                                  */
 413                                 val = AR9280_WA_DEFAULT;
 414                                 if (!power_off)
 415                                         val &= (~AR_WA_D3_L1_DISABLE);
 416                         } else {
 417                                 val = AR_WA_DEFAULT;
 418                         }
 419                 }
 420
 421                 /* WAR for ASPM system hang */
 422                 if (AR_SREV_9285(ah) || AR_SREV_9287(ah))
 423                         val |= (AR_WA_BIT6 | AR_WA_BIT7);
 424
 425                 if (AR_SREV_9285E_20(ah))
 426                         val |= AR_WA_BIT23;
 427
 428                 REG_WRITE(ah, AR_WA, val);
 429
 430                 /* set bit 19 to allow forcing of pcie core into L1 state */
 431                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 432         }
 433 }
 434
 435 static int ar9002_hw_get_radiorev(struct ath_hw *ah)
 436 {
 437         u32 val;
 438         int i;
 439
 440         ENABLE_REGWRITE_BUFFER(ah);
 441
 442         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 443         for (i = 0; i < 8; i++)
 444                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 445
 446         REGWRITE_BUFFER_FLUSH(ah);
 447
 448         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 449         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 450
 451         return ath9k_hw_reverse_bits(val, 8);
 452 }
 453
 454 int ar9002_hw_rf_claim(struct ath_hw *ah)
 455 {
 456         u32 val;
 457
 458         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 459
 460         val = ar9002_hw_get_radiorev(ah);
 461         switch (val & AR_RADIO_SREV_MAJOR) {
 462         case 0:
 463                 val = AR_RAD5133_SREV_MAJOR;
 464                 break;
 465         case AR_RAD5133_SREV_MAJOR:
 466         case AR_RAD5122_SREV_MAJOR:
 467         case AR_RAD2133_SREV_MAJOR:
 468         case AR_RAD2122_SREV_MAJOR:
 469                 break;
 470         default:
 471                 ath_err(ath9k_hw_common(ah),
 472                         "Radio Chip Rev 0x%02X not supported\n",
 473                         val & AR_RADIO_SREV_MAJOR);
 474                 return -EOPNOTSUPP;
 475         }
 476
 477         ah->hw_version.analog5GhzRev = val;
 478
 479         return 0;
 480 }
 481
 482 void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
 483 {
 484         if (AR_SREV_9287_13_OR_LATER(ah)) {
 485                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 486                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
 487                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
 488                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 489                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
 490                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 491                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
 492         }
 493 }
 494
 495 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
 496 void ar9002_hw_attach_ops(struct ath_hw *ah)
 497 {
 498         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
 499         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 500
 501         priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
 502         priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
 503
 504         ops->config_pci_powersave = ar9002_hw_configpcipowersave;
 505
 506         ar5008_hw_attach_phy_ops(ah);
 507         if (AR_SREV_9280_20_OR_LATER(ah))
 508                 ar9002_hw_attach_phy_ops(ah);
 509
 510         ar9002_hw_attach_calib_ops(ah);
 511         ar9002_hw_attach_mac_ops(ah);
 512 }
 513
 514 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
 515 {
 516         u32 modesIndex;
 517         int i;
 518
 519         switch (chan->chanmode) {
 520         case CHANNEL_A:
 521         case CHANNEL_A_HT20:
 522                 modesIndex = 1;
 523                 break;
 524         case CHANNEL_A_HT40PLUS:
 525         case CHANNEL_A_HT40MINUS:
 526                 modesIndex = 2;
 527                 break;
 528         case CHANNEL_G:
 529         case CHANNEL_G_HT20:
 530         case CHANNEL_B:
 531                 modesIndex = 4;
 532                 break;
 533         case CHANNEL_G_HT40PLUS:
 534         case CHANNEL_G_HT40MINUS:
 535                 modesIndex = 3;
 536                 break;
 537
 538         default:
 539                 return;
 540         }
 541
 542         ENABLE_REGWRITE_BUFFER(ah);
 543
 544         for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) {
 545                 u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0);
 546                 u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex);
 547                 u32 val_orig;
 548
 549                 if (reg == AR_PHY_CCK_DETECT) {
 550                         val_orig = REG_READ(ah, reg);
 551                         val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
 552                         val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
 553
 554                         REG_WRITE(ah, reg, val|val_orig);
 555                 } else
 556                         REG_WRITE(ah, reg, val);
 557         }
 558
 559         REGWRITE_BUFFER_FLUSH(ah);
 560 }