1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/of_device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/of_address.h>
13 #include <linux/iommu.h>
17 #include <linux/remoteproc.h>
19 #include <linux/soc/qcom/smem.h>
20 #include <linux/soc/qcom/smem_state.h>
22 static const struct of_device_id ath11k_ahb_of_match[] = {
23 /* TODO: Should we change the compatible string to something similar
24 * to one that ath10k uses?
26 { .compatible = "qcom,ipq8074-wifi",
27 .data = (void *)ATH11K_HW_IPQ8074,
29 { .compatible = "qcom,ipq6018-wifi",
30 .data = (void *)ATH11K_HW_IPQ6018_HW10,
32 { .compatible = "qcom,wcn6750-wifi",
33 .data = (void *)ATH11K_HW_WCN6750_HW10,
35 { .compatible = "qcom,ipq5018-wifi",
36 .data = (void *)ATH11K_HW_IPQ5018_HW10,
41 MODULE_DEVICE_TABLE(of, ath11k_ahb_of_match);
43 #define ATH11K_IRQ_CE0_OFFSET 4
45 static const char *irq_name[ATH11K_IRQ_NUM_MAX] = {
63 "host2reo-re-injection",
65 "host2rxdma-monitor-ring3",
66 "host2rxdma-monitor-ring2",
67 "host2rxdma-monitor-ring1",
69 "wbm2host-rx-release",
71 "reo2host-destination-ring4",
72 "reo2host-destination-ring3",
73 "reo2host-destination-ring2",
74 "reo2host-destination-ring1",
75 "rxdma2host-monitor-destination-mac3",
76 "rxdma2host-monitor-destination-mac2",
77 "rxdma2host-monitor-destination-mac1",
78 "ppdu-end-interrupts-mac3",
79 "ppdu-end-interrupts-mac2",
80 "ppdu-end-interrupts-mac1",
81 "rxdma2host-monitor-status-ring-mac3",
82 "rxdma2host-monitor-status-ring-mac2",
83 "rxdma2host-monitor-status-ring-mac1",
84 "host2rxdma-host-buf-ring-mac3",
85 "host2rxdma-host-buf-ring-mac2",
86 "host2rxdma-host-buf-ring-mac1",
87 "rxdma2host-destination-ring-mac3",
88 "rxdma2host-destination-ring-mac2",
89 "rxdma2host-destination-ring-mac1",
90 "host2tcl-input-ring4",
91 "host2tcl-input-ring3",
92 "host2tcl-input-ring2",
93 "host2tcl-input-ring1",
94 "wbm2host-tx-completions-ring3",
95 "wbm2host-tx-completions-ring2",
96 "wbm2host-tx-completions-ring1",
97 "tcl2host-status-ring",
100 /* enum ext_irq_num - irq numbers that can be used by external modules
104 host2wbm_desc_feed = 16,
105 host2reo_re_injection,
107 host2rxdma_monitor_ring3,
108 host2rxdma_monitor_ring2,
109 host2rxdma_monitor_ring1,
113 reo2host_destination_ring4,
114 reo2host_destination_ring3,
115 reo2host_destination_ring2,
116 reo2host_destination_ring1,
117 rxdma2host_monitor_destination_mac3,
118 rxdma2host_monitor_destination_mac2,
119 rxdma2host_monitor_destination_mac1,
120 ppdu_end_interrupts_mac3,
121 ppdu_end_interrupts_mac2,
122 ppdu_end_interrupts_mac1,
123 rxdma2host_monitor_status_ring_mac3,
124 rxdma2host_monitor_status_ring_mac2,
125 rxdma2host_monitor_status_ring_mac1,
126 host2rxdma_host_buf_ring_mac3,
127 host2rxdma_host_buf_ring_mac2,
128 host2rxdma_host_buf_ring_mac1,
129 rxdma2host_destination_ring_mac3,
130 rxdma2host_destination_ring_mac2,
131 rxdma2host_destination_ring_mac1,
132 host2tcl_input_ring4,
133 host2tcl_input_ring3,
134 host2tcl_input_ring2,
135 host2tcl_input_ring1,
136 wbm2host_tx_completions_ring3,
137 wbm2host_tx_completions_ring2,
138 wbm2host_tx_completions_ring1,
139 tcl2host_status_ring,
143 ath11k_ahb_get_msi_irq_wcn6750(struct ath11k_base *ab, unsigned int vector)
145 return ab->pci.msi.irqs[vector];
149 ath11k_ahb_get_window_start_wcn6750(struct ath11k_base *ab, u32 offset)
151 u32 window_start = 0;
153 /* If offset lies within DP register range, use 1st window */
154 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
155 window_start = ATH11K_PCI_WINDOW_START;
156 /* If offset lies within CE register range, use 2nd window */
157 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) <
158 ATH11K_PCI_WINDOW_RANGE_MASK)
159 window_start = 2 * ATH11K_PCI_WINDOW_START;
165 ath11k_ahb_window_write32_wcn6750(struct ath11k_base *ab, u32 offset, u32 value)
169 /* WCN6750 uses static window based register access*/
170 window_start = ath11k_ahb_get_window_start_wcn6750(ab, offset);
172 iowrite32(value, ab->mem + window_start +
173 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
176 static u32 ath11k_ahb_window_read32_wcn6750(struct ath11k_base *ab, u32 offset)
181 /* WCN6750 uses static window based register access */
182 window_start = ath11k_ahb_get_window_start_wcn6750(ab, offset);
184 val = ioread32(ab->mem + window_start +
185 (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
189 static const struct ath11k_pci_ops ath11k_ahb_pci_ops_wcn6750 = {
192 .get_msi_irq = ath11k_ahb_get_msi_irq_wcn6750,
193 .window_write32 = ath11k_ahb_window_write32_wcn6750,
194 .window_read32 = ath11k_ahb_window_read32_wcn6750,
197 static inline u32 ath11k_ahb_read32(struct ath11k_base *ab, u32 offset)
199 return ioread32(ab->mem + offset);
202 static inline void ath11k_ahb_write32(struct ath11k_base *ab, u32 offset, u32 value)
204 iowrite32(value, ab->mem + offset);
207 static void ath11k_ahb_kill_tasklets(struct ath11k_base *ab)
211 for (i = 0; i < ab->hw_params.ce_count; i++) {
212 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
214 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
217 tasklet_kill(&ce_pipe->intr_tq);
221 static void ath11k_ahb_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp)
225 for (i = 0; i < irq_grp->num_irq; i++)
226 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
229 static void __ath11k_ahb_ext_irq_disable(struct ath11k_base *ab)
233 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
234 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
236 ath11k_ahb_ext_grp_disable(irq_grp);
238 if (irq_grp->napi_enabled) {
239 napi_synchronize(&irq_grp->napi);
240 napi_disable(&irq_grp->napi);
241 irq_grp->napi_enabled = false;
246 static void ath11k_ahb_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp)
250 for (i = 0; i < irq_grp->num_irq; i++)
251 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
254 static void ath11k_ahb_setbit32(struct ath11k_base *ab, u8 bit, u32 offset)
258 val = ath11k_ahb_read32(ab, offset);
259 ath11k_ahb_write32(ab, offset, val | BIT(bit));
262 static void ath11k_ahb_clearbit32(struct ath11k_base *ab, u8 bit, u32 offset)
266 val = ath11k_ahb_read32(ab, offset);
267 ath11k_ahb_write32(ab, offset, val & ~BIT(bit));
270 static void ath11k_ahb_ce_irq_enable(struct ath11k_base *ab, u16 ce_id)
272 const struct ce_attr *ce_attr;
273 const struct ce_ie_addr *ce_ie_addr = ab->hw_params.ce_ie_addr;
274 u32 ie1_reg_addr, ie2_reg_addr, ie3_reg_addr;
276 ie1_reg_addr = ce_ie_addr->ie1_reg_addr + ATH11K_CE_OFFSET(ab);
277 ie2_reg_addr = ce_ie_addr->ie2_reg_addr + ATH11K_CE_OFFSET(ab);
278 ie3_reg_addr = ce_ie_addr->ie3_reg_addr + ATH11K_CE_OFFSET(ab);
280 ce_attr = &ab->hw_params.host_ce_config[ce_id];
281 if (ce_attr->src_nentries)
282 ath11k_ahb_setbit32(ab, ce_id, ie1_reg_addr);
284 if (ce_attr->dest_nentries) {
285 ath11k_ahb_setbit32(ab, ce_id, ie2_reg_addr);
286 ath11k_ahb_setbit32(ab, ce_id + CE_HOST_IE_3_SHIFT,
291 static void ath11k_ahb_ce_irq_disable(struct ath11k_base *ab, u16 ce_id)
293 const struct ce_attr *ce_attr;
294 const struct ce_ie_addr *ce_ie_addr = ab->hw_params.ce_ie_addr;
295 u32 ie1_reg_addr, ie2_reg_addr, ie3_reg_addr;
297 ie1_reg_addr = ce_ie_addr->ie1_reg_addr + ATH11K_CE_OFFSET(ab);
298 ie2_reg_addr = ce_ie_addr->ie2_reg_addr + ATH11K_CE_OFFSET(ab);
299 ie3_reg_addr = ce_ie_addr->ie3_reg_addr + ATH11K_CE_OFFSET(ab);
301 ce_attr = &ab->hw_params.host_ce_config[ce_id];
302 if (ce_attr->src_nentries)
303 ath11k_ahb_clearbit32(ab, ce_id, ie1_reg_addr);
305 if (ce_attr->dest_nentries) {
306 ath11k_ahb_clearbit32(ab, ce_id, ie2_reg_addr);
307 ath11k_ahb_clearbit32(ab, ce_id + CE_HOST_IE_3_SHIFT,
312 static void ath11k_ahb_sync_ce_irqs(struct ath11k_base *ab)
317 for (i = 0; i < ab->hw_params.ce_count; i++) {
318 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
321 irq_idx = ATH11K_IRQ_CE0_OFFSET + i;
322 synchronize_irq(ab->irq_num[irq_idx]);
326 static void ath11k_ahb_sync_ext_irqs(struct ath11k_base *ab)
331 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
332 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
334 for (j = 0; j < irq_grp->num_irq; j++) {
335 irq_idx = irq_grp->irqs[j];
336 synchronize_irq(ab->irq_num[irq_idx]);
341 static void ath11k_ahb_ce_irqs_enable(struct ath11k_base *ab)
345 for (i = 0; i < ab->hw_params.ce_count; i++) {
346 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
348 ath11k_ahb_ce_irq_enable(ab, i);
352 static void ath11k_ahb_ce_irqs_disable(struct ath11k_base *ab)
356 for (i = 0; i < ab->hw_params.ce_count; i++) {
357 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
359 ath11k_ahb_ce_irq_disable(ab, i);
363 static int ath11k_ahb_start(struct ath11k_base *ab)
365 ath11k_ahb_ce_irqs_enable(ab);
366 ath11k_ce_rx_post_buf(ab);
371 static void ath11k_ahb_ext_irq_enable(struct ath11k_base *ab)
375 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
376 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
378 if (!irq_grp->napi_enabled) {
379 napi_enable(&irq_grp->napi);
380 irq_grp->napi_enabled = true;
382 ath11k_ahb_ext_grp_enable(irq_grp);
386 static void ath11k_ahb_ext_irq_disable(struct ath11k_base *ab)
388 __ath11k_ahb_ext_irq_disable(ab);
389 ath11k_ahb_sync_ext_irqs(ab);
392 static void ath11k_ahb_stop(struct ath11k_base *ab)
394 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
395 ath11k_ahb_ce_irqs_disable(ab);
396 ath11k_ahb_sync_ce_irqs(ab);
397 ath11k_ahb_kill_tasklets(ab);
398 del_timer_sync(&ab->rx_replenish_retry);
399 ath11k_ce_cleanup_pipes(ab);
402 static int ath11k_ahb_power_up(struct ath11k_base *ab)
404 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
407 ret = rproc_boot(ab_ahb->tgt_rproc);
409 ath11k_err(ab, "failed to boot the remote processor Q6\n");
414 static void ath11k_ahb_power_down(struct ath11k_base *ab)
416 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
418 rproc_shutdown(ab_ahb->tgt_rproc);
421 static int ath11k_ahb_fwreset_from_cold_boot(struct ath11k_base *ab)
425 if (ath11k_cold_boot_cal == 0 || ab->qmi.cal_done ||
426 ab->hw_params.cold_boot_calib == 0 ||
427 ab->hw_params.cbcal_restart_fw == 0)
430 ath11k_dbg(ab, ATH11K_DBG_AHB, "wait for cold boot done\n");
431 timeout = wait_event_timeout(ab->qmi.cold_boot_waitq,
432 (ab->qmi.cal_done == 1),
433 ATH11K_COLD_BOOT_FW_RESET_DELAY);
435 ath11k_cold_boot_cal = 0;
436 ath11k_warn(ab, "Coldboot Calibration failed timed out\n");
439 /* reset the firmware */
440 ath11k_ahb_power_down(ab);
441 ath11k_ahb_power_up(ab);
443 ath11k_dbg(ab, ATH11K_DBG_AHB, "exited from cold boot mode\n");
447 static void ath11k_ahb_init_qmi_ce_config(struct ath11k_base *ab)
449 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
451 cfg->tgt_ce_len = ab->hw_params.target_ce_count;
452 cfg->tgt_ce = ab->hw_params.target_ce_config;
453 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len;
454 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map;
455 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id;
458 static void ath11k_ahb_free_ext_irq(struct ath11k_base *ab)
462 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
463 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
465 for (j = 0; j < irq_grp->num_irq; j++)
466 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);
468 netif_napi_del(&irq_grp->napi);
472 static void ath11k_ahb_free_irq(struct ath11k_base *ab)
477 if (ab->hw_params.hybrid_bus_type)
478 return ath11k_pcic_free_irq(ab);
480 for (i = 0; i < ab->hw_params.ce_count; i++) {
481 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
483 irq_idx = ATH11K_IRQ_CE0_OFFSET + i;
484 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
487 ath11k_ahb_free_ext_irq(ab);
490 static void ath11k_ahb_ce_tasklet(struct tasklet_struct *t)
492 struct ath11k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq);
494 ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);
496 ath11k_ahb_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num);
499 static irqreturn_t ath11k_ahb_ce_interrupt_handler(int irq, void *arg)
501 struct ath11k_ce_pipe *ce_pipe = arg;
503 /* last interrupt received for this CE */
504 ce_pipe->timestamp = jiffies;
506 ath11k_ahb_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num);
508 tasklet_schedule(&ce_pipe->intr_tq);
513 static int ath11k_ahb_ext_grp_napi_poll(struct napi_struct *napi, int budget)
515 struct ath11k_ext_irq_grp *irq_grp = container_of(napi,
516 struct ath11k_ext_irq_grp,
518 struct ath11k_base *ab = irq_grp->ab;
521 work_done = ath11k_dp_service_srng(ab, irq_grp, budget);
522 if (work_done < budget) {
523 napi_complete_done(napi, work_done);
524 ath11k_ahb_ext_grp_enable(irq_grp);
527 if (work_done > budget)
533 static irqreturn_t ath11k_ahb_ext_interrupt_handler(int irq, void *arg)
535 struct ath11k_ext_irq_grp *irq_grp = arg;
537 /* last interrupt received for this group */
538 irq_grp->timestamp = jiffies;
540 ath11k_ahb_ext_grp_disable(irq_grp);
542 napi_schedule(&irq_grp->napi);
547 static int ath11k_ahb_config_ext_irq(struct ath11k_base *ab)
549 struct ath11k_hw_params *hw = &ab->hw_params;
554 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
555 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
560 init_dummy_netdev(&irq_grp->napi_ndev);
561 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
562 ath11k_ahb_ext_grp_napi_poll);
564 for (j = 0; j < ATH11K_EXT_IRQ_NUM_MAX; j++) {
565 if (ab->hw_params.ring_mask->tx[i] & BIT(j)) {
566 irq_grp->irqs[num_irq++] =
567 wbm2host_tx_completions_ring1 - j;
570 if (ab->hw_params.ring_mask->rx[i] & BIT(j)) {
571 irq_grp->irqs[num_irq++] =
572 reo2host_destination_ring1 - j;
575 if (ab->hw_params.ring_mask->rx_err[i] & BIT(j))
576 irq_grp->irqs[num_irq++] = reo2host_exception;
578 if (ab->hw_params.ring_mask->rx_wbm_rel[i] & BIT(j))
579 irq_grp->irqs[num_irq++] = wbm2host_rx_release;
581 if (ab->hw_params.ring_mask->reo_status[i] & BIT(j))
582 irq_grp->irqs[num_irq++] = reo2host_status;
584 if (j < ab->hw_params.max_radios) {
585 if (ab->hw_params.ring_mask->rxdma2host[i] & BIT(j)) {
586 irq_grp->irqs[num_irq++] =
587 rxdma2host_destination_ring_mac1 -
588 ath11k_hw_get_mac_from_pdev_id(hw, j);
591 if (ab->hw_params.ring_mask->host2rxdma[i] & BIT(j)) {
592 irq_grp->irqs[num_irq++] =
593 host2rxdma_host_buf_ring_mac1 -
594 ath11k_hw_get_mac_from_pdev_id(hw, j);
597 if (ab->hw_params.ring_mask->rx_mon_status[i] & BIT(j)) {
598 irq_grp->irqs[num_irq++] =
599 ppdu_end_interrupts_mac1 -
600 ath11k_hw_get_mac_from_pdev_id(hw, j);
601 irq_grp->irqs[num_irq++] =
602 rxdma2host_monitor_status_ring_mac1 -
603 ath11k_hw_get_mac_from_pdev_id(hw, j);
607 irq_grp->num_irq = num_irq;
609 for (j = 0; j < irq_grp->num_irq; j++) {
610 int irq_idx = irq_grp->irqs[j];
612 irq = platform_get_irq_byname(ab->pdev,
614 ab->irq_num[irq_idx] = irq;
615 irq_set_status_flags(irq, IRQ_NOAUTOEN | IRQ_DISABLE_UNLAZY);
616 ret = request_irq(irq, ath11k_ahb_ext_interrupt_handler,
618 irq_name[irq_idx], irq_grp);
620 ath11k_err(ab, "failed request_irq for %d\n",
629 static int ath11k_ahb_config_irq(struct ath11k_base *ab)
634 if (ab->hw_params.hybrid_bus_type)
635 return ath11k_pcic_config_irq(ab);
637 /* Configure CE irqs */
638 for (i = 0; i < ab->hw_params.ce_count; i++) {
639 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
641 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
644 irq_idx = ATH11K_IRQ_CE0_OFFSET + i;
646 tasklet_setup(&ce_pipe->intr_tq, ath11k_ahb_ce_tasklet);
647 irq = platform_get_irq_byname(ab->pdev, irq_name[irq_idx]);
648 ret = request_irq(irq, ath11k_ahb_ce_interrupt_handler,
649 IRQF_TRIGGER_RISING, irq_name[irq_idx],
654 ab->irq_num[irq_idx] = irq;
657 /* Configure external interrupts */
658 ret = ath11k_ahb_config_ext_irq(ab);
663 static int ath11k_ahb_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
664 u8 *ul_pipe, u8 *dl_pipe)
666 const struct service_to_pipe *entry;
667 bool ul_set = false, dl_set = false;
670 for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) {
671 entry = &ab->hw_params.svc_to_ce_map[i];
673 if (__le32_to_cpu(entry->service_id) != service_id)
676 switch (__le32_to_cpu(entry->pipedir)) {
681 *dl_pipe = __le32_to_cpu(entry->pipenum);
686 *ul_pipe = __le32_to_cpu(entry->pipenum);
692 *dl_pipe = __le32_to_cpu(entry->pipenum);
693 *ul_pipe = __le32_to_cpu(entry->pipenum);
700 if (WARN_ON(!ul_set || !dl_set))
706 static int ath11k_ahb_hif_suspend(struct ath11k_base *ab)
708 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
713 if (!device_may_wakeup(ab->dev))
716 wake_irq = ab->irq_num[ATH11K_PCI_IRQ_CE0_OFFSET + ATH11K_PCI_CE_WAKE_IRQ];
718 ret = enable_irq_wake(wake_irq);
720 ath11k_err(ab, "failed to enable wakeup irq :%d\n", ret);
724 value = u32_encode_bits(ab_ahb->smp2p_info.seq_no++,
725 ATH11K_AHB_SMP2P_SMEM_SEQ_NO);
726 value |= u32_encode_bits(ATH11K_AHB_POWER_SAVE_ENTER,
727 ATH11K_AHB_SMP2P_SMEM_MSG);
729 ret = qcom_smem_state_update_bits(ab_ahb->smp2p_info.smem_state,
730 ATH11K_AHB_SMP2P_SMEM_VALUE_MASK, value);
732 ath11k_err(ab, "failed to send smp2p power save enter cmd :%d\n", ret);
736 ath11k_dbg(ab, ATH11K_DBG_AHB, "device suspended\n");
741 static int ath11k_ahb_hif_resume(struct ath11k_base *ab)
743 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
748 if (!device_may_wakeup(ab->dev))
751 wake_irq = ab->irq_num[ATH11K_PCI_IRQ_CE0_OFFSET + ATH11K_PCI_CE_WAKE_IRQ];
753 ret = disable_irq_wake(wake_irq);
755 ath11k_err(ab, "failed to disable wakeup irq: %d\n", ret);
759 reinit_completion(&ab->wow.wakeup_completed);
761 value = u32_encode_bits(ab_ahb->smp2p_info.seq_no++,
762 ATH11K_AHB_SMP2P_SMEM_SEQ_NO);
763 value |= u32_encode_bits(ATH11K_AHB_POWER_SAVE_EXIT,
764 ATH11K_AHB_SMP2P_SMEM_MSG);
766 ret = qcom_smem_state_update_bits(ab_ahb->smp2p_info.smem_state,
767 ATH11K_AHB_SMP2P_SMEM_VALUE_MASK, value);
769 ath11k_err(ab, "failed to send smp2p power save enter cmd :%d\n", ret);
773 ret = wait_for_completion_timeout(&ab->wow.wakeup_completed, 3 * HZ);
775 ath11k_warn(ab, "timed out while waiting for wow wakeup completion\n");
779 ath11k_dbg(ab, ATH11K_DBG_AHB, "device resumed\n");
784 static const struct ath11k_hif_ops ath11k_ahb_hif_ops_ipq8074 = {
785 .start = ath11k_ahb_start,
786 .stop = ath11k_ahb_stop,
787 .read32 = ath11k_ahb_read32,
788 .write32 = ath11k_ahb_write32,
790 .irq_enable = ath11k_ahb_ext_irq_enable,
791 .irq_disable = ath11k_ahb_ext_irq_disable,
792 .map_service_to_pipe = ath11k_ahb_map_service_to_pipe,
793 .power_down = ath11k_ahb_power_down,
794 .power_up = ath11k_ahb_power_up,
797 static const struct ath11k_hif_ops ath11k_ahb_hif_ops_wcn6750 = {
798 .start = ath11k_pcic_start,
799 .stop = ath11k_pcic_stop,
800 .read32 = ath11k_pcic_read32,
801 .write32 = ath11k_pcic_write32,
803 .irq_enable = ath11k_pcic_ext_irq_enable,
804 .irq_disable = ath11k_pcic_ext_irq_disable,
805 .get_msi_address = ath11k_pcic_get_msi_address,
806 .get_user_msi_vector = ath11k_pcic_get_user_msi_assignment,
807 .map_service_to_pipe = ath11k_pcic_map_service_to_pipe,
808 .power_down = ath11k_ahb_power_down,
809 .power_up = ath11k_ahb_power_up,
810 .suspend = ath11k_ahb_hif_suspend,
811 .resume = ath11k_ahb_hif_resume,
812 .ce_irq_enable = ath11k_pci_enable_ce_irqs_except_wake_irq,
813 .ce_irq_disable = ath11k_pci_disable_ce_irqs_except_wake_irq,
816 static int ath11k_core_get_rproc(struct ath11k_base *ab)
818 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
819 struct device *dev = ab->dev;
820 struct rproc *prproc;
821 phandle rproc_phandle;
823 if (of_property_read_u32(dev->of_node, "qcom,rproc", &rproc_phandle)) {
824 ath11k_err(ab, "failed to get q6_rproc handle\n");
828 prproc = rproc_get_by_phandle(rproc_phandle);
830 ath11k_err(ab, "failed to get rproc\n");
833 ab_ahb->tgt_rproc = prproc;
838 static int ath11k_ahb_setup_msi_resources(struct ath11k_base *ab)
840 struct platform_device *pdev = ab->pdev;
841 phys_addr_t msi_addr_pa;
842 dma_addr_t msi_addr_iova;
843 struct resource *res;
848 ret = ath11k_pcic_init_msi_config(ab);
850 ath11k_err(ab, "failed to init msi config: %d\n", ret);
854 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
856 ath11k_err(ab, "failed to fetch msi_addr\n");
860 msi_addr_pa = res->start;
861 msi_addr_iova = dma_map_resource(ab->dev, msi_addr_pa, PAGE_SIZE,
863 if (dma_mapping_error(ab->dev, msi_addr_iova))
866 ab->pci.msi.addr_lo = lower_32_bits(msi_addr_iova);
867 ab->pci.msi.addr_hi = upper_32_bits(msi_addr_iova);
869 ret = of_property_read_u32_index(ab->dev->of_node, "interrupts", 1, &int_prop);
873 ab->pci.msi.ep_base_data = int_prop + 32;
875 for (i = 0; i < ab->pci.msi.config->total_vectors; i++) {
876 ret = platform_get_irq(pdev, i);
880 ab->pci.msi.irqs[i] = ret;
883 set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
888 static int ath11k_ahb_setup_smp2p_handle(struct ath11k_base *ab)
890 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
892 if (!ab->hw_params.smp2p_wow_exit)
895 ab_ahb->smp2p_info.smem_state = qcom_smem_state_get(ab->dev, "wlan-smp2p-out",
896 &ab_ahb->smp2p_info.smem_bit);
897 if (IS_ERR(ab_ahb->smp2p_info.smem_state)) {
898 ath11k_err(ab, "failed to fetch smem state: %ld\n",
899 PTR_ERR(ab_ahb->smp2p_info.smem_state));
900 return PTR_ERR(ab_ahb->smp2p_info.smem_state);
906 static void ath11k_ahb_release_smp2p_handle(struct ath11k_base *ab)
908 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
910 if (!ab->hw_params.smp2p_wow_exit)
913 qcom_smem_state_put(ab_ahb->smp2p_info.smem_state);
916 static int ath11k_ahb_setup_resources(struct ath11k_base *ab)
918 struct platform_device *pdev = ab->pdev;
919 struct resource *mem_res;
922 if (ab->hw_params.hybrid_bus_type)
923 return ath11k_ahb_setup_msi_resources(ab);
925 mem = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res);
927 dev_err(&pdev->dev, "ioremap error\n");
932 ab->mem_len = resource_size(mem_res);
937 static int ath11k_ahb_setup_msa_resources(struct ath11k_base *ab)
939 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
940 struct device *dev = ab->dev;
941 struct device_node *node;
945 node = of_parse_phandle(dev->of_node, "memory-region", 0);
949 ret = of_address_to_resource(node, 0, &r);
952 dev_err(dev, "failed to resolve msa fixed region\n");
956 ab_ahb->fw.msa_paddr = r.start;
957 ab_ahb->fw.msa_size = resource_size(&r);
959 node = of_parse_phandle(dev->of_node, "memory-region", 1);
963 ret = of_address_to_resource(node, 0, &r);
966 dev_err(dev, "failed to resolve ce fixed region\n");
970 ab_ahb->fw.ce_paddr = r.start;
971 ab_ahb->fw.ce_size = resource_size(&r);
976 static int ath11k_ahb_fw_resources_init(struct ath11k_base *ab)
978 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
979 struct device *host_dev = ab->dev;
980 struct platform_device_info info = {0};
981 struct iommu_domain *iommu_dom;
982 struct platform_device *pdev;
983 struct device_node *node;
986 /* Chipsets not requiring MSA need not initialize
987 * MSA resources, return success in such cases.
989 if (!ab->hw_params.fixed_fw_mem)
992 ret = ath11k_ahb_setup_msa_resources(ab);
994 ath11k_err(ab, "failed to setup msa resources\n");
998 node = of_get_child_by_name(host_dev->of_node, "wifi-firmware");
1000 ab_ahb->fw.use_tz = true;
1004 info.fwnode = &node->fwnode;
1005 info.parent = host_dev;
1006 info.name = node->name;
1007 info.dma_mask = DMA_BIT_MASK(32);
1009 pdev = platform_device_register_full(&info);
1012 return PTR_ERR(pdev);
1015 ret = of_dma_configure(&pdev->dev, node, true);
1017 ath11k_err(ab, "dma configure fail: %d\n", ret);
1018 goto err_unregister;
1021 ab_ahb->fw.dev = &pdev->dev;
1023 iommu_dom = iommu_domain_alloc(&platform_bus_type);
1025 ath11k_err(ab, "failed to allocate iommu domain\n");
1027 goto err_unregister;
1030 ret = iommu_attach_device(iommu_dom, ab_ahb->fw.dev);
1032 ath11k_err(ab, "could not attach device: %d\n", ret);
1033 goto err_iommu_free;
1036 ret = iommu_map(iommu_dom, ab_ahb->fw.msa_paddr,
1037 ab_ahb->fw.msa_paddr, ab_ahb->fw.msa_size,
1038 IOMMU_READ | IOMMU_WRITE, GFP_KERNEL);
1040 ath11k_err(ab, "failed to map firmware region: %d\n", ret);
1041 goto err_iommu_detach;
1044 ret = iommu_map(iommu_dom, ab_ahb->fw.ce_paddr,
1045 ab_ahb->fw.ce_paddr, ab_ahb->fw.ce_size,
1046 IOMMU_READ | IOMMU_WRITE, GFP_KERNEL);
1048 ath11k_err(ab, "failed to map firmware CE region: %d\n", ret);
1049 goto err_iommu_unmap;
1052 ab_ahb->fw.use_tz = false;
1053 ab_ahb->fw.iommu_domain = iommu_dom;
1059 iommu_unmap(iommu_dom, ab_ahb->fw.msa_paddr, ab_ahb->fw.msa_size);
1062 iommu_detach_device(iommu_dom, ab_ahb->fw.dev);
1065 iommu_domain_free(iommu_dom);
1068 platform_device_unregister(pdev);
1074 static int ath11k_ahb_fw_resource_deinit(struct ath11k_base *ab)
1076 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
1077 struct iommu_domain *iommu;
1078 size_t unmapped_size;
1080 /* Chipsets not requiring MSA would have not initialized
1081 * MSA resources, return success in such cases.
1083 if (!ab->hw_params.fixed_fw_mem)
1086 if (ab_ahb->fw.use_tz)
1089 iommu = ab_ahb->fw.iommu_domain;
1091 unmapped_size = iommu_unmap(iommu, ab_ahb->fw.msa_paddr, ab_ahb->fw.msa_size);
1092 if (unmapped_size != ab_ahb->fw.msa_size)
1093 ath11k_err(ab, "failed to unmap firmware: %zu\n",
1096 unmapped_size = iommu_unmap(iommu, ab_ahb->fw.ce_paddr, ab_ahb->fw.ce_size);
1097 if (unmapped_size != ab_ahb->fw.ce_size)
1098 ath11k_err(ab, "failed to unmap firmware CE memory: %zu\n",
1101 iommu_detach_device(iommu, ab_ahb->fw.dev);
1102 iommu_domain_free(iommu);
1104 platform_device_unregister(to_platform_device(ab_ahb->fw.dev));
1109 static int ath11k_ahb_probe(struct platform_device *pdev)
1111 struct ath11k_base *ab;
1112 const struct of_device_id *of_id;
1113 const struct ath11k_hif_ops *hif_ops;
1114 const struct ath11k_pci_ops *pci_ops;
1115 enum ath11k_hw_rev hw_rev;
1118 of_id = of_match_device(ath11k_ahb_of_match, &pdev->dev);
1120 dev_err(&pdev->dev, "failed to find matching device tree id\n");
1124 hw_rev = (enum ath11k_hw_rev)of_id->data;
1127 case ATH11K_HW_IPQ8074:
1128 case ATH11K_HW_IPQ6018_HW10:
1129 case ATH11K_HW_IPQ5018_HW10:
1130 hif_ops = &ath11k_ahb_hif_ops_ipq8074;
1133 case ATH11K_HW_WCN6750_HW10:
1134 hif_ops = &ath11k_ahb_hif_ops_wcn6750;
1135 pci_ops = &ath11k_ahb_pci_ops_wcn6750;
1138 dev_err(&pdev->dev, "unsupported device type %d\n", hw_rev);
1142 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1144 dev_err(&pdev->dev, "failed to set 32-bit consistent dma\n");
1148 ab = ath11k_core_alloc(&pdev->dev, sizeof(struct ath11k_ahb),
1151 dev_err(&pdev->dev, "failed to allocate ath11k base\n");
1155 ab->hif.ops = hif_ops;
1157 ab->hw_rev = hw_rev;
1158 ab->fw_mode = ATH11K_FIRMWARE_MODE_NORMAL;
1159 platform_set_drvdata(pdev, ab);
1161 ret = ath11k_pcic_register_pci_ops(ab, pci_ops);
1163 ath11k_err(ab, "failed to register PCI ops: %d\n", ret);
1167 ret = ath11k_core_pre_init(ab);
1171 ret = ath11k_ahb_setup_resources(ab);
1175 ab->mem_ce = ab->mem;
1177 if (ab->hw_params.ce_remap) {
1178 const struct ce_remap *ce_remap = ab->hw_params.ce_remap;
1179 /* ce register space is moved out of wcss unlike ipq8074 or ipq6018
1180 * and the space is not contiguous, hence remapping the CE registers
1181 * to a new space for accessing them.
1183 ab->mem_ce = ioremap(ce_remap->base, ce_remap->size);
1185 dev_err(&pdev->dev, "ce ioremap error\n");
1191 ret = ath11k_ahb_fw_resources_init(ab);
1195 ret = ath11k_ahb_setup_smp2p_handle(ab);
1199 ret = ath11k_hal_srng_init(ab);
1201 goto err_release_smp2p_handle;
1203 ret = ath11k_ce_alloc_pipes(ab);
1205 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret);
1206 goto err_hal_srng_deinit;
1209 ath11k_ahb_init_qmi_ce_config(ab);
1211 ret = ath11k_core_get_rproc(ab);
1213 ath11k_err(ab, "failed to get rproc: %d\n", ret);
1217 ret = ath11k_core_init(ab);
1219 ath11k_err(ab, "failed to init core: %d\n", ret);
1223 ret = ath11k_ahb_config_irq(ab);
1225 ath11k_err(ab, "failed to configure irq: %d\n", ret);
1229 ath11k_ahb_fwreset_from_cold_boot(ab);
1234 ath11k_ce_free_pipes(ab);
1236 err_hal_srng_deinit:
1237 ath11k_hal_srng_deinit(ab);
1239 err_release_smp2p_handle:
1240 ath11k_ahb_release_smp2p_handle(ab);
1243 ath11k_ahb_fw_resource_deinit(ab);
1246 ath11k_core_free(ab);
1247 platform_set_drvdata(pdev, NULL);
1252 static void ath11k_ahb_remove_prepare(struct ath11k_base *ab)
1256 if (test_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags)) {
1257 left = wait_for_completion_timeout(&ab->driver_recovery,
1258 ATH11K_AHB_RECOVERY_TIMEOUT);
1260 ath11k_warn(ab, "failed to receive recovery response completion\n");
1263 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags);
1264 cancel_work_sync(&ab->restart_work);
1265 cancel_work_sync(&ab->qmi.event_work);
1268 static void ath11k_ahb_free_resources(struct ath11k_base *ab)
1270 struct platform_device *pdev = ab->pdev;
1272 ath11k_ahb_free_irq(ab);
1273 ath11k_hal_srng_deinit(ab);
1274 ath11k_ahb_release_smp2p_handle(ab);
1275 ath11k_ahb_fw_resource_deinit(ab);
1276 ath11k_ce_free_pipes(ab);
1278 if (ab->hw_params.ce_remap)
1279 iounmap(ab->mem_ce);
1281 ath11k_core_free(ab);
1282 platform_set_drvdata(pdev, NULL);
1285 static int ath11k_ahb_remove(struct platform_device *pdev)
1287 struct ath11k_base *ab = platform_get_drvdata(pdev);
1289 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
1290 ath11k_ahb_power_down(ab);
1291 ath11k_debugfs_soc_destroy(ab);
1292 ath11k_qmi_deinit_service(ab);
1296 ath11k_ahb_remove_prepare(ab);
1297 ath11k_core_deinit(ab);
1300 ath11k_ahb_free_resources(ab);
1305 static void ath11k_ahb_shutdown(struct platform_device *pdev)
1307 struct ath11k_base *ab = platform_get_drvdata(pdev);
1309 /* platform shutdown() & remove() are mutually exclusive.
1310 * remove() is invoked during rmmod & shutdown() during
1311 * system reboot/shutdown.
1313 ath11k_ahb_remove_prepare(ab);
1315 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags)))
1316 goto free_resources;
1318 ath11k_core_deinit(ab);
1321 ath11k_ahb_free_resources(ab);
1324 static struct platform_driver ath11k_ahb_driver = {
1327 .of_match_table = ath11k_ahb_of_match,
1329 .probe = ath11k_ahb_probe,
1330 .remove = ath11k_ahb_remove,
1331 .shutdown = ath11k_ahb_shutdown,
1334 static int ath11k_ahb_init(void)
1336 return platform_driver_register(&ath11k_ahb_driver);
1338 module_init(ath11k_ahb_init);
1340 static void ath11k_ahb_exit(void)
1342 platform_driver_unregister(&ath11k_ahb_driver);
1344 module_exit(ath11k_ahb_exit);
1346 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN AHB devices");
1347 MODULE_LICENSE("Dual BSD/GPL");