drivers/net/wireless/ath/ath10k/snoc.c

   1 /*
   2  * Copyright (c) 2018 The Linux Foundation. All rights reserved.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regulator/consumer.h>
  24
  25 #include "ce.h"
  26 #include "debug.h"
  27 #include "hif.h"
  28 #include "htc.h"
  29 #include "snoc.h"
  30
  31 #define ATH10K_SNOC_RX_POST_RETRY_MS 50
  32 #define CE_POLL_PIPE 4
  33 #define ATH10K_SNOC_WAKE_IRQ 2
  34
  35 static char *const ce_name[] = {
  36         "WLAN_CE_0",
  37         "WLAN_CE_1",
  38         "WLAN_CE_2",
  39         "WLAN_CE_3",
  40         "WLAN_CE_4",
  41         "WLAN_CE_5",
  42         "WLAN_CE_6",
  43         "WLAN_CE_7",
  44         "WLAN_CE_8",
  45         "WLAN_CE_9",
  46         "WLAN_CE_10",
  47         "WLAN_CE_11",
  48 };
  49
  50 static struct ath10k_vreg_info vreg_cfg[] = {
  51         {NULL, "vdd-0.8-cx-mx", 800000, 850000, 0, 0, false},
  52         {NULL, "vdd-1.8-xo", 1800000, 1850000, 0, 0, false},
  53         {NULL, "vdd-1.3-rfa", 1300000, 1350000, 0, 0, false},
  54         {NULL, "vdd-3.3-ch0", 3300000, 3350000, 0, 0, false},
  55 };
  56
  57 static struct ath10k_clk_info clk_cfg[] = {
  58         {NULL, "cxo_ref_clk_pin", 0, false},
  59 };
  60
  61 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
  62 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
  63 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
  64 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
  65 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
  66 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
  67
  68 static const struct ath10k_snoc_drv_priv drv_priv = {
  69         .hw_rev = ATH10K_HW_WCN3990,
  70         .dma_mask = DMA_BIT_MASK(35),
  71         .msa_size = 0x100000,
  72 };
  73
  74 #define WCN3990_SRC_WR_IDX_OFFSET 0x3C
  75 #define WCN3990_DST_WR_IDX_OFFSET 0x40
  76
  77 static struct ath10k_shadow_reg_cfg target_shadow_reg_cfg_map[] = {
  78                 {
  79                         .ce_id = __cpu_to_le16(0),
  80                         .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
  81                 },
  82
  83                 {
  84                         .ce_id = __cpu_to_le16(3),
  85                         .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
  86                 },
  87
  88                 {
  89                         .ce_id = __cpu_to_le16(4),
  90                         .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
  91                 },
  92
  93                 {
  94                         .ce_id = __cpu_to_le16(5),
  95                         .reg_offset =  __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
  96                 },
  97
  98                 {
  99                         .ce_id = __cpu_to_le16(7),
 100                         .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
 101                 },
 102
 103                 {
 104                         .ce_id = __cpu_to_le16(1),
 105                         .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
 106                 },
 107
 108                 {
 109                         .ce_id = __cpu_to_le16(2),
 110                         .reg_offset =  __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
 111                 },
 112
 113                 {
 114                         .ce_id = __cpu_to_le16(7),
 115                         .reg_offset =  __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
 116                 },
 117
 118                 {
 119                         .ce_id = __cpu_to_le16(8),
 120                         .reg_offset =  __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
 121                 },
 122
 123                 {
 124                         .ce_id = __cpu_to_le16(9),
 125                         .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
 126                 },
 127
 128                 {
 129                         .ce_id = __cpu_to_le16(10),
 130                         .reg_offset =  __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
 131                 },
 132
 133                 {
 134                         .ce_id = __cpu_to_le16(11),
 135                         .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
 136                 },
 137 };
 138
 139 static struct ce_attr host_ce_config_wlan[] = {
 140         /* CE0: host->target HTC control streams */
 141         {
 142                 .flags = CE_ATTR_FLAGS,
 143                 .src_nentries = 16,
 144                 .src_sz_max = 2048,
 145                 .dest_nentries = 0,
 146                 .send_cb = ath10k_snoc_htc_tx_cb,
 147         },
 148
 149         /* CE1: target->host HTT + HTC control */
 150         {
 151                 .flags = CE_ATTR_FLAGS,
 152                 .src_nentries = 0,
 153                 .src_sz_max = 2048,
 154                 .dest_nentries = 512,
 155                 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
 156         },
 157
 158         /* CE2: target->host WMI */
 159         {
 160                 .flags = CE_ATTR_FLAGS,
 161                 .src_nentries = 0,
 162                 .src_sz_max = 2048,
 163                 .dest_nentries = 64,
 164                 .recv_cb = ath10k_snoc_htc_rx_cb,
 165         },
 166
 167         /* CE3: host->target WMI */
 168         {
 169                 .flags = CE_ATTR_FLAGS,
 170                 .src_nentries = 32,
 171                 .src_sz_max = 2048,
 172                 .dest_nentries = 0,
 173                 .send_cb = ath10k_snoc_htc_tx_cb,
 174         },
 175
 176         /* CE4: host->target HTT */
 177         {
 178                 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
 179                 .src_nentries = 256,
 180                 .src_sz_max = 256,
 181                 .dest_nentries = 0,
 182                 .send_cb = ath10k_snoc_htt_tx_cb,
 183         },
 184
 185         /* CE5: target->host HTT (ipa_uc->target ) */
 186         {
 187                 .flags = CE_ATTR_FLAGS,
 188                 .src_nentries = 0,
 189                 .src_sz_max = 512,
 190                 .dest_nentries = 512,
 191                 .recv_cb = ath10k_snoc_htt_rx_cb,
 192         },
 193
 194         /* CE6: target autonomous hif_memcpy */
 195         {
 196                 .flags = CE_ATTR_FLAGS,
 197                 .src_nentries = 0,
 198                 .src_sz_max = 0,
 199                 .dest_nentries = 0,
 200         },
 201
 202         /* CE7: ce_diag, the Diagnostic Window */
 203         {
 204                 .flags = CE_ATTR_FLAGS,
 205                 .src_nentries = 2,
 206                 .src_sz_max = 2048,
 207                 .dest_nentries = 2,
 208         },
 209
 210         /* CE8: Target to uMC */
 211         {
 212                 .flags = CE_ATTR_FLAGS,
 213                 .src_nentries = 0,
 214                 .src_sz_max = 2048,
 215                 .dest_nentries = 128,
 216         },
 217
 218         /* CE9 target->host HTT */
 219         {
 220                 .flags = CE_ATTR_FLAGS,
 221                 .src_nentries = 0,
 222                 .src_sz_max = 2048,
 223                 .dest_nentries = 512,
 224                 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
 225         },
 226
 227         /* CE10: target->host HTT */
 228         {
 229                 .flags = CE_ATTR_FLAGS,
 230                 .src_nentries = 0,
 231                 .src_sz_max = 2048,
 232                 .dest_nentries = 512,
 233                 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
 234         },
 235
 236         /* CE11: target -> host PKTLOG */
 237         {
 238                 .flags = CE_ATTR_FLAGS,
 239                 .src_nentries = 0,
 240                 .src_sz_max = 2048,
 241                 .dest_nentries = 512,
 242                 .recv_cb = ath10k_snoc_pktlog_rx_cb,
 243         },
 244 };
 245
 246 static struct ce_pipe_config target_ce_config_wlan[] = {
 247         /* CE0: host->target HTC control and raw streams */
 248         {
 249                 .pipenum = __cpu_to_le32(0),
 250                 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
 251                 .nentries = __cpu_to_le32(32),
 252                 .nbytes_max = __cpu_to_le32(2048),
 253                 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
 254                 .reserved = __cpu_to_le32(0),
 255         },
 256
 257         /* CE1: target->host HTT + HTC control */
 258         {
 259                 .pipenum = __cpu_to_le32(1),
 260                 .pipedir = __cpu_to_le32(PIPEDIR_IN),
 261                 .nentries = __cpu_to_le32(32),
 262                 .nbytes_max = __cpu_to_le32(2048),
 263                 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
 264                 .reserved = __cpu_to_le32(0),
 265         },
 266
 267         /* CE2: target->host WMI */
 268         {
 269                 .pipenum = __cpu_to_le32(2),
 270                 .pipedir = __cpu_to_le32(PIPEDIR_IN),
 271                 .nentries = __cpu_to_le32(64),
 272                 .nbytes_max = __cpu_to_le32(2048),
 273                 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
 274                 .reserved = __cpu_to_le32(0),
 275         },
 276
 277         /* CE3: host->target WMI */
 278         {
 279                 .pipenum = __cpu_to_le32(3),
 280                 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
 281                 .nentries = __cpu_to_le32(32),
 282                 .nbytes_max = __cpu_to_le32(2048),
 283                 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
 284                 .reserved = __cpu_to_le32(0),
 285         },
 286
 287         /* CE4: host->target HTT */
 288         {
 289                 .pipenum = __cpu_to_le32(4),
 290                 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
 291                 .nentries = __cpu_to_le32(256),
 292                 .nbytes_max = __cpu_to_le32(256),
 293                 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
 294                 .reserved = __cpu_to_le32(0),
 295         },
 296
 297         /* CE5: target->host HTT (HIF->HTT) */
 298         {
 299                 .pipenum = __cpu_to_le32(5),
 300                 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
 301                 .nentries = __cpu_to_le32(1024),
 302                 .nbytes_max = __cpu_to_le32(64),
 303                 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
 304                 .reserved = __cpu_to_le32(0),
 305         },
 306
 307         /* CE6: Reserved for target autonomous hif_memcpy */
 308         {
 309                 .pipenum = __cpu_to_le32(6),
 310                 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
 311                 .nentries = __cpu_to_le32(32),
 312                 .nbytes_max = __cpu_to_le32(16384),
 313                 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
 314                 .reserved = __cpu_to_le32(0),
 315         },
 316
 317         /* CE7 used only by Host */
 318         {
 319                 .pipenum = __cpu_to_le32(7),
 320                 .pipedir = __cpu_to_le32(4),
 321                 .nentries = __cpu_to_le32(0),
 322                 .nbytes_max = __cpu_to_le32(0),
 323                 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
 324                 .reserved = __cpu_to_le32(0),
 325         },
 326
 327         /* CE8 Target to uMC */
 328         {
 329                 .pipenum = __cpu_to_le32(8),
 330                 .pipedir = __cpu_to_le32(PIPEDIR_IN),
 331                 .nentries = __cpu_to_le32(32),
 332                 .nbytes_max = __cpu_to_le32(2048),
 333                 .flags = __cpu_to_le32(0),
 334                 .reserved = __cpu_to_le32(0),
 335         },
 336
 337         /* CE9 target->host HTT */
 338         {
 339                 .pipenum = __cpu_to_le32(9),
 340                 .pipedir = __cpu_to_le32(PIPEDIR_IN),
 341                 .nentries = __cpu_to_le32(32),
 342                 .nbytes_max = __cpu_to_le32(2048),
 343                 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
 344                 .reserved = __cpu_to_le32(0),
 345         },
 346
 347         /* CE10 target->host HTT */
 348         {
 349                 .pipenum = __cpu_to_le32(10),
 350                 .pipedir = __cpu_to_le32(PIPEDIR_IN),
 351                 .nentries = __cpu_to_le32(32),
 352                 .nbytes_max = __cpu_to_le32(2048),
 353                 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
 354                 .reserved = __cpu_to_le32(0),
 355         },
 356
 357         /* CE11 target autonomous qcache memcpy */
 358         {
 359                 .pipenum = __cpu_to_le32(11),
 360                 .pipedir = __cpu_to_le32(PIPEDIR_IN),
 361                 .nentries = __cpu_to_le32(32),
 362                 .nbytes_max = __cpu_to_le32(2048),
 363                 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
 364                 .reserved = __cpu_to_le32(0),
 365         },
 366 };
 367
 368 static struct service_to_pipe target_service_to_ce_map_wlan[] = {
 369         {
 370                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
 371                 __cpu_to_le32(PIPEDIR_OUT),     /* out = UL = host -> target */
 372                 __cpu_to_le32(3),
 373         },
 374         {
 375                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
 376                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 377                 __cpu_to_le32(2),
 378         },
 379         {
 380                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
 381                 __cpu_to_le32(PIPEDIR_OUT),     /* out = UL = host -> target */
 382                 __cpu_to_le32(3),
 383         },
 384         {
 385                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
 386                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 387                 __cpu_to_le32(2),
 388         },
 389         {
 390                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
 391                 __cpu_to_le32(PIPEDIR_OUT),     /* out = UL = host -> target */
 392                 __cpu_to_le32(3),
 393         },
 394         {
 395                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
 396                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 397                 __cpu_to_le32(2),
 398         },
 399         {
 400                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
 401                 __cpu_to_le32(PIPEDIR_OUT),     /* out = UL = host -> target */
 402                 __cpu_to_le32(3),
 403         },
 404         {
 405                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
 406                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 407                 __cpu_to_le32(2),
 408         },
 409         {
 410                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
 411                 __cpu_to_le32(PIPEDIR_OUT),     /* out = UL = host -> target */
 412                 __cpu_to_le32(3),
 413         },
 414         {
 415                 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
 416                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 417                 __cpu_to_le32(2),
 418         },
 419         {
 420                 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
 421                 __cpu_to_le32(PIPEDIR_OUT),     /* out = UL = host -> target */
 422                 __cpu_to_le32(0),
 423         },
 424         {
 425                 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
 426                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 427                 __cpu_to_le32(2),
 428         },
 429         { /* not used */
 430                 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
 431                 __cpu_to_le32(PIPEDIR_OUT),     /* out = UL = host -> target */
 432                 __cpu_to_le32(0),
 433         },
 434         { /* not used */
 435                 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
 436                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 437                 __cpu_to_le32(2),
 438         },
 439         {
 440                 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
 441                 __cpu_to_le32(PIPEDIR_OUT),     /* out = UL = host -> target */
 442                 __cpu_to_le32(4),
 443         },
 444         {
 445                 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
 446                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 447                 __cpu_to_le32(1),
 448         },
 449         { /* not used */
 450                 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
 451                 __cpu_to_le32(PIPEDIR_OUT),
 452                 __cpu_to_le32(5),
 453         },
 454         { /* in = DL = target -> host */
 455                 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA2_MSG),
 456                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 457                 __cpu_to_le32(9),
 458         },
 459         { /* in = DL = target -> host */
 460                 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA3_MSG),
 461                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 462                 __cpu_to_le32(10),
 463         },
 464         { /* in = DL = target -> host pktlog */
 465                 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_LOG_MSG),
 466                 __cpu_to_le32(PIPEDIR_IN),      /* in = DL = target -> host */
 467                 __cpu_to_le32(11),
 468         },
 469         /* (Additions here) */
 470
 471         { /* must be last */
 472                 __cpu_to_le32(0),
 473                 __cpu_to_le32(0),
 474                 __cpu_to_le32(0),
 475         },
 476 };
 477
 478 static void ath10k_snoc_write32(struct ath10k *ar, u32 offset, u32 value)
 479 {
 480         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 481
 482         iowrite32(value, ar_snoc->mem + offset);
 483 }
 484
 485 static u32 ath10k_snoc_read32(struct ath10k *ar, u32 offset)
 486 {
 487         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 488         u32 val;
 489
 490         val = ioread32(ar_snoc->mem + offset);
 491
 492         return val;
 493 }
 494
 495 static int __ath10k_snoc_rx_post_buf(struct ath10k_snoc_pipe *pipe)
 496 {
 497         struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
 498         struct ath10k *ar = pipe->hif_ce_state;
 499         struct ath10k_ce *ce = ath10k_ce_priv(ar);
 500         struct sk_buff *skb;
 501         dma_addr_t paddr;
 502         int ret;
 503
 504         skb = dev_alloc_skb(pipe->buf_sz);
 505         if (!skb)
 506                 return -ENOMEM;
 507
 508         WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
 509
 510         paddr = dma_map_single(ar->dev, skb->data,
 511                                skb->len + skb_tailroom(skb),
 512                                DMA_FROM_DEVICE);
 513         if (unlikely(dma_mapping_error(ar->dev, paddr))) {
 514                 ath10k_warn(ar, "failed to dma map snoc rx buf\n");
 515                 dev_kfree_skb_any(skb);
 516                 return -EIO;
 517         }
 518
 519         ATH10K_SKB_RXCB(skb)->paddr = paddr;
 520
 521         spin_lock_bh(&ce->ce_lock);
 522         ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr);
 523         spin_unlock_bh(&ce->ce_lock);
 524         if (ret) {
 525                 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
 526                                  DMA_FROM_DEVICE);
 527                 dev_kfree_skb_any(skb);
 528                 return ret;
 529         }
 530
 531         return 0;
 532 }
 533
 534 static void ath10k_snoc_rx_post_pipe(struct ath10k_snoc_pipe *pipe)
 535 {
 536         struct ath10k *ar = pipe->hif_ce_state;
 537         struct ath10k_ce *ce = ath10k_ce_priv(ar);
 538         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 539         struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
 540         int ret, num;
 541
 542         if (pipe->buf_sz == 0)
 543                 return;
 544
 545         if (!ce_pipe->dest_ring)
 546                 return;
 547
 548         spin_lock_bh(&ce->ce_lock);
 549         num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
 550         spin_unlock_bh(&ce->ce_lock);
 551         while (num--) {
 552                 ret = __ath10k_snoc_rx_post_buf(pipe);
 553                 if (ret) {
 554                         if (ret == -ENOSPC)
 555                                 break;
 556                         ath10k_warn(ar, "failed to post rx buf: %d\n", ret);
 557                         mod_timer(&ar_snoc->rx_post_retry, jiffies +
 558                                   ATH10K_SNOC_RX_POST_RETRY_MS);
 559                         break;
 560                 }
 561         }
 562 }
 563
 564 static void ath10k_snoc_rx_post(struct ath10k *ar)
 565 {
 566         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 567         int i;
 568
 569         for (i = 0; i < CE_COUNT; i++)
 570                 ath10k_snoc_rx_post_pipe(&ar_snoc->pipe_info[i]);
 571 }
 572
 573 static void ath10k_snoc_process_rx_cb(struct ath10k_ce_pipe *ce_state,
 574                                       void (*callback)(struct ath10k *ar,
 575                                                        struct sk_buff *skb))
 576 {
 577         struct ath10k *ar = ce_state->ar;
 578         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 579         struct ath10k_snoc_pipe *pipe_info =  &ar_snoc->pipe_info[ce_state->id];
 580         struct sk_buff *skb;
 581         struct sk_buff_head list;
 582         void *transfer_context;
 583         unsigned int nbytes, max_nbytes;
 584
 585         __skb_queue_head_init(&list);
 586         while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
 587                                              &nbytes) == 0) {
 588                 skb = transfer_context;
 589                 max_nbytes = skb->len + skb_tailroom(skb);
 590                 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
 591                                  max_nbytes, DMA_FROM_DEVICE);
 592
 593                 if (unlikely(max_nbytes < nbytes)) {
 594                         ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
 595                                     nbytes, max_nbytes);
 596                         dev_kfree_skb_any(skb);
 597                         continue;
 598                 }
 599
 600                 skb_put(skb, nbytes);
 601                 __skb_queue_tail(&list, skb);
 602         }
 603
 604         while ((skb = __skb_dequeue(&list))) {
 605                 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc rx ce pipe %d len %d\n",
 606                            ce_state->id, skb->len);
 607
 608                 callback(ar, skb);
 609         }
 610
 611         ath10k_snoc_rx_post_pipe(pipe_info);
 612 }
 613
 614 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
 615 {
 616         ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
 617 }
 618
 619 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
 620 {
 621         /* CE4 polling needs to be done whenever CE pipe which transports
 622          * HTT Rx (target->host) is processed.
 623          */
 624         ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE);
 625
 626         ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
 627 }
 628
 629 /* Called by lower (CE) layer when data is received from the Target.
 630  * WCN3990 firmware uses separate CE(CE11) to transfer pktlog data.
 631  */
 632 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
 633 {
 634         ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
 635 }
 636
 637 static void ath10k_snoc_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
 638 {
 639         skb_pull(skb, sizeof(struct ath10k_htc_hdr));
 640         ath10k_htt_t2h_msg_handler(ar, skb);
 641 }
 642
 643 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
 644 {
 645         ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE);
 646         ath10k_snoc_process_rx_cb(ce_state, ath10k_snoc_htt_rx_deliver);
 647 }
 648
 649 static void ath10k_snoc_rx_replenish_retry(struct timer_list *t)
 650 {
 651         struct ath10k_snoc *ar_snoc = from_timer(ar_snoc, t, rx_post_retry);
 652         struct ath10k *ar = ar_snoc->ar;
 653
 654         ath10k_snoc_rx_post(ar);
 655 }
 656
 657 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
 658 {
 659         struct ath10k *ar = ce_state->ar;
 660         struct sk_buff_head list;
 661         struct sk_buff *skb;
 662
 663         __skb_queue_head_init(&list);
 664         while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
 665                 if (!skb)
 666                         continue;
 667
 668                 __skb_queue_tail(&list, skb);
 669         }
 670
 671         while ((skb = __skb_dequeue(&list)))
 672                 ath10k_htc_tx_completion_handler(ar, skb);
 673 }
 674
 675 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
 676 {
 677         struct ath10k *ar = ce_state->ar;
 678         struct sk_buff *skb;
 679
 680         while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
 681                 if (!skb)
 682                         continue;
 683
 684                 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
 685                                  skb->len, DMA_TO_DEVICE);
 686                 ath10k_htt_hif_tx_complete(ar, skb);
 687         }
 688 }
 689
 690 static int ath10k_snoc_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
 691                                  struct ath10k_hif_sg_item *items, int n_items)
 692 {
 693         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 694         struct ath10k_ce *ce = ath10k_ce_priv(ar);
 695         struct ath10k_snoc_pipe *snoc_pipe;
 696         struct ath10k_ce_pipe *ce_pipe;
 697         int err, i = 0;
 698
 699         snoc_pipe = &ar_snoc->pipe_info[pipe_id];
 700         ce_pipe = snoc_pipe->ce_hdl;
 701         spin_lock_bh(&ce->ce_lock);
 702
 703         for (i = 0; i < n_items - 1; i++) {
 704                 ath10k_dbg(ar, ATH10K_DBG_SNOC,
 705                            "snoc tx item %d paddr %pad len %d n_items %d\n",
 706                            i, &items[i].paddr, items[i].len, n_items);
 707
 708                 err = ath10k_ce_send_nolock(ce_pipe,
 709                                             items[i].transfer_context,
 710                                             items[i].paddr,
 711                                             items[i].len,
 712                                             items[i].transfer_id,
 713                                             CE_SEND_FLAG_GATHER);
 714                 if (err)
 715                         goto err;
 716         }
 717
 718         ath10k_dbg(ar, ATH10K_DBG_SNOC,
 719                    "snoc tx item %d paddr %pad len %d n_items %d\n",
 720                    i, &items[i].paddr, items[i].len, n_items);
 721
 722         err = ath10k_ce_send_nolock(ce_pipe,
 723                                     items[i].transfer_context,
 724                                     items[i].paddr,
 725                                     items[i].len,
 726                                     items[i].transfer_id,
 727                                     0);
 728         if (err)
 729                 goto err;
 730
 731         spin_unlock_bh(&ce->ce_lock);
 732
 733         return 0;
 734
 735 err:
 736         for (; i > 0; i--)
 737                 __ath10k_ce_send_revert(ce_pipe);
 738
 739         spin_unlock_bh(&ce->ce_lock);
 740         return err;
 741 }
 742
 743 static int ath10k_snoc_hif_get_target_info(struct ath10k *ar,
 744                                            struct bmi_target_info *target_info)
 745 {
 746         target_info->version = ATH10K_HW_WCN3990;
 747         target_info->type = ATH10K_HW_WCN3990;
 748
 749         return 0;
 750 }
 751
 752 static u16 ath10k_snoc_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
 753 {
 754         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 755
 756         ath10k_dbg(ar, ATH10K_DBG_SNOC, "hif get free queue number\n");
 757
 758         return ath10k_ce_num_free_src_entries(ar_snoc->pipe_info[pipe].ce_hdl);
 759 }
 760
 761 static void ath10k_snoc_hif_send_complete_check(struct ath10k *ar, u8 pipe,
 762                                                 int force)
 763 {
 764         int resources;
 765
 766         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif send complete check\n");
 767
 768         if (!force) {
 769                 resources = ath10k_snoc_hif_get_free_queue_number(ar, pipe);
 770
 771                 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
 772                         return;
 773         }
 774         ath10k_ce_per_engine_service(ar, pipe);
 775 }
 776
 777 static int ath10k_snoc_hif_map_service_to_pipe(struct ath10k *ar,
 778                                                u16 service_id,
 779                                                u8 *ul_pipe, u8 *dl_pipe)
 780 {
 781         const struct service_to_pipe *entry;
 782         bool ul_set = false, dl_set = false;
 783         int i;
 784
 785         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif map service\n");
 786
 787         for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
 788                 entry = &target_service_to_ce_map_wlan[i];
 789
 790                 if (__le32_to_cpu(entry->service_id) != service_id)
 791                         continue;
 792
 793                 switch (__le32_to_cpu(entry->pipedir)) {
 794                 case PIPEDIR_NONE:
 795                         break;
 796                 case PIPEDIR_IN:
 797                         WARN_ON(dl_set);
 798                         *dl_pipe = __le32_to_cpu(entry->pipenum);
 799                         dl_set = true;
 800                         break;
 801                 case PIPEDIR_OUT:
 802                         WARN_ON(ul_set);
 803                         *ul_pipe = __le32_to_cpu(entry->pipenum);
 804                         ul_set = true;
 805                         break;
 806                 case PIPEDIR_INOUT:
 807                         WARN_ON(dl_set);
 808                         WARN_ON(ul_set);
 809                         *dl_pipe = __le32_to_cpu(entry->pipenum);
 810                         *ul_pipe = __le32_to_cpu(entry->pipenum);
 811                         dl_set = true;
 812                         ul_set = true;
 813                         break;
 814                 }
 815         }
 816
 817         if (!ul_set || !dl_set)
 818                 return -ENOENT;
 819
 820         return 0;
 821 }
 822
 823 static void ath10k_snoc_hif_get_default_pipe(struct ath10k *ar,
 824                                              u8 *ul_pipe, u8 *dl_pipe)
 825 {
 826         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif get default pipe\n");
 827
 828         (void)ath10k_snoc_hif_map_service_to_pipe(ar,
 829                                                  ATH10K_HTC_SVC_ID_RSVD_CTRL,
 830                                                  ul_pipe, dl_pipe);
 831 }
 832
 833 static inline void ath10k_snoc_irq_disable(struct ath10k *ar)
 834 {
 835         ath10k_ce_disable_interrupts(ar);
 836 }
 837
 838 static inline void ath10k_snoc_irq_enable(struct ath10k *ar)
 839 {
 840         ath10k_ce_enable_interrupts(ar);
 841 }
 842
 843 static void ath10k_snoc_rx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe)
 844 {
 845         struct ath10k_ce_pipe *ce_pipe;
 846         struct ath10k_ce_ring *ce_ring;
 847         struct sk_buff *skb;
 848         struct ath10k *ar;
 849         int i;
 850
 851         ar = snoc_pipe->hif_ce_state;
 852         ce_pipe = snoc_pipe->ce_hdl;
 853         ce_ring = ce_pipe->dest_ring;
 854
 855         if (!ce_ring)
 856                 return;
 857
 858         if (!snoc_pipe->buf_sz)
 859                 return;
 860
 861         for (i = 0; i < ce_ring->nentries; i++) {
 862                 skb = ce_ring->per_transfer_context[i];
 863                 if (!skb)
 864                         continue;
 865
 866                 ce_ring->per_transfer_context[i] = NULL;
 867
 868                 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
 869                                  skb->len + skb_tailroom(skb),
 870                                  DMA_FROM_DEVICE);
 871                 dev_kfree_skb_any(skb);
 872         }
 873 }
 874
 875 static void ath10k_snoc_tx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe)
 876 {
 877         struct ath10k_ce_pipe *ce_pipe;
 878         struct ath10k_ce_ring *ce_ring;
 879         struct sk_buff *skb;
 880         struct ath10k *ar;
 881         int i;
 882
 883         ar = snoc_pipe->hif_ce_state;
 884         ce_pipe = snoc_pipe->ce_hdl;
 885         ce_ring = ce_pipe->src_ring;
 886
 887         if (!ce_ring)
 888                 return;
 889
 890         if (!snoc_pipe->buf_sz)
 891                 return;
 892
 893         for (i = 0; i < ce_ring->nentries; i++) {
 894                 skb = ce_ring->per_transfer_context[i];
 895                 if (!skb)
 896                         continue;
 897
 898                 ce_ring->per_transfer_context[i] = NULL;
 899
 900                 ath10k_htc_tx_completion_handler(ar, skb);
 901         }
 902 }
 903
 904 static void ath10k_snoc_buffer_cleanup(struct ath10k *ar)
 905 {
 906         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 907         struct ath10k_snoc_pipe *pipe_info;
 908         int pipe_num;
 909
 910         del_timer_sync(&ar_snoc->rx_post_retry);
 911         for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
 912                 pipe_info = &ar_snoc->pipe_info[pipe_num];
 913                 ath10k_snoc_rx_pipe_cleanup(pipe_info);
 914                 ath10k_snoc_tx_pipe_cleanup(pipe_info);
 915         }
 916 }
 917
 918 static void ath10k_snoc_hif_stop(struct ath10k *ar)
 919 {
 920         if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags))
 921                 ath10k_snoc_irq_disable(ar);
 922
 923         napi_synchronize(&ar->napi);
 924         napi_disable(&ar->napi);
 925         ath10k_snoc_buffer_cleanup(ar);
 926         ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
 927 }
 928
 929 static int ath10k_snoc_hif_start(struct ath10k *ar)
 930 {
 931         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
 932
 933         napi_enable(&ar->napi);
 934         ath10k_snoc_irq_enable(ar);
 935         ath10k_snoc_rx_post(ar);
 936
 937         clear_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags);
 938
 939         ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
 940
 941         return 0;
 942 }
 943
 944 static int ath10k_snoc_init_pipes(struct ath10k *ar)
 945 {
 946         int i, ret;
 947
 948         for (i = 0; i < CE_COUNT; i++) {
 949                 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
 950                 if (ret) {
 951                         ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
 952                                    i, ret);
 953                         return ret;
 954                 }
 955         }
 956
 957         return 0;
 958 }
 959
 960 static int ath10k_snoc_wlan_enable(struct ath10k *ar,
 961                                    enum ath10k_firmware_mode fw_mode)
 962 {
 963         struct ath10k_tgt_pipe_cfg tgt_cfg[CE_COUNT_MAX];
 964         struct ath10k_qmi_wlan_enable_cfg cfg;
 965         enum wlfw_driver_mode_enum_v01 mode;
 966         int pipe_num;
 967
 968         for (pipe_num = 0; pipe_num < CE_COUNT_MAX; pipe_num++) {
 969                 tgt_cfg[pipe_num].pipe_num =
 970                                 target_ce_config_wlan[pipe_num].pipenum;
 971                 tgt_cfg[pipe_num].pipe_dir =
 972                                 target_ce_config_wlan[pipe_num].pipedir;
 973                 tgt_cfg[pipe_num].nentries =
 974                                 target_ce_config_wlan[pipe_num].nentries;
 975                 tgt_cfg[pipe_num].nbytes_max =
 976                                 target_ce_config_wlan[pipe_num].nbytes_max;
 977                 tgt_cfg[pipe_num].flags =
 978                                 target_ce_config_wlan[pipe_num].flags;
 979                 tgt_cfg[pipe_num].reserved = 0;
 980         }
 981
 982         cfg.num_ce_tgt_cfg = sizeof(target_ce_config_wlan) /
 983                                 sizeof(struct ath10k_tgt_pipe_cfg);
 984         cfg.ce_tgt_cfg = (struct ath10k_tgt_pipe_cfg *)
 985                 &tgt_cfg;
 986         cfg.num_ce_svc_pipe_cfg = sizeof(target_service_to_ce_map_wlan) /
 987                                   sizeof(struct ath10k_svc_pipe_cfg);
 988         cfg.ce_svc_cfg = (struct ath10k_svc_pipe_cfg *)
 989                 &target_service_to_ce_map_wlan;
 990         cfg.num_shadow_reg_cfg = sizeof(target_shadow_reg_cfg_map) /
 991                                         sizeof(struct ath10k_shadow_reg_cfg);
 992         cfg.shadow_reg_cfg = (struct ath10k_shadow_reg_cfg *)
 993                 &target_shadow_reg_cfg_map;
 994
 995         switch (fw_mode) {
 996         case ATH10K_FIRMWARE_MODE_NORMAL:
 997                 mode = QMI_WLFW_MISSION_V01;
 998                 break;
 999         case ATH10K_FIRMWARE_MODE_UTF:
1000                 mode = QMI_WLFW_FTM_V01;
1001                 break;
1002         default:
1003                 ath10k_err(ar, "invalid firmware mode %d\n", fw_mode);
1004                 return -EINVAL;
1005         }
1006
1007         return ath10k_qmi_wlan_enable(ar, &cfg, mode,
1008                                        NULL);
1009 }
1010
1011 static void ath10k_snoc_wlan_disable(struct ath10k *ar)
1012 {
1013         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1014
1015         /* If both ATH10K_FLAG_CRASH_FLUSH and ATH10K_SNOC_FLAG_RECOVERY
1016          * flags are not set, it means that the driver has restarted
1017          * due to a crash inject via debugfs. In this case, the driver
1018          * needs to restart the firmware and hence send qmi wlan disable,
1019          * during the driver restart sequence.
1020          */
1021         if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags) ||
1022             !test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags))
1023                 ath10k_qmi_wlan_disable(ar);
1024 }
1025
1026 static void ath10k_snoc_hif_power_down(struct ath10k *ar)
1027 {
1028         ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
1029
1030         ath10k_snoc_wlan_disable(ar);
1031         ath10k_ce_free_rri(ar);
1032 }
1033
1034 static int ath10k_snoc_hif_power_up(struct ath10k *ar,
1035                                     enum ath10k_firmware_mode fw_mode)
1036 {
1037         int ret;
1038
1039         ath10k_dbg(ar, ATH10K_DBG_SNOC, "%s:WCN3990 driver state = %d\n",
1040                    __func__, ar->state);
1041
1042         ret = ath10k_snoc_wlan_enable(ar, fw_mode);
1043         if (ret) {
1044                 ath10k_err(ar, "failed to enable wcn3990: %d\n", ret);
1045                 return ret;
1046         }
1047
1048         ath10k_ce_alloc_rri(ar);
1049
1050         ret = ath10k_snoc_init_pipes(ar);
1051         if (ret) {
1052                 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
1053                 goto err_wlan_enable;
1054         }
1055
1056         return 0;
1057
1058 err_wlan_enable:
1059         ath10k_snoc_wlan_disable(ar);
1060
1061         return ret;
1062 }
1063
1064 #ifdef CONFIG_PM
1065 static int ath10k_snoc_hif_suspend(struct ath10k *ar)
1066 {
1067         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1068         int ret;
1069
1070         if (!device_may_wakeup(ar->dev))
1071                 return -EPERM;
1072
1073         ret = enable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line);
1074         if (ret) {
1075                 ath10k_err(ar, "failed to enable wakeup irq :%d\n", ret);
1076                 return ret;
1077         }
1078
1079         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device suspended\n");
1080
1081         return ret;
1082 }
1083
1084 static int ath10k_snoc_hif_resume(struct ath10k *ar)
1085 {
1086         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1087         int ret;
1088
1089         if (!device_may_wakeup(ar->dev))
1090                 return -EPERM;
1091
1092         ret = disable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line);
1093         if (ret) {
1094                 ath10k_err(ar, "failed to disable wakeup irq: %d\n", ret);
1095                 return ret;
1096         }
1097
1098         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device resumed\n");
1099
1100         return ret;
1101 }
1102 #endif
1103
1104 static const struct ath10k_hif_ops ath10k_snoc_hif_ops = {
1105         .read32         = ath10k_snoc_read32,
1106         .write32        = ath10k_snoc_write32,
1107         .start          = ath10k_snoc_hif_start,
1108         .stop           = ath10k_snoc_hif_stop,
1109         .map_service_to_pipe    = ath10k_snoc_hif_map_service_to_pipe,
1110         .get_default_pipe       = ath10k_snoc_hif_get_default_pipe,
1111         .power_up               = ath10k_snoc_hif_power_up,
1112         .power_down             = ath10k_snoc_hif_power_down,
1113         .tx_sg                  = ath10k_snoc_hif_tx_sg,
1114         .send_complete_check    = ath10k_snoc_hif_send_complete_check,
1115         .get_free_queue_number  = ath10k_snoc_hif_get_free_queue_number,
1116         .get_target_info        = ath10k_snoc_hif_get_target_info,
1117 #ifdef CONFIG_PM
1118         .suspend                = ath10k_snoc_hif_suspend,
1119         .resume                 = ath10k_snoc_hif_resume,
1120 #endif
1121 };
1122
1123 static const struct ath10k_bus_ops ath10k_snoc_bus_ops = {
1124         .read32         = ath10k_snoc_read32,
1125         .write32        = ath10k_snoc_write32,
1126 };
1127
1128 static int ath10k_snoc_get_ce_id_from_irq(struct ath10k *ar, int irq)
1129 {
1130         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1131         int i;
1132
1133         for (i = 0; i < CE_COUNT_MAX; i++) {
1134                 if (ar_snoc->ce_irqs[i].irq_line == irq)
1135                         return i;
1136         }
1137         ath10k_err(ar, "No matching CE id for irq %d\n", irq);
1138
1139         return -EINVAL;
1140 }
1141
1142 static irqreturn_t ath10k_snoc_per_engine_handler(int irq, void *arg)
1143 {
1144         struct ath10k *ar = arg;
1145         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1146         int ce_id = ath10k_snoc_get_ce_id_from_irq(ar, irq);
1147
1148         if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_snoc->pipe_info)) {
1149                 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq,
1150                             ce_id);
1151                 return IRQ_HANDLED;
1152         }
1153
1154         ath10k_snoc_irq_disable(ar);
1155         napi_schedule(&ar->napi);
1156
1157         return IRQ_HANDLED;
1158 }
1159
1160 static int ath10k_snoc_napi_poll(struct napi_struct *ctx, int budget)
1161 {
1162         struct ath10k *ar = container_of(ctx, struct ath10k, napi);
1163         int done = 0;
1164
1165         if (test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags)) {
1166                 napi_complete(ctx);
1167                 return done;
1168         }
1169
1170         ath10k_ce_per_engine_service_any(ar);
1171         done = ath10k_htt_txrx_compl_task(ar, budget);
1172
1173         if (done < budget) {
1174                 napi_complete(ctx);
1175                 ath10k_snoc_irq_enable(ar);
1176         }
1177
1178         return done;
1179 }
1180
1181 static void ath10k_snoc_init_napi(struct ath10k *ar)
1182 {
1183         netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_snoc_napi_poll,
1184                        ATH10K_NAPI_BUDGET);
1185 }
1186
1187 static int ath10k_snoc_request_irq(struct ath10k *ar)
1188 {
1189         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1190         int irqflags = IRQF_TRIGGER_RISING;
1191         int ret, id;
1192
1193         for (id = 0; id < CE_COUNT_MAX; id++) {
1194                 ret = request_irq(ar_snoc->ce_irqs[id].irq_line,
1195                                   ath10k_snoc_per_engine_handler,
1196                                   irqflags, ce_name[id], ar);
1197                 if (ret) {
1198                         ath10k_err(ar,
1199                                    "failed to register IRQ handler for CE %d: %d",
1200                                    id, ret);
1201                         goto err_irq;
1202                 }
1203         }
1204
1205         return 0;
1206
1207 err_irq:
1208         for (id -= 1; id >= 0; id--)
1209                 free_irq(ar_snoc->ce_irqs[id].irq_line, ar);
1210
1211         return ret;
1212 }
1213
1214 static void ath10k_snoc_free_irq(struct ath10k *ar)
1215 {
1216         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1217         int id;
1218
1219         for (id = 0; id < CE_COUNT_MAX; id++)
1220                 free_irq(ar_snoc->ce_irqs[id].irq_line, ar);
1221 }
1222
1223 static int ath10k_snoc_resource_init(struct ath10k *ar)
1224 {
1225         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1226         struct platform_device *pdev;
1227         struct resource *res;
1228         int i, ret = 0;
1229
1230         pdev = ar_snoc->dev;
1231         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "membase");
1232         if (!res) {
1233                 ath10k_err(ar, "Memory base not found in DT\n");
1234                 return -EINVAL;
1235         }
1236
1237         ar_snoc->mem_pa = res->start;
1238         ar_snoc->mem = devm_ioremap(&pdev->dev, ar_snoc->mem_pa,
1239                                     resource_size(res));
1240         if (!ar_snoc->mem) {
1241                 ath10k_err(ar, "Memory base ioremap failed with physical address %pa\n",
1242                            &ar_snoc->mem_pa);
1243                 return -EINVAL;
1244         }
1245
1246         for (i = 0; i < CE_COUNT; i++) {
1247                 res = platform_get_resource(ar_snoc->dev, IORESOURCE_IRQ, i);
1248                 if (!res) {
1249                         ath10k_err(ar, "failed to get IRQ%d\n", i);
1250                         ret = -ENODEV;
1251                         goto out;
1252                 }
1253                 ar_snoc->ce_irqs[i].irq_line = res->start;
1254         }
1255
1256 out:
1257         return ret;
1258 }
1259
1260 int ath10k_snoc_fw_indication(struct ath10k *ar, u64 type)
1261 {
1262         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1263         struct ath10k_bus_params bus_params;
1264         int ret;
1265
1266         if (test_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags))
1267                 return 0;
1268
1269         switch (type) {
1270         case ATH10K_QMI_EVENT_FW_READY_IND:
1271                 if (test_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags)) {
1272                         queue_work(ar->workqueue, &ar->restart_work);
1273                         break;
1274                 }
1275
1276                 bus_params.dev_type = ATH10K_DEV_TYPE_LL;
1277                 bus_params.chip_id = ar_snoc->target_info.soc_version;
1278                 ret = ath10k_core_register(ar, &bus_params);
1279                 if (ret) {
1280                         ath10k_err(ar, "Failed to register driver core: %d\n",
1281                                    ret);
1282                         return ret;
1283                 }
1284                 set_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags);
1285                 break;
1286         case ATH10K_QMI_EVENT_FW_DOWN_IND:
1287                 set_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags);
1288                 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
1289                 break;
1290         default:
1291                 ath10k_err(ar, "invalid fw indication: %llx\n", type);
1292                 return -EINVAL;
1293         }
1294
1295         return 0;
1296 }
1297
1298 static int ath10k_snoc_setup_resource(struct ath10k *ar)
1299 {
1300         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1301         struct ath10k_ce *ce = ath10k_ce_priv(ar);
1302         struct ath10k_snoc_pipe *pipe;
1303         int i, ret;
1304
1305         timer_setup(&ar_snoc->rx_post_retry, ath10k_snoc_rx_replenish_retry, 0);
1306         spin_lock_init(&ce->ce_lock);
1307         for (i = 0; i < CE_COUNT; i++) {
1308                 pipe = &ar_snoc->pipe_info[i];
1309                 pipe->ce_hdl = &ce->ce_states[i];
1310                 pipe->pipe_num = i;
1311                 pipe->hif_ce_state = ar;
1312
1313                 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
1314                 if (ret) {
1315                         ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
1316                                    i, ret);
1317                         return ret;
1318                 }
1319
1320                 pipe->buf_sz = host_ce_config_wlan[i].src_sz_max;
1321         }
1322         ath10k_snoc_init_napi(ar);
1323
1324         return 0;
1325 }
1326
1327 static void ath10k_snoc_release_resource(struct ath10k *ar)
1328 {
1329         int i;
1330
1331         netif_napi_del(&ar->napi);
1332         for (i = 0; i < CE_COUNT; i++)
1333                 ath10k_ce_free_pipe(ar, i);
1334 }
1335
1336 static int ath10k_get_vreg_info(struct ath10k *ar, struct device *dev,
1337                                 struct ath10k_vreg_info *vreg_info)
1338 {
1339         struct regulator *reg;
1340         int ret = 0;
1341
1342         reg = devm_regulator_get_optional(dev, vreg_info->name);
1343
1344         if (IS_ERR(reg)) {
1345                 ret = PTR_ERR(reg);
1346
1347                 if (ret  == -EPROBE_DEFER) {
1348                         ath10k_err(ar, "EPROBE_DEFER for regulator: %s\n",
1349                                    vreg_info->name);
1350                         return ret;
1351                 }
1352                 if (vreg_info->required) {
1353                         ath10k_err(ar, "Regulator %s doesn't exist: %d\n",
1354                                    vreg_info->name, ret);
1355                         return ret;
1356                 }
1357                 ath10k_dbg(ar, ATH10K_DBG_SNOC,
1358                            "Optional regulator %s doesn't exist: %d\n",
1359                            vreg_info->name, ret);
1360                 goto done;
1361         }
1362
1363         vreg_info->reg = reg;
1364
1365 done:
1366         ath10k_dbg(ar, ATH10K_DBG_SNOC,
1367                    "snog vreg %s min_v %u max_v %u load_ua %u settle_delay %lu\n",
1368                    vreg_info->name, vreg_info->min_v, vreg_info->max_v,
1369                    vreg_info->load_ua, vreg_info->settle_delay);
1370
1371         return 0;
1372 }
1373
1374 static int ath10k_get_clk_info(struct ath10k *ar, struct device *dev,
1375                                struct ath10k_clk_info *clk_info)
1376 {
1377         struct clk *handle;
1378         int ret = 0;
1379
1380         handle = devm_clk_get(dev, clk_info->name);
1381         if (IS_ERR(handle)) {
1382                 ret = PTR_ERR(handle);
1383                 if (clk_info->required) {
1384                         ath10k_err(ar, "snoc clock %s isn't available: %d\n",
1385                                    clk_info->name, ret);
1386                         return ret;
1387                 }
1388                 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc ignoring clock %s: %d\n",
1389                            clk_info->name,
1390                            ret);
1391                 return 0;
1392         }
1393
1394         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc clock %s freq %u\n",
1395                    clk_info->name, clk_info->freq);
1396
1397         clk_info->handle = handle;
1398
1399         return ret;
1400 }
1401
1402 static int __ath10k_snoc_vreg_on(struct ath10k *ar,
1403                                  struct ath10k_vreg_info *vreg_info)
1404 {
1405         int ret;
1406
1407         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc regulator %s being enabled\n",
1408                    vreg_info->name);
1409
1410         ret = regulator_set_voltage(vreg_info->reg, vreg_info->min_v,
1411                                     vreg_info->max_v);
1412         if (ret) {
1413                 ath10k_err(ar,
1414                            "failed to set regulator %s voltage-min: %d voltage-max: %d\n",
1415                            vreg_info->name, vreg_info->min_v, vreg_info->max_v);
1416                 return ret;
1417         }
1418
1419         if (vreg_info->load_ua) {
1420                 ret = regulator_set_load(vreg_info->reg, vreg_info->load_ua);
1421                 if (ret < 0) {
1422                         ath10k_err(ar, "failed to set regulator %s load: %d\n",
1423                                    vreg_info->name, vreg_info->load_ua);
1424                         goto err_set_load;
1425                 }
1426         }
1427
1428         ret = regulator_enable(vreg_info->reg);
1429         if (ret) {
1430                 ath10k_err(ar, "failed to enable regulator %s\n",
1431                            vreg_info->name);
1432                 goto err_enable;
1433         }
1434
1435         if (vreg_info->settle_delay)
1436                 udelay(vreg_info->settle_delay);
1437
1438         return 0;
1439
1440 err_enable:
1441         regulator_set_load(vreg_info->reg, 0);
1442 err_set_load:
1443         regulator_set_voltage(vreg_info->reg, 0, vreg_info->max_v);
1444
1445         return ret;
1446 }
1447
1448 static int __ath10k_snoc_vreg_off(struct ath10k *ar,
1449                                   struct ath10k_vreg_info *vreg_info)
1450 {
1451         int ret;
1452
1453         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc regulator %s being disabled\n",
1454                    vreg_info->name);
1455
1456         ret = regulator_disable(vreg_info->reg);
1457         if (ret)
1458                 ath10k_err(ar, "failed to disable regulator %s\n",
1459                            vreg_info->name);
1460
1461         ret = regulator_set_load(vreg_info->reg, 0);
1462         if (ret < 0)
1463                 ath10k_err(ar, "failed to set load %s\n", vreg_info->name);
1464
1465         ret = regulator_set_voltage(vreg_info->reg, 0, vreg_info->max_v);
1466         if (ret)
1467                 ath10k_err(ar, "failed to set voltage %s\n", vreg_info->name);
1468
1469         return ret;
1470 }
1471
1472 static int ath10k_snoc_vreg_on(struct ath10k *ar)
1473 {
1474         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1475         struct ath10k_vreg_info *vreg_info;
1476         int ret = 0;
1477         int i;
1478
1479         for (i = 0; i < ARRAY_SIZE(vreg_cfg); i++) {
1480                 vreg_info = &ar_snoc->vreg[i];
1481
1482                 if (!vreg_info->reg)
1483                         continue;
1484
1485                 ret = __ath10k_snoc_vreg_on(ar, vreg_info);
1486                 if (ret)
1487                         goto err_reg_config;
1488         }
1489
1490         return 0;
1491
1492 err_reg_config:
1493         for (i = i - 1; i >= 0; i--) {
1494                 vreg_info = &ar_snoc->vreg[i];
1495
1496                 if (!vreg_info->reg)
1497                         continue;
1498
1499                 __ath10k_snoc_vreg_off(ar, vreg_info);
1500         }
1501
1502         return ret;
1503 }
1504
1505 static int ath10k_snoc_vreg_off(struct ath10k *ar)
1506 {
1507         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1508         struct ath10k_vreg_info *vreg_info;
1509         int ret = 0;
1510         int i;
1511
1512         for (i = ARRAY_SIZE(vreg_cfg) - 1; i >= 0; i--) {
1513                 vreg_info = &ar_snoc->vreg[i];
1514
1515                 if (!vreg_info->reg)
1516                         continue;
1517
1518                 ret = __ath10k_snoc_vreg_off(ar, vreg_info);
1519         }
1520
1521         return ret;
1522 }
1523
1524 static int ath10k_snoc_clk_init(struct ath10k *ar)
1525 {
1526         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1527         struct ath10k_clk_info *clk_info;
1528         int ret = 0;
1529         int i;
1530
1531         for (i = 0; i < ARRAY_SIZE(clk_cfg); i++) {
1532                 clk_info = &ar_snoc->clk[i];
1533
1534                 if (!clk_info->handle)
1535                         continue;
1536
1537                 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc clock %s being enabled\n",
1538                            clk_info->name);
1539
1540                 if (clk_info->freq) {
1541                         ret = clk_set_rate(clk_info->handle, clk_info->freq);
1542
1543                         if (ret) {
1544                                 ath10k_err(ar, "failed to set clock %s freq %u\n",
1545                                            clk_info->name, clk_info->freq);
1546                                 goto err_clock_config;
1547                         }
1548                 }
1549
1550                 ret = clk_prepare_enable(clk_info->handle);
1551                 if (ret) {
1552                         ath10k_err(ar, "failed to enable clock %s\n",
1553                                    clk_info->name);
1554                         goto err_clock_config;
1555                 }
1556         }
1557
1558         return 0;
1559
1560 err_clock_config:
1561         for (i = i - 1; i >= 0; i--) {
1562                 clk_info = &ar_snoc->clk[i];
1563
1564                 if (!clk_info->handle)
1565                         continue;
1566
1567                 clk_disable_unprepare(clk_info->handle);
1568         }
1569
1570         return ret;
1571 }
1572
1573 static int ath10k_snoc_clk_deinit(struct ath10k *ar)
1574 {
1575         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1576         struct ath10k_clk_info *clk_info;
1577         int i;
1578
1579         for (i = 0; i < ARRAY_SIZE(clk_cfg); i++) {
1580                 clk_info = &ar_snoc->clk[i];
1581
1582                 if (!clk_info->handle)
1583                         continue;
1584
1585                 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc clock %s being disabled\n",
1586                            clk_info->name);
1587
1588                 clk_disable_unprepare(clk_info->handle);
1589         }
1590
1591         return 0;
1592 }
1593
1594 static int ath10k_hw_power_on(struct ath10k *ar)
1595 {
1596         int ret;
1597
1598         ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power on\n");
1599
1600         ret = ath10k_snoc_vreg_on(ar);
1601         if (ret)
1602                 return ret;
1603
1604         ret = ath10k_snoc_clk_init(ar);
1605         if (ret)
1606                 goto vreg_off;
1607
1608         return ret;
1609
1610 vreg_off:
1611         ath10k_snoc_vreg_off(ar);
1612         return ret;
1613 }
1614
1615 static int ath10k_hw_power_off(struct ath10k *ar)
1616 {
1617         int ret;
1618
1619         ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power off\n");
1620
1621         ath10k_snoc_clk_deinit(ar);
1622
1623         ret = ath10k_snoc_vreg_off(ar);
1624
1625         return ret;
1626 }
1627
1628 static const struct of_device_id ath10k_snoc_dt_match[] = {
1629         { .compatible = "qcom,wcn3990-wifi",
1630          .data = &drv_priv,
1631         },
1632         { }
1633 };
1634 MODULE_DEVICE_TABLE(of, ath10k_snoc_dt_match);
1635
1636 static int ath10k_snoc_probe(struct platform_device *pdev)
1637 {
1638         const struct ath10k_snoc_drv_priv *drv_data;
1639         const struct of_device_id *of_id;
1640         struct ath10k_snoc *ar_snoc;
1641         struct device *dev;
1642         struct ath10k *ar;
1643         u32 msa_size;
1644         int ret;
1645         u32 i;
1646
1647         of_id = of_match_device(ath10k_snoc_dt_match, &pdev->dev);
1648         if (!of_id) {
1649                 dev_err(&pdev->dev, "failed to find matching device tree id\n");
1650                 return -EINVAL;
1651         }
1652
1653         drv_data = of_id->data;
1654         dev = &pdev->dev;
1655
1656         ret = dma_set_mask_and_coherent(dev, drv_data->dma_mask);
1657         if (ret) {
1658                 dev_err(dev, "failed to set dma mask: %d", ret);
1659                 return ret;
1660         }
1661
1662         ar = ath10k_core_create(sizeof(*ar_snoc), dev, ATH10K_BUS_SNOC,
1663                                 drv_data->hw_rev, &ath10k_snoc_hif_ops);
1664         if (!ar) {
1665                 dev_err(dev, "failed to allocate core\n");
1666                 return -ENOMEM;
1667         }
1668
1669         ar_snoc = ath10k_snoc_priv(ar);
1670         ar_snoc->dev = pdev;
1671         platform_set_drvdata(pdev, ar);
1672         ar_snoc->ar = ar;
1673         ar_snoc->ce.bus_ops = &ath10k_snoc_bus_ops;
1674         ar->ce_priv = &ar_snoc->ce;
1675         msa_size = drv_data->msa_size;
1676
1677         ret = ath10k_snoc_resource_init(ar);
1678         if (ret) {
1679                 ath10k_warn(ar, "failed to initialize resource: %d\n", ret);
1680                 goto err_core_destroy;
1681         }
1682
1683         ret = ath10k_snoc_setup_resource(ar);
1684         if (ret) {
1685                 ath10k_warn(ar, "failed to setup resource: %d\n", ret);
1686                 goto err_core_destroy;
1687         }
1688         ret = ath10k_snoc_request_irq(ar);
1689         if (ret) {
1690                 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
1691                 goto err_release_resource;
1692         }
1693
1694         ar_snoc->vreg = vreg_cfg;
1695         for (i = 0; i < ARRAY_SIZE(vreg_cfg); i++) {
1696                 ret = ath10k_get_vreg_info(ar, dev, &ar_snoc->vreg[i]);
1697                 if (ret)
1698                         goto err_free_irq;
1699         }
1700
1701         ar_snoc->clk = clk_cfg;
1702         for (i = 0; i < ARRAY_SIZE(clk_cfg); i++) {
1703                 ret = ath10k_get_clk_info(ar, dev, &ar_snoc->clk[i]);
1704                 if (ret)
1705                         goto err_free_irq;
1706         }
1707
1708         ret = ath10k_hw_power_on(ar);
1709         if (ret) {
1710                 ath10k_err(ar, "failed to power on device: %d\n", ret);
1711                 goto err_free_irq;
1712         }
1713
1714         ret = ath10k_qmi_init(ar, msa_size);
1715         if (ret) {
1716                 ath10k_warn(ar, "failed to register wlfw qmi client: %d\n", ret);
1717                 goto err_core_destroy;
1718         }
1719
1720         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc probe\n");
1721
1722         return 0;
1723
1724 err_free_irq:
1725         ath10k_snoc_free_irq(ar);
1726
1727 err_release_resource:
1728         ath10k_snoc_release_resource(ar);
1729
1730 err_core_destroy:
1731         ath10k_core_destroy(ar);
1732
1733         return ret;
1734 }
1735
1736 static int ath10k_snoc_remove(struct platform_device *pdev)
1737 {
1738         struct ath10k *ar = platform_get_drvdata(pdev);
1739         struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1740
1741         ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc remove\n");
1742
1743         reinit_completion(&ar->driver_recovery);
1744
1745         if (test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags))
1746                 wait_for_completion_timeout(&ar->driver_recovery, 3 * HZ);
1747
1748         set_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags);
1749
1750         ath10k_core_unregister(ar);
1751         ath10k_hw_power_off(ar);
1752         ath10k_snoc_free_irq(ar);
1753         ath10k_snoc_release_resource(ar);
1754         ath10k_qmi_deinit(ar);
1755         ath10k_core_destroy(ar);
1756
1757         return 0;
1758 }
1759
1760 static struct platform_driver ath10k_snoc_driver = {
1761         .probe  = ath10k_snoc_probe,
1762         .remove = ath10k_snoc_remove,
1763         .driver = {
1764                 .name   = "ath10k_snoc",
1765                 .of_match_table = ath10k_snoc_dt_match,
1766         },
1767 };
1768 module_platform_driver(ath10k_snoc_driver);
1769
1770 MODULE_AUTHOR("Qualcomm");
1771 MODULE_LICENSE("Dual BSD/GPL");
1772 MODULE_DESCRIPTION("Driver support for Atheros WCN3990 SNOC devices");