1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2004-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2012,2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2016-2017 Erik Stromdahl <erik.stromdahl@gmail.com>
8 #include <linux/module.h>
9 #include <linux/mmc/card.h>
10 #include <linux/mmc/mmc.h>
11 #include <linux/mmc/host.h>
12 #include <linux/mmc/sdio_func.h>
13 #include <linux/mmc/sdio_ids.h>
14 #include <linux/mmc/sdio.h>
15 #include <linux/mmc/sd.h>
16 #include <linux/bitfield.h>
23 #include "targaddrs.h"
27 /* inlined helper functions */
29 static inline int ath10k_sdio_calc_txrx_padded_len(struct ath10k_sdio *ar_sdio,
32 return __ALIGN_MASK((len), ar_sdio->mbox_info.block_mask);
35 static inline enum ath10k_htc_ep_id pipe_id_to_eid(u8 pipe_id)
37 return (enum ath10k_htc_ep_id)pipe_id;
40 static inline void ath10k_sdio_mbox_free_rx_pkt(struct ath10k_sdio_rx_data *pkt)
42 dev_kfree_skb(pkt->skb);
46 pkt->trailer_only = false;
49 static inline int ath10k_sdio_mbox_alloc_rx_pkt(struct ath10k_sdio_rx_data *pkt,
50 size_t act_len, size_t full_len,
54 pkt->skb = dev_alloc_skb(full_len);
58 pkt->act_len = act_len;
59 pkt->alloc_len = full_len;
60 pkt->part_of_bundle = part_of_bundle;
61 pkt->last_in_bundle = last_in_bundle;
62 pkt->trailer_only = false;
67 static inline bool is_trailer_only_msg(struct ath10k_sdio_rx_data *pkt)
69 bool trailer_only = false;
70 struct ath10k_htc_hdr *htc_hdr =
71 (struct ath10k_htc_hdr *)pkt->skb->data;
72 u16 len = __le16_to_cpu(htc_hdr->len);
74 if (len == htc_hdr->trailer_len)
80 /* sdio/mmc functions */
82 static inline void ath10k_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw,
86 *arg = FIELD_PREP(BIT(31), write) |
87 FIELD_PREP(BIT(27), raw) |
88 FIELD_PREP(BIT(26), 1) |
89 FIELD_PREP(GENMASK(25, 9), address) |
90 FIELD_PREP(BIT(8), 1) |
91 FIELD_PREP(GENMASK(7, 0), val);
94 static int ath10k_sdio_func0_cmd52_wr_byte(struct mmc_card *card,
98 struct mmc_command io_cmd;
100 memset(&io_cmd, 0, sizeof(io_cmd));
101 ath10k_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte);
102 io_cmd.opcode = SD_IO_RW_DIRECT;
103 io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
105 return mmc_wait_for_cmd(card->host, &io_cmd, 0);
108 static int ath10k_sdio_func0_cmd52_rd_byte(struct mmc_card *card,
109 unsigned int address,
112 struct mmc_command io_cmd;
115 memset(&io_cmd, 0, sizeof(io_cmd));
116 ath10k_sdio_set_cmd52_arg(&io_cmd.arg, 0, 0, address, 0);
117 io_cmd.opcode = SD_IO_RW_DIRECT;
118 io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
120 ret = mmc_wait_for_cmd(card->host, &io_cmd, 0);
122 *byte = io_cmd.resp[0];
127 static int ath10k_sdio_config(struct ath10k *ar)
129 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
130 struct sdio_func *func = ar_sdio->func;
131 unsigned char byte, asyncintdelay = 2;
134 ath10k_dbg(ar, ATH10K_DBG_BOOT, "sdio configuration\n");
136 sdio_claim_host(func);
139 ret = ath10k_sdio_func0_cmd52_rd_byte(func->card,
140 SDIO_CCCR_DRIVE_STRENGTH,
143 byte &= ~ATH10K_SDIO_DRIVE_DTSX_MASK;
144 byte |= FIELD_PREP(ATH10K_SDIO_DRIVE_DTSX_MASK,
145 ATH10K_SDIO_DRIVE_DTSX_TYPE_D);
147 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
148 SDIO_CCCR_DRIVE_STRENGTH,
152 ret = ath10k_sdio_func0_cmd52_rd_byte(
154 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR,
157 byte |= (CCCR_SDIO_DRIVER_STRENGTH_ENABLE_A |
158 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_C |
159 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_D);
161 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
162 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR,
165 ath10k_warn(ar, "failed to enable driver strength: %d\n", ret);
170 ret = ath10k_sdio_func0_cmd52_rd_byte(func->card,
171 CCCR_SDIO_IRQ_MODE_REG_SDIO3,
174 byte |= SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_SDIO3;
176 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
177 CCCR_SDIO_IRQ_MODE_REG_SDIO3,
180 ath10k_warn(ar, "failed to enable 4-bit async irq mode: %d\n",
186 ret = ath10k_sdio_func0_cmd52_rd_byte(func->card,
187 CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS,
190 byte &= ~CCCR_SDIO_ASYNC_INT_DELAY_MASK;
191 byte |= FIELD_PREP(CCCR_SDIO_ASYNC_INT_DELAY_MASK, asyncintdelay);
193 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
194 CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS,
197 /* give us some time to enable, in ms */
198 func->enable_timeout = 100;
200 ret = sdio_set_block_size(func, ar_sdio->mbox_info.block_size);
202 ath10k_warn(ar, "failed to set sdio block size to %d: %d\n",
203 ar_sdio->mbox_info.block_size, ret);
208 sdio_release_host(func);
212 static int ath10k_sdio_write32(struct ath10k *ar, u32 addr, u32 val)
214 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
215 struct sdio_func *func = ar_sdio->func;
218 sdio_claim_host(func);
220 sdio_writel(func, val, addr, &ret);
222 ath10k_warn(ar, "failed to write 0x%x to address 0x%x: %d\n",
227 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio write32 addr 0x%x val 0x%x\n",
231 sdio_release_host(func);
236 static int ath10k_sdio_writesb32(struct ath10k *ar, u32 addr, u32 val)
238 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
239 struct sdio_func *func = ar_sdio->func;
243 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
247 *buf = cpu_to_le32(val);
249 sdio_claim_host(func);
251 ret = sdio_writesb(func, addr, buf, sizeof(*buf));
253 ath10k_warn(ar, "failed to write value 0x%x to fixed sb address 0x%x: %d\n",
258 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio writesb32 addr 0x%x val 0x%x\n",
262 sdio_release_host(func);
269 static int ath10k_sdio_read32(struct ath10k *ar, u32 addr, u32 *val)
271 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
272 struct sdio_func *func = ar_sdio->func;
275 sdio_claim_host(func);
276 *val = sdio_readl(func, addr, &ret);
278 ath10k_warn(ar, "failed to read from address 0x%x: %d\n",
283 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio read32 addr 0x%x val 0x%x\n",
287 sdio_release_host(func);
292 static int ath10k_sdio_read(struct ath10k *ar, u32 addr, void *buf, size_t len)
294 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
295 struct sdio_func *func = ar_sdio->func;
298 sdio_claim_host(func);
300 ret = sdio_memcpy_fromio(func, buf, addr, len);
302 ath10k_warn(ar, "failed to read from address 0x%x: %d\n",
307 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio read addr 0x%x buf 0x%p len %zu\n",
309 ath10k_dbg_dump(ar, ATH10K_DBG_SDIO_DUMP, NULL, "sdio read ", buf, len);
312 sdio_release_host(func);
317 static int ath10k_sdio_write(struct ath10k *ar, u32 addr, const void *buf, size_t len)
319 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
320 struct sdio_func *func = ar_sdio->func;
323 sdio_claim_host(func);
325 /* For some reason toio() doesn't have const for the buffer, need
326 * an ugly hack to workaround that.
328 ret = sdio_memcpy_toio(func, addr, (void *)buf, len);
330 ath10k_warn(ar, "failed to write to address 0x%x: %d\n",
335 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio write addr 0x%x buf 0x%p len %zu\n",
337 ath10k_dbg_dump(ar, ATH10K_DBG_SDIO_DUMP, NULL, "sdio write ", buf, len);
340 sdio_release_host(func);
345 static int ath10k_sdio_readsb(struct ath10k *ar, u32 addr, void *buf, size_t len)
347 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
348 struct sdio_func *func = ar_sdio->func;
351 sdio_claim_host(func);
353 len = round_down(len, ar_sdio->mbox_info.block_size);
355 ret = sdio_readsb(func, buf, addr, len);
357 ath10k_warn(ar, "failed to read from fixed (sb) address 0x%x: %d\n",
362 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio readsb addr 0x%x buf 0x%p len %zu\n",
364 ath10k_dbg_dump(ar, ATH10K_DBG_SDIO_DUMP, NULL, "sdio readsb ", buf, len);
367 sdio_release_host(func);
372 /* HIF mbox functions */
374 static int ath10k_sdio_mbox_rx_process_packet(struct ath10k *ar,
375 struct ath10k_sdio_rx_data *pkt,
379 struct ath10k_htc *htc = &ar->htc;
380 struct sk_buff *skb = pkt->skb;
381 struct ath10k_htc_hdr *htc_hdr = (struct ath10k_htc_hdr *)skb->data;
382 bool trailer_present = htc_hdr->flags & ATH10K_HTC_FLAG_TRAILER_PRESENT;
383 enum ath10k_htc_ep_id eid;
388 payload_len = le16_to_cpu(htc_hdr->len);
389 skb->len = payload_len + sizeof(struct ath10k_htc_hdr);
391 if (trailer_present) {
392 trailer = skb->data + sizeof(*htc_hdr) +
393 payload_len - htc_hdr->trailer_len;
395 eid = pipe_id_to_eid(htc_hdr->eid);
397 ret = ath10k_htc_process_trailer(htc,
399 htc_hdr->trailer_len,
406 if (is_trailer_only_msg(pkt))
407 pkt->trailer_only = true;
409 skb_trim(skb, skb->len - htc_hdr->trailer_len);
412 skb_pull(skb, sizeof(*htc_hdr));
417 static int ath10k_sdio_mbox_rx_process_packets(struct ath10k *ar,
421 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
422 struct ath10k_htc *htc = &ar->htc;
423 struct ath10k_sdio_rx_data *pkt;
424 struct ath10k_htc_ep *ep;
425 enum ath10k_htc_ep_id id;
426 int ret, i, *n_lookahead_local;
427 u32 *lookaheads_local;
428 int lookahead_idx = 0;
430 for (i = 0; i < ar_sdio->n_rx_pkts; i++) {
431 lookaheads_local = lookaheads;
432 n_lookahead_local = n_lookahead;
434 id = ((struct ath10k_htc_hdr *)
435 &lookaheads[lookahead_idx++])->eid;
437 if (id >= ATH10K_HTC_EP_COUNT) {
438 ath10k_warn(ar, "invalid endpoint in look-ahead: %d\n",
444 ep = &htc->endpoint[id];
446 if (ep->service_id == 0) {
447 ath10k_warn(ar, "ep %d is not connected\n", id);
452 pkt = &ar_sdio->rx_pkts[i];
454 if (pkt->part_of_bundle && !pkt->last_in_bundle) {
455 /* Only read lookahead's from RX trailers
456 * for the last packet in a bundle.
459 lookaheads_local = NULL;
460 n_lookahead_local = NULL;
463 ret = ath10k_sdio_mbox_rx_process_packet(ar,
470 if (!pkt->trailer_only)
471 ep->ep_ops.ep_rx_complete(ar_sdio->ar, pkt->skb);
475 /* The RX complete handler now owns the skb...*/
483 /* Free all packets that was not passed on to the RX completion
486 for (; i < ar_sdio->n_rx_pkts; i++)
487 ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]);
492 static int ath10k_sdio_mbox_alloc_pkt_bundle(struct ath10k *ar,
493 struct ath10k_sdio_rx_data *rx_pkts,
494 struct ath10k_htc_hdr *htc_hdr,
495 size_t full_len, size_t act_len,
500 *bndl_cnt = FIELD_GET(ATH10K_HTC_FLAG_BUNDLE_MASK, htc_hdr->flags);
502 if (*bndl_cnt > HTC_HOST_MAX_MSG_PER_RX_BUNDLE) {
504 "HTC bundle length %u exceeds maximum %u\n",
505 le16_to_cpu(htc_hdr->len),
506 HTC_HOST_MAX_MSG_PER_RX_BUNDLE);
510 /* Allocate bndl_cnt extra skb's for the bundle.
511 * The package containing the
512 * ATH10K_HTC_FLAG_BUNDLE_MASK flag is not included
513 * in bndl_cnt. The skb for that packet will be
514 * allocated separately.
516 for (i = 0; i < *bndl_cnt; i++) {
517 ret = ath10k_sdio_mbox_alloc_rx_pkt(&rx_pkts[i],
529 static int ath10k_sdio_mbox_rx_alloc(struct ath10k *ar,
530 u32 lookaheads[], int n_lookaheads)
532 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
533 struct ath10k_htc_hdr *htc_hdr;
534 size_t full_len, act_len;
538 if (n_lookaheads > ATH10K_SDIO_MAX_RX_MSGS) {
540 "the total number of pkgs to be fetched (%u) exceeds maximum %u\n",
542 ATH10K_SDIO_MAX_RX_MSGS);
547 for (i = 0; i < n_lookaheads; i++) {
548 htc_hdr = (struct ath10k_htc_hdr *)&lookaheads[i];
549 last_in_bundle = false;
551 if (le16_to_cpu(htc_hdr->len) >
552 ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH) {
554 "payload length %d exceeds max htc length: %zu\n",
555 le16_to_cpu(htc_hdr->len),
556 ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH);
561 act_len = le16_to_cpu(htc_hdr->len) + sizeof(*htc_hdr);
562 full_len = ath10k_sdio_calc_txrx_padded_len(ar_sdio, act_len);
564 if (full_len > ATH10K_SDIO_MAX_BUFFER_SIZE) {
566 "rx buffer requested with invalid htc_hdr length (%d, 0x%x): %d\n",
567 htc_hdr->eid, htc_hdr->flags,
568 le16_to_cpu(htc_hdr->len));
573 if (htc_hdr->flags & ATH10K_HTC_FLAG_BUNDLE_MASK) {
574 /* HTC header indicates that every packet to follow
575 * has the same padded length so that it can be
576 * optimally fetched as a full bundle.
580 ret = ath10k_sdio_mbox_alloc_pkt_bundle(ar,
581 &ar_sdio->rx_pkts[i],
587 n_lookaheads += bndl_cnt;
589 /*Next buffer will be the last in the bundle */
590 last_in_bundle = true;
593 /* Allocate skb for packet. If the packet had the
594 * ATH10K_HTC_FLAG_BUNDLE_MASK flag set, all bundled
595 * packet skb's have been allocated in the previous step.
597 if (htc_hdr->flags & ATH10K_HTC_FLAGS_RECV_1MORE_BLOCK)
598 full_len += ATH10K_HIF_MBOX_BLOCK_SIZE;
600 ret = ath10k_sdio_mbox_alloc_rx_pkt(&ar_sdio->rx_pkts[i],
607 ar_sdio->n_rx_pkts = i;
612 for (i = 0; i < ATH10K_SDIO_MAX_RX_MSGS; i++) {
613 if (!ar_sdio->rx_pkts[i].alloc_len)
615 ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]);
621 static int ath10k_sdio_mbox_rx_packet(struct ath10k *ar,
622 struct ath10k_sdio_rx_data *pkt)
624 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
625 struct sk_buff *skb = pkt->skb;
628 ret = ath10k_sdio_readsb(ar, ar_sdio->mbox_info.htc_addr,
629 skb->data, pkt->alloc_len);
632 skb_put(skb, pkt->act_len);
637 static int ath10k_sdio_mbox_rx_fetch(struct ath10k *ar)
639 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
642 for (i = 0; i < ar_sdio->n_rx_pkts; i++) {
643 ret = ath10k_sdio_mbox_rx_packet(ar,
644 &ar_sdio->rx_pkts[i]);
652 /* Free all packets that was not successfully fetched. */
653 for (; i < ar_sdio->n_rx_pkts; i++)
654 ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]);
659 /* This is the timeout for mailbox processing done in the sdio irq
660 * handler. The timeout is deliberately set quite high since SDIO dump logs
661 * over serial port can/will add a substantial overhead to the processing
664 #define SDIO_MBOX_PROCESSING_TIMEOUT_HZ (20 * HZ)
666 static int ath10k_sdio_mbox_rxmsg_pending_handler(struct ath10k *ar,
667 u32 msg_lookahead, bool *done)
669 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
670 u32 lookaheads[ATH10K_SDIO_MAX_RX_MSGS];
671 int n_lookaheads = 1;
672 unsigned long timeout;
677 /* Copy the lookahead obtained from the HTC register table into our
678 * temp array as a start value.
680 lookaheads[0] = msg_lookahead;
682 timeout = jiffies + SDIO_MBOX_PROCESSING_TIMEOUT_HZ;
684 /* Try to allocate as many HTC RX packets indicated by
687 ret = ath10k_sdio_mbox_rx_alloc(ar, lookaheads,
692 if (ar_sdio->n_rx_pkts >= 2)
693 /* A recv bundle was detected, force IRQ status
698 ret = ath10k_sdio_mbox_rx_fetch(ar);
700 /* Process fetched packets. This will potentially update
701 * n_lookaheads depending on if the packets contain lookahead
705 ret = ath10k_sdio_mbox_rx_process_packets(ar,
709 if (!n_lookaheads || ret)
712 /* For SYNCH processing, if we get here, we are running
713 * through the loop again due to updated lookaheads. Set
714 * flag that we should re-check IRQ status registers again
715 * before leaving IRQ processing, this can net better
716 * performance in high throughput situations.
719 } while (time_before(jiffies, timeout));
721 if (ret && (ret != -ECANCELED))
722 ath10k_warn(ar, "failed to get pending recv messages: %d\n",
728 static int ath10k_sdio_mbox_proc_dbg_intr(struct ath10k *ar)
733 /* TODO: Add firmware crash handling */
734 ath10k_warn(ar, "firmware crashed\n");
736 /* read counter to clear the interrupt, the debug error interrupt is
739 ret = ath10k_sdio_read32(ar, MBOX_COUNT_DEC_ADDRESS, &val);
741 ath10k_warn(ar, "failed to clear debug interrupt: %d\n", ret);
746 static int ath10k_sdio_mbox_proc_counter_intr(struct ath10k *ar)
748 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
749 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
750 u8 counter_int_status;
753 mutex_lock(&irq_data->mtx);
754 counter_int_status = irq_data->irq_proc_reg->counter_int_status &
755 irq_data->irq_en_reg->cntr_int_status_en;
757 /* NOTE: other modules like GMBOX may use the counter interrupt for
758 * credit flow control on other counters, we only need to check for
759 * the debug assertion counter interrupt.
761 if (counter_int_status & ATH10K_SDIO_TARGET_DEBUG_INTR_MASK)
762 ret = ath10k_sdio_mbox_proc_dbg_intr(ar);
766 mutex_unlock(&irq_data->mtx);
771 static int ath10k_sdio_mbox_proc_err_intr(struct ath10k *ar)
773 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
774 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
778 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio error interrupt\n");
780 error_int_status = irq_data->irq_proc_reg->error_int_status & 0x0F;
781 if (!error_int_status) {
782 ath10k_warn(ar, "invalid error interrupt status: 0x%x\n",
787 ath10k_dbg(ar, ATH10K_DBG_SDIO,
788 "sdio error_int_status 0x%x\n", error_int_status);
790 if (FIELD_GET(MBOX_ERROR_INT_STATUS_WAKEUP_MASK,
792 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio interrupt error wakeup\n");
794 if (FIELD_GET(MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
796 ath10k_warn(ar, "rx underflow interrupt error\n");
798 if (FIELD_GET(MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
800 ath10k_warn(ar, "tx overflow interrupt error\n");
802 /* Clear the interrupt */
803 irq_data->irq_proc_reg->error_int_status &= ~error_int_status;
805 /* set W1C value to clear the interrupt, this hits the register first */
806 ret = ath10k_sdio_writesb32(ar, MBOX_ERROR_INT_STATUS_ADDRESS,
809 ath10k_warn(ar, "unable to write to error int status address: %d\n",
817 static int ath10k_sdio_mbox_proc_cpu_intr(struct ath10k *ar)
819 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
820 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
824 mutex_lock(&irq_data->mtx);
825 cpu_int_status = irq_data->irq_proc_reg->cpu_int_status &
826 irq_data->irq_en_reg->cpu_int_status_en;
827 if (!cpu_int_status) {
828 ath10k_warn(ar, "CPU interrupt status is zero\n");
833 /* Clear the interrupt */
834 irq_data->irq_proc_reg->cpu_int_status &= ~cpu_int_status;
836 /* Set up the register transfer buffer to hit the register 4 times,
837 * this is done to make the access 4-byte aligned to mitigate issues
838 * with host bus interconnects that restrict bus transfer lengths to
839 * be a multiple of 4-bytes.
841 * Set W1C value to clear the interrupt, this hits the register first.
843 ret = ath10k_sdio_writesb32(ar, MBOX_CPU_INT_STATUS_ADDRESS,
846 ath10k_warn(ar, "unable to write to cpu interrupt status address: %d\n",
852 mutex_unlock(&irq_data->mtx);
856 static int ath10k_sdio_mbox_read_int_status(struct ath10k *ar,
860 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
861 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
862 struct ath10k_sdio_irq_proc_regs *irq_proc_reg = irq_data->irq_proc_reg;
863 struct ath10k_sdio_irq_enable_regs *irq_en_reg = irq_data->irq_en_reg;
864 u8 htc_mbox = FIELD_PREP(ATH10K_HTC_MAILBOX_MASK, 1);
867 mutex_lock(&irq_data->mtx);
870 *host_int_status = 0;
872 /* int_status_en is supposed to be non zero, otherwise interrupts
873 * shouldn't be enabled. There is however a short time frame during
874 * initialization between the irq register and int_status_en init
875 * where this can happen.
876 * We silently ignore this condition.
878 if (!irq_en_reg->int_status_en) {
883 /* Read the first sizeof(struct ath10k_irq_proc_registers)
884 * bytes of the HTC register table. This
885 * will yield us the value of different int status
886 * registers and the lookahead registers.
888 ret = ath10k_sdio_read(ar, MBOX_HOST_INT_STATUS_ADDRESS,
889 irq_proc_reg, sizeof(*irq_proc_reg));
893 /* Update only those registers that are enabled */
894 *host_int_status = irq_proc_reg->host_int_status &
895 irq_en_reg->int_status_en;
897 /* Look at mbox status */
898 if (!(*host_int_status & htc_mbox)) {
904 /* Mask out pending mbox value, we use look ahead as
905 * the real flag for mbox processing.
907 *host_int_status &= ~htc_mbox;
908 if (irq_proc_reg->rx_lookahead_valid & htc_mbox) {
909 *lookahead = le32_to_cpu(
910 irq_proc_reg->rx_lookahead[ATH10K_HTC_MAILBOX]);
912 ath10k_warn(ar, "sdio mbox lookahead is zero\n");
916 mutex_unlock(&irq_data->mtx);
920 static int ath10k_sdio_mbox_proc_pending_irqs(struct ath10k *ar,
927 /* NOTE: HIF implementation guarantees that the context of this
928 * call allows us to perform SYNCHRONOUS I/O, that is we can block,
929 * sleep or call any API that can block or switch thread/task
930 * contexts. This is a fully schedulable context.
933 ret = ath10k_sdio_mbox_read_int_status(ar,
941 if (!host_int_status && !lookahead) {
948 ath10k_dbg(ar, ATH10K_DBG_SDIO,
949 "sdio pending mailbox msg lookahead 0x%08x\n",
952 ret = ath10k_sdio_mbox_rxmsg_pending_handler(ar,
959 /* now, handle the rest of the interrupts */
960 ath10k_dbg(ar, ATH10K_DBG_SDIO,
961 "sdio host_int_status 0x%x\n", host_int_status);
963 if (FIELD_GET(MBOX_HOST_INT_STATUS_CPU_MASK, host_int_status)) {
965 ret = ath10k_sdio_mbox_proc_cpu_intr(ar);
970 if (FIELD_GET(MBOX_HOST_INT_STATUS_ERROR_MASK, host_int_status)) {
971 /* Error Interrupt */
972 ret = ath10k_sdio_mbox_proc_err_intr(ar);
977 if (FIELD_GET(MBOX_HOST_INT_STATUS_COUNTER_MASK, host_int_status))
978 /* Counter Interrupt */
979 ret = ath10k_sdio_mbox_proc_counter_intr(ar);
984 /* An optimization to bypass reading the IRQ status registers
985 * unecessarily which can re-wake the target, if upper layers
986 * determine that we are in a low-throughput mode, we can rely on
987 * taking another interrupt rather than re-checking the status
988 * registers which can re-wake the target.
990 * NOTE : for host interfaces that makes use of detecting pending
991 * mbox messages at hif can not use this optimization due to
992 * possible side effects, SPI requires the host to drain all
993 * messages from the mailbox before exiting the ISR routine.
996 ath10k_dbg(ar, ATH10K_DBG_SDIO,
997 "sdio pending irqs done %d status %d",
1003 static void ath10k_sdio_set_mbox_info(struct ath10k *ar)
1005 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1006 struct ath10k_mbox_info *mbox_info = &ar_sdio->mbox_info;
1007 u16 device = ar_sdio->func->device, dev_id_base, dev_id_chiprev;
1009 mbox_info->htc_addr = ATH10K_HIF_MBOX_BASE_ADDR;
1010 mbox_info->block_size = ATH10K_HIF_MBOX_BLOCK_SIZE;
1011 mbox_info->block_mask = ATH10K_HIF_MBOX_BLOCK_SIZE - 1;
1012 mbox_info->gmbox_addr = ATH10K_HIF_GMBOX_BASE_ADDR;
1013 mbox_info->gmbox_sz = ATH10K_HIF_GMBOX_WIDTH;
1015 mbox_info->ext_info[0].htc_ext_addr = ATH10K_HIF_MBOX0_EXT_BASE_ADDR;
1017 dev_id_base = FIELD_GET(QCA_MANUFACTURER_ID_BASE, device);
1018 dev_id_chiprev = FIELD_GET(QCA_MANUFACTURER_ID_REV_MASK, device);
1019 switch (dev_id_base) {
1020 case QCA_MANUFACTURER_ID_AR6005_BASE:
1021 if (dev_id_chiprev < 4)
1022 mbox_info->ext_info[0].htc_ext_sz =
1023 ATH10K_HIF_MBOX0_EXT_WIDTH;
1025 /* from QCA6174 2.0(0x504), the width has been extended
1028 mbox_info->ext_info[0].htc_ext_sz =
1029 ATH10K_HIF_MBOX0_EXT_WIDTH_ROME_2_0;
1031 case QCA_MANUFACTURER_ID_QCA9377_BASE:
1032 mbox_info->ext_info[0].htc_ext_sz =
1033 ATH10K_HIF_MBOX0_EXT_WIDTH_ROME_2_0;
1036 mbox_info->ext_info[0].htc_ext_sz =
1037 ATH10K_HIF_MBOX0_EXT_WIDTH;
1040 mbox_info->ext_info[1].htc_ext_addr =
1041 mbox_info->ext_info[0].htc_ext_addr +
1042 mbox_info->ext_info[0].htc_ext_sz +
1043 ATH10K_HIF_MBOX_DUMMY_SPACE_SIZE;
1044 mbox_info->ext_info[1].htc_ext_sz = ATH10K_HIF_MBOX1_EXT_WIDTH;
1049 static int ath10k_sdio_bmi_credits(struct ath10k *ar)
1051 u32 addr, cmd_credits;
1052 unsigned long timeout;
1055 /* Read the counter register to get the command credits */
1056 addr = MBOX_COUNT_DEC_ADDRESS + ATH10K_HIF_MBOX_NUM_MAX * 4;
1057 timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1060 while (time_before(jiffies, timeout) && !cmd_credits) {
1061 /* Hit the credit counter with a 4-byte access, the first byte
1062 * read will hit the counter and cause a decrement, while the
1063 * remaining 3 bytes has no effect. The rationale behind this
1064 * is to make all HIF accesses 4-byte aligned.
1066 ret = ath10k_sdio_read32(ar, addr, &cmd_credits);
1069 "unable to decrement the command credit count register: %d\n",
1074 /* The counter is only 8 bits.
1075 * Ignore anything in the upper 3 bytes
1077 cmd_credits &= 0xFF;
1081 ath10k_warn(ar, "bmi communication timeout\n");
1088 static int ath10k_sdio_bmi_get_rx_lookahead(struct ath10k *ar)
1090 unsigned long timeout;
1094 timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1097 while ((time_before(jiffies, timeout)) && !rx_word) {
1098 ret = ath10k_sdio_read32(ar,
1099 MBOX_HOST_INT_STATUS_ADDRESS,
1102 ath10k_warn(ar, "unable to read RX_LOOKAHEAD_VALID: %d\n", ret);
1106 /* all we really want is one bit */
1111 ath10k_warn(ar, "bmi_recv_buf FIFO empty\n");
1118 static int ath10k_sdio_bmi_exchange_msg(struct ath10k *ar,
1119 void *req, u32 req_len,
1120 void *resp, u32 *resp_len)
1122 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1127 ret = ath10k_sdio_bmi_credits(ar);
1131 addr = ar_sdio->mbox_info.htc_addr;
1133 memcpy(ar_sdio->bmi_buf, req, req_len);
1134 ret = ath10k_sdio_write(ar, addr, ar_sdio->bmi_buf, req_len);
1137 "unable to send the bmi data to the device: %d\n",
1143 if (!resp || !resp_len)
1144 /* No response expected */
1147 /* During normal bootup, small reads may be required.
1148 * Rather than issue an HIF Read and then wait as the Target
1149 * adds successive bytes to the FIFO, we wait here until
1150 * we know that response data is available.
1152 * This allows us to cleanly timeout on an unexpected
1153 * Target failure rather than risk problems at the HIF level.
1154 * In particular, this avoids SDIO timeouts and possibly garbage
1155 * data on some host controllers. And on an interconnect
1156 * such as Compact Flash (as well as some SDIO masters) which
1157 * does not provide any indication on data timeout, it avoids
1158 * a potential hang or garbage response.
1160 * Synchronization is more difficult for reads larger than the
1161 * size of the MBOX FIFO (128B), because the Target is unable
1162 * to push the 129th byte of data until AFTER the Host posts an
1163 * HIF Read and removes some FIFO data. So for large reads the
1164 * Host proceeds to post an HIF Read BEFORE all the data is
1165 * actually available to read. Fortunately, large BMI reads do
1166 * not occur in practice -- they're supported for debug/development.
1168 * So Host/Target BMI synchronization is divided into these cases:
1169 * CASE 1: length < 4
1172 * CASE 2: 4 <= length <= 128
1173 * Wait for first 4 bytes to be in FIFO
1174 * If CONSERVATIVE_BMI_READ is enabled, also wait for
1175 * a BMI command credit, which indicates that the ENTIRE
1176 * response is available in the the FIFO
1178 * CASE 3: length > 128
1179 * Wait for the first 4 bytes to be in FIFO
1181 * For most uses, a small timeout should be sufficient and we will
1182 * usually see a response quickly; but there may be some unusual
1183 * (debug) cases of BMI_EXECUTE where we want an larger timeout.
1184 * For now, we use an unbounded busy loop while waiting for
1187 * If BMI_EXECUTE ever needs to support longer-latency execution,
1188 * especially in production, this code needs to be enhanced to sleep
1189 * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently
1190 * a function of Host processor speed.
1192 ret = ath10k_sdio_bmi_get_rx_lookahead(ar);
1196 /* We always read from the start of the mbox address */
1197 addr = ar_sdio->mbox_info.htc_addr;
1198 ret = ath10k_sdio_read(ar, addr, ar_sdio->bmi_buf, *resp_len);
1201 "unable to read the bmi data from the device: %d\n",
1206 memcpy(resp, ar_sdio->bmi_buf, *resp_len);
1211 /* sdio async handling functions */
1213 static struct ath10k_sdio_bus_request
1214 *ath10k_sdio_alloc_busreq(struct ath10k *ar)
1216 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1217 struct ath10k_sdio_bus_request *bus_req;
1219 spin_lock_bh(&ar_sdio->lock);
1221 if (list_empty(&ar_sdio->bus_req_freeq)) {
1226 bus_req = list_first_entry(&ar_sdio->bus_req_freeq,
1227 struct ath10k_sdio_bus_request, list);
1228 list_del(&bus_req->list);
1231 spin_unlock_bh(&ar_sdio->lock);
1235 static void ath10k_sdio_free_bus_req(struct ath10k *ar,
1236 struct ath10k_sdio_bus_request *bus_req)
1238 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1240 memset(bus_req, 0, sizeof(*bus_req));
1242 spin_lock_bh(&ar_sdio->lock);
1243 list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq);
1244 spin_unlock_bh(&ar_sdio->lock);
1247 static void __ath10k_sdio_write_async(struct ath10k *ar,
1248 struct ath10k_sdio_bus_request *req)
1250 struct ath10k_htc_ep *ep;
1251 struct sk_buff *skb;
1255 ret = ath10k_sdio_write(ar, req->address, skb->data, skb->len);
1257 ath10k_warn(ar, "failed to write skb to 0x%x asynchronously: %d",
1261 ep = &ar->htc.endpoint[req->eid];
1262 ath10k_htc_notify_tx_completion(ep, skb);
1263 } else if (req->comp) {
1264 complete(req->comp);
1267 ath10k_sdio_free_bus_req(ar, req);
1270 static void ath10k_sdio_write_async_work(struct work_struct *work)
1272 struct ath10k_sdio *ar_sdio = container_of(work, struct ath10k_sdio,
1274 struct ath10k *ar = ar_sdio->ar;
1275 struct ath10k_sdio_bus_request *req, *tmp_req;
1277 spin_lock_bh(&ar_sdio->wr_async_lock);
1279 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
1280 list_del(&req->list);
1281 spin_unlock_bh(&ar_sdio->wr_async_lock);
1282 __ath10k_sdio_write_async(ar, req);
1283 spin_lock_bh(&ar_sdio->wr_async_lock);
1286 spin_unlock_bh(&ar_sdio->wr_async_lock);
1289 static int ath10k_sdio_prep_async_req(struct ath10k *ar, u32 addr,
1290 struct sk_buff *skb,
1291 struct completion *comp,
1292 bool htc_msg, enum ath10k_htc_ep_id eid)
1294 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1295 struct ath10k_sdio_bus_request *bus_req;
1297 /* Allocate a bus request for the message and queue it on the
1300 bus_req = ath10k_sdio_alloc_busreq(ar);
1303 "unable to allocate bus request for async request\n");
1309 bus_req->address = addr;
1310 bus_req->htc_msg = htc_msg;
1311 bus_req->comp = comp;
1313 spin_lock_bh(&ar_sdio->wr_async_lock);
1314 list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq);
1315 spin_unlock_bh(&ar_sdio->wr_async_lock);
1322 static void ath10k_sdio_irq_handler(struct sdio_func *func)
1324 struct ath10k_sdio *ar_sdio = sdio_get_drvdata(func);
1325 struct ath10k *ar = ar_sdio->ar;
1326 unsigned long timeout;
1330 /* Release the host during interrupts so we can pick it back up when
1331 * we process commands.
1333 sdio_release_host(ar_sdio->func);
1335 timeout = jiffies + ATH10K_SDIO_HIF_COMMUNICATION_TIMEOUT_HZ;
1337 ret = ath10k_sdio_mbox_proc_pending_irqs(ar, &done);
1340 } while (time_before(jiffies, timeout) && !done);
1342 ath10k_mac_tx_push_pending(ar);
1344 sdio_claim_host(ar_sdio->func);
1346 if (ret && ret != -ECANCELED)
1347 ath10k_warn(ar, "failed to process pending SDIO interrupts: %d\n",
1351 /* sdio HIF functions */
1353 static int ath10k_sdio_hif_disable_intrs(struct ath10k *ar)
1355 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1356 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
1357 struct ath10k_sdio_irq_enable_regs *regs = irq_data->irq_en_reg;
1360 mutex_lock(&irq_data->mtx);
1362 memset(regs, 0, sizeof(*regs));
1363 ret = ath10k_sdio_write(ar, MBOX_INT_STATUS_ENABLE_ADDRESS,
1364 ®s->int_status_en, sizeof(*regs));
1366 ath10k_warn(ar, "unable to disable sdio interrupts: %d\n", ret);
1368 mutex_unlock(&irq_data->mtx);
1373 static int ath10k_sdio_hif_power_up(struct ath10k *ar,
1374 enum ath10k_firmware_mode fw_mode)
1376 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1377 struct sdio_func *func = ar_sdio->func;
1380 if (!ar_sdio->is_disabled)
1383 ath10k_dbg(ar, ATH10K_DBG_BOOT, "sdio power on\n");
1385 sdio_claim_host(func);
1387 ret = sdio_enable_func(func);
1389 ath10k_warn(ar, "unable to enable sdio function: %d)\n", ret);
1390 sdio_release_host(func);
1394 sdio_release_host(func);
1396 /* Wait for hardware to initialise. It should take a lot less than
1397 * 20 ms but let's be conservative here.
1401 ar_sdio->is_disabled = false;
1403 ret = ath10k_sdio_hif_disable_intrs(ar);
1410 static void ath10k_sdio_hif_power_down(struct ath10k *ar)
1412 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1415 if (ar_sdio->is_disabled)
1418 ath10k_dbg(ar, ATH10K_DBG_BOOT, "sdio power off\n");
1420 /* Disable the card */
1421 sdio_claim_host(ar_sdio->func);
1422 ret = sdio_disable_func(ar_sdio->func);
1423 sdio_release_host(ar_sdio->func);
1426 ath10k_warn(ar, "unable to disable sdio function: %d\n", ret);
1428 ar_sdio->is_disabled = true;
1431 static int ath10k_sdio_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
1432 struct ath10k_hif_sg_item *items, int n_items)
1434 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1435 enum ath10k_htc_ep_id eid;
1436 struct sk_buff *skb;
1439 eid = pipe_id_to_eid(pipe_id);
1441 for (i = 0; i < n_items; i++) {
1445 skb = items[i].transfer_context;
1446 padded_len = ath10k_sdio_calc_txrx_padded_len(ar_sdio,
1448 skb_trim(skb, padded_len);
1450 /* Write TX data to the end of the mbox address space */
1451 address = ar_sdio->mbox_addr[eid] + ar_sdio->mbox_size[eid] -
1453 ret = ath10k_sdio_prep_async_req(ar, address, skb,
1459 queue_work(ar_sdio->workqueue, &ar_sdio->wr_async_work);
1464 static int ath10k_sdio_hif_enable_intrs(struct ath10k *ar)
1466 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1467 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
1468 struct ath10k_sdio_irq_enable_regs *regs = irq_data->irq_en_reg;
1471 mutex_lock(&irq_data->mtx);
1473 /* Enable all but CPU interrupts */
1474 regs->int_status_en = FIELD_PREP(MBOX_INT_STATUS_ENABLE_ERROR_MASK, 1) |
1475 FIELD_PREP(MBOX_INT_STATUS_ENABLE_CPU_MASK, 1) |
1476 FIELD_PREP(MBOX_INT_STATUS_ENABLE_COUNTER_MASK, 1);
1478 /* NOTE: There are some cases where HIF can do detection of
1479 * pending mbox messages which is disabled now.
1481 regs->int_status_en |=
1482 FIELD_PREP(MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK, 1);
1484 /* Set up the CPU Interrupt status Register */
1485 regs->cpu_int_status_en = 0;
1487 /* Set up the Error Interrupt status Register */
1488 regs->err_int_status_en =
1489 FIELD_PREP(MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK, 1) |
1490 FIELD_PREP(MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK, 1);
1492 /* Enable Counter interrupt status register to get fatal errors for
1495 regs->cntr_int_status_en =
1496 FIELD_PREP(MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
1497 ATH10K_SDIO_TARGET_DEBUG_INTR_MASK);
1499 ret = ath10k_sdio_write(ar, MBOX_INT_STATUS_ENABLE_ADDRESS,
1500 ®s->int_status_en, sizeof(*regs));
1503 "failed to update mbox interrupt status register : %d\n",
1506 mutex_unlock(&irq_data->mtx);
1510 static int ath10k_sdio_hif_set_mbox_sleep(struct ath10k *ar, bool enable_sleep)
1515 ret = ath10k_sdio_read32(ar, ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL, &val);
1517 ath10k_warn(ar, "failed to read fifo/chip control register: %d\n",
1523 val &= ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_OFF;
1525 val |= ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_ON;
1527 ret = ath10k_sdio_write32(ar, ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL, val);
1529 ath10k_warn(ar, "failed to write to FIFO_TIMEOUT_AND_CHIP_CONTROL: %d",
1537 /* HIF diagnostics */
1539 static int ath10k_sdio_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
1544 /* set window register to start read cycle */
1545 ret = ath10k_sdio_write32(ar, MBOX_WINDOW_READ_ADDR_ADDRESS, address);
1547 ath10k_warn(ar, "failed to set mbox window read address: %d", ret);
1552 ret = ath10k_sdio_read(ar, MBOX_WINDOW_DATA_ADDRESS, buf, buf_len);
1554 ath10k_warn(ar, "failed to read from mbox window data address: %d\n",
1562 static int ath10k_sdio_hif_diag_read32(struct ath10k *ar, u32 address,
1568 val = kzalloc(sizeof(*val), GFP_KERNEL);
1572 ret = ath10k_sdio_hif_diag_read(ar, address, val, sizeof(*val));
1576 *value = __le32_to_cpu(*val);
1584 static int ath10k_sdio_hif_diag_write_mem(struct ath10k *ar, u32 address,
1585 const void *data, int nbytes)
1589 /* set write data */
1590 ret = ath10k_sdio_write(ar, MBOX_WINDOW_DATA_ADDRESS, data, nbytes);
1593 "failed to write 0x%p to mbox window data address: %d\n",
1598 /* set window register, which starts the write cycle */
1599 ret = ath10k_sdio_write32(ar, MBOX_WINDOW_WRITE_ADDR_ADDRESS, address);
1601 ath10k_warn(ar, "failed to set mbox window write address: %d", ret);
1608 static int ath10k_sdio_hif_swap_mailbox(struct ath10k *ar)
1610 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1614 addr = host_interest_item_address(HI_ITEM(hi_acs_flags));
1616 ret = ath10k_sdio_hif_diag_read32(ar, addr, &val);
1618 ath10k_warn(ar, "unable to read hi_acs_flags : %d\n", ret);
1622 if (val & HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_FW_ACK) {
1623 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1624 "sdio mailbox swap service enabled\n");
1625 ar_sdio->swap_mbox = true;
1630 /* HIF start/stop */
1632 static int ath10k_sdio_hif_start(struct ath10k *ar)
1634 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1637 /* Sleep 20 ms before HIF interrupts are disabled.
1638 * This will give target plenty of time to process the BMI done
1639 * request before interrupts are disabled.
1642 ret = ath10k_sdio_hif_disable_intrs(ar);
1646 /* eid 0 always uses the lower part of the extended mailbox address
1647 * space (ext_info[0].htc_ext_addr).
1649 ar_sdio->mbox_addr[0] = ar_sdio->mbox_info.ext_info[0].htc_ext_addr;
1650 ar_sdio->mbox_size[0] = ar_sdio->mbox_info.ext_info[0].htc_ext_sz;
1652 sdio_claim_host(ar_sdio->func);
1654 /* Register the isr */
1655 ret = sdio_claim_irq(ar_sdio->func, ath10k_sdio_irq_handler);
1657 ath10k_warn(ar, "failed to claim sdio interrupt: %d\n", ret);
1658 sdio_release_host(ar_sdio->func);
1662 sdio_release_host(ar_sdio->func);
1664 ret = ath10k_sdio_hif_enable_intrs(ar);
1666 ath10k_warn(ar, "failed to enable sdio interrupts: %d\n", ret);
1668 /* Enable sleep and then disable it again */
1669 ret = ath10k_sdio_hif_set_mbox_sleep(ar, true);
1673 /* Wait for 20ms for the written value to take effect */
1676 ret = ath10k_sdio_hif_set_mbox_sleep(ar, false);
1683 #define SDIO_IRQ_DISABLE_TIMEOUT_HZ (3 * HZ)
1685 static void ath10k_sdio_irq_disable(struct ath10k *ar)
1687 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1688 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
1689 struct ath10k_sdio_irq_enable_regs *regs = irq_data->irq_en_reg;
1690 struct sk_buff *skb;
1691 struct completion irqs_disabled_comp;
1694 skb = dev_alloc_skb(sizeof(*regs));
1698 mutex_lock(&irq_data->mtx);
1700 memset(regs, 0, sizeof(*regs)); /* disable all interrupts */
1701 memcpy(skb->data, regs, sizeof(*regs));
1702 skb_put(skb, sizeof(*regs));
1704 mutex_unlock(&irq_data->mtx);
1706 init_completion(&irqs_disabled_comp);
1707 ret = ath10k_sdio_prep_async_req(ar, MBOX_INT_STATUS_ENABLE_ADDRESS,
1708 skb, &irqs_disabled_comp, false, 0);
1712 queue_work(ar_sdio->workqueue, &ar_sdio->wr_async_work);
1714 /* Wait for the completion of the IRQ disable request.
1715 * If there is a timeout we will try to disable irq's anyway.
1717 ret = wait_for_completion_timeout(&irqs_disabled_comp,
1718 SDIO_IRQ_DISABLE_TIMEOUT_HZ);
1720 ath10k_warn(ar, "sdio irq disable request timed out\n");
1722 sdio_claim_host(ar_sdio->func);
1724 ret = sdio_release_irq(ar_sdio->func);
1726 ath10k_warn(ar, "failed to release sdio interrupt: %d\n", ret);
1728 sdio_release_host(ar_sdio->func);
1734 static void ath10k_sdio_hif_stop(struct ath10k *ar)
1736 struct ath10k_sdio_bus_request *req, *tmp_req;
1737 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1739 ath10k_sdio_irq_disable(ar);
1741 cancel_work_sync(&ar_sdio->wr_async_work);
1743 spin_lock_bh(&ar_sdio->wr_async_lock);
1745 /* Free all bus requests that have not been handled */
1746 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
1747 struct ath10k_htc_ep *ep;
1749 list_del(&req->list);
1752 ep = &ar->htc.endpoint[req->eid];
1753 ath10k_htc_notify_tx_completion(ep, req->skb);
1754 } else if (req->skb) {
1755 kfree_skb(req->skb);
1757 ath10k_sdio_free_bus_req(ar, req);
1760 spin_unlock_bh(&ar_sdio->wr_async_lock);
1765 static int ath10k_sdio_hif_suspend(struct ath10k *ar)
1770 static int ath10k_sdio_hif_resume(struct ath10k *ar)
1772 switch (ar->state) {
1773 case ATH10K_STATE_OFF:
1774 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1775 "sdio resume configuring sdio\n");
1777 /* need to set sdio settings after power is cut from sdio */
1778 ath10k_sdio_config(ar);
1781 case ATH10K_STATE_ON:
1790 static int ath10k_sdio_hif_map_service_to_pipe(struct ath10k *ar,
1792 u8 *ul_pipe, u8 *dl_pipe)
1794 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1795 struct ath10k_htc *htc = &ar->htc;
1796 u32 htt_addr, wmi_addr, htt_mbox_size, wmi_mbox_size;
1797 enum ath10k_htc_ep_id eid;
1798 bool ep_found = false;
1801 /* For sdio, we are interested in the mapping between eid
1802 * and pipeid rather than service_id to pipe_id.
1803 * First we find out which eid has been allocated to the
1806 for (i = 0; i < ATH10K_HTC_EP_COUNT; i++) {
1807 if (htc->endpoint[i].service_id == service_id) {
1808 eid = htc->endpoint[i].eid;
1817 /* Then we create the simplest mapping possible between pipeid
1820 *ul_pipe = *dl_pipe = (u8)eid;
1822 /* Normally, HTT will use the upper part of the extended
1823 * mailbox address space (ext_info[1].htc_ext_addr) and WMI ctrl
1824 * the lower part (ext_info[0].htc_ext_addr).
1825 * If fw wants swapping of mailbox addresses, the opposite is true.
1827 if (ar_sdio->swap_mbox) {
1828 htt_addr = ar_sdio->mbox_info.ext_info[0].htc_ext_addr;
1829 wmi_addr = ar_sdio->mbox_info.ext_info[1].htc_ext_addr;
1830 htt_mbox_size = ar_sdio->mbox_info.ext_info[0].htc_ext_sz;
1831 wmi_mbox_size = ar_sdio->mbox_info.ext_info[1].htc_ext_sz;
1833 htt_addr = ar_sdio->mbox_info.ext_info[1].htc_ext_addr;
1834 wmi_addr = ar_sdio->mbox_info.ext_info[0].htc_ext_addr;
1835 htt_mbox_size = ar_sdio->mbox_info.ext_info[1].htc_ext_sz;
1836 wmi_mbox_size = ar_sdio->mbox_info.ext_info[0].htc_ext_sz;
1839 switch (service_id) {
1840 case ATH10K_HTC_SVC_ID_RSVD_CTRL:
1841 /* HTC ctrl ep mbox address has already been setup in
1842 * ath10k_sdio_hif_start
1845 case ATH10K_HTC_SVC_ID_WMI_CONTROL:
1846 ar_sdio->mbox_addr[eid] = wmi_addr;
1847 ar_sdio->mbox_size[eid] = wmi_mbox_size;
1848 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1849 "sdio wmi ctrl mbox_addr 0x%x mbox_size %d\n",
1850 ar_sdio->mbox_addr[eid], ar_sdio->mbox_size[eid]);
1852 case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
1853 ar_sdio->mbox_addr[eid] = htt_addr;
1854 ar_sdio->mbox_size[eid] = htt_mbox_size;
1855 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1856 "sdio htt data mbox_addr 0x%x mbox_size %d\n",
1857 ar_sdio->mbox_addr[eid], ar_sdio->mbox_size[eid]);
1860 ath10k_warn(ar, "unsupported HTC service id: %d\n",
1868 static void ath10k_sdio_hif_get_default_pipe(struct ath10k *ar,
1869 u8 *ul_pipe, u8 *dl_pipe)
1871 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio hif get default pipe\n");
1873 /* HTC ctrl ep (SVC id 1) always has eid (and pipe_id in our
1880 /* This op is currently only used by htc_wait_target if the HTC ready
1881 * message times out. It is not applicable for SDIO since there is nothing
1882 * we can do if the HTC ready message does not arrive in time.
1883 * TODO: Make this op non mandatory by introducing a NULL check in the
1886 static void ath10k_sdio_hif_send_complete_check(struct ath10k *ar,
1891 static const struct ath10k_hif_ops ath10k_sdio_hif_ops = {
1892 .tx_sg = ath10k_sdio_hif_tx_sg,
1893 .diag_read = ath10k_sdio_hif_diag_read,
1894 .diag_write = ath10k_sdio_hif_diag_write_mem,
1895 .exchange_bmi_msg = ath10k_sdio_bmi_exchange_msg,
1896 .start = ath10k_sdio_hif_start,
1897 .stop = ath10k_sdio_hif_stop,
1898 .swap_mailbox = ath10k_sdio_hif_swap_mailbox,
1899 .map_service_to_pipe = ath10k_sdio_hif_map_service_to_pipe,
1900 .get_default_pipe = ath10k_sdio_hif_get_default_pipe,
1901 .send_complete_check = ath10k_sdio_hif_send_complete_check,
1902 .power_up = ath10k_sdio_hif_power_up,
1903 .power_down = ath10k_sdio_hif_power_down,
1905 .suspend = ath10k_sdio_hif_suspend,
1906 .resume = ath10k_sdio_hif_resume,
1910 #ifdef CONFIG_PM_SLEEP
1912 /* Empty handlers so that mmc subsystem doesn't remove us entirely during
1913 * suspend. We instead follow cfg80211 suspend/resume handlers.
1915 static int ath10k_sdio_pm_suspend(struct device *device)
1920 static int ath10k_sdio_pm_resume(struct device *device)
1925 static SIMPLE_DEV_PM_OPS(ath10k_sdio_pm_ops, ath10k_sdio_pm_suspend,
1926 ath10k_sdio_pm_resume);
1928 #define ATH10K_SDIO_PM_OPS (&ath10k_sdio_pm_ops)
1932 #define ATH10K_SDIO_PM_OPS NULL
1934 #endif /* CONFIG_PM_SLEEP */
1936 static int ath10k_sdio_probe(struct sdio_func *func,
1937 const struct sdio_device_id *id)
1939 struct ath10k_sdio *ar_sdio;
1941 enum ath10k_hw_rev hw_rev;
1943 struct ath10k_bus_params bus_params;
1946 /* Assumption: All SDIO based chipsets (so far) are QCA6174 based.
1947 * If there will be newer chipsets that does not use the hw reg
1948 * setup as defined in qca6174_regs and qca6174_values, this
1949 * assumption is no longer valid and hw_rev must be setup differently
1950 * depending on chipset.
1952 hw_rev = ATH10K_HW_QCA6174;
1954 ar = ath10k_core_create(sizeof(*ar_sdio), &func->dev, ATH10K_BUS_SDIO,
1955 hw_rev, &ath10k_sdio_hif_ops);
1957 dev_err(&func->dev, "failed to allocate core\n");
1961 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1962 "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n",
1963 func->num, func->vendor, func->device,
1964 func->max_blksize, func->cur_blksize);
1966 ar_sdio = ath10k_sdio_priv(ar);
1968 ar_sdio->irq_data.irq_proc_reg =
1969 devm_kzalloc(ar->dev, sizeof(struct ath10k_sdio_irq_proc_regs),
1971 if (!ar_sdio->irq_data.irq_proc_reg) {
1973 goto err_core_destroy;
1976 ar_sdio->irq_data.irq_en_reg =
1977 devm_kzalloc(ar->dev, sizeof(struct ath10k_sdio_irq_enable_regs),
1979 if (!ar_sdio->irq_data.irq_en_reg) {
1981 goto err_core_destroy;
1984 ar_sdio->bmi_buf = devm_kzalloc(ar->dev, BMI_MAX_CMDBUF_SIZE, GFP_KERNEL);
1985 if (!ar_sdio->bmi_buf) {
1987 goto err_core_destroy;
1990 ar_sdio->func = func;
1991 sdio_set_drvdata(func, ar_sdio);
1993 ar_sdio->is_disabled = true;
1996 spin_lock_init(&ar_sdio->lock);
1997 spin_lock_init(&ar_sdio->wr_async_lock);
1998 mutex_init(&ar_sdio->irq_data.mtx);
2000 INIT_LIST_HEAD(&ar_sdio->bus_req_freeq);
2001 INIT_LIST_HEAD(&ar_sdio->wr_asyncq);
2003 INIT_WORK(&ar_sdio->wr_async_work, ath10k_sdio_write_async_work);
2004 ar_sdio->workqueue = create_singlethread_workqueue("ath10k_sdio_wq");
2005 if (!ar_sdio->workqueue) {
2007 goto err_core_destroy;
2010 for (i = 0; i < ATH10K_SDIO_BUS_REQUEST_MAX_NUM; i++)
2011 ath10k_sdio_free_bus_req(ar, &ar_sdio->bus_req[i]);
2013 dev_id_base = FIELD_GET(QCA_MANUFACTURER_ID_BASE, id->device);
2014 switch (dev_id_base) {
2015 case QCA_MANUFACTURER_ID_AR6005_BASE:
2016 case QCA_MANUFACTURER_ID_QCA9377_BASE:
2017 ar->dev_id = QCA9377_1_0_DEVICE_ID;
2021 ath10k_err(ar, "unsupported device id %u (0x%x)\n",
2022 dev_id_base, id->device);
2026 ar->id.vendor = id->vendor;
2027 ar->id.device = id->device;
2029 ath10k_sdio_set_mbox_info(ar);
2031 ret = ath10k_sdio_config(ar);
2033 ath10k_err(ar, "failed to config sdio: %d\n", ret);
2037 bus_params.dev_type = ATH10K_DEV_TYPE_HL;
2038 /* TODO: don't know yet how to get chip_id with SDIO */
2039 bus_params.chip_id = 0;
2040 ret = ath10k_core_register(ar, &bus_params);
2042 ath10k_err(ar, "failed to register driver core: %d\n", ret);
2046 /* TODO: remove this once SDIO support is fully implemented */
2047 ath10k_warn(ar, "WARNING: ath10k SDIO support is incomplete, don't expect anything to work!\n");
2052 destroy_workqueue(ar_sdio->workqueue);
2054 ath10k_core_destroy(ar);
2059 static void ath10k_sdio_remove(struct sdio_func *func)
2061 struct ath10k_sdio *ar_sdio = sdio_get_drvdata(func);
2062 struct ath10k *ar = ar_sdio->ar;
2064 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2065 "sdio removed func %d vendor 0x%x device 0x%x\n",
2066 func->num, func->vendor, func->device);
2068 (void)ath10k_sdio_hif_disable_intrs(ar);
2069 cancel_work_sync(&ar_sdio->wr_async_work);
2070 ath10k_core_unregister(ar);
2071 ath10k_core_destroy(ar);
2074 static const struct sdio_device_id ath10k_sdio_devices[] = {
2075 {SDIO_DEVICE(QCA_MANUFACTURER_CODE,
2076 (QCA_SDIO_ID_AR6005_BASE | 0xA))},
2077 {SDIO_DEVICE(QCA_MANUFACTURER_CODE,
2078 (QCA_SDIO_ID_QCA9377_BASE | 0x1))},
2082 MODULE_DEVICE_TABLE(sdio, ath10k_sdio_devices);
2084 static struct sdio_driver ath10k_sdio_driver = {
2085 .name = "ath10k_sdio",
2086 .id_table = ath10k_sdio_devices,
2087 .probe = ath10k_sdio_probe,
2088 .remove = ath10k_sdio_remove,
2090 .owner = THIS_MODULE,
2091 .pm = ATH10K_SDIO_PM_OPS,
2095 static int __init ath10k_sdio_init(void)
2099 ret = sdio_register_driver(&ath10k_sdio_driver);
2101 pr_err("sdio driver registration failed: %d\n", ret);
2106 static void __exit ath10k_sdio_exit(void)
2108 sdio_unregister_driver(&ath10k_sdio_driver);
2111 module_init(ath10k_sdio_init);
2112 module_exit(ath10k_sdio_exit);
2114 MODULE_AUTHOR("Qualcomm Atheros");
2115 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN SDIO devices");
2116 MODULE_LICENSE("Dual BSD/GPL");