2 * Copyright (c) 2004-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012,2017 Qualcomm Atheros, Inc.
4 * Copyright (c) 2016-2017 Erik Stromdahl <erik.stromdahl@gmail.com>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #include <linux/module.h>
20 #include <linux/mmc/card.h>
21 #include <linux/mmc/mmc.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/sdio_func.h>
24 #include <linux/mmc/sdio_ids.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sd.h>
27 #include <linux/bitfield.h>
34 #include "targaddrs.h"
38 /* inlined helper functions */
40 static inline int ath10k_sdio_calc_txrx_padded_len(struct ath10k_sdio *ar_sdio,
43 return __ALIGN_MASK((len), ar_sdio->mbox_info.block_mask);
46 static inline enum ath10k_htc_ep_id pipe_id_to_eid(u8 pipe_id)
48 return (enum ath10k_htc_ep_id)pipe_id;
51 static inline void ath10k_sdio_mbox_free_rx_pkt(struct ath10k_sdio_rx_data *pkt)
53 dev_kfree_skb(pkt->skb);
57 pkt->trailer_only = false;
60 static inline int ath10k_sdio_mbox_alloc_rx_pkt(struct ath10k_sdio_rx_data *pkt,
61 size_t act_len, size_t full_len,
65 pkt->skb = dev_alloc_skb(full_len);
69 pkt->act_len = act_len;
70 pkt->alloc_len = full_len;
71 pkt->part_of_bundle = part_of_bundle;
72 pkt->last_in_bundle = last_in_bundle;
73 pkt->trailer_only = false;
78 static inline bool is_trailer_only_msg(struct ath10k_sdio_rx_data *pkt)
80 bool trailer_only = false;
81 struct ath10k_htc_hdr *htc_hdr =
82 (struct ath10k_htc_hdr *)pkt->skb->data;
83 u16 len = __le16_to_cpu(htc_hdr->len);
85 if (len == htc_hdr->trailer_len)
91 /* sdio/mmc functions */
93 static inline void ath10k_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw,
97 *arg = FIELD_PREP(BIT(31), write) |
98 FIELD_PREP(BIT(27), raw) |
99 FIELD_PREP(BIT(26), 1) |
100 FIELD_PREP(GENMASK(25, 9), address) |
101 FIELD_PREP(BIT(8), 1) |
102 FIELD_PREP(GENMASK(7, 0), val);
105 static int ath10k_sdio_func0_cmd52_wr_byte(struct mmc_card *card,
106 unsigned int address,
109 struct mmc_command io_cmd;
111 memset(&io_cmd, 0, sizeof(io_cmd));
112 ath10k_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte);
113 io_cmd.opcode = SD_IO_RW_DIRECT;
114 io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
116 return mmc_wait_for_cmd(card->host, &io_cmd, 0);
119 static int ath10k_sdio_func0_cmd52_rd_byte(struct mmc_card *card,
120 unsigned int address,
123 struct mmc_command io_cmd;
126 memset(&io_cmd, 0, sizeof(io_cmd));
127 ath10k_sdio_set_cmd52_arg(&io_cmd.arg, 0, 0, address, 0);
128 io_cmd.opcode = SD_IO_RW_DIRECT;
129 io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
131 ret = mmc_wait_for_cmd(card->host, &io_cmd, 0);
133 *byte = io_cmd.resp[0];
138 static int ath10k_sdio_config(struct ath10k *ar)
140 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
141 struct sdio_func *func = ar_sdio->func;
142 unsigned char byte, asyncintdelay = 2;
145 ath10k_dbg(ar, ATH10K_DBG_BOOT, "sdio configuration\n");
147 sdio_claim_host(func);
150 ret = ath10k_sdio_func0_cmd52_rd_byte(func->card,
151 SDIO_CCCR_DRIVE_STRENGTH,
154 byte &= ~ATH10K_SDIO_DRIVE_DTSX_MASK;
155 byte |= FIELD_PREP(ATH10K_SDIO_DRIVE_DTSX_MASK,
156 ATH10K_SDIO_DRIVE_DTSX_TYPE_D);
158 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
159 SDIO_CCCR_DRIVE_STRENGTH,
163 ret = ath10k_sdio_func0_cmd52_rd_byte(
165 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR,
168 byte |= (CCCR_SDIO_DRIVER_STRENGTH_ENABLE_A |
169 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_C |
170 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_D);
172 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
173 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR,
176 ath10k_warn(ar, "failed to enable driver strength: %d\n", ret);
181 ret = ath10k_sdio_func0_cmd52_rd_byte(func->card,
182 CCCR_SDIO_IRQ_MODE_REG_SDIO3,
185 byte |= SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_SDIO3;
187 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
188 CCCR_SDIO_IRQ_MODE_REG_SDIO3,
191 ath10k_warn(ar, "failed to enable 4-bit async irq mode: %d\n",
197 ret = ath10k_sdio_func0_cmd52_rd_byte(func->card,
198 CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS,
201 byte &= ~CCCR_SDIO_ASYNC_INT_DELAY_MASK;
202 byte |= FIELD_PREP(CCCR_SDIO_ASYNC_INT_DELAY_MASK, asyncintdelay);
204 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
205 CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS,
208 /* give us some time to enable, in ms */
209 func->enable_timeout = 100;
211 ret = sdio_set_block_size(func, ar_sdio->mbox_info.block_size);
213 ath10k_warn(ar, "failed to set sdio block size to %d: %d\n",
214 ar_sdio->mbox_info.block_size, ret);
219 sdio_release_host(func);
223 static int ath10k_sdio_write32(struct ath10k *ar, u32 addr, u32 val)
225 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
226 struct sdio_func *func = ar_sdio->func;
229 sdio_claim_host(func);
231 sdio_writel(func, val, addr, &ret);
233 ath10k_warn(ar, "failed to write 0x%x to address 0x%x: %d\n",
238 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio write32 addr 0x%x val 0x%x\n",
242 sdio_release_host(func);
247 static int ath10k_sdio_writesb32(struct ath10k *ar, u32 addr, u32 val)
249 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
250 struct sdio_func *func = ar_sdio->func;
254 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
258 *buf = cpu_to_le32(val);
260 sdio_claim_host(func);
262 ret = sdio_writesb(func, addr, buf, sizeof(*buf));
264 ath10k_warn(ar, "failed to write value 0x%x to fixed sb address 0x%x: %d\n",
269 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio writesb32 addr 0x%x val 0x%x\n",
273 sdio_release_host(func);
280 static int ath10k_sdio_read32(struct ath10k *ar, u32 addr, u32 *val)
282 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
283 struct sdio_func *func = ar_sdio->func;
286 sdio_claim_host(func);
287 *val = sdio_readl(func, addr, &ret);
289 ath10k_warn(ar, "failed to read from address 0x%x: %d\n",
294 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio read32 addr 0x%x val 0x%x\n",
298 sdio_release_host(func);
303 static int ath10k_sdio_read(struct ath10k *ar, u32 addr, void *buf, size_t len)
305 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
306 struct sdio_func *func = ar_sdio->func;
309 sdio_claim_host(func);
311 ret = sdio_memcpy_fromio(func, buf, addr, len);
313 ath10k_warn(ar, "failed to read from address 0x%x: %d\n",
318 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio read addr 0x%x buf 0x%p len %zu\n",
320 ath10k_dbg_dump(ar, ATH10K_DBG_SDIO_DUMP, NULL, "sdio read ", buf, len);
323 sdio_release_host(func);
328 static int ath10k_sdio_write(struct ath10k *ar, u32 addr, const void *buf, size_t len)
330 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
331 struct sdio_func *func = ar_sdio->func;
334 sdio_claim_host(func);
336 /* For some reason toio() doesn't have const for the buffer, need
337 * an ugly hack to workaround that.
339 ret = sdio_memcpy_toio(func, addr, (void *)buf, len);
341 ath10k_warn(ar, "failed to write to address 0x%x: %d\n",
346 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio write addr 0x%x buf 0x%p len %zu\n",
348 ath10k_dbg_dump(ar, ATH10K_DBG_SDIO_DUMP, NULL, "sdio write ", buf, len);
351 sdio_release_host(func);
356 static int ath10k_sdio_readsb(struct ath10k *ar, u32 addr, void *buf, size_t len)
358 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
359 struct sdio_func *func = ar_sdio->func;
362 sdio_claim_host(func);
364 len = round_down(len, ar_sdio->mbox_info.block_size);
366 ret = sdio_readsb(func, buf, addr, len);
368 ath10k_warn(ar, "failed to read from fixed (sb) address 0x%x: %d\n",
373 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio readsb addr 0x%x buf 0x%p len %zu\n",
375 ath10k_dbg_dump(ar, ATH10K_DBG_SDIO_DUMP, NULL, "sdio readsb ", buf, len);
378 sdio_release_host(func);
383 /* HIF mbox functions */
385 static int ath10k_sdio_mbox_rx_process_packet(struct ath10k *ar,
386 struct ath10k_sdio_rx_data *pkt,
390 struct ath10k_htc *htc = &ar->htc;
391 struct sk_buff *skb = pkt->skb;
392 struct ath10k_htc_hdr *htc_hdr = (struct ath10k_htc_hdr *)skb->data;
393 bool trailer_present = htc_hdr->flags & ATH10K_HTC_FLAG_TRAILER_PRESENT;
394 enum ath10k_htc_ep_id eid;
399 payload_len = le16_to_cpu(htc_hdr->len);
400 skb->len = payload_len + sizeof(struct ath10k_htc_hdr);
402 if (trailer_present) {
403 trailer = skb->data + sizeof(*htc_hdr) +
404 payload_len - htc_hdr->trailer_len;
406 eid = pipe_id_to_eid(htc_hdr->eid);
408 ret = ath10k_htc_process_trailer(htc,
410 htc_hdr->trailer_len,
417 if (is_trailer_only_msg(pkt))
418 pkt->trailer_only = true;
420 skb_trim(skb, skb->len - htc_hdr->trailer_len);
423 skb_pull(skb, sizeof(*htc_hdr));
428 static int ath10k_sdio_mbox_rx_process_packets(struct ath10k *ar,
432 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
433 struct ath10k_htc *htc = &ar->htc;
434 struct ath10k_sdio_rx_data *pkt;
435 struct ath10k_htc_ep *ep;
436 enum ath10k_htc_ep_id id;
437 int ret, i, *n_lookahead_local;
438 u32 *lookaheads_local;
439 int lookahead_idx = 0;
441 for (i = 0; i < ar_sdio->n_rx_pkts; i++) {
442 lookaheads_local = lookaheads;
443 n_lookahead_local = n_lookahead;
445 id = ((struct ath10k_htc_hdr *)
446 &lookaheads[lookahead_idx++])->eid;
448 if (id >= ATH10K_HTC_EP_COUNT) {
449 ath10k_warn(ar, "invalid endpoint in look-ahead: %d\n",
455 ep = &htc->endpoint[id];
457 if (ep->service_id == 0) {
458 ath10k_warn(ar, "ep %d is not connected\n", id);
463 pkt = &ar_sdio->rx_pkts[i];
465 if (pkt->part_of_bundle && !pkt->last_in_bundle) {
466 /* Only read lookahead's from RX trailers
467 * for the last packet in a bundle.
470 lookaheads_local = NULL;
471 n_lookahead_local = NULL;
474 ret = ath10k_sdio_mbox_rx_process_packet(ar,
481 if (!pkt->trailer_only)
482 ep->ep_ops.ep_rx_complete(ar_sdio->ar, pkt->skb);
486 /* The RX complete handler now owns the skb...*/
494 /* Free all packets that was not passed on to the RX completion
497 for (; i < ar_sdio->n_rx_pkts; i++)
498 ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]);
503 static int ath10k_sdio_mbox_alloc_pkt_bundle(struct ath10k *ar,
504 struct ath10k_sdio_rx_data *rx_pkts,
505 struct ath10k_htc_hdr *htc_hdr,
506 size_t full_len, size_t act_len,
511 *bndl_cnt = FIELD_GET(ATH10K_HTC_FLAG_BUNDLE_MASK, htc_hdr->flags);
513 if (*bndl_cnt > HTC_HOST_MAX_MSG_PER_RX_BUNDLE) {
515 "HTC bundle length %u exceeds maximum %u\n",
516 le16_to_cpu(htc_hdr->len),
517 HTC_HOST_MAX_MSG_PER_RX_BUNDLE);
521 /* Allocate bndl_cnt extra skb's for the bundle.
522 * The package containing the
523 * ATH10K_HTC_FLAG_BUNDLE_MASK flag is not included
524 * in bndl_cnt. The skb for that packet will be
525 * allocated separately.
527 for (i = 0; i < *bndl_cnt; i++) {
528 ret = ath10k_sdio_mbox_alloc_rx_pkt(&rx_pkts[i],
540 static int ath10k_sdio_mbox_rx_alloc(struct ath10k *ar,
541 u32 lookaheads[], int n_lookaheads)
543 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
544 struct ath10k_htc_hdr *htc_hdr;
545 size_t full_len, act_len;
549 if (n_lookaheads > ATH10K_SDIO_MAX_RX_MSGS) {
551 "the total number of pkgs to be fetched (%u) exceeds maximum %u\n",
553 ATH10K_SDIO_MAX_RX_MSGS);
558 for (i = 0; i < n_lookaheads; i++) {
559 htc_hdr = (struct ath10k_htc_hdr *)&lookaheads[i];
560 last_in_bundle = false;
562 if (le16_to_cpu(htc_hdr->len) >
563 ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH) {
565 "payload length %d exceeds max htc length: %zu\n",
566 le16_to_cpu(htc_hdr->len),
567 ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH);
572 act_len = le16_to_cpu(htc_hdr->len) + sizeof(*htc_hdr);
573 full_len = ath10k_sdio_calc_txrx_padded_len(ar_sdio, act_len);
575 if (full_len > ATH10K_SDIO_MAX_BUFFER_SIZE) {
577 "rx buffer requested with invalid htc_hdr length (%d, 0x%x): %d\n",
578 htc_hdr->eid, htc_hdr->flags,
579 le16_to_cpu(htc_hdr->len));
584 if (htc_hdr->flags & ATH10K_HTC_FLAG_BUNDLE_MASK) {
585 /* HTC header indicates that every packet to follow
586 * has the same padded length so that it can be
587 * optimally fetched as a full bundle.
591 ret = ath10k_sdio_mbox_alloc_pkt_bundle(ar,
592 &ar_sdio->rx_pkts[i],
598 n_lookaheads += bndl_cnt;
600 /*Next buffer will be the last in the bundle */
601 last_in_bundle = true;
604 /* Allocate skb for packet. If the packet had the
605 * ATH10K_HTC_FLAG_BUNDLE_MASK flag set, all bundled
606 * packet skb's have been allocated in the previous step.
608 if (htc_hdr->flags & ATH10K_HTC_FLAGS_RECV_1MORE_BLOCK)
609 full_len += ATH10K_HIF_MBOX_BLOCK_SIZE;
611 ret = ath10k_sdio_mbox_alloc_rx_pkt(&ar_sdio->rx_pkts[i],
618 ar_sdio->n_rx_pkts = i;
623 for (i = 0; i < ATH10K_SDIO_MAX_RX_MSGS; i++) {
624 if (!ar_sdio->rx_pkts[i].alloc_len)
626 ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]);
632 static int ath10k_sdio_mbox_rx_packet(struct ath10k *ar,
633 struct ath10k_sdio_rx_data *pkt)
635 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
636 struct sk_buff *skb = pkt->skb;
639 ret = ath10k_sdio_readsb(ar, ar_sdio->mbox_info.htc_addr,
640 skb->data, pkt->alloc_len);
643 skb_put(skb, pkt->act_len);
648 static int ath10k_sdio_mbox_rx_fetch(struct ath10k *ar)
650 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
653 for (i = 0; i < ar_sdio->n_rx_pkts; i++) {
654 ret = ath10k_sdio_mbox_rx_packet(ar,
655 &ar_sdio->rx_pkts[i]);
663 /* Free all packets that was not successfully fetched. */
664 for (; i < ar_sdio->n_rx_pkts; i++)
665 ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]);
670 /* This is the timeout for mailbox processing done in the sdio irq
671 * handler. The timeout is deliberately set quite high since SDIO dump logs
672 * over serial port can/will add a substantial overhead to the processing
675 #define SDIO_MBOX_PROCESSING_TIMEOUT_HZ (20 * HZ)
677 static int ath10k_sdio_mbox_rxmsg_pending_handler(struct ath10k *ar,
678 u32 msg_lookahead, bool *done)
680 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
681 u32 lookaheads[ATH10K_SDIO_MAX_RX_MSGS];
682 int n_lookaheads = 1;
683 unsigned long timeout;
688 /* Copy the lookahead obtained from the HTC register table into our
689 * temp array as a start value.
691 lookaheads[0] = msg_lookahead;
693 timeout = jiffies + SDIO_MBOX_PROCESSING_TIMEOUT_HZ;
695 /* Try to allocate as many HTC RX packets indicated by
698 ret = ath10k_sdio_mbox_rx_alloc(ar, lookaheads,
703 if (ar_sdio->n_rx_pkts >= 2)
704 /* A recv bundle was detected, force IRQ status
709 ret = ath10k_sdio_mbox_rx_fetch(ar);
711 /* Process fetched packets. This will potentially update
712 * n_lookaheads depending on if the packets contain lookahead
716 ret = ath10k_sdio_mbox_rx_process_packets(ar,
720 if (!n_lookaheads || ret)
723 /* For SYNCH processing, if we get here, we are running
724 * through the loop again due to updated lookaheads. Set
725 * flag that we should re-check IRQ status registers again
726 * before leaving IRQ processing, this can net better
727 * performance in high throughput situations.
730 } while (time_before(jiffies, timeout));
732 if (ret && (ret != -ECANCELED))
733 ath10k_warn(ar, "failed to get pending recv messages: %d\n",
739 static int ath10k_sdio_mbox_proc_dbg_intr(struct ath10k *ar)
744 /* TODO: Add firmware crash handling */
745 ath10k_warn(ar, "firmware crashed\n");
747 /* read counter to clear the interrupt, the debug error interrupt is
750 ret = ath10k_sdio_read32(ar, MBOX_COUNT_DEC_ADDRESS, &val);
752 ath10k_warn(ar, "failed to clear debug interrupt: %d\n", ret);
757 static int ath10k_sdio_mbox_proc_counter_intr(struct ath10k *ar)
759 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
760 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
761 u8 counter_int_status;
764 mutex_lock(&irq_data->mtx);
765 counter_int_status = irq_data->irq_proc_reg->counter_int_status &
766 irq_data->irq_en_reg->cntr_int_status_en;
768 /* NOTE: other modules like GMBOX may use the counter interrupt for
769 * credit flow control on other counters, we only need to check for
770 * the debug assertion counter interrupt.
772 if (counter_int_status & ATH10K_SDIO_TARGET_DEBUG_INTR_MASK)
773 ret = ath10k_sdio_mbox_proc_dbg_intr(ar);
777 mutex_unlock(&irq_data->mtx);
782 static int ath10k_sdio_mbox_proc_err_intr(struct ath10k *ar)
784 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
785 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
789 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio error interrupt\n");
791 error_int_status = irq_data->irq_proc_reg->error_int_status & 0x0F;
792 if (!error_int_status) {
793 ath10k_warn(ar, "invalid error interrupt status: 0x%x\n",
798 ath10k_dbg(ar, ATH10K_DBG_SDIO,
799 "sdio error_int_status 0x%x\n", error_int_status);
801 if (FIELD_GET(MBOX_ERROR_INT_STATUS_WAKEUP_MASK,
803 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio interrupt error wakeup\n");
805 if (FIELD_GET(MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
807 ath10k_warn(ar, "rx underflow interrupt error\n");
809 if (FIELD_GET(MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
811 ath10k_warn(ar, "tx overflow interrupt error\n");
813 /* Clear the interrupt */
814 irq_data->irq_proc_reg->error_int_status &= ~error_int_status;
816 /* set W1C value to clear the interrupt, this hits the register first */
817 ret = ath10k_sdio_writesb32(ar, MBOX_ERROR_INT_STATUS_ADDRESS,
820 ath10k_warn(ar, "unable to write to error int status address: %d\n",
828 static int ath10k_sdio_mbox_proc_cpu_intr(struct ath10k *ar)
830 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
831 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
835 mutex_lock(&irq_data->mtx);
836 cpu_int_status = irq_data->irq_proc_reg->cpu_int_status &
837 irq_data->irq_en_reg->cpu_int_status_en;
838 if (!cpu_int_status) {
839 ath10k_warn(ar, "CPU interrupt status is zero\n");
844 /* Clear the interrupt */
845 irq_data->irq_proc_reg->cpu_int_status &= ~cpu_int_status;
847 /* Set up the register transfer buffer to hit the register 4 times,
848 * this is done to make the access 4-byte aligned to mitigate issues
849 * with host bus interconnects that restrict bus transfer lengths to
850 * be a multiple of 4-bytes.
852 * Set W1C value to clear the interrupt, this hits the register first.
854 ret = ath10k_sdio_writesb32(ar, MBOX_CPU_INT_STATUS_ADDRESS,
857 ath10k_warn(ar, "unable to write to cpu interrupt status address: %d\n",
863 mutex_unlock(&irq_data->mtx);
867 static int ath10k_sdio_mbox_read_int_status(struct ath10k *ar,
871 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
872 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
873 struct ath10k_sdio_irq_proc_regs *irq_proc_reg = irq_data->irq_proc_reg;
874 struct ath10k_sdio_irq_enable_regs *irq_en_reg = irq_data->irq_en_reg;
875 u8 htc_mbox = FIELD_PREP(ATH10K_HTC_MAILBOX_MASK, 1);
878 mutex_lock(&irq_data->mtx);
881 *host_int_status = 0;
883 /* int_status_en is supposed to be non zero, otherwise interrupts
884 * shouldn't be enabled. There is however a short time frame during
885 * initialization between the irq register and int_status_en init
886 * where this can happen.
887 * We silently ignore this condition.
889 if (!irq_en_reg->int_status_en) {
894 /* Read the first sizeof(struct ath10k_irq_proc_registers)
895 * bytes of the HTC register table. This
896 * will yield us the value of different int status
897 * registers and the lookahead registers.
899 ret = ath10k_sdio_read(ar, MBOX_HOST_INT_STATUS_ADDRESS,
900 irq_proc_reg, sizeof(*irq_proc_reg));
904 /* Update only those registers that are enabled */
905 *host_int_status = irq_proc_reg->host_int_status &
906 irq_en_reg->int_status_en;
908 /* Look at mbox status */
909 if (!(*host_int_status & htc_mbox)) {
915 /* Mask out pending mbox value, we use look ahead as
916 * the real flag for mbox processing.
918 *host_int_status &= ~htc_mbox;
919 if (irq_proc_reg->rx_lookahead_valid & htc_mbox) {
920 *lookahead = le32_to_cpu(
921 irq_proc_reg->rx_lookahead[ATH10K_HTC_MAILBOX]);
923 ath10k_warn(ar, "sdio mbox lookahead is zero\n");
927 mutex_unlock(&irq_data->mtx);
931 static int ath10k_sdio_mbox_proc_pending_irqs(struct ath10k *ar,
938 /* NOTE: HIF implementation guarantees that the context of this
939 * call allows us to perform SYNCHRONOUS I/O, that is we can block,
940 * sleep or call any API that can block or switch thread/task
941 * contexts. This is a fully schedulable context.
944 ret = ath10k_sdio_mbox_read_int_status(ar,
952 if (!host_int_status && !lookahead) {
959 ath10k_dbg(ar, ATH10K_DBG_SDIO,
960 "sdio pending mailbox msg lookahead 0x%08x\n",
963 ret = ath10k_sdio_mbox_rxmsg_pending_handler(ar,
970 /* now, handle the rest of the interrupts */
971 ath10k_dbg(ar, ATH10K_DBG_SDIO,
972 "sdio host_int_status 0x%x\n", host_int_status);
974 if (FIELD_GET(MBOX_HOST_INT_STATUS_CPU_MASK, host_int_status)) {
976 ret = ath10k_sdio_mbox_proc_cpu_intr(ar);
981 if (FIELD_GET(MBOX_HOST_INT_STATUS_ERROR_MASK, host_int_status)) {
982 /* Error Interrupt */
983 ret = ath10k_sdio_mbox_proc_err_intr(ar);
988 if (FIELD_GET(MBOX_HOST_INT_STATUS_COUNTER_MASK, host_int_status))
989 /* Counter Interrupt */
990 ret = ath10k_sdio_mbox_proc_counter_intr(ar);
995 /* An optimization to bypass reading the IRQ status registers
996 * unecessarily which can re-wake the target, if upper layers
997 * determine that we are in a low-throughput mode, we can rely on
998 * taking another interrupt rather than re-checking the status
999 * registers which can re-wake the target.
1001 * NOTE : for host interfaces that makes use of detecting pending
1002 * mbox messages at hif can not use this optimization due to
1003 * possible side effects, SPI requires the host to drain all
1004 * messages from the mailbox before exiting the ISR routine.
1007 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1008 "sdio pending irqs done %d status %d",
1014 static void ath10k_sdio_set_mbox_info(struct ath10k *ar)
1016 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1017 struct ath10k_mbox_info *mbox_info = &ar_sdio->mbox_info;
1018 u16 device = ar_sdio->func->device, dev_id_base, dev_id_chiprev;
1020 mbox_info->htc_addr = ATH10K_HIF_MBOX_BASE_ADDR;
1021 mbox_info->block_size = ATH10K_HIF_MBOX_BLOCK_SIZE;
1022 mbox_info->block_mask = ATH10K_HIF_MBOX_BLOCK_SIZE - 1;
1023 mbox_info->gmbox_addr = ATH10K_HIF_GMBOX_BASE_ADDR;
1024 mbox_info->gmbox_sz = ATH10K_HIF_GMBOX_WIDTH;
1026 mbox_info->ext_info[0].htc_ext_addr = ATH10K_HIF_MBOX0_EXT_BASE_ADDR;
1028 dev_id_base = FIELD_GET(QCA_MANUFACTURER_ID_BASE, device);
1029 dev_id_chiprev = FIELD_GET(QCA_MANUFACTURER_ID_REV_MASK, device);
1030 switch (dev_id_base) {
1031 case QCA_MANUFACTURER_ID_AR6005_BASE:
1032 if (dev_id_chiprev < 4)
1033 mbox_info->ext_info[0].htc_ext_sz =
1034 ATH10K_HIF_MBOX0_EXT_WIDTH;
1036 /* from QCA6174 2.0(0x504), the width has been extended
1039 mbox_info->ext_info[0].htc_ext_sz =
1040 ATH10K_HIF_MBOX0_EXT_WIDTH_ROME_2_0;
1042 case QCA_MANUFACTURER_ID_QCA9377_BASE:
1043 mbox_info->ext_info[0].htc_ext_sz =
1044 ATH10K_HIF_MBOX0_EXT_WIDTH_ROME_2_0;
1047 mbox_info->ext_info[0].htc_ext_sz =
1048 ATH10K_HIF_MBOX0_EXT_WIDTH;
1051 mbox_info->ext_info[1].htc_ext_addr =
1052 mbox_info->ext_info[0].htc_ext_addr +
1053 mbox_info->ext_info[0].htc_ext_sz +
1054 ATH10K_HIF_MBOX_DUMMY_SPACE_SIZE;
1055 mbox_info->ext_info[1].htc_ext_sz = ATH10K_HIF_MBOX1_EXT_WIDTH;
1060 static int ath10k_sdio_bmi_credits(struct ath10k *ar)
1062 u32 addr, cmd_credits;
1063 unsigned long timeout;
1066 /* Read the counter register to get the command credits */
1067 addr = MBOX_COUNT_DEC_ADDRESS + ATH10K_HIF_MBOX_NUM_MAX * 4;
1068 timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1071 while (time_before(jiffies, timeout) && !cmd_credits) {
1072 /* Hit the credit counter with a 4-byte access, the first byte
1073 * read will hit the counter and cause a decrement, while the
1074 * remaining 3 bytes has no effect. The rationale behind this
1075 * is to make all HIF accesses 4-byte aligned.
1077 ret = ath10k_sdio_read32(ar, addr, &cmd_credits);
1080 "unable to decrement the command credit count register: %d\n",
1085 /* The counter is only 8 bits.
1086 * Ignore anything in the upper 3 bytes
1088 cmd_credits &= 0xFF;
1092 ath10k_warn(ar, "bmi communication timeout\n");
1099 static int ath10k_sdio_bmi_get_rx_lookahead(struct ath10k *ar)
1101 unsigned long timeout;
1105 timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1108 while ((time_before(jiffies, timeout)) && !rx_word) {
1109 ret = ath10k_sdio_read32(ar,
1110 MBOX_HOST_INT_STATUS_ADDRESS,
1113 ath10k_warn(ar, "unable to read RX_LOOKAHEAD_VALID: %d\n", ret);
1117 /* all we really want is one bit */
1122 ath10k_warn(ar, "bmi_recv_buf FIFO empty\n");
1129 static int ath10k_sdio_bmi_exchange_msg(struct ath10k *ar,
1130 void *req, u32 req_len,
1131 void *resp, u32 *resp_len)
1133 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1138 ret = ath10k_sdio_bmi_credits(ar);
1142 addr = ar_sdio->mbox_info.htc_addr;
1144 memcpy(ar_sdio->bmi_buf, req, req_len);
1145 ret = ath10k_sdio_write(ar, addr, ar_sdio->bmi_buf, req_len);
1148 "unable to send the bmi data to the device: %d\n",
1154 if (!resp || !resp_len)
1155 /* No response expected */
1158 /* During normal bootup, small reads may be required.
1159 * Rather than issue an HIF Read and then wait as the Target
1160 * adds successive bytes to the FIFO, we wait here until
1161 * we know that response data is available.
1163 * This allows us to cleanly timeout on an unexpected
1164 * Target failure rather than risk problems at the HIF level.
1165 * In particular, this avoids SDIO timeouts and possibly garbage
1166 * data on some host controllers. And on an interconnect
1167 * such as Compact Flash (as well as some SDIO masters) which
1168 * does not provide any indication on data timeout, it avoids
1169 * a potential hang or garbage response.
1171 * Synchronization is more difficult for reads larger than the
1172 * size of the MBOX FIFO (128B), because the Target is unable
1173 * to push the 129th byte of data until AFTER the Host posts an
1174 * HIF Read and removes some FIFO data. So for large reads the
1175 * Host proceeds to post an HIF Read BEFORE all the data is
1176 * actually available to read. Fortunately, large BMI reads do
1177 * not occur in practice -- they're supported for debug/development.
1179 * So Host/Target BMI synchronization is divided into these cases:
1180 * CASE 1: length < 4
1183 * CASE 2: 4 <= length <= 128
1184 * Wait for first 4 bytes to be in FIFO
1185 * If CONSERVATIVE_BMI_READ is enabled, also wait for
1186 * a BMI command credit, which indicates that the ENTIRE
1187 * response is available in the the FIFO
1189 * CASE 3: length > 128
1190 * Wait for the first 4 bytes to be in FIFO
1192 * For most uses, a small timeout should be sufficient and we will
1193 * usually see a response quickly; but there may be some unusual
1194 * (debug) cases of BMI_EXECUTE where we want an larger timeout.
1195 * For now, we use an unbounded busy loop while waiting for
1198 * If BMI_EXECUTE ever needs to support longer-latency execution,
1199 * especially in production, this code needs to be enhanced to sleep
1200 * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently
1201 * a function of Host processor speed.
1203 ret = ath10k_sdio_bmi_get_rx_lookahead(ar);
1207 /* We always read from the start of the mbox address */
1208 addr = ar_sdio->mbox_info.htc_addr;
1209 ret = ath10k_sdio_read(ar, addr, ar_sdio->bmi_buf, *resp_len);
1212 "unable to read the bmi data from the device: %d\n",
1217 memcpy(resp, ar_sdio->bmi_buf, *resp_len);
1222 /* sdio async handling functions */
1224 static struct ath10k_sdio_bus_request
1225 *ath10k_sdio_alloc_busreq(struct ath10k *ar)
1227 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1228 struct ath10k_sdio_bus_request *bus_req;
1230 spin_lock_bh(&ar_sdio->lock);
1232 if (list_empty(&ar_sdio->bus_req_freeq)) {
1237 bus_req = list_first_entry(&ar_sdio->bus_req_freeq,
1238 struct ath10k_sdio_bus_request, list);
1239 list_del(&bus_req->list);
1242 spin_unlock_bh(&ar_sdio->lock);
1246 static void ath10k_sdio_free_bus_req(struct ath10k *ar,
1247 struct ath10k_sdio_bus_request *bus_req)
1249 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1251 memset(bus_req, 0, sizeof(*bus_req));
1253 spin_lock_bh(&ar_sdio->lock);
1254 list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq);
1255 spin_unlock_bh(&ar_sdio->lock);
1258 static void __ath10k_sdio_write_async(struct ath10k *ar,
1259 struct ath10k_sdio_bus_request *req)
1261 struct ath10k_htc_ep *ep;
1262 struct sk_buff *skb;
1266 ret = ath10k_sdio_write(ar, req->address, skb->data, skb->len);
1268 ath10k_warn(ar, "failed to write skb to 0x%x asynchronously: %d",
1272 ep = &ar->htc.endpoint[req->eid];
1273 ath10k_htc_notify_tx_completion(ep, skb);
1274 } else if (req->comp) {
1275 complete(req->comp);
1278 ath10k_sdio_free_bus_req(ar, req);
1281 static void ath10k_sdio_write_async_work(struct work_struct *work)
1283 struct ath10k_sdio *ar_sdio = container_of(work, struct ath10k_sdio,
1285 struct ath10k *ar = ar_sdio->ar;
1286 struct ath10k_sdio_bus_request *req, *tmp_req;
1288 spin_lock_bh(&ar_sdio->wr_async_lock);
1290 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
1291 list_del(&req->list);
1292 spin_unlock_bh(&ar_sdio->wr_async_lock);
1293 __ath10k_sdio_write_async(ar, req);
1294 spin_lock_bh(&ar_sdio->wr_async_lock);
1297 spin_unlock_bh(&ar_sdio->wr_async_lock);
1300 static int ath10k_sdio_prep_async_req(struct ath10k *ar, u32 addr,
1301 struct sk_buff *skb,
1302 struct completion *comp,
1303 bool htc_msg, enum ath10k_htc_ep_id eid)
1305 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1306 struct ath10k_sdio_bus_request *bus_req;
1308 /* Allocate a bus request for the message and queue it on the
1311 bus_req = ath10k_sdio_alloc_busreq(ar);
1314 "unable to allocate bus request for async request\n");
1320 bus_req->address = addr;
1321 bus_req->htc_msg = htc_msg;
1322 bus_req->comp = comp;
1324 spin_lock_bh(&ar_sdio->wr_async_lock);
1325 list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq);
1326 spin_unlock_bh(&ar_sdio->wr_async_lock);
1333 static void ath10k_sdio_irq_handler(struct sdio_func *func)
1335 struct ath10k_sdio *ar_sdio = sdio_get_drvdata(func);
1336 struct ath10k *ar = ar_sdio->ar;
1337 unsigned long timeout;
1341 /* Release the host during interrupts so we can pick it back up when
1342 * we process commands.
1344 sdio_release_host(ar_sdio->func);
1346 timeout = jiffies + ATH10K_SDIO_HIF_COMMUNICATION_TIMEOUT_HZ;
1348 ret = ath10k_sdio_mbox_proc_pending_irqs(ar, &done);
1351 } while (time_before(jiffies, timeout) && !done);
1353 ath10k_mac_tx_push_pending(ar);
1355 sdio_claim_host(ar_sdio->func);
1357 if (ret && ret != -ECANCELED)
1358 ath10k_warn(ar, "failed to process pending SDIO interrupts: %d\n",
1362 /* sdio HIF functions */
1364 static int ath10k_sdio_hif_disable_intrs(struct ath10k *ar)
1366 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1367 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
1368 struct ath10k_sdio_irq_enable_regs *regs = irq_data->irq_en_reg;
1371 mutex_lock(&irq_data->mtx);
1373 memset(regs, 0, sizeof(*regs));
1374 ret = ath10k_sdio_write(ar, MBOX_INT_STATUS_ENABLE_ADDRESS,
1375 ®s->int_status_en, sizeof(*regs));
1377 ath10k_warn(ar, "unable to disable sdio interrupts: %d\n", ret);
1379 mutex_unlock(&irq_data->mtx);
1384 static int ath10k_sdio_hif_power_up(struct ath10k *ar,
1385 enum ath10k_firmware_mode fw_mode)
1387 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1388 struct sdio_func *func = ar_sdio->func;
1391 if (!ar_sdio->is_disabled)
1394 ath10k_dbg(ar, ATH10K_DBG_BOOT, "sdio power on\n");
1396 sdio_claim_host(func);
1398 ret = sdio_enable_func(func);
1400 ath10k_warn(ar, "unable to enable sdio function: %d)\n", ret);
1401 sdio_release_host(func);
1405 sdio_release_host(func);
1407 /* Wait for hardware to initialise. It should take a lot less than
1408 * 20 ms but let's be conservative here.
1412 ar_sdio->is_disabled = false;
1414 ret = ath10k_sdio_hif_disable_intrs(ar);
1421 static void ath10k_sdio_hif_power_down(struct ath10k *ar)
1423 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1426 if (ar_sdio->is_disabled)
1429 ath10k_dbg(ar, ATH10K_DBG_BOOT, "sdio power off\n");
1431 /* Disable the card */
1432 sdio_claim_host(ar_sdio->func);
1433 ret = sdio_disable_func(ar_sdio->func);
1434 sdio_release_host(ar_sdio->func);
1437 ath10k_warn(ar, "unable to disable sdio function: %d\n", ret);
1439 ar_sdio->is_disabled = true;
1442 static int ath10k_sdio_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
1443 struct ath10k_hif_sg_item *items, int n_items)
1445 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1446 enum ath10k_htc_ep_id eid;
1447 struct sk_buff *skb;
1450 eid = pipe_id_to_eid(pipe_id);
1452 for (i = 0; i < n_items; i++) {
1456 skb = items[i].transfer_context;
1457 padded_len = ath10k_sdio_calc_txrx_padded_len(ar_sdio,
1459 skb_trim(skb, padded_len);
1461 /* Write TX data to the end of the mbox address space */
1462 address = ar_sdio->mbox_addr[eid] + ar_sdio->mbox_size[eid] -
1464 ret = ath10k_sdio_prep_async_req(ar, address, skb,
1470 queue_work(ar_sdio->workqueue, &ar_sdio->wr_async_work);
1475 static int ath10k_sdio_hif_enable_intrs(struct ath10k *ar)
1477 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1478 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
1479 struct ath10k_sdio_irq_enable_regs *regs = irq_data->irq_en_reg;
1482 mutex_lock(&irq_data->mtx);
1484 /* Enable all but CPU interrupts */
1485 regs->int_status_en = FIELD_PREP(MBOX_INT_STATUS_ENABLE_ERROR_MASK, 1) |
1486 FIELD_PREP(MBOX_INT_STATUS_ENABLE_CPU_MASK, 1) |
1487 FIELD_PREP(MBOX_INT_STATUS_ENABLE_COUNTER_MASK, 1);
1489 /* NOTE: There are some cases where HIF can do detection of
1490 * pending mbox messages which is disabled now.
1492 regs->int_status_en |=
1493 FIELD_PREP(MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK, 1);
1495 /* Set up the CPU Interrupt status Register */
1496 regs->cpu_int_status_en = 0;
1498 /* Set up the Error Interrupt status Register */
1499 regs->err_int_status_en =
1500 FIELD_PREP(MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK, 1) |
1501 FIELD_PREP(MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK, 1);
1503 /* Enable Counter interrupt status register to get fatal errors for
1506 regs->cntr_int_status_en =
1507 FIELD_PREP(MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
1508 ATH10K_SDIO_TARGET_DEBUG_INTR_MASK);
1510 ret = ath10k_sdio_write(ar, MBOX_INT_STATUS_ENABLE_ADDRESS,
1511 ®s->int_status_en, sizeof(*regs));
1514 "failed to update mbox interrupt status register : %d\n",
1517 mutex_unlock(&irq_data->mtx);
1521 static int ath10k_sdio_hif_set_mbox_sleep(struct ath10k *ar, bool enable_sleep)
1526 ret = ath10k_sdio_read32(ar, ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL, &val);
1528 ath10k_warn(ar, "failed to read fifo/chip control register: %d\n",
1534 val &= ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_OFF;
1536 val |= ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_ON;
1538 ret = ath10k_sdio_write32(ar, ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL, val);
1540 ath10k_warn(ar, "failed to write to FIFO_TIMEOUT_AND_CHIP_CONTROL: %d",
1548 /* HIF diagnostics */
1550 static int ath10k_sdio_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
1555 /* set window register to start read cycle */
1556 ret = ath10k_sdio_write32(ar, MBOX_WINDOW_READ_ADDR_ADDRESS, address);
1558 ath10k_warn(ar, "failed to set mbox window read address: %d", ret);
1563 ret = ath10k_sdio_read(ar, MBOX_WINDOW_DATA_ADDRESS, buf, buf_len);
1565 ath10k_warn(ar, "failed to read from mbox window data address: %d\n",
1573 static int ath10k_sdio_hif_diag_read32(struct ath10k *ar, u32 address,
1579 val = kzalloc(sizeof(*val), GFP_KERNEL);
1583 ret = ath10k_sdio_hif_diag_read(ar, address, val, sizeof(*val));
1587 *value = __le32_to_cpu(*val);
1595 static int ath10k_sdio_hif_diag_write_mem(struct ath10k *ar, u32 address,
1596 const void *data, int nbytes)
1600 /* set write data */
1601 ret = ath10k_sdio_write(ar, MBOX_WINDOW_DATA_ADDRESS, data, nbytes);
1604 "failed to write 0x%p to mbox window data address: %d\n",
1609 /* set window register, which starts the write cycle */
1610 ret = ath10k_sdio_write32(ar, MBOX_WINDOW_WRITE_ADDR_ADDRESS, address);
1612 ath10k_warn(ar, "failed to set mbox window write address: %d", ret);
1619 static int ath10k_sdio_hif_swap_mailbox(struct ath10k *ar)
1621 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1625 addr = host_interest_item_address(HI_ITEM(hi_acs_flags));
1627 ret = ath10k_sdio_hif_diag_read32(ar, addr, &val);
1629 ath10k_warn(ar, "unable to read hi_acs_flags : %d\n", ret);
1633 if (val & HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_FW_ACK) {
1634 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1635 "sdio mailbox swap service enabled\n");
1636 ar_sdio->swap_mbox = true;
1641 /* HIF start/stop */
1643 static int ath10k_sdio_hif_start(struct ath10k *ar)
1645 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1648 /* Sleep 20 ms before HIF interrupts are disabled.
1649 * This will give target plenty of time to process the BMI done
1650 * request before interrupts are disabled.
1653 ret = ath10k_sdio_hif_disable_intrs(ar);
1657 /* eid 0 always uses the lower part of the extended mailbox address
1658 * space (ext_info[0].htc_ext_addr).
1660 ar_sdio->mbox_addr[0] = ar_sdio->mbox_info.ext_info[0].htc_ext_addr;
1661 ar_sdio->mbox_size[0] = ar_sdio->mbox_info.ext_info[0].htc_ext_sz;
1663 sdio_claim_host(ar_sdio->func);
1665 /* Register the isr */
1666 ret = sdio_claim_irq(ar_sdio->func, ath10k_sdio_irq_handler);
1668 ath10k_warn(ar, "failed to claim sdio interrupt: %d\n", ret);
1669 sdio_release_host(ar_sdio->func);
1673 sdio_release_host(ar_sdio->func);
1675 ret = ath10k_sdio_hif_enable_intrs(ar);
1677 ath10k_warn(ar, "failed to enable sdio interrupts: %d\n", ret);
1679 /* Enable sleep and then disable it again */
1680 ret = ath10k_sdio_hif_set_mbox_sleep(ar, true);
1684 /* Wait for 20ms for the written value to take effect */
1687 ret = ath10k_sdio_hif_set_mbox_sleep(ar, false);
1694 #define SDIO_IRQ_DISABLE_TIMEOUT_HZ (3 * HZ)
1696 static void ath10k_sdio_irq_disable(struct ath10k *ar)
1698 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1699 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data;
1700 struct ath10k_sdio_irq_enable_regs *regs = irq_data->irq_en_reg;
1701 struct sk_buff *skb;
1702 struct completion irqs_disabled_comp;
1705 skb = dev_alloc_skb(sizeof(*regs));
1709 mutex_lock(&irq_data->mtx);
1711 memset(regs, 0, sizeof(*regs)); /* disable all interrupts */
1712 memcpy(skb->data, regs, sizeof(*regs));
1713 skb_put(skb, sizeof(*regs));
1715 mutex_unlock(&irq_data->mtx);
1717 init_completion(&irqs_disabled_comp);
1718 ret = ath10k_sdio_prep_async_req(ar, MBOX_INT_STATUS_ENABLE_ADDRESS,
1719 skb, &irqs_disabled_comp, false, 0);
1723 queue_work(ar_sdio->workqueue, &ar_sdio->wr_async_work);
1725 /* Wait for the completion of the IRQ disable request.
1726 * If there is a timeout we will try to disable irq's anyway.
1728 ret = wait_for_completion_timeout(&irqs_disabled_comp,
1729 SDIO_IRQ_DISABLE_TIMEOUT_HZ);
1731 ath10k_warn(ar, "sdio irq disable request timed out\n");
1733 sdio_claim_host(ar_sdio->func);
1735 ret = sdio_release_irq(ar_sdio->func);
1737 ath10k_warn(ar, "failed to release sdio interrupt: %d\n", ret);
1739 sdio_release_host(ar_sdio->func);
1745 static void ath10k_sdio_hif_stop(struct ath10k *ar)
1747 struct ath10k_sdio_bus_request *req, *tmp_req;
1748 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1750 ath10k_sdio_irq_disable(ar);
1752 cancel_work_sync(&ar_sdio->wr_async_work);
1754 spin_lock_bh(&ar_sdio->wr_async_lock);
1756 /* Free all bus requests that have not been handled */
1757 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
1758 struct ath10k_htc_ep *ep;
1760 list_del(&req->list);
1763 ep = &ar->htc.endpoint[req->eid];
1764 ath10k_htc_notify_tx_completion(ep, req->skb);
1765 } else if (req->skb) {
1766 kfree_skb(req->skb);
1768 ath10k_sdio_free_bus_req(ar, req);
1771 spin_unlock_bh(&ar_sdio->wr_async_lock);
1776 static int ath10k_sdio_hif_suspend(struct ath10k *ar)
1781 static int ath10k_sdio_hif_resume(struct ath10k *ar)
1783 switch (ar->state) {
1784 case ATH10K_STATE_OFF:
1785 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1786 "sdio resume configuring sdio\n");
1788 /* need to set sdio settings after power is cut from sdio */
1789 ath10k_sdio_config(ar);
1792 case ATH10K_STATE_ON:
1801 static int ath10k_sdio_hif_map_service_to_pipe(struct ath10k *ar,
1803 u8 *ul_pipe, u8 *dl_pipe)
1805 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
1806 struct ath10k_htc *htc = &ar->htc;
1807 u32 htt_addr, wmi_addr, htt_mbox_size, wmi_mbox_size;
1808 enum ath10k_htc_ep_id eid;
1809 bool ep_found = false;
1812 /* For sdio, we are interested in the mapping between eid
1813 * and pipeid rather than service_id to pipe_id.
1814 * First we find out which eid has been allocated to the
1817 for (i = 0; i < ATH10K_HTC_EP_COUNT; i++) {
1818 if (htc->endpoint[i].service_id == service_id) {
1819 eid = htc->endpoint[i].eid;
1828 /* Then we create the simplest mapping possible between pipeid
1831 *ul_pipe = *dl_pipe = (u8)eid;
1833 /* Normally, HTT will use the upper part of the extended
1834 * mailbox address space (ext_info[1].htc_ext_addr) and WMI ctrl
1835 * the lower part (ext_info[0].htc_ext_addr).
1836 * If fw wants swapping of mailbox addresses, the opposite is true.
1838 if (ar_sdio->swap_mbox) {
1839 htt_addr = ar_sdio->mbox_info.ext_info[0].htc_ext_addr;
1840 wmi_addr = ar_sdio->mbox_info.ext_info[1].htc_ext_addr;
1841 htt_mbox_size = ar_sdio->mbox_info.ext_info[0].htc_ext_sz;
1842 wmi_mbox_size = ar_sdio->mbox_info.ext_info[1].htc_ext_sz;
1844 htt_addr = ar_sdio->mbox_info.ext_info[1].htc_ext_addr;
1845 wmi_addr = ar_sdio->mbox_info.ext_info[0].htc_ext_addr;
1846 htt_mbox_size = ar_sdio->mbox_info.ext_info[1].htc_ext_sz;
1847 wmi_mbox_size = ar_sdio->mbox_info.ext_info[0].htc_ext_sz;
1850 switch (service_id) {
1851 case ATH10K_HTC_SVC_ID_RSVD_CTRL:
1852 /* HTC ctrl ep mbox address has already been setup in
1853 * ath10k_sdio_hif_start
1856 case ATH10K_HTC_SVC_ID_WMI_CONTROL:
1857 ar_sdio->mbox_addr[eid] = wmi_addr;
1858 ar_sdio->mbox_size[eid] = wmi_mbox_size;
1859 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1860 "sdio wmi ctrl mbox_addr 0x%x mbox_size %d\n",
1861 ar_sdio->mbox_addr[eid], ar_sdio->mbox_size[eid]);
1863 case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
1864 ar_sdio->mbox_addr[eid] = htt_addr;
1865 ar_sdio->mbox_size[eid] = htt_mbox_size;
1866 ath10k_dbg(ar, ATH10K_DBG_SDIO,
1867 "sdio htt data mbox_addr 0x%x mbox_size %d\n",
1868 ar_sdio->mbox_addr[eid], ar_sdio->mbox_size[eid]);
1871 ath10k_warn(ar, "unsupported HTC service id: %d\n",
1879 static void ath10k_sdio_hif_get_default_pipe(struct ath10k *ar,
1880 u8 *ul_pipe, u8 *dl_pipe)
1882 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio hif get default pipe\n");
1884 /* HTC ctrl ep (SVC id 1) always has eid (and pipe_id in our
1891 /* This op is currently only used by htc_wait_target if the HTC ready
1892 * message times out. It is not applicable for SDIO since there is nothing
1893 * we can do if the HTC ready message does not arrive in time.
1894 * TODO: Make this op non mandatory by introducing a NULL check in the
1897 static void ath10k_sdio_hif_send_complete_check(struct ath10k *ar,
1902 static const struct ath10k_hif_ops ath10k_sdio_hif_ops = {
1903 .tx_sg = ath10k_sdio_hif_tx_sg,
1904 .diag_read = ath10k_sdio_hif_diag_read,
1905 .diag_write = ath10k_sdio_hif_diag_write_mem,
1906 .exchange_bmi_msg = ath10k_sdio_bmi_exchange_msg,
1907 .start = ath10k_sdio_hif_start,
1908 .stop = ath10k_sdio_hif_stop,
1909 .swap_mailbox = ath10k_sdio_hif_swap_mailbox,
1910 .map_service_to_pipe = ath10k_sdio_hif_map_service_to_pipe,
1911 .get_default_pipe = ath10k_sdio_hif_get_default_pipe,
1912 .send_complete_check = ath10k_sdio_hif_send_complete_check,
1913 .power_up = ath10k_sdio_hif_power_up,
1914 .power_down = ath10k_sdio_hif_power_down,
1916 .suspend = ath10k_sdio_hif_suspend,
1917 .resume = ath10k_sdio_hif_resume,
1921 #ifdef CONFIG_PM_SLEEP
1923 /* Empty handlers so that mmc subsystem doesn't remove us entirely during
1924 * suspend. We instead follow cfg80211 suspend/resume handlers.
1926 static int ath10k_sdio_pm_suspend(struct device *device)
1931 static int ath10k_sdio_pm_resume(struct device *device)
1936 static SIMPLE_DEV_PM_OPS(ath10k_sdio_pm_ops, ath10k_sdio_pm_suspend,
1937 ath10k_sdio_pm_resume);
1939 #define ATH10K_SDIO_PM_OPS (&ath10k_sdio_pm_ops)
1943 #define ATH10K_SDIO_PM_OPS NULL
1945 #endif /* CONFIG_PM_SLEEP */
1947 static int ath10k_sdio_probe(struct sdio_func *func,
1948 const struct sdio_device_id *id)
1950 struct ath10k_sdio *ar_sdio;
1952 enum ath10k_hw_rev hw_rev;
1954 struct ath10k_bus_params bus_params;
1957 /* Assumption: All SDIO based chipsets (so far) are QCA6174 based.
1958 * If there will be newer chipsets that does not use the hw reg
1959 * setup as defined in qca6174_regs and qca6174_values, this
1960 * assumption is no longer valid and hw_rev must be setup differently
1961 * depending on chipset.
1963 hw_rev = ATH10K_HW_QCA6174;
1965 ar = ath10k_core_create(sizeof(*ar_sdio), &func->dev, ATH10K_BUS_SDIO,
1966 hw_rev, &ath10k_sdio_hif_ops);
1968 dev_err(&func->dev, "failed to allocate core\n");
1972 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1973 "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n",
1974 func->num, func->vendor, func->device,
1975 func->max_blksize, func->cur_blksize);
1977 ar_sdio = ath10k_sdio_priv(ar);
1979 ar_sdio->irq_data.irq_proc_reg =
1980 devm_kzalloc(ar->dev, sizeof(struct ath10k_sdio_irq_proc_regs),
1982 if (!ar_sdio->irq_data.irq_proc_reg) {
1984 goto err_core_destroy;
1987 ar_sdio->irq_data.irq_en_reg =
1988 devm_kzalloc(ar->dev, sizeof(struct ath10k_sdio_irq_enable_regs),
1990 if (!ar_sdio->irq_data.irq_en_reg) {
1992 goto err_core_destroy;
1995 ar_sdio->bmi_buf = devm_kzalloc(ar->dev, BMI_MAX_CMDBUF_SIZE, GFP_KERNEL);
1996 if (!ar_sdio->bmi_buf) {
1998 goto err_core_destroy;
2001 ar_sdio->func = func;
2002 sdio_set_drvdata(func, ar_sdio);
2004 ar_sdio->is_disabled = true;
2007 spin_lock_init(&ar_sdio->lock);
2008 spin_lock_init(&ar_sdio->wr_async_lock);
2009 mutex_init(&ar_sdio->irq_data.mtx);
2011 INIT_LIST_HEAD(&ar_sdio->bus_req_freeq);
2012 INIT_LIST_HEAD(&ar_sdio->wr_asyncq);
2014 INIT_WORK(&ar_sdio->wr_async_work, ath10k_sdio_write_async_work);
2015 ar_sdio->workqueue = create_singlethread_workqueue("ath10k_sdio_wq");
2016 if (!ar_sdio->workqueue) {
2018 goto err_core_destroy;
2021 for (i = 0; i < ATH10K_SDIO_BUS_REQUEST_MAX_NUM; i++)
2022 ath10k_sdio_free_bus_req(ar, &ar_sdio->bus_req[i]);
2024 dev_id_base = FIELD_GET(QCA_MANUFACTURER_ID_BASE, id->device);
2025 switch (dev_id_base) {
2026 case QCA_MANUFACTURER_ID_AR6005_BASE:
2027 case QCA_MANUFACTURER_ID_QCA9377_BASE:
2028 ar->dev_id = QCA9377_1_0_DEVICE_ID;
2032 ath10k_err(ar, "unsupported device id %u (0x%x)\n",
2033 dev_id_base, id->device);
2037 ar->id.vendor = id->vendor;
2038 ar->id.device = id->device;
2040 ath10k_sdio_set_mbox_info(ar);
2042 ret = ath10k_sdio_config(ar);
2044 ath10k_err(ar, "failed to config sdio: %d\n", ret);
2048 bus_params.dev_type = ATH10K_DEV_TYPE_HL;
2049 /* TODO: don't know yet how to get chip_id with SDIO */
2050 bus_params.chip_id = 0;
2051 ret = ath10k_core_register(ar, &bus_params);
2053 ath10k_err(ar, "failed to register driver core: %d\n", ret);
2057 /* TODO: remove this once SDIO support is fully implemented */
2058 ath10k_warn(ar, "WARNING: ath10k SDIO support is incomplete, don't expect anything to work!\n");
2063 destroy_workqueue(ar_sdio->workqueue);
2065 ath10k_core_destroy(ar);
2070 static void ath10k_sdio_remove(struct sdio_func *func)
2072 struct ath10k_sdio *ar_sdio = sdio_get_drvdata(func);
2073 struct ath10k *ar = ar_sdio->ar;
2075 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2076 "sdio removed func %d vendor 0x%x device 0x%x\n",
2077 func->num, func->vendor, func->device);
2079 (void)ath10k_sdio_hif_disable_intrs(ar);
2080 cancel_work_sync(&ar_sdio->wr_async_work);
2081 ath10k_core_unregister(ar);
2082 ath10k_core_destroy(ar);
2085 static const struct sdio_device_id ath10k_sdio_devices[] = {
2086 {SDIO_DEVICE(QCA_MANUFACTURER_CODE,
2087 (QCA_SDIO_ID_AR6005_BASE | 0xA))},
2088 {SDIO_DEVICE(QCA_MANUFACTURER_CODE,
2089 (QCA_SDIO_ID_QCA9377_BASE | 0x1))},
2093 MODULE_DEVICE_TABLE(sdio, ath10k_sdio_devices);
2095 static struct sdio_driver ath10k_sdio_driver = {
2096 .name = "ath10k_sdio",
2097 .id_table = ath10k_sdio_devices,
2098 .probe = ath10k_sdio_probe,
2099 .remove = ath10k_sdio_remove,
2101 .owner = THIS_MODULE,
2102 .pm = ATH10K_SDIO_PM_OPS,
2106 static int __init ath10k_sdio_init(void)
2110 ret = sdio_register_driver(&ath10k_sdio_driver);
2112 pr_err("sdio driver registration failed: %d\n", ret);
2117 static void __exit ath10k_sdio_exit(void)
2119 sdio_unregister_driver(&ath10k_sdio_driver);
2122 module_init(ath10k_sdio_init);
2123 module_exit(ath10k_sdio_exit);
2125 MODULE_AUTHOR("Qualcomm Atheros");
2126 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN SDIO devices");
2127 MODULE_LICENSE("Dual BSD/GPL");