2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include <linux/interrupt.h>
28 * maximum number of bytes that can be handled atomically by DiagRead/DiagWrite
30 #define DIAG_TRANSFER_LIMIT 2048
33 * maximum number of bytes that can be
34 * handled atomically by DiagRead/DiagWrite
36 #define DIAG_TRANSFER_LIMIT 2048
46 * PCI-specific Target state
48 * NOTE: Structure is shared between Host software and Target firmware!
50 * Much of this may be of interest to the Host so
51 * HOST_INTEREST->hi_interconnect_state points here
52 * (and all members are 32-bit quantities in order to
53 * facilitate Host access). In particular, Host software is
54 * required to initialize pipe_cfg_addr and svc_to_pipe_map.
57 /* Pipe configuration Target address */
58 /* NB: ce_pipe_config[CE_COUNT] */
61 /* Service to pipe map Target address */
62 /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
65 /* number of MSI interrupts requested */
68 /* number of MSI interrupts granted */
71 /* Message Signalled Interrupt address */
78 * Data for firmware interrupt;
79 * MSI data for other interrupts are
80 * in various SoC registers
84 /* PCIE_PWR_METHOD_* */
85 u32 power_mgmt_method;
87 /* PCIE_CONFIG_FLAG_* */
91 /* PCIE_CONFIG_FLAG definitions */
92 #define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
94 /* Host software's Copy Engine configuration. */
95 #define CE_ATTR_FLAGS 0
98 * Configuration information for a Copy Engine pipe.
99 * Passed from Host to Target during startup (one per CE).
101 * NOTE: Structure is shared between Host software and Target firmware!
103 struct ce_pipe_config {
113 * Directions for interconnect pipe configuration.
114 * These definitions may be used during configuration and are shared
115 * between Host and Target.
117 * Pipe Directions are relative to the Host, so PIPEDIR_IN means
118 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
119 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
120 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
121 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
122 * over the interconnect.
124 #define PIPEDIR_NONE 0
125 #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
126 #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
127 #define PIPEDIR_INOUT 3 /* bidirectional */
129 /* Establish a mapping between a service/direction and a pipe. */
130 struct service_to_pipe {
136 /* Per-pipe state. */
137 struct ath10k_pci_pipe {
138 /* Handle of underlying Copy Engine */
139 struct ath10k_ce_pipe *ce_hdl;
141 /* Our pipe number; facilitiates use of pipe_info ptrs. */
144 /* Convenience back pointer to hif_ce_state. */
145 struct ath10k *hif_ce_state;
149 /* protects compl_free and num_send_allowed */
150 spinlock_t pipe_lock;
153 struct ath10k_pci_supp_chip {
158 struct ath10k_bus_ops {
159 u32 (*read32)(struct ath10k *ar, u32 offset);
160 void (*write32)(struct ath10k *ar, u32 offset, u32 value);
161 int (*get_num_banks)(struct ath10k *ar);
164 enum ath10k_pci_irq_mode {
165 ATH10K_PCI_IRQ_AUTO = 0,
166 ATH10K_PCI_IRQ_LEGACY = 1,
167 ATH10K_PCI_IRQ_MSI = 2,
171 struct pci_dev *pdev;
177 /* Operating interrupt mode */
178 enum ath10k_pci_irq_mode oper_irq_mode;
180 struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
182 /* Copy Engine used for Diagnostic Accesses */
183 struct ath10k_ce_pipe *ce_diag;
185 /* FIXME: document what this really protects */
188 /* Map CE id to ce_state */
189 struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
190 struct timer_list rx_post_retry;
192 /* Due to HW quirks it is recommended to disable ASPM during device
193 * bootup. To do that the original PCI-E Link Control is stored before
194 * device bootup is executed and re-programmed later.
198 /* Protects ps_awake and ps_wake_refcount */
201 /* The device has a special powersave-oriented register. When device is
202 * considered asleep it drains less power and driver is forbidden from
203 * accessing most MMIO registers. If host were to access them without
204 * waking up the device might scribble over host memory or return
205 * 0xdeadbeef readouts.
207 unsigned long ps_wake_refcount;
209 /* Waking up takes some time (up to 2ms in some cases) so it can be bad
210 * for latency. To mitigate this the device isn't immediately allowed
211 * to sleep after all references are undone - instead there's a grace
212 * period after which the powersave register is updated unless some
213 * activity to/from device happened in the meantime.
215 * Also see comments on ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC.
217 struct timer_list ps_timer;
219 /* MMIO registers are used to communicate with the device. With
220 * intensive traffic accessing powersave register would be a bit
221 * wasteful overhead and would needlessly stall CPU. It is far more
222 * efficient to rely on a variable in RAM and update it only upon
223 * powersave register state changes.
227 /* pci power save, disable for QCA988X and QCA99X0.
228 * Writing 'false' to this variable avoids frequent locking
229 * on MMIO read/write.
233 const struct ath10k_bus_ops *bus_ops;
235 /* Chip specific pci reset routine used to do a safe reset */
236 int (*pci_soft_reset)(struct ath10k *ar);
238 /* Chip specific pci full reset function */
239 int (*pci_hard_reset)(struct ath10k *ar);
241 /* Keep this entry in the last, memory for struct ath10k_ahb is
242 * allocated (ahb support enabled case) in the continuation of
245 struct ath10k_ahb ahb[0];
248 static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
250 return (struct ath10k_pci *)ar->drv_priv;
253 #define ATH10K_PCI_RX_POST_RETRY_MS 50
254 #define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
255 #define PCIE_WAKE_TIMEOUT 30000 /* 30ms */
256 #define PCIE_WAKE_LATE_US 10000 /* 10ms */
260 #define CDC_WAR_MAGIC_STR 0xceef0000
261 #define CDC_WAR_DATA_CE 4
263 /* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
264 #define DIAG_ACCESS_CE_TIMEOUT_MS 10
266 void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value);
267 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val);
268 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val);
270 u32 ath10k_pci_read32(struct ath10k *ar, u32 offset);
271 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr);
272 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr);
274 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
275 struct ath10k_hif_sg_item *items, int n_items);
276 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
278 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
279 const void *data, int nbytes);
280 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len,
281 void *resp, u32 *resp_len);
282 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
283 u8 *ul_pipe, u8 *dl_pipe);
284 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe,
286 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
288 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe);
289 void ath10k_pci_hif_power_down(struct ath10k *ar);
290 int ath10k_pci_alloc_pipes(struct ath10k *ar);
291 void ath10k_pci_free_pipes(struct ath10k *ar);
292 void ath10k_pci_free_pipes(struct ath10k *ar);
293 void ath10k_pci_rx_replenish_retry(unsigned long ptr);
294 void ath10k_pci_ce_deinit(struct ath10k *ar);
295 void ath10k_pci_init_napi(struct ath10k *ar);
296 int ath10k_pci_init_pipes(struct ath10k *ar);
297 int ath10k_pci_init_config(struct ath10k *ar);
298 void ath10k_pci_rx_post(struct ath10k *ar);
299 void ath10k_pci_flush(struct ath10k *ar);
300 void ath10k_pci_enable_legacy_irq(struct ath10k *ar);
301 bool ath10k_pci_irq_pending(struct ath10k *ar);
302 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar);
303 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar);
304 int ath10k_pci_wait_for_target_init(struct ath10k *ar);
305 int ath10k_pci_setup_resource(struct ath10k *ar);
306 void ath10k_pci_release_resource(struct ath10k *ar);
308 /* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too
309 * frequently. To avoid this put SoC to sleep after a very conservative grace
310 * period. Adjust with great care.
312 #define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC 60