drivers/net/wireless/ath/ath10k/hw.c

   1 /*
   2  * Copyright (c) 2014-2017 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/types.h>
  18 #include <linux/bitops.h>
  19 #include <linux/bitfield.h>
  20 #include "core.h"
  21 #include "hw.h"
  22 #include "hif.h"
  23 #include "wmi-ops.h"
  24 #include "bmi.h"
  25
  26 const struct ath10k_hw_regs qca988x_regs = {
  27         .rtc_soc_base_address           = 0x00004000,
  28         .rtc_wmac_base_address          = 0x00005000,
  29         .soc_core_base_address          = 0x00009000,
  30         .wlan_mac_base_address          = 0x00020000,
  31         .ce_wrapper_base_address        = 0x00057000,
  32         .ce0_base_address               = 0x00057400,
  33         .ce1_base_address               = 0x00057800,
  34         .ce2_base_address               = 0x00057c00,
  35         .ce3_base_address               = 0x00058000,
  36         .ce4_base_address               = 0x00058400,
  37         .ce5_base_address               = 0x00058800,
  38         .ce6_base_address               = 0x00058c00,
  39         .ce7_base_address               = 0x00059000,
  40         .soc_reset_control_si0_rst_mask = 0x00000001,
  41         .soc_reset_control_ce_rst_mask  = 0x00040000,
  42         .soc_chip_id_address            = 0x000000ec,
  43         .scratch_3_address              = 0x00000030,
  44         .fw_indicator_address           = 0x00009030,
  45         .pcie_local_base_address        = 0x00080000,
  46         .ce_wrap_intr_sum_host_msi_lsb  = 0x00000008,
  47         .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
  48         .pcie_intr_fw_mask              = 0x00000400,
  49         .pcie_intr_ce_mask_all          = 0x0007f800,
  50         .pcie_intr_clr_address          = 0x00000014,
  51 };
  52
  53 const struct ath10k_hw_regs qca6174_regs = {
  54         .rtc_soc_base_address                   = 0x00000800,
  55         .rtc_wmac_base_address                  = 0x00001000,
  56         .soc_core_base_address                  = 0x0003a000,
  57         .wlan_mac_base_address                  = 0x00010000,
  58         .ce_wrapper_base_address                = 0x00034000,
  59         .ce0_base_address                       = 0x00034400,
  60         .ce1_base_address                       = 0x00034800,
  61         .ce2_base_address                       = 0x00034c00,
  62         .ce3_base_address                       = 0x00035000,
  63         .ce4_base_address                       = 0x00035400,
  64         .ce5_base_address                       = 0x00035800,
  65         .ce6_base_address                       = 0x00035c00,
  66         .ce7_base_address                       = 0x00036000,
  67         .soc_reset_control_si0_rst_mask         = 0x00000000,
  68         .soc_reset_control_ce_rst_mask          = 0x00000001,
  69         .soc_chip_id_address                    = 0x000000f0,
  70         .scratch_3_address                      = 0x00000028,
  71         .fw_indicator_address                   = 0x0003a028,
  72         .pcie_local_base_address                = 0x00080000,
  73         .ce_wrap_intr_sum_host_msi_lsb          = 0x00000008,
  74         .ce_wrap_intr_sum_host_msi_mask         = 0x0000ff00,
  75         .pcie_intr_fw_mask                      = 0x00000400,
  76         .pcie_intr_ce_mask_all                  = 0x0007f800,
  77         .pcie_intr_clr_address                  = 0x00000014,
  78         .cpu_pll_init_address                   = 0x00404020,
  79         .cpu_speed_address                      = 0x00404024,
  80         .core_clk_div_address                   = 0x00404028,
  81 };
  82
  83 const struct ath10k_hw_regs qca99x0_regs = {
  84         .rtc_soc_base_address                   = 0x00080000,
  85         .rtc_wmac_base_address                  = 0x00000000,
  86         .soc_core_base_address                  = 0x00082000,
  87         .wlan_mac_base_address                  = 0x00030000,
  88         .ce_wrapper_base_address                = 0x0004d000,
  89         .ce0_base_address                       = 0x0004a000,
  90         .ce1_base_address                       = 0x0004a400,
  91         .ce2_base_address                       = 0x0004a800,
  92         .ce3_base_address                       = 0x0004ac00,
  93         .ce4_base_address                       = 0x0004b000,
  94         .ce5_base_address                       = 0x0004b400,
  95         .ce6_base_address                       = 0x0004b800,
  96         .ce7_base_address                       = 0x0004bc00,
  97         /* Note: qca99x0 supports upto 12 Copy Engines. Other than address of
  98          * CE0 and CE1 no other copy engine is directly referred in the code.
  99          * It is not really necessary to assign address for newly supported
 100          * CEs in this address table.
 101          *      Copy Engine             Address
 102          *      CE8                     0x0004c000
 103          *      CE9                     0x0004c400
 104          *      CE10                    0x0004c800
 105          *      CE11                    0x0004cc00
 106          */
 107         .soc_reset_control_si0_rst_mask         = 0x00000001,
 108         .soc_reset_control_ce_rst_mask          = 0x00000100,
 109         .soc_chip_id_address                    = 0x000000ec,
 110         .scratch_3_address                      = 0x00040050,
 111         .fw_indicator_address                   = 0x00040050,
 112         .pcie_local_base_address                = 0x00000000,
 113         .ce_wrap_intr_sum_host_msi_lsb          = 0x0000000c,
 114         .ce_wrap_intr_sum_host_msi_mask         = 0x00fff000,
 115         .pcie_intr_fw_mask                      = 0x00100000,
 116         .pcie_intr_ce_mask_all                  = 0x000fff00,
 117         .pcie_intr_clr_address                  = 0x00000010,
 118 };
 119
 120 const struct ath10k_hw_regs qca4019_regs = {
 121         .rtc_soc_base_address                   = 0x00080000,
 122         .soc_core_base_address                  = 0x00082000,
 123         .wlan_mac_base_address                  = 0x00030000,
 124         .ce_wrapper_base_address                = 0x0004d000,
 125         .ce0_base_address                       = 0x0004a000,
 126         .ce1_base_address                       = 0x0004a400,
 127         .ce2_base_address                       = 0x0004a800,
 128         .ce3_base_address                       = 0x0004ac00,
 129         .ce4_base_address                       = 0x0004b000,
 130         .ce5_base_address                       = 0x0004b400,
 131         .ce6_base_address                       = 0x0004b800,
 132         .ce7_base_address                       = 0x0004bc00,
 133         /* qca4019 supports upto 12 copy engines. Since base address
 134          * of ce8 to ce11 are not directly referred in the code,
 135          * no need have them in separate members in this table.
 136          *      Copy Engine             Address
 137          *      CE8                     0x0004c000
 138          *      CE9                     0x0004c400
 139          *      CE10                    0x0004c800
 140          *      CE11                    0x0004cc00
 141          */
 142         .soc_reset_control_si0_rst_mask         = 0x00000001,
 143         .soc_reset_control_ce_rst_mask          = 0x00000100,
 144         .soc_chip_id_address                    = 0x000000ec,
 145         .fw_indicator_address                   = 0x0004f00c,
 146         .ce_wrap_intr_sum_host_msi_lsb          = 0x0000000c,
 147         .ce_wrap_intr_sum_host_msi_mask         = 0x00fff000,
 148         .pcie_intr_fw_mask                      = 0x00100000,
 149         .pcie_intr_ce_mask_all                  = 0x000fff00,
 150         .pcie_intr_clr_address                  = 0x00000010,
 151 };
 152
 153 const struct ath10k_hw_values qca988x_values = {
 154         .rtc_state_val_on               = 3,
 155         .ce_count                       = 8,
 156         .msi_assign_ce_max              = 7,
 157         .num_target_ce_config_wlan      = 7,
 158         .ce_desc_meta_data_mask         = 0xFFFC,
 159         .ce_desc_meta_data_lsb          = 2,
 160 };
 161
 162 const struct ath10k_hw_values qca6174_values = {
 163         .rtc_state_val_on               = 3,
 164         .ce_count                       = 8,
 165         .msi_assign_ce_max              = 7,
 166         .num_target_ce_config_wlan      = 7,
 167         .ce_desc_meta_data_mask         = 0xFFFC,
 168         .ce_desc_meta_data_lsb          = 2,
 169 };
 170
 171 const struct ath10k_hw_values qca99x0_values = {
 172         .rtc_state_val_on               = 5,
 173         .ce_count                       = 12,
 174         .msi_assign_ce_max              = 12,
 175         .num_target_ce_config_wlan      = 10,
 176         .ce_desc_meta_data_mask         = 0xFFF0,
 177         .ce_desc_meta_data_lsb          = 4,
 178 };
 179
 180 const struct ath10k_hw_values qca9888_values = {
 181         .rtc_state_val_on               = 3,
 182         .ce_count                       = 12,
 183         .msi_assign_ce_max              = 12,
 184         .num_target_ce_config_wlan      = 10,
 185         .ce_desc_meta_data_mask         = 0xFFF0,
 186         .ce_desc_meta_data_lsb          = 4,
 187 };
 188
 189 const struct ath10k_hw_values qca4019_values = {
 190         .ce_count                       = 12,
 191         .num_target_ce_config_wlan      = 10,
 192         .ce_desc_meta_data_mask         = 0xFFF0,
 193         .ce_desc_meta_data_lsb          = 4,
 194 };
 195
 196 const struct ath10k_hw_regs wcn3990_regs = {
 197         .rtc_soc_base_address                   = 0x00000000,
 198         .rtc_wmac_base_address                  = 0x00000000,
 199         .soc_core_base_address                  = 0x00000000,
 200         .ce_wrapper_base_address                = 0x0024C000,
 201         .ce0_base_address                       = 0x00240000,
 202         .ce1_base_address                       = 0x00241000,
 203         .ce2_base_address                       = 0x00242000,
 204         .ce3_base_address                       = 0x00243000,
 205         .ce4_base_address                       = 0x00244000,
 206         .ce5_base_address                       = 0x00245000,
 207         .ce6_base_address                       = 0x00246000,
 208         .ce7_base_address                       = 0x00247000,
 209         .ce8_base_address                       = 0x00248000,
 210         .ce9_base_address                       = 0x00249000,
 211         .ce10_base_address                      = 0x0024A000,
 212         .ce11_base_address                      = 0x0024B000,
 213         .soc_chip_id_address                    = 0x000000f0,
 214         .soc_reset_control_si0_rst_mask         = 0x00000001,
 215         .soc_reset_control_ce_rst_mask          = 0x00000100,
 216         .ce_wrap_intr_sum_host_msi_lsb          = 0x0000000c,
 217         .ce_wrap_intr_sum_host_msi_mask         = 0x00fff000,
 218         .pcie_intr_fw_mask                      = 0x00100000,
 219 };
 220
 221 static struct ath10k_hw_ce_regs_addr_map wcn3990_src_ring = {
 222         .msb    = 0x00000010,
 223         .lsb    = 0x00000010,
 224         .mask   = GENMASK(17, 17),
 225 };
 226
 227 static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_ring = {
 228         .msb    = 0x00000012,
 229         .lsb    = 0x00000012,
 230         .mask   = GENMASK(18, 18),
 231 };
 232
 233 static struct ath10k_hw_ce_regs_addr_map wcn3990_dmax = {
 234         .msb    = 0x00000000,
 235         .lsb    = 0x00000000,
 236         .mask   = GENMASK(15, 0),
 237 };
 238
 239 static struct ath10k_hw_ce_ctrl1 wcn3990_ctrl1 = {
 240         .addr           = 0x00000018,
 241         .src_ring       = &wcn3990_src_ring,
 242         .dst_ring       = &wcn3990_dst_ring,
 243         .dmax           = &wcn3990_dmax,
 244 };
 245
 246 static struct ath10k_hw_ce_regs_addr_map wcn3990_host_ie_cc = {
 247         .mask   = GENMASK(0, 0),
 248 };
 249
 250 static struct ath10k_hw_ce_host_ie wcn3990_host_ie = {
 251         .copy_complete  = &wcn3990_host_ie_cc,
 252 };
 253
 254 static struct ath10k_hw_ce_host_wm_regs wcn3990_wm_reg = {
 255         .dstr_lmask     = 0x00000010,
 256         .dstr_hmask     = 0x00000008,
 257         .srcr_lmask     = 0x00000004,
 258         .srcr_hmask     = 0x00000002,
 259         .cc_mask        = 0x00000001,
 260         .wm_mask        = 0x0000001E,
 261         .addr           = 0x00000030,
 262 };
 263
 264 static struct ath10k_hw_ce_misc_regs wcn3990_misc_reg = {
 265         .axi_err        = 0x00000100,
 266         .dstr_add_err   = 0x00000200,
 267         .srcr_len_err   = 0x00000100,
 268         .dstr_mlen_vio  = 0x00000080,
 269         .dstr_overflow  = 0x00000040,
 270         .srcr_overflow  = 0x00000020,
 271         .err_mask       = 0x000003E0,
 272         .addr           = 0x00000038,
 273 };
 274
 275 static struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_low = {
 276         .msb    = 0x00000000,
 277         .lsb    = 0x00000010,
 278         .mask   = GENMASK(31, 16),
 279 };
 280
 281 static struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_high = {
 282         .msb    = 0x0000000f,
 283         .lsb    = 0x00000000,
 284         .mask   = GENMASK(15, 0),
 285 };
 286
 287 static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_src_ring = {
 288         .addr           = 0x0000004c,
 289         .low_rst        = 0x00000000,
 290         .high_rst       = 0x00000000,
 291         .wm_low         = &wcn3990_src_wm_low,
 292         .wm_high        = &wcn3990_src_wm_high,
 293 };
 294
 295 static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_low = {
 296         .lsb    = 0x00000010,
 297         .mask   = GENMASK(31, 16),
 298 };
 299
 300 static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_high = {
 301         .msb    = 0x0000000f,
 302         .lsb    = 0x00000000,
 303         .mask   = GENMASK(15, 0),
 304 };
 305
 306 static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_dst_ring = {
 307         .addr           = 0x00000050,
 308         .low_rst        = 0x00000000,
 309         .high_rst       = 0x00000000,
 310         .wm_low         = &wcn3990_dst_wm_low,
 311         .wm_high        = &wcn3990_dst_wm_high,
 312 };
 313
 314 static struct ath10k_hw_ce_ctrl1_upd wcn3990_ctrl1_upd = {
 315         .shift = 19,
 316         .mask = 0x00080000,
 317         .enable = 0x00000000,
 318 };
 319
 320 const struct ath10k_hw_ce_regs wcn3990_ce_regs = {
 321         .sr_base_addr_lo        = 0x00000000,
 322         .sr_base_addr_hi        = 0x00000004,
 323         .sr_size_addr           = 0x00000008,
 324         .dr_base_addr_lo        = 0x0000000c,
 325         .dr_base_addr_hi        = 0x00000010,
 326         .dr_size_addr           = 0x00000014,
 327         .misc_ie_addr           = 0x00000034,
 328         .sr_wr_index_addr       = 0x0000003c,
 329         .dst_wr_index_addr      = 0x00000040,
 330         .current_srri_addr      = 0x00000044,
 331         .current_drri_addr      = 0x00000048,
 332         .ce_rri_low             = 0x0024C004,
 333         .ce_rri_high            = 0x0024C008,
 334         .host_ie_addr           = 0x0000002c,
 335         .ctrl1_regs             = &wcn3990_ctrl1,
 336         .host_ie                = &wcn3990_host_ie,
 337         .wm_regs                = &wcn3990_wm_reg,
 338         .misc_regs              = &wcn3990_misc_reg,
 339         .wm_srcr                = &wcn3990_wm_src_ring,
 340         .wm_dstr                = &wcn3990_wm_dst_ring,
 341         .upd                    = &wcn3990_ctrl1_upd,
 342 };
 343
 344 const struct ath10k_hw_values wcn3990_values = {
 345         .rtc_state_val_on               = 5,
 346         .ce_count                       = 12,
 347         .msi_assign_ce_max              = 12,
 348         .num_target_ce_config_wlan      = 12,
 349         .ce_desc_meta_data_mask         = 0xFFF0,
 350         .ce_desc_meta_data_lsb          = 4,
 351 };
 352
 353 static struct ath10k_hw_ce_regs_addr_map qcax_src_ring = {
 354         .msb    = 0x00000010,
 355         .lsb    = 0x00000010,
 356         .mask   = GENMASK(16, 16),
 357 };
 358
 359 static struct ath10k_hw_ce_regs_addr_map qcax_dst_ring = {
 360         .msb    = 0x00000011,
 361         .lsb    = 0x00000011,
 362         .mask   = GENMASK(17, 17),
 363 };
 364
 365 static struct ath10k_hw_ce_regs_addr_map qcax_dmax = {
 366         .msb    = 0x0000000f,
 367         .lsb    = 0x00000000,
 368         .mask   = GENMASK(15, 0),
 369 };
 370
 371 static struct ath10k_hw_ce_ctrl1 qcax_ctrl1 = {
 372         .addr           = 0x00000010,
 373         .hw_mask        = 0x0007ffff,
 374         .sw_mask        = 0x0007ffff,
 375         .hw_wr_mask     = 0x00000000,
 376         .sw_wr_mask     = 0x0007ffff,
 377         .reset_mask     = 0xffffffff,
 378         .reset          = 0x00000080,
 379         .src_ring       = &qcax_src_ring,
 380         .dst_ring       = &qcax_dst_ring,
 381         .dmax           = &qcax_dmax,
 382 };
 383
 384 static struct ath10k_hw_ce_regs_addr_map qcax_cmd_halt_status = {
 385         .msb    = 0x00000003,
 386         .lsb    = 0x00000003,
 387         .mask   = GENMASK(3, 3),
 388 };
 389
 390 static struct ath10k_hw_ce_cmd_halt qcax_cmd_halt = {
 391         .msb            = 0x00000000,
 392         .mask           = GENMASK(0, 0),
 393         .status_reset   = 0x00000000,
 394         .status         = &qcax_cmd_halt_status,
 395 };
 396
 397 static struct ath10k_hw_ce_regs_addr_map qcax_host_ie_cc = {
 398         .msb    = 0x00000000,
 399         .lsb    = 0x00000000,
 400         .mask   = GENMASK(0, 0),
 401 };
 402
 403 static struct ath10k_hw_ce_host_ie qcax_host_ie = {
 404         .copy_complete_reset    = 0x00000000,
 405         .copy_complete          = &qcax_host_ie_cc,
 406 };
 407
 408 static struct ath10k_hw_ce_host_wm_regs qcax_wm_reg = {
 409         .dstr_lmask     = 0x00000010,
 410         .dstr_hmask     = 0x00000008,
 411         .srcr_lmask     = 0x00000004,
 412         .srcr_hmask     = 0x00000002,
 413         .cc_mask        = 0x00000001,
 414         .wm_mask        = 0x0000001E,
 415         .addr           = 0x00000030,
 416 };
 417
 418 static struct ath10k_hw_ce_misc_regs qcax_misc_reg = {
 419         .axi_err        = 0x00000400,
 420         .dstr_add_err   = 0x00000200,
 421         .srcr_len_err   = 0x00000100,
 422         .dstr_mlen_vio  = 0x00000080,
 423         .dstr_overflow  = 0x00000040,
 424         .srcr_overflow  = 0x00000020,
 425         .err_mask       = 0x000007E0,
 426         .addr           = 0x00000038,
 427 };
 428
 429 static struct ath10k_hw_ce_regs_addr_map qcax_src_wm_low = {
 430         .msb    = 0x0000001f,
 431         .lsb    = 0x00000010,
 432         .mask   = GENMASK(31, 16),
 433 };
 434
 435 static struct ath10k_hw_ce_regs_addr_map qcax_src_wm_high = {
 436         .msb    = 0x0000000f,
 437         .lsb    = 0x00000000,
 438         .mask   = GENMASK(15, 0),
 439 };
 440
 441 static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_src_ring = {
 442         .addr           = 0x0000004c,
 443         .low_rst        = 0x00000000,
 444         .high_rst       = 0x00000000,
 445         .wm_low         = &qcax_src_wm_low,
 446         .wm_high        = &qcax_src_wm_high,
 447 };
 448
 449 static struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_low = {
 450         .lsb    = 0x00000010,
 451         .mask   = GENMASK(31, 16),
 452 };
 453
 454 static struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_high = {
 455         .msb    = 0x0000000f,
 456         .lsb    = 0x00000000,
 457         .mask   = GENMASK(15, 0),
 458 };
 459
 460 static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_dst_ring = {
 461         .addr           = 0x00000050,
 462         .low_rst        = 0x00000000,
 463         .high_rst       = 0x00000000,
 464         .wm_low         = &qcax_dst_wm_low,
 465         .wm_high        = &qcax_dst_wm_high,
 466 };
 467
 468 const struct ath10k_hw_ce_regs qcax_ce_regs = {
 469         .sr_base_addr_lo        = 0x00000000,
 470         .sr_size_addr           = 0x00000004,
 471         .dr_base_addr_lo        = 0x00000008,
 472         .dr_size_addr           = 0x0000000c,
 473         .ce_cmd_addr            = 0x00000018,
 474         .misc_ie_addr           = 0x00000034,
 475         .sr_wr_index_addr       = 0x0000003c,
 476         .dst_wr_index_addr      = 0x00000040,
 477         .current_srri_addr      = 0x00000044,
 478         .current_drri_addr      = 0x00000048,
 479         .host_ie_addr           = 0x0000002c,
 480         .ctrl1_regs             = &qcax_ctrl1,
 481         .cmd_halt               = &qcax_cmd_halt,
 482         .host_ie                = &qcax_host_ie,
 483         .wm_regs                = &qcax_wm_reg,
 484         .misc_regs              = &qcax_misc_reg,
 485         .wm_srcr                = &qcax_wm_src_ring,
 486         .wm_dstr                = &qcax_wm_dst_ring,
 487 };
 488
 489 const struct ath10k_hw_clk_params qca6174_clk[ATH10K_HW_REFCLK_COUNT] = {
 490         {
 491                 .refclk = 48000000,
 492                 .div = 0xe,
 493                 .rnfrac = 0x2aaa8,
 494                 .settle_time = 2400,
 495                 .refdiv = 0,
 496                 .outdiv = 1,
 497         },
 498         {
 499                 .refclk = 19200000,
 500                 .div = 0x24,
 501                 .rnfrac = 0x2aaa8,
 502                 .settle_time = 960,
 503                 .refdiv = 0,
 504                 .outdiv = 1,
 505         },
 506         {
 507                 .refclk = 24000000,
 508                 .div = 0x1d,
 509                 .rnfrac = 0x15551,
 510                 .settle_time = 1200,
 511                 .refdiv = 0,
 512                 .outdiv = 1,
 513         },
 514         {
 515                 .refclk = 26000000,
 516                 .div = 0x1b,
 517                 .rnfrac = 0x4ec4,
 518                 .settle_time = 1300,
 519                 .refdiv = 0,
 520                 .outdiv = 1,
 521         },
 522         {
 523                 .refclk = 37400000,
 524                 .div = 0x12,
 525                 .rnfrac = 0x34b49,
 526                 .settle_time = 1870,
 527                 .refdiv = 0,
 528                 .outdiv = 1,
 529         },
 530         {
 531                 .refclk = 38400000,
 532                 .div = 0x12,
 533                 .rnfrac = 0x15551,
 534                 .settle_time = 1920,
 535                 .refdiv = 0,
 536                 .outdiv = 1,
 537         },
 538         {
 539                 .refclk = 40000000,
 540                 .div = 0x12,
 541                 .rnfrac = 0x26665,
 542                 .settle_time = 2000,
 543                 .refdiv = 0,
 544                 .outdiv = 1,
 545         },
 546         {
 547                 .refclk = 52000000,
 548                 .div = 0x1b,
 549                 .rnfrac = 0x4ec4,
 550                 .settle_time = 2600,
 551                 .refdiv = 0,
 552                 .outdiv = 1,
 553         },
 554 };
 555
 556 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
 557                                 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)
 558 {
 559         u32 cc_fix = 0;
 560         u32 rcc_fix = 0;
 561         enum ath10k_hw_cc_wraparound_type wraparound_type;
 562
 563         survey->filled |= SURVEY_INFO_TIME |
 564                           SURVEY_INFO_TIME_BUSY;
 565
 566         wraparound_type = ar->hw_params.cc_wraparound_type;
 567
 568         if (cc < cc_prev || rcc < rcc_prev) {
 569                 switch (wraparound_type) {
 570                 case ATH10K_HW_CC_WRAP_SHIFTED_ALL:
 571                         if (cc < cc_prev) {
 572                                 cc_fix = 0x7fffffff;
 573                                 survey->filled &= ~SURVEY_INFO_TIME_BUSY;
 574                         }
 575                         break;
 576                 case ATH10K_HW_CC_WRAP_SHIFTED_EACH:
 577                         if (cc < cc_prev)
 578                                 cc_fix = 0x7fffffff;
 579
 580                         if (rcc < rcc_prev)
 581                                 rcc_fix = 0x7fffffff;
 582                         break;
 583                 case ATH10K_HW_CC_WRAP_DISABLED:
 584                         break;
 585                 }
 586         }
 587
 588         cc -= cc_prev - cc_fix;
 589         rcc -= rcc_prev - rcc_fix;
 590
 591         survey->time = CCNT_TO_MSEC(ar, cc);
 592         survey->time_busy = CCNT_TO_MSEC(ar, rcc);
 593 }
 594
 595 /* The firmware does not support setting the coverage class. Instead this
 596  * function monitors and modifies the corresponding MAC registers.
 597  */
 598 static void ath10k_hw_qca988x_set_coverage_class(struct ath10k *ar,
 599                                                  s16 value)
 600 {
 601         u32 slottime_reg;
 602         u32 slottime;
 603         u32 timeout_reg;
 604         u32 ack_timeout;
 605         u32 cts_timeout;
 606         u32 phyclk_reg;
 607         u32 phyclk;
 608         u64 fw_dbglog_mask;
 609         u32 fw_dbglog_level;
 610
 611         mutex_lock(&ar->conf_mutex);
 612
 613         /* Only modify registers if the core is started. */
 614         if ((ar->state != ATH10K_STATE_ON) &&
 615             (ar->state != ATH10K_STATE_RESTARTED)) {
 616                 spin_lock_bh(&ar->data_lock);
 617                 /* Store config value for when radio boots up */
 618                 ar->fw_coverage.coverage_class = value;
 619                 spin_unlock_bh(&ar->data_lock);
 620                 goto unlock;
 621         }
 622
 623         /* Retrieve the current values of the two registers that need to be
 624          * adjusted.
 625          */
 626         slottime_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
 627                                              WAVE1_PCU_GBL_IFS_SLOT);
 628         timeout_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
 629                                             WAVE1_PCU_ACK_CTS_TIMEOUT);
 630         phyclk_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
 631                                            WAVE1_PHYCLK);
 632         phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1;
 633
 634         if (value < 0)
 635                 value = ar->fw_coverage.coverage_class;
 636
 637         /* Break out if the coverage class and registers have the expected
 638          * value.
 639          */
 640         if (value == ar->fw_coverage.coverage_class &&
 641             slottime_reg == ar->fw_coverage.reg_slottime_conf &&
 642             timeout_reg == ar->fw_coverage.reg_ack_cts_timeout_conf &&
 643             phyclk_reg == ar->fw_coverage.reg_phyclk)
 644                 goto unlock;
 645
 646         /* Store new initial register values from the firmware. */
 647         if (slottime_reg != ar->fw_coverage.reg_slottime_conf)
 648                 ar->fw_coverage.reg_slottime_orig = slottime_reg;
 649         if (timeout_reg != ar->fw_coverage.reg_ack_cts_timeout_conf)
 650                 ar->fw_coverage.reg_ack_cts_timeout_orig = timeout_reg;
 651         ar->fw_coverage.reg_phyclk = phyclk_reg;
 652
 653         /* Calculate new value based on the (original) firmware calculation. */
 654         slottime_reg = ar->fw_coverage.reg_slottime_orig;
 655         timeout_reg = ar->fw_coverage.reg_ack_cts_timeout_orig;
 656
 657         /* Do some sanity checks on the slottime register. */
 658         if (slottime_reg % phyclk) {
 659                 ath10k_warn(ar,
 660                             "failed to set coverage class: expected integer microsecond value in register\n");
 661
 662                 goto store_regs;
 663         }
 664
 665         slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);
 666         slottime = slottime / phyclk;
 667         if (slottime != 9 && slottime != 20) {
 668                 ath10k_warn(ar,
 669                             "failed to set coverage class: expected slot time of 9 or 20us in HW register. It is %uus.\n",
 670                             slottime);
 671
 672                 goto store_regs;
 673         }
 674
 675         /* Recalculate the register values by adding the additional propagation
 676          * delay (3us per coverage class).
 677          */
 678
 679         slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);
 680         slottime += value * 3 * phyclk;
 681         slottime = min_t(u32, slottime, WAVE1_PCU_GBL_IFS_SLOT_MAX);
 682         slottime = SM(slottime, WAVE1_PCU_GBL_IFS_SLOT);
 683         slottime_reg = (slottime_reg & ~WAVE1_PCU_GBL_IFS_SLOT_MASK) | slottime;
 684
 685         /* Update ack timeout (lower halfword). */
 686         ack_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);
 687         ack_timeout += 3 * value * phyclk;
 688         ack_timeout = min_t(u32, ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX);
 689         ack_timeout = SM(ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);
 690
 691         /* Update cts timeout (upper halfword). */
 692         cts_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);
 693         cts_timeout += 3 * value * phyclk;
 694         cts_timeout = min_t(u32, cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX);
 695         cts_timeout = SM(cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);
 696
 697         timeout_reg = ack_timeout | cts_timeout;
 698
 699         ath10k_hif_write32(ar,
 700                            WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_GBL_IFS_SLOT,
 701                            slottime_reg);
 702         ath10k_hif_write32(ar,
 703                            WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_ACK_CTS_TIMEOUT,
 704                            timeout_reg);
 705
 706         /* Ensure we have a debug level of WARN set for the case that the
 707          * coverage class is larger than 0. This is important as we need to
 708          * set the registers again if the firmware does an internal reset and
 709          * this way we will be notified of the event.
 710          */
 711         fw_dbglog_mask = ath10k_debug_get_fw_dbglog_mask(ar);
 712         fw_dbglog_level = ath10k_debug_get_fw_dbglog_level(ar);
 713
 714         if (value > 0) {
 715                 if (fw_dbglog_level > ATH10K_DBGLOG_LEVEL_WARN)
 716                         fw_dbglog_level = ATH10K_DBGLOG_LEVEL_WARN;
 717                 fw_dbglog_mask = ~0;
 718         }
 719
 720         ath10k_wmi_dbglog_cfg(ar, fw_dbglog_mask, fw_dbglog_level);
 721
 722 store_regs:
 723         /* After an error we will not retry setting the coverage class. */
 724         spin_lock_bh(&ar->data_lock);
 725         ar->fw_coverage.coverage_class = value;
 726         spin_unlock_bh(&ar->data_lock);
 727
 728         ar->fw_coverage.reg_slottime_conf = slottime_reg;
 729         ar->fw_coverage.reg_ack_cts_timeout_conf = timeout_reg;
 730
 731 unlock:
 732         mutex_unlock(&ar->conf_mutex);
 733 }
 734
 735 /**
 736  * ath10k_hw_qca6174_enable_pll_clock() - enable the qca6174 hw pll clock
 737  * @ar: the ath10k blob
 738  *
 739  * This function is very hardware specific, the clock initialization
 740  * steps is very sensitive and could lead to unknown crash, so they
 741  * should be done in sequence.
 742  *
 743  * *** Be aware if you planned to refactor them. ***
 744  *
 745  * Return: 0 if successfully enable the pll, otherwise EINVAL
 746  */
 747 static int ath10k_hw_qca6174_enable_pll_clock(struct ath10k *ar)
 748 {
 749         int ret, wait_limit;
 750         u32 clk_div_addr, pll_init_addr, speed_addr;
 751         u32 addr, reg_val, mem_val;
 752         struct ath10k_hw_params *hw;
 753         const struct ath10k_hw_clk_params *hw_clk;
 754
 755         hw = &ar->hw_params;
 756
 757         if (ar->regs->core_clk_div_address == 0 ||
 758             ar->regs->cpu_pll_init_address == 0 ||
 759             ar->regs->cpu_speed_address == 0)
 760                 return -EINVAL;
 761
 762         clk_div_addr = ar->regs->core_clk_div_address;
 763         pll_init_addr = ar->regs->cpu_pll_init_address;
 764         speed_addr = ar->regs->cpu_speed_address;
 765
 766         /* Read efuse register to find out the right hw clock configuration */
 767         addr = (RTC_SOC_BASE_ADDRESS | EFUSE_OFFSET);
 768         ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
 769         if (ret)
 770                 return -EINVAL;
 771
 772         /* sanitize if the hw refclk index is out of the boundary */
 773         if (MS(reg_val, EFUSE_XTAL_SEL) > ATH10K_HW_REFCLK_COUNT)
 774                 return -EINVAL;
 775
 776         hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)];
 777
 778         /* Set the rnfrac and outdiv params to bb_pll register */
 779         addr = (RTC_SOC_BASE_ADDRESS | BB_PLL_CONFIG_OFFSET);
 780         ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
 781         if (ret)
 782                 return -EINVAL;
 783
 784         reg_val &= ~(BB_PLL_CONFIG_FRAC_MASK | BB_PLL_CONFIG_OUTDIV_MASK);
 785         reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) |
 786                     SM(hw_clk->outdiv, BB_PLL_CONFIG_OUTDIV));
 787         ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
 788         if (ret)
 789                 return -EINVAL;
 790
 791         /* Set the correct settle time value to pll_settle register */
 792         addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_SETTLE_OFFSET);
 793         ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
 794         if (ret)
 795                 return -EINVAL;
 796
 797         reg_val &= ~WLAN_PLL_SETTLE_TIME_MASK;
 798         reg_val |= SM(hw_clk->settle_time, WLAN_PLL_SETTLE_TIME);
 799         ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
 800         if (ret)
 801                 return -EINVAL;
 802
 803         /* Set the clock_ctrl div to core_clk_ctrl register */
 804         addr = (RTC_SOC_BASE_ADDRESS | SOC_CORE_CLK_CTRL_OFFSET);
 805         ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
 806         if (ret)
 807                 return -EINVAL;
 808
 809         reg_val &= ~SOC_CORE_CLK_CTRL_DIV_MASK;
 810         reg_val |= SM(1, SOC_CORE_CLK_CTRL_DIV);
 811         ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
 812         if (ret)
 813                 return -EINVAL;
 814
 815         /* Set the clock_div register */
 816         mem_val = 1;
 817         ret = ath10k_bmi_write_memory(ar, clk_div_addr, &mem_val,
 818                                       sizeof(mem_val));
 819         if (ret)
 820                 return -EINVAL;
 821
 822         /* Configure the pll_control register */
 823         addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET);
 824         ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
 825         if (ret)
 826                 return -EINVAL;
 827
 828         reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) |
 829                     SM(hw_clk->div, WLAN_PLL_CONTROL_DIV) |
 830                     SM(1, WLAN_PLL_CONTROL_NOPWD));
 831         ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
 832         if (ret)
 833                 return -EINVAL;
 834
 835         /* busy wait (max 1s) the rtc_sync status register indicate ready */
 836         wait_limit = 100000;
 837         addr = (RTC_WMAC_BASE_ADDRESS | RTC_SYNC_STATUS_OFFSET);
 838         do {
 839                 ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
 840                 if (ret)
 841                         return -EINVAL;
 842
 843                 if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))
 844                         break;
 845
 846                 wait_limit--;
 847                 udelay(10);
 848
 849         } while (wait_limit > 0);
 850
 851         if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))
 852                 return -EINVAL;
 853
 854         /* Unset the pll_bypass in pll_control register */
 855         addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET);
 856         ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
 857         if (ret)
 858                 return -EINVAL;
 859
 860         reg_val &= ~WLAN_PLL_CONTROL_BYPASS_MASK;
 861         reg_val |= SM(0, WLAN_PLL_CONTROL_BYPASS);
 862         ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
 863         if (ret)
 864                 return -EINVAL;
 865
 866         /* busy wait (max 1s) the rtc_sync status register indicate ready */
 867         wait_limit = 100000;
 868         addr = (RTC_WMAC_BASE_ADDRESS | RTC_SYNC_STATUS_OFFSET);
 869         do {
 870                 ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
 871                 if (ret)
 872                         return -EINVAL;
 873
 874                 if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))
 875                         break;
 876
 877                 wait_limit--;
 878                 udelay(10);
 879
 880         } while (wait_limit > 0);
 881
 882         if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))
 883                 return -EINVAL;
 884
 885         /* Enable the hardware cpu clock register */
 886         addr = (RTC_SOC_BASE_ADDRESS | SOC_CPU_CLOCK_OFFSET);
 887         ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
 888         if (ret)
 889                 return -EINVAL;
 890
 891         reg_val &= ~SOC_CPU_CLOCK_STANDARD_MASK;
 892         reg_val |= SM(1, SOC_CPU_CLOCK_STANDARD);
 893         ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
 894         if (ret)
 895                 return -EINVAL;
 896
 897         /* unset the nopwd from pll_control register */
 898         addr = (RTC_WMAC_BASE_ADDRESS | WLAN_PLL_CONTROL_OFFSET);
 899         ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val);
 900         if (ret)
 901                 return -EINVAL;
 902
 903         reg_val &= ~WLAN_PLL_CONTROL_NOPWD_MASK;
 904         ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val);
 905         if (ret)
 906                 return -EINVAL;
 907
 908         /* enable the pll_init register */
 909         mem_val = 1;
 910         ret = ath10k_bmi_write_memory(ar, pll_init_addr, &mem_val,
 911                                       sizeof(mem_val));
 912         if (ret)
 913                 return -EINVAL;
 914
 915         /* set the target clock frequency to speed register */
 916         ret = ath10k_bmi_write_memory(ar, speed_addr, &hw->target_cpu_freq,
 917                                       sizeof(hw->target_cpu_freq));
 918         if (ret)
 919                 return -EINVAL;
 920
 921         return 0;
 922 }
 923
 924 /* Program CPU_ADDR_MSB to allow different memory
 925  * region access.
 926  */
 927 static void ath10k_hw_map_target_mem(struct ath10k *ar, u32 msb)
 928 {
 929         u32 address = SOC_CORE_BASE_ADDRESS + FW_RAM_CONFIG_ADDRESS;
 930
 931         ath10k_hif_write32(ar, address, msb);
 932 }
 933
 934 /* 1. Write to memory region of target, such as IRAM adn DRAM.
 935  * 2. Target address( 0 ~ 00100000 & 0x00400000~0x00500000)
 936  *    can be written directly. See ath10k_pci_targ_cpu_to_ce_addr() too.
 937  * 3. In order to access the region other than the above,
 938  *    we need to set the value of register CPU_ADDR_MSB.
 939  * 4. Target memory access space is limited to 1M size. If the size is larger
 940  *    than 1M, need to split it and program CPU_ADDR_MSB accordingly.
 941  */
 942 static int ath10k_hw_diag_segment_msb_download(struct ath10k *ar,
 943                                                const void *buffer,
 944                                                u32 address,
 945                                                u32 length)
 946 {
 947         u32 addr = address & REGION_ACCESS_SIZE_MASK;
 948         int ret, remain_size, size;
 949         const u8 *buf;
 950
 951         ath10k_hw_map_target_mem(ar, CPU_ADDR_MSB_REGION_VAL(address));
 952
 953         if (addr + length > REGION_ACCESS_SIZE_LIMIT) {
 954                 size = REGION_ACCESS_SIZE_LIMIT - addr;
 955                 remain_size = length - size;
 956
 957                 ret = ath10k_hif_diag_write(ar, address, buffer, size);
 958                 if (ret) {
 959                         ath10k_warn(ar,
 960                                     "failed to download the first %d bytes segment to address:0x%x: %d\n",
 961                                     size, address, ret);
 962                         goto done;
 963                 }
 964
 965                 /* Change msb to the next memory region*/
 966                 ath10k_hw_map_target_mem(ar,
 967                                          CPU_ADDR_MSB_REGION_VAL(address) + 1);
 968                 buf = buffer +  size;
 969                 ret = ath10k_hif_diag_write(ar,
 970                                             address & ~REGION_ACCESS_SIZE_MASK,
 971                                             buf, remain_size);
 972                 if (ret) {
 973                         ath10k_warn(ar,
 974                                     "failed to download the second %d bytes segment to address:0x%x: %d\n",
 975                                     remain_size,
 976                                     address & ~REGION_ACCESS_SIZE_MASK,
 977                                     ret);
 978                         goto done;
 979                 }
 980         } else {
 981                 ret = ath10k_hif_diag_write(ar, address, buffer, length);
 982                 if (ret) {
 983                         ath10k_warn(ar,
 984                                     "failed to download the only %d bytes segment to address:0x%x: %d\n",
 985                                     length, address, ret);
 986                         goto done;
 987                 }
 988         }
 989
 990 done:
 991         /* Change msb to DRAM */
 992         ath10k_hw_map_target_mem(ar,
 993                                  CPU_ADDR_MSB_REGION_VAL(DRAM_BASE_ADDRESS));
 994         return ret;
 995 }
 996
 997 static int ath10k_hw_diag_segment_download(struct ath10k *ar,
 998                                            const void *buffer,
 999                                            u32 address,
1000                                            u32 length)
1001 {
1002         if (address >= DRAM_BASE_ADDRESS + REGION_ACCESS_SIZE_LIMIT)
1003                 /* Needs to change MSB for memory write */
1004                 return ath10k_hw_diag_segment_msb_download(ar, buffer,
1005                                                            address, length);
1006         else
1007                 return ath10k_hif_diag_write(ar, address, buffer, length);
1008 }
1009
1010 int ath10k_hw_diag_fast_download(struct ath10k *ar,
1011                                  u32 address,
1012                                  const void *buffer,
1013                                  u32 length)
1014 {
1015         const u8 *buf = buffer;
1016         bool sgmt_end = false;
1017         u32 base_addr = 0;
1018         u32 base_len = 0;
1019         u32 left = 0;
1020         struct bmi_segmented_file_header *hdr;
1021         struct bmi_segmented_metadata *metadata;
1022         int ret = 0;
1023
1024         if (length < sizeof(*hdr))
1025                 return -EINVAL;
1026
1027         /* check firmware header. If it has no correct magic number
1028          * or it's compressed, returns error.
1029          */
1030         hdr = (struct bmi_segmented_file_header *)buf;
1031         if (__le32_to_cpu(hdr->magic_num) != BMI_SGMTFILE_MAGIC_NUM) {
1032                 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1033                            "Not a supported firmware, magic_num:0x%x\n",
1034                            hdr->magic_num);
1035                 return -EINVAL;
1036         }
1037
1038         if (hdr->file_flags != 0) {
1039                 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1040                            "Not a supported firmware, file_flags:0x%x\n",
1041                            hdr->file_flags);
1042                 return -EINVAL;
1043         }
1044
1045         metadata = (struct bmi_segmented_metadata *)hdr->data;
1046         left = length - sizeof(*hdr);
1047
1048         while (left > 0) {
1049                 if (left < sizeof(*metadata)) {
1050                         ath10k_warn(ar, "firmware segment is truncated: %d\n",
1051                                     left);
1052                         ret = -EINVAL;
1053                         break;
1054                 }
1055                 base_addr = __le32_to_cpu(metadata->addr);
1056                 base_len = __le32_to_cpu(metadata->length);
1057                 buf = metadata->data;
1058                 left -= sizeof(*metadata);
1059
1060                 switch (base_len) {
1061                 case BMI_SGMTFILE_BEGINADDR:
1062                         /* base_addr is the start address to run */
1063                         ret = ath10k_bmi_set_start(ar, base_addr);
1064                         base_len = 0;
1065                         break;
1066                 case BMI_SGMTFILE_DONE:
1067                         /* no more segment */
1068                         base_len = 0;
1069                         sgmt_end = true;
1070                         ret = 0;
1071                         break;
1072                 case BMI_SGMTFILE_BDDATA:
1073                 case BMI_SGMTFILE_EXEC:
1074                         ath10k_warn(ar,
1075                                     "firmware has unsupported segment:%d\n",
1076                                     base_len);
1077                         ret = -EINVAL;
1078                         break;
1079                 default:
1080                         if (base_len > left) {
1081                                 /* sanity check */
1082                                 ath10k_warn(ar,
1083                                             "firmware has invalid segment length, %d > %d\n",
1084                                             base_len, left);
1085                                 ret = -EINVAL;
1086                                 break;
1087                         }
1088
1089                         ret = ath10k_hw_diag_segment_download(ar,
1090                                                               buf,
1091                                                               base_addr,
1092                                                               base_len);
1093
1094                         if (ret)
1095                                 ath10k_warn(ar,
1096                                             "failed to download firmware via diag interface:%d\n",
1097                                             ret);
1098                         break;
1099                 }
1100
1101                 if (ret || sgmt_end)
1102                         break;
1103
1104                 metadata = (struct bmi_segmented_metadata *)(buf + base_len);
1105                 left -= base_len;
1106         }
1107
1108         if (ret == 0)
1109                 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1110                            "boot firmware fast diag download successfully.\n");
1111         return ret;
1112 }
1113
1114 const struct ath10k_hw_ops qca988x_ops = {
1115         .set_coverage_class = ath10k_hw_qca988x_set_coverage_class,
1116 };
1117
1118 static int ath10k_qca99x0_rx_desc_get_l3_pad_bytes(struct htt_rx_desc *rxd)
1119 {
1120         return MS(__le32_to_cpu(rxd->msdu_end.qca99x0.info1),
1121                   RX_MSDU_END_INFO1_L3_HDR_PAD);
1122 }
1123
1124 static bool ath10k_qca99x0_rx_desc_msdu_limit_error(struct htt_rx_desc *rxd)
1125 {
1126         return !!(rxd->msdu_end.common.info0 &
1127                   __cpu_to_le32(RX_MSDU_END_INFO0_MSDU_LIMIT_ERR));
1128 }
1129
1130 const struct ath10k_hw_ops qca99x0_ops = {
1131         .rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes,
1132         .rx_desc_get_msdu_limit_error = ath10k_qca99x0_rx_desc_msdu_limit_error,
1133 };
1134
1135 const struct ath10k_hw_ops qca6174_ops = {
1136         .set_coverage_class = ath10k_hw_qca988x_set_coverage_class,
1137         .enable_pll_clk = ath10k_hw_qca6174_enable_pll_clock,
1138 };
1139
1140 const struct ath10k_hw_ops wcn3990_ops = {};