1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
11 #include <linux/bug.h>
12 #include <linux/interrupt.h>
13 #include <linux/dmapool.h>
14 #include <linux/hashtable.h>
15 #include <linux/kfifo.h>
16 #include <net/mac80211.h>
22 enum htt_dbg_stats_type {
23 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0,
24 HTT_DBG_STATS_RX_REORDER = 1 << 1,
25 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2,
26 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3,
27 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4,
28 /* bits 5-23 currently reserved */
30 HTT_DBG_NUM_STATS /* keep this last */
33 enum htt_h2t_msg_type { /* host-to-target */
34 HTT_H2T_MSG_TYPE_VERSION_REQ = 0,
35 HTT_H2T_MSG_TYPE_TX_FRM = 1,
36 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2,
37 HTT_H2T_MSG_TYPE_STATS_REQ = 3,
38 HTT_H2T_MSG_TYPE_SYNC = 4,
39 HTT_H2T_MSG_TYPE_AGGR_CFG = 5,
40 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6,
42 /* This command is used for sending management frames in HTT < 3.0.
43 * HTT >= 3.0 uses TX_FRM for everything.
45 HTT_H2T_MSG_TYPE_MGMT_TX = 7,
46 HTT_H2T_MSG_TYPE_TX_FETCH_RESP = 11,
48 HTT_H2T_NUM_MSGS /* keep this last */
56 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)];
60 * HTT tx MSDU descriptor
62 * The HTT tx MSDU descriptor is created by the host HTT SW for each
63 * tx MSDU. The HTT tx MSDU descriptor contains the information that
64 * the target firmware needs for the FW's tx processing, particularly
65 * for creating the HW msdu descriptor.
66 * The same HTT tx descriptor is used for HL and LL systems, though
67 * a few fields within the tx descriptor are used only by LL or
69 * The HTT tx descriptor is defined in two manners: by a struct with
70 * bitfields, and by a series of [dword offset, bit mask, bit shift]
72 * The target should use the struct def, for simplicitly and clarity,
73 * but the host shall use the bit-mast + bit-shift defs, to be endian-
74 * neutral. Specifically, the host shall use the get/set macros built
75 * around the mask + shift defs.
77 struct htt_data_tx_desc_frag {
79 struct double_word_addr {
82 } __packed dword_addr;
83 struct triple_word_addr {
87 } __packed tword_addr;
91 struct htt_msdu_ext_desc {
93 __le16 ip_identification;
96 struct htt_data_tx_desc_frag frags[6];
99 struct htt_msdu_ext_desc_64 {
101 __le16 ip_identification;
104 struct htt_data_tx_desc_frag frags[6];
107 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0)
108 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1)
109 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2)
110 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3)
111 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4)
113 #define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \
114 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE \
115 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE \
116 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \
117 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE)
119 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 BIT(16)
120 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 BIT(17)
121 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 BIT(18)
122 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 BIT(19)
123 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64 BIT(20)
124 #define HTT_MSDU_EXT_DESC_FLAG_PARTIAL_CSUM_ENABLE_64 BIT(21)
126 #define HTT_MSDU_CHECKSUM_ENABLE_64 (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 \
127 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 \
128 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 \
129 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 \
130 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64)
132 enum htt_data_tx_desc_flags0 {
133 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0,
134 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1,
135 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2,
136 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3,
137 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4
138 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0
139 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5
142 enum htt_data_tx_desc_flags1 {
143 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6
144 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F
145 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0
146 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5
147 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0
148 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6
149 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11,
150 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12,
151 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13,
152 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14,
153 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15
156 enum htt_data_tx_ext_tid {
157 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16,
158 HTT_DATA_TX_EXT_TID_MGMT = 17,
159 HTT_DATA_TX_EXT_TID_INVALID = 31
162 #define HTT_INVALID_PEERID 0xFFFF
165 * htt_data_tx_desc - used for data tx path
167 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1.
168 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_
169 * for special kinds of tids
170 * postponed: only for HL hosts. indicates if this is a resend
171 * (HL hosts manage queues on the host )
172 * more_in_batch: only for HL hosts. indicates if more packets are
173 * pending. this allows target to wait and aggregate
174 * freq: 0 means home channel of given vdev. intended for offchannel
176 struct htt_data_tx_desc {
177 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */
178 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */
187 } __packed offchan_tx;
189 u8 prefetch[0]; /* start of frame, for FW classification engine */
192 struct htt_data_tx_desc_64 {
193 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */
194 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */
203 } __packed offchan_tx;
205 u8 prefetch[0]; /* start of frame, for FW classification engine */
208 enum htt_rx_ring_flags {
209 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0,
210 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1,
211 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2,
212 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3,
213 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4,
214 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5,
215 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6,
216 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7,
217 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8,
218 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9,
219 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10,
220 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11,
221 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12,
222 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13,
223 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14,
224 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15
227 #define HTT_RX_RING_SIZE_MIN 128
228 #define HTT_RX_RING_SIZE_MAX 2048
229 #define HTT_RX_RING_SIZE HTT_RX_RING_SIZE_MAX
230 #define HTT_RX_RING_FILL_LEVEL (((HTT_RX_RING_SIZE) / 2) - 1)
231 #define HTT_RX_RING_FILL_LEVEL_DUAL_MAC (HTT_RX_RING_SIZE - 1)
233 struct htt_rx_ring_setup_ring32 {
234 __le32 fw_idx_shadow_reg_paddr;
235 __le32 rx_ring_base_paddr;
236 __le16 rx_ring_len; /* in 4-byte words */
237 __le16 rx_ring_bufsize; /* rx skb size - in bytes */
238 __le16 flags; /* %HTT_RX_RING_FLAGS_ */
239 __le16 fw_idx_init_val;
241 /* the following offsets are in 4-byte units */
242 __le16 mac80211_hdr_offset;
243 __le16 msdu_payload_offset;
244 __le16 ppdu_start_offset;
245 __le16 ppdu_end_offset;
246 __le16 mpdu_start_offset;
247 __le16 mpdu_end_offset;
248 __le16 msdu_start_offset;
249 __le16 msdu_end_offset;
250 __le16 rx_attention_offset;
251 __le16 frag_info_offset;
254 struct htt_rx_ring_setup_ring64 {
255 __le64 fw_idx_shadow_reg_paddr;
256 __le64 rx_ring_base_paddr;
257 __le16 rx_ring_len; /* in 4-byte words */
258 __le16 rx_ring_bufsize; /* rx skb size - in bytes */
259 __le16 flags; /* %HTT_RX_RING_FLAGS_ */
260 __le16 fw_idx_init_val;
262 /* the following offsets are in 4-byte units */
263 __le16 mac80211_hdr_offset;
264 __le16 msdu_payload_offset;
265 __le16 ppdu_start_offset;
266 __le16 ppdu_end_offset;
267 __le16 mpdu_start_offset;
268 __le16 mpdu_end_offset;
269 __le16 msdu_start_offset;
270 __le16 msdu_end_offset;
271 __le16 rx_attention_offset;
272 __le16 frag_info_offset;
275 struct htt_rx_ring_setup_hdr {
276 u8 num_rings; /* supported values: 1, 2 */
280 struct htt_rx_ring_setup_32 {
281 struct htt_rx_ring_setup_hdr hdr;
282 struct htt_rx_ring_setup_ring32 rings[0];
285 struct htt_rx_ring_setup_64 {
286 struct htt_rx_ring_setup_hdr hdr;
287 struct htt_rx_ring_setup_ring64 rings[0];
291 * htt_stats_req - request target to send specified statistics
293 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ
294 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually
295 * so make sure its little-endian.
296 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually
297 * so make sure its little-endian.
298 * @cfg_val: stat_type specific configuration
299 * @stat_type: see %htt_dbg_stats_type
300 * @cookie_lsb: used for confirmation message from target->host
301 * @cookie_msb: ditto as %cookie
303 struct htt_stats_req {
317 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff
320 * htt_oob_sync_req - request out-of-band sync
322 * The HTT SYNC tells the target to suspend processing of subsequent
323 * HTT host-to-target messages until some other target agent locally
324 * informs the target HTT FW that the current sync counter is equal to
325 * or greater than (in a modulo sense) the sync counter specified in
328 * This allows other host-target components to synchronize their operation
329 * with HTT, e.g. to ensure that tx frames don't get transmitted until a
330 * security key has been downloaded to and activated by the target.
331 * In the absence of any explicit synchronization counter value
332 * specification, the target HTT FW will use zero as the default current
335 * The HTT target FW will suspend its host->target message processing as long
336 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128.
338 struct htt_oob_sync_req {
343 struct htt_aggr_conf {
344 u8 max_num_ampdu_subframes;
345 /* amsdu_subframes is limited by 0x1F mask */
346 u8 max_num_amsdu_subframes;
349 struct htt_aggr_conf_v2 {
350 u8 max_num_ampdu_subframes;
351 /* amsdu_subframes is limited by 0x1F mask */
352 u8 max_num_amsdu_subframes;
356 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32
357 struct htt_mgmt_tx_desc_qca99x0 {
361 struct htt_mgmt_tx_desc {
362 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)];
367 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN];
369 struct htt_mgmt_tx_desc_qca99x0 qca99x0;
373 enum htt_mgmt_tx_status {
374 HTT_MGMT_TX_STATUS_OK = 0,
375 HTT_MGMT_TX_STATUS_RETRY = 1,
376 HTT_MGMT_TX_STATUS_DROP = 2
379 /*=== target -> host messages ===============================================*/
381 enum htt_main_t2h_msg_type {
382 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0,
383 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1,
384 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2,
385 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3,
386 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
387 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5,
388 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6,
389 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
390 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8,
391 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9,
392 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
393 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb,
394 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
395 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
396 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf,
397 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10,
398 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11,
399 HTT_MAIN_T2H_MSG_TYPE_TEST,
401 HTT_MAIN_T2H_NUM_MSGS
404 enum htt_10x_t2h_msg_type {
405 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0,
406 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1,
407 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2,
408 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3,
409 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
410 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5,
411 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6,
412 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
413 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8,
414 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9,
415 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
416 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb,
417 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc,
418 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
419 HTT_10X_T2H_MSG_TYPE_TEST = 0xe,
420 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf,
421 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11,
422 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12,
423 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13,
428 enum htt_tlv_t2h_msg_type {
429 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0,
430 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1,
431 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2,
432 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3,
433 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
434 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5,
435 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6,
436 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
437 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8,
438 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9,
439 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
440 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb,
441 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* deprecated */
442 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
443 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
444 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf,
445 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10,
446 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11,
447 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12,
449 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14,
450 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15,
451 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16,
452 HTT_TLV_T2H_MSG_TYPE_TEST,
457 enum htt_10_4_t2h_msg_type {
458 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF = 0x0,
459 HTT_10_4_T2H_MSG_TYPE_RX_IND = 0x1,
460 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH = 0x2,
461 HTT_10_4_T2H_MSG_TYPE_PEER_MAP = 0x3,
462 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
463 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA = 0x5,
464 HTT_10_4_T2H_MSG_TYPE_RX_DELBA = 0x6,
465 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
466 HTT_10_4_T2H_MSG_TYPE_PKTLOG = 0x8,
467 HTT_10_4_T2H_MSG_TYPE_STATS_CONF = 0x9,
468 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
469 HTT_10_4_T2H_MSG_TYPE_SEC_IND = 0xb,
470 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc,
471 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
472 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
473 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE = 0xf,
474 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0x10,
475 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND = 0x11,
476 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x12,
477 HTT_10_4_T2H_MSG_TYPE_TEST = 0x13,
478 HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14,
479 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15,
480 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16,
481 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM = 0x17,
482 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18,
483 /* 0x19 to 0x2f are reserved */
484 HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND = 0x30,
485 HTT_10_4_T2H_MSG_TYPE_PEER_STATS = 0x31,
487 HTT_10_4_T2H_NUM_MSGS
490 enum htt_t2h_msg_type {
491 HTT_T2H_MSG_TYPE_VERSION_CONF,
492 HTT_T2H_MSG_TYPE_RX_IND,
493 HTT_T2H_MSG_TYPE_RX_FLUSH,
494 HTT_T2H_MSG_TYPE_PEER_MAP,
495 HTT_T2H_MSG_TYPE_PEER_UNMAP,
496 HTT_T2H_MSG_TYPE_RX_ADDBA,
497 HTT_T2H_MSG_TYPE_RX_DELBA,
498 HTT_T2H_MSG_TYPE_TX_COMPL_IND,
499 HTT_T2H_MSG_TYPE_PKTLOG,
500 HTT_T2H_MSG_TYPE_STATS_CONF,
501 HTT_T2H_MSG_TYPE_RX_FRAG_IND,
502 HTT_T2H_MSG_TYPE_SEC_IND,
503 HTT_T2H_MSG_TYPE_RC_UPDATE_IND,
504 HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
505 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
506 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND,
507 HTT_T2H_MSG_TYPE_RX_PN_IND,
508 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND,
509 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND,
510 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE,
511 HTT_T2H_MSG_TYPE_CHAN_CHANGE,
512 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR,
513 HTT_T2H_MSG_TYPE_AGGR_CONF,
514 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD,
515 HTT_T2H_MSG_TYPE_TEST,
516 HTT_T2H_MSG_TYPE_EN_STATS,
517 HTT_T2H_MSG_TYPE_TX_FETCH_IND,
518 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM,
519 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND,
520 HTT_T2H_MSG_TYPE_PEER_STATS,
526 * htt_resp_hdr - header for target-to-host messages
528 * msg_type: see htt_t2h_msg_type
530 struct htt_resp_hdr {
534 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0
535 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff
536 #define HTT_RESP_HDR_MSG_TYPE_LSB 0
538 /* htt_ver_resp - response sent for htt_ver_req */
539 struct htt_ver_resp {
545 #define HTT_MGMT_TX_CMPL_FLAG_ACK_RSSI BIT(0)
547 #define HTT_MGMT_TX_CMPL_INFO_ACK_RSSI_MASK GENMASK(7, 0)
549 struct htt_mgmt_tx_completion {
559 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x1F)
560 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0)
561 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 5)
562 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 6)
563 #define HTT_RX_INDICATION_INFO0_PPDU_DURATION BIT(7)
565 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F
566 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0
567 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0
568 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6
569 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000
570 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12
571 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000
572 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18
573 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000
574 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24
576 #define HTT_TX_CMPL_FLAG_DATA_RSSI BIT(0)
577 #define HTT_TX_CMPL_FLAG_PPID_PRESENT BIT(1)
578 #define HTT_TX_CMPL_FLAG_PA_PRESENT BIT(2)
579 #define HTT_TX_CMPL_FLAG_PPDU_DURATION_PRESENT BIT(3)
581 struct htt_rx_indication_hdr {
582 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */
584 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */
587 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0)
588 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E)
589 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1)
590 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5)
591 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6)
592 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7)
594 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF
595 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0
596 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000
597 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24
599 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF
600 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0
601 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000
602 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24
604 enum htt_rx_legacy_rate {
615 HTT_RX_CCK_11_LP = 0,
616 HTT_RX_CCK_5_5_LP = 1,
625 enum htt_rx_legacy_rate_type {
626 HTT_RX_LEGACY_RATE_OFDM = 0,
627 HTT_RX_LEGACY_RATE_CCK
630 enum htt_rx_preamble_type {
633 HTT_RX_HT_WITH_TXBF = 0x9,
635 HTT_RX_VHT_WITH_TXBF = 0xD,
639 * Fields: phy_err_valid, phy_err_code, tsf,
640 * usec_timestamp, sub_usec_timestamp
641 * ..are valid only if end_valid == 1.
643 * Fields: rssi_chains, legacy_rate_type,
644 * legacy_rate_cck, preamble_type, service,
646 * ..are valid only if start_valid == 1;
648 struct htt_rx_indication_ppdu {
650 u8 sub_usec_timestamp;
652 u8 info0; /* HTT_RX_INDICATION_INFO0_ */
658 } __packed rssi_chains[4];
660 __le32 usec_timestamp;
661 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */
662 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */
665 enum htt_rx_mpdu_status {
666 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0,
667 HTT_RX_IND_MPDU_STATUS_OK,
668 HTT_RX_IND_MPDU_STATUS_ERR_FCS,
669 HTT_RX_IND_MPDU_STATUS_ERR_DUP,
670 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY,
671 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER,
672 /* only accept EAPOL frames */
673 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER,
674 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC,
675 /* Non-data in promiscuous mode */
676 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL,
677 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR,
678 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR,
679 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR,
680 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR,
681 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR,
684 * MISC: discard for unspecified reasons.
685 * Leave this enum value last.
687 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF
690 struct htt_rx_indication_mpdu_range {
692 u8 mpdu_range_status; /* %htt_rx_mpdu_status */
697 struct htt_rx_indication_prefix {
698 __le16 fw_rx_desc_bytes;
703 struct htt_rx_indication {
704 struct htt_rx_indication_hdr hdr;
705 struct htt_rx_indication_ppdu ppdu;
706 struct htt_rx_indication_prefix prefix;
709 * the following fields are both dynamically sized, so
710 * take care addressing them
713 /* the size of this is %fw_rx_desc_bytes */
714 struct fw_rx_desc_base fw_desc;
717 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4)
718 * and has %num_mpdu_ranges elements.
720 struct htt_rx_indication_mpdu_range mpdu_ranges[0];
723 /* High latency version of the RX indication */
724 struct htt_rx_indication_hl {
725 struct htt_rx_indication_hdr hdr;
726 struct htt_rx_indication_ppdu ppdu;
727 struct htt_rx_indication_prefix prefix;
728 struct fw_rx_desc_hl fw_desc;
729 struct htt_rx_indication_mpdu_range mpdu_ranges[0];
732 static inline struct htt_rx_indication_mpdu_range *
733 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind)
737 ptr += sizeof(rx_ind->hdr)
738 + sizeof(rx_ind->ppdu)
739 + sizeof(rx_ind->prefix)
740 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4);
744 static inline struct htt_rx_indication_mpdu_range *
745 htt_rx_ind_get_mpdu_ranges_hl(struct htt_rx_indication_hl *rx_ind)
749 ptr += sizeof(rx_ind->hdr)
750 + sizeof(rx_ind->ppdu)
751 + sizeof(rx_ind->prefix)
752 + sizeof(rx_ind->fw_desc);
756 enum htt_rx_flush_mpdu_status {
757 HTT_RX_FLUSH_MPDU_DISCARD = 0,
758 HTT_RX_FLUSH_MPDU_REORDER = 1,
762 * htt_rx_flush - discard or reorder given range of mpdus
764 * Note: host must check if all sequence numbers between
765 * [seq_num_start, seq_num_end-1] are valid.
767 struct htt_rx_flush {
771 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */
772 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */
773 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */
776 struct htt_rx_peer_map {
784 struct htt_rx_peer_unmap {
789 enum htt_security_types {
795 HTT_SECURITY_TKIP_NOMIC,
796 HTT_SECURITY_AES_CCMP,
799 HTT_NUM_SECURITY_TYPES /* keep this last! */
802 enum htt_security_flags {
803 #define HTT_SECURITY_TYPE_MASK 0x7F
804 #define HTT_SECURITY_TYPE_LSB 0
805 HTT_SECURITY_IS_UNICAST = 1 << 7
808 struct htt_security_indication {
810 /* dont use bitfields; undefined behaviour */
811 u8 flags; /* %htt_security_flags */
813 u8 security_type:7, /* %htt_security_types */
822 #define HTT_RX_BA_INFO0_TID_MASK 0x000F
823 #define HTT_RX_BA_INFO0_TID_LSB 0
824 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0
825 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4
827 struct htt_rx_addba {
829 __le16 info0; /* %HTT_RX_BA_INFO0_ */
832 struct htt_rx_delba {
834 __le16 info0; /* %HTT_RX_BA_INFO0_ */
837 enum htt_data_tx_status {
838 HTT_DATA_TX_STATUS_OK = 0,
839 HTT_DATA_TX_STATUS_DISCARD = 1,
840 HTT_DATA_TX_STATUS_NO_ACK = 2,
841 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */
842 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128
845 enum htt_data_tx_flags {
846 #define HTT_DATA_TX_STATUS_MASK 0x07
847 #define HTT_DATA_TX_STATUS_LSB 0
848 #define HTT_DATA_TX_TID_MASK 0x78
849 #define HTT_DATA_TX_TID_LSB 3
850 HTT_DATA_TX_TID_INVALID = 1 << 7
853 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF
855 struct htt_data_tx_completion {
865 u8 flags2; /* HTT_TX_CMPL_FLAG_DATA_RSSI */
866 __le16 msdus[0]; /* variable length based on %num_msdus */
869 #define HTT_TX_PPDU_DUR_INFO0_PEER_ID_MASK GENMASK(15, 0)
870 #define HTT_TX_PPDU_DUR_INFO0_TID_MASK GENMASK(20, 16)
872 struct htt_data_tx_ppdu_dur {
873 __le32 info0; /* HTT_TX_PPDU_DUR_INFO0_ */
874 __le32 tx_duration; /* in usecs */
877 #define HTT_TX_COMPL_PPDU_DUR_INFO0_NUM_ENTRIES_MASK GENMASK(7, 0)
879 struct htt_data_tx_compl_ppdu_dur {
880 __le32 info0; /* HTT_TX_COMPL_PPDU_DUR_INFO0_ */
881 struct htt_data_tx_ppdu_dur ppdu_dur[0];
884 struct htt_tx_compl_ind_base {
886 u16 payload[1/*or more*/];
889 struct htt_rc_tx_done_params {
893 u32 num_enqued; /* 1 for non-AMPDU */
895 u32 num_failed; /* for AMPDU */
901 struct htt_rc_update {
907 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */
910 /* see htt_rx_indication for similar fields and descriptions */
911 struct htt_rx_fragment_indication {
913 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */
920 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */
921 __le16 fw_rx_desc_bytes;
924 u8 fw_msdu_rx_desc[0];
927 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F
928 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0
929 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20
930 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5
932 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F
933 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0
934 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0
935 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6
937 struct htt_rx_pn_ind {
947 struct htt_rx_offload_msdu {
956 struct htt_rx_offload_ind {
961 struct htt_rx_in_ord_msdu_desc {
968 struct htt_rx_in_ord_msdu_desc_ext {
975 struct htt_rx_in_ord_ind {
982 struct htt_rx_in_ord_msdu_desc msdu_descs32[0];
983 struct htt_rx_in_ord_msdu_desc_ext msdu_descs64[0];
987 #define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f
988 #define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0
989 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020
990 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5
991 #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040
992 #define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6
995 * target -> host test message definition
997 * The following field definitions describe the format of the test
998 * message sent from the target to the host.
999 * The message consists of a 4-octet header, followed by a variable
1000 * number of 32-bit integer values, followed by a variable number
1001 * of 8-bit character values.
1004 * |-----------------------------------------------------------|
1005 * | num chars | num ints | msg type |
1006 * |-----------------------------------------------------------|
1008 * |-----------------------------------------------------------|
1010 * |-----------------------------------------------------------|
1012 * |-----------------------------------------------------------|
1013 * | char 3 | char 2 | char 1 | char 0 |
1014 * |-----------------------------------------------------------|
1015 * | | | ... | char 4 |
1016 * |-----------------------------------------------------------|
1019 * Purpose: identifies this as a test message
1020 * Value: HTT_MSG_TYPE_TEST
1023 * Purpose: indicate how many 32-bit integers follow the message header
1026 * Purpose: indicate how many 8-bit characters follow the series of integers
1028 struct htt_rx_test {
1032 /* payload consists of 2 lists:
1033 * a) num_ints * sizeof(__le32)
1034 * b) num_chars * sizeof(u8) aligned to 4bytes
1039 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test)
1041 return (__le32 *)rx_test->payload;
1044 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test)
1046 return rx_test->payload + (rx_test->num_ints * sizeof(__le32));
1050 * target -> host packet log message
1052 * The following field definitions describe the format of the packet log
1053 * message sent from the target to the host.
1054 * The message consists of a 4-octet header,followed by a variable number
1055 * of 32-bit character values.
1057 * |31 24|23 16|15 8|7 0|
1058 * |-----------------------------------------------------------|
1059 * | | | | msg type |
1060 * |-----------------------------------------------------------|
1062 * |-----------------------------------------------------------|
1065 * Purpose: identifies this as a test message
1066 * Value: HTT_MSG_TYPE_PACKETLOG
1068 struct htt_pktlog_msg {
1073 struct htt_dbg_stats_rx_reorder_stats {
1074 /* Non QoS MPDUs received */
1075 __le32 deliver_non_qos;
1077 /* MPDUs received in-order */
1078 __le32 deliver_in_order;
1080 /* Flush due to reorder timer expired */
1081 __le32 deliver_flush_timeout;
1083 /* Flush due to move out of window */
1084 __le32 deliver_flush_oow;
1086 /* Flush due to DELBA */
1087 __le32 deliver_flush_delba;
1089 /* MPDUs dropped due to FCS error */
1092 /* MPDUs dropped due to monitor mode non-data packet */
1095 /* MPDUs dropped due to invalid peer */
1096 __le32 invalid_peer;
1098 /* MPDUs dropped due to duplication (non aggregation) */
1099 __le32 dup_non_aggr;
1101 /* MPDUs dropped due to processed before */
1104 /* MPDUs dropped due to duplicate in reorder queue */
1105 __le32 dup_in_reorder;
1107 /* Reorder timeout happened */
1108 __le32 reorder_timeout;
1110 /* invalid bar ssn */
1111 __le32 invalid_bar_ssn;
1113 /* reorder reset due to bar ssn */
1117 struct htt_dbg_stats_wal_tx_stats {
1118 /* Num HTT cookies queued to dispatch list */
1121 /* Num HTT cookies dispatched */
1122 __le32 comp_delivered;
1124 /* Num MSDU queued to WAL */
1127 /* Num MPDU queue to WAL */
1130 /* Num MSDUs dropped by WMM limit */
1133 /* Num Local frames queued */
1134 __le32 local_enqued;
1136 /* Num Local frames done */
1139 /* Num queued to HW */
1142 /* Num PPDU reaped from HW */
1148 /* Num PPDUs cleaned up in TX abort */
1151 /* Num MPDUs requed by SW */
1152 __le32 mpdus_requed;
1154 /* excessive retries */
1157 /* data hw rate code */
1160 /* Scheduler self triggers */
1161 __le32 self_triggers;
1163 /* frames dropped due to excessive sw retries */
1164 __le32 sw_retry_failure;
1166 /* illegal rate phy errors */
1167 __le32 illgl_rate_phy_err;
1169 /* wal pdev continuous xretry */
1170 __le32 pdev_cont_xretry;
1172 /* wal pdev continuous xretry */
1173 __le32 pdev_tx_timeout;
1175 /* wal pdev resets */
1178 __le32 phy_underrun;
1180 /* MPDU is more than txop limit */
1184 struct htt_dbg_stats_wal_rx_stats {
1185 /* Cnts any change in ring routing mid-ppdu */
1186 __le32 mid_ppdu_route_change;
1188 /* Total number of statuses processed */
1191 /* Extra frags on rings 0-3 */
1197 /* MSDUs / MPDUs delivered to HTT */
1201 /* MSDUs / MPDUs delivered to local stack */
1205 /* AMSDUs that have more MSDUs than the status ring size */
1206 __le32 oversize_amsdu;
1208 /* Number of PHY errors */
1211 /* Number of PHY errors drops */
1212 __le32 phy_err_drop;
1214 /* Number of mpdu errors - FCS, MIC, ENC etc. */
1218 struct htt_dbg_stats_wal_peer_stats {
1219 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */
1222 struct htt_dbg_stats_wal_pdev_txrx {
1223 struct htt_dbg_stats_wal_tx_stats tx_stats;
1224 struct htt_dbg_stats_wal_rx_stats rx_stats;
1225 struct htt_dbg_stats_wal_peer_stats peer_stats;
1228 struct htt_dbg_stats_rx_rate_info {
1240 * htt_dbg_stats_status -
1241 * present - The requested stats have been delivered in full.
1242 * This indicates that either the stats information was contained
1243 * in its entirety within this message, or else this message
1244 * completes the delivery of the requested stats info that was
1245 * partially delivered through earlier STATS_CONF messages.
1246 * partial - The requested stats have been delivered in part.
1247 * One or more subsequent STATS_CONF messages with the same
1248 * cookie value will be sent to deliver the remainder of the
1250 * error - The requested stats could not be delivered, for example due
1251 * to a shortage of memory to construct a message holding the
1253 * invalid - The requested stat type is either not recognized, or the
1254 * target is configured to not gather the stats type in question.
1255 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1256 * series_done - This special value indicates that no further stats info
1257 * elements are present within a series of stats info elems
1258 * (within a stats upload confirmation message).
1260 enum htt_dbg_stats_status {
1261 HTT_DBG_STATS_STATUS_PRESENT = 0,
1262 HTT_DBG_STATS_STATUS_PARTIAL = 1,
1263 HTT_DBG_STATS_STATUS_ERROR = 2,
1264 HTT_DBG_STATS_STATUS_INVALID = 3,
1265 HTT_DBG_STATS_STATUS_SERIES_DONE = 7
1269 * target -> host statistics upload
1271 * The following field definitions describe the format of the HTT target
1272 * to host stats upload confirmation message.
1273 * The message contains a cookie echoed from the HTT host->target stats
1274 * upload request, which identifies which request the confirmation is
1275 * for, and a series of tag-length-value stats information elements.
1276 * The tag-length header for each stats info element also includes a
1277 * status field, to indicate whether the request for the stat type in
1278 * question was fully met, partially met, unable to be met, or invalid
1279 * (if the stat type in question is disabled in the target).
1280 * A special value of all 1's in this status field is used to indicate
1281 * the end of the series of stats info elements.
1284 * |31 16|15 8|7 5|4 0|
1285 * |------------------------------------------------------------|
1286 * | reserved | msg type |
1287 * |------------------------------------------------------------|
1289 * |------------------------------------------------------------|
1291 * |------------------------------------------------------------|
1292 * | stats entry length | reserved | S |stat type|
1293 * |------------------------------------------------------------|
1295 * | type-specific stats info |
1297 * |------------------------------------------------------------|
1298 * | stats entry length | reserved | S |stat type|
1299 * |------------------------------------------------------------|
1301 * | type-specific stats info |
1303 * |------------------------------------------------------------|
1304 * | n/a | reserved | 111 | n/a |
1305 * |------------------------------------------------------------|
1309 * Purpose: identifies this is a statistics upload confirmation message
1313 * Purpose: Provide a mechanism to match a target->host stats confirmation
1314 * message with its preceding host->target stats request message.
1315 * Value: LSBs of the opaque cookie specified by the host-side requestor
1318 * Purpose: Provide a mechanism to match a target->host stats confirmation
1319 * message with its preceding host->target stats request message.
1320 * Value: MSBs of the opaque cookie specified by the host-side requestor
1322 * Stats Information Element tag-length header fields:
1325 * Purpose: identifies the type of statistics info held in the
1326 * following information element
1327 * Value: htt_dbg_stats_type
1330 * Purpose: indicate whether the requested stats are present
1331 * Value: htt_dbg_stats_status, including a special value (0x7) to mark
1332 * the completion of the stats entry series
1335 * Purpose: indicate the stats information size
1336 * Value: This field specifies the number of bytes of stats information
1337 * that follows the element tag-length header.
1338 * It is expected but not required that this length is a multiple of
1339 * 4 bytes. Even if the length is not an integer multiple of 4, the
1340 * subsequent stats entry header will begin on a 4-byte aligned
1344 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F
1345 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0
1346 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0
1347 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5
1349 struct htt_stats_conf_item {
1353 u8 stat_type:5; /* %HTT_DBG_STATS_ */
1354 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */
1359 u8 payload[0]; /* roundup(length, 4) long */
1362 struct htt_stats_conf {
1367 /* each item has variable length! */
1368 struct htt_stats_conf_item items[0];
1371 static inline struct htt_stats_conf_item *htt_stats_conf_next_item(
1372 const struct htt_stats_conf_item *item)
1374 return (void *)item + sizeof(*item) + roundup(item->length, 4);
1378 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank
1380 * The following field definitions describe the format of the HTT host
1381 * to target frag_desc/msdu_ext bank configuration message.
1382 * The message contains the based address and the min and max id of the
1383 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and
1384 * MSDU_EXT/FRAG_DESC.
1385 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr.
1386 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0
1387 * the hardware does the mapping/translation.
1389 * Total banks that can be configured is configured to 16.
1391 * This should be called before any TX has be initiated by the HTT
1393 * |31 16|15 8|7 5|4 0|
1394 * |------------------------------------------------------------|
1395 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type |
1396 * |------------------------------------------------------------|
1397 * | BANK0_BASE_ADDRESS |
1398 * |------------------------------------------------------------|
1400 * |------------------------------------------------------------|
1401 * | BANK15_BASE_ADDRESS |
1402 * |------------------------------------------------------------|
1403 * | BANK0_MAX_ID | BANK0_MIN_ID |
1404 * |------------------------------------------------------------|
1406 * |------------------------------------------------------------|
1407 * | BANK15_MAX_ID | BANK15_MIN_ID |
1408 * |------------------------------------------------------------|
1413 * - BANKx_BASE_ADDRESS
1415 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT
1416 * bank physical/bus address.
1419 * Purpose: Provide a mechanism to specify the min index that needs to
1423 * Purpose: Provide a mechanism to specify the max index that needs to
1426 struct htt_frag_desc_bank_id {
1431 /* real is 16 but it wouldn't fit in the max htt message size
1432 * so we use a conservatively safe value for now
1434 #define HTT_FRAG_DESC_BANK_MAX 4
1436 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03
1437 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0
1438 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2)
1439 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3)
1440 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4)
1441 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB 4
1443 enum htt_q_depth_type {
1444 HTT_Q_DEPTH_TYPE_BYTES = 0,
1445 HTT_Q_DEPTH_TYPE_MSDUS = 1,
1448 #define HTT_TX_Q_STATE_NUM_PEERS (TARGET_10_4_NUM_QCACHE_PEERS_MAX + \
1449 TARGET_10_4_NUM_VDEVS)
1450 #define HTT_TX_Q_STATE_NUM_TIDS 8
1451 #define HTT_TX_Q_STATE_ENTRY_SIZE 1
1452 #define HTT_TX_Q_STATE_ENTRY_MULTIPLIER 0
1455 * htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config
1457 * Defines host q state format and behavior. See htt_q_state.
1459 * @record_size: Defines the size of each host q entry in bytes. In practice
1460 * however firmware (at least 10.4.3-00191) ignores this host
1461 * configuration value and uses hardcoded value of 1.
1462 * @record_multiplier: This is valid only when q depth type is MSDUs. It
1463 * defines the exponent for the power of 2 multiplication.
1465 struct htt_q_state_conf {
1470 u8 record_multiplier;
1474 struct htt_frag_desc_bank_cfg32 {
1475 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */
1478 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX];
1479 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX];
1480 struct htt_q_state_conf q_state;
1483 struct htt_frag_desc_bank_cfg64 {
1484 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */
1487 __le64 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX];
1488 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX];
1489 struct htt_q_state_conf q_state;
1492 #define HTT_TX_Q_STATE_ENTRY_COEFFICIENT 128
1493 #define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK 0x3f
1494 #define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB 0
1495 #define HTT_TX_Q_STATE_ENTRY_EXP_MASK 0xc0
1496 #define HTT_TX_Q_STATE_ENTRY_EXP_LSB 6
1499 * htt_q_state - shared between host and firmware via DMA
1501 * This structure is used for the host to expose it's software queue state to
1502 * firmware so that its rate control can schedule fetch requests for optimized
1503 * performance. This is most notably used for MU-MIMO aggregation when multiple
1504 * MU clients are connected.
1506 * @count: Each element defines the host queue depth. When q depth type was
1507 * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as:
1508 * FACTOR * 128 * 8^EXP (see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and
1509 * HTT_TX_Q_STATE_ENTRY_EXP_MASK). When q depth type was configured as
1510 * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 **
1511 * record_multiplier (see htt_q_state_conf).
1512 * @map: Used by firmware to quickly check which host queues are not empty. It
1513 * is a bitmap simply saying.
1514 * @seq: Used by firmware to quickly check if the host queues were updated
1515 * since it last checked.
1517 * FIXME: Is the q_state map[] size calculation really correct?
1519 struct htt_q_state {
1520 u8 count[HTT_TX_Q_STATE_NUM_TIDS][HTT_TX_Q_STATE_NUM_PEERS];
1521 u32 map[HTT_TX_Q_STATE_NUM_TIDS][(HTT_TX_Q_STATE_NUM_PEERS + 31) / 32];
1525 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK 0x0fff
1526 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB 0
1527 #define HTT_TX_FETCH_RECORD_INFO_TID_MASK 0xf000
1528 #define HTT_TX_FETCH_RECORD_INFO_TID_LSB 12
1530 struct htt_tx_fetch_record {
1531 __le16 info; /* HTT_TX_FETCH_IND_RECORD_INFO_ */
1536 struct htt_tx_fetch_ind {
1538 __le16 fetch_seq_num;
1540 __le16 num_resp_ids;
1542 struct htt_tx_fetch_record records[0];
1543 __le32 resp_ids[0]; /* ath10k_htt_get_tx_fetch_ind_resp_ids() */
1546 static inline void *
1547 ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind *ind)
1549 return (void *)&ind->records[le16_to_cpu(ind->num_records)];
1552 struct htt_tx_fetch_resp {
1555 __le16 fetch_seq_num;
1558 struct htt_tx_fetch_record records[0];
1561 struct htt_tx_fetch_confirm {
1563 __le16 num_resp_ids;
1567 enum htt_tx_mode_switch_mode {
1568 HTT_TX_MODE_SWITCH_PUSH = 0,
1569 HTT_TX_MODE_SWITCH_PUSH_PULL = 1,
1572 #define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0)
1573 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK 0xfffe
1574 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB 1
1576 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK 0x0003
1577 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB 0
1578 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK 0xfffc
1579 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB 2
1581 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK 0x0fff
1582 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB 0
1583 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK 0xf000
1584 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB 12
1586 struct htt_tx_mode_switch_record {
1587 __le16 info0; /* HTT_TX_MODE_SWITCH_RECORD_INFO0_ */
1588 __le16 num_max_msdus;
1591 struct htt_tx_mode_switch_ind {
1593 __le16 info0; /* HTT_TX_MODE_SWITCH_IND_INFO0_ */
1594 __le16 info1; /* HTT_TX_MODE_SWITCH_IND_INFO1_ */
1596 struct htt_tx_mode_switch_record records[0];
1599 struct htt_channel_change {
1602 __le32 center_freq1;
1603 __le32 center_freq2;
1607 struct htt_per_peer_tx_stats_ind {
1610 __le32 failed_bytes;
1622 struct htt_peer_tx_stats {
1629 #define ATH10K_10_2_TX_STATS_OFFSET 136
1630 #define PEER_STATS_FOR_NO_OF_PPDUS 4
1632 struct ath10k_10_2_peer_tx_stats {
1633 u8 ratecode[PEER_STATS_FOR_NO_OF_PPDUS];
1634 u8 success_pkts[PEER_STATS_FOR_NO_OF_PPDUS];
1635 __le16 success_bytes[PEER_STATS_FOR_NO_OF_PPDUS];
1636 u8 retry_pkts[PEER_STATS_FOR_NO_OF_PPDUS];
1637 __le16 retry_bytes[PEER_STATS_FOR_NO_OF_PPDUS];
1638 u8 failed_pkts[PEER_STATS_FOR_NO_OF_PPDUS];
1639 __le16 failed_bytes[PEER_STATS_FOR_NO_OF_PPDUS];
1640 u8 flags[PEER_STATS_FOR_NO_OF_PPDUS];
1647 /* WEP: 24-bit PN */
1650 /* TKIP or CCMP: 48-bit PN */
1653 /* WAPI: 128-bit PN */
1658 struct htt_cmd_hdr hdr;
1660 struct htt_ver_req ver_req;
1661 struct htt_mgmt_tx_desc mgmt_tx;
1662 struct htt_data_tx_desc data_tx;
1663 struct htt_rx_ring_setup_32 rx_setup_32;
1664 struct htt_rx_ring_setup_64 rx_setup_64;
1665 struct htt_stats_req stats_req;
1666 struct htt_oob_sync_req oob_sync_req;
1667 struct htt_aggr_conf aggr_conf;
1668 struct htt_aggr_conf_v2 aggr_conf_v2;
1669 struct htt_frag_desc_bank_cfg32 frag_desc_bank_cfg32;
1670 struct htt_frag_desc_bank_cfg64 frag_desc_bank_cfg64;
1671 struct htt_tx_fetch_resp tx_fetch_resp;
1676 struct htt_resp_hdr hdr;
1678 struct htt_ver_resp ver_resp;
1679 struct htt_mgmt_tx_completion mgmt_tx_completion;
1680 struct htt_data_tx_completion data_tx_completion;
1681 struct htt_rx_indication rx_ind;
1682 struct htt_rx_indication_hl rx_ind_hl;
1683 struct htt_rx_fragment_indication rx_frag_ind;
1684 struct htt_rx_peer_map peer_map;
1685 struct htt_rx_peer_unmap peer_unmap;
1686 struct htt_rx_flush rx_flush;
1687 struct htt_rx_addba rx_addba;
1688 struct htt_rx_delba rx_delba;
1689 struct htt_security_indication security_indication;
1690 struct htt_rc_update rc_update;
1691 struct htt_rx_test rx_test;
1692 struct htt_pktlog_msg pktlog_msg;
1693 struct htt_stats_conf stats_conf;
1694 struct htt_rx_pn_ind rx_pn_ind;
1695 struct htt_rx_offload_ind rx_offload_ind;
1696 struct htt_rx_in_ord_ind rx_in_ord_ind;
1697 struct htt_tx_fetch_ind tx_fetch_ind;
1698 struct htt_tx_fetch_confirm tx_fetch_confirm;
1699 struct htt_tx_mode_switch_ind tx_mode_switch_ind;
1700 struct htt_channel_change chan_change;
1701 struct htt_peer_tx_stats peer_tx_stats;
1705 /*** host side structures follow ***/
1707 struct htt_tx_done {
1713 enum htt_tx_compl_state {
1714 HTT_TX_COMPL_STATE_NONE,
1715 HTT_TX_COMPL_STATE_ACK,
1716 HTT_TX_COMPL_STATE_NOACK,
1717 HTT_TX_COMPL_STATE_DISCARD,
1720 struct htt_peer_map_event {
1726 struct htt_peer_unmap_event {
1730 struct ath10k_htt_txbuf_32 {
1731 struct htt_data_tx_desc_frag frags[2];
1732 struct ath10k_htc_hdr htc_hdr;
1733 struct htt_cmd_hdr cmd_hdr;
1734 struct htt_data_tx_desc cmd_tx;
1735 } __packed __aligned(4);
1737 struct ath10k_htt_txbuf_64 {
1738 struct htt_data_tx_desc_frag frags[2];
1739 struct ath10k_htc_hdr htc_hdr;
1740 struct htt_cmd_hdr cmd_hdr;
1741 struct htt_data_tx_desc_64 cmd_tx;
1742 } __packed __aligned(4);
1746 enum ath10k_htc_ep_id eid;
1748 u8 target_version_major;
1749 u8 target_version_minor;
1750 struct completion target_version_received;
1754 const enum htt_t2h_msg_type *t2h_msg_types;
1755 u32 t2h_msg_types_max;
1759 * Ring of network buffer objects - This ring is
1760 * used exclusively by the host SW. This ring
1761 * mirrors the dev_addrs_ring that is shared
1762 * between the host SW and the MAC HW. The host SW
1763 * uses this netbufs ring to locate the network
1764 * buffer objects whose data buffers the HW has
1767 struct sk_buff **netbufs_ring;
1769 /* This is used only with firmware supporting IN_ORD_IND.
1771 * With Full Rx Reorder the HTT Rx Ring is more of a temporary
1772 * buffer ring from which buffer addresses are copied by the
1773 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND
1774 * pointing to specific (re-ordered) buffers.
1776 * FIXME: With kernel generic hashing functions there's a lot
1777 * of hash collisions for sk_buffs.
1780 DECLARE_HASHTABLE(skb_table, 4);
1783 * Ring of buffer addresses -
1784 * This ring holds the "physical" device address of the
1785 * rx buffers the host SW provides for the MAC HW to
1789 __le64 *paddrs_ring_64;
1790 __le32 *paddrs_ring_32;
1794 * Base address of ring, as a "physical" device address
1795 * rather than a CPU address.
1797 dma_addr_t base_paddr;
1799 /* how many elems in the ring (power of 2) */
1803 unsigned int size_mask;
1805 /* how many rx buffers to keep in the ring */
1808 /* how many rx buffers (full+empty) are in the ring */
1812 * alloc_idx - where HTT SW has deposited empty buffers
1813 * This is allocated in consistent mem, so that the FW can
1814 * read this variable, and program the HW's FW_IDX reg with
1815 * the value of this shadow register.
1822 /* where HTT SW has processed bufs filled by rx MAC DMA */
1824 unsigned int msdu_payld;
1828 * refill_retry_timer - timer triggered when the ring is
1829 * not refilled to the level expected
1831 struct timer_list refill_retry_timer;
1833 /* Protects access to all rx ring buffer state variables */
1837 unsigned int prefetch_len;
1839 /* Protects access to pending_tx, num_pending_tx */
1841 int max_num_pending_tx;
1843 int num_pending_mgmt_tx;
1844 struct idr pending_tx;
1845 wait_queue_head_t empty_tx_wq;
1847 /* FIFO for storing tx done status {ack, no-ack, discard} and msdu id */
1848 DECLARE_KFIFO_PTR(txdone_fifo, struct htt_tx_done);
1850 /* set if host-fw communication goes haywire
1851 * used to avoid further failures
1854 atomic_t num_mpdus_ready;
1856 /* This is used to group tx/rx completions separately and process them
1857 * in batches to reduce cache stalls
1859 struct sk_buff_head rx_msdus_q;
1860 struct sk_buff_head rx_in_ord_compl_q;
1861 struct sk_buff_head tx_fetch_ind_q;
1863 /* rx_status template */
1864 struct ieee80211_rx_status rx_status;
1869 struct htt_msdu_ext_desc *vaddr_desc_32;
1870 struct htt_msdu_ext_desc_64 *vaddr_desc_64;
1878 struct ath10k_htt_txbuf_32 *vaddr_txbuff_32;
1879 struct ath10k_htt_txbuf_64 *vaddr_txbuff_64;
1886 struct htt_q_state *vaddr;
1888 u16 num_push_allowed;
1891 enum htt_tx_mode_switch_mode mode;
1892 enum htt_q_depth_type type;
1895 bool tx_mem_allocated;
1896 const struct ath10k_htt_tx_ops *tx_ops;
1897 const struct ath10k_htt_rx_ops *rx_ops;
1900 struct ath10k_htt_tx_ops {
1901 int (*htt_send_rx_ring_cfg)(struct ath10k_htt *htt);
1902 int (*htt_send_frag_desc_bank_cfg)(struct ath10k_htt *htt);
1903 int (*htt_alloc_frag_desc)(struct ath10k_htt *htt);
1904 void (*htt_free_frag_desc)(struct ath10k_htt *htt);
1905 int (*htt_tx)(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode,
1906 struct sk_buff *msdu);
1907 int (*htt_alloc_txbuff)(struct ath10k_htt *htt);
1908 void (*htt_free_txbuff)(struct ath10k_htt *htt);
1909 int (*htt_h2t_aggr_cfg_msg)(struct ath10k_htt *htt,
1910 u8 max_subfrms_ampdu,
1911 u8 max_subfrms_amsdu);
1914 static inline int ath10k_htt_send_rx_ring_cfg(struct ath10k_htt *htt)
1916 if (!htt->tx_ops->htt_send_rx_ring_cfg)
1919 return htt->tx_ops->htt_send_rx_ring_cfg(htt);
1922 static inline int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt)
1924 if (!htt->tx_ops->htt_send_frag_desc_bank_cfg)
1927 return htt->tx_ops->htt_send_frag_desc_bank_cfg(htt);
1930 static inline int ath10k_htt_alloc_frag_desc(struct ath10k_htt *htt)
1932 if (!htt->tx_ops->htt_alloc_frag_desc)
1935 return htt->tx_ops->htt_alloc_frag_desc(htt);
1938 static inline void ath10k_htt_free_frag_desc(struct ath10k_htt *htt)
1940 if (htt->tx_ops->htt_free_frag_desc)
1941 htt->tx_ops->htt_free_frag_desc(htt);
1944 static inline int ath10k_htt_tx(struct ath10k_htt *htt,
1945 enum ath10k_hw_txrx_mode txmode,
1946 struct sk_buff *msdu)
1948 return htt->tx_ops->htt_tx(htt, txmode, msdu);
1951 static inline int ath10k_htt_alloc_txbuff(struct ath10k_htt *htt)
1953 if (!htt->tx_ops->htt_alloc_txbuff)
1956 return htt->tx_ops->htt_alloc_txbuff(htt);
1959 static inline void ath10k_htt_free_txbuff(struct ath10k_htt *htt)
1961 if (htt->tx_ops->htt_free_txbuff)
1962 htt->tx_ops->htt_free_txbuff(htt);
1965 struct ath10k_htt_rx_ops {
1966 size_t (*htt_get_rx_ring_size)(struct ath10k_htt *htt);
1967 void (*htt_config_paddrs_ring)(struct ath10k_htt *htt, void *vaddr);
1968 void (*htt_set_paddrs_ring)(struct ath10k_htt *htt, dma_addr_t paddr,
1970 void* (*htt_get_vaddr_ring)(struct ath10k_htt *htt);
1971 void (*htt_reset_paddrs_ring)(struct ath10k_htt *htt, int idx);
1974 static inline size_t ath10k_htt_get_rx_ring_size(struct ath10k_htt *htt)
1976 if (!htt->rx_ops->htt_get_rx_ring_size)
1979 return htt->rx_ops->htt_get_rx_ring_size(htt);
1982 static inline void ath10k_htt_config_paddrs_ring(struct ath10k_htt *htt,
1985 if (htt->rx_ops->htt_config_paddrs_ring)
1986 htt->rx_ops->htt_config_paddrs_ring(htt, vaddr);
1989 static inline void ath10k_htt_set_paddrs_ring(struct ath10k_htt *htt,
1993 if (htt->rx_ops->htt_set_paddrs_ring)
1994 htt->rx_ops->htt_set_paddrs_ring(htt, paddr, idx);
1997 static inline void *ath10k_htt_get_vaddr_ring(struct ath10k_htt *htt)
1999 if (!htt->rx_ops->htt_get_vaddr_ring)
2002 return htt->rx_ops->htt_get_vaddr_ring(htt);
2005 static inline void ath10k_htt_reset_paddrs_ring(struct ath10k_htt *htt, int idx)
2007 if (htt->rx_ops->htt_reset_paddrs_ring)
2008 htt->rx_ops->htt_reset_paddrs_ring(htt, idx);
2011 #define RX_HTT_HDR_STATUS_LEN 64
2013 /* This structure layout is programmed via rx ring setup
2014 * so that FW knows how to transfer the rx descriptor to the host.
2015 * Buffers like this are placed on the rx ring.
2017 struct htt_rx_desc {
2019 /* This field is filled on the host using the msdu buffer
2020 * from htt_rx_indication
2022 struct fw_rx_desc_base fw_desc;
2026 struct rx_attention attention;
2027 struct rx_frag_info frag_info;
2028 struct rx_mpdu_start mpdu_start;
2029 struct rx_msdu_start msdu_start;
2030 struct rx_msdu_end msdu_end;
2031 struct rx_mpdu_end mpdu_end;
2032 struct rx_ppdu_start ppdu_start;
2033 struct rx_ppdu_end ppdu_end;
2035 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN];
2039 #define HTT_RX_DESC_HL_INFO_SEQ_NUM_MASK 0x00000fff
2040 #define HTT_RX_DESC_HL_INFO_SEQ_NUM_LSB 0
2041 #define HTT_RX_DESC_HL_INFO_ENCRYPTED_MASK 0x00001000
2042 #define HTT_RX_DESC_HL_INFO_ENCRYPTED_LSB 12
2043 #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_MASK 0x00002000
2044 #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_LSB 13
2045 #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_MASK 0x00008000
2046 #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_LSB 15
2047 #define HTT_RX_DESC_HL_INFO_FRAGMENT_MASK 0x00010000
2048 #define HTT_RX_DESC_HL_INFO_FRAGMENT_LSB 16
2049 #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_MASK 0x01fe0000
2050 #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_LSB 17
2052 struct htt_rx_desc_base_hl {
2053 __le32 info; /* HTT_RX_DESC_HL_INFO_ */
2056 struct htt_rx_chan_info {
2057 __le16 primary_chan_center_freq_mhz;
2058 __le16 contig_chan1_center_freq_mhz;
2059 __le16 contig_chan2_center_freq_mhz;
2064 #define HTT_RX_DESC_ALIGN 8
2066 #define HTT_MAC_ADDR_LEN 6
2070 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size,
2071 * rounded up to a cache line size.
2073 #define HTT_RX_BUF_SIZE 1920
2074 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc))
2076 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle
2077 * aggregated traffic more nicely.
2079 #define ATH10K_HTT_MAX_NUM_REFILL 100
2082 * DMA_MAP expects the buffer to be an integral number of cache lines.
2083 * Rather than checking the actual cache line size, this code makes a
2084 * conservative estimate of what the cache line size could be.
2086 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */
2087 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1)
2089 /* These values are default in most firmware revisions and apparently are a
2090 * sweet spot performance wise.
2092 #define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3
2093 #define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64
2095 int ath10k_htt_connect(struct ath10k_htt *htt);
2096 int ath10k_htt_init(struct ath10k *ar);
2097 int ath10k_htt_setup(struct ath10k_htt *htt);
2099 int ath10k_htt_tx_start(struct ath10k_htt *htt);
2100 void ath10k_htt_tx_stop(struct ath10k_htt *htt);
2101 void ath10k_htt_tx_destroy(struct ath10k_htt *htt);
2102 void ath10k_htt_tx_free(struct ath10k_htt *htt);
2104 int ath10k_htt_rx_alloc(struct ath10k_htt *htt);
2105 int ath10k_htt_rx_ring_refill(struct ath10k *ar);
2106 void ath10k_htt_rx_free(struct ath10k_htt *htt);
2108 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb);
2109 void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb);
2110 bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb);
2111 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt);
2112 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie);
2113 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
2114 u8 max_subfrms_ampdu,
2115 u8 max_subfrms_amsdu);
2116 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb);
2117 int ath10k_htt_tx_fetch_resp(struct ath10k *ar,
2119 __le16 fetch_seq_num,
2120 struct htt_tx_fetch_record *records,
2121 size_t num_records);
2123 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw,
2124 struct ieee80211_txq *txq);
2125 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw,
2126 struct ieee80211_txq *txq);
2127 void ath10k_htt_tx_txq_sync(struct ath10k *ar);
2128 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt);
2129 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt);
2130 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt);
2131 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt,
2134 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb);
2135 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id);
2136 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu);
2137 void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar,
2138 struct sk_buff *skb);
2139 int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget);
2140 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt);
2141 void ath10k_htt_set_rx_ops(struct ath10k_htt *htt);