2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #include <linux/bug.h>
23 #include <linux/interrupt.h>
24 #include <linux/dmapool.h>
25 #include <linux/hashtable.h>
26 #include <linux/kfifo.h>
27 #include <net/mac80211.h>
33 enum htt_dbg_stats_type {
34 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0,
35 HTT_DBG_STATS_RX_REORDER = 1 << 1,
36 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2,
37 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3,
38 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4,
39 /* bits 5-23 currently reserved */
41 HTT_DBG_NUM_STATS /* keep this last */
44 enum htt_h2t_msg_type { /* host-to-target */
45 HTT_H2T_MSG_TYPE_VERSION_REQ = 0,
46 HTT_H2T_MSG_TYPE_TX_FRM = 1,
47 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2,
48 HTT_H2T_MSG_TYPE_STATS_REQ = 3,
49 HTT_H2T_MSG_TYPE_SYNC = 4,
50 HTT_H2T_MSG_TYPE_AGGR_CFG = 5,
51 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6,
53 /* This command is used for sending management frames in HTT < 3.0.
54 * HTT >= 3.0 uses TX_FRM for everything.
56 HTT_H2T_MSG_TYPE_MGMT_TX = 7,
57 HTT_H2T_MSG_TYPE_TX_FETCH_RESP = 11,
59 HTT_H2T_NUM_MSGS /* keep this last */
67 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)];
71 * HTT tx MSDU descriptor
73 * The HTT tx MSDU descriptor is created by the host HTT SW for each
74 * tx MSDU. The HTT tx MSDU descriptor contains the information that
75 * the target firmware needs for the FW's tx processing, particularly
76 * for creating the HW msdu descriptor.
77 * The same HTT tx descriptor is used for HL and LL systems, though
78 * a few fields within the tx descriptor are used only by LL or
80 * The HTT tx descriptor is defined in two manners: by a struct with
81 * bitfields, and by a series of [dword offset, bit mask, bit shift]
83 * The target should use the struct def, for simplicitly and clarity,
84 * but the host shall use the bit-mast + bit-shift defs, to be endian-
85 * neutral. Specifically, the host shall use the get/set macros built
86 * around the mask + shift defs.
88 struct htt_data_tx_desc_frag {
90 struct double_word_addr {
93 } __packed dword_addr;
94 struct triple_word_addr {
98 } __packed tword_addr;
102 struct htt_msdu_ext_desc {
104 __le16 ip_identification;
107 struct htt_data_tx_desc_frag frags[6];
110 struct htt_msdu_ext_desc_64 {
112 __le16 ip_identification;
115 struct htt_data_tx_desc_frag frags[6];
118 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0)
119 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1)
120 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2)
121 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3)
122 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4)
124 #define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \
125 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE \
126 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE \
127 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \
128 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE)
130 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 BIT(16)
131 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 BIT(17)
132 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 BIT(18)
133 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 BIT(19)
134 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64 BIT(20)
135 #define HTT_MSDU_EXT_DESC_FLAG_PARTIAL_CSUM_ENABLE_64 BIT(21)
137 #define HTT_MSDU_CHECKSUM_ENABLE_64 (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 \
138 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 \
139 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 \
140 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 \
141 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64)
143 enum htt_data_tx_desc_flags0 {
144 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0,
145 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1,
146 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2,
147 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3,
148 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4
149 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0
150 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5
153 enum htt_data_tx_desc_flags1 {
154 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6
155 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F
156 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0
157 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5
158 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0
159 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6
160 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11,
161 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12,
162 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13,
163 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14,
164 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15
167 enum htt_data_tx_ext_tid {
168 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16,
169 HTT_DATA_TX_EXT_TID_MGMT = 17,
170 HTT_DATA_TX_EXT_TID_INVALID = 31
173 #define HTT_INVALID_PEERID 0xFFFF
176 * htt_data_tx_desc - used for data tx path
178 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1.
179 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_
180 * for special kinds of tids
181 * postponed: only for HL hosts. indicates if this is a resend
182 * (HL hosts manage queues on the host )
183 * more_in_batch: only for HL hosts. indicates if more packets are
184 * pending. this allows target to wait and aggregate
185 * freq: 0 means home channel of given vdev. intended for offchannel
187 struct htt_data_tx_desc {
188 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */
189 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */
198 } __packed offchan_tx;
200 u8 prefetch[0]; /* start of frame, for FW classification engine */
203 struct htt_data_tx_desc_64 {
204 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */
205 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */
214 } __packed offchan_tx;
216 u8 prefetch[0]; /* start of frame, for FW classification engine */
219 enum htt_rx_ring_flags {
220 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0,
221 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1,
222 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2,
223 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3,
224 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4,
225 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5,
226 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6,
227 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7,
228 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8,
229 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9,
230 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10,
231 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11,
232 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12,
233 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13,
234 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14,
235 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15
238 #define HTT_RX_RING_SIZE_MIN 128
239 #define HTT_RX_RING_SIZE_MAX 2048
240 #define HTT_RX_RING_SIZE HTT_RX_RING_SIZE_MAX
241 #define HTT_RX_RING_FILL_LEVEL (((HTT_RX_RING_SIZE) / 2) - 1)
242 #define HTT_RX_RING_FILL_LEVEL_DUAL_MAC (HTT_RX_RING_SIZE - 1)
244 struct htt_rx_ring_setup_ring32 {
245 __le32 fw_idx_shadow_reg_paddr;
246 __le32 rx_ring_base_paddr;
247 __le16 rx_ring_len; /* in 4-byte words */
248 __le16 rx_ring_bufsize; /* rx skb size - in bytes */
249 __le16 flags; /* %HTT_RX_RING_FLAGS_ */
250 __le16 fw_idx_init_val;
252 /* the following offsets are in 4-byte units */
253 __le16 mac80211_hdr_offset;
254 __le16 msdu_payload_offset;
255 __le16 ppdu_start_offset;
256 __le16 ppdu_end_offset;
257 __le16 mpdu_start_offset;
258 __le16 mpdu_end_offset;
259 __le16 msdu_start_offset;
260 __le16 msdu_end_offset;
261 __le16 rx_attention_offset;
262 __le16 frag_info_offset;
265 struct htt_rx_ring_setup_ring64 {
266 __le64 fw_idx_shadow_reg_paddr;
267 __le64 rx_ring_base_paddr;
268 __le16 rx_ring_len; /* in 4-byte words */
269 __le16 rx_ring_bufsize; /* rx skb size - in bytes */
270 __le16 flags; /* %HTT_RX_RING_FLAGS_ */
271 __le16 fw_idx_init_val;
273 /* the following offsets are in 4-byte units */
274 __le16 mac80211_hdr_offset;
275 __le16 msdu_payload_offset;
276 __le16 ppdu_start_offset;
277 __le16 ppdu_end_offset;
278 __le16 mpdu_start_offset;
279 __le16 mpdu_end_offset;
280 __le16 msdu_start_offset;
281 __le16 msdu_end_offset;
282 __le16 rx_attention_offset;
283 __le16 frag_info_offset;
286 struct htt_rx_ring_setup_hdr {
287 u8 num_rings; /* supported values: 1, 2 */
291 struct htt_rx_ring_setup_32 {
292 struct htt_rx_ring_setup_hdr hdr;
293 struct htt_rx_ring_setup_ring32 rings[0];
296 struct htt_rx_ring_setup_64 {
297 struct htt_rx_ring_setup_hdr hdr;
298 struct htt_rx_ring_setup_ring64 rings[0];
302 * htt_stats_req - request target to send specified statistics
304 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ
305 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually
306 * so make sure its little-endian.
307 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually
308 * so make sure its little-endian.
309 * @cfg_val: stat_type specific configuration
310 * @stat_type: see %htt_dbg_stats_type
311 * @cookie_lsb: used for confirmation message from target->host
312 * @cookie_msb: ditto as %cookie
314 struct htt_stats_req {
328 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff
331 * htt_oob_sync_req - request out-of-band sync
333 * The HTT SYNC tells the target to suspend processing of subsequent
334 * HTT host-to-target messages until some other target agent locally
335 * informs the target HTT FW that the current sync counter is equal to
336 * or greater than (in a modulo sense) the sync counter specified in
339 * This allows other host-target components to synchronize their operation
340 * with HTT, e.g. to ensure that tx frames don't get transmitted until a
341 * security key has been downloaded to and activated by the target.
342 * In the absence of any explicit synchronization counter value
343 * specification, the target HTT FW will use zero as the default current
346 * The HTT target FW will suspend its host->target message processing as long
347 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128.
349 struct htt_oob_sync_req {
354 struct htt_aggr_conf {
355 u8 max_num_ampdu_subframes;
356 /* amsdu_subframes is limited by 0x1F mask */
357 u8 max_num_amsdu_subframes;
360 struct htt_aggr_conf_v2 {
361 u8 max_num_ampdu_subframes;
362 /* amsdu_subframes is limited by 0x1F mask */
363 u8 max_num_amsdu_subframes;
367 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32
368 struct htt_mgmt_tx_desc_qca99x0 {
372 struct htt_mgmt_tx_desc {
373 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)];
378 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN];
380 struct htt_mgmt_tx_desc_qca99x0 qca99x0;
384 enum htt_mgmt_tx_status {
385 HTT_MGMT_TX_STATUS_OK = 0,
386 HTT_MGMT_TX_STATUS_RETRY = 1,
387 HTT_MGMT_TX_STATUS_DROP = 2
390 /*=== target -> host messages ===============================================*/
392 enum htt_main_t2h_msg_type {
393 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0,
394 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1,
395 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2,
396 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3,
397 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
398 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5,
399 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6,
400 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
401 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8,
402 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9,
403 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
404 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb,
405 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
406 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
407 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf,
408 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10,
409 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11,
410 HTT_MAIN_T2H_MSG_TYPE_TEST,
412 HTT_MAIN_T2H_NUM_MSGS
415 enum htt_10x_t2h_msg_type {
416 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0,
417 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1,
418 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2,
419 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3,
420 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
421 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5,
422 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6,
423 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
424 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8,
425 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9,
426 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
427 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb,
428 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc,
429 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
430 HTT_10X_T2H_MSG_TYPE_TEST = 0xe,
431 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf,
432 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11,
433 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12,
434 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13,
439 enum htt_tlv_t2h_msg_type {
440 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0,
441 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1,
442 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2,
443 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3,
444 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
445 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5,
446 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6,
447 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
448 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8,
449 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9,
450 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
451 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb,
452 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* deprecated */
453 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
454 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
455 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf,
456 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10,
457 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11,
458 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12,
460 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14,
461 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15,
462 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16,
463 HTT_TLV_T2H_MSG_TYPE_TEST,
468 enum htt_10_4_t2h_msg_type {
469 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF = 0x0,
470 HTT_10_4_T2H_MSG_TYPE_RX_IND = 0x1,
471 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH = 0x2,
472 HTT_10_4_T2H_MSG_TYPE_PEER_MAP = 0x3,
473 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
474 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA = 0x5,
475 HTT_10_4_T2H_MSG_TYPE_RX_DELBA = 0x6,
476 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
477 HTT_10_4_T2H_MSG_TYPE_PKTLOG = 0x8,
478 HTT_10_4_T2H_MSG_TYPE_STATS_CONF = 0x9,
479 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
480 HTT_10_4_T2H_MSG_TYPE_SEC_IND = 0xb,
481 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc,
482 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
483 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
484 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE = 0xf,
485 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0x10,
486 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND = 0x11,
487 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x12,
488 HTT_10_4_T2H_MSG_TYPE_TEST = 0x13,
489 HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14,
490 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15,
491 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16,
492 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM = 0x17,
493 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18,
494 /* 0x19 to 0x2f are reserved */
495 HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND = 0x30,
496 HTT_10_4_T2H_MSG_TYPE_PEER_STATS = 0x31,
498 HTT_10_4_T2H_NUM_MSGS
501 enum htt_t2h_msg_type {
502 HTT_T2H_MSG_TYPE_VERSION_CONF,
503 HTT_T2H_MSG_TYPE_RX_IND,
504 HTT_T2H_MSG_TYPE_RX_FLUSH,
505 HTT_T2H_MSG_TYPE_PEER_MAP,
506 HTT_T2H_MSG_TYPE_PEER_UNMAP,
507 HTT_T2H_MSG_TYPE_RX_ADDBA,
508 HTT_T2H_MSG_TYPE_RX_DELBA,
509 HTT_T2H_MSG_TYPE_TX_COMPL_IND,
510 HTT_T2H_MSG_TYPE_PKTLOG,
511 HTT_T2H_MSG_TYPE_STATS_CONF,
512 HTT_T2H_MSG_TYPE_RX_FRAG_IND,
513 HTT_T2H_MSG_TYPE_SEC_IND,
514 HTT_T2H_MSG_TYPE_RC_UPDATE_IND,
515 HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
516 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
517 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND,
518 HTT_T2H_MSG_TYPE_RX_PN_IND,
519 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND,
520 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND,
521 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE,
522 HTT_T2H_MSG_TYPE_CHAN_CHANGE,
523 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR,
524 HTT_T2H_MSG_TYPE_AGGR_CONF,
525 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD,
526 HTT_T2H_MSG_TYPE_TEST,
527 HTT_T2H_MSG_TYPE_EN_STATS,
528 HTT_T2H_MSG_TYPE_TX_FETCH_IND,
529 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM,
530 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND,
531 HTT_T2H_MSG_TYPE_PEER_STATS,
537 * htt_resp_hdr - header for target-to-host messages
539 * msg_type: see htt_t2h_msg_type
541 struct htt_resp_hdr {
545 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0
546 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff
547 #define HTT_RESP_HDR_MSG_TYPE_LSB 0
549 /* htt_ver_resp - response sent for htt_ver_req */
550 struct htt_ver_resp {
556 #define HTT_MGMT_TX_CMPL_FLAG_ACK_RSSI BIT(0)
558 #define HTT_MGMT_TX_CMPL_INFO_ACK_RSSI_MASK GENMASK(7, 0)
560 struct htt_mgmt_tx_completion {
570 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x1F)
571 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0)
572 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 5)
573 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 6)
574 #define HTT_RX_INDICATION_INFO0_PPDU_DURATION BIT(7)
576 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F
577 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0
578 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0
579 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6
580 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000
581 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12
582 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000
583 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18
584 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000
585 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24
587 #define HTT_TX_CMPL_FLAG_DATA_RSSI BIT(0)
588 #define HTT_TX_CMPL_FLAG_PPID_PRESENT BIT(1)
589 #define HTT_TX_CMPL_FLAG_PA_PRESENT BIT(2)
590 #define HTT_TX_CMPL_FLAG_PPDU_DURATION_PRESENT BIT(3)
592 struct htt_rx_indication_hdr {
593 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */
595 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */
598 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0)
599 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E)
600 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1)
601 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5)
602 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6)
603 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7)
605 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF
606 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0
607 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000
608 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24
610 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF
611 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0
612 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000
613 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24
615 enum htt_rx_legacy_rate {
626 HTT_RX_CCK_11_LP = 0,
627 HTT_RX_CCK_5_5_LP = 1,
636 enum htt_rx_legacy_rate_type {
637 HTT_RX_LEGACY_RATE_OFDM = 0,
638 HTT_RX_LEGACY_RATE_CCK
641 enum htt_rx_preamble_type {
644 HTT_RX_HT_WITH_TXBF = 0x9,
646 HTT_RX_VHT_WITH_TXBF = 0xD,
650 * Fields: phy_err_valid, phy_err_code, tsf,
651 * usec_timestamp, sub_usec_timestamp
652 * ..are valid only if end_valid == 1.
654 * Fields: rssi_chains, legacy_rate_type,
655 * legacy_rate_cck, preamble_type, service,
657 * ..are valid only if start_valid == 1;
659 struct htt_rx_indication_ppdu {
661 u8 sub_usec_timestamp;
663 u8 info0; /* HTT_RX_INDICATION_INFO0_ */
669 } __packed rssi_chains[4];
671 __le32 usec_timestamp;
672 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */
673 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */
676 enum htt_rx_mpdu_status {
677 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0,
678 HTT_RX_IND_MPDU_STATUS_OK,
679 HTT_RX_IND_MPDU_STATUS_ERR_FCS,
680 HTT_RX_IND_MPDU_STATUS_ERR_DUP,
681 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY,
682 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER,
683 /* only accept EAPOL frames */
684 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER,
685 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC,
686 /* Non-data in promiscuous mode */
687 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL,
688 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR,
689 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR,
690 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR,
691 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR,
692 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR,
695 * MISC: discard for unspecified reasons.
696 * Leave this enum value last.
698 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF
701 struct htt_rx_indication_mpdu_range {
703 u8 mpdu_range_status; /* %htt_rx_mpdu_status */
708 struct htt_rx_indication_prefix {
709 __le16 fw_rx_desc_bytes;
714 struct htt_rx_indication {
715 struct htt_rx_indication_hdr hdr;
716 struct htt_rx_indication_ppdu ppdu;
717 struct htt_rx_indication_prefix prefix;
720 * the following fields are both dynamically sized, so
721 * take care addressing them
724 /* the size of this is %fw_rx_desc_bytes */
725 struct fw_rx_desc_base fw_desc;
728 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4)
729 * and has %num_mpdu_ranges elements.
731 struct htt_rx_indication_mpdu_range mpdu_ranges[0];
734 /* High latency version of the RX indication */
735 struct htt_rx_indication_hl {
736 struct htt_rx_indication_hdr hdr;
737 struct htt_rx_indication_ppdu ppdu;
738 struct htt_rx_indication_prefix prefix;
739 struct fw_rx_desc_hl fw_desc;
740 struct htt_rx_indication_mpdu_range mpdu_ranges[0];
743 static inline struct htt_rx_indication_mpdu_range *
744 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind)
748 ptr += sizeof(rx_ind->hdr)
749 + sizeof(rx_ind->ppdu)
750 + sizeof(rx_ind->prefix)
751 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4);
755 static inline struct htt_rx_indication_mpdu_range *
756 htt_rx_ind_get_mpdu_ranges_hl(struct htt_rx_indication_hl *rx_ind)
760 ptr += sizeof(rx_ind->hdr)
761 + sizeof(rx_ind->ppdu)
762 + sizeof(rx_ind->prefix)
763 + sizeof(rx_ind->fw_desc);
767 enum htt_rx_flush_mpdu_status {
768 HTT_RX_FLUSH_MPDU_DISCARD = 0,
769 HTT_RX_FLUSH_MPDU_REORDER = 1,
773 * htt_rx_flush - discard or reorder given range of mpdus
775 * Note: host must check if all sequence numbers between
776 * [seq_num_start, seq_num_end-1] are valid.
778 struct htt_rx_flush {
782 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */
783 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */
784 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */
787 struct htt_rx_peer_map {
795 struct htt_rx_peer_unmap {
800 enum htt_security_types {
806 HTT_SECURITY_TKIP_NOMIC,
807 HTT_SECURITY_AES_CCMP,
810 HTT_NUM_SECURITY_TYPES /* keep this last! */
813 enum htt_security_flags {
814 #define HTT_SECURITY_TYPE_MASK 0x7F
815 #define HTT_SECURITY_TYPE_LSB 0
816 HTT_SECURITY_IS_UNICAST = 1 << 7
819 struct htt_security_indication {
821 /* dont use bitfields; undefined behaviour */
822 u8 flags; /* %htt_security_flags */
824 u8 security_type:7, /* %htt_security_types */
833 #define HTT_RX_BA_INFO0_TID_MASK 0x000F
834 #define HTT_RX_BA_INFO0_TID_LSB 0
835 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0
836 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4
838 struct htt_rx_addba {
840 __le16 info0; /* %HTT_RX_BA_INFO0_ */
843 struct htt_rx_delba {
845 __le16 info0; /* %HTT_RX_BA_INFO0_ */
848 enum htt_data_tx_status {
849 HTT_DATA_TX_STATUS_OK = 0,
850 HTT_DATA_TX_STATUS_DISCARD = 1,
851 HTT_DATA_TX_STATUS_NO_ACK = 2,
852 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */
853 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128
856 enum htt_data_tx_flags {
857 #define HTT_DATA_TX_STATUS_MASK 0x07
858 #define HTT_DATA_TX_STATUS_LSB 0
859 #define HTT_DATA_TX_TID_MASK 0x78
860 #define HTT_DATA_TX_TID_LSB 3
861 HTT_DATA_TX_TID_INVALID = 1 << 7
864 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF
866 struct htt_data_tx_completion {
876 u8 flags2; /* HTT_TX_CMPL_FLAG_DATA_RSSI */
877 __le16 msdus[0]; /* variable length based on %num_msdus */
880 #define HTT_TX_PPDU_DUR_INFO0_PEER_ID_MASK GENMASK(15, 0)
881 #define HTT_TX_PPDU_DUR_INFO0_TID_MASK GENMASK(20, 16)
883 struct htt_data_tx_ppdu_dur {
884 __le32 info0; /* HTT_TX_PPDU_DUR_INFO0_ */
885 __le32 tx_duration; /* in usecs */
888 #define HTT_TX_COMPL_PPDU_DUR_INFO0_NUM_ENTRIES_MASK GENMASK(7, 0)
890 struct htt_data_tx_compl_ppdu_dur {
891 __le32 info0; /* HTT_TX_COMPL_PPDU_DUR_INFO0_ */
892 struct htt_data_tx_ppdu_dur ppdu_dur[0];
895 struct htt_tx_compl_ind_base {
897 u16 payload[1/*or more*/];
900 struct htt_rc_tx_done_params {
904 u32 num_enqued; /* 1 for non-AMPDU */
906 u32 num_failed; /* for AMPDU */
912 struct htt_rc_update {
918 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */
921 /* see htt_rx_indication for similar fields and descriptions */
922 struct htt_rx_fragment_indication {
924 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */
931 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */
932 __le16 fw_rx_desc_bytes;
935 u8 fw_msdu_rx_desc[0];
938 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F
939 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0
940 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20
941 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5
943 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F
944 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0
945 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0
946 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6
948 struct htt_rx_pn_ind {
958 struct htt_rx_offload_msdu {
967 struct htt_rx_offload_ind {
972 struct htt_rx_in_ord_msdu_desc {
979 struct htt_rx_in_ord_msdu_desc_ext {
986 struct htt_rx_in_ord_ind {
993 struct htt_rx_in_ord_msdu_desc msdu_descs32[0];
994 struct htt_rx_in_ord_msdu_desc_ext msdu_descs64[0];
998 #define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f
999 #define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0
1000 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020
1001 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5
1002 #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040
1003 #define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6
1006 * target -> host test message definition
1008 * The following field definitions describe the format of the test
1009 * message sent from the target to the host.
1010 * The message consists of a 4-octet header, followed by a variable
1011 * number of 32-bit integer values, followed by a variable number
1012 * of 8-bit character values.
1015 * |-----------------------------------------------------------|
1016 * | num chars | num ints | msg type |
1017 * |-----------------------------------------------------------|
1019 * |-----------------------------------------------------------|
1021 * |-----------------------------------------------------------|
1023 * |-----------------------------------------------------------|
1024 * | char 3 | char 2 | char 1 | char 0 |
1025 * |-----------------------------------------------------------|
1026 * | | | ... | char 4 |
1027 * |-----------------------------------------------------------|
1030 * Purpose: identifies this as a test message
1031 * Value: HTT_MSG_TYPE_TEST
1034 * Purpose: indicate how many 32-bit integers follow the message header
1037 * Purpose: indicate how many 8-bit characters follow the series of integers
1039 struct htt_rx_test {
1043 /* payload consists of 2 lists:
1044 * a) num_ints * sizeof(__le32)
1045 * b) num_chars * sizeof(u8) aligned to 4bytes
1050 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test)
1052 return (__le32 *)rx_test->payload;
1055 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test)
1057 return rx_test->payload + (rx_test->num_ints * sizeof(__le32));
1061 * target -> host packet log message
1063 * The following field definitions describe the format of the packet log
1064 * message sent from the target to the host.
1065 * The message consists of a 4-octet header,followed by a variable number
1066 * of 32-bit character values.
1068 * |31 24|23 16|15 8|7 0|
1069 * |-----------------------------------------------------------|
1070 * | | | | msg type |
1071 * |-----------------------------------------------------------|
1073 * |-----------------------------------------------------------|
1076 * Purpose: identifies this as a test message
1077 * Value: HTT_MSG_TYPE_PACKETLOG
1079 struct htt_pktlog_msg {
1084 struct htt_dbg_stats_rx_reorder_stats {
1085 /* Non QoS MPDUs received */
1086 __le32 deliver_non_qos;
1088 /* MPDUs received in-order */
1089 __le32 deliver_in_order;
1091 /* Flush due to reorder timer expired */
1092 __le32 deliver_flush_timeout;
1094 /* Flush due to move out of window */
1095 __le32 deliver_flush_oow;
1097 /* Flush due to DELBA */
1098 __le32 deliver_flush_delba;
1100 /* MPDUs dropped due to FCS error */
1103 /* MPDUs dropped due to monitor mode non-data packet */
1106 /* MPDUs dropped due to invalid peer */
1107 __le32 invalid_peer;
1109 /* MPDUs dropped due to duplication (non aggregation) */
1110 __le32 dup_non_aggr;
1112 /* MPDUs dropped due to processed before */
1115 /* MPDUs dropped due to duplicate in reorder queue */
1116 __le32 dup_in_reorder;
1118 /* Reorder timeout happened */
1119 __le32 reorder_timeout;
1121 /* invalid bar ssn */
1122 __le32 invalid_bar_ssn;
1124 /* reorder reset due to bar ssn */
1128 struct htt_dbg_stats_wal_tx_stats {
1129 /* Num HTT cookies queued to dispatch list */
1132 /* Num HTT cookies dispatched */
1133 __le32 comp_delivered;
1135 /* Num MSDU queued to WAL */
1138 /* Num MPDU queue to WAL */
1141 /* Num MSDUs dropped by WMM limit */
1144 /* Num Local frames queued */
1145 __le32 local_enqued;
1147 /* Num Local frames done */
1150 /* Num queued to HW */
1153 /* Num PPDU reaped from HW */
1159 /* Num PPDUs cleaned up in TX abort */
1162 /* Num MPDUs requed by SW */
1163 __le32 mpdus_requed;
1165 /* excessive retries */
1168 /* data hw rate code */
1171 /* Scheduler self triggers */
1172 __le32 self_triggers;
1174 /* frames dropped due to excessive sw retries */
1175 __le32 sw_retry_failure;
1177 /* illegal rate phy errors */
1178 __le32 illgl_rate_phy_err;
1180 /* wal pdev continuous xretry */
1181 __le32 pdev_cont_xretry;
1183 /* wal pdev continuous xretry */
1184 __le32 pdev_tx_timeout;
1186 /* wal pdev resets */
1189 __le32 phy_underrun;
1191 /* MPDU is more than txop limit */
1195 struct htt_dbg_stats_wal_rx_stats {
1196 /* Cnts any change in ring routing mid-ppdu */
1197 __le32 mid_ppdu_route_change;
1199 /* Total number of statuses processed */
1202 /* Extra frags on rings 0-3 */
1208 /* MSDUs / MPDUs delivered to HTT */
1212 /* MSDUs / MPDUs delivered to local stack */
1216 /* AMSDUs that have more MSDUs than the status ring size */
1217 __le32 oversize_amsdu;
1219 /* Number of PHY errors */
1222 /* Number of PHY errors drops */
1223 __le32 phy_err_drop;
1225 /* Number of mpdu errors - FCS, MIC, ENC etc. */
1229 struct htt_dbg_stats_wal_peer_stats {
1230 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */
1233 struct htt_dbg_stats_wal_pdev_txrx {
1234 struct htt_dbg_stats_wal_tx_stats tx_stats;
1235 struct htt_dbg_stats_wal_rx_stats rx_stats;
1236 struct htt_dbg_stats_wal_peer_stats peer_stats;
1239 struct htt_dbg_stats_rx_rate_info {
1251 * htt_dbg_stats_status -
1252 * present - The requested stats have been delivered in full.
1253 * This indicates that either the stats information was contained
1254 * in its entirety within this message, or else this message
1255 * completes the delivery of the requested stats info that was
1256 * partially delivered through earlier STATS_CONF messages.
1257 * partial - The requested stats have been delivered in part.
1258 * One or more subsequent STATS_CONF messages with the same
1259 * cookie value will be sent to deliver the remainder of the
1261 * error - The requested stats could not be delivered, for example due
1262 * to a shortage of memory to construct a message holding the
1264 * invalid - The requested stat type is either not recognized, or the
1265 * target is configured to not gather the stats type in question.
1266 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1267 * series_done - This special value indicates that no further stats info
1268 * elements are present within a series of stats info elems
1269 * (within a stats upload confirmation message).
1271 enum htt_dbg_stats_status {
1272 HTT_DBG_STATS_STATUS_PRESENT = 0,
1273 HTT_DBG_STATS_STATUS_PARTIAL = 1,
1274 HTT_DBG_STATS_STATUS_ERROR = 2,
1275 HTT_DBG_STATS_STATUS_INVALID = 3,
1276 HTT_DBG_STATS_STATUS_SERIES_DONE = 7
1280 * target -> host statistics upload
1282 * The following field definitions describe the format of the HTT target
1283 * to host stats upload confirmation message.
1284 * The message contains a cookie echoed from the HTT host->target stats
1285 * upload request, which identifies which request the confirmation is
1286 * for, and a series of tag-length-value stats information elements.
1287 * The tag-length header for each stats info element also includes a
1288 * status field, to indicate whether the request for the stat type in
1289 * question was fully met, partially met, unable to be met, or invalid
1290 * (if the stat type in question is disabled in the target).
1291 * A special value of all 1's in this status field is used to indicate
1292 * the end of the series of stats info elements.
1295 * |31 16|15 8|7 5|4 0|
1296 * |------------------------------------------------------------|
1297 * | reserved | msg type |
1298 * |------------------------------------------------------------|
1300 * |------------------------------------------------------------|
1302 * |------------------------------------------------------------|
1303 * | stats entry length | reserved | S |stat type|
1304 * |------------------------------------------------------------|
1306 * | type-specific stats info |
1308 * |------------------------------------------------------------|
1309 * | stats entry length | reserved | S |stat type|
1310 * |------------------------------------------------------------|
1312 * | type-specific stats info |
1314 * |------------------------------------------------------------|
1315 * | n/a | reserved | 111 | n/a |
1316 * |------------------------------------------------------------|
1320 * Purpose: identifies this is a statistics upload confirmation message
1324 * Purpose: Provide a mechanism to match a target->host stats confirmation
1325 * message with its preceding host->target stats request message.
1326 * Value: LSBs of the opaque cookie specified by the host-side requestor
1329 * Purpose: Provide a mechanism to match a target->host stats confirmation
1330 * message with its preceding host->target stats request message.
1331 * Value: MSBs of the opaque cookie specified by the host-side requestor
1333 * Stats Information Element tag-length header fields:
1336 * Purpose: identifies the type of statistics info held in the
1337 * following information element
1338 * Value: htt_dbg_stats_type
1341 * Purpose: indicate whether the requested stats are present
1342 * Value: htt_dbg_stats_status, including a special value (0x7) to mark
1343 * the completion of the stats entry series
1346 * Purpose: indicate the stats information size
1347 * Value: This field specifies the number of bytes of stats information
1348 * that follows the element tag-length header.
1349 * It is expected but not required that this length is a multiple of
1350 * 4 bytes. Even if the length is not an integer multiple of 4, the
1351 * subsequent stats entry header will begin on a 4-byte aligned
1355 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F
1356 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0
1357 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0
1358 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5
1360 struct htt_stats_conf_item {
1364 u8 stat_type:5; /* %HTT_DBG_STATS_ */
1365 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */
1370 u8 payload[0]; /* roundup(length, 4) long */
1373 struct htt_stats_conf {
1378 /* each item has variable length! */
1379 struct htt_stats_conf_item items[0];
1382 static inline struct htt_stats_conf_item *htt_stats_conf_next_item(
1383 const struct htt_stats_conf_item *item)
1385 return (void *)item + sizeof(*item) + roundup(item->length, 4);
1389 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank
1391 * The following field definitions describe the format of the HTT host
1392 * to target frag_desc/msdu_ext bank configuration message.
1393 * The message contains the based address and the min and max id of the
1394 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and
1395 * MSDU_EXT/FRAG_DESC.
1396 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr.
1397 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0
1398 * the hardware does the mapping/translation.
1400 * Total banks that can be configured is configured to 16.
1402 * This should be called before any TX has be initiated by the HTT
1404 * |31 16|15 8|7 5|4 0|
1405 * |------------------------------------------------------------|
1406 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type |
1407 * |------------------------------------------------------------|
1408 * | BANK0_BASE_ADDRESS |
1409 * |------------------------------------------------------------|
1411 * |------------------------------------------------------------|
1412 * | BANK15_BASE_ADDRESS |
1413 * |------------------------------------------------------------|
1414 * | BANK0_MAX_ID | BANK0_MIN_ID |
1415 * |------------------------------------------------------------|
1417 * |------------------------------------------------------------|
1418 * | BANK15_MAX_ID | BANK15_MIN_ID |
1419 * |------------------------------------------------------------|
1424 * - BANKx_BASE_ADDRESS
1426 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT
1427 * bank physical/bus address.
1430 * Purpose: Provide a mechanism to specify the min index that needs to
1434 * Purpose: Provide a mechanism to specify the max index that needs to
1437 struct htt_frag_desc_bank_id {
1442 /* real is 16 but it wouldn't fit in the max htt message size
1443 * so we use a conservatively safe value for now
1445 #define HTT_FRAG_DESC_BANK_MAX 4
1447 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03
1448 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0
1449 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2)
1450 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3)
1451 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4)
1452 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB 4
1454 enum htt_q_depth_type {
1455 HTT_Q_DEPTH_TYPE_BYTES = 0,
1456 HTT_Q_DEPTH_TYPE_MSDUS = 1,
1459 #define HTT_TX_Q_STATE_NUM_PEERS (TARGET_10_4_NUM_QCACHE_PEERS_MAX + \
1460 TARGET_10_4_NUM_VDEVS)
1461 #define HTT_TX_Q_STATE_NUM_TIDS 8
1462 #define HTT_TX_Q_STATE_ENTRY_SIZE 1
1463 #define HTT_TX_Q_STATE_ENTRY_MULTIPLIER 0
1466 * htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config
1468 * Defines host q state format and behavior. See htt_q_state.
1470 * @record_size: Defines the size of each host q entry in bytes. In practice
1471 * however firmware (at least 10.4.3-00191) ignores this host
1472 * configuration value and uses hardcoded value of 1.
1473 * @record_multiplier: This is valid only when q depth type is MSDUs. It
1474 * defines the exponent for the power of 2 multiplication.
1476 struct htt_q_state_conf {
1481 u8 record_multiplier;
1485 struct htt_frag_desc_bank_cfg32 {
1486 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */
1489 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX];
1490 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX];
1491 struct htt_q_state_conf q_state;
1494 struct htt_frag_desc_bank_cfg64 {
1495 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */
1498 __le64 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX];
1499 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX];
1500 struct htt_q_state_conf q_state;
1503 #define HTT_TX_Q_STATE_ENTRY_COEFFICIENT 128
1504 #define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK 0x3f
1505 #define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB 0
1506 #define HTT_TX_Q_STATE_ENTRY_EXP_MASK 0xc0
1507 #define HTT_TX_Q_STATE_ENTRY_EXP_LSB 6
1510 * htt_q_state - shared between host and firmware via DMA
1512 * This structure is used for the host to expose it's software queue state to
1513 * firmware so that its rate control can schedule fetch requests for optimized
1514 * performance. This is most notably used for MU-MIMO aggregation when multiple
1515 * MU clients are connected.
1517 * @count: Each element defines the host queue depth. When q depth type was
1518 * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as:
1519 * FACTOR * 128 * 8^EXP (see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and
1520 * HTT_TX_Q_STATE_ENTRY_EXP_MASK). When q depth type was configured as
1521 * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 **
1522 * record_multiplier (see htt_q_state_conf).
1523 * @map: Used by firmware to quickly check which host queues are not empty. It
1524 * is a bitmap simply saying.
1525 * @seq: Used by firmware to quickly check if the host queues were updated
1526 * since it last checked.
1528 * FIXME: Is the q_state map[] size calculation really correct?
1530 struct htt_q_state {
1531 u8 count[HTT_TX_Q_STATE_NUM_TIDS][HTT_TX_Q_STATE_NUM_PEERS];
1532 u32 map[HTT_TX_Q_STATE_NUM_TIDS][(HTT_TX_Q_STATE_NUM_PEERS + 31) / 32];
1536 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK 0x0fff
1537 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB 0
1538 #define HTT_TX_FETCH_RECORD_INFO_TID_MASK 0xf000
1539 #define HTT_TX_FETCH_RECORD_INFO_TID_LSB 12
1541 struct htt_tx_fetch_record {
1542 __le16 info; /* HTT_TX_FETCH_IND_RECORD_INFO_ */
1547 struct htt_tx_fetch_ind {
1549 __le16 fetch_seq_num;
1551 __le16 num_resp_ids;
1553 struct htt_tx_fetch_record records[0];
1554 __le32 resp_ids[0]; /* ath10k_htt_get_tx_fetch_ind_resp_ids() */
1557 static inline void *
1558 ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind *ind)
1560 return (void *)&ind->records[le16_to_cpu(ind->num_records)];
1563 struct htt_tx_fetch_resp {
1566 __le16 fetch_seq_num;
1569 struct htt_tx_fetch_record records[0];
1572 struct htt_tx_fetch_confirm {
1574 __le16 num_resp_ids;
1578 enum htt_tx_mode_switch_mode {
1579 HTT_TX_MODE_SWITCH_PUSH = 0,
1580 HTT_TX_MODE_SWITCH_PUSH_PULL = 1,
1583 #define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0)
1584 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK 0xfffe
1585 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB 1
1587 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK 0x0003
1588 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB 0
1589 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK 0xfffc
1590 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB 2
1592 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK 0x0fff
1593 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB 0
1594 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK 0xf000
1595 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB 12
1597 struct htt_tx_mode_switch_record {
1598 __le16 info0; /* HTT_TX_MODE_SWITCH_RECORD_INFO0_ */
1599 __le16 num_max_msdus;
1602 struct htt_tx_mode_switch_ind {
1604 __le16 info0; /* HTT_TX_MODE_SWITCH_IND_INFO0_ */
1605 __le16 info1; /* HTT_TX_MODE_SWITCH_IND_INFO1_ */
1607 struct htt_tx_mode_switch_record records[0];
1610 struct htt_channel_change {
1613 __le32 center_freq1;
1614 __le32 center_freq2;
1618 struct htt_per_peer_tx_stats_ind {
1621 __le32 failed_bytes;
1633 struct htt_peer_tx_stats {
1640 #define ATH10K_10_2_TX_STATS_OFFSET 136
1641 #define PEER_STATS_FOR_NO_OF_PPDUS 4
1643 struct ath10k_10_2_peer_tx_stats {
1644 u8 ratecode[PEER_STATS_FOR_NO_OF_PPDUS];
1645 u8 success_pkts[PEER_STATS_FOR_NO_OF_PPDUS];
1646 __le16 success_bytes[PEER_STATS_FOR_NO_OF_PPDUS];
1647 u8 retry_pkts[PEER_STATS_FOR_NO_OF_PPDUS];
1648 __le16 retry_bytes[PEER_STATS_FOR_NO_OF_PPDUS];
1649 u8 failed_pkts[PEER_STATS_FOR_NO_OF_PPDUS];
1650 __le16 failed_bytes[PEER_STATS_FOR_NO_OF_PPDUS];
1651 u8 flags[PEER_STATS_FOR_NO_OF_PPDUS];
1658 /* WEP: 24-bit PN */
1661 /* TKIP or CCMP: 48-bit PN */
1664 /* WAPI: 128-bit PN */
1669 struct htt_cmd_hdr hdr;
1671 struct htt_ver_req ver_req;
1672 struct htt_mgmt_tx_desc mgmt_tx;
1673 struct htt_data_tx_desc data_tx;
1674 struct htt_rx_ring_setup_32 rx_setup_32;
1675 struct htt_rx_ring_setup_64 rx_setup_64;
1676 struct htt_stats_req stats_req;
1677 struct htt_oob_sync_req oob_sync_req;
1678 struct htt_aggr_conf aggr_conf;
1679 struct htt_aggr_conf_v2 aggr_conf_v2;
1680 struct htt_frag_desc_bank_cfg32 frag_desc_bank_cfg32;
1681 struct htt_frag_desc_bank_cfg64 frag_desc_bank_cfg64;
1682 struct htt_tx_fetch_resp tx_fetch_resp;
1687 struct htt_resp_hdr hdr;
1689 struct htt_ver_resp ver_resp;
1690 struct htt_mgmt_tx_completion mgmt_tx_completion;
1691 struct htt_data_tx_completion data_tx_completion;
1692 struct htt_rx_indication rx_ind;
1693 struct htt_rx_indication_hl rx_ind_hl;
1694 struct htt_rx_fragment_indication rx_frag_ind;
1695 struct htt_rx_peer_map peer_map;
1696 struct htt_rx_peer_unmap peer_unmap;
1697 struct htt_rx_flush rx_flush;
1698 struct htt_rx_addba rx_addba;
1699 struct htt_rx_delba rx_delba;
1700 struct htt_security_indication security_indication;
1701 struct htt_rc_update rc_update;
1702 struct htt_rx_test rx_test;
1703 struct htt_pktlog_msg pktlog_msg;
1704 struct htt_stats_conf stats_conf;
1705 struct htt_rx_pn_ind rx_pn_ind;
1706 struct htt_rx_offload_ind rx_offload_ind;
1707 struct htt_rx_in_ord_ind rx_in_ord_ind;
1708 struct htt_tx_fetch_ind tx_fetch_ind;
1709 struct htt_tx_fetch_confirm tx_fetch_confirm;
1710 struct htt_tx_mode_switch_ind tx_mode_switch_ind;
1711 struct htt_channel_change chan_change;
1712 struct htt_peer_tx_stats peer_tx_stats;
1716 /*** host side structures follow ***/
1718 struct htt_tx_done {
1724 enum htt_tx_compl_state {
1725 HTT_TX_COMPL_STATE_NONE,
1726 HTT_TX_COMPL_STATE_ACK,
1727 HTT_TX_COMPL_STATE_NOACK,
1728 HTT_TX_COMPL_STATE_DISCARD,
1731 struct htt_peer_map_event {
1737 struct htt_peer_unmap_event {
1741 struct ath10k_htt_txbuf_32 {
1742 struct htt_data_tx_desc_frag frags[2];
1743 struct ath10k_htc_hdr htc_hdr;
1744 struct htt_cmd_hdr cmd_hdr;
1745 struct htt_data_tx_desc cmd_tx;
1746 } __packed __aligned(4);
1748 struct ath10k_htt_txbuf_64 {
1749 struct htt_data_tx_desc_frag frags[2];
1750 struct ath10k_htc_hdr htc_hdr;
1751 struct htt_cmd_hdr cmd_hdr;
1752 struct htt_data_tx_desc_64 cmd_tx;
1753 } __packed __aligned(4);
1757 enum ath10k_htc_ep_id eid;
1759 u8 target_version_major;
1760 u8 target_version_minor;
1761 struct completion target_version_received;
1765 const enum htt_t2h_msg_type *t2h_msg_types;
1766 u32 t2h_msg_types_max;
1770 * Ring of network buffer objects - This ring is
1771 * used exclusively by the host SW. This ring
1772 * mirrors the dev_addrs_ring that is shared
1773 * between the host SW and the MAC HW. The host SW
1774 * uses this netbufs ring to locate the network
1775 * buffer objects whose data buffers the HW has
1778 struct sk_buff **netbufs_ring;
1780 /* This is used only with firmware supporting IN_ORD_IND.
1782 * With Full Rx Reorder the HTT Rx Ring is more of a temporary
1783 * buffer ring from which buffer addresses are copied by the
1784 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND
1785 * pointing to specific (re-ordered) buffers.
1787 * FIXME: With kernel generic hashing functions there's a lot
1788 * of hash collisions for sk_buffs.
1791 DECLARE_HASHTABLE(skb_table, 4);
1794 * Ring of buffer addresses -
1795 * This ring holds the "physical" device address of the
1796 * rx buffers the host SW provides for the MAC HW to
1800 __le64 *paddrs_ring_64;
1801 __le32 *paddrs_ring_32;
1805 * Base address of ring, as a "physical" device address
1806 * rather than a CPU address.
1808 dma_addr_t base_paddr;
1810 /* how many elems in the ring (power of 2) */
1814 unsigned int size_mask;
1816 /* how many rx buffers to keep in the ring */
1819 /* how many rx buffers (full+empty) are in the ring */
1823 * alloc_idx - where HTT SW has deposited empty buffers
1824 * This is allocated in consistent mem, so that the FW can
1825 * read this variable, and program the HW's FW_IDX reg with
1826 * the value of this shadow register.
1833 /* where HTT SW has processed bufs filled by rx MAC DMA */
1835 unsigned int msdu_payld;
1839 * refill_retry_timer - timer triggered when the ring is
1840 * not refilled to the level expected
1842 struct timer_list refill_retry_timer;
1844 /* Protects access to all rx ring buffer state variables */
1848 unsigned int prefetch_len;
1850 /* Protects access to pending_tx, num_pending_tx */
1852 int max_num_pending_tx;
1854 int num_pending_mgmt_tx;
1855 struct idr pending_tx;
1856 wait_queue_head_t empty_tx_wq;
1858 /* FIFO for storing tx done status {ack, no-ack, discard} and msdu id */
1859 DECLARE_KFIFO_PTR(txdone_fifo, struct htt_tx_done);
1861 /* set if host-fw communication goes haywire
1862 * used to avoid further failures
1865 atomic_t num_mpdus_ready;
1867 /* This is used to group tx/rx completions separately and process them
1868 * in batches to reduce cache stalls
1870 struct sk_buff_head rx_msdus_q;
1871 struct sk_buff_head rx_in_ord_compl_q;
1872 struct sk_buff_head tx_fetch_ind_q;
1874 /* rx_status template */
1875 struct ieee80211_rx_status rx_status;
1880 struct htt_msdu_ext_desc *vaddr_desc_32;
1881 struct htt_msdu_ext_desc_64 *vaddr_desc_64;
1889 struct ath10k_htt_txbuf_32 *vaddr_txbuff_32;
1890 struct ath10k_htt_txbuf_64 *vaddr_txbuff_64;
1897 struct htt_q_state *vaddr;
1899 u16 num_push_allowed;
1902 enum htt_tx_mode_switch_mode mode;
1903 enum htt_q_depth_type type;
1906 bool tx_mem_allocated;
1907 const struct ath10k_htt_tx_ops *tx_ops;
1908 const struct ath10k_htt_rx_ops *rx_ops;
1911 struct ath10k_htt_tx_ops {
1912 int (*htt_send_rx_ring_cfg)(struct ath10k_htt *htt);
1913 int (*htt_send_frag_desc_bank_cfg)(struct ath10k_htt *htt);
1914 int (*htt_alloc_frag_desc)(struct ath10k_htt *htt);
1915 void (*htt_free_frag_desc)(struct ath10k_htt *htt);
1916 int (*htt_tx)(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode,
1917 struct sk_buff *msdu);
1918 int (*htt_alloc_txbuff)(struct ath10k_htt *htt);
1919 void (*htt_free_txbuff)(struct ath10k_htt *htt);
1920 int (*htt_h2t_aggr_cfg_msg)(struct ath10k_htt *htt,
1921 u8 max_subfrms_ampdu,
1922 u8 max_subfrms_amsdu);
1925 static inline int ath10k_htt_send_rx_ring_cfg(struct ath10k_htt *htt)
1927 if (!htt->tx_ops->htt_send_rx_ring_cfg)
1930 return htt->tx_ops->htt_send_rx_ring_cfg(htt);
1933 static inline int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt)
1935 if (!htt->tx_ops->htt_send_frag_desc_bank_cfg)
1938 return htt->tx_ops->htt_send_frag_desc_bank_cfg(htt);
1941 static inline int ath10k_htt_alloc_frag_desc(struct ath10k_htt *htt)
1943 if (!htt->tx_ops->htt_alloc_frag_desc)
1946 return htt->tx_ops->htt_alloc_frag_desc(htt);
1949 static inline void ath10k_htt_free_frag_desc(struct ath10k_htt *htt)
1951 if (htt->tx_ops->htt_free_frag_desc)
1952 htt->tx_ops->htt_free_frag_desc(htt);
1955 static inline int ath10k_htt_tx(struct ath10k_htt *htt,
1956 enum ath10k_hw_txrx_mode txmode,
1957 struct sk_buff *msdu)
1959 return htt->tx_ops->htt_tx(htt, txmode, msdu);
1962 static inline int ath10k_htt_alloc_txbuff(struct ath10k_htt *htt)
1964 if (!htt->tx_ops->htt_alloc_txbuff)
1967 return htt->tx_ops->htt_alloc_txbuff(htt);
1970 static inline void ath10k_htt_free_txbuff(struct ath10k_htt *htt)
1972 if (htt->tx_ops->htt_free_txbuff)
1973 htt->tx_ops->htt_free_txbuff(htt);
1976 struct ath10k_htt_rx_ops {
1977 size_t (*htt_get_rx_ring_size)(struct ath10k_htt *htt);
1978 void (*htt_config_paddrs_ring)(struct ath10k_htt *htt, void *vaddr);
1979 void (*htt_set_paddrs_ring)(struct ath10k_htt *htt, dma_addr_t paddr,
1981 void* (*htt_get_vaddr_ring)(struct ath10k_htt *htt);
1982 void (*htt_reset_paddrs_ring)(struct ath10k_htt *htt, int idx);
1985 static inline size_t ath10k_htt_get_rx_ring_size(struct ath10k_htt *htt)
1987 if (!htt->rx_ops->htt_get_rx_ring_size)
1990 return htt->rx_ops->htt_get_rx_ring_size(htt);
1993 static inline void ath10k_htt_config_paddrs_ring(struct ath10k_htt *htt,
1996 if (htt->rx_ops->htt_config_paddrs_ring)
1997 htt->rx_ops->htt_config_paddrs_ring(htt, vaddr);
2000 static inline void ath10k_htt_set_paddrs_ring(struct ath10k_htt *htt,
2004 if (htt->rx_ops->htt_set_paddrs_ring)
2005 htt->rx_ops->htt_set_paddrs_ring(htt, paddr, idx);
2008 static inline void *ath10k_htt_get_vaddr_ring(struct ath10k_htt *htt)
2010 if (!htt->rx_ops->htt_get_vaddr_ring)
2013 return htt->rx_ops->htt_get_vaddr_ring(htt);
2016 static inline void ath10k_htt_reset_paddrs_ring(struct ath10k_htt *htt, int idx)
2018 if (htt->rx_ops->htt_reset_paddrs_ring)
2019 htt->rx_ops->htt_reset_paddrs_ring(htt, idx);
2022 #define RX_HTT_HDR_STATUS_LEN 64
2024 /* This structure layout is programmed via rx ring setup
2025 * so that FW knows how to transfer the rx descriptor to the host.
2026 * Buffers like this are placed on the rx ring.
2028 struct htt_rx_desc {
2030 /* This field is filled on the host using the msdu buffer
2031 * from htt_rx_indication
2033 struct fw_rx_desc_base fw_desc;
2037 struct rx_attention attention;
2038 struct rx_frag_info frag_info;
2039 struct rx_mpdu_start mpdu_start;
2040 struct rx_msdu_start msdu_start;
2041 struct rx_msdu_end msdu_end;
2042 struct rx_mpdu_end mpdu_end;
2043 struct rx_ppdu_start ppdu_start;
2044 struct rx_ppdu_end ppdu_end;
2046 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN];
2050 #define HTT_RX_DESC_HL_INFO_SEQ_NUM_MASK 0x00000fff
2051 #define HTT_RX_DESC_HL_INFO_SEQ_NUM_LSB 0
2052 #define HTT_RX_DESC_HL_INFO_ENCRYPTED_MASK 0x00001000
2053 #define HTT_RX_DESC_HL_INFO_ENCRYPTED_LSB 12
2054 #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_MASK 0x00002000
2055 #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_LSB 13
2056 #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_MASK 0x00008000
2057 #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_LSB 15
2058 #define HTT_RX_DESC_HL_INFO_FRAGMENT_MASK 0x00010000
2059 #define HTT_RX_DESC_HL_INFO_FRAGMENT_LSB 16
2060 #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_MASK 0x01fe0000
2061 #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_LSB 17
2063 struct htt_rx_desc_base_hl {
2064 __le32 info; /* HTT_RX_DESC_HL_INFO_ */
2067 struct htt_rx_chan_info {
2068 __le16 primary_chan_center_freq_mhz;
2069 __le16 contig_chan1_center_freq_mhz;
2070 __le16 contig_chan2_center_freq_mhz;
2075 #define HTT_RX_DESC_ALIGN 8
2077 #define HTT_MAC_ADDR_LEN 6
2081 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size,
2082 * rounded up to a cache line size.
2084 #define HTT_RX_BUF_SIZE 1920
2085 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc))
2087 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle
2088 * aggregated traffic more nicely.
2090 #define ATH10K_HTT_MAX_NUM_REFILL 100
2093 * DMA_MAP expects the buffer to be an integral number of cache lines.
2094 * Rather than checking the actual cache line size, this code makes a
2095 * conservative estimate of what the cache line size could be.
2097 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */
2098 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1)
2100 /* These values are default in most firmware revisions and apparently are a
2101 * sweet spot performance wise.
2103 #define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3
2104 #define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64
2106 int ath10k_htt_connect(struct ath10k_htt *htt);
2107 int ath10k_htt_init(struct ath10k *ar);
2108 int ath10k_htt_setup(struct ath10k_htt *htt);
2110 int ath10k_htt_tx_start(struct ath10k_htt *htt);
2111 void ath10k_htt_tx_stop(struct ath10k_htt *htt);
2112 void ath10k_htt_tx_destroy(struct ath10k_htt *htt);
2113 void ath10k_htt_tx_free(struct ath10k_htt *htt);
2115 int ath10k_htt_rx_alloc(struct ath10k_htt *htt);
2116 int ath10k_htt_rx_ring_refill(struct ath10k *ar);
2117 void ath10k_htt_rx_free(struct ath10k_htt *htt);
2119 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb);
2120 void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb);
2121 bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb);
2122 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt);
2123 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie);
2124 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
2125 u8 max_subfrms_ampdu,
2126 u8 max_subfrms_amsdu);
2127 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb);
2128 int ath10k_htt_tx_fetch_resp(struct ath10k *ar,
2130 __le16 fetch_seq_num,
2131 struct htt_tx_fetch_record *records,
2132 size_t num_records);
2134 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw,
2135 struct ieee80211_txq *txq);
2136 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw,
2137 struct ieee80211_txq *txq);
2138 void ath10k_htt_tx_txq_sync(struct ath10k *ar);
2139 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt);
2140 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt);
2141 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt);
2142 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt,
2145 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb);
2146 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id);
2147 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu);
2148 void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar,
2149 struct sk_buff *skb);
2150 int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget);
2151 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt);
2152 void ath10k_htt_set_rx_ops(struct ath10k_htt *htt);