2 * Cyclades PC300 synchronous serial card driver for Linux
4 * Copyright (C) 2000-2007 Krzysztof Halasa <khc@pm.waw.pl>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
10 * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/>.
12 * Sources of information:
13 * Hitachi HD64572 SCA-II User's Manual
14 * Cyclades PC300 Linux driver
16 * This driver currently supports only PC300/RSV (V.24/V.35) and
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/sched.h>
24 #include <linux/types.h>
25 #include <linux/fcntl.h>
27 #include <linux/string.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/ioport.h>
31 #include <linux/moduleparam.h>
32 #include <linux/netdevice.h>
33 #include <linux/hdlc.h>
34 #include <linux/pci.h>
35 #include <linux/delay.h>
43 #define PC300_PLX_SIZE 0x80 /* PLX control window size (128 B) */
44 #define PC300_SCA_SIZE 0x400 /* SCA window size (1 KB) */
45 #define MAX_TX_BUFFERS 10
47 static int pci_clock_freq = 33000000;
48 static int use_crystal_clock = 0;
49 static unsigned int CLOCK_BASE;
51 /* Masks to access the init_ctrl PLX register */
52 #define PC300_CLKSEL_MASK (0x00000004UL)
53 #define PC300_CHMEDIA_MASK(port) (0x00000020UL << ((port) * 3))
54 #define PC300_CTYPE_MASK (0x00000800UL)
57 enum { PC300_RSV = 1, PC300_X21, PC300_TE }; /* card types */
60 * PLX PCI9050-1 local configuration and shared runtime registers.
61 * This structure can be used to access 9050 registers (memory mapped).
64 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
65 u32 loc_rom_range; /* 10h : Local ROM Range */
66 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
67 u32 loc_rom_base; /* 24h : Local ROM Base */
68 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
69 u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
70 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
71 u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
72 u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
77 typedef struct port_s {
78 struct napi_struct napi;
79 struct net_device *dev;
81 spinlock_t lock; /* TX lock */
82 sync_serial_settings settings;
83 int rxpart; /* partial frame received, next frame invalid*/
84 unsigned short encoding;
85 unsigned short parity;
87 u16 rxin; /* rx ring buffer 'in' pointer */
88 u16 txin; /* tx ring buffer 'in' and 'last' pointers */
90 u8 rxs, txs, tmc; /* SCA registers */
91 u8 phy_node; /* physical port # - 0 or 1 */
96 typedef struct card_s {
97 int type; /* RSV, X21, etc. */
98 int n_ports; /* 1 or 2 ports */
99 u8 __iomem *rambase; /* buffer memory base (virtual) */
100 u8 __iomem *scabase; /* SCA memory base (virtual) */
101 plx9050 __iomem *plxbase; /* PLX registers memory base (virtual) */
102 u32 init_ctrl_value; /* Saved value - 9050 bug workaround */
103 u16 rx_ring_buffers; /* number of buffers in a ring */
105 u16 buff_offset; /* offset of first buffer of first channel */
106 u8 irq; /* interrupt request level */
112 #define sca_in(reg, card) readb(card->scabase + (reg))
113 #define sca_out(value, reg, card) writeb(value, card->scabase + (reg))
114 #define sca_inw(reg, card) readw(card->scabase + (reg))
115 #define sca_outw(value, reg, card) writew(value, card->scabase + (reg))
116 #define sca_inl(reg, card) readl(card->scabase + (reg))
117 #define sca_outl(value, reg, card) writel(value, card->scabase + (reg))
119 #define port_to_card(port) (port->card)
120 #define log_node(port) (port->phy_node)
121 #define phy_node(port) (port->phy_node)
122 #define winbase(card) (card->rambase)
123 #define get_port(card, port) ((port) < (card)->n_ports ? \
124 (&(card)->ports[port]) : (NULL))
129 static void pc300_set_iface(port_t *port)
131 card_t *card = port->card;
132 u32 __iomem * init_ctrl = &card->plxbase->init_ctrl;
133 u16 msci = get_msci(port);
134 u8 rxs = port->rxs & CLK_BRG_MASK;
135 u8 txs = port->txs & CLK_BRG_MASK;
137 sca_out(EXS_TES1, (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
139 switch(port->settings.clock_type) {
141 rxs |= CLK_BRG; /* BRG output */
142 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
146 rxs |= CLK_LINE; /* RXC input */
147 txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
151 rxs |= CLK_LINE; /* RXC input */
152 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
155 default: /* EXTernal clock */
156 rxs |= CLK_LINE; /* RXC input */
157 txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
163 sca_out(rxs, msci + RXS, card);
164 sca_out(txs, msci + TXS, card);
167 if (port->card->type == PC300_RSV) {
168 if (port->iface == IF_IFACE_V35)
169 writel(card->init_ctrl_value |
170 PC300_CHMEDIA_MASK(port->phy_node), init_ctrl);
172 writel(card->init_ctrl_value &
173 ~PC300_CHMEDIA_MASK(port->phy_node), init_ctrl);
179 static int pc300_open(struct net_device *dev)
181 port_t *port = dev_to_port(dev);
183 int result = hdlc_open(dev);
188 pc300_set_iface(port);
194 static int pc300_close(struct net_device *dev)
203 static int pc300_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
205 const size_t size = sizeof(sync_serial_settings);
206 sync_serial_settings new_line;
207 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
209 port_t *port = dev_to_port(dev);
212 if (cmd == SIOCDEVPRIVATE) {
217 if (cmd != SIOCWANDEV)
218 return hdlc_ioctl(dev, ifr, cmd);
220 if (ifr->ifr_settings.type == IF_GET_IFACE) {
221 ifr->ifr_settings.type = port->iface;
222 if (ifr->ifr_settings.size < size) {
223 ifr->ifr_settings.size = size; /* data size wanted */
226 if (copy_to_user(line, &port->settings, size))
232 if (port->card->type == PC300_X21 &&
233 (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL ||
234 ifr->ifr_settings.type == IF_IFACE_X21))
235 new_type = IF_IFACE_X21;
237 else if (port->card->type == PC300_RSV &&
238 (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL ||
239 ifr->ifr_settings.type == IF_IFACE_V35))
240 new_type = IF_IFACE_V35;
242 else if (port->card->type == PC300_RSV &&
243 ifr->ifr_settings.type == IF_IFACE_V24)
244 new_type = IF_IFACE_V24;
247 return hdlc_ioctl(dev, ifr, cmd);
249 if (!capable(CAP_NET_ADMIN))
252 if (copy_from_user(&new_line, line, size))
255 if (new_line.clock_type != CLOCK_EXT &&
256 new_line.clock_type != CLOCK_TXFROMRX &&
257 new_line.clock_type != CLOCK_INT &&
258 new_line.clock_type != CLOCK_TXINT)
259 return -EINVAL; /* No such clock setting */
261 if (new_line.loopback != 0 && new_line.loopback != 1)
264 memcpy(&port->settings, &new_line, size); /* Update settings */
265 port->iface = new_type;
266 pc300_set_iface(port);
272 static void pc300_pci_remove_one(struct pci_dev *pdev)
275 card_t *card = pci_get_drvdata(pdev);
277 for (i = 0; i < 2; i++)
278 if (card->ports[i].card) {
279 struct net_device *dev = port_to_dev(&card->ports[i]);
280 unregister_hdlc_device(dev);
284 free_irq(card->irq, card);
287 iounmap(card->rambase);
289 iounmap(card->scabase);
291 iounmap(card->plxbase);
293 pci_release_regions(pdev);
294 pci_disable_device(pdev);
295 pci_set_drvdata(pdev, NULL);
296 if (card->ports[0].dev)
297 free_netdev(card->ports[0].dev);
298 if (card->ports[1].dev)
299 free_netdev(card->ports[1].dev);
305 static int __devinit pc300_pci_init_one(struct pci_dev *pdev,
306 const struct pci_device_id *ent)
312 u32 ramphys; /* buffer memory base */
313 u32 scaphys; /* SCA memory base */
314 u32 plxphys; /* PLX registers memory base */
316 i = pci_enable_device(pdev);
320 i = pci_request_regions(pdev, "PC300");
322 pci_disable_device(pdev);
326 card = kzalloc(sizeof(card_t), GFP_KERNEL);
328 printk(KERN_ERR "pc300: unable to allocate memory\n");
329 pci_release_regions(pdev);
330 pci_disable_device(pdev);
333 pci_set_drvdata(pdev, card);
335 if (pdev->device == PCI_DEVICE_ID_PC300_TE_1 ||
336 pdev->device == PCI_DEVICE_ID_PC300_TE_2)
337 card->type = PC300_TE; /* not fully supported */
338 else if (card->init_ctrl_value & PC300_CTYPE_MASK)
339 card->type = PC300_X21;
341 card->type = PC300_RSV;
343 if (pdev->device == PCI_DEVICE_ID_PC300_RX_1 ||
344 pdev->device == PCI_DEVICE_ID_PC300_TE_1)
349 for (i = 0; i < card->n_ports; i++)
350 if (!(card->ports[i].dev = alloc_hdlcdev(&card->ports[i]))) {
351 printk(KERN_ERR "pc300: unable to allocate memory\n");
352 pc300_pci_remove_one(pdev);
356 if (pci_resource_len(pdev, 0) != PC300_PLX_SIZE ||
357 pci_resource_len(pdev, 2) != PC300_SCA_SIZE ||
358 pci_resource_len(pdev, 3) < 16384) {
359 printk(KERN_ERR "pc300: invalid card EEPROM parameters\n");
360 pc300_pci_remove_one(pdev);
364 plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK;
365 card->plxbase = ioremap(plxphys, PC300_PLX_SIZE);
367 scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK;
368 card->scabase = ioremap(scaphys, PC300_SCA_SIZE);
370 ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK;
371 card->rambase = pci_ioremap_bar(pdev, 3);
373 if (card->plxbase == NULL ||
374 card->scabase == NULL ||
375 card->rambase == NULL) {
376 printk(KERN_ERR "pc300: ioremap() failed\n");
377 pc300_pci_remove_one(pdev);
380 /* PLX PCI 9050 workaround for local configuration register read bug */
381 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, scaphys);
382 card->init_ctrl_value = readl(&((plx9050 __iomem *)card->scabase)->init_ctrl);
383 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, plxphys);
386 p = &card->plxbase->init_ctrl;
387 writel(card->init_ctrl_value | 0x40000000, p);
388 readl(p); /* Flush the write - do not use sca_flush */
391 writel(card->init_ctrl_value, p);
392 readl(p); /* Flush the write - do not use sca_flush */
395 /* Reload Config. Registers from EEPROM */
396 writel(card->init_ctrl_value | 0x20000000, p);
397 readl(p); /* Flush the write - do not use sca_flush */
400 writel(card->init_ctrl_value, p);
401 readl(p); /* Flush the write - do not use sca_flush */
404 ramsize = sca_detect_ram(card, card->rambase,
405 pci_resource_len(pdev, 3));
407 if (use_crystal_clock)
408 card->init_ctrl_value &= ~PC300_CLKSEL_MASK;
410 card->init_ctrl_value |= PC300_CLKSEL_MASK;
412 writel(card->init_ctrl_value, &card->plxbase->init_ctrl);
413 /* number of TX + RX buffers for one port */
414 i = ramsize / (card->n_ports * (sizeof(pkt_desc) + HDLC_MAX_MRU));
415 card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
416 card->rx_ring_buffers = i - card->tx_ring_buffers;
418 card->buff_offset = card->n_ports * sizeof(pkt_desc) *
419 (card->tx_ring_buffers + card->rx_ring_buffers);
421 printk(KERN_INFO "pc300: PC300/%s, %u KB RAM at 0x%x, IRQ%u, "
422 "using %u TX + %u RX packets rings\n",
423 card->type == PC300_X21 ? "X21" :
424 card->type == PC300_TE ? "TE" : "RSV",
425 ramsize / 1024, ramphys, pdev->irq,
426 card->tx_ring_buffers, card->rx_ring_buffers);
428 if (card->tx_ring_buffers < 1) {
429 printk(KERN_ERR "pc300: RAM test failed\n");
430 pc300_pci_remove_one(pdev);
434 /* Enable interrupts on the PCI bridge, LINTi1 active low */
435 writew(0x0041, &card->plxbase->intr_ctrl_stat);
438 if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, "pc300", card)) {
439 printk(KERN_WARNING "pc300: could not allocate IRQ%d.\n",
441 pc300_pci_remove_one(pdev);
444 card->irq = pdev->irq;
448 // COTE not set - allows better TX DMA settings
449 // sca_out(sca_in(PCR, card) | PCR_COTE, PCR, card);
451 sca_out(0x10, BTCR, card);
453 for (i = 0; i < card->n_ports; i++) {
454 port_t *port = &card->ports[i];
455 struct net_device *dev = port_to_dev(port);
456 hdlc_device *hdlc = dev_to_hdlc(dev);
459 spin_lock_init(&port->lock);
460 dev->irq = card->irq;
461 dev->mem_start = ramphys;
462 dev->mem_end = ramphys + ramsize - 1;
463 dev->tx_queue_len = 50;
464 dev->do_ioctl = pc300_ioctl;
465 dev->open = pc300_open;
466 dev->stop = pc300_close;
467 hdlc->attach = sca_attach;
468 hdlc->xmit = sca_xmit;
469 port->settings.clock_type = CLOCK_EXT;
471 if (card->type == PC300_X21)
472 port->iface = IF_IFACE_X21;
474 port->iface = IF_IFACE_V35;
477 if (register_hdlc_device(dev)) {
478 printk(KERN_ERR "pc300: unable to register hdlc "
481 pc300_pci_remove_one(pdev);
485 printk(KERN_INFO "%s: PC300 node %d\n",
486 dev->name, port->phy_node);
493 static struct pci_device_id pc300_pci_tbl[] __devinitdata = {
494 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_1, PCI_ANY_ID,
495 PCI_ANY_ID, 0, 0, 0 },
496 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_2, PCI_ANY_ID,
497 PCI_ANY_ID, 0, 0, 0 },
498 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_1, PCI_ANY_ID,
499 PCI_ANY_ID, 0, 0, 0 },
500 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_2, PCI_ANY_ID,
501 PCI_ANY_ID, 0, 0, 0 },
506 static struct pci_driver pc300_pci_driver = {
508 .id_table = pc300_pci_tbl,
509 .probe = pc300_pci_init_one,
510 .remove = pc300_pci_remove_one,
514 static int __init pc300_init_module(void)
516 if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) {
517 printk(KERN_ERR "pc300: Invalid PCI clock frequency\n");
520 if (use_crystal_clock != 0 && use_crystal_clock != 1) {
521 printk(KERN_ERR "pc300: Invalid 'use_crystal_clock' value\n");
525 CLOCK_BASE = use_crystal_clock ? 24576000 : pci_clock_freq;
527 return pci_register_driver(&pc300_pci_driver);
532 static void __exit pc300_cleanup_module(void)
534 pci_unregister_driver(&pc300_pci_driver);
537 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
538 MODULE_DESCRIPTION("Cyclades PC300 serial port driver");
539 MODULE_LICENSE("GPL v2");
540 MODULE_DEVICE_TABLE(pci, pc300_pci_tbl);
541 module_param(pci_clock_freq, int, 0444);
542 MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz");
543 module_param(use_crystal_clock, int, 0444);
544 MODULE_PARM_DESC(use_crystal_clock,
545 "Use 24.576 MHz clock instead of PCI clock");
546 module_init(pc300_init_module);
547 module_exit(pc300_cleanup_module);