1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29 #include <linux/usb/r8152.h>
31 /* Information for net-next */
32 #define NETNEXT_VERSION "12"
34 /* Information for net */
35 #define NET_VERSION "12"
37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
42 #define R8152_PHY_ID 32
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RCR1 0xc012
47 #define PLA_RMS 0xc016
48 #define PLA_RXFIFO_CTRL0 0xc0a0
49 #define PLA_RXFIFO_FULL 0xc0a2
50 #define PLA_RXFIFO_CTRL1 0xc0a4
51 #define PLA_RX_FIFO_FULL 0xc0a6
52 #define PLA_RXFIFO_CTRL2 0xc0a8
53 #define PLA_RX_FIFO_EMPTY 0xc0aa
54 #define PLA_DMY_REG0 0xc0b0
55 #define PLA_FMC 0xc0b4
56 #define PLA_CFG_WOL 0xc0b6
57 #define PLA_TEREDO_CFG 0xc0bc
58 #define PLA_TEREDO_WAKE_BASE 0xc0c4
59 #define PLA_MAR 0xcd00
60 #define PLA_BACKUP 0xd000
61 #define PLA_BDC_CR 0xd1a0
62 #define PLA_TEREDO_TIMER 0xd2cc
63 #define PLA_REALWOW_TIMER 0xd2e8
64 #define PLA_UPHY_TIMER 0xd388
65 #define PLA_SUSPEND_FLAG 0xd38a
66 #define PLA_INDICATE_FALG 0xd38c
67 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
68 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
69 #define PLA_EXTRA_STATUS 0xd398
70 #define PLA_GPHY_CTRL 0xd3ae
71 #define PLA_POL_GPIO_CTRL 0xdc6a
72 #define PLA_EFUSE_DATA 0xdd00
73 #define PLA_EFUSE_CMD 0xdd02
74 #define PLA_LEDSEL 0xdd90
75 #define PLA_LED_FEATURE 0xdd92
76 #define PLA_PHYAR 0xde00
77 #define PLA_BOOT_CTRL 0xe004
78 #define PLA_LWAKE_CTRL_REG 0xe007
79 #define PLA_GPHY_INTR_IMR 0xe022
80 #define PLA_EEE_CR 0xe040
81 #define PLA_EEE_TXTWSYS 0xe04c
82 #define PLA_EEE_TXTWSYS_2P5G 0xe058
83 #define PLA_EEEP_CR 0xe080
84 #define PLA_MAC_PWR_CTRL 0xe0c0
85 #define PLA_MAC_PWR_CTRL2 0xe0ca
86 #define PLA_MAC_PWR_CTRL3 0xe0cc
87 #define PLA_MAC_PWR_CTRL4 0xe0ce
88 #define PLA_WDT6_CTRL 0xe428
89 #define PLA_TCR0 0xe610
90 #define PLA_TCR1 0xe612
91 #define PLA_MTPS 0xe615
92 #define PLA_TXFIFO_CTRL 0xe618
93 #define PLA_TXFIFO_FULL 0xe61a
94 #define PLA_RSTTALLY 0xe800
96 #define PLA_CRWECR 0xe81c
97 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
98 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
99 #define PLA_CONFIG5 0xe822
100 #define PLA_PHY_PWR 0xe84c
101 #define PLA_OOB_CTRL 0xe84f
102 #define PLA_CPCR 0xe854
103 #define PLA_MISC_0 0xe858
104 #define PLA_MISC_1 0xe85a
105 #define PLA_OCP_GPHY_BASE 0xe86c
106 #define PLA_TALLYCNT 0xe890
107 #define PLA_SFF_STS_7 0xe8de
108 #define PLA_PHYSTATUS 0xe908
109 #define PLA_CONFIG6 0xe90a /* CONFIG6 */
110 #define PLA_USB_CFG 0xe952
111 #define PLA_BP_BA 0xfc26
112 #define PLA_BP_0 0xfc28
113 #define PLA_BP_1 0xfc2a
114 #define PLA_BP_2 0xfc2c
115 #define PLA_BP_3 0xfc2e
116 #define PLA_BP_4 0xfc30
117 #define PLA_BP_5 0xfc32
118 #define PLA_BP_6 0xfc34
119 #define PLA_BP_7 0xfc36
120 #define PLA_BP_EN 0xfc38
122 #define USB_USB2PHY 0xb41e
123 #define USB_SSPHYLINK1 0xb426
124 #define USB_SSPHYLINK2 0xb428
125 #define USB_L1_CTRL 0xb45e
126 #define USB_U2P3_CTRL 0xb460
127 #define USB_CSR_DUMMY1 0xb464
128 #define USB_CSR_DUMMY2 0xb466
129 #define USB_DEV_STAT 0xb808
130 #define USB_CONNECT_TIMER 0xcbf8
131 #define USB_MSC_TIMER 0xcbfc
132 #define USB_BURST_SIZE 0xcfc0
133 #define USB_FW_FIX_EN0 0xcfca
134 #define USB_FW_FIX_EN1 0xcfcc
135 #define USB_LPM_CONFIG 0xcfd8
136 #define USB_ECM_OPTION 0xcfee
137 #define USB_CSTMR 0xcfef /* RTL8153A */
138 #define USB_MISC_2 0xcfff
139 #define USB_ECM_OP 0xd26b
140 #define USB_GPHY_CTRL 0xd284
141 #define USB_SPEED_OPTION 0xd32a
142 #define USB_FW_CTRL 0xd334 /* RTL8153B */
143 #define USB_FC_TIMER 0xd340
144 #define USB_USB_CTRL 0xd406
145 #define USB_PHY_CTRL 0xd408
146 #define USB_TX_AGG 0xd40a
147 #define USB_RX_BUF_TH 0xd40c
148 #define USB_USB_TIMER 0xd428
149 #define USB_RX_EARLY_TIMEOUT 0xd42c
150 #define USB_RX_EARLY_SIZE 0xd42e
151 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
152 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
153 #define USB_TX_DMA 0xd434
154 #define USB_UPT_RXDMA_OWN 0xd437
155 #define USB_UPHY3_MDCMDIO 0xd480
156 #define USB_TOLERANCE 0xd490
157 #define USB_LPM_CTRL 0xd41a
158 #define USB_BMU_RESET 0xd4b0
159 #define USB_BMU_CONFIG 0xd4b4
160 #define USB_U1U2_TIMER 0xd4da
161 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
162 #define USB_RX_AGGR_NUM 0xd4ee
163 #define USB_UPS_CTRL 0xd800
164 #define USB_POWER_CUT 0xd80a
165 #define USB_MISC_0 0xd81a
166 #define USB_MISC_1 0xd81f
167 #define USB_AFE_CTRL2 0xd824
168 #define USB_UPHY_XTAL 0xd826
169 #define USB_UPS_CFG 0xd842
170 #define USB_UPS_FLAGS 0xd848
171 #define USB_WDT1_CTRL 0xe404
172 #define USB_WDT11_CTRL 0xe43c
173 #define USB_BP_BA PLA_BP_BA
174 #define USB_BP_0 PLA_BP_0
175 #define USB_BP_1 PLA_BP_1
176 #define USB_BP_2 PLA_BP_2
177 #define USB_BP_3 PLA_BP_3
178 #define USB_BP_4 PLA_BP_4
179 #define USB_BP_5 PLA_BP_5
180 #define USB_BP_6 PLA_BP_6
181 #define USB_BP_7 PLA_BP_7
182 #define USB_BP_EN PLA_BP_EN /* RTL8153A */
183 #define USB_BP_8 0xfc38 /* RTL8153B */
184 #define USB_BP_9 0xfc3a
185 #define USB_BP_10 0xfc3c
186 #define USB_BP_11 0xfc3e
187 #define USB_BP_12 0xfc40
188 #define USB_BP_13 0xfc42
189 #define USB_BP_14 0xfc44
190 #define USB_BP_15 0xfc46
191 #define USB_BP2_EN 0xfc48
194 #define OCP_ALDPS_CONFIG 0x2010
195 #define OCP_EEE_CONFIG1 0x2080
196 #define OCP_EEE_CONFIG2 0x2092
197 #define OCP_EEE_CONFIG3 0x2094
198 #define OCP_BASE_MII 0xa400
199 #define OCP_EEE_AR 0xa41a
200 #define OCP_EEE_DATA 0xa41c
201 #define OCP_PHY_STATUS 0xa420
202 #define OCP_NCTL_CFG 0xa42c
203 #define OCP_POWER_CFG 0xa430
204 #define OCP_EEE_CFG 0xa432
205 #define OCP_SRAM_ADDR 0xa436
206 #define OCP_SRAM_DATA 0xa438
207 #define OCP_DOWN_SPEED 0xa442
208 #define OCP_EEE_ABLE 0xa5c4
209 #define OCP_EEE_ADV 0xa5d0
210 #define OCP_EEE_LPABLE 0xa5d2
211 #define OCP_10GBT_CTRL 0xa5d4
212 #define OCP_10GBT_STAT 0xa5d6
213 #define OCP_EEE_ADV2 0xa6d4
214 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
215 #define OCP_PHY_PATCH_STAT 0xb800
216 #define OCP_PHY_PATCH_CMD 0xb820
217 #define OCP_PHY_LOCK 0xb82e
218 #define OCP_ADC_IOFFSET 0xbcfc
219 #define OCP_ADC_CFG 0xbc06
220 #define OCP_SYSCLK_CFG 0xc416
223 #define SRAM_GREEN_CFG 0x8011
224 #define SRAM_LPF_CFG 0x8012
225 #define SRAM_GPHY_FW_VER 0x801e
226 #define SRAM_10M_AMP1 0x8080
227 #define SRAM_10M_AMP2 0x8082
228 #define SRAM_IMPEDANCE 0x8084
229 #define SRAM_PHY_LOCK 0xb82e
232 #define RCR_AAP 0x00000001
233 #define RCR_APM 0x00000002
234 #define RCR_AM 0x00000004
235 #define RCR_AB 0x00000008
236 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
237 #define SLOT_EN BIT(11)
240 #define OUTER_VLAN BIT(7)
241 #define INNER_VLAN BIT(6)
243 /* PLA_RXFIFO_CTRL0 */
244 #define RXFIFO_THR1_NORMAL 0x00080002
245 #define RXFIFO_THR1_OOB 0x01800003
247 /* PLA_RXFIFO_FULL */
248 #define RXFIFO_FULL_MASK 0xfff
250 /* PLA_RXFIFO_CTRL1 */
251 #define RXFIFO_THR2_FULL 0x00000060
252 #define RXFIFO_THR2_HIGH 0x00000038
253 #define RXFIFO_THR2_OOB 0x0000004a
254 #define RXFIFO_THR2_NORMAL 0x00a0
256 /* PLA_RXFIFO_CTRL2 */
257 #define RXFIFO_THR3_FULL 0x00000078
258 #define RXFIFO_THR3_HIGH 0x00000048
259 #define RXFIFO_THR3_OOB 0x0000005a
260 #define RXFIFO_THR3_NORMAL 0x0110
262 /* PLA_TXFIFO_CTRL */
263 #define TXFIFO_THR_NORMAL 0x00400008
264 #define TXFIFO_THR_NORMAL2 0x01000008
267 #define ECM_ALDPS 0x0002
270 #define FMC_FCR_MCU_EN 0x0001
273 #define EEEP_CR_EEEP_TX 0x0002
276 #define WDT6_SET_MODE 0x0010
279 #define TCR0_TX_EMPTY 0x0800
280 #define TCR0_AUTO_FIFO 0x0080
283 #define VERSION_MASK 0x7cf0
284 #define IFG_MASK (BIT(3) | BIT(9) | BIT(8))
285 #define IFG_144NS BIT(9)
286 #define IFG_96NS (BIT(9) | BIT(8))
289 #define MTPS_JUMBO (12 * 1024 / 64)
290 #define MTPS_DEFAULT (6 * 1024 / 64)
293 #define TALLY_RESET 0x0001
301 #define CRWECR_NORAML 0x00
302 #define CRWECR_CONFIG 0xc0
305 #define NOW_IS_OOB 0x80
306 #define TXFIFO_EMPTY 0x20
307 #define RXFIFO_EMPTY 0x10
308 #define LINK_LIST_READY 0x02
309 #define DIS_MCU_CLROOB 0x01
310 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
313 #define RXDY_GATED_EN 0x0008
316 #define RE_INIT_LL 0x8000
317 #define MCU_BORW_EN 0x4000
320 #define FLOW_CTRL_EN BIT(0)
321 #define CPCR_RX_VLAN 0x0040
324 #define MAGIC_EN 0x0001
327 #define TEREDO_SEL 0x8000
328 #define TEREDO_WAKE_MASK 0x7f00
329 #define TEREDO_RS_EVENT_MASK 0x00fe
330 #define OOB_TEREDO_EN 0x0001
333 #define ALDPS_PROXY_MODE 0x0001
336 #define EFUSE_READ_CMD BIT(15)
337 #define EFUSE_DATA_BIT16 BIT(7)
340 #define LINK_ON_WAKE_EN 0x0010
341 #define LINK_OFF_WAKE_EN 0x0008
344 #define LANWAKE_CLR_EN BIT(0)
347 #define EN_XG_LIP BIT(1)
348 #define EN_G_LIP BIT(2)
351 #define BWF_EN 0x0040
352 #define MWF_EN 0x0020
353 #define UWF_EN 0x0010
354 #define LAN_WAKE_EN 0x0002
356 /* PLA_LED_FEATURE */
357 #define LED_MODE_MASK 0x0700
360 #define TX_10M_IDLE_EN 0x0080
361 #define PFM_PWM_SWITCH 0x0040
362 #define TEST_IO_OFF BIT(4)
364 /* PLA_MAC_PWR_CTRL */
365 #define D3_CLK_GATED_EN 0x00004000
366 #define MCU_CLK_RATIO 0x07010f07
367 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
368 #define ALDPS_SPDWN_RATIO 0x0f87
370 /* PLA_MAC_PWR_CTRL2 */
371 #define EEE_SPDWN_RATIO 0x8007
372 #define MAC_CLK_SPDWN_EN BIT(15)
373 #define EEE_SPDWN_RATIO_MASK 0xff
375 /* PLA_MAC_PWR_CTRL3 */
376 #define PLA_MCU_SPDWN_EN BIT(14)
377 #define PKT_AVAIL_SPDWN_EN 0x0100
378 #define SUSPEND_SPDWN_EN 0x0004
379 #define U1U2_SPDWN_EN 0x0002
380 #define L1_SPDWN_EN 0x0001
382 /* PLA_MAC_PWR_CTRL4 */
383 #define PWRSAVE_SPDWN_EN 0x1000
384 #define RXDV_SPDWN_EN 0x0800
385 #define TX10MIDLE_EN 0x0100
386 #define IDLE_SPDWN_EN BIT(6)
387 #define TP100_SPDWN_EN 0x0020
388 #define TP500_SPDWN_EN 0x0010
389 #define TP1000_SPDWN_EN 0x0008
390 #define EEE_SPDWN_EN 0x0001
392 /* PLA_GPHY_INTR_IMR */
393 #define GPHY_STS_MSK 0x0001
394 #define SPEED_DOWN_MSK 0x0002
395 #define SPDWN_RXDV_MSK 0x0004
396 #define SPDWN_LINKCHG_MSK 0x0008
399 #define PHYAR_FLAG 0x80000000
402 #define EEE_RX_EN 0x0001
403 #define EEE_TX_EN 0x0002
406 #define AUTOLOAD_DONE 0x0002
408 /* PLA_LWAKE_CTRL_REG */
409 #define LANWAKE_PIN BIT(7)
411 /* PLA_SUSPEND_FLAG */
412 #define LINK_CHG_EVENT BIT(0)
414 /* PLA_INDICATE_FALG */
415 #define UPCOMING_RUNTIME_D3 BIT(0)
417 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
418 #define DEBUG_OE BIT(0)
419 #define DEBUG_LTSSM 0x0082
421 /* PLA_EXTRA_STATUS */
422 #define CUR_LINK_OK BIT(15)
423 #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
424 #define LINK_CHANGE_FLAG BIT(8)
425 #define POLL_LINK_CHG BIT(0)
428 #define GPHY_FLASH BIT(1)
430 /* PLA_POL_GPIO_CTRL */
431 #define DACK_DET_EN BIT(15)
432 #define POL_GPHY_PATCH BIT(4)
435 #define USB2PHY_SUSPEND 0x0001
436 #define USB2PHY_L1 0x0002
439 #define DELAY_PHY_PWR_CHG BIT(1)
442 #define pwd_dn_scale_mask 0x3ffe
443 #define pwd_dn_scale(x) ((x) << 1)
446 #define DYNAMIC_BURST 0x0001
449 #define EP4_FULL_FC 0x0001
452 #define STAT_SPEED_MASK 0x0006
453 #define STAT_SPEED_HIGH 0x0000
454 #define STAT_SPEED_FULL 0x0002
457 #define FW_FIX_SUSPEND BIT(14)
460 #define FW_IP_RESET_EN BIT(9)
463 #define LPM_U1U2_EN BIT(0)
466 #define TX_AGG_MAX_THRESHOLD 0x03
469 #define RX_THR_SUPPER 0x0c350180
470 #define RX_THR_HIGH 0x7a120180
471 #define RX_THR_SLOW 0xffff0180
472 #define RX_THR_B 0x00010001
475 #define TEST_MODE_DISABLE 0x00000001
476 #define TX_SIZE_ADJUST1 0x00000100
479 #define BMU_RESET_EP_IN 0x01
480 #define BMU_RESET_EP_OUT 0x02
483 #define ACT_ODMA BIT(1)
485 /* USB_UPT_RXDMA_OWN */
486 #define OWN_UPDATE BIT(0)
487 #define OWN_CLEAR BIT(1)
490 #define FC_PATCH_TASK BIT(1)
492 /* USB_RX_AGGR_NUM */
493 #define RX_AGGR_NUM_MASK 0x1ff
496 #define POWER_CUT 0x0100
498 /* USB_PM_CTRL_STATUS */
499 #define RESUME_INDICATE 0x0001
502 #define BYPASS_MAC_RESET BIT(5)
505 #define FORCE_SUPER BIT(0)
508 #define UPS_FORCE_PWR_DOWN BIT(0)
511 #define EN_ALL_SPEED BIT(0)
514 #define GPHY_PATCH_DONE BIT(2)
515 #define BYPASS_FLASH BIT(5)
516 #define BACKUP_RESTRORE BIT(6)
518 /* USB_SPEED_OPTION */
519 #define RG_PWRDN_EN BIT(8)
520 #define ALL_SPEED_OFF BIT(9)
523 #define FLOW_CTRL_PATCH_OPT BIT(1)
524 #define AUTO_SPEEDUP BIT(3)
525 #define FLOW_CTRL_PATCH_2 BIT(8)
528 #define CTRL_TIMER_EN BIT(15)
531 #define CDC_ECM_EN BIT(3)
532 #define RX_AGG_DISABLE 0x0010
533 #define RX_ZERO_EN 0x0080
536 #define U2P3_ENABLE 0x0001
537 #define RX_DETECT8 BIT(3)
540 #define PWR_EN 0x0001
541 #define PHASE2_EN 0x0008
542 #define UPS_EN BIT(4)
543 #define USP_PREWAKE BIT(5)
546 #define PCUT_STATUS 0x0001
548 /* USB_RX_EARLY_TIMEOUT */
549 #define COALESCE_SUPER 85000U
550 #define COALESCE_HIGH 250000U
551 #define COALESCE_SLOW 524280U
554 #define WTD1_EN BIT(0)
557 #define TIMER11_EN 0x0001
560 /* bit 4 ~ 5: fifo empty boundary */
561 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
562 /* bit 2 ~ 3: LMP timer */
563 #define LPM_TIMER_MASK 0x0c
564 #define LPM_TIMER_500MS 0x04 /* 500 ms */
565 #define LPM_TIMER_500US 0x0c /* 500 us */
566 #define ROK_EXIT_LPM 0x02
569 #define SEN_VAL_MASK 0xf800
570 #define SEN_VAL_NORMAL 0xa000
571 #define SEL_RXIDLE 0x0100
574 #define OOBS_POLLING BIT(8)
577 #define SAW_CNT_1MS_MASK 0x0fff
578 #define MID_REVERSE BIT(5) /* RTL8156A */
581 #define UPS_FLAGS_R_TUNE BIT(0)
582 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
583 #define UPS_FLAGS_250M_CKDIV BIT(2)
584 #define UPS_FLAGS_EN_ALDPS BIT(3)
585 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
586 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
587 #define ups_flags_speed(x) ((x) << 16)
588 #define UPS_FLAGS_EN_EEE BIT(20)
589 #define UPS_FLAGS_EN_500M_EEE BIT(21)
590 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
591 #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
592 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
593 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
594 #define UPS_FLAGS_EN_GREEN BIT(26)
595 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
611 /* OCP_ALDPS_CONFIG */
612 #define ENPWRSAVE 0x8000
613 #define ENPDNPS 0x0200
614 #define LINKENA 0x0100
615 #define DIS_SDSAVE 0x0010
618 #define PHY_STAT_MASK 0x0007
619 #define PHY_STAT_EXT_INIT 2
620 #define PHY_STAT_LAN_ON 3
621 #define PHY_STAT_PWRDN 5
624 #define PGA_RETURN_EN BIT(1)
627 #define EEE_CLKDIV_EN 0x8000
628 #define EN_ALDPS 0x0004
629 #define EN_10M_PLLOFF 0x0001
631 /* OCP_EEE_CONFIG1 */
632 #define RG_TXLPI_MSK_HFDUP 0x8000
633 #define RG_MATCLR_EN 0x4000
634 #define EEE_10_CAP 0x2000
635 #define EEE_NWAY_EN 0x1000
636 #define TX_QUIET_EN 0x0200
637 #define RX_QUIET_EN 0x0100
638 #define sd_rise_time_mask 0x0070
639 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
640 #define RG_RXLPI_MSK_HFDUP 0x0008
641 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
643 /* OCP_EEE_CONFIG2 */
644 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
645 #define RG_DACQUIET_EN 0x0400
646 #define RG_LDVQUIET_EN 0x0200
647 #define RG_CKRSEL 0x0020
648 #define RG_EEEPRG_EN 0x0010
650 /* OCP_EEE_CONFIG3 */
651 #define fast_snr_mask 0xff80
652 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
653 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
654 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
657 /* bit[15:14] function */
658 #define FUN_ADDR 0x0000
659 #define FUN_DATA 0x4000
660 /* bit[4:0] device addr */
663 #define CTAP_SHORT_EN 0x0040
664 #define EEE10_EN 0x0010
667 #define EN_EEE_CMODE BIT(14)
668 #define EN_EEE_1000 BIT(13)
669 #define EN_EEE_100 BIT(12)
670 #define EN_10M_CLKDIV BIT(11)
671 #define EN_10M_BGOFF 0x0080
674 #define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */
677 #define TXDIS_STATE 0x01
678 #define ABD_STATE 0x02
680 /* OCP_PHY_PATCH_STAT */
681 #define PATCH_READY BIT(6)
683 /* OCP_PHY_PATCH_CMD */
684 #define PATCH_REQUEST BIT(4)
687 #define PATCH_LOCK BIT(0)
690 #define CKADSEL_L 0x0100
691 #define ADC_EN 0x0080
692 #define EN_EMI_L 0x0040
695 #define sysclk_div_expo(x) (min(x, 5) << 8)
696 #define clk_div_expo(x) (min(x, 5) << 4)
699 #define GREEN_ETH_EN BIT(15)
700 #define R_TUNE_EN BIT(11)
703 #define LPF_AUTO_TUNE 0x8000
706 #define GDAC_IB_UPALL 0x0008
709 #define AMP_DN 0x0200
712 #define RX_DRIVING_MASK 0x6000
715 #define PHY_PATCH_LOCK 0x0001
718 #define AD_MASK 0xfee0
719 #define BND_MASK 0x0004
720 #define BD_MASK 0x0001
722 #define PASS_THRU_MASK 0x1
724 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
726 enum rtl_register_content {
739 #define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
740 #define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
742 #define RTL8152_MAX_TX 4
743 #define RTL8152_MAX_RX 10
748 #define RTL8152_RX_MAX_PENDING 4096
749 #define RTL8152_RXFG_HEADSZ 256
751 #define INTR_LINK 0x0004
753 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
754 #define RTL8153_RMS RTL8153_MAX_PACKET
755 #define RTL8152_TX_TIMEOUT (5 * HZ)
756 #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
757 #define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
758 #define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
773 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
774 #define DEVICE_ID_THINKPAD_USB_C_DONGLE 0x720c
775 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
776 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3 0x3062
778 struct tally_counter {
785 __le32 tx_one_collision;
786 __le32 tx_multi_collision;
796 #define RX_LEN_MASK 0x7fff
799 #define RD_UDP_CS BIT(23)
800 #define RD_TCP_CS BIT(22)
801 #define RD_IPV6_CS BIT(20)
802 #define RD_IPV4_CS BIT(19)
805 #define IPF BIT(23) /* IP checksum fail */
806 #define UDPF BIT(22) /* UDP checksum fail */
807 #define TCPF BIT(21) /* TCP checksum fail */
808 #define RX_VLAN_TAG BIT(16)
817 #define TX_FS BIT(31) /* First segment of a packet */
818 #define TX_LS BIT(30) /* Final segment of a packet */
819 #define GTSENDV4 BIT(28)
820 #define GTSENDV6 BIT(27)
821 #define GTTCPHO_SHIFT 18
822 #define GTTCPHO_MAX 0x7fU
823 #define TX_LEN_MAX 0x3ffffU
826 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
827 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
828 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
829 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
831 #define MSS_MAX 0x7ffU
832 #define TCPHO_SHIFT 17
833 #define TCPHO_MAX 0x7ffU
834 #define TX_VLAN_TAG BIT(16)
840 struct list_head list, info_list;
842 struct r8152 *context;
848 struct list_head list;
850 struct r8152 *context;
859 struct usb_device *udev;
860 struct napi_struct napi;
861 struct usb_interface *intf;
862 struct net_device *netdev;
863 struct urb *intr_urb;
864 struct tx_agg tx_info[RTL8152_MAX_TX];
865 struct list_head rx_info, rx_used;
866 struct list_head rx_done, tx_free;
867 struct sk_buff_head tx_queue, rx_queue;
868 spinlock_t rx_lock, tx_lock;
869 struct delayed_work schedule, hw_phy_work;
870 struct mii_if_info mii;
871 struct mutex control; /* use for hw setting */
872 #ifdef CONFIG_PM_SLEEP
873 struct notifier_block pm_notifier;
875 struct tasklet_struct tx_tl;
878 void (*init)(struct r8152 *tp);
879 int (*enable)(struct r8152 *tp);
880 void (*disable)(struct r8152 *tp);
881 void (*up)(struct r8152 *tp);
882 void (*down)(struct r8152 *tp);
883 void (*unload)(struct r8152 *tp);
884 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
885 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
886 bool (*in_nway)(struct r8152 *tp);
887 void (*hw_phy_cfg)(struct r8152 *tp);
888 void (*autosuspend_en)(struct r8152 *tp, bool enable);
889 void (*change_mtu)(struct r8152 *tp);
902 u32 eee_plloff_100:1;
903 u32 eee_plloff_giga:1;
907 u32 ctap_short_off:1;
910 #define RTL_VER_SIZE 32
914 const struct firmware *fw;
916 char version[RTL_VER_SIZE];
917 int (*pre_fw)(struct r8152 *tp);
918 int (*post_fw)(struct r8152 *tp);
935 u32 fc_pause_on, fc_pause_off;
937 unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out;
939 u32 support_2500full:1;
940 u32 lenovo_macpassthru:1;
941 u32 dell_tb_rx_agg_bug:1;
952 * struct fw_block - block type and total length
953 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
954 * RTL_FW_USB and so on.
955 * @length: total length of the current block.
963 * struct fw_header - header of the firmware file
964 * @checksum: checksum of sha256 which is calculated from the whole file
965 * except the checksum field of the file. That is, calculate sha256
966 * from the version field to the end of the file.
967 * @version: version of this firmware.
968 * @blocks: the first firmware block of the file
972 char version[RTL_VER_SIZE];
973 struct fw_block blocks[];
976 enum rtl8152_fw_flags {
990 enum rtl8152_fw_fixup_cmd {
1002 struct fw_phy_speed_up {
1003 struct fw_block blk_hdr;
1012 struct fw_block blk_hdr;
1013 struct fw_phy_set ver;
1017 struct fw_phy_fixup {
1018 struct fw_block blk_hdr;
1019 struct fw_phy_set setting;
1024 struct fw_phy_union {
1025 struct fw_block blk_hdr;
1028 struct fw_phy_set pre_set[2];
1029 struct fw_phy_set bp[8];
1030 struct fw_phy_set bp_en;
1037 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
1038 * The layout of the firmware block is:
1039 * <struct fw_mac> + <info> + <firmware data>.
1040 * @blk_hdr: firmware descriptor (type, length)
1041 * @fw_offset: offset of the firmware binary data. The start address of
1042 * the data would be the address of struct fw_mac + @fw_offset.
1043 * @fw_reg: the register to load the firmware. Depends on chip.
1044 * @bp_ba_addr: the register to write break point base address. Depends on
1046 * @bp_ba_value: break point base address. Depends on chip.
1047 * @bp_en_addr: the register to write break point enabled mask. Depends
1049 * @bp_en_value: break point enabled mask. Depends on the firmware.
1050 * @bp_start: the start register of break points. Depends on chip.
1051 * @bp_num: the break point number which needs to be set for this firmware.
1052 * Depends on the firmware.
1053 * @bp: break points. Depends on firmware.
1054 * @reserved: reserved space (unused)
1055 * @fw_ver_reg: the register to store the fw version.
1056 * @fw_ver_data: the firmware version of the current type.
1057 * @info: additional information for debugging, and is followed by the
1058 * binary data of firmware.
1061 struct fw_block blk_hdr;
1070 __le16 bp[16]; /* any value determined by firmware */
1078 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
1079 * This is used to set patch key when loading the firmware of PHY.
1080 * @blk_hdr: firmware descriptor (type, length)
1081 * @key_reg: the register to write the patch key.
1082 * @key_data: patch key.
1083 * @reserved: reserved space (unused)
1085 struct fw_phy_patch_key {
1086 struct fw_block blk_hdr;
1093 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
1094 * The layout of the firmware block is:
1095 * <struct fw_phy_nc> + <info> + <firmware data>.
1096 * @blk_hdr: firmware descriptor (type, length)
1097 * @fw_offset: offset of the firmware binary data. The start address of
1098 * the data would be the address of struct fw_phy_nc + @fw_offset.
1099 * @fw_reg: the register to load the firmware. Depends on chip.
1100 * @ba_reg: the register to write the base address. Depends on chip.
1101 * @ba_data: base address. Depends on chip.
1102 * @patch_en_addr: the register of enabling patch mode. Depends on chip.
1103 * @patch_en_value: patch mode enabled mask. Depends on the firmware.
1104 * @mode_reg: the regitster of switching the mode.
1105 * @mode_pre: the mode needing to be set before loading the firmware.
1106 * @mode_post: the mode to be set when finishing to load the firmware.
1107 * @reserved: reserved space (unused)
1108 * @bp_start: the start register of break points. Depends on chip.
1109 * @bp_num: the break point number which needs to be set for this firmware.
1110 * Depends on the firmware.
1111 * @bp: break points. Depends on firmware.
1112 * @info: additional information for debugging, and is followed by the
1113 * binary data of firmware.
1116 struct fw_block blk_hdr;
1121 __le16 patch_en_addr;
1122 __le16 patch_en_value;
1141 RTL_FW_PHY_UNION_NC,
1142 RTL_FW_PHY_UNION_NC1,
1143 RTL_FW_PHY_UNION_NC2,
1144 RTL_FW_PHY_UNION_UC2,
1145 RTL_FW_PHY_UNION_UC,
1146 RTL_FW_PHY_UNION_MISC,
1147 RTL_FW_PHY_SPEED_UP,
1152 RTL_VER_UNKNOWN = 0,
1175 TX_CSUM_SUCCESS = 0,
1180 #define RTL_ADVERTISED_10_HALF BIT(0)
1181 #define RTL_ADVERTISED_10_FULL BIT(1)
1182 #define RTL_ADVERTISED_100_HALF BIT(2)
1183 #define RTL_ADVERTISED_100_FULL BIT(3)
1184 #define RTL_ADVERTISED_1000_HALF BIT(4)
1185 #define RTL_ADVERTISED_1000_FULL BIT(5)
1186 #define RTL_ADVERTISED_2500_FULL BIT(6)
1188 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1189 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1191 static const int multicast_filter_limit = 32;
1192 static unsigned int agg_buf_sz = 16384;
1194 #define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))
1197 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1202 tmp = kmalloc(size, GFP_KERNEL);
1206 ret = usb_control_msg(tp->udev, tp->pipe_ctrl_in,
1207 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1208 value, index, tmp, size, 500);
1210 memset(data, 0xff, size);
1212 memcpy(data, tmp, size);
1220 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1225 tmp = kmemdup(data, size, GFP_KERNEL);
1229 ret = usb_control_msg(tp->udev, tp->pipe_ctrl_out,
1230 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1231 value, index, tmp, size, 500);
1238 static void rtl_set_unplug(struct r8152 *tp)
1240 if (tp->udev->state == USB_STATE_NOTATTACHED) {
1241 set_bit(RTL8152_UNPLUG, &tp->flags);
1242 smp_mb__after_atomic();
1246 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1247 void *data, u16 type)
1252 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1255 /* both size and indix must be 4 bytes align */
1256 if ((size & 3) || !size || (index & 3) || !data)
1259 if ((u32)index + (u32)size > 0xffff)
1264 ret = get_registers(tp, index, type, limit, data);
1272 ret = get_registers(tp, index, type, size, data);
1289 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1290 u16 size, void *data, u16 type)
1293 u16 byteen_start, byteen_end, byen;
1296 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1299 /* both size and indix must be 4 bytes align */
1300 if ((size & 3) || !size || (index & 3) || !data)
1303 if ((u32)index + (u32)size > 0xffff)
1306 byteen_start = byteen & BYTE_EN_START_MASK;
1307 byteen_end = byteen & BYTE_EN_END_MASK;
1309 byen = byteen_start | (byteen_start << 4);
1310 ret = set_registers(tp, index, type | byen, 4, data);
1323 ret = set_registers(tp, index,
1324 type | BYTE_EN_DWORD,
1333 ret = set_registers(tp, index,
1334 type | BYTE_EN_DWORD,
1346 byen = byteen_end | (byteen_end >> 4);
1347 ret = set_registers(tp, index, type | byen, 4, data);
1360 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1362 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1366 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1368 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1372 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1374 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1377 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1381 generic_ocp_read(tp, index, sizeof(data), &data, type);
1383 return __le32_to_cpu(data);
1386 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1388 __le32 tmp = __cpu_to_le32(data);
1390 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1393 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1397 u16 byen = BYTE_EN_WORD;
1398 u8 shift = index & 2;
1403 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1405 data = __le32_to_cpu(tmp);
1406 data >>= (shift * 8);
1412 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1416 u16 byen = BYTE_EN_WORD;
1417 u8 shift = index & 2;
1423 mask <<= (shift * 8);
1424 data <<= (shift * 8);
1428 tmp = __cpu_to_le32(data);
1430 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1433 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1437 u8 shift = index & 3;
1441 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1443 data = __le32_to_cpu(tmp);
1444 data >>= (shift * 8);
1450 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1454 u16 byen = BYTE_EN_BYTE;
1455 u8 shift = index & 3;
1461 mask <<= (shift * 8);
1462 data <<= (shift * 8);
1466 tmp = __cpu_to_le32(data);
1468 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1471 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1473 u16 ocp_base, ocp_index;
1475 ocp_base = addr & 0xf000;
1476 if (ocp_base != tp->ocp_base) {
1477 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1478 tp->ocp_base = ocp_base;
1481 ocp_index = (addr & 0x0fff) | 0xb000;
1482 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1485 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1487 u16 ocp_base, ocp_index;
1489 ocp_base = addr & 0xf000;
1490 if (ocp_base != tp->ocp_base) {
1491 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1492 tp->ocp_base = ocp_base;
1495 ocp_index = (addr & 0x0fff) | 0xb000;
1496 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1499 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1501 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1504 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1506 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1509 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1511 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1512 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1515 static u16 sram_read(struct r8152 *tp, u16 addr)
1517 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1518 return ocp_reg_read(tp, OCP_SRAM_DATA);
1521 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1523 struct r8152 *tp = netdev_priv(netdev);
1526 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1529 if (phy_id != R8152_PHY_ID)
1532 ret = r8152_mdio_read(tp, reg);
1538 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1540 struct r8152 *tp = netdev_priv(netdev);
1542 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1545 if (phy_id != R8152_PHY_ID)
1548 r8152_mdio_write(tp, reg, val);
1552 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1555 rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1558 static int __rtl8152_set_mac_address(struct net_device *netdev, void *p,
1561 struct r8152 *tp = netdev_priv(netdev);
1562 struct sockaddr *addr = p;
1563 int ret = -EADDRNOTAVAIL;
1565 if (!is_valid_ether_addr(addr->sa_data))
1569 ret = usb_autopm_get_interface(tp->intf);
1574 mutex_lock(&tp->control);
1576 eth_hw_addr_set(netdev, addr->sa_data);
1578 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1579 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1580 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1582 mutex_unlock(&tp->control);
1585 usb_autopm_put_interface(tp->intf);
1590 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1592 return __rtl8152_set_mac_address(netdev, p, false);
1595 /* Devices containing proper chips can support a persistent
1596 * host system provided MAC address.
1597 * Examples of this are Dell TB15 and Dell WD15 docks
1599 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1602 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1603 union acpi_object *obj;
1606 unsigned char buf[6];
1608 acpi_object_type mac_obj_type;
1611 if (tp->lenovo_macpassthru) {
1612 mac_obj_name = "\\MACA";
1613 mac_obj_type = ACPI_TYPE_STRING;
1616 /* test for -AD variant of RTL8153 */
1617 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1618 if ((ocp_data & AD_MASK) == 0x1000) {
1619 /* test for MAC address pass-through bit */
1620 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1621 if ((ocp_data & PASS_THRU_MASK) != 1) {
1622 netif_dbg(tp, probe, tp->netdev,
1623 "No efuse for RTL8153-AD MAC pass through\n");
1627 /* test for RTL8153-BND and RTL8153-BD */
1628 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1629 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1630 netif_dbg(tp, probe, tp->netdev,
1631 "Invalid variant for MAC pass through\n");
1636 mac_obj_name = "\\_SB.AMAC";
1637 mac_obj_type = ACPI_TYPE_BUFFER;
1641 /* returns _AUXMAC_#AABBCCDDEEFF# */
1642 status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1643 obj = (union acpi_object *)buffer.pointer;
1644 if (!ACPI_SUCCESS(status))
1646 if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1647 netif_warn(tp, probe, tp->netdev,
1648 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1649 obj->type, obj->string.length);
1653 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1654 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1655 netif_warn(tp, probe, tp->netdev,
1656 "Invalid header when reading pass-thru MAC addr\n");
1659 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1660 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1661 netif_warn(tp, probe, tp->netdev,
1662 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1667 memcpy(sa->sa_data, buf, 6);
1668 netif_info(tp, probe, tp->netdev,
1669 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1676 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1678 struct net_device *dev = tp->netdev;
1681 sa->sa_family = dev->type;
1683 ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1685 if (tp->version == RTL_VER_01) {
1686 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1688 /* if device doesn't support MAC pass through this will
1689 * be expected to be non-zero
1691 ret = vendor_mac_passthru_addr_read(tp, sa);
1693 ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1699 netif_err(tp, probe, dev, "Get ether addr fail\n");
1700 } else if (!is_valid_ether_addr(sa->sa_data)) {
1701 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1703 eth_hw_addr_random(dev);
1704 ether_addr_copy(sa->sa_data, dev->dev_addr);
1705 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1713 static int set_ethernet_addr(struct r8152 *tp, bool in_resume)
1715 struct net_device *dev = tp->netdev;
1719 ret = determine_ethernet_addr(tp, &sa);
1723 if (tp->version == RTL_VER_01)
1724 eth_hw_addr_set(dev, sa.sa_data);
1726 ret = __rtl8152_set_mac_address(dev, &sa, in_resume);
1731 static void read_bulk_callback(struct urb *urb)
1733 struct net_device *netdev;
1734 int status = urb->status;
1737 unsigned long flags;
1747 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1750 if (!test_bit(WORK_ENABLE, &tp->flags))
1753 netdev = tp->netdev;
1755 /* When link down, the driver would cancel all bulks. */
1756 /* This avoid the re-submitting bulk */
1757 if (!netif_carrier_ok(netdev))
1760 usb_mark_last_busy(tp->udev);
1764 if (urb->actual_length < ETH_ZLEN)
1767 spin_lock_irqsave(&tp->rx_lock, flags);
1768 list_add_tail(&agg->list, &tp->rx_done);
1769 spin_unlock_irqrestore(&tp->rx_lock, flags);
1770 napi_schedule(&tp->napi);
1774 netif_device_detach(tp->netdev);
1777 urb->actual_length = 0;
1778 spin_lock_irqsave(&tp->rx_lock, flags);
1779 list_add_tail(&agg->list, &tp->rx_done);
1780 spin_unlock_irqrestore(&tp->rx_lock, flags);
1781 set_bit(RX_EPROTO, &tp->flags);
1782 schedule_delayed_work(&tp->schedule, 1);
1785 return; /* the urb is in unlink state */
1787 if (net_ratelimit())
1788 netdev_warn(netdev, "maybe reset is needed?\n");
1791 if (net_ratelimit())
1792 netdev_warn(netdev, "Rx status %d\n", status);
1796 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1799 static void write_bulk_callback(struct urb *urb)
1801 struct net_device_stats *stats;
1802 struct net_device *netdev;
1805 unsigned long flags;
1806 int status = urb->status;
1816 netdev = tp->netdev;
1817 stats = &netdev->stats;
1819 if (net_ratelimit())
1820 netdev_warn(netdev, "Tx status %d\n", status);
1821 stats->tx_errors += agg->skb_num;
1823 stats->tx_packets += agg->skb_num;
1824 stats->tx_bytes += agg->skb_len;
1827 spin_lock_irqsave(&tp->tx_lock, flags);
1828 list_add_tail(&agg->list, &tp->tx_free);
1829 spin_unlock_irqrestore(&tp->tx_lock, flags);
1831 usb_autopm_put_interface_async(tp->intf);
1833 if (!netif_carrier_ok(netdev))
1836 if (!test_bit(WORK_ENABLE, &tp->flags))
1839 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1842 if (!skb_queue_empty(&tp->tx_queue))
1843 tasklet_schedule(&tp->tx_tl);
1846 static void intr_callback(struct urb *urb)
1850 int status = urb->status;
1857 if (!test_bit(WORK_ENABLE, &tp->flags))
1860 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1864 case 0: /* success */
1866 case -ECONNRESET: /* unlink */
1868 netif_device_detach(tp->netdev);
1872 netif_info(tp, intr, tp->netdev,
1873 "Stop submitting intr, status %d\n", status);
1876 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1878 /* -EPIPE: should clear the halt */
1880 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1884 d = urb->transfer_buffer;
1885 if (INTR_LINK & __le16_to_cpu(d[0])) {
1886 if (!netif_carrier_ok(tp->netdev)) {
1887 set_bit(RTL8152_LINK_CHG, &tp->flags);
1888 schedule_delayed_work(&tp->schedule, 0);
1891 if (netif_carrier_ok(tp->netdev)) {
1892 netif_stop_queue(tp->netdev);
1893 set_bit(RTL8152_LINK_CHG, &tp->flags);
1894 schedule_delayed_work(&tp->schedule, 0);
1899 res = usb_submit_urb(urb, GFP_ATOMIC);
1900 if (res == -ENODEV) {
1902 netif_device_detach(tp->netdev);
1904 netif_err(tp, intr, tp->netdev,
1905 "can't resubmit intr, status %d\n", res);
1909 static inline void *rx_agg_align(void *data)
1911 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1914 static inline void *tx_agg_align(void *data)
1916 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1919 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1921 list_del(&agg->info_list);
1923 usb_free_urb(agg->urb);
1924 put_page(agg->page);
1927 atomic_dec(&tp->rx_count);
1930 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1932 struct net_device *netdev = tp->netdev;
1933 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1934 unsigned int order = get_order(tp->rx_buf_sz);
1935 struct rx_agg *rx_agg;
1936 unsigned long flags;
1938 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1942 rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1946 rx_agg->buffer = page_address(rx_agg->page);
1948 rx_agg->urb = usb_alloc_urb(0, mflags);
1952 rx_agg->context = tp;
1954 INIT_LIST_HEAD(&rx_agg->list);
1955 INIT_LIST_HEAD(&rx_agg->info_list);
1956 spin_lock_irqsave(&tp->rx_lock, flags);
1957 list_add_tail(&rx_agg->info_list, &tp->rx_info);
1958 spin_unlock_irqrestore(&tp->rx_lock, flags);
1960 atomic_inc(&tp->rx_count);
1965 __free_pages(rx_agg->page, order);
1971 static void free_all_mem(struct r8152 *tp)
1973 struct rx_agg *agg, *agg_next;
1974 unsigned long flags;
1977 spin_lock_irqsave(&tp->rx_lock, flags);
1979 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1980 free_rx_agg(tp, agg);
1982 spin_unlock_irqrestore(&tp->rx_lock, flags);
1984 WARN_ON(atomic_read(&tp->rx_count));
1986 for (i = 0; i < RTL8152_MAX_TX; i++) {
1987 usb_free_urb(tp->tx_info[i].urb);
1988 tp->tx_info[i].urb = NULL;
1990 kfree(tp->tx_info[i].buffer);
1991 tp->tx_info[i].buffer = NULL;
1992 tp->tx_info[i].head = NULL;
1995 usb_free_urb(tp->intr_urb);
1996 tp->intr_urb = NULL;
1998 kfree(tp->intr_buff);
1999 tp->intr_buff = NULL;
2002 static int alloc_all_mem(struct r8152 *tp)
2004 struct net_device *netdev = tp->netdev;
2005 struct usb_interface *intf = tp->intf;
2006 struct usb_host_interface *alt = intf->cur_altsetting;
2007 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
2010 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
2012 spin_lock_init(&tp->rx_lock);
2013 spin_lock_init(&tp->tx_lock);
2014 INIT_LIST_HEAD(&tp->rx_info);
2015 INIT_LIST_HEAD(&tp->tx_free);
2016 INIT_LIST_HEAD(&tp->rx_done);
2017 skb_queue_head_init(&tp->tx_queue);
2018 skb_queue_head_init(&tp->rx_queue);
2019 atomic_set(&tp->rx_count, 0);
2021 for (i = 0; i < RTL8152_MAX_RX; i++) {
2022 if (!alloc_rx_agg(tp, GFP_KERNEL))
2026 for (i = 0; i < RTL8152_MAX_TX; i++) {
2030 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
2034 if (buf != tx_agg_align(buf)) {
2036 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
2042 urb = usb_alloc_urb(0, GFP_KERNEL);
2048 INIT_LIST_HEAD(&tp->tx_info[i].list);
2049 tp->tx_info[i].context = tp;
2050 tp->tx_info[i].urb = urb;
2051 tp->tx_info[i].buffer = buf;
2052 tp->tx_info[i].head = tx_agg_align(buf);
2054 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
2057 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
2061 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
2065 tp->intr_interval = (int)ep_intr->desc.bInterval;
2066 usb_fill_int_urb(tp->intr_urb, tp->udev, tp->pipe_intr,
2067 tp->intr_buff, INTBUFSIZE, intr_callback,
2068 tp, tp->intr_interval);
2077 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
2079 struct tx_agg *agg = NULL;
2080 unsigned long flags;
2082 if (list_empty(&tp->tx_free))
2085 spin_lock_irqsave(&tp->tx_lock, flags);
2086 if (!list_empty(&tp->tx_free)) {
2087 struct list_head *cursor;
2089 cursor = tp->tx_free.next;
2090 list_del_init(cursor);
2091 agg = list_entry(cursor, struct tx_agg, list);
2093 spin_unlock_irqrestore(&tp->tx_lock, flags);
2098 /* r8152_csum_workaround()
2099 * The hw limits the value of the transport offset. When the offset is out of
2100 * range, calculate the checksum by sw.
2102 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
2103 struct sk_buff_head *list)
2105 if (skb_shinfo(skb)->gso_size) {
2106 netdev_features_t features = tp->netdev->features;
2107 struct sk_buff *segs, *seg, *next;
2108 struct sk_buff_head seg_list;
2110 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
2111 segs = skb_gso_segment(skb, features);
2112 if (IS_ERR(segs) || !segs)
2115 __skb_queue_head_init(&seg_list);
2117 skb_list_walk_safe(segs, seg, next) {
2118 skb_mark_not_on_list(seg);
2119 __skb_queue_tail(&seg_list, seg);
2122 skb_queue_splice(&seg_list, list);
2124 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2125 if (skb_checksum_help(skb) < 0)
2128 __skb_queue_head(list, skb);
2130 struct net_device_stats *stats;
2133 stats = &tp->netdev->stats;
2134 stats->tx_dropped++;
2139 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
2141 if (skb_vlan_tag_present(skb)) {
2144 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
2145 desc->opts2 |= cpu_to_le32(opts2);
2149 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
2151 u32 opts2 = le32_to_cpu(desc->opts2);
2153 if (opts2 & RX_VLAN_TAG)
2154 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2155 swab16(opts2 & 0xffff));
2158 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
2159 struct sk_buff *skb, u32 len)
2161 u32 mss = skb_shinfo(skb)->gso_size;
2162 u32 opts1, opts2 = 0;
2163 int ret = TX_CSUM_SUCCESS;
2165 WARN_ON_ONCE(len > TX_LEN_MAX);
2167 opts1 = len | TX_FS | TX_LS;
2170 u32 transport_offset = (u32)skb_transport_offset(skb);
2172 if (transport_offset > GTTCPHO_MAX) {
2173 netif_warn(tp, tx_err, tp->netdev,
2174 "Invalid transport offset 0x%x for TSO\n",
2180 switch (vlan_get_protocol(skb)) {
2181 case htons(ETH_P_IP):
2185 case htons(ETH_P_IPV6):
2186 if (skb_cow_head(skb, 0)) {
2190 tcp_v6_gso_csum_prep(skb);
2199 opts1 |= transport_offset << GTTCPHO_SHIFT;
2200 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2201 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2202 u32 transport_offset = (u32)skb_transport_offset(skb);
2205 if (transport_offset > TCPHO_MAX) {
2206 netif_warn(tp, tx_err, tp->netdev,
2207 "Invalid transport offset 0x%x\n",
2213 switch (vlan_get_protocol(skb)) {
2214 case htons(ETH_P_IP):
2216 ip_protocol = ip_hdr(skb)->protocol;
2219 case htons(ETH_P_IPV6):
2221 ip_protocol = ipv6_hdr(skb)->nexthdr;
2225 ip_protocol = IPPROTO_RAW;
2229 if (ip_protocol == IPPROTO_TCP)
2231 else if (ip_protocol == IPPROTO_UDP)
2236 opts2 |= transport_offset << TCPHO_SHIFT;
2239 desc->opts2 = cpu_to_le32(opts2);
2240 desc->opts1 = cpu_to_le32(opts1);
2246 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2248 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2252 __skb_queue_head_init(&skb_head);
2253 spin_lock(&tx_queue->lock);
2254 skb_queue_splice_init(tx_queue, &skb_head);
2255 spin_unlock(&tx_queue->lock);
2257 tx_data = agg->head;
2260 remain = agg_buf_sz;
2262 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2263 struct tx_desc *tx_desc;
2264 struct sk_buff *skb;
2267 skb = __skb_dequeue(&skb_head);
2271 len = skb->len + sizeof(*tx_desc);
2274 __skb_queue_head(&skb_head, skb);
2278 tx_data = tx_agg_align(tx_data);
2279 tx_desc = (struct tx_desc *)tx_data;
2281 if (r8152_tx_csum(tp, tx_desc, skb, skb->len)) {
2282 r8152_csum_workaround(tp, skb, &skb_head);
2286 rtl_tx_vlan_tag(tx_desc, skb);
2288 tx_data += sizeof(*tx_desc);
2291 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2292 struct net_device_stats *stats = &tp->netdev->stats;
2294 stats->tx_dropped++;
2295 dev_kfree_skb_any(skb);
2296 tx_data -= sizeof(*tx_desc);
2301 agg->skb_len += len;
2302 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2304 dev_kfree_skb_any(skb);
2306 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2308 if (tp->dell_tb_rx_agg_bug)
2312 if (!skb_queue_empty(&skb_head)) {
2313 spin_lock(&tx_queue->lock);
2314 skb_queue_splice(&skb_head, tx_queue);
2315 spin_unlock(&tx_queue->lock);
2318 netif_tx_lock(tp->netdev);
2320 if (netif_queue_stopped(tp->netdev) &&
2321 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2322 netif_wake_queue(tp->netdev);
2324 netif_tx_unlock(tp->netdev);
2326 ret = usb_autopm_get_interface_async(tp->intf);
2330 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_out,
2331 agg->head, (int)(tx_data - (u8 *)agg->head),
2332 (usb_complete_t)write_bulk_callback, agg);
2334 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2336 usb_autopm_put_interface_async(tp->intf);
2342 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2344 u8 checksum = CHECKSUM_NONE;
2347 if (!(tp->netdev->features & NETIF_F_RXCSUM))
2350 opts2 = le32_to_cpu(rx_desc->opts2);
2351 opts3 = le32_to_cpu(rx_desc->opts3);
2353 if (opts2 & RD_IPV4_CS) {
2355 checksum = CHECKSUM_NONE;
2356 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2357 checksum = CHECKSUM_UNNECESSARY;
2358 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2359 checksum = CHECKSUM_UNNECESSARY;
2360 } else if (opts2 & RD_IPV6_CS) {
2361 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2362 checksum = CHECKSUM_UNNECESSARY;
2363 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2364 checksum = CHECKSUM_UNNECESSARY;
2371 static inline bool rx_count_exceed(struct r8152 *tp)
2373 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2376 static inline int agg_offset(struct rx_agg *agg, void *addr)
2378 return (int)(addr - agg->buffer);
2381 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2383 struct rx_agg *agg, *agg_next, *agg_free = NULL;
2384 unsigned long flags;
2386 spin_lock_irqsave(&tp->rx_lock, flags);
2388 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2389 if (page_count(agg->page) == 1) {
2391 list_del_init(&agg->list);
2395 if (rx_count_exceed(tp)) {
2396 list_del_init(&agg->list);
2397 free_rx_agg(tp, agg);
2403 spin_unlock_irqrestore(&tp->rx_lock, flags);
2405 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2406 agg_free = alloc_rx_agg(tp, mflags);
2411 static int rx_bottom(struct r8152 *tp, int budget)
2413 unsigned long flags;
2414 struct list_head *cursor, *next, rx_queue;
2415 int ret = 0, work_done = 0;
2416 struct napi_struct *napi = &tp->napi;
2418 if (!skb_queue_empty(&tp->rx_queue)) {
2419 while (work_done < budget) {
2420 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2421 struct net_device *netdev = tp->netdev;
2422 struct net_device_stats *stats = &netdev->stats;
2423 unsigned int pkt_len;
2429 napi_gro_receive(napi, skb);
2431 stats->rx_packets++;
2432 stats->rx_bytes += pkt_len;
2436 if (list_empty(&tp->rx_done))
2439 clear_bit(RX_EPROTO, &tp->flags);
2440 INIT_LIST_HEAD(&rx_queue);
2441 spin_lock_irqsave(&tp->rx_lock, flags);
2442 list_splice_init(&tp->rx_done, &rx_queue);
2443 spin_unlock_irqrestore(&tp->rx_lock, flags);
2445 list_for_each_safe(cursor, next, &rx_queue) {
2446 struct rx_desc *rx_desc;
2447 struct rx_agg *agg, *agg_free;
2452 list_del_init(cursor);
2454 agg = list_entry(cursor, struct rx_agg, list);
2456 if (urb->status != 0 || urb->actual_length < ETH_ZLEN)
2459 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2461 rx_desc = agg->buffer;
2462 rx_data = agg->buffer;
2463 len_used += sizeof(struct rx_desc);
2465 while (urb->actual_length > len_used) {
2466 struct net_device *netdev = tp->netdev;
2467 struct net_device_stats *stats = &netdev->stats;
2468 unsigned int pkt_len, rx_frag_head_sz;
2469 struct sk_buff *skb;
2471 /* limit the skb numbers for rx_queue */
2472 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2475 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2476 if (pkt_len < ETH_ZLEN)
2479 len_used += pkt_len;
2480 if (urb->actual_length < len_used)
2483 pkt_len -= ETH_FCS_LEN;
2484 rx_data += sizeof(struct rx_desc);
2486 if (!agg_free || tp->rx_copybreak > pkt_len)
2487 rx_frag_head_sz = pkt_len;
2489 rx_frag_head_sz = tp->rx_copybreak;
2491 skb = napi_alloc_skb(napi, rx_frag_head_sz);
2493 stats->rx_dropped++;
2497 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2498 memcpy(skb->data, rx_data, rx_frag_head_sz);
2499 skb_put(skb, rx_frag_head_sz);
2500 pkt_len -= rx_frag_head_sz;
2501 rx_data += rx_frag_head_sz;
2503 skb_add_rx_frag(skb, 0, agg->page,
2504 agg_offset(agg, rx_data),
2506 SKB_DATA_ALIGN(pkt_len));
2507 get_page(agg->page);
2510 skb->protocol = eth_type_trans(skb, netdev);
2511 rtl_rx_vlan_tag(rx_desc, skb);
2512 if (work_done < budget) {
2514 stats->rx_packets++;
2515 stats->rx_bytes += skb->len;
2516 napi_gro_receive(napi, skb);
2518 __skb_queue_tail(&tp->rx_queue, skb);
2522 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2523 rx_desc = (struct rx_desc *)rx_data;
2524 len_used = agg_offset(agg, rx_data);
2525 len_used += sizeof(struct rx_desc);
2528 WARN_ON(!agg_free && page_count(agg->page) > 1);
2531 spin_lock_irqsave(&tp->rx_lock, flags);
2532 if (page_count(agg->page) == 1) {
2533 list_add(&agg_free->list, &tp->rx_used);
2535 list_add_tail(&agg->list, &tp->rx_used);
2539 spin_unlock_irqrestore(&tp->rx_lock, flags);
2544 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2546 urb->actual_length = 0;
2547 list_add_tail(&agg->list, next);
2551 if (!list_empty(&rx_queue)) {
2552 spin_lock_irqsave(&tp->rx_lock, flags);
2553 list_splice_tail(&rx_queue, &tp->rx_done);
2554 spin_unlock_irqrestore(&tp->rx_lock, flags);
2561 static void tx_bottom(struct r8152 *tp)
2566 struct net_device *netdev = tp->netdev;
2569 if (skb_queue_empty(&tp->tx_queue))
2572 agg = r8152_get_tx_agg(tp);
2576 res = r8152_tx_agg_fill(tp, agg);
2580 if (res == -ENODEV) {
2582 netif_device_detach(netdev);
2584 struct net_device_stats *stats = &netdev->stats;
2585 unsigned long flags;
2587 netif_warn(tp, tx_err, netdev,
2588 "failed tx_urb %d\n", res);
2589 stats->tx_dropped += agg->skb_num;
2591 spin_lock_irqsave(&tp->tx_lock, flags);
2592 list_add_tail(&agg->list, &tp->tx_free);
2593 spin_unlock_irqrestore(&tp->tx_lock, flags);
2598 static void bottom_half(struct tasklet_struct *t)
2600 struct r8152 *tp = from_tasklet(tp, t, tx_tl);
2602 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2605 if (!test_bit(WORK_ENABLE, &tp->flags))
2608 /* When link down, the driver would cancel all bulks. */
2609 /* This avoid the re-submitting bulk */
2610 if (!netif_carrier_ok(tp->netdev))
2613 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2618 static int r8152_poll(struct napi_struct *napi, int budget)
2620 struct r8152 *tp = container_of(napi, struct r8152, napi);
2623 work_done = rx_bottom(tp, budget);
2625 if (work_done < budget) {
2626 if (!napi_complete_done(napi, work_done))
2628 if (!list_empty(&tp->rx_done))
2629 napi_schedule(napi);
2637 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2641 /* The rx would be stopped, so skip submitting */
2642 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2643 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2646 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_in,
2647 agg->buffer, tp->rx_buf_sz,
2648 (usb_complete_t)read_bulk_callback, agg);
2650 ret = usb_submit_urb(agg->urb, mem_flags);
2651 if (ret == -ENODEV) {
2653 netif_device_detach(tp->netdev);
2655 struct urb *urb = agg->urb;
2656 unsigned long flags;
2658 urb->actual_length = 0;
2659 spin_lock_irqsave(&tp->rx_lock, flags);
2660 list_add_tail(&agg->list, &tp->rx_done);
2661 spin_unlock_irqrestore(&tp->rx_lock, flags);
2663 netif_err(tp, rx_err, tp->netdev,
2664 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2666 napi_schedule(&tp->napi);
2672 static void rtl_drop_queued_tx(struct r8152 *tp)
2674 struct net_device_stats *stats = &tp->netdev->stats;
2675 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2676 struct sk_buff *skb;
2678 if (skb_queue_empty(tx_queue))
2681 __skb_queue_head_init(&skb_head);
2682 spin_lock_bh(&tx_queue->lock);
2683 skb_queue_splice_init(tx_queue, &skb_head);
2684 spin_unlock_bh(&tx_queue->lock);
2686 while ((skb = __skb_dequeue(&skb_head))) {
2688 stats->tx_dropped++;
2692 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2694 struct r8152 *tp = netdev_priv(netdev);
2696 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2698 usb_queue_reset_device(tp->intf);
2701 static void rtl8152_set_rx_mode(struct net_device *netdev)
2703 struct r8152 *tp = netdev_priv(netdev);
2705 if (netif_carrier_ok(netdev)) {
2706 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2707 schedule_delayed_work(&tp->schedule, 0);
2711 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2713 struct r8152 *tp = netdev_priv(netdev);
2714 u32 mc_filter[2]; /* Multicast hash filter */
2718 netif_stop_queue(netdev);
2719 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2720 ocp_data &= ~RCR_ACPT_ALL;
2721 ocp_data |= RCR_AB | RCR_APM;
2723 if (netdev->flags & IFF_PROMISC) {
2724 /* Unconditionally log net taps. */
2725 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2726 ocp_data |= RCR_AM | RCR_AAP;
2727 mc_filter[1] = 0xffffffff;
2728 mc_filter[0] = 0xffffffff;
2729 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2730 (netdev->flags & IFF_ALLMULTI)) {
2731 /* Too many to filter perfectly -- accept all multicasts. */
2733 mc_filter[1] = 0xffffffff;
2734 mc_filter[0] = 0xffffffff;
2736 struct netdev_hw_addr *ha;
2740 netdev_for_each_mc_addr(ha, netdev) {
2741 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2743 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2748 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2749 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2751 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2752 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2753 netif_wake_queue(netdev);
2756 static netdev_features_t
2757 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2758 netdev_features_t features)
2760 u32 mss = skb_shinfo(skb)->gso_size;
2761 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2763 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) &&
2764 skb_transport_offset(skb) > max_offset)
2765 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2766 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2767 features &= ~NETIF_F_GSO_MASK;
2772 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2773 struct net_device *netdev)
2775 struct r8152 *tp = netdev_priv(netdev);
2777 skb_tx_timestamp(skb);
2779 skb_queue_tail(&tp->tx_queue, skb);
2781 if (!list_empty(&tp->tx_free)) {
2782 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2783 set_bit(SCHEDULE_TASKLET, &tp->flags);
2784 schedule_delayed_work(&tp->schedule, 0);
2786 usb_mark_last_busy(tp->udev);
2787 tasklet_schedule(&tp->tx_tl);
2789 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2790 netif_stop_queue(netdev);
2793 return NETDEV_TX_OK;
2796 static void r8152b_reset_packet_filter(struct r8152 *tp)
2800 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2801 ocp_data &= ~FMC_FCR_MCU_EN;
2802 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2803 ocp_data |= FMC_FCR_MCU_EN;
2804 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2807 static void rtl8152_nic_reset(struct r8152 *tp)
2812 switch (tp->version) {
2816 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2818 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2820 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2821 ocp_data &= ~BMU_RESET_EP_IN;
2822 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2824 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2825 ocp_data |= CDC_ECM_EN;
2826 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2828 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2830 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2832 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2833 ocp_data |= BMU_RESET_EP_IN;
2834 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2836 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2837 ocp_data &= ~CDC_ECM_EN;
2838 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2842 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2844 for (i = 0; i < 1000; i++) {
2845 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2847 usleep_range(100, 400);
2853 static void set_tx_qlen(struct r8152 *tp)
2855 tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
2858 static inline u16 rtl8152_get_speed(struct r8152 *tp)
2860 return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2863 static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
2867 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2869 ocp_data |= EEEP_CR_EEEP_TX;
2871 ocp_data &= ~EEEP_CR_EEEP_TX;
2872 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2875 static void rtl_set_eee_plus(struct r8152 *tp)
2877 if (rtl8152_get_speed(tp) & _10bps)
2878 rtl_eee_plus_en(tp, true);
2880 rtl_eee_plus_en(tp, false);
2883 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2887 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2889 ocp_data |= RXDY_GATED_EN;
2891 ocp_data &= ~RXDY_GATED_EN;
2892 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2895 static int rtl_start_rx(struct r8152 *tp)
2897 struct rx_agg *agg, *agg_next;
2898 struct list_head tmp_list;
2899 unsigned long flags;
2902 INIT_LIST_HEAD(&tmp_list);
2904 spin_lock_irqsave(&tp->rx_lock, flags);
2906 INIT_LIST_HEAD(&tp->rx_done);
2907 INIT_LIST_HEAD(&tp->rx_used);
2909 list_splice_init(&tp->rx_info, &tmp_list);
2911 spin_unlock_irqrestore(&tp->rx_lock, flags);
2913 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2914 INIT_LIST_HEAD(&agg->list);
2916 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2917 if (++i > RTL8152_MAX_RX) {
2918 spin_lock_irqsave(&tp->rx_lock, flags);
2919 list_add_tail(&agg->list, &tp->rx_used);
2920 spin_unlock_irqrestore(&tp->rx_lock, flags);
2921 } else if (unlikely(ret < 0)) {
2922 spin_lock_irqsave(&tp->rx_lock, flags);
2923 list_add_tail(&agg->list, &tp->rx_done);
2924 spin_unlock_irqrestore(&tp->rx_lock, flags);
2926 ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2930 spin_lock_irqsave(&tp->rx_lock, flags);
2931 WARN_ON(!list_empty(&tp->rx_info));
2932 list_splice(&tmp_list, &tp->rx_info);
2933 spin_unlock_irqrestore(&tp->rx_lock, flags);
2938 static int rtl_stop_rx(struct r8152 *tp)
2940 struct rx_agg *agg, *agg_next;
2941 struct list_head tmp_list;
2942 unsigned long flags;
2944 INIT_LIST_HEAD(&tmp_list);
2946 /* The usb_kill_urb() couldn't be used in atomic.
2947 * Therefore, move the list of rx_info to a tmp one.
2948 * Then, list_for_each_entry_safe could be used without
2952 spin_lock_irqsave(&tp->rx_lock, flags);
2953 list_splice_init(&tp->rx_info, &tmp_list);
2954 spin_unlock_irqrestore(&tp->rx_lock, flags);
2956 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2957 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2958 * equal to 1, so the other ones could be freed safely.
2960 if (page_count(agg->page) > 1)
2961 free_rx_agg(tp, agg);
2963 usb_kill_urb(agg->urb);
2966 /* Move back the list of temp to the rx_info */
2967 spin_lock_irqsave(&tp->rx_lock, flags);
2968 WARN_ON(!list_empty(&tp->rx_info));
2969 list_splice(&tmp_list, &tp->rx_info);
2970 spin_unlock_irqrestore(&tp->rx_lock, flags);
2972 while (!skb_queue_empty(&tp->rx_queue))
2973 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2978 static void rtl_set_ifg(struct r8152 *tp, u16 speed)
2982 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
2983 ocp_data &= ~IFG_MASK;
2984 if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
2985 ocp_data |= IFG_144NS;
2986 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
2988 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
2989 ocp_data &= ~TX10MIDLE_EN;
2990 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
2992 ocp_data |= IFG_96NS;
2993 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
2995 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
2996 ocp_data |= TX10MIDLE_EN;
2997 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
3001 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
3003 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
3004 OWN_UPDATE | OWN_CLEAR);
3007 static int rtl_enable(struct r8152 *tp)
3011 r8152b_reset_packet_filter(tp);
3013 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
3014 ocp_data |= CR_RE | CR_TE;
3015 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
3017 switch (tp->version) {
3021 r8153b_rx_agg_chg_indicate(tp);
3027 rxdy_gated_en(tp, false);
3032 static int rtl8152_enable(struct r8152 *tp)
3034 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3038 rtl_set_eee_plus(tp);
3040 return rtl_enable(tp);
3043 static void r8153_set_rx_early_timeout(struct r8152 *tp)
3045 u32 ocp_data = tp->coalesce / 8;
3047 switch (tp->version) {
3052 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3059 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
3060 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
3062 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3064 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3073 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3075 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3077 r8153b_rx_agg_chg_indicate(tp);
3085 static void r8153_set_rx_early_size(struct r8152 *tp)
3087 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
3089 switch (tp->version) {
3094 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3100 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3109 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3111 r8153b_rx_agg_chg_indicate(tp);
3119 static int rtl8153_enable(struct r8152 *tp)
3123 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3127 rtl_set_eee_plus(tp);
3128 r8153_set_rx_early_timeout(tp);
3129 r8153_set_rx_early_size(tp);
3131 rtl_set_ifg(tp, rtl8152_get_speed(tp));
3133 switch (tp->version) {
3136 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
3137 ocp_data &= ~FC_PATCH_TASK;
3138 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3139 usleep_range(1000, 2000);
3140 ocp_data |= FC_PATCH_TASK;
3141 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3147 return rtl_enable(tp);
3150 static void rtl_disable(struct r8152 *tp)
3155 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3156 rtl_drop_queued_tx(tp);
3160 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3161 ocp_data &= ~RCR_ACPT_ALL;
3162 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3164 rtl_drop_queued_tx(tp);
3166 for (i = 0; i < RTL8152_MAX_TX; i++)
3167 usb_kill_urb(tp->tx_info[i].urb);
3169 rxdy_gated_en(tp, true);
3171 for (i = 0; i < 1000; i++) {
3172 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3173 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
3175 usleep_range(1000, 2000);
3178 for (i = 0; i < 1000; i++) {
3179 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
3181 usleep_range(1000, 2000);
3186 rtl8152_nic_reset(tp);
3189 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
3193 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
3195 ocp_data |= POWER_CUT;
3197 ocp_data &= ~POWER_CUT;
3198 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
3200 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
3201 ocp_data &= ~RESUME_INDICATE;
3202 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
3205 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
3209 switch (tp->version) {
3220 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
3222 ocp_data |= CPCR_RX_VLAN;
3224 ocp_data &= ~CPCR_RX_VLAN;
3225 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
3235 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
3237 ocp_data |= OUTER_VLAN | INNER_VLAN;
3239 ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
3240 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);
3245 static int rtl8152_set_features(struct net_device *dev,
3246 netdev_features_t features)
3248 netdev_features_t changed = features ^ dev->features;
3249 struct r8152 *tp = netdev_priv(dev);
3252 ret = usb_autopm_get_interface(tp->intf);
3256 mutex_lock(&tp->control);
3258 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
3259 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3260 rtl_rx_vlan_en(tp, true);
3262 rtl_rx_vlan_en(tp, false);
3265 mutex_unlock(&tp->control);
3267 usb_autopm_put_interface(tp->intf);
3273 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
3275 static u32 __rtl_get_wol(struct r8152 *tp)
3280 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3281 if (ocp_data & LINK_ON_WAKE_EN)
3282 wolopts |= WAKE_PHY;
3284 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3285 if (ocp_data & UWF_EN)
3286 wolopts |= WAKE_UCAST;
3287 if (ocp_data & BWF_EN)
3288 wolopts |= WAKE_BCAST;
3289 if (ocp_data & MWF_EN)
3290 wolopts |= WAKE_MCAST;
3292 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3293 if (ocp_data & MAGIC_EN)
3294 wolopts |= WAKE_MAGIC;
3299 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3303 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3305 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3306 ocp_data &= ~LINK_ON_WAKE_EN;
3307 if (wolopts & WAKE_PHY)
3308 ocp_data |= LINK_ON_WAKE_EN;
3309 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3311 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3312 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3313 if (wolopts & WAKE_UCAST)
3315 if (wolopts & WAKE_BCAST)
3317 if (wolopts & WAKE_MCAST)
3319 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3321 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3323 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3324 ocp_data &= ~MAGIC_EN;
3325 if (wolopts & WAKE_MAGIC)
3326 ocp_data |= MAGIC_EN;
3327 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3329 if (wolopts & WAKE_ANY)
3330 device_set_wakeup_enable(&tp->udev->dev, true);
3332 device_set_wakeup_enable(&tp->udev->dev, false);
3335 static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
3337 u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3339 /* MAC clock speed down */
3341 ocp_data |= MAC_CLK_SPDWN_EN;
3343 ocp_data &= ~MAC_CLK_SPDWN_EN;
3345 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3348 static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
3352 /* MAC clock speed down */
3354 /* aldps_spdwn_ratio, tp10_spdwn_ratio */
3355 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3358 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3359 ocp_data &= ~EEE_SPDWN_RATIO_MASK;
3360 ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
3361 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3363 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3364 ocp_data &= ~MAC_CLK_SPDWN_EN;
3365 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3369 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3374 memset(u1u2, 0xff, sizeof(u1u2));
3376 memset(u1u2, 0x00, sizeof(u1u2));
3378 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3381 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3385 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3387 ocp_data |= LPM_U1U2_EN;
3389 ocp_data &= ~LPM_U1U2_EN;
3391 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3394 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3398 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3400 ocp_data |= U2P3_ENABLE;
3402 ocp_data &= ~U2P3_ENABLE;
3403 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3406 static void r8153b_ups_flags(struct r8152 *tp)
3410 if (tp->ups_info.green)
3411 ups_flags |= UPS_FLAGS_EN_GREEN;
3413 if (tp->ups_info.aldps)
3414 ups_flags |= UPS_FLAGS_EN_ALDPS;
3416 if (tp->ups_info.eee)
3417 ups_flags |= UPS_FLAGS_EN_EEE;
3419 if (tp->ups_info.flow_control)
3420 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3422 if (tp->ups_info.eee_ckdiv)
3423 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3425 if (tp->ups_info.eee_cmod_lv)
3426 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3428 if (tp->ups_info.r_tune)
3429 ups_flags |= UPS_FLAGS_R_TUNE;
3431 if (tp->ups_info._10m_ckdiv)
3432 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3434 if (tp->ups_info.eee_plloff_100)
3435 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3437 if (tp->ups_info.eee_plloff_giga)
3438 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3440 if (tp->ups_info._250m_ckdiv)
3441 ups_flags |= UPS_FLAGS_250M_CKDIV;
3443 if (tp->ups_info.ctap_short_off)
3444 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3446 switch (tp->ups_info.speed_duplex) {
3448 ups_flags |= ups_flags_speed(1);
3451 ups_flags |= ups_flags_speed(2);
3453 case NWAY_100M_HALF:
3454 ups_flags |= ups_flags_speed(3);
3456 case NWAY_100M_FULL:
3457 ups_flags |= ups_flags_speed(4);
3459 case NWAY_1000M_FULL:
3460 ups_flags |= ups_flags_speed(5);
3462 case FORCE_10M_HALF:
3463 ups_flags |= ups_flags_speed(6);
3465 case FORCE_10M_FULL:
3466 ups_flags |= ups_flags_speed(7);
3468 case FORCE_100M_HALF:
3469 ups_flags |= ups_flags_speed(8);
3471 case FORCE_100M_FULL:
3472 ups_flags |= ups_flags_speed(9);
3478 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3481 static void r8156_ups_flags(struct r8152 *tp)
3485 if (tp->ups_info.green)
3486 ups_flags |= UPS_FLAGS_EN_GREEN;
3488 if (tp->ups_info.aldps)
3489 ups_flags |= UPS_FLAGS_EN_ALDPS;
3491 if (tp->ups_info.eee)
3492 ups_flags |= UPS_FLAGS_EN_EEE;
3494 if (tp->ups_info.flow_control)
3495 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3497 if (tp->ups_info.eee_ckdiv)
3498 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3500 if (tp->ups_info._10m_ckdiv)
3501 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3503 if (tp->ups_info.eee_plloff_100)
3504 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3506 if (tp->ups_info.eee_plloff_giga)
3507 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3509 if (tp->ups_info._250m_ckdiv)
3510 ups_flags |= UPS_FLAGS_250M_CKDIV;
3512 switch (tp->ups_info.speed_duplex) {
3513 case FORCE_10M_HALF:
3514 ups_flags |= ups_flags_speed(0);
3516 case FORCE_10M_FULL:
3517 ups_flags |= ups_flags_speed(1);
3519 case FORCE_100M_HALF:
3520 ups_flags |= ups_flags_speed(2);
3522 case FORCE_100M_FULL:
3523 ups_flags |= ups_flags_speed(3);
3526 ups_flags |= ups_flags_speed(4);
3529 ups_flags |= ups_flags_speed(5);
3531 case NWAY_100M_HALF:
3532 ups_flags |= ups_flags_speed(6);
3534 case NWAY_100M_FULL:
3535 ups_flags |= ups_flags_speed(7);
3537 case NWAY_1000M_FULL:
3538 ups_flags |= ups_flags_speed(8);
3540 case NWAY_2500M_FULL:
3541 ups_flags |= ups_flags_speed(9);
3547 switch (tp->ups_info.lite_mode) {
3549 ups_flags |= 0 << 5;
3552 ups_flags |= 2 << 5;
3556 ups_flags |= 1 << 5;
3560 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3563 static void rtl_green_en(struct r8152 *tp, bool enable)
3567 data = sram_read(tp, SRAM_GREEN_CFG);
3569 data |= GREEN_ETH_EN;
3571 data &= ~GREEN_ETH_EN;
3572 sram_write(tp, SRAM_GREEN_CFG, data);
3574 tp->ups_info.green = enable;
3577 static void r8153b_green_en(struct r8152 *tp, bool enable)
3580 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
3581 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3582 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3584 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3585 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3586 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3589 rtl_green_en(tp, true);
3592 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3597 for (i = 0; i < 500; i++) {
3598 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3599 data &= PHY_STAT_MASK;
3601 if (data == desired)
3603 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3604 data == PHY_STAT_EXT_INIT) {
3609 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3616 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3618 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3621 r8153b_ups_flags(tp);
3623 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3624 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3626 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3627 ocp_data |= UPS_FORCE_PWR_DOWN;
3628 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3630 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3631 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3633 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3634 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3635 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3637 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3640 for (i = 0; i < 500; i++) {
3641 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3647 tp->rtl_ops.hw_phy_cfg(tp);
3649 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3650 tp->duplex, tp->advertising);
3655 static void r8153c_ups_en(struct r8152 *tp, bool enable)
3657 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3660 r8153b_ups_flags(tp);
3662 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3663 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3665 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3666 ocp_data |= UPS_FORCE_PWR_DOWN;
3667 ocp_data &= ~BIT(7);
3668 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3670 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3671 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3673 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3674 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3675 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3677 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3680 for (i = 0; i < 500; i++) {
3681 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3687 tp->rtl_ops.hw_phy_cfg(tp);
3689 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3690 tp->duplex, tp->advertising);
3693 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3695 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3697 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3699 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3703 static void r8156_ups_en(struct r8152 *tp, bool enable)
3705 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3708 r8156_ups_flags(tp);
3710 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3711 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3713 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3714 ocp_data |= UPS_FORCE_PWR_DOWN;
3715 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3717 switch (tp->version) {
3720 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
3721 ocp_data &= ~OOBS_POLLING;
3722 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
3728 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3729 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3731 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3732 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3733 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3735 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3736 tp->rtl_ops.hw_phy_cfg(tp);
3738 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3739 tp->duplex, tp->advertising);
3744 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3748 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3750 ocp_data |= PWR_EN | PHASE2_EN;
3752 ocp_data &= ~(PWR_EN | PHASE2_EN);
3753 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3755 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3756 ocp_data &= ~PCUT_STATUS;
3757 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3760 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3764 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3766 ocp_data |= PWR_EN | PHASE2_EN;
3768 ocp_data &= ~PWR_EN;
3769 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3771 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3772 ocp_data &= ~PCUT_STATUS;
3773 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3776 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3780 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3782 ocp_data |= UPCOMING_RUNTIME_D3;
3784 ocp_data &= ~UPCOMING_RUNTIME_D3;
3785 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3787 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3788 ocp_data &= ~LINK_CHG_EVENT;
3789 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3791 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3792 ocp_data &= ~LINK_CHANGE_FLAG;
3793 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3796 static bool rtl_can_wakeup(struct r8152 *tp)
3798 struct usb_device *udev = tp->udev;
3800 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3803 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3808 __rtl_set_wol(tp, WAKE_ANY);
3810 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3812 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3813 ocp_data |= LINK_OFF_WAKE_EN;
3814 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3816 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3820 __rtl_set_wol(tp, tp->saved_wolopts);
3822 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3824 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3825 ocp_data &= ~LINK_OFF_WAKE_EN;
3826 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3828 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3832 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3835 r8153_u1u2en(tp, false);
3836 r8153_u2p3en(tp, false);
3837 rtl_runtime_suspend_enable(tp, true);
3839 rtl_runtime_suspend_enable(tp, false);
3841 switch (tp->version) {
3848 r8153_u2p3en(tp, true);
3852 r8153_u1u2en(tp, true);
3856 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3859 r8153_queue_wake(tp, true);
3860 r8153b_u1u2en(tp, false);
3861 r8153_u2p3en(tp, false);
3862 rtl_runtime_suspend_enable(tp, true);
3863 r8153b_ups_en(tp, true);
3865 r8153b_ups_en(tp, false);
3866 r8153_queue_wake(tp, false);
3867 rtl_runtime_suspend_enable(tp, false);
3868 if (tp->udev->speed >= USB_SPEED_SUPER)
3869 r8153b_u1u2en(tp, true);
3873 static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
3876 r8153_queue_wake(tp, true);
3877 r8153b_u1u2en(tp, false);
3878 r8153_u2p3en(tp, false);
3879 rtl_runtime_suspend_enable(tp, true);
3880 r8153c_ups_en(tp, true);
3882 r8153c_ups_en(tp, false);
3883 r8153_queue_wake(tp, false);
3884 rtl_runtime_suspend_enable(tp, false);
3885 r8153b_u1u2en(tp, true);
3889 static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
3892 r8153_queue_wake(tp, true);
3893 r8153b_u1u2en(tp, false);
3894 r8153_u2p3en(tp, false);
3895 rtl_runtime_suspend_enable(tp, true);
3897 r8153_queue_wake(tp, false);
3898 rtl_runtime_suspend_enable(tp, false);
3899 r8153_u2p3en(tp, true);
3900 if (tp->udev->speed >= USB_SPEED_SUPER)
3901 r8153b_u1u2en(tp, true);
3905 static void r8153_teredo_off(struct r8152 *tp)
3909 switch (tp->version) {
3917 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3918 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3920 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3933 /* The bit 0 ~ 7 are relative with teredo settings. They are
3934 * W1C (write 1 to clear), so set all 1 to disable it.
3936 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3940 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3941 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3942 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3945 static void rtl_reset_bmu(struct r8152 *tp)
3949 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3950 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3951 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3952 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3953 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3956 /* Clear the bp to stop the firmware before loading a new one */
3957 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3959 switch (tp->version) {
3968 ocp_write_byte(tp, type, PLA_BP_EN, 0);
3971 ocp_write_word(tp, type, USB_BP2_EN, 0);
3973 ocp_write_word(tp, type, USB_BP_8, 0);
3974 ocp_write_word(tp, type, USB_BP_9, 0);
3975 ocp_write_word(tp, type, USB_BP_10, 0);
3976 ocp_write_word(tp, type, USB_BP_11, 0);
3977 ocp_write_word(tp, type, USB_BP_12, 0);
3978 ocp_write_word(tp, type, USB_BP_13, 0);
3979 ocp_write_word(tp, type, USB_BP_14, 0);
3980 ocp_write_word(tp, type, USB_BP_15, 0);
3990 if (type == MCU_TYPE_USB) {
3991 ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3993 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3994 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3995 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3996 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3997 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3998 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3999 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
4000 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
4002 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
4007 ocp_write_word(tp, type, PLA_BP_0, 0);
4008 ocp_write_word(tp, type, PLA_BP_1, 0);
4009 ocp_write_word(tp, type, PLA_BP_2, 0);
4010 ocp_write_word(tp, type, PLA_BP_3, 0);
4011 ocp_write_word(tp, type, PLA_BP_4, 0);
4012 ocp_write_word(tp, type, PLA_BP_5, 0);
4013 ocp_write_word(tp, type, PLA_BP_6, 0);
4014 ocp_write_word(tp, type, PLA_BP_7, 0);
4016 /* wait 3 ms to make sure the firmware is stopped */
4017 usleep_range(3000, 6000);
4018 ocp_write_word(tp, type, PLA_BP_BA, 0);
4021 static inline void rtl_reset_ocp_base(struct r8152 *tp)
4026 static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
4031 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
4033 data |= PATCH_REQUEST;
4036 data &= ~PATCH_REQUEST;
4037 check = PATCH_READY;
4039 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
4041 for (i = 0; wait && i < 5000; i++) {
4044 usleep_range(1000, 2000);
4045 ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
4046 if ((ocp_data & PATCH_READY) ^ check)
4050 if (request && wait &&
4051 !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
4052 dev_err(&tp->intf->dev, "PHY patch request fail\n");
4053 rtl_phy_patch_request(tp, false, false);
4060 static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
4062 if (patch_key && key_addr) {
4063 sram_write(tp, key_addr, patch_key);
4064 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
4065 } else if (key_addr) {
4068 sram_write(tp, 0x0000, 0x0000);
4070 data = ocp_reg_read(tp, OCP_PHY_LOCK);
4071 data &= ~PATCH_LOCK;
4072 ocp_reg_write(tp, OCP_PHY_LOCK, data);
4074 sram_write(tp, key_addr, 0x0000);
4081 rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
4083 if (rtl_phy_patch_request(tp, true, wait))
4086 rtl_patch_key_set(tp, key_addr, patch_key);
4091 static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
4093 rtl_patch_key_set(tp, key_addr, 0);
4095 rtl_phy_patch_request(tp, false, wait);
4100 static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)
4106 switch (tp->version) {
4127 fw_offset = __le16_to_cpu(phy->fw_offset);
4128 length = __le32_to_cpu(phy->blk_hdr.length);
4129 if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4130 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4134 length -= fw_offset;
4136 dev_err(&tp->intf->dev, "invalid block length\n");
4140 if (__le16_to_cpu(phy->fw_reg) != 0x9A00) {
4141 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4150 static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)
4154 switch (tp->version) {
4165 if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {
4166 dev_err(&tp->intf->dev, "invalid block length\n");
4170 if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {
4171 dev_err(&tp->intf->dev, "invalid phy ver addr\n");
4180 static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)
4184 switch (tp->version) {
4195 if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {
4196 dev_err(&tp->intf->dev, "invalid block length\n");
4200 if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||
4201 __le16_to_cpu(fix->setting.data) != BIT(7)) {
4202 dev_err(&tp->intf->dev, "invalid phy fixup\n");
4211 static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)
4217 switch (tp->version) {
4228 fw_offset = __le16_to_cpu(phy->fw_offset);
4229 length = __le32_to_cpu(phy->blk_hdr.length);
4230 if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4231 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4235 length -= fw_offset;
4237 dev_err(&tp->intf->dev, "invalid block length\n");
4241 if (phy->pre_num > 2) {
4242 dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num);
4246 if (phy->bp_num > 8) {
4247 dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num);
4256 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
4259 u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
4262 switch (tp->version) {
4268 patch_en_addr = 0xa01a;
4276 fw_offset = __le16_to_cpu(phy->fw_offset);
4277 if (fw_offset < sizeof(*phy)) {
4278 dev_err(&tp->intf->dev, "fw_offset too small\n");
4282 length = __le32_to_cpu(phy->blk_hdr.length);
4283 if (length < fw_offset) {
4284 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4288 length -= __le16_to_cpu(phy->fw_offset);
4289 if (!length || (length & 1)) {
4290 dev_err(&tp->intf->dev, "invalid block length\n");
4294 if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
4295 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4299 if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
4300 dev_err(&tp->intf->dev, "invalid base address register\n");
4304 if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
4305 dev_err(&tp->intf->dev,
4306 "invalid patch mode enabled register\n");
4310 if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
4311 dev_err(&tp->intf->dev,
4312 "invalid register to switch the mode\n");
4316 if (__le16_to_cpu(phy->bp_start) != bp_start) {
4317 dev_err(&tp->intf->dev,
4318 "invalid start register of break point\n");
4322 if (__le16_to_cpu(phy->bp_num) > 4) {
4323 dev_err(&tp->intf->dev, "invalid break point number\n");
4332 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
4334 u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
4339 type = __le32_to_cpu(mac->blk_hdr.type);
4340 if (type == RTL_FW_PLA) {
4341 switch (tp->version) {
4346 bp_ba_addr = PLA_BP_BA;
4348 bp_start = PLA_BP_0;
4362 bp_ba_addr = PLA_BP_BA;
4363 bp_en_addr = PLA_BP_EN;
4364 bp_start = PLA_BP_0;
4369 bp_ba_addr = PLA_BP_BA;
4370 bp_en_addr = USB_BP2_EN;
4371 bp_start = PLA_BP_0;
4377 } else if (type == RTL_FW_USB) {
4378 switch (tp->version) {
4384 bp_ba_addr = USB_BP_BA;
4385 bp_en_addr = USB_BP_EN;
4386 bp_start = USB_BP_0;
4397 bp_ba_addr = USB_BP_BA;
4398 bp_en_addr = USB_BP2_EN;
4399 bp_start = USB_BP_0;
4412 fw_offset = __le16_to_cpu(mac->fw_offset);
4413 if (fw_offset < sizeof(*mac)) {
4414 dev_err(&tp->intf->dev, "fw_offset too small\n");
4418 length = __le32_to_cpu(mac->blk_hdr.length);
4419 if (length < fw_offset) {
4420 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4424 length -= fw_offset;
4425 if (length < 4 || (length & 3)) {
4426 dev_err(&tp->intf->dev, "invalid block length\n");
4430 if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
4431 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4435 if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
4436 dev_err(&tp->intf->dev, "invalid base address register\n");
4440 if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
4441 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
4445 if (__le16_to_cpu(mac->bp_start) != bp_start) {
4446 dev_err(&tp->intf->dev,
4447 "invalid start register of break point\n");
4451 if (__le16_to_cpu(mac->bp_num) > max_bp) {
4452 dev_err(&tp->intf->dev, "invalid break point number\n");
4456 for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
4458 dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
4468 /* Verify the checksum for the firmware file. It is calculated from the version
4469 * field to the end of the file. Compare the result with the checksum field to
4470 * make sure the file is correct.
4472 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
4473 struct fw_header *fw_hdr, size_t size)
4475 unsigned char checksum[sizeof(fw_hdr->checksum)];
4476 struct crypto_shash *alg;
4477 struct shash_desc *sdesc;
4481 alg = crypto_alloc_shash("sha256", 0, 0);
4487 if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
4489 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
4490 crypto_shash_digestsize(alg));
4494 len = sizeof(*sdesc) + crypto_shash_descsize(alg);
4495 sdesc = kmalloc(len, GFP_KERNEL);
4502 len = size - sizeof(fw_hdr->checksum);
4503 rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
4508 if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
4509 dev_err(&tp->intf->dev, "checksum fail\n");
4514 crypto_free_shash(alg);
4519 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
4521 const struct firmware *fw = rtl_fw->fw;
4522 struct fw_header *fw_hdr = (struct fw_header *)fw->data;
4523 unsigned long fw_flags = 0;
4527 if (fw->size < sizeof(*fw_hdr)) {
4528 dev_err(&tp->intf->dev, "file too small\n");
4532 ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
4538 for (i = sizeof(*fw_hdr); i < fw->size;) {
4539 struct fw_block *block = (struct fw_block *)&fw->data[i];
4542 if ((i + sizeof(*block)) > fw->size)
4545 type = __le32_to_cpu(block->type);
4548 if (__le32_to_cpu(block->length) != sizeof(*block))
4552 if (test_bit(FW_FLAGS_PLA, &fw_flags)) {
4553 dev_err(&tp->intf->dev,
4554 "multiple PLA firmware encountered");
4558 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4559 dev_err(&tp->intf->dev,
4560 "check PLA firmware failed\n");
4563 __set_bit(FW_FLAGS_PLA, &fw_flags);
4566 if (test_bit(FW_FLAGS_USB, &fw_flags)) {
4567 dev_err(&tp->intf->dev,
4568 "multiple USB firmware encountered");
4572 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4573 dev_err(&tp->intf->dev,
4574 "check USB firmware failed\n");
4577 __set_bit(FW_FLAGS_USB, &fw_flags);
4579 case RTL_FW_PHY_START:
4580 if (test_bit(FW_FLAGS_START, &fw_flags) ||
4581 test_bit(FW_FLAGS_NC, &fw_flags) ||
4582 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4583 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4584 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4585 test_bit(FW_FLAGS_UC, &fw_flags) ||
4586 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4587 dev_err(&tp->intf->dev,
4588 "check PHY_START fail\n");
4592 if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {
4593 dev_err(&tp->intf->dev,
4594 "Invalid length for PHY_START\n");
4597 __set_bit(FW_FLAGS_START, &fw_flags);
4599 case RTL_FW_PHY_STOP:
4600 if (test_bit(FW_FLAGS_STOP, &fw_flags) ||
4601 !test_bit(FW_FLAGS_START, &fw_flags)) {
4602 dev_err(&tp->intf->dev,
4603 "Check PHY_STOP fail\n");
4607 if (__le32_to_cpu(block->length) != sizeof(*block)) {
4608 dev_err(&tp->intf->dev,
4609 "Invalid length for PHY_STOP\n");
4612 __set_bit(FW_FLAGS_STOP, &fw_flags);
4615 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4616 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4617 dev_err(&tp->intf->dev,
4618 "check PHY_NC fail\n");
4622 if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4623 dev_err(&tp->intf->dev,
4624 "multiple PHY NC encountered\n");
4628 if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) {
4629 dev_err(&tp->intf->dev,
4630 "check PHY NC firmware failed\n");
4633 __set_bit(FW_FLAGS_NC, &fw_flags);
4635 case RTL_FW_PHY_UNION_NC:
4636 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4637 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4638 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4639 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4640 test_bit(FW_FLAGS_UC, &fw_flags) ||
4641 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4642 dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n");
4646 if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4647 dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n");
4651 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4652 dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n");
4655 __set_bit(FW_FLAGS_NC, &fw_flags);
4657 case RTL_FW_PHY_UNION_NC1:
4658 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4659 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4660 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4661 test_bit(FW_FLAGS_UC, &fw_flags) ||
4662 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4663 dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n");
4667 if (test_bit(FW_FLAGS_NC1, &fw_flags)) {
4668 dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n");
4672 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4673 dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n");
4676 __set_bit(FW_FLAGS_NC1, &fw_flags);
4678 case RTL_FW_PHY_UNION_NC2:
4679 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4680 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4681 test_bit(FW_FLAGS_UC, &fw_flags) ||
4682 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4683 dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n");
4687 if (test_bit(FW_FLAGS_NC2, &fw_flags)) {
4688 dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n");
4692 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4693 dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n");
4696 __set_bit(FW_FLAGS_NC2, &fw_flags);
4698 case RTL_FW_PHY_UNION_UC2:
4699 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4700 test_bit(FW_FLAGS_UC, &fw_flags) ||
4701 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4702 dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n");
4706 if (test_bit(FW_FLAGS_UC2, &fw_flags)) {
4707 dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n");
4711 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4712 dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n");
4715 __set_bit(FW_FLAGS_UC2, &fw_flags);
4717 case RTL_FW_PHY_UNION_UC:
4718 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4719 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4720 dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n");
4724 if (test_bit(FW_FLAGS_UC, &fw_flags)) {
4725 dev_err(&tp->intf->dev, "multiple PHY UC encountered\n");
4729 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4730 dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n");
4733 __set_bit(FW_FLAGS_UC, &fw_flags);
4735 case RTL_FW_PHY_UNION_MISC:
4736 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4737 dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n");
4741 case RTL_FW_PHY_FIXUP:
4742 if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) {
4743 dev_err(&tp->intf->dev, "check PHY fixup failed\n");
4747 case RTL_FW_PHY_SPEED_UP:
4748 if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {
4749 dev_err(&tp->intf->dev, "multiple PHY firmware encountered");
4753 if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) {
4754 dev_err(&tp->intf->dev, "check PHY speed up failed\n");
4757 __set_bit(FW_FLAGS_SPEED_UP, &fw_flags);
4759 case RTL_FW_PHY_VER:
4760 if (test_bit(FW_FLAGS_START, &fw_flags) ||
4761 test_bit(FW_FLAGS_NC, &fw_flags) ||
4762 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4763 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4764 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4765 test_bit(FW_FLAGS_UC, &fw_flags) ||
4766 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4767 dev_err(&tp->intf->dev, "Invalid order to set PHY version\n");
4771 if (test_bit(FW_FLAGS_VER, &fw_flags)) {
4772 dev_err(&tp->intf->dev, "multiple PHY version encountered");
4776 if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) {
4777 dev_err(&tp->intf->dev, "check PHY version failed\n");
4780 __set_bit(FW_FLAGS_VER, &fw_flags);
4783 dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
4789 i += ALIGN(__le32_to_cpu(block->length), 8);
4793 if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {
4794 dev_err(&tp->intf->dev, "without PHY_STOP\n");
4803 static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)
4808 rtl_reset_ocp_base(tp);
4810 if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {
4811 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4815 len = __le32_to_cpu(phy->blk_hdr.length);
4816 len -= __le16_to_cpu(phy->fw_offset);
4817 data = (u8 *)phy + __le16_to_cpu(phy->fw_offset);
4819 if (rtl_phy_patch_request(tp, true, wait))
4831 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);
4832 ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;
4833 ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data);
4835 generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB);
4840 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);
4841 ocp_data |= POL_GPHY_PATCH;
4842 ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data);
4844 for (i = 0; i < 1000; i++) {
4845 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))
4850 dev_err(&tp->intf->dev, "ram code speedup mode timeout\n");
4855 rtl_reset_ocp_base(tp);
4857 rtl_phy_patch_request(tp, false, wait);
4859 if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))
4860 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4862 dev_err(&tp->intf->dev, "ram code speedup mode fail\n");
4865 static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)
4869 ver_addr = __le16_to_cpu(phy_ver->ver.addr);
4870 ver = __le16_to_cpu(phy_ver->ver.data);
4872 rtl_reset_ocp_base(tp);
4874 if (sram_read(tp, ver_addr) >= ver) {
4875 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4879 sram_write(tp, ver_addr, ver);
4881 dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver);
4886 static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)
4890 rtl_reset_ocp_base(tp);
4892 addr = __le16_to_cpu(fix->setting.addr);
4893 data = ocp_reg_read(tp, addr);
4895 switch (__le16_to_cpu(fix->bit_cmd)) {
4897 data &= __le16_to_cpu(fix->setting.data);
4900 data |= __le16_to_cpu(fix->setting.data);
4903 data &= ~__le16_to_cpu(fix->setting.data);
4906 data ^= __le16_to_cpu(fix->setting.data);
4912 ocp_reg_write(tp, addr, data);
4914 dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data);
4917 static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)
4923 rtl_reset_ocp_base(tp);
4926 for (i = 0; i < num; i++)
4927 sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),
4928 __le16_to_cpu(phy->pre_set[i].data));
4930 length = __le32_to_cpu(phy->blk_hdr.length);
4931 length -= __le16_to_cpu(phy->fw_offset);
4933 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
4935 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
4936 for (i = 0; i < num; i++)
4937 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
4940 for (i = 0; i < num; i++)
4941 sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));
4943 if (phy->bp_num && phy->bp_en.addr)
4944 sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));
4946 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4949 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
4951 u16 mode_reg, bp_index;
4955 rtl_reset_ocp_base(tp);
4957 mode_reg = __le16_to_cpu(phy->mode_reg);
4958 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
4959 sram_write(tp, __le16_to_cpu(phy->ba_reg),
4960 __le16_to_cpu(phy->ba_data));
4962 length = __le32_to_cpu(phy->blk_hdr.length);
4963 length -= __le16_to_cpu(phy->fw_offset);
4965 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
4967 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
4968 for (i = 0; i < num; i++)
4969 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
4971 sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
4972 __le16_to_cpu(phy->patch_en_value));
4974 bp_index = __le16_to_cpu(phy->bp_start);
4975 num = __le16_to_cpu(phy->bp_num);
4976 for (i = 0; i < num; i++) {
4977 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
4981 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
4983 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4986 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
4988 u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
4993 switch (__le32_to_cpu(mac->blk_hdr.type)) {
4995 type = MCU_TYPE_PLA;
4998 type = MCU_TYPE_USB;
5004 fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
5005 if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) {
5006 dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB");
5010 rtl_clear_bp(tp, type);
5012 /* Enable backup/restore of MACDBG. This is required after clearing PLA
5013 * break points and before applying the PLA firmware.
5015 if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
5016 !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
5017 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
5018 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
5021 length = __le32_to_cpu(mac->blk_hdr.length);
5022 length -= __le16_to_cpu(mac->fw_offset);
5025 data += __le16_to_cpu(mac->fw_offset);
5027 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
5030 ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
5031 __le16_to_cpu(mac->bp_ba_value));
5033 bp_index = __le16_to_cpu(mac->bp_start);
5034 bp_num = __le16_to_cpu(mac->bp_num);
5035 for (i = 0; i < bp_num; i++) {
5036 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
5040 bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
5042 ocp_write_word(tp, type, bp_en_addr,
5043 __le16_to_cpu(mac->bp_en_value));
5046 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
5049 dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
5052 static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
5054 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5055 const struct firmware *fw;
5056 struct fw_header *fw_hdr;
5057 struct fw_phy_patch_key *key;
5059 int i, patch_phy = 1;
5061 if (IS_ERR_OR_NULL(rtl_fw->fw))
5065 fw_hdr = (struct fw_header *)fw->data;
5070 for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
5071 struct fw_block *block = (struct fw_block *)&fw->data[i];
5073 switch (__le32_to_cpu(block->type)) {
5078 rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
5080 case RTL_FW_PHY_START:
5083 key = (struct fw_phy_patch_key *)block;
5084 key_addr = __le16_to_cpu(key->key_reg);
5085 rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);
5087 case RTL_FW_PHY_STOP:
5091 rtl_post_ram_code(tp, key_addr, !power_cut);
5094 rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
5096 case RTL_FW_PHY_VER:
5097 patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block);
5099 case RTL_FW_PHY_UNION_NC:
5100 case RTL_FW_PHY_UNION_NC1:
5101 case RTL_FW_PHY_UNION_NC2:
5102 case RTL_FW_PHY_UNION_UC2:
5103 case RTL_FW_PHY_UNION_UC:
5104 case RTL_FW_PHY_UNION_MISC:
5106 rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block);
5108 case RTL_FW_PHY_FIXUP:
5110 rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block);
5112 case RTL_FW_PHY_SPEED_UP:
5113 rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut);
5119 i += ALIGN(__le32_to_cpu(block->length), 8);
5123 if (rtl_fw->post_fw)
5124 rtl_fw->post_fw(tp);
5126 rtl_reset_ocp_base(tp);
5127 strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
5128 dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
5131 static void rtl8152_release_firmware(struct r8152 *tp)
5133 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5135 if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
5136 release_firmware(rtl_fw->fw);
5141 static int rtl8152_request_firmware(struct r8152 *tp)
5143 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5146 if (rtl_fw->fw || !rtl_fw->fw_name) {
5147 dev_info(&tp->intf->dev, "skip request firmware\n");
5152 rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
5156 rc = rtl8152_check_firmware(tp, rtl_fw);
5158 release_firmware(rtl_fw->fw);
5162 rtl_fw->fw = ERR_PTR(rc);
5164 dev_warn(&tp->intf->dev,
5165 "unable to load firmware patch %s (%ld)\n",
5166 rtl_fw->fw_name, rc);
5172 static void r8152_aldps_en(struct r8152 *tp, bool enable)
5175 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
5176 LINKENA | DIS_SDSAVE);
5178 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
5184 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
5186 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
5187 ocp_reg_write(tp, OCP_EEE_DATA, reg);
5188 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
5191 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
5195 r8152_mmd_indirect(tp, dev, reg);
5196 data = ocp_reg_read(tp, OCP_EEE_DATA);
5197 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5202 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
5204 r8152_mmd_indirect(tp, dev, reg);
5205 ocp_reg_write(tp, OCP_EEE_DATA, data);
5206 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5209 static void r8152_eee_en(struct r8152 *tp, bool enable)
5211 u16 config1, config2, config3;
5214 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5215 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
5216 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
5217 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
5220 ocp_data |= EEE_RX_EN | EEE_TX_EN;
5221 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
5222 config1 |= sd_rise_time(1);
5223 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
5224 config3 |= fast_snr(42);
5226 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5227 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
5229 config1 |= sd_rise_time(7);
5230 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
5231 config3 |= fast_snr(511);
5234 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5235 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
5236 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
5237 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
5240 static void r8153_eee_en(struct r8152 *tp, bool enable)
5245 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5246 config = ocp_reg_read(tp, OCP_EEE_CFG);
5249 ocp_data |= EEE_RX_EN | EEE_TX_EN;
5252 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5253 config &= ~EEE10_EN;
5256 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5257 ocp_reg_write(tp, OCP_EEE_CFG, config);
5259 tp->ups_info.eee = enable;
5262 static void r8156_eee_en(struct r8152 *tp, bool enable)
5266 r8153_eee_en(tp, enable);
5268 config = ocp_reg_read(tp, OCP_EEE_ADV2);
5271 config |= MDIO_EEE_2_5GT;
5273 config &= ~MDIO_EEE_2_5GT;
5275 ocp_reg_write(tp, OCP_EEE_ADV2, config);
5278 static void rtl_eee_enable(struct r8152 *tp, bool enable)
5280 switch (tp->version) {
5285 r8152_eee_en(tp, true);
5286 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
5289 r8152_eee_en(tp, false);
5290 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
5301 r8153_eee_en(tp, true);
5302 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5304 r8153_eee_en(tp, false);
5305 ocp_reg_write(tp, OCP_EEE_ADV, 0);
5314 r8156_eee_en(tp, true);
5315 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5317 r8156_eee_en(tp, false);
5318 ocp_reg_write(tp, OCP_EEE_ADV, 0);
5326 static void r8152b_enable_fc(struct r8152 *tp)
5330 anar = r8152_mdio_read(tp, MII_ADVERTISE);
5331 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
5332 r8152_mdio_write(tp, MII_ADVERTISE, anar);
5334 tp->ups_info.flow_control = true;
5337 static void rtl8152_disable(struct r8152 *tp)
5339 r8152_aldps_en(tp, false);
5341 r8152_aldps_en(tp, true);
5344 static void r8152b_hw_phy_cfg(struct r8152 *tp)
5346 rtl8152_apply_firmware(tp, false);
5347 rtl_eee_enable(tp, tp->eee_en);
5348 r8152_aldps_en(tp, true);
5349 r8152b_enable_fc(tp);
5351 set_bit(PHY_RESET, &tp->flags);
5354 static void wait_oob_link_list_ready(struct r8152 *tp)
5359 for (i = 0; i < 1000; i++) {
5360 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5361 if (ocp_data & LINK_LIST_READY)
5363 usleep_range(1000, 2000);
5367 static void r8156b_wait_loading_flash(struct r8152 *tp)
5369 if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
5370 !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
5373 for (i = 0; i < 100; i++) {
5374 if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
5376 usleep_range(1000, 2000);
5381 static void r8152b_exit_oob(struct r8152 *tp)
5385 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5386 ocp_data &= ~RCR_ACPT_ALL;
5387 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5389 rxdy_gated_en(tp, true);
5390 r8153_teredo_off(tp);
5391 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
5392 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
5394 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5395 ocp_data &= ~NOW_IS_OOB;
5396 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5398 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5399 ocp_data &= ~MCU_BORW_EN;
5400 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5402 wait_oob_link_list_ready(tp);
5404 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5405 ocp_data |= RE_INIT_LL;
5406 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5408 wait_oob_link_list_ready(tp);
5410 rtl8152_nic_reset(tp);
5412 /* rx share fifo credit full threshold */
5413 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5415 if (tp->udev->speed == USB_SPEED_FULL ||
5416 tp->udev->speed == USB_SPEED_LOW) {
5417 /* rx share fifo credit near full threshold */
5418 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5420 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5423 /* rx share fifo credit near full threshold */
5424 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5426 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5430 /* TX share fifo free credit full threshold */
5431 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5433 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
5434 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
5435 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
5436 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
5438 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5440 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5442 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5443 ocp_data |= TCR0_AUTO_FIFO;
5444 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5447 static void r8152b_enter_oob(struct r8152 *tp)
5451 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5452 ocp_data &= ~NOW_IS_OOB;
5453 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5455 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
5456 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
5457 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
5461 wait_oob_link_list_ready(tp);
5463 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5464 ocp_data |= RE_INIT_LL;
5465 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5467 wait_oob_link_list_ready(tp);
5469 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5471 rtl_rx_vlan_en(tp, true);
5473 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5474 ocp_data |= ALDPS_PROXY_MODE;
5475 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5477 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5478 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5479 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5481 rxdy_gated_en(tp, false);
5483 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5484 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5485 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5488 static int r8153_pre_firmware_1(struct r8152 *tp)
5492 /* Wait till the WTD timer is ready. It would take at most 104 ms. */
5493 for (i = 0; i < 104; i++) {
5494 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
5496 if (!(ocp_data & WTD1_EN))
5498 usleep_range(1000, 2000);
5504 static int r8153_post_firmware_1(struct r8152 *tp)
5506 /* set USB_BP_4 to support USB_SPEED_SUPER only */
5507 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
5508 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
5510 /* reset UPHY timer to 36 ms */
5511 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5516 static int r8153_pre_firmware_2(struct r8152 *tp)
5520 r8153_pre_firmware_1(tp);
5522 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5523 ocp_data &= ~FW_FIX_SUSPEND;
5524 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5529 static int r8153_post_firmware_2(struct r8152 *tp)
5533 /* enable bp0 if support USB_SPEED_SUPER only */
5534 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
5535 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5537 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5540 /* reset UPHY timer to 36 ms */
5541 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5543 /* enable U3P3 check, set the counter to 4 */
5544 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
5546 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5547 ocp_data |= FW_FIX_SUSPEND;
5548 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5550 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5551 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5552 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5557 static int r8153_post_firmware_3(struct r8152 *tp)
5561 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5562 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5563 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5565 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5566 ocp_data |= FW_IP_RESET_EN;
5567 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5572 static int r8153b_pre_firmware_1(struct r8152 *tp)
5574 /* enable fc timer and set timer to 1 second. */
5575 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
5576 CTRL_TIMER_EN | (1000 / 8));
5581 static int r8153b_post_firmware_1(struct r8152 *tp)
5585 /* enable bp0 for RTL8153-BND */
5586 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
5587 if (ocp_data & BND_MASK) {
5588 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5590 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5593 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5594 ocp_data |= FLOW_CTRL_PATCH_OPT;
5595 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5597 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5598 ocp_data |= FC_PATCH_TASK;
5599 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5601 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5602 ocp_data |= FW_IP_RESET_EN;
5603 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5608 static int r8153c_post_firmware_1(struct r8152 *tp)
5612 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5613 ocp_data |= FLOW_CTRL_PATCH_2;
5614 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5616 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5617 ocp_data |= FC_PATCH_TASK;
5618 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5623 static int r8156a_post_firmware_1(struct r8152 *tp)
5627 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5628 ocp_data |= FW_IP_RESET_EN;
5629 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5631 /* Modify U3PHY parameter for compatibility issue */
5632 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e);
5633 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9);
5638 static void r8153_aldps_en(struct r8152 *tp, bool enable)
5642 data = ocp_reg_read(tp, OCP_POWER_CFG);
5645 ocp_reg_write(tp, OCP_POWER_CFG, data);
5650 ocp_reg_write(tp, OCP_POWER_CFG, data);
5651 for (i = 0; i < 20; i++) {
5652 usleep_range(1000, 2000);
5653 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
5658 tp->ups_info.aldps = enable;
5661 static void r8153_hw_phy_cfg(struct r8152 *tp)
5666 /* disable ALDPS before updating the PHY parameters */
5667 r8153_aldps_en(tp, false);
5669 /* disable EEE before updating the PHY parameters */
5670 rtl_eee_enable(tp, false);
5672 rtl8152_apply_firmware(tp, false);
5674 if (tp->version == RTL_VER_03) {
5675 data = ocp_reg_read(tp, OCP_EEE_CFG);
5676 data &= ~CTAP_SHORT_EN;
5677 ocp_reg_write(tp, OCP_EEE_CFG, data);
5680 data = ocp_reg_read(tp, OCP_POWER_CFG);
5681 data |= EEE_CLKDIV_EN;
5682 ocp_reg_write(tp, OCP_POWER_CFG, data);
5684 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5685 data |= EN_10M_BGOFF;
5686 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5687 data = ocp_reg_read(tp, OCP_POWER_CFG);
5688 data |= EN_10M_PLLOFF;
5689 ocp_reg_write(tp, OCP_POWER_CFG, data);
5690 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
5692 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5693 ocp_data |= PFM_PWM_SWITCH;
5694 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5696 /* Enable LPF corner auto tune */
5697 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
5699 /* Adjust 10M Amplitude */
5700 sram_write(tp, SRAM_10M_AMP1, 0x00af);
5701 sram_write(tp, SRAM_10M_AMP2, 0x0208);
5704 rtl_eee_enable(tp, true);
5706 r8153_aldps_en(tp, true);
5707 r8152b_enable_fc(tp);
5709 switch (tp->version) {
5716 r8153_u2p3en(tp, true);
5720 set_bit(PHY_RESET, &tp->flags);
5723 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
5727 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
5728 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
5729 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
5730 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
5735 static void r8153b_hw_phy_cfg(struct r8152 *tp)
5740 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
5741 if (ocp_data & PCUT_STATUS) {
5742 ocp_data &= ~PCUT_STATUS;
5743 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
5746 /* disable ALDPS before updating the PHY parameters */
5747 r8153_aldps_en(tp, false);
5749 /* disable EEE before updating the PHY parameters */
5750 rtl_eee_enable(tp, false);
5752 /* U1/U2/L1 idle timer. 500 us */
5753 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5755 data = r8153_phy_status(tp, 0);
5758 case PHY_STAT_PWRDN:
5759 case PHY_STAT_EXT_INIT:
5760 rtl8152_apply_firmware(tp, true);
5762 data = r8152_mdio_read(tp, MII_BMCR);
5763 data &= ~BMCR_PDOWN;
5764 r8152_mdio_write(tp, MII_BMCR, data);
5766 case PHY_STAT_LAN_ON:
5768 rtl8152_apply_firmware(tp, false);
5772 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
5774 data = sram_read(tp, SRAM_GREEN_CFG);
5776 sram_write(tp, SRAM_GREEN_CFG, data);
5777 data = ocp_reg_read(tp, OCP_NCTL_CFG);
5778 data |= PGA_RETURN_EN;
5779 ocp_reg_write(tp, OCP_NCTL_CFG, data);
5781 /* ADC Bias Calibration:
5782 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
5783 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
5786 ocp_data = r8152_efuse_read(tp, 0x7d);
5787 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
5789 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
5791 /* ups mode tx-link-pulse timing adjustment:
5792 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
5793 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
5795 ocp_data = ocp_reg_read(tp, 0xc426);
5798 u32 swr_cnt_1ms_ini;
5800 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
5801 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
5802 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
5803 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
5806 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5807 ocp_data |= PFM_PWM_SWITCH;
5808 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5811 if (!rtl_phy_patch_request(tp, true, true)) {
5812 data = ocp_reg_read(tp, OCP_POWER_CFG);
5813 data |= EEE_CLKDIV_EN;
5814 ocp_reg_write(tp, OCP_POWER_CFG, data);
5815 tp->ups_info.eee_ckdiv = true;
5817 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5818 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
5819 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5820 tp->ups_info.eee_cmod_lv = true;
5821 tp->ups_info._10m_ckdiv = true;
5822 tp->ups_info.eee_plloff_giga = true;
5824 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
5825 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
5826 tp->ups_info._250m_ckdiv = true;
5828 rtl_phy_patch_request(tp, false, true);
5832 rtl_eee_enable(tp, true);
5834 r8153_aldps_en(tp, true);
5835 r8152b_enable_fc(tp);
5837 set_bit(PHY_RESET, &tp->flags);
5840 static void r8153c_hw_phy_cfg(struct r8152 *tp)
5842 r8153b_hw_phy_cfg(tp);
5844 tp->ups_info.r_tune = true;
5847 static void rtl8153_change_mtu(struct r8152 *tp)
5849 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5850 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
5853 static void r8153_first_init(struct r8152 *tp)
5857 rxdy_gated_en(tp, true);
5858 r8153_teredo_off(tp);
5860 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5861 ocp_data &= ~RCR_ACPT_ALL;
5862 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5864 rtl8152_nic_reset(tp);
5867 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5868 ocp_data &= ~NOW_IS_OOB;
5869 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5871 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5872 ocp_data &= ~MCU_BORW_EN;
5873 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5875 wait_oob_link_list_ready(tp);
5877 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5878 ocp_data |= RE_INIT_LL;
5879 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5881 wait_oob_link_list_ready(tp);
5883 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5885 rtl8153_change_mtu(tp);
5887 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5888 ocp_data |= TCR0_AUTO_FIFO;
5889 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5891 rtl8152_nic_reset(tp);
5893 /* rx share fifo credit full threshold */
5894 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5895 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
5896 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
5897 /* TX share fifo free credit full threshold */
5898 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5901 static void r8153_enter_oob(struct r8152 *tp)
5905 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5906 ocp_data &= ~NOW_IS_OOB;
5907 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5912 wait_oob_link_list_ready(tp);
5914 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5915 ocp_data |= RE_INIT_LL;
5916 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5918 wait_oob_link_list_ready(tp);
5920 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5922 switch (tp->version) {
5927 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
5928 ocp_data &= ~TEREDO_WAKE_MASK;
5929 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
5935 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
5936 * type. Set it to zero. bits[7:0] are the W1C bits about
5937 * the events. Set them to all 1 to clear them.
5939 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
5946 rtl_rx_vlan_en(tp, true);
5948 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5949 ocp_data |= ALDPS_PROXY_MODE;
5950 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5952 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5953 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5954 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5956 rxdy_gated_en(tp, false);
5958 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5959 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5960 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5963 static void rtl8153_disable(struct r8152 *tp)
5965 r8153_aldps_en(tp, false);
5968 r8153_aldps_en(tp, true);
5971 static int rtl8156_enable(struct r8152 *tp)
5976 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5980 rtl_set_eee_plus(tp);
5981 r8153_set_rx_early_timeout(tp);
5982 r8153_set_rx_early_size(tp);
5984 speed = rtl8152_get_speed(tp);
5985 rtl_set_ifg(tp, speed);
5987 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
5988 if (speed & _2500bps)
5989 ocp_data &= ~IDLE_SPDWN_EN;
5991 ocp_data |= IDLE_SPDWN_EN;
5992 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
5994 if (speed & _1000bps)
5995 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);
5996 else if (speed & _500bps)
5997 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d);
5999 if (tp->udev->speed == USB_SPEED_HIGH) {
6000 /* USB 0xb45e[3:0] l1_nyet_hird */
6001 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6003 if (is_flow_control(speed))
6007 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6010 return rtl_enable(tp);
6013 static int rtl8156b_enable(struct r8152 *tp)
6018 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6022 rtl_set_eee_plus(tp);
6024 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
6025 ocp_data &= ~RX_AGGR_NUM_MASK;
6026 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);
6028 r8153_set_rx_early_timeout(tp);
6029 r8153_set_rx_early_size(tp);
6031 speed = rtl8152_get_speed(tp);
6032 rtl_set_ifg(tp, speed);
6034 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6035 if (speed & _2500bps)
6036 ocp_data &= ~IDLE_SPDWN_EN;
6038 ocp_data |= IDLE_SPDWN_EN;
6039 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
6041 if (tp->udev->speed == USB_SPEED_HIGH) {
6042 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6044 if (is_flow_control(speed))
6048 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6051 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6052 ocp_data &= ~FC_PATCH_TASK;
6053 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6054 usleep_range(1000, 2000);
6055 ocp_data |= FC_PATCH_TASK;
6056 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6058 return rtl_enable(tp);
6061 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
6067 if (autoneg == AUTONEG_DISABLE) {
6068 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
6073 bmcr = BMCR_SPEED10;
6074 if (duplex == DUPLEX_FULL) {
6075 bmcr |= BMCR_FULLDPLX;
6076 tp->ups_info.speed_duplex = FORCE_10M_FULL;
6078 tp->ups_info.speed_duplex = FORCE_10M_HALF;
6082 bmcr = BMCR_SPEED100;
6083 if (duplex == DUPLEX_FULL) {
6084 bmcr |= BMCR_FULLDPLX;
6085 tp->ups_info.speed_duplex = FORCE_100M_FULL;
6087 tp->ups_info.speed_duplex = FORCE_100M_HALF;
6091 if (tp->mii.supports_gmii) {
6092 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
6093 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6102 if (duplex == DUPLEX_FULL)
6103 tp->mii.full_duplex = 1;
6105 tp->mii.full_duplex = 0;
6107 tp->mii.force_media = 1;
6112 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6113 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6115 if (tp->mii.supports_gmii) {
6116 support |= RTL_ADVERTISED_1000_FULL;
6118 if (tp->support_2500full)
6119 support |= RTL_ADVERTISED_2500_FULL;
6122 if (!(advertising & support))
6125 orig = r8152_mdio_read(tp, MII_ADVERTISE);
6126 new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
6127 ADVERTISE_100HALF | ADVERTISE_100FULL);
6128 if (advertising & RTL_ADVERTISED_10_HALF) {
6129 new1 |= ADVERTISE_10HALF;
6130 tp->ups_info.speed_duplex = NWAY_10M_HALF;
6132 if (advertising & RTL_ADVERTISED_10_FULL) {
6133 new1 |= ADVERTISE_10FULL;
6134 tp->ups_info.speed_duplex = NWAY_10M_FULL;
6137 if (advertising & RTL_ADVERTISED_100_HALF) {
6138 new1 |= ADVERTISE_100HALF;
6139 tp->ups_info.speed_duplex = NWAY_100M_HALF;
6141 if (advertising & RTL_ADVERTISED_100_FULL) {
6142 new1 |= ADVERTISE_100FULL;
6143 tp->ups_info.speed_duplex = NWAY_100M_FULL;
6147 r8152_mdio_write(tp, MII_ADVERTISE, new1);
6148 tp->mii.advertising = new1;
6151 if (tp->mii.supports_gmii) {
6152 orig = r8152_mdio_read(tp, MII_CTRL1000);
6153 new1 = orig & ~(ADVERTISE_1000FULL |
6154 ADVERTISE_1000HALF);
6156 if (advertising & RTL_ADVERTISED_1000_FULL) {
6157 new1 |= ADVERTISE_1000FULL;
6158 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6162 r8152_mdio_write(tp, MII_CTRL1000, new1);
6165 if (tp->support_2500full) {
6166 orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
6167 new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
6169 if (advertising & RTL_ADVERTISED_2500_FULL) {
6170 new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
6171 tp->ups_info.speed_duplex = NWAY_2500M_FULL;
6175 ocp_reg_write(tp, OCP_10GBT_CTRL, new1);
6178 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
6180 tp->mii.force_media = 0;
6183 if (test_and_clear_bit(PHY_RESET, &tp->flags))
6186 r8152_mdio_write(tp, MII_BMCR, bmcr);
6188 if (bmcr & BMCR_RESET) {
6191 for (i = 0; i < 50; i++) {
6193 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
6202 static void rtl8152_up(struct r8152 *tp)
6204 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6207 r8152_aldps_en(tp, false);
6208 r8152b_exit_oob(tp);
6209 r8152_aldps_en(tp, true);
6212 static void rtl8152_down(struct r8152 *tp)
6214 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6215 rtl_drop_queued_tx(tp);
6219 r8152_power_cut_en(tp, false);
6220 r8152_aldps_en(tp, false);
6221 r8152b_enter_oob(tp);
6222 r8152_aldps_en(tp, true);
6225 static void rtl8153_up(struct r8152 *tp)
6229 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6232 r8153_u1u2en(tp, false);
6233 r8153_u2p3en(tp, false);
6234 r8153_aldps_en(tp, false);
6235 r8153_first_init(tp);
6237 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6238 ocp_data |= LANWAKE_CLR_EN;
6239 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6241 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6242 ocp_data &= ~LANWAKE_PIN;
6243 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
6245 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
6246 ocp_data &= ~DELAY_PHY_PWR_CHG;
6247 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
6249 r8153_aldps_en(tp, true);
6251 switch (tp->version) {
6258 r8153_u2p3en(tp, true);
6262 r8153_u1u2en(tp, true);
6265 static void rtl8153_down(struct r8152 *tp)
6269 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6270 rtl_drop_queued_tx(tp);
6274 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6275 ocp_data &= ~LANWAKE_CLR_EN;
6276 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6278 r8153_u1u2en(tp, false);
6279 r8153_u2p3en(tp, false);
6280 r8153_power_cut_en(tp, false);
6281 r8153_aldps_en(tp, false);
6282 r8153_enter_oob(tp);
6283 r8153_aldps_en(tp, true);
6286 static void rtl8153b_up(struct r8152 *tp)
6290 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6293 r8153b_u1u2en(tp, false);
6294 r8153_u2p3en(tp, false);
6295 r8153_aldps_en(tp, false);
6297 r8153_first_init(tp);
6298 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6300 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6301 ocp_data &= ~PLA_MCU_SPDWN_EN;
6302 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6304 r8153_aldps_en(tp, true);
6306 if (tp->udev->speed >= USB_SPEED_SUPER)
6307 r8153b_u1u2en(tp, true);
6310 static void rtl8153b_down(struct r8152 *tp)
6314 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6315 rtl_drop_queued_tx(tp);
6319 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6320 ocp_data |= PLA_MCU_SPDWN_EN;
6321 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6323 r8153b_u1u2en(tp, false);
6324 r8153_u2p3en(tp, false);
6325 r8153b_power_cut_en(tp, false);
6326 r8153_aldps_en(tp, false);
6327 r8153_enter_oob(tp);
6328 r8153_aldps_en(tp, true);
6331 static void rtl8153c_change_mtu(struct r8152 *tp)
6333 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
6334 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64);
6336 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6338 /* Adjust the tx fifo free credit full threshold, otherwise
6339 * the fifo would be too small to send a jumbo frame packet.
6341 if (tp->netdev->mtu < 8000)
6342 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8);
6344 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8);
6347 static void rtl8153c_up(struct r8152 *tp)
6351 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6354 r8153b_u1u2en(tp, false);
6355 r8153_u2p3en(tp, false);
6356 r8153_aldps_en(tp, false);
6358 rxdy_gated_en(tp, true);
6359 r8153_teredo_off(tp);
6361 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6362 ocp_data &= ~RCR_ACPT_ALL;
6363 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6365 rtl8152_nic_reset(tp);
6368 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6369 ocp_data &= ~NOW_IS_OOB;
6370 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6372 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6373 ocp_data &= ~MCU_BORW_EN;
6374 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6376 wait_oob_link_list_ready(tp);
6378 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6379 ocp_data |= RE_INIT_LL;
6380 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6382 wait_oob_link_list_ready(tp);
6384 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6386 rtl8153c_change_mtu(tp);
6388 rtl8152_nic_reset(tp);
6390 /* rx share fifo credit full threshold */
6391 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02);
6392 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08);
6393 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6394 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6396 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6398 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
6400 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
6402 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
6404 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
6406 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6407 ocp_data &= ~PLA_MCU_SPDWN_EN;
6408 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6410 r8153_aldps_en(tp, true);
6411 r8153b_u1u2en(tp, true);
6414 static inline u32 fc_pause_on_auto(struct r8152 *tp)
6416 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
6419 static inline u32 fc_pause_off_auto(struct r8152 *tp)
6421 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
6424 static void r8156_fc_parameter(struct r8152 *tp)
6426 u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
6427 u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
6429 switch (tp->version) {
6432 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 8);
6433 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 8);
6438 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16);
6439 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16);
6446 static void rtl8156_change_mtu(struct r8152 *tp)
6448 u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
6450 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size);
6451 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
6452 r8156_fc_parameter(tp);
6454 /* TX share fifo free credit full threshold */
6455 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6456 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
6457 ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
6460 static void rtl8156_up(struct r8152 *tp)
6464 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6467 r8153b_u1u2en(tp, false);
6468 r8153_u2p3en(tp, false);
6469 r8153_aldps_en(tp, false);
6471 rxdy_gated_en(tp, true);
6472 r8153_teredo_off(tp);
6474 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6475 ocp_data &= ~RCR_ACPT_ALL;
6476 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6478 rtl8152_nic_reset(tp);
6481 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6482 ocp_data &= ~NOW_IS_OOB;
6483 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6485 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6486 ocp_data &= ~MCU_BORW_EN;
6487 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6489 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6491 rtl8156_change_mtu(tp);
6493 switch (tp->version) {
6497 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
6498 ocp_data |= ACT_ODMA;
6499 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
6505 /* share FIFO settings */
6506 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
6507 ocp_data &= ~RXFIFO_FULL_MASK;
6509 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);
6511 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6512 ocp_data &= ~PLA_MCU_SPDWN_EN;
6513 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6515 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
6516 ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
6517 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);
6519 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);
6521 if (tp->saved_wolopts != __rtl_get_wol(tp)) {
6522 netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
6523 __rtl_set_wol(tp, tp->saved_wolopts);
6526 r8153_aldps_en(tp, true);
6527 r8153_u2p3en(tp, true);
6529 if (tp->udev->speed >= USB_SPEED_SUPER)
6530 r8153b_u1u2en(tp, true);
6533 static void rtl8156_down(struct r8152 *tp)
6537 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6538 rtl_drop_queued_tx(tp);
6542 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6543 ocp_data |= PLA_MCU_SPDWN_EN;
6544 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6546 r8153b_u1u2en(tp, false);
6547 r8153_u2p3en(tp, false);
6548 r8153b_power_cut_en(tp, false);
6549 r8153_aldps_en(tp, false);
6551 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6552 ocp_data &= ~NOW_IS_OOB;
6553 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6558 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
6559 * type. Set it to zero. bits[7:0] are the W1C bits about
6560 * the events. Set them to all 1 to clear them.
6562 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
6564 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6565 ocp_data |= NOW_IS_OOB;
6566 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6568 rtl_rx_vlan_en(tp, true);
6569 rxdy_gated_en(tp, false);
6571 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6572 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6573 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6575 r8153_aldps_en(tp, true);
6578 static bool rtl8152_in_nway(struct r8152 *tp)
6582 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
6583 tp->ocp_base = 0x2000;
6584 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
6585 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
6587 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
6588 if (nway_state & 0xc000)
6594 static bool rtl8153_in_nway(struct r8152 *tp)
6596 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
6598 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
6604 static void r8156_mdio_force_mode(struct r8152 *tp)
6608 /* Select force mode through 0xa5b4 bit 15
6609 * 0: MDIO force mode
6612 data = ocp_reg_read(tp, 0xa5b4);
6613 if (data & BIT(15)) {
6615 ocp_reg_write(tp, 0xa5b4, data);
6619 static void set_carrier(struct r8152 *tp)
6621 struct net_device *netdev = tp->netdev;
6622 struct napi_struct *napi = &tp->napi;
6625 speed = rtl8152_get_speed(tp);
6627 if (speed & LINK_STATUS) {
6628 if (!netif_carrier_ok(netdev)) {
6629 tp->rtl_ops.enable(tp);
6630 netif_stop_queue(netdev);
6632 netif_carrier_on(netdev);
6634 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6635 _rtl8152_set_rx_mode(netdev);
6637 netif_wake_queue(netdev);
6638 netif_info(tp, link, netdev, "carrier on\n");
6639 } else if (netif_queue_stopped(netdev) &&
6640 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
6641 netif_wake_queue(netdev);
6644 if (netif_carrier_ok(netdev)) {
6645 netif_carrier_off(netdev);
6646 tasklet_disable(&tp->tx_tl);
6648 tp->rtl_ops.disable(tp);
6650 tasklet_enable(&tp->tx_tl);
6651 netif_info(tp, link, netdev, "carrier off\n");
6656 static void rtl_work_func_t(struct work_struct *work)
6658 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
6660 /* If the device is unplugged or !netif_running(), the workqueue
6661 * doesn't need to wake the device, and could return directly.
6663 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
6666 if (usb_autopm_get_interface(tp->intf) < 0)
6669 if (!test_bit(WORK_ENABLE, &tp->flags))
6672 if (!mutex_trylock(&tp->control)) {
6673 schedule_delayed_work(&tp->schedule, 0);
6677 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
6680 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
6681 _rtl8152_set_rx_mode(tp->netdev);
6683 /* don't schedule tasket before linking */
6684 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
6685 netif_carrier_ok(tp->netdev))
6686 tasklet_schedule(&tp->tx_tl);
6688 if (test_and_clear_bit(RX_EPROTO, &tp->flags) &&
6689 !list_empty(&tp->rx_done))
6690 napi_schedule(&tp->napi);
6692 mutex_unlock(&tp->control);
6695 usb_autopm_put_interface(tp->intf);
6698 static void rtl_hw_phy_work_func_t(struct work_struct *work)
6700 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
6702 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6705 if (usb_autopm_get_interface(tp->intf) < 0)
6708 mutex_lock(&tp->control);
6710 if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
6711 tp->rtl_fw.retry = false;
6712 tp->rtl_fw.fw = NULL;
6714 /* Delay execution in case request_firmware() is not ready yet.
6716 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
6720 tp->rtl_ops.hw_phy_cfg(tp);
6722 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
6726 mutex_unlock(&tp->control);
6728 usb_autopm_put_interface(tp->intf);
6731 #ifdef CONFIG_PM_SLEEP
6732 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
6735 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
6738 case PM_HIBERNATION_PREPARE:
6739 case PM_SUSPEND_PREPARE:
6740 usb_autopm_get_interface(tp->intf);
6743 case PM_POST_HIBERNATION:
6744 case PM_POST_SUSPEND:
6745 usb_autopm_put_interface(tp->intf);
6748 case PM_POST_RESTORE:
6749 case PM_RESTORE_PREPARE:
6758 static int rtl8152_open(struct net_device *netdev)
6760 struct r8152 *tp = netdev_priv(netdev);
6763 if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
6764 cancel_delayed_work_sync(&tp->hw_phy_work);
6765 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
6768 res = alloc_all_mem(tp);
6772 res = usb_autopm_get_interface(tp->intf);
6776 mutex_lock(&tp->control);
6780 netif_carrier_off(netdev);
6781 netif_start_queue(netdev);
6782 set_bit(WORK_ENABLE, &tp->flags);
6784 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
6787 netif_device_detach(tp->netdev);
6788 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
6792 napi_enable(&tp->napi);
6793 tasklet_enable(&tp->tx_tl);
6795 mutex_unlock(&tp->control);
6797 usb_autopm_put_interface(tp->intf);
6798 #ifdef CONFIG_PM_SLEEP
6799 tp->pm_notifier.notifier_call = rtl_notifier;
6800 register_pm_notifier(&tp->pm_notifier);
6805 mutex_unlock(&tp->control);
6806 usb_autopm_put_interface(tp->intf);
6813 static int rtl8152_close(struct net_device *netdev)
6815 struct r8152 *tp = netdev_priv(netdev);
6818 #ifdef CONFIG_PM_SLEEP
6819 unregister_pm_notifier(&tp->pm_notifier);
6821 tasklet_disable(&tp->tx_tl);
6822 clear_bit(WORK_ENABLE, &tp->flags);
6823 usb_kill_urb(tp->intr_urb);
6824 cancel_delayed_work_sync(&tp->schedule);
6825 napi_disable(&tp->napi);
6826 netif_stop_queue(netdev);
6828 res = usb_autopm_get_interface(tp->intf);
6829 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
6830 rtl_drop_queued_tx(tp);
6833 mutex_lock(&tp->control);
6835 tp->rtl_ops.down(tp);
6837 mutex_unlock(&tp->control);
6841 usb_autopm_put_interface(tp->intf);
6848 static void rtl_tally_reset(struct r8152 *tp)
6852 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
6853 ocp_data |= TALLY_RESET;
6854 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
6857 static void r8152b_init(struct r8152 *tp)
6862 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6865 data = r8152_mdio_read(tp, MII_BMCR);
6866 if (data & BMCR_PDOWN) {
6867 data &= ~BMCR_PDOWN;
6868 r8152_mdio_write(tp, MII_BMCR, data);
6871 r8152_aldps_en(tp, false);
6873 if (tp->version == RTL_VER_01) {
6874 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
6875 ocp_data &= ~LED_MODE_MASK;
6876 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
6879 r8152_power_cut_en(tp, false);
6881 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
6882 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
6883 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
6884 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
6885 ocp_data &= ~MCU_CLK_RATIO_MASK;
6886 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
6887 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
6888 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
6889 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
6890 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
6892 rtl_tally_reset(tp);
6894 /* enable rx aggregation */
6895 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
6896 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
6897 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
6900 static void r8153_init(struct r8152 *tp)
6906 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6909 r8153_u1u2en(tp, false);
6911 for (i = 0; i < 500; i++) {
6912 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
6917 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6921 data = r8153_phy_status(tp, 0);
6923 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
6924 tp->version == RTL_VER_05)
6925 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
6927 data = r8152_mdio_read(tp, MII_BMCR);
6928 if (data & BMCR_PDOWN) {
6929 data &= ~BMCR_PDOWN;
6930 r8152_mdio_write(tp, MII_BMCR, data);
6933 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
6935 r8153_u2p3en(tp, false);
6937 if (tp->version == RTL_VER_04) {
6938 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
6939 ocp_data &= ~pwd_dn_scale_mask;
6940 ocp_data |= pwd_dn_scale(96);
6941 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
6943 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
6944 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
6945 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
6946 } else if (tp->version == RTL_VER_05) {
6947 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
6948 ocp_data &= ~ECM_ALDPS;
6949 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
6951 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
6952 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
6953 ocp_data &= ~DYNAMIC_BURST;
6955 ocp_data |= DYNAMIC_BURST;
6956 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
6957 } else if (tp->version == RTL_VER_06) {
6958 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
6959 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
6960 ocp_data &= ~DYNAMIC_BURST;
6962 ocp_data |= DYNAMIC_BURST;
6963 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
6965 r8153_queue_wake(tp, false);
6967 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
6968 if (rtl8152_get_speed(tp) & LINK_STATUS)
6969 ocp_data |= CUR_LINK_OK;
6971 ocp_data &= ~CUR_LINK_OK;
6972 ocp_data |= POLL_LINK_CHG;
6973 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
6976 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
6977 ocp_data |= EP4_FULL_FC;
6978 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
6980 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
6981 ocp_data &= ~TIMER11_EN;
6982 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
6984 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
6985 ocp_data &= ~LED_MODE_MASK;
6986 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
6988 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
6989 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
6990 ocp_data |= LPM_TIMER_500MS;
6992 ocp_data |= LPM_TIMER_500US;
6993 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
6995 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
6996 ocp_data &= ~SEN_VAL_MASK;
6997 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
6998 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
7000 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
7002 r8153_power_cut_en(tp, false);
7003 rtl_runtime_suspend_enable(tp, false);
7004 r8153_mac_clk_speed_down(tp, false);
7005 r8153_u1u2en(tp, true);
7006 usb_enable_lpm(tp->udev);
7008 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
7009 ocp_data |= LANWAKE_CLR_EN;
7010 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
7012 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
7013 ocp_data &= ~LANWAKE_PIN;
7014 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
7016 /* rx aggregation */
7017 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7018 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7019 if (tp->dell_tb_rx_agg_bug)
7020 ocp_data |= RX_AGG_DISABLE;
7022 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7024 rtl_tally_reset(tp);
7026 switch (tp->udev->speed) {
7027 case USB_SPEED_SUPER:
7028 case USB_SPEED_SUPER_PLUS:
7029 tp->coalesce = COALESCE_SUPER;
7031 case USB_SPEED_HIGH:
7032 tp->coalesce = COALESCE_HIGH;
7035 tp->coalesce = COALESCE_SLOW;
7040 static void r8153b_init(struct r8152 *tp)
7046 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7049 r8153b_u1u2en(tp, false);
7051 for (i = 0; i < 500; i++) {
7052 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7057 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7061 data = r8153_phy_status(tp, 0);
7063 data = r8152_mdio_read(tp, MII_BMCR);
7064 if (data & BMCR_PDOWN) {
7065 data &= ~BMCR_PDOWN;
7066 r8152_mdio_write(tp, MII_BMCR, data);
7069 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7071 r8153_u2p3en(tp, false);
7073 /* MSC timer = 0xfff * 8ms = 32760 ms */
7074 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7076 r8153b_power_cut_en(tp, false);
7077 r8153b_ups_en(tp, false);
7078 r8153_queue_wake(tp, false);
7079 rtl_runtime_suspend_enable(tp, false);
7081 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7082 if (rtl8152_get_speed(tp) & LINK_STATUS)
7083 ocp_data |= CUR_LINK_OK;
7085 ocp_data &= ~CUR_LINK_OK;
7086 ocp_data |= POLL_LINK_CHG;
7087 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7089 if (tp->udev->speed >= USB_SPEED_SUPER)
7090 r8153b_u1u2en(tp, true);
7092 usb_enable_lpm(tp->udev);
7094 /* MAC clock speed down */
7095 r8153_mac_clk_speed_down(tp, true);
7097 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7098 ocp_data &= ~PLA_MCU_SPDWN_EN;
7099 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
7101 if (tp->version == RTL_VER_09) {
7102 /* Disable Test IO for 32QFN */
7103 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
7104 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7105 ocp_data |= TEST_IO_OFF;
7106 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7110 set_bit(GREEN_ETHERNET, &tp->flags);
7112 /* rx aggregation */
7113 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7114 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7115 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7117 rtl_tally_reset(tp);
7119 tp->coalesce = 15000; /* 15 us */
7122 static void r8153c_init(struct r8152 *tp)
7128 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7131 r8153b_u1u2en(tp, false);
7133 /* Disable spi_en */
7134 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
7135 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
7136 ocp_data &= ~BIT(3);
7137 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
7138 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);
7140 ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);
7142 for (i = 0; i < 500; i++) {
7143 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7148 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7152 data = r8153_phy_status(tp, 0);
7154 data = r8152_mdio_read(tp, MII_BMCR);
7155 if (data & BMCR_PDOWN) {
7156 data &= ~BMCR_PDOWN;
7157 r8152_mdio_write(tp, MII_BMCR, data);
7160 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7162 r8153_u2p3en(tp, false);
7164 /* MSC timer = 0xfff * 8ms = 32760 ms */
7165 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7167 r8153b_power_cut_en(tp, false);
7168 r8153c_ups_en(tp, false);
7169 r8153_queue_wake(tp, false);
7170 rtl_runtime_suspend_enable(tp, false);
7172 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7173 if (rtl8152_get_speed(tp) & LINK_STATUS)
7174 ocp_data |= CUR_LINK_OK;
7176 ocp_data &= ~CUR_LINK_OK;
7178 ocp_data |= POLL_LINK_CHG;
7179 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7181 r8153b_u1u2en(tp, true);
7183 usb_enable_lpm(tp->udev);
7185 /* MAC clock speed down */
7186 r8153_mac_clk_speed_down(tp, true);
7188 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
7189 ocp_data &= ~BIT(7);
7190 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
7192 set_bit(GREEN_ETHERNET, &tp->flags);
7194 /* rx aggregation */
7195 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7196 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7197 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7199 rtl_tally_reset(tp);
7201 tp->coalesce = 15000; /* 15 us */
7204 static void r8156_hw_phy_cfg(struct r8152 *tp)
7209 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7210 if (ocp_data & PCUT_STATUS) {
7211 ocp_data &= ~PCUT_STATUS;
7212 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7215 data = r8153_phy_status(tp, 0);
7217 case PHY_STAT_EXT_INIT:
7218 rtl8152_apply_firmware(tp, true);
7220 data = ocp_reg_read(tp, 0xa468);
7221 data &= ~(BIT(3) | BIT(1));
7222 ocp_reg_write(tp, 0xa468, data);
7224 case PHY_STAT_LAN_ON:
7225 case PHY_STAT_PWRDN:
7227 rtl8152_apply_firmware(tp, false);
7231 /* disable ALDPS before updating the PHY parameters */
7232 r8153_aldps_en(tp, false);
7234 /* disable EEE before updating the PHY parameters */
7235 rtl_eee_enable(tp, false);
7237 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7238 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7240 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7241 ocp_data |= PFM_PWM_SWITCH;
7242 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7244 switch (tp->version) {
7246 data = ocp_reg_read(tp, 0xad40);
7248 data |= BIT(7) | BIT(2);
7249 ocp_reg_write(tp, 0xad40, data);
7251 data = ocp_reg_read(tp, 0xad4e);
7253 ocp_reg_write(tp, 0xad4e, data);
7254 data = ocp_reg_read(tp, 0xad16);
7257 ocp_reg_write(tp, 0xad16, data);
7258 data = ocp_reg_read(tp, 0xad32);
7261 ocp_reg_write(tp, 0xad32, data);
7262 data = ocp_reg_read(tp, 0xac08);
7263 data &= ~(BIT(12) | BIT(8));
7264 ocp_reg_write(tp, 0xac08, data);
7265 data = ocp_reg_read(tp, 0xac8a);
7266 data |= BIT(12) | BIT(13) | BIT(14);
7268 ocp_reg_write(tp, 0xac8a, data);
7269 data = ocp_reg_read(tp, 0xad18);
7271 ocp_reg_write(tp, 0xad18, data);
7272 data = ocp_reg_read(tp, 0xad1a);
7274 ocp_reg_write(tp, 0xad1a, data);
7275 data = ocp_reg_read(tp, 0xad1c);
7277 ocp_reg_write(tp, 0xad1c, data);
7279 data = sram_read(tp, 0x80ea);
7282 sram_write(tp, 0x80ea, data);
7283 data = sram_read(tp, 0x80eb);
7286 sram_write(tp, 0x80eb, data);
7287 data = sram_read(tp, 0x80f8);
7290 sram_write(tp, 0x80f8, data);
7291 data = sram_read(tp, 0x80f1);
7294 sram_write(tp, 0x80f1, data);
7296 data = sram_read(tp, 0x80fe);
7299 sram_write(tp, 0x80fe, data);
7300 data = sram_read(tp, 0x8102);
7303 sram_write(tp, 0x8102, data);
7304 data = sram_read(tp, 0x8015);
7307 sram_write(tp, 0x8015, data);
7308 data = sram_read(tp, 0x8100);
7311 sram_write(tp, 0x8100, data);
7312 data = sram_read(tp, 0x8014);
7315 sram_write(tp, 0x8014, data);
7316 data = sram_read(tp, 0x8016);
7319 sram_write(tp, 0x8016, data);
7320 data = sram_read(tp, 0x80dc);
7323 sram_write(tp, 0x80dc, data);
7324 data = sram_read(tp, 0x80df);
7326 sram_write(tp, 0x80df, data);
7327 data = sram_read(tp, 0x80e1);
7329 sram_write(tp, 0x80e1, data);
7331 data = ocp_reg_read(tp, 0xbf06);
7334 ocp_reg_write(tp, 0xbf06, data);
7336 sram_write(tp, 0x819f, 0xddb6);
7338 ocp_reg_write(tp, 0xbc34, 0x5555);
7339 data = ocp_reg_read(tp, 0xbf0a);
7342 ocp_reg_write(tp, 0xbf0a, data);
7344 data = ocp_reg_read(tp, 0xbd2c);
7346 ocp_reg_write(tp, 0xbd2c, data);
7349 data = ocp_reg_read(tp, 0xad16);
7351 ocp_reg_write(tp, 0xad16, data);
7352 data = ocp_reg_read(tp, 0xad32);
7355 ocp_reg_write(tp, 0xad32, data);
7356 data = ocp_reg_read(tp, 0xac08);
7357 data &= ~(BIT(12) | BIT(8));
7358 ocp_reg_write(tp, 0xac08, data);
7359 data = ocp_reg_read(tp, 0xacc0);
7362 ocp_reg_write(tp, 0xacc0, data);
7363 data = ocp_reg_read(tp, 0xad40);
7365 data |= BIT(6) | BIT(2);
7366 ocp_reg_write(tp, 0xad40, data);
7367 data = ocp_reg_read(tp, 0xac14);
7369 ocp_reg_write(tp, 0xac14, data);
7370 data = ocp_reg_read(tp, 0xac80);
7371 data &= ~(BIT(8) | BIT(9));
7372 ocp_reg_write(tp, 0xac80, data);
7373 data = ocp_reg_read(tp, 0xac5e);
7376 ocp_reg_write(tp, 0xac5e, data);
7377 ocp_reg_write(tp, 0xad4c, 0x00a8);
7378 ocp_reg_write(tp, 0xac5c, 0x01ff);
7379 data = ocp_reg_read(tp, 0xac8a);
7381 data |= BIT(4) | BIT(5);
7382 ocp_reg_write(tp, 0xac8a, data);
7383 ocp_reg_write(tp, 0xb87c, 0x8157);
7384 data = ocp_reg_read(tp, 0xb87e);
7387 ocp_reg_write(tp, 0xb87e, data);
7388 ocp_reg_write(tp, 0xb87c, 0x8159);
7389 data = ocp_reg_read(tp, 0xb87e);
7392 ocp_reg_write(tp, 0xb87e, data);
7395 ocp_reg_write(tp, 0xb87c, 0x80a2);
7396 ocp_reg_write(tp, 0xb87e, 0x0153);
7397 ocp_reg_write(tp, 0xb87c, 0x809c);
7398 ocp_reg_write(tp, 0xb87e, 0x0153);
7401 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
7403 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7404 ocp_data |= EN_XG_LIP | EN_G_LIP;
7405 ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7407 sram_write(tp, 0x8257, 0x020f); /* XG PLL */
7408 sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */
7410 if (rtl_phy_patch_request(tp, true, true))
7414 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7415 ocp_data |= EEE_SPDWN_EN;
7416 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7418 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7419 data &= ~(EN_EEE_100 | EN_EEE_1000);
7420 data |= EN_10M_CLKDIV;
7421 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7422 tp->ups_info._10m_ckdiv = true;
7423 tp->ups_info.eee_plloff_100 = false;
7424 tp->ups_info.eee_plloff_giga = false;
7426 data = ocp_reg_read(tp, OCP_POWER_CFG);
7427 data &= ~EEE_CLKDIV_EN;
7428 ocp_reg_write(tp, OCP_POWER_CFG, data);
7429 tp->ups_info.eee_ckdiv = false;
7431 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
7432 ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
7433 tp->ups_info._250m_ckdiv = false;
7435 rtl_phy_patch_request(tp, false, true);
7437 /* enable ADC Ibias Cal */
7438 data = ocp_reg_read(tp, 0xd068);
7440 ocp_reg_write(tp, 0xd068, data);
7442 /* enable Thermal Sensor */
7443 data = sram_read(tp, 0x81a2);
7445 sram_write(tp, 0x81a2, data);
7446 data = ocp_reg_read(tp, 0xb54c);
7449 ocp_reg_write(tp, 0xb54c, data);
7451 /* Nway 2.5G Lite */
7452 data = ocp_reg_read(tp, 0xa454);
7454 ocp_reg_write(tp, 0xa454, data);
7456 /* CS DSP solution */
7457 data = ocp_reg_read(tp, OCP_10GBT_CTRL);
7458 data |= RTL_ADV2_5G_F_R;
7459 ocp_reg_write(tp, OCP_10GBT_CTRL, data);
7460 data = ocp_reg_read(tp, 0xad4e);
7462 ocp_reg_write(tp, 0xad4e, data);
7463 data = ocp_reg_read(tp, 0xa86a);
7465 ocp_reg_write(tp, 0xa86a, data);
7468 if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
7469 (ocp_reg_read(tp, 0xd068) & BIT(1))) {
7472 data = ocp_reg_read(tp, 0xd068);
7474 data |= 0x1; /* p0 */
7475 ocp_reg_write(tp, 0xd068, data);
7476 swap_a = ocp_reg_read(tp, 0xd06a);
7478 data |= 0x18; /* p3 */
7479 ocp_reg_write(tp, 0xd068, data);
7480 swap_b = ocp_reg_read(tp, 0xd06a);
7481 data &= ~0x18; /* p0 */
7482 ocp_reg_write(tp, 0xd068, data);
7483 ocp_reg_write(tp, 0xd06a,
7484 (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7485 data |= 0x18; /* p3 */
7486 ocp_reg_write(tp, 0xd068, data);
7487 ocp_reg_write(tp, 0xd06a,
7488 (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7490 data |= 0x08; /* p1 */
7491 ocp_reg_write(tp, 0xd068, data);
7492 swap_a = ocp_reg_read(tp, 0xd06a);
7494 data |= 0x10; /* p2 */
7495 ocp_reg_write(tp, 0xd068, data);
7496 swap_b = ocp_reg_read(tp, 0xd06a);
7498 data |= 0x08; /* p1 */
7499 ocp_reg_write(tp, 0xd068, data);
7500 ocp_reg_write(tp, 0xd06a,
7501 (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7503 data |= 0x10; /* p2 */
7504 ocp_reg_write(tp, 0xd068, data);
7505 ocp_reg_write(tp, 0xd06a,
7506 (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7507 swap_a = ocp_reg_read(tp, 0xbd5a);
7508 swap_b = ocp_reg_read(tp, 0xbd5c);
7509 ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) |
7510 ((swap_b & 0x1f) << 8) |
7511 ((swap_b >> 8) & 0x1f));
7512 ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) |
7513 ((swap_a & 0x1f) << 8) |
7514 ((swap_a >> 8) & 0x1f));
7515 swap_a = ocp_reg_read(tp, 0xbc18);
7516 swap_b = ocp_reg_read(tp, 0xbc1a);
7517 ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) |
7518 ((swap_b & 0x1f) << 8) |
7519 ((swap_b >> 8) & 0x1f));
7520 ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) |
7521 ((swap_a & 0x1f) << 8) |
7522 ((swap_a >> 8) & 0x1f));
7529 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7531 data = ocp_reg_read(tp, 0xa428);
7533 ocp_reg_write(tp, 0xa428, data);
7534 data = ocp_reg_read(tp, 0xa5ea);
7536 ocp_reg_write(tp, 0xa5ea, data);
7537 tp->ups_info.lite_mode = 0;
7540 rtl_eee_enable(tp, true);
7542 r8153_aldps_en(tp, true);
7543 r8152b_enable_fc(tp);
7544 r8153_u2p3en(tp, true);
7546 set_bit(PHY_RESET, &tp->flags);
7549 static void r8156b_hw_phy_cfg(struct r8152 *tp)
7554 switch (tp->version) {
7556 ocp_reg_write(tp, 0xbf86, 0x9000);
7557 data = ocp_reg_read(tp, 0xc402);
7559 ocp_reg_write(tp, 0xc402, data);
7561 ocp_reg_write(tp, 0xc402, data);
7562 ocp_reg_write(tp, 0xbd86, 0x1010);
7563 ocp_reg_write(tp, 0xbd88, 0x1010);
7564 data = ocp_reg_read(tp, 0xbd4e);
7565 data &= ~(BIT(10) | BIT(11));
7567 ocp_reg_write(tp, 0xbd4e, data);
7568 data = ocp_reg_read(tp, 0xbf46);
7571 ocp_reg_write(tp, 0xbf46, data);
7575 r8156b_wait_loading_flash(tp);
7581 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7582 if (ocp_data & PCUT_STATUS) {
7583 ocp_data &= ~PCUT_STATUS;
7584 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7587 data = r8153_phy_status(tp, 0);
7589 case PHY_STAT_EXT_INIT:
7590 rtl8152_apply_firmware(tp, true);
7592 data = ocp_reg_read(tp, 0xa466);
7594 ocp_reg_write(tp, 0xa466, data);
7596 data = ocp_reg_read(tp, 0xa468);
7597 data &= ~(BIT(3) | BIT(1));
7598 ocp_reg_write(tp, 0xa468, data);
7600 case PHY_STAT_LAN_ON:
7601 case PHY_STAT_PWRDN:
7603 rtl8152_apply_firmware(tp, false);
7607 data = r8152_mdio_read(tp, MII_BMCR);
7608 if (data & BMCR_PDOWN) {
7609 data &= ~BMCR_PDOWN;
7610 r8152_mdio_write(tp, MII_BMCR, data);
7613 /* disable ALDPS before updating the PHY parameters */
7614 r8153_aldps_en(tp, false);
7616 /* disable EEE before updating the PHY parameters */
7617 rtl_eee_enable(tp, false);
7619 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7620 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7622 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7623 ocp_data |= PFM_PWM_SWITCH;
7624 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7626 switch (tp->version) {
7628 data = ocp_reg_read(tp, 0xbc08);
7629 data |= BIT(3) | BIT(2);
7630 ocp_reg_write(tp, 0xbc08, data);
7632 data = sram_read(tp, 0x8fff);
7635 sram_write(tp, 0x8fff, data);
7637 data = ocp_reg_read(tp, 0xacda);
7639 ocp_reg_write(tp, 0xacda, data);
7640 data = ocp_reg_read(tp, 0xacde);
7642 ocp_reg_write(tp, 0xacde, data);
7643 ocp_reg_write(tp, 0xac8c, 0x0ffc);
7644 ocp_reg_write(tp, 0xac46, 0xb7b4);
7645 ocp_reg_write(tp, 0xac50, 0x0fbc);
7646 ocp_reg_write(tp, 0xac3c, 0x9240);
7647 ocp_reg_write(tp, 0xac4e, 0x0db4);
7648 ocp_reg_write(tp, 0xacc6, 0x0707);
7649 ocp_reg_write(tp, 0xacc8, 0xa0d3);
7650 ocp_reg_write(tp, 0xad08, 0x0007);
7652 ocp_reg_write(tp, 0xb87c, 0x8560);
7653 ocp_reg_write(tp, 0xb87e, 0x19cc);
7654 ocp_reg_write(tp, 0xb87c, 0x8562);
7655 ocp_reg_write(tp, 0xb87e, 0x19cc);
7656 ocp_reg_write(tp, 0xb87c, 0x8564);
7657 ocp_reg_write(tp, 0xb87e, 0x19cc);
7658 ocp_reg_write(tp, 0xb87c, 0x8566);
7659 ocp_reg_write(tp, 0xb87e, 0x147d);
7660 ocp_reg_write(tp, 0xb87c, 0x8568);
7661 ocp_reg_write(tp, 0xb87e, 0x147d);
7662 ocp_reg_write(tp, 0xb87c, 0x856a);
7663 ocp_reg_write(tp, 0xb87e, 0x147d);
7664 ocp_reg_write(tp, 0xb87c, 0x8ffe);
7665 ocp_reg_write(tp, 0xb87e, 0x0907);
7666 ocp_reg_write(tp, 0xb87c, 0x80d6);
7667 ocp_reg_write(tp, 0xb87e, 0x2801);
7668 ocp_reg_write(tp, 0xb87c, 0x80f2);
7669 ocp_reg_write(tp, 0xb87e, 0x2801);
7670 ocp_reg_write(tp, 0xb87c, 0x80f4);
7671 ocp_reg_write(tp, 0xb87e, 0x6077);
7672 ocp_reg_write(tp, 0xb506, 0x01e7);
7674 ocp_reg_write(tp, 0xb87c, 0x8013);
7675 ocp_reg_write(tp, 0xb87e, 0x0700);
7676 ocp_reg_write(tp, 0xb87c, 0x8fb9);
7677 ocp_reg_write(tp, 0xb87e, 0x2801);
7678 ocp_reg_write(tp, 0xb87c, 0x8fba);
7679 ocp_reg_write(tp, 0xb87e, 0x0100);
7680 ocp_reg_write(tp, 0xb87c, 0x8fbc);
7681 ocp_reg_write(tp, 0xb87e, 0x1900);
7682 ocp_reg_write(tp, 0xb87c, 0x8fbe);
7683 ocp_reg_write(tp, 0xb87e, 0xe100);
7684 ocp_reg_write(tp, 0xb87c, 0x8fc0);
7685 ocp_reg_write(tp, 0xb87e, 0x0800);
7686 ocp_reg_write(tp, 0xb87c, 0x8fc2);
7687 ocp_reg_write(tp, 0xb87e, 0xe500);
7688 ocp_reg_write(tp, 0xb87c, 0x8fc4);
7689 ocp_reg_write(tp, 0xb87e, 0x0f00);
7690 ocp_reg_write(tp, 0xb87c, 0x8fc6);
7691 ocp_reg_write(tp, 0xb87e, 0xf100);
7692 ocp_reg_write(tp, 0xb87c, 0x8fc8);
7693 ocp_reg_write(tp, 0xb87e, 0x0400);
7694 ocp_reg_write(tp, 0xb87c, 0x8fca);
7695 ocp_reg_write(tp, 0xb87e, 0xf300);
7696 ocp_reg_write(tp, 0xb87c, 0x8fcc);
7697 ocp_reg_write(tp, 0xb87e, 0xfd00);
7698 ocp_reg_write(tp, 0xb87c, 0x8fce);
7699 ocp_reg_write(tp, 0xb87e, 0xff00);
7700 ocp_reg_write(tp, 0xb87c, 0x8fd0);
7701 ocp_reg_write(tp, 0xb87e, 0xfb00);
7702 ocp_reg_write(tp, 0xb87c, 0x8fd2);
7703 ocp_reg_write(tp, 0xb87e, 0x0100);
7704 ocp_reg_write(tp, 0xb87c, 0x8fd4);
7705 ocp_reg_write(tp, 0xb87e, 0xf400);
7706 ocp_reg_write(tp, 0xb87c, 0x8fd6);
7707 ocp_reg_write(tp, 0xb87e, 0xff00);
7708 ocp_reg_write(tp, 0xb87c, 0x8fd8);
7709 ocp_reg_write(tp, 0xb87e, 0xf600);
7711 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7712 ocp_data |= EN_XG_LIP | EN_G_LIP;
7713 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7714 ocp_reg_write(tp, 0xb87c, 0x813d);
7715 ocp_reg_write(tp, 0xb87e, 0x390e);
7716 ocp_reg_write(tp, 0xb87c, 0x814f);
7717 ocp_reg_write(tp, 0xb87e, 0x790e);
7718 ocp_reg_write(tp, 0xb87c, 0x80b0);
7719 ocp_reg_write(tp, 0xb87e, 0x0f31);
7720 data = ocp_reg_read(tp, 0xbf4c);
7722 ocp_reg_write(tp, 0xbf4c, data);
7723 data = ocp_reg_read(tp, 0xbcca);
7724 data |= BIT(9) | BIT(8);
7725 ocp_reg_write(tp, 0xbcca, data);
7726 ocp_reg_write(tp, 0xb87c, 0x8141);
7727 ocp_reg_write(tp, 0xb87e, 0x320e);
7728 ocp_reg_write(tp, 0xb87c, 0x8153);
7729 ocp_reg_write(tp, 0xb87e, 0x720e);
7730 ocp_reg_write(tp, 0xb87c, 0x8529);
7731 ocp_reg_write(tp, 0xb87e, 0x050e);
7732 data = ocp_reg_read(tp, OCP_EEE_CFG);
7733 data &= ~CTAP_SHORT_EN;
7734 ocp_reg_write(tp, OCP_EEE_CFG, data);
7736 sram_write(tp, 0x816c, 0xc4a0);
7737 sram_write(tp, 0x8170, 0xc4a0);
7738 sram_write(tp, 0x8174, 0x04a0);
7739 sram_write(tp, 0x8178, 0x04a0);
7740 sram_write(tp, 0x817c, 0x0719);
7741 sram_write(tp, 0x8ff4, 0x0400);
7742 sram_write(tp, 0x8ff1, 0x0404);
7744 ocp_reg_write(tp, 0xbf4a, 0x001b);
7745 ocp_reg_write(tp, 0xb87c, 0x8033);
7746 ocp_reg_write(tp, 0xb87e, 0x7c13);
7747 ocp_reg_write(tp, 0xb87c, 0x8037);
7748 ocp_reg_write(tp, 0xb87e, 0x7c13);
7749 ocp_reg_write(tp, 0xb87c, 0x803b);
7750 ocp_reg_write(tp, 0xb87e, 0xfc32);
7751 ocp_reg_write(tp, 0xb87c, 0x803f);
7752 ocp_reg_write(tp, 0xb87e, 0x7c13);
7753 ocp_reg_write(tp, 0xb87c, 0x8043);
7754 ocp_reg_write(tp, 0xb87e, 0x7c13);
7755 ocp_reg_write(tp, 0xb87c, 0x8047);
7756 ocp_reg_write(tp, 0xb87e, 0x7c13);
7758 ocp_reg_write(tp, 0xb87c, 0x8145);
7759 ocp_reg_write(tp, 0xb87e, 0x370e);
7760 ocp_reg_write(tp, 0xb87c, 0x8157);
7761 ocp_reg_write(tp, 0xb87e, 0x770e);
7762 ocp_reg_write(tp, 0xb87c, 0x8169);
7763 ocp_reg_write(tp, 0xb87e, 0x0d0a);
7764 ocp_reg_write(tp, 0xb87c, 0x817b);
7765 ocp_reg_write(tp, 0xb87e, 0x1d0a);
7767 data = sram_read(tp, 0x8217);
7770 sram_write(tp, 0x8217, data);
7771 data = sram_read(tp, 0x821a);
7774 sram_write(tp, 0x821a, data);
7775 sram_write(tp, 0x80da, 0x0403);
7776 data = sram_read(tp, 0x80dc);
7779 sram_write(tp, 0x80dc, data);
7780 sram_write(tp, 0x80b3, 0x0384);
7781 sram_write(tp, 0x80b7, 0x2007);
7782 data = sram_read(tp, 0x80ba);
7785 sram_write(tp, 0x80ba, data);
7786 sram_write(tp, 0x80b5, 0xf009);
7787 data = sram_read(tp, 0x80bd);
7790 sram_write(tp, 0x80bd, data);
7791 sram_write(tp, 0x80c7, 0xf083);
7792 sram_write(tp, 0x80dd, 0x03f0);
7793 data = sram_read(tp, 0x80df);
7796 sram_write(tp, 0x80df, data);
7797 sram_write(tp, 0x80cb, 0x2007);
7798 data = sram_read(tp, 0x80ce);
7801 sram_write(tp, 0x80ce, data);
7802 sram_write(tp, 0x80c9, 0x8009);
7803 data = sram_read(tp, 0x80d1);
7806 sram_write(tp, 0x80d1, data);
7807 sram_write(tp, 0x80a3, 0x200a);
7808 sram_write(tp, 0x80a5, 0xf0ad);
7809 sram_write(tp, 0x809f, 0x6073);
7810 sram_write(tp, 0x80a1, 0x000b);
7811 data = sram_read(tp, 0x80a9);
7814 sram_write(tp, 0x80a9, data);
7816 if (rtl_phy_patch_request(tp, true, true))
7819 data = ocp_reg_read(tp, 0xb896);
7821 ocp_reg_write(tp, 0xb896, data);
7822 data = ocp_reg_read(tp, 0xb892);
7824 ocp_reg_write(tp, 0xb892, data);
7825 ocp_reg_write(tp, 0xb88e, 0xc23e);
7826 ocp_reg_write(tp, 0xb890, 0x0000);
7827 ocp_reg_write(tp, 0xb88e, 0xc240);
7828 ocp_reg_write(tp, 0xb890, 0x0103);
7829 ocp_reg_write(tp, 0xb88e, 0xc242);
7830 ocp_reg_write(tp, 0xb890, 0x0507);
7831 ocp_reg_write(tp, 0xb88e, 0xc244);
7832 ocp_reg_write(tp, 0xb890, 0x090b);
7833 ocp_reg_write(tp, 0xb88e, 0xc246);
7834 ocp_reg_write(tp, 0xb890, 0x0c0e);
7835 ocp_reg_write(tp, 0xb88e, 0xc248);
7836 ocp_reg_write(tp, 0xb890, 0x1012);
7837 ocp_reg_write(tp, 0xb88e, 0xc24a);
7838 ocp_reg_write(tp, 0xb890, 0x1416);
7839 data = ocp_reg_read(tp, 0xb896);
7841 ocp_reg_write(tp, 0xb896, data);
7843 rtl_phy_patch_request(tp, false, true);
7845 data = ocp_reg_read(tp, 0xa86a);
7847 ocp_reg_write(tp, 0xa86a, data);
7848 data = ocp_reg_read(tp, 0xa6f0);
7850 ocp_reg_write(tp, 0xa6f0, data);
7852 ocp_reg_write(tp, 0xbfa0, 0xd70d);
7853 ocp_reg_write(tp, 0xbfa2, 0x4100);
7854 ocp_reg_write(tp, 0xbfa4, 0xe868);
7855 ocp_reg_write(tp, 0xbfa6, 0xdc59);
7856 ocp_reg_write(tp, 0xb54c, 0x3c18);
7857 data = ocp_reg_read(tp, 0xbfa4);
7859 ocp_reg_write(tp, 0xbfa4, data);
7860 data = sram_read(tp, 0x817d);
7862 sram_write(tp, 0x817d, data);
7866 data = ocp_reg_read(tp, 0xac46);
7869 ocp_reg_write(tp, 0xac46, data);
7870 data = ocp_reg_read(tp, 0xad30);
7873 ocp_reg_write(tp, 0xad30, data);
7877 ocp_reg_write(tp, 0xb87c, 0x80f5);
7878 ocp_reg_write(tp, 0xb87e, 0x760e);
7879 ocp_reg_write(tp, 0xb87c, 0x8107);
7880 ocp_reg_write(tp, 0xb87e, 0x360e);
7881 ocp_reg_write(tp, 0xb87c, 0x8551);
7882 data = ocp_reg_read(tp, 0xb87e);
7885 ocp_reg_write(tp, 0xb87e, data);
7887 /* ADC_PGA parameter */
7888 data = ocp_reg_read(tp, 0xbf00);
7891 ocp_reg_write(tp, 0xbf00, data);
7892 data = ocp_reg_read(tp, 0xbf46);
7895 ocp_reg_write(tp, 0xbf46, data);
7897 /* Green Table-PGA, 1G full viterbi */
7898 sram_write(tp, 0x8044, 0x2417);
7899 sram_write(tp, 0x804a, 0x2417);
7900 sram_write(tp, 0x8050, 0x2417);
7901 sram_write(tp, 0x8056, 0x2417);
7902 sram_write(tp, 0x805c, 0x2417);
7903 sram_write(tp, 0x8062, 0x2417);
7904 sram_write(tp, 0x8068, 0x2417);
7905 sram_write(tp, 0x806e, 0x2417);
7906 sram_write(tp, 0x8074, 0x2417);
7907 sram_write(tp, 0x807a, 0x2417);
7910 data = ocp_reg_read(tp, 0xbf84);
7913 ocp_reg_write(tp, 0xbf84, data);
7919 if (rtl_phy_patch_request(tp, true, true))
7922 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7923 ocp_data |= EEE_SPDWN_EN;
7924 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7926 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7927 data &= ~(EN_EEE_100 | EN_EEE_1000);
7928 data |= EN_10M_CLKDIV;
7929 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7930 tp->ups_info._10m_ckdiv = true;
7931 tp->ups_info.eee_plloff_100 = false;
7932 tp->ups_info.eee_plloff_giga = false;
7934 data = ocp_reg_read(tp, OCP_POWER_CFG);
7935 data &= ~EEE_CLKDIV_EN;
7936 ocp_reg_write(tp, OCP_POWER_CFG, data);
7937 tp->ups_info.eee_ckdiv = false;
7939 rtl_phy_patch_request(tp, false, true);
7941 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7943 data = ocp_reg_read(tp, 0xa428);
7945 ocp_reg_write(tp, 0xa428, data);
7946 data = ocp_reg_read(tp, 0xa5ea);
7948 ocp_reg_write(tp, 0xa5ea, data);
7949 tp->ups_info.lite_mode = 0;
7952 rtl_eee_enable(tp, true);
7954 r8153_aldps_en(tp, true);
7955 r8152b_enable_fc(tp);
7956 r8153_u2p3en(tp, true);
7958 set_bit(PHY_RESET, &tp->flags);
7961 static void r8156_init(struct r8152 *tp)
7967 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7970 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
7971 ocp_data &= ~EN_ALL_SPEED;
7972 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
7974 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
7976 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
7977 ocp_data |= BYPASS_MAC_RESET;
7978 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
7980 r8153b_u1u2en(tp, false);
7982 for (i = 0; i < 500; i++) {
7983 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7988 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7992 data = r8153_phy_status(tp, 0);
7993 if (data == PHY_STAT_EXT_INIT) {
7994 data = ocp_reg_read(tp, 0xa468);
7995 data &= ~(BIT(3) | BIT(1));
7996 ocp_reg_write(tp, 0xa468, data);
7999 data = r8152_mdio_read(tp, MII_BMCR);
8000 if (data & BMCR_PDOWN) {
8001 data &= ~BMCR_PDOWN;
8002 r8152_mdio_write(tp, MII_BMCR, data);
8005 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8006 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
8008 r8153_u2p3en(tp, false);
8010 /* MSC timer = 0xfff * 8ms = 32760 ms */
8011 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
8013 /* U1/U2/L1 idle timer. 500 us */
8014 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
8016 r8153b_power_cut_en(tp, false);
8017 r8156_ups_en(tp, false);
8018 r8153_queue_wake(tp, false);
8019 rtl_runtime_suspend_enable(tp, false);
8021 if (tp->udev->speed >= USB_SPEED_SUPER)
8022 r8153b_u1u2en(tp, true);
8024 usb_enable_lpm(tp->udev);
8026 r8156_mac_clk_spd(tp, true);
8028 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8029 ocp_data &= ~PLA_MCU_SPDWN_EN;
8030 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8032 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8033 if (rtl8152_get_speed(tp) & LINK_STATUS)
8034 ocp_data |= CUR_LINK_OK;
8036 ocp_data &= ~CUR_LINK_OK;
8037 ocp_data |= POLL_LINK_CHG;
8038 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8040 set_bit(GREEN_ETHERNET, &tp->flags);
8042 /* rx aggregation */
8043 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8044 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8045 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8047 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
8048 ocp_data |= ACT_ODMA;
8049 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
8051 r8156_mdio_force_mode(tp);
8052 rtl_tally_reset(tp);
8054 tp->coalesce = 15000; /* 15 us */
8057 static void r8156b_init(struct r8152 *tp)
8063 if (test_bit(RTL8152_UNPLUG, &tp->flags))
8066 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8067 ocp_data &= ~EN_ALL_SPEED;
8068 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
8070 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
8072 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8073 ocp_data |= BYPASS_MAC_RESET;
8074 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
8076 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
8077 ocp_data |= RX_DETECT8;
8078 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
8080 r8153b_u1u2en(tp, false);
8082 switch (tp->version) {
8085 r8156b_wait_loading_flash(tp);
8091 for (i = 0; i < 500; i++) {
8092 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8097 if (test_bit(RTL8152_UNPLUG, &tp->flags))
8101 data = r8153_phy_status(tp, 0);
8102 if (data == PHY_STAT_EXT_INIT) {
8103 data = ocp_reg_read(tp, 0xa468);
8104 data &= ~(BIT(3) | BIT(1));
8105 ocp_reg_write(tp, 0xa468, data);
8107 data = ocp_reg_read(tp, 0xa466);
8109 ocp_reg_write(tp, 0xa466, data);
8112 data = r8152_mdio_read(tp, MII_BMCR);
8113 if (data & BMCR_PDOWN) {
8114 data &= ~BMCR_PDOWN;
8115 r8152_mdio_write(tp, MII_BMCR, data);
8118 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8120 r8153_u2p3en(tp, false);
8122 /* MSC timer = 0xfff * 8ms = 32760 ms */
8123 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
8125 /* U1/U2/L1 idle timer. 500 us */
8126 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
8128 r8153b_power_cut_en(tp, false);
8129 r8156_ups_en(tp, false);
8130 r8153_queue_wake(tp, false);
8131 rtl_runtime_suspend_enable(tp, false);
8133 if (tp->udev->speed >= USB_SPEED_SUPER)
8134 r8153b_u1u2en(tp, true);
8136 usb_enable_lpm(tp->udev);
8138 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
8139 ocp_data &= ~SLOT_EN;
8140 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8142 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
8143 ocp_data |= FLOW_CTRL_EN;
8144 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
8146 /* enable fc timer and set timer to 600 ms. */
8147 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
8148 CTRL_TIMER_EN | (600 / 8));
8150 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
8151 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
8152 ocp_data |= FLOW_CTRL_PATCH_2;
8153 ocp_data &= ~AUTO_SPEEDUP;
8154 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
8156 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
8157 ocp_data |= FC_PATCH_TASK;
8158 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
8160 r8156_mac_clk_spd(tp, true);
8162 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8163 ocp_data &= ~PLA_MCU_SPDWN_EN;
8164 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8166 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8167 if (rtl8152_get_speed(tp) & LINK_STATUS)
8168 ocp_data |= CUR_LINK_OK;
8170 ocp_data &= ~CUR_LINK_OK;
8171 ocp_data |= POLL_LINK_CHG;
8172 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8174 set_bit(GREEN_ETHERNET, &tp->flags);
8176 /* rx aggregation */
8177 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8178 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8179 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8181 r8156_mdio_force_mode(tp);
8182 rtl_tally_reset(tp);
8184 tp->coalesce = 15000; /* 15 us */
8187 static bool rtl_check_vendor_ok(struct usb_interface *intf)
8189 struct usb_host_interface *alt = intf->cur_altsetting;
8190 struct usb_endpoint_descriptor *in, *out, *intr;
8192 if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) {
8193 dev_err(&intf->dev, "Expected endpoints are not found\n");
8197 /* Check Rx endpoint address */
8198 if (usb_endpoint_num(in) != 1) {
8199 dev_err(&intf->dev, "Invalid Rx endpoint address\n");
8203 /* Check Tx endpoint address */
8204 if (usb_endpoint_num(out) != 2) {
8205 dev_err(&intf->dev, "Invalid Tx endpoint address\n");
8209 /* Check interrupt endpoint address */
8210 if (usb_endpoint_num(intr) != 3) {
8211 dev_err(&intf->dev, "Invalid interrupt endpoint address\n");
8218 static bool rtl_vendor_mode(struct usb_interface *intf)
8220 struct usb_host_interface *alt = intf->cur_altsetting;
8221 struct usb_device *udev;
8222 struct usb_host_config *c;
8225 if (alt->desc.bInterfaceClass == USB_CLASS_VENDOR_SPEC)
8226 return rtl_check_vendor_ok(intf);
8228 /* The vendor mode is not always config #1, so to find it out. */
8229 udev = interface_to_usbdev(intf);
8231 num_configs = udev->descriptor.bNumConfigurations;
8232 if (num_configs < 2)
8235 for (i = 0; i < num_configs; (i++, c++)) {
8236 struct usb_interface_descriptor *desc = NULL;
8238 if (c->desc.bNumInterfaces > 0)
8239 desc = &c->intf_cache[0]->altsetting->desc;
8243 if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) {
8244 usb_driver_set_configuration(udev, c->desc.bConfigurationValue);
8249 if (i == num_configs)
8250 dev_err(&intf->dev, "Unexpected Device\n");
8255 static int rtl8152_pre_reset(struct usb_interface *intf)
8257 struct r8152 *tp = usb_get_intfdata(intf);
8258 struct net_device *netdev;
8263 netdev = tp->netdev;
8264 if (!netif_running(netdev))
8267 netif_stop_queue(netdev);
8268 tasklet_disable(&tp->tx_tl);
8269 clear_bit(WORK_ENABLE, &tp->flags);
8270 usb_kill_urb(tp->intr_urb);
8271 cancel_delayed_work_sync(&tp->schedule);
8272 napi_disable(&tp->napi);
8273 if (netif_carrier_ok(netdev)) {
8274 mutex_lock(&tp->control);
8275 tp->rtl_ops.disable(tp);
8276 mutex_unlock(&tp->control);
8282 static int rtl8152_post_reset(struct usb_interface *intf)
8284 struct r8152 *tp = usb_get_intfdata(intf);
8285 struct net_device *netdev;
8291 /* reset the MAC address in case of policy change */
8292 if (determine_ethernet_addr(tp, &sa) >= 0) {
8294 dev_set_mac_address (tp->netdev, &sa, NULL);
8298 netdev = tp->netdev;
8299 if (!netif_running(netdev))
8302 set_bit(WORK_ENABLE, &tp->flags);
8303 if (netif_carrier_ok(netdev)) {
8304 mutex_lock(&tp->control);
8305 tp->rtl_ops.enable(tp);
8307 _rtl8152_set_rx_mode(netdev);
8308 mutex_unlock(&tp->control);
8311 napi_enable(&tp->napi);
8312 tasklet_enable(&tp->tx_tl);
8313 netif_wake_queue(netdev);
8314 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
8316 if (!list_empty(&tp->rx_done))
8317 napi_schedule(&tp->napi);
8322 static bool delay_autosuspend(struct r8152 *tp)
8324 bool sw_linking = !!netif_carrier_ok(tp->netdev);
8325 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
8327 /* This means a linking change occurs and the driver doesn't detect it,
8328 * yet. If the driver has disabled tx/rx and hw is linking on, the
8329 * device wouldn't wake up by receiving any packet.
8331 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
8334 /* If the linking down is occurred by nway, the device may miss the
8335 * linking change event. And it wouldn't wake when linking on.
8337 if (!sw_linking && tp->rtl_ops.in_nway(tp))
8339 else if (!skb_queue_empty(&tp->tx_queue))
8345 static int rtl8152_runtime_resume(struct r8152 *tp)
8347 struct net_device *netdev = tp->netdev;
8349 if (netif_running(netdev) && netdev->flags & IFF_UP) {
8350 struct napi_struct *napi = &tp->napi;
8352 tp->rtl_ops.autosuspend_en(tp, false);
8354 set_bit(WORK_ENABLE, &tp->flags);
8356 if (netif_carrier_ok(netdev)) {
8357 if (rtl8152_get_speed(tp) & LINK_STATUS) {
8360 netif_carrier_off(netdev);
8361 tp->rtl_ops.disable(tp);
8362 netif_info(tp, link, netdev, "linking down\n");
8367 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8368 smp_mb__after_atomic();
8370 if (!list_empty(&tp->rx_done))
8371 napi_schedule(&tp->napi);
8373 usb_submit_urb(tp->intr_urb, GFP_NOIO);
8375 if (netdev->flags & IFF_UP)
8376 tp->rtl_ops.autosuspend_en(tp, false);
8378 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8384 static int rtl8152_system_resume(struct r8152 *tp)
8386 struct net_device *netdev = tp->netdev;
8388 netif_device_attach(netdev);
8390 if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
8392 netif_carrier_off(netdev);
8393 set_bit(WORK_ENABLE, &tp->flags);
8394 usb_submit_urb(tp->intr_urb, GFP_NOIO);
8400 static int rtl8152_runtime_suspend(struct r8152 *tp)
8402 struct net_device *netdev = tp->netdev;
8405 if (!tp->rtl_ops.autosuspend_en)
8408 set_bit(SELECTIVE_SUSPEND, &tp->flags);
8409 smp_mb__after_atomic();
8411 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8414 if (netif_carrier_ok(netdev)) {
8417 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
8418 ocp_data = rcr & ~RCR_ACPT_ALL;
8419 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8420 rxdy_gated_en(tp, true);
8421 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
8423 if (!(ocp_data & RXFIFO_EMPTY)) {
8424 rxdy_gated_en(tp, false);
8425 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8426 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8427 smp_mb__after_atomic();
8433 clear_bit(WORK_ENABLE, &tp->flags);
8434 usb_kill_urb(tp->intr_urb);
8436 tp->rtl_ops.autosuspend_en(tp, true);
8438 if (netif_carrier_ok(netdev)) {
8439 struct napi_struct *napi = &tp->napi;
8443 rxdy_gated_en(tp, false);
8444 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8448 if (delay_autosuspend(tp)) {
8449 rtl8152_runtime_resume(tp);
8458 static int rtl8152_system_suspend(struct r8152 *tp)
8460 struct net_device *netdev = tp->netdev;
8462 netif_device_detach(netdev);
8464 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8465 struct napi_struct *napi = &tp->napi;
8467 clear_bit(WORK_ENABLE, &tp->flags);
8468 usb_kill_urb(tp->intr_urb);
8469 tasklet_disable(&tp->tx_tl);
8471 cancel_delayed_work_sync(&tp->schedule);
8472 tp->rtl_ops.down(tp);
8474 tasklet_enable(&tp->tx_tl);
8480 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
8482 struct r8152 *tp = usb_get_intfdata(intf);
8485 mutex_lock(&tp->control);
8487 if (PMSG_IS_AUTO(message))
8488 ret = rtl8152_runtime_suspend(tp);
8490 ret = rtl8152_system_suspend(tp);
8492 mutex_unlock(&tp->control);
8497 static int rtl8152_resume(struct usb_interface *intf)
8499 struct r8152 *tp = usb_get_intfdata(intf);
8502 mutex_lock(&tp->control);
8504 rtl_reset_ocp_base(tp);
8506 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
8507 ret = rtl8152_runtime_resume(tp);
8509 ret = rtl8152_system_resume(tp);
8511 mutex_unlock(&tp->control);
8516 static int rtl8152_reset_resume(struct usb_interface *intf)
8518 struct r8152 *tp = usb_get_intfdata(intf);
8520 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8521 rtl_reset_ocp_base(tp);
8522 tp->rtl_ops.init(tp);
8523 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
8524 set_ethernet_addr(tp, true);
8525 return rtl8152_resume(intf);
8528 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8530 struct r8152 *tp = netdev_priv(dev);
8532 if (usb_autopm_get_interface(tp->intf) < 0)
8535 if (!rtl_can_wakeup(tp)) {
8539 mutex_lock(&tp->control);
8540 wol->supported = WAKE_ANY;
8541 wol->wolopts = __rtl_get_wol(tp);
8542 mutex_unlock(&tp->control);
8545 usb_autopm_put_interface(tp->intf);
8548 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8550 struct r8152 *tp = netdev_priv(dev);
8553 if (!rtl_can_wakeup(tp))
8556 if (wol->wolopts & ~WAKE_ANY)
8559 ret = usb_autopm_get_interface(tp->intf);
8563 mutex_lock(&tp->control);
8565 __rtl_set_wol(tp, wol->wolopts);
8566 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
8568 mutex_unlock(&tp->control);
8570 usb_autopm_put_interface(tp->intf);
8576 static u32 rtl8152_get_msglevel(struct net_device *dev)
8578 struct r8152 *tp = netdev_priv(dev);
8580 return tp->msg_enable;
8583 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
8585 struct r8152 *tp = netdev_priv(dev);
8587 tp->msg_enable = value;
8590 static void rtl8152_get_drvinfo(struct net_device *netdev,
8591 struct ethtool_drvinfo *info)
8593 struct r8152 *tp = netdev_priv(netdev);
8595 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
8596 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
8597 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
8598 if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
8599 strlcpy(info->fw_version, tp->rtl_fw.version,
8600 sizeof(info->fw_version));
8604 int rtl8152_get_link_ksettings(struct net_device *netdev,
8605 struct ethtool_link_ksettings *cmd)
8607 struct r8152 *tp = netdev_priv(netdev);
8610 if (!tp->mii.mdio_read)
8613 ret = usb_autopm_get_interface(tp->intf);
8617 mutex_lock(&tp->control);
8619 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
8621 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8622 cmd->link_modes.supported, tp->support_2500full);
8624 if (tp->support_2500full) {
8625 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8626 cmd->link_modes.advertising,
8627 ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
8629 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8630 cmd->link_modes.lp_advertising,
8631 ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
8633 if (is_speed_2500(rtl8152_get_speed(tp)))
8634 cmd->base.speed = SPEED_2500;
8637 mutex_unlock(&tp->control);
8639 usb_autopm_put_interface(tp->intf);
8645 static int rtl8152_set_link_ksettings(struct net_device *dev,
8646 const struct ethtool_link_ksettings *cmd)
8648 struct r8152 *tp = netdev_priv(dev);
8649 u32 advertising = 0;
8652 ret = usb_autopm_get_interface(tp->intf);
8656 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
8657 cmd->link_modes.advertising))
8658 advertising |= RTL_ADVERTISED_10_HALF;
8660 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
8661 cmd->link_modes.advertising))
8662 advertising |= RTL_ADVERTISED_10_FULL;
8664 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
8665 cmd->link_modes.advertising))
8666 advertising |= RTL_ADVERTISED_100_HALF;
8668 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
8669 cmd->link_modes.advertising))
8670 advertising |= RTL_ADVERTISED_100_FULL;
8672 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
8673 cmd->link_modes.advertising))
8674 advertising |= RTL_ADVERTISED_1000_HALF;
8676 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
8677 cmd->link_modes.advertising))
8678 advertising |= RTL_ADVERTISED_1000_FULL;
8680 if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8681 cmd->link_modes.advertising))
8682 advertising |= RTL_ADVERTISED_2500_FULL;
8684 mutex_lock(&tp->control);
8686 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
8687 cmd->base.duplex, advertising);
8689 tp->autoneg = cmd->base.autoneg;
8690 tp->speed = cmd->base.speed;
8691 tp->duplex = cmd->base.duplex;
8692 tp->advertising = advertising;
8695 mutex_unlock(&tp->control);
8697 usb_autopm_put_interface(tp->intf);
8703 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
8710 "tx_single_collisions",
8711 "tx_multi_collisions",
8719 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
8723 return ARRAY_SIZE(rtl8152_gstrings);
8729 static void rtl8152_get_ethtool_stats(struct net_device *dev,
8730 struct ethtool_stats *stats, u64 *data)
8732 struct r8152 *tp = netdev_priv(dev);
8733 struct tally_counter tally;
8735 if (usb_autopm_get_interface(tp->intf) < 0)
8738 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
8740 usb_autopm_put_interface(tp->intf);
8742 data[0] = le64_to_cpu(tally.tx_packets);
8743 data[1] = le64_to_cpu(tally.rx_packets);
8744 data[2] = le64_to_cpu(tally.tx_errors);
8745 data[3] = le32_to_cpu(tally.rx_errors);
8746 data[4] = le16_to_cpu(tally.rx_missed);
8747 data[5] = le16_to_cpu(tally.align_errors);
8748 data[6] = le32_to_cpu(tally.tx_one_collision);
8749 data[7] = le32_to_cpu(tally.tx_multi_collision);
8750 data[8] = le64_to_cpu(tally.rx_unicast);
8751 data[9] = le64_to_cpu(tally.rx_broadcast);
8752 data[10] = le32_to_cpu(tally.rx_multicast);
8753 data[11] = le16_to_cpu(tally.tx_aborted);
8754 data[12] = le16_to_cpu(tally.tx_underrun);
8757 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
8759 switch (stringset) {
8761 memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
8766 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8768 u32 lp, adv, supported = 0;
8771 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
8772 supported = mmd_eee_cap_to_ethtool_sup_t(val);
8774 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
8775 adv = mmd_eee_adv_to_ethtool_adv_t(val);
8777 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
8778 lp = mmd_eee_adv_to_ethtool_adv_t(val);
8780 eee->eee_enabled = tp->eee_en;
8781 eee->eee_active = !!(supported & adv & lp);
8782 eee->supported = supported;
8783 eee->advertised = tp->eee_adv;
8784 eee->lp_advertised = lp;
8789 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
8791 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
8793 tp->eee_en = eee->eee_enabled;
8796 rtl_eee_enable(tp, tp->eee_en);
8801 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8803 u32 lp, adv, supported = 0;
8806 val = ocp_reg_read(tp, OCP_EEE_ABLE);
8807 supported = mmd_eee_cap_to_ethtool_sup_t(val);
8809 val = ocp_reg_read(tp, OCP_EEE_ADV);
8810 adv = mmd_eee_adv_to_ethtool_adv_t(val);
8812 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
8813 lp = mmd_eee_adv_to_ethtool_adv_t(val);
8815 eee->eee_enabled = tp->eee_en;
8816 eee->eee_active = !!(supported & adv & lp);
8817 eee->supported = supported;
8818 eee->advertised = tp->eee_adv;
8819 eee->lp_advertised = lp;
8825 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
8827 struct r8152 *tp = netdev_priv(net);
8830 if (!tp->rtl_ops.eee_get) {
8835 ret = usb_autopm_get_interface(tp->intf);
8839 mutex_lock(&tp->control);
8841 ret = tp->rtl_ops.eee_get(tp, edata);
8843 mutex_unlock(&tp->control);
8845 usb_autopm_put_interface(tp->intf);
8852 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
8854 struct r8152 *tp = netdev_priv(net);
8857 if (!tp->rtl_ops.eee_set) {
8862 ret = usb_autopm_get_interface(tp->intf);
8866 mutex_lock(&tp->control);
8868 ret = tp->rtl_ops.eee_set(tp, edata);
8870 ret = mii_nway_restart(&tp->mii);
8872 mutex_unlock(&tp->control);
8874 usb_autopm_put_interface(tp->intf);
8880 static int rtl8152_nway_reset(struct net_device *dev)
8882 struct r8152 *tp = netdev_priv(dev);
8885 ret = usb_autopm_get_interface(tp->intf);
8889 mutex_lock(&tp->control);
8891 ret = mii_nway_restart(&tp->mii);
8893 mutex_unlock(&tp->control);
8895 usb_autopm_put_interface(tp->intf);
8901 static int rtl8152_get_coalesce(struct net_device *netdev,
8902 struct ethtool_coalesce *coalesce,
8903 struct kernel_ethtool_coalesce *kernel_coal,
8904 struct netlink_ext_ack *extack)
8906 struct r8152 *tp = netdev_priv(netdev);
8908 switch (tp->version) {
8917 coalesce->rx_coalesce_usecs = tp->coalesce;
8922 static int rtl8152_set_coalesce(struct net_device *netdev,
8923 struct ethtool_coalesce *coalesce,
8924 struct kernel_ethtool_coalesce *kernel_coal,
8925 struct netlink_ext_ack *extack)
8927 struct r8152 *tp = netdev_priv(netdev);
8930 switch (tp->version) {
8939 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
8942 ret = usb_autopm_get_interface(tp->intf);
8946 mutex_lock(&tp->control);
8948 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
8949 tp->coalesce = coalesce->rx_coalesce_usecs;
8951 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
8952 netif_stop_queue(netdev);
8953 napi_disable(&tp->napi);
8954 tp->rtl_ops.disable(tp);
8955 tp->rtl_ops.enable(tp);
8957 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
8958 _rtl8152_set_rx_mode(netdev);
8959 napi_enable(&tp->napi);
8960 netif_wake_queue(netdev);
8964 mutex_unlock(&tp->control);
8966 usb_autopm_put_interface(tp->intf);
8971 static int rtl8152_get_tunable(struct net_device *netdev,
8972 const struct ethtool_tunable *tunable, void *d)
8974 struct r8152 *tp = netdev_priv(netdev);
8976 switch (tunable->id) {
8977 case ETHTOOL_RX_COPYBREAK:
8978 *(u32 *)d = tp->rx_copybreak;
8987 static int rtl8152_set_tunable(struct net_device *netdev,
8988 const struct ethtool_tunable *tunable,
8991 struct r8152 *tp = netdev_priv(netdev);
8994 switch (tunable->id) {
8995 case ETHTOOL_RX_COPYBREAK:
8997 if (val < ETH_ZLEN) {
8998 netif_err(tp, rx_err, netdev,
8999 "Invalid rx copy break value\n");
9003 if (tp->rx_copybreak != val) {
9004 if (netdev->flags & IFF_UP) {
9005 mutex_lock(&tp->control);
9006 napi_disable(&tp->napi);
9007 tp->rx_copybreak = val;
9008 napi_enable(&tp->napi);
9009 mutex_unlock(&tp->control);
9011 tp->rx_copybreak = val;
9022 static void rtl8152_get_ringparam(struct net_device *netdev,
9023 struct ethtool_ringparam *ring,
9024 struct kernel_ethtool_ringparam *kernel_ring,
9025 struct netlink_ext_ack *extack)
9027 struct r8152 *tp = netdev_priv(netdev);
9029 ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
9030 ring->rx_pending = tp->rx_pending;
9033 static int rtl8152_set_ringparam(struct net_device *netdev,
9034 struct ethtool_ringparam *ring,
9035 struct kernel_ethtool_ringparam *kernel_ring,
9036 struct netlink_ext_ack *extack)
9038 struct r8152 *tp = netdev_priv(netdev);
9040 if (ring->rx_pending < (RTL8152_MAX_RX * 2))
9043 if (tp->rx_pending != ring->rx_pending) {
9044 if (netdev->flags & IFF_UP) {
9045 mutex_lock(&tp->control);
9046 napi_disable(&tp->napi);
9047 tp->rx_pending = ring->rx_pending;
9048 napi_enable(&tp->napi);
9049 mutex_unlock(&tp->control);
9051 tp->rx_pending = ring->rx_pending;
9058 static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9060 struct r8152 *tp = netdev_priv(netdev);
9061 u16 bmcr, lcladv, rmtadv;
9064 if (usb_autopm_get_interface(tp->intf) < 0)
9067 mutex_lock(&tp->control);
9069 bmcr = r8152_mdio_read(tp, MII_BMCR);
9070 lcladv = r8152_mdio_read(tp, MII_ADVERTISE);
9071 rmtadv = r8152_mdio_read(tp, MII_LPA);
9073 mutex_unlock(&tp->control);
9075 usb_autopm_put_interface(tp->intf);
9077 if (!(bmcr & BMCR_ANENABLE)) {
9079 pause->rx_pause = 0;
9080 pause->tx_pause = 0;
9086 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
9088 if (cap & FLOW_CTRL_RX)
9089 pause->rx_pause = 1;
9091 if (cap & FLOW_CTRL_TX)
9092 pause->tx_pause = 1;
9095 static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9097 struct r8152 *tp = netdev_priv(netdev);
9102 ret = usb_autopm_get_interface(tp->intf);
9106 mutex_lock(&tp->control);
9108 if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) {
9113 if (pause->rx_pause)
9114 cap |= FLOW_CTRL_RX;
9116 if (pause->tx_pause)
9117 cap |= FLOW_CTRL_TX;
9119 old = r8152_mdio_read(tp, MII_ADVERTISE);
9120 new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap);
9122 r8152_mdio_write(tp, MII_ADVERTISE, new1);
9125 mutex_unlock(&tp->control);
9126 usb_autopm_put_interface(tp->intf);
9131 static const struct ethtool_ops ops = {
9132 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
9133 .get_drvinfo = rtl8152_get_drvinfo,
9134 .get_link = ethtool_op_get_link,
9135 .nway_reset = rtl8152_nway_reset,
9136 .get_msglevel = rtl8152_get_msglevel,
9137 .set_msglevel = rtl8152_set_msglevel,
9138 .get_wol = rtl8152_get_wol,
9139 .set_wol = rtl8152_set_wol,
9140 .get_strings = rtl8152_get_strings,
9141 .get_sset_count = rtl8152_get_sset_count,
9142 .get_ethtool_stats = rtl8152_get_ethtool_stats,
9143 .get_coalesce = rtl8152_get_coalesce,
9144 .set_coalesce = rtl8152_set_coalesce,
9145 .get_eee = rtl_ethtool_get_eee,
9146 .set_eee = rtl_ethtool_set_eee,
9147 .get_link_ksettings = rtl8152_get_link_ksettings,
9148 .set_link_ksettings = rtl8152_set_link_ksettings,
9149 .get_tunable = rtl8152_get_tunable,
9150 .set_tunable = rtl8152_set_tunable,
9151 .get_ringparam = rtl8152_get_ringparam,
9152 .set_ringparam = rtl8152_set_ringparam,
9153 .get_pauseparam = rtl8152_get_pauseparam,
9154 .set_pauseparam = rtl8152_set_pauseparam,
9157 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
9159 struct r8152 *tp = netdev_priv(netdev);
9160 struct mii_ioctl_data *data = if_mii(rq);
9163 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9166 res = usb_autopm_get_interface(tp->intf);
9172 data->phy_id = R8152_PHY_ID; /* Internal PHY */
9176 mutex_lock(&tp->control);
9177 data->val_out = r8152_mdio_read(tp, data->reg_num);
9178 mutex_unlock(&tp->control);
9182 if (!capable(CAP_NET_ADMIN)) {
9186 mutex_lock(&tp->control);
9187 r8152_mdio_write(tp, data->reg_num, data->val_in);
9188 mutex_unlock(&tp->control);
9195 usb_autopm_put_interface(tp->intf);
9201 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
9203 struct r8152 *tp = netdev_priv(dev);
9206 switch (tp->version) {
9216 ret = usb_autopm_get_interface(tp->intf);
9220 mutex_lock(&tp->control);
9224 if (netif_running(dev)) {
9225 if (tp->rtl_ops.change_mtu)
9226 tp->rtl_ops.change_mtu(tp);
9228 if (netif_carrier_ok(dev)) {
9229 netif_stop_queue(dev);
9230 napi_disable(&tp->napi);
9231 tasklet_disable(&tp->tx_tl);
9232 tp->rtl_ops.disable(tp);
9233 tp->rtl_ops.enable(tp);
9235 tasklet_enable(&tp->tx_tl);
9236 napi_enable(&tp->napi);
9237 rtl8152_set_rx_mode(dev);
9238 netif_wake_queue(dev);
9242 mutex_unlock(&tp->control);
9244 usb_autopm_put_interface(tp->intf);
9249 static const struct net_device_ops rtl8152_netdev_ops = {
9250 .ndo_open = rtl8152_open,
9251 .ndo_stop = rtl8152_close,
9252 .ndo_eth_ioctl = rtl8152_ioctl,
9253 .ndo_start_xmit = rtl8152_start_xmit,
9254 .ndo_tx_timeout = rtl8152_tx_timeout,
9255 .ndo_set_features = rtl8152_set_features,
9256 .ndo_set_rx_mode = rtl8152_set_rx_mode,
9257 .ndo_set_mac_address = rtl8152_set_mac_address,
9258 .ndo_change_mtu = rtl8152_change_mtu,
9259 .ndo_validate_addr = eth_validate_addr,
9260 .ndo_features_check = rtl8152_features_check,
9263 static void rtl8152_unload(struct r8152 *tp)
9265 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9268 if (tp->version != RTL_VER_01)
9269 r8152_power_cut_en(tp, true);
9272 static void rtl8153_unload(struct r8152 *tp)
9274 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9277 r8153_power_cut_en(tp, false);
9280 static void rtl8153b_unload(struct r8152 *tp)
9282 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9285 r8153b_power_cut_en(tp, false);
9288 static int rtl_ops_init(struct r8152 *tp)
9290 struct rtl_ops *ops = &tp->rtl_ops;
9293 switch (tp->version) {
9297 ops->init = r8152b_init;
9298 ops->enable = rtl8152_enable;
9299 ops->disable = rtl8152_disable;
9300 ops->up = rtl8152_up;
9301 ops->down = rtl8152_down;
9302 ops->unload = rtl8152_unload;
9303 ops->eee_get = r8152_get_eee;
9304 ops->eee_set = r8152_set_eee;
9305 ops->in_nway = rtl8152_in_nway;
9306 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
9307 ops->autosuspend_en = rtl_runtime_suspend_enable;
9308 tp->rx_buf_sz = 16 * 1024;
9310 tp->eee_adv = MDIO_EEE_100TX;
9317 ops->init = r8153_init;
9318 ops->enable = rtl8153_enable;
9319 ops->disable = rtl8153_disable;
9320 ops->up = rtl8153_up;
9321 ops->down = rtl8153_down;
9322 ops->unload = rtl8153_unload;
9323 ops->eee_get = r8153_get_eee;
9324 ops->eee_set = r8152_set_eee;
9325 ops->in_nway = rtl8153_in_nway;
9326 ops->hw_phy_cfg = r8153_hw_phy_cfg;
9327 ops->autosuspend_en = rtl8153_runtime_enable;
9328 ops->change_mtu = rtl8153_change_mtu;
9329 if (tp->udev->speed < USB_SPEED_SUPER)
9330 tp->rx_buf_sz = 16 * 1024;
9332 tp->rx_buf_sz = 32 * 1024;
9334 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9339 ops->init = r8153b_init;
9340 ops->enable = rtl8153_enable;
9341 ops->disable = rtl8153_disable;
9342 ops->up = rtl8153b_up;
9343 ops->down = rtl8153b_down;
9344 ops->unload = rtl8153b_unload;
9345 ops->eee_get = r8153_get_eee;
9346 ops->eee_set = r8152_set_eee;
9347 ops->in_nway = rtl8153_in_nway;
9348 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
9349 ops->autosuspend_en = rtl8153b_runtime_enable;
9350 ops->change_mtu = rtl8153_change_mtu;
9351 tp->rx_buf_sz = 32 * 1024;
9353 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9358 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9361 ops->init = r8156_init;
9362 ops->enable = rtl8156_enable;
9363 ops->disable = rtl8153_disable;
9364 ops->up = rtl8156_up;
9365 ops->down = rtl8156_down;
9366 ops->unload = rtl8153_unload;
9367 ops->eee_get = r8153_get_eee;
9368 ops->eee_set = r8152_set_eee;
9369 ops->in_nway = rtl8153_in_nway;
9370 ops->hw_phy_cfg = r8156_hw_phy_cfg;
9371 ops->autosuspend_en = rtl8156_runtime_enable;
9372 ops->change_mtu = rtl8156_change_mtu;
9373 tp->rx_buf_sz = 48 * 1024;
9374 tp->support_2500full = 1;
9379 tp->support_2500full = 1;
9383 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9384 ops->init = r8156b_init;
9385 ops->enable = rtl8156b_enable;
9386 ops->disable = rtl8153_disable;
9387 ops->up = rtl8156_up;
9388 ops->down = rtl8156_down;
9389 ops->unload = rtl8153_unload;
9390 ops->eee_get = r8153_get_eee;
9391 ops->eee_set = r8152_set_eee;
9392 ops->in_nway = rtl8153_in_nway;
9393 ops->hw_phy_cfg = r8156b_hw_phy_cfg;
9394 ops->autosuspend_en = rtl8156_runtime_enable;
9395 ops->change_mtu = rtl8156_change_mtu;
9396 tp->rx_buf_sz = 48 * 1024;
9400 ops->init = r8153c_init;
9401 ops->enable = rtl8153_enable;
9402 ops->disable = rtl8153_disable;
9403 ops->up = rtl8153c_up;
9404 ops->down = rtl8153b_down;
9405 ops->unload = rtl8153_unload;
9406 ops->eee_get = r8153_get_eee;
9407 ops->eee_set = r8152_set_eee;
9408 ops->in_nway = rtl8153_in_nway;
9409 ops->hw_phy_cfg = r8153c_hw_phy_cfg;
9410 ops->autosuspend_en = rtl8153c_runtime_enable;
9411 ops->change_mtu = rtl8153c_change_mtu;
9412 tp->rx_buf_sz = 32 * 1024;
9414 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9419 dev_err(&tp->intf->dev, "Unknown Device\n");
9426 #define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
9427 #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
9428 #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
9429 #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
9430 #define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw"
9431 #define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw"
9432 #define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw"
9434 MODULE_FIRMWARE(FIRMWARE_8153A_2);
9435 MODULE_FIRMWARE(FIRMWARE_8153A_3);
9436 MODULE_FIRMWARE(FIRMWARE_8153A_4);
9437 MODULE_FIRMWARE(FIRMWARE_8153B_2);
9438 MODULE_FIRMWARE(FIRMWARE_8153C_1);
9439 MODULE_FIRMWARE(FIRMWARE_8156A_2);
9440 MODULE_FIRMWARE(FIRMWARE_8156B_2);
9442 static int rtl_fw_init(struct r8152 *tp)
9444 struct rtl_fw *rtl_fw = &tp->rtl_fw;
9446 switch (tp->version) {
9448 rtl_fw->fw_name = FIRMWARE_8153A_2;
9449 rtl_fw->pre_fw = r8153_pre_firmware_1;
9450 rtl_fw->post_fw = r8153_post_firmware_1;
9453 rtl_fw->fw_name = FIRMWARE_8153A_3;
9454 rtl_fw->pre_fw = r8153_pre_firmware_2;
9455 rtl_fw->post_fw = r8153_post_firmware_2;
9458 rtl_fw->fw_name = FIRMWARE_8153A_4;
9459 rtl_fw->post_fw = r8153_post_firmware_3;
9462 rtl_fw->fw_name = FIRMWARE_8153B_2;
9463 rtl_fw->pre_fw = r8153b_pre_firmware_1;
9464 rtl_fw->post_fw = r8153b_post_firmware_1;
9467 rtl_fw->fw_name = FIRMWARE_8156A_2;
9468 rtl_fw->post_fw = r8156a_post_firmware_1;
9472 rtl_fw->fw_name = FIRMWARE_8156B_2;
9475 rtl_fw->fw_name = FIRMWARE_8153C_1;
9476 rtl_fw->pre_fw = r8153b_pre_firmware_1;
9477 rtl_fw->post_fw = r8153c_post_firmware_1;
9486 u8 rtl8152_get_version(struct usb_interface *intf)
9488 struct usb_device *udev = interface_to_usbdev(intf);
9494 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
9498 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
9499 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
9500 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
9502 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
9508 version = RTL_VER_01;
9511 version = RTL_VER_02;
9514 version = RTL_VER_03;
9517 version = RTL_VER_04;
9520 version = RTL_VER_05;
9523 version = RTL_VER_06;
9526 version = RTL_VER_07;
9529 version = RTL_VER_08;
9532 version = RTL_VER_09;
9535 version = RTL_TEST_01;
9538 version = RTL_VER_10;
9541 version = RTL_VER_11;
9544 version = RTL_VER_12;
9547 version = RTL_VER_13;
9550 version = RTL_VER_14;
9553 version = RTL_VER_15;
9556 version = RTL_VER_UNKNOWN;
9557 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
9561 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
9565 EXPORT_SYMBOL_GPL(rtl8152_get_version);
9567 static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev)
9569 int parent_vendor_id = le16_to_cpu(udev->parent->descriptor.idVendor);
9570 int product_id = le16_to_cpu(udev->descriptor.idProduct);
9571 int vendor_id = le16_to_cpu(udev->descriptor.idVendor);
9573 if (vendor_id == VENDOR_ID_LENOVO) {
9574 switch (product_id) {
9575 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
9576 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
9577 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3:
9578 case DEVICE_ID_THINKPAD_USB_C_DONGLE:
9581 } else if (vendor_id == VENDOR_ID_REALTEK && parent_vendor_id == VENDOR_ID_LENOVO) {
9582 switch (product_id) {
9590 static int rtl8152_probe(struct usb_interface *intf,
9591 const struct usb_device_id *id)
9593 struct usb_device *udev = interface_to_usbdev(intf);
9594 u8 version = rtl8152_get_version(intf);
9596 struct net_device *netdev;
9599 if (version == RTL_VER_UNKNOWN)
9602 if (!rtl_vendor_mode(intf))
9605 usb_reset_device(udev);
9606 netdev = alloc_etherdev(sizeof(struct r8152));
9608 dev_err(&intf->dev, "Out of memory\n");
9612 SET_NETDEV_DEV(netdev, &intf->dev);
9613 tp = netdev_priv(netdev);
9614 tp->msg_enable = 0x7FFF;
9617 tp->netdev = netdev;
9619 tp->version = version;
9621 tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0);
9622 tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0);
9623 tp->pipe_in = usb_rcvbulkpipe(udev, 1);
9624 tp->pipe_out = usb_sndbulkpipe(udev, 2);
9625 tp->pipe_intr = usb_rcvintpipe(udev, 3);
9631 tp->mii.supports_gmii = 0;
9634 tp->mii.supports_gmii = 1;
9638 ret = rtl_ops_init(tp);
9644 mutex_init(&tp->control);
9645 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
9646 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
9647 tasklet_setup(&tp->tx_tl, bottom_half);
9648 tasklet_disable(&tp->tx_tl);
9650 netdev->netdev_ops = &rtl8152_netdev_ops;
9651 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
9653 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9654 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
9655 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
9656 NETIF_F_HW_VLAN_CTAG_TX;
9657 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9658 NETIF_F_TSO | NETIF_F_FRAGLIST |
9659 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
9660 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
9661 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
9662 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
9663 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
9665 if (tp->version == RTL_VER_01) {
9666 netdev->features &= ~NETIF_F_RXCSUM;
9667 netdev->hw_features &= ~NETIF_F_RXCSUM;
9670 tp->lenovo_macpassthru = rtl8152_supports_lenovo_macpassthru(udev);
9672 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
9673 (!strcmp(udev->serial, "000001000000") ||
9674 !strcmp(udev->serial, "000002000000"))) {
9675 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
9676 tp->dell_tb_rx_agg_bug = 1;
9679 netdev->ethtool_ops = &ops;
9680 netif_set_tso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
9682 /* MTU range: 68 - 1500 or 9194 */
9683 netdev->min_mtu = ETH_MIN_MTU;
9684 switch (tp->version) {
9692 netdev->max_mtu = size_to_mtu(9 * 1024);
9696 netdev->max_mtu = size_to_mtu(15 * 1024);
9701 netdev->max_mtu = size_to_mtu(16 * 1024);
9707 netdev->max_mtu = ETH_DATA_LEN;
9711 tp->mii.dev = netdev;
9712 tp->mii.mdio_read = read_mii_word;
9713 tp->mii.mdio_write = write_mii_word;
9714 tp->mii.phy_id_mask = 0x3f;
9715 tp->mii.reg_num_mask = 0x1f;
9716 tp->mii.phy_id = R8152_PHY_ID;
9718 tp->autoneg = AUTONEG_ENABLE;
9719 tp->speed = SPEED_100;
9720 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
9721 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
9722 if (tp->mii.supports_gmii) {
9723 if (tp->support_2500full &&
9724 tp->udev->speed >= USB_SPEED_SUPER) {
9725 tp->speed = SPEED_2500;
9726 tp->advertising |= RTL_ADVERTISED_2500_FULL;
9728 tp->speed = SPEED_1000;
9730 tp->advertising |= RTL_ADVERTISED_1000_FULL;
9732 tp->duplex = DUPLEX_FULL;
9734 tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
9735 tp->rx_pending = 10 * RTL8152_MAX_RX;
9737 intf->needs_remote_wakeup = 1;
9739 if (!rtl_can_wakeup(tp))
9740 __rtl_set_wol(tp, 0);
9742 tp->saved_wolopts = __rtl_get_wol(tp);
9744 tp->rtl_ops.init(tp);
9745 #if IS_BUILTIN(CONFIG_USB_RTL8152)
9746 /* Retry in case request_firmware() is not ready yet. */
9747 tp->rtl_fw.retry = true;
9749 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
9750 set_ethernet_addr(tp, false);
9752 usb_set_intfdata(intf, tp);
9754 netif_napi_add_weight(netdev, &tp->napi, r8152_poll,
9755 tp->support_2500full ? 256 : 64);
9757 ret = register_netdev(netdev);
9759 dev_err(&intf->dev, "couldn't register the device\n");
9763 if (tp->saved_wolopts)
9764 device_set_wakeup_enable(&udev->dev, true);
9766 device_set_wakeup_enable(&udev->dev, false);
9768 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
9773 tasklet_kill(&tp->tx_tl);
9774 usb_set_intfdata(intf, NULL);
9776 free_netdev(netdev);
9780 static void rtl8152_disconnect(struct usb_interface *intf)
9782 struct r8152 *tp = usb_get_intfdata(intf);
9784 usb_set_intfdata(intf, NULL);
9788 unregister_netdev(tp->netdev);
9789 tasklet_kill(&tp->tx_tl);
9790 cancel_delayed_work_sync(&tp->hw_phy_work);
9791 if (tp->rtl_ops.unload)
9792 tp->rtl_ops.unload(tp);
9793 rtl8152_release_firmware(tp);
9794 free_netdev(tp->netdev);
9798 #define REALTEK_USB_DEVICE(vend, prod) { \
9799 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC), \
9802 USB_DEVICE_AND_INTERFACE_INFO(vend, prod, USB_CLASS_COMM, \
9803 USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE), \
9806 /* table of devices that work with this driver */
9807 static const struct usb_device_id rtl8152_table[] = {
9809 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050),
9810 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8053),
9811 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152),
9812 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153),
9813 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8155),
9814 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8156),
9817 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab),
9818 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6),
9819 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927),
9820 REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101),
9821 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f),
9822 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062),
9823 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069),
9824 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082),
9825 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205),
9826 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c),
9827 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214),
9828 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e),
9829 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387),
9830 REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041),
9831 REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff),
9832 REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601),
9836 MODULE_DEVICE_TABLE(usb, rtl8152_table);
9838 static struct usb_driver rtl8152_driver = {
9840 .id_table = rtl8152_table,
9841 .probe = rtl8152_probe,
9842 .disconnect = rtl8152_disconnect,
9843 .suspend = rtl8152_suspend,
9844 .resume = rtl8152_resume,
9845 .reset_resume = rtl8152_reset_resume,
9846 .pre_reset = rtl8152_pre_reset,
9847 .post_reset = rtl8152_post_reset,
9848 .supports_autosuspend = 1,
9849 .disable_hub_initiated_lpm = 1,
9852 module_usb_driver(rtl8152_driver);
9854 MODULE_AUTHOR(DRIVER_AUTHOR);
9855 MODULE_DESCRIPTION(DRIVER_DESC);
9856 MODULE_LICENSE("GPL");
9857 MODULE_VERSION(DRIVER_VERSION);