1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29 #include <linux/usb/r8152.h>
32 /* Information for net-next */
33 #define NETNEXT_VERSION "12"
35 /* Information for net */
36 #define NET_VERSION "13"
38 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
39 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
40 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
41 #define MODULENAME "r8152"
43 #define R8152_PHY_ID 32
45 #define PLA_IDR 0xc000
46 #define PLA_RCR 0xc010
47 #define PLA_RCR1 0xc012
48 #define PLA_RMS 0xc016
49 #define PLA_RXFIFO_CTRL0 0xc0a0
50 #define PLA_RXFIFO_FULL 0xc0a2
51 #define PLA_RXFIFO_CTRL1 0xc0a4
52 #define PLA_RX_FIFO_FULL 0xc0a6
53 #define PLA_RXFIFO_CTRL2 0xc0a8
54 #define PLA_RX_FIFO_EMPTY 0xc0aa
55 #define PLA_DMY_REG0 0xc0b0
56 #define PLA_FMC 0xc0b4
57 #define PLA_CFG_WOL 0xc0b6
58 #define PLA_TEREDO_CFG 0xc0bc
59 #define PLA_TEREDO_WAKE_BASE 0xc0c4
60 #define PLA_MAR 0xcd00
61 #define PLA_BACKUP 0xd000
62 #define PLA_BDC_CR 0xd1a0
63 #define PLA_TEREDO_TIMER 0xd2cc
64 #define PLA_REALWOW_TIMER 0xd2e8
65 #define PLA_UPHY_TIMER 0xd388
66 #define PLA_SUSPEND_FLAG 0xd38a
67 #define PLA_INDICATE_FALG 0xd38c
68 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
69 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
70 #define PLA_EXTRA_STATUS 0xd398
71 #define PLA_GPHY_CTRL 0xd3ae
72 #define PLA_POL_GPIO_CTRL 0xdc6a
73 #define PLA_EFUSE_DATA 0xdd00
74 #define PLA_EFUSE_CMD 0xdd02
75 #define PLA_LEDSEL 0xdd90
76 #define PLA_LED_FEATURE 0xdd92
77 #define PLA_PHYAR 0xde00
78 #define PLA_BOOT_CTRL 0xe004
79 #define PLA_LWAKE_CTRL_REG 0xe007
80 #define PLA_GPHY_INTR_IMR 0xe022
81 #define PLA_EEE_CR 0xe040
82 #define PLA_EEE_TXTWSYS 0xe04c
83 #define PLA_EEE_TXTWSYS_2P5G 0xe058
84 #define PLA_EEEP_CR 0xe080
85 #define PLA_MAC_PWR_CTRL 0xe0c0
86 #define PLA_MAC_PWR_CTRL2 0xe0ca
87 #define PLA_MAC_PWR_CTRL3 0xe0cc
88 #define PLA_MAC_PWR_CTRL4 0xe0ce
89 #define PLA_WDT6_CTRL 0xe428
90 #define PLA_TCR0 0xe610
91 #define PLA_TCR1 0xe612
92 #define PLA_MTPS 0xe615
93 #define PLA_TXFIFO_CTRL 0xe618
94 #define PLA_TXFIFO_FULL 0xe61a
95 #define PLA_RSTTALLY 0xe800
97 #define PLA_CRWECR 0xe81c
98 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
99 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
100 #define PLA_CONFIG5 0xe822
101 #define PLA_PHY_PWR 0xe84c
102 #define PLA_OOB_CTRL 0xe84f
103 #define PLA_CPCR 0xe854
104 #define PLA_MISC_0 0xe858
105 #define PLA_MISC_1 0xe85a
106 #define PLA_OCP_GPHY_BASE 0xe86c
107 #define PLA_TALLYCNT 0xe890
108 #define PLA_SFF_STS_7 0xe8de
109 #define PLA_PHYSTATUS 0xe908
110 #define PLA_CONFIG6 0xe90a /* CONFIG6 */
111 #define PLA_USB_CFG 0xe952
112 #define PLA_BP_BA 0xfc26
113 #define PLA_BP_0 0xfc28
114 #define PLA_BP_1 0xfc2a
115 #define PLA_BP_2 0xfc2c
116 #define PLA_BP_3 0xfc2e
117 #define PLA_BP_4 0xfc30
118 #define PLA_BP_5 0xfc32
119 #define PLA_BP_6 0xfc34
120 #define PLA_BP_7 0xfc36
121 #define PLA_BP_EN 0xfc38
123 #define USB_USB2PHY 0xb41e
124 #define USB_SSPHYLINK1 0xb426
125 #define USB_SSPHYLINK2 0xb428
126 #define USB_L1_CTRL 0xb45e
127 #define USB_U2P3_CTRL 0xb460
128 #define USB_CSR_DUMMY1 0xb464
129 #define USB_CSR_DUMMY2 0xb466
130 #define USB_DEV_STAT 0xb808
131 #define USB_CONNECT_TIMER 0xcbf8
132 #define USB_MSC_TIMER 0xcbfc
133 #define USB_BURST_SIZE 0xcfc0
134 #define USB_FW_FIX_EN0 0xcfca
135 #define USB_FW_FIX_EN1 0xcfcc
136 #define USB_LPM_CONFIG 0xcfd8
137 #define USB_ECM_OPTION 0xcfee
138 #define USB_CSTMR 0xcfef /* RTL8153A */
139 #define USB_MISC_2 0xcfff
140 #define USB_ECM_OP 0xd26b
141 #define USB_GPHY_CTRL 0xd284
142 #define USB_SPEED_OPTION 0xd32a
143 #define USB_FW_CTRL 0xd334 /* RTL8153B */
144 #define USB_FC_TIMER 0xd340
145 #define USB_USB_CTRL 0xd406
146 #define USB_PHY_CTRL 0xd408
147 #define USB_TX_AGG 0xd40a
148 #define USB_RX_BUF_TH 0xd40c
149 #define USB_USB_TIMER 0xd428
150 #define USB_RX_EARLY_TIMEOUT 0xd42c
151 #define USB_RX_EARLY_SIZE 0xd42e
152 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
153 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
154 #define USB_TX_DMA 0xd434
155 #define USB_UPT_RXDMA_OWN 0xd437
156 #define USB_UPHY3_MDCMDIO 0xd480
157 #define USB_TOLERANCE 0xd490
158 #define USB_LPM_CTRL 0xd41a
159 #define USB_BMU_RESET 0xd4b0
160 #define USB_BMU_CONFIG 0xd4b4
161 #define USB_U1U2_TIMER 0xd4da
162 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
163 #define USB_RX_AGGR_NUM 0xd4ee
164 #define USB_UPS_CTRL 0xd800
165 #define USB_POWER_CUT 0xd80a
166 #define USB_MISC_0 0xd81a
167 #define USB_MISC_1 0xd81f
168 #define USB_AFE_CTRL2 0xd824
169 #define USB_UPHY_XTAL 0xd826
170 #define USB_UPS_CFG 0xd842
171 #define USB_UPS_FLAGS 0xd848
172 #define USB_WDT1_CTRL 0xe404
173 #define USB_WDT11_CTRL 0xe43c
174 #define USB_BP_BA PLA_BP_BA
175 #define USB_BP_0 PLA_BP_0
176 #define USB_BP_1 PLA_BP_1
177 #define USB_BP_2 PLA_BP_2
178 #define USB_BP_3 PLA_BP_3
179 #define USB_BP_4 PLA_BP_4
180 #define USB_BP_5 PLA_BP_5
181 #define USB_BP_6 PLA_BP_6
182 #define USB_BP_7 PLA_BP_7
183 #define USB_BP_EN PLA_BP_EN /* RTL8153A */
184 #define USB_BP_8 0xfc38 /* RTL8153B */
185 #define USB_BP_9 0xfc3a
186 #define USB_BP_10 0xfc3c
187 #define USB_BP_11 0xfc3e
188 #define USB_BP_12 0xfc40
189 #define USB_BP_13 0xfc42
190 #define USB_BP_14 0xfc44
191 #define USB_BP_15 0xfc46
192 #define USB_BP2_EN 0xfc48
195 #define OCP_ALDPS_CONFIG 0x2010
196 #define OCP_EEE_CONFIG1 0x2080
197 #define OCP_EEE_CONFIG2 0x2092
198 #define OCP_EEE_CONFIG3 0x2094
199 #define OCP_BASE_MII 0xa400
200 #define OCP_EEE_AR 0xa41a
201 #define OCP_EEE_DATA 0xa41c
202 #define OCP_PHY_STATUS 0xa420
203 #define OCP_INTR_EN 0xa424
204 #define OCP_NCTL_CFG 0xa42c
205 #define OCP_POWER_CFG 0xa430
206 #define OCP_EEE_CFG 0xa432
207 #define OCP_SRAM_ADDR 0xa436
208 #define OCP_SRAM_DATA 0xa438
209 #define OCP_DOWN_SPEED 0xa442
210 #define OCP_EEE_ABLE 0xa5c4
211 #define OCP_EEE_ADV 0xa5d0
212 #define OCP_EEE_LPABLE 0xa5d2
213 #define OCP_10GBT_CTRL 0xa5d4
214 #define OCP_10GBT_STAT 0xa5d6
215 #define OCP_EEE_ADV2 0xa6d4
216 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
217 #define OCP_PHY_PATCH_STAT 0xb800
218 #define OCP_PHY_PATCH_CMD 0xb820
219 #define OCP_PHY_LOCK 0xb82e
220 #define OCP_ADC_IOFFSET 0xbcfc
221 #define OCP_ADC_CFG 0xbc06
222 #define OCP_SYSCLK_CFG 0xc416
225 #define SRAM_GREEN_CFG 0x8011
226 #define SRAM_LPF_CFG 0x8012
227 #define SRAM_GPHY_FW_VER 0x801e
228 #define SRAM_10M_AMP1 0x8080
229 #define SRAM_10M_AMP2 0x8082
230 #define SRAM_IMPEDANCE 0x8084
231 #define SRAM_PHY_LOCK 0xb82e
234 #define RCR_AAP 0x00000001
235 #define RCR_APM 0x00000002
236 #define RCR_AM 0x00000004
237 #define RCR_AB 0x00000008
238 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
239 #define SLOT_EN BIT(11)
242 #define OUTER_VLAN BIT(7)
243 #define INNER_VLAN BIT(6)
245 /* PLA_RXFIFO_CTRL0 */
246 #define RXFIFO_THR1_NORMAL 0x00080002
247 #define RXFIFO_THR1_OOB 0x01800003
249 /* PLA_RXFIFO_FULL */
250 #define RXFIFO_FULL_MASK 0xfff
252 /* PLA_RXFIFO_CTRL1 */
253 #define RXFIFO_THR2_FULL 0x00000060
254 #define RXFIFO_THR2_HIGH 0x00000038
255 #define RXFIFO_THR2_OOB 0x0000004a
256 #define RXFIFO_THR2_NORMAL 0x00a0
258 /* PLA_RXFIFO_CTRL2 */
259 #define RXFIFO_THR3_FULL 0x00000078
260 #define RXFIFO_THR3_HIGH 0x00000048
261 #define RXFIFO_THR3_OOB 0x0000005a
262 #define RXFIFO_THR3_NORMAL 0x0110
264 /* PLA_TXFIFO_CTRL */
265 #define TXFIFO_THR_NORMAL 0x00400008
266 #define TXFIFO_THR_NORMAL2 0x01000008
269 #define ECM_ALDPS 0x0002
272 #define FMC_FCR_MCU_EN 0x0001
275 #define EEEP_CR_EEEP_TX 0x0002
278 #define WDT6_SET_MODE 0x0010
281 #define TCR0_TX_EMPTY 0x0800
282 #define TCR0_AUTO_FIFO 0x0080
285 #define VERSION_MASK 0x7cf0
286 #define IFG_MASK (BIT(3) | BIT(9) | BIT(8))
287 #define IFG_144NS BIT(9)
288 #define IFG_96NS (BIT(9) | BIT(8))
291 #define MTPS_JUMBO (12 * 1024 / 64)
292 #define MTPS_DEFAULT (6 * 1024 / 64)
295 #define TALLY_RESET 0x0001
303 #define CRWECR_NORAML 0x00
304 #define CRWECR_CONFIG 0xc0
307 #define NOW_IS_OOB 0x80
308 #define TXFIFO_EMPTY 0x20
309 #define RXFIFO_EMPTY 0x10
310 #define LINK_LIST_READY 0x02
311 #define DIS_MCU_CLROOB 0x01
312 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
315 #define RXDY_GATED_EN 0x0008
318 #define RE_INIT_LL 0x8000
319 #define MCU_BORW_EN 0x4000
322 #define FLOW_CTRL_EN BIT(0)
323 #define CPCR_RX_VLAN 0x0040
326 #define MAGIC_EN 0x0001
329 #define TEREDO_SEL 0x8000
330 #define TEREDO_WAKE_MASK 0x7f00
331 #define TEREDO_RS_EVENT_MASK 0x00fe
332 #define OOB_TEREDO_EN 0x0001
335 #define ALDPS_PROXY_MODE 0x0001
338 #define EFUSE_READ_CMD BIT(15)
339 #define EFUSE_DATA_BIT16 BIT(7)
342 #define LINK_ON_WAKE_EN 0x0010
343 #define LINK_OFF_WAKE_EN 0x0008
346 #define LANWAKE_CLR_EN BIT(0)
349 #define EN_XG_LIP BIT(1)
350 #define EN_G_LIP BIT(2)
353 #define BWF_EN 0x0040
354 #define MWF_EN 0x0020
355 #define UWF_EN 0x0010
356 #define LAN_WAKE_EN 0x0002
358 /* PLA_LED_FEATURE */
359 #define LED_MODE_MASK 0x0700
362 #define TX_10M_IDLE_EN 0x0080
363 #define PFM_PWM_SWITCH 0x0040
364 #define TEST_IO_OFF BIT(4)
366 /* PLA_MAC_PWR_CTRL */
367 #define D3_CLK_GATED_EN 0x00004000
368 #define MCU_CLK_RATIO 0x07010f07
369 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
370 #define ALDPS_SPDWN_RATIO 0x0f87
372 /* PLA_MAC_PWR_CTRL2 */
373 #define EEE_SPDWN_RATIO 0x8007
374 #define MAC_CLK_SPDWN_EN BIT(15)
375 #define EEE_SPDWN_RATIO_MASK 0xff
377 /* PLA_MAC_PWR_CTRL3 */
378 #define PLA_MCU_SPDWN_EN BIT(14)
379 #define PKT_AVAIL_SPDWN_EN 0x0100
380 #define SUSPEND_SPDWN_EN 0x0004
381 #define U1U2_SPDWN_EN 0x0002
382 #define L1_SPDWN_EN 0x0001
384 /* PLA_MAC_PWR_CTRL4 */
385 #define PWRSAVE_SPDWN_EN 0x1000
386 #define RXDV_SPDWN_EN 0x0800
387 #define TX10MIDLE_EN 0x0100
388 #define IDLE_SPDWN_EN BIT(6)
389 #define TP100_SPDWN_EN 0x0020
390 #define TP500_SPDWN_EN 0x0010
391 #define TP1000_SPDWN_EN 0x0008
392 #define EEE_SPDWN_EN 0x0001
394 /* PLA_GPHY_INTR_IMR */
395 #define GPHY_STS_MSK 0x0001
396 #define SPEED_DOWN_MSK 0x0002
397 #define SPDWN_RXDV_MSK 0x0004
398 #define SPDWN_LINKCHG_MSK 0x0008
401 #define PHYAR_FLAG 0x80000000
404 #define EEE_RX_EN 0x0001
405 #define EEE_TX_EN 0x0002
408 #define AUTOLOAD_DONE 0x0002
410 /* PLA_LWAKE_CTRL_REG */
411 #define LANWAKE_PIN BIT(7)
413 /* PLA_SUSPEND_FLAG */
414 #define LINK_CHG_EVENT BIT(0)
416 /* PLA_INDICATE_FALG */
417 #define UPCOMING_RUNTIME_D3 BIT(0)
419 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
420 #define DEBUG_OE BIT(0)
421 #define DEBUG_LTSSM 0x0082
423 /* PLA_EXTRA_STATUS */
424 #define CUR_LINK_OK BIT(15)
425 #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
426 #define LINK_CHANGE_FLAG BIT(8)
427 #define POLL_LINK_CHG BIT(0)
430 #define GPHY_FLASH BIT(1)
432 /* PLA_POL_GPIO_CTRL */
433 #define DACK_DET_EN BIT(15)
434 #define POL_GPHY_PATCH BIT(4)
437 #define USB2PHY_SUSPEND 0x0001
438 #define USB2PHY_L1 0x0002
441 #define DELAY_PHY_PWR_CHG BIT(1)
444 #define pwd_dn_scale_mask 0x3ffe
445 #define pwd_dn_scale(x) ((x) << 1)
448 #define DYNAMIC_BURST 0x0001
451 #define EP4_FULL_FC 0x0001
454 #define STAT_SPEED_MASK 0x0006
455 #define STAT_SPEED_HIGH 0x0000
456 #define STAT_SPEED_FULL 0x0002
459 #define FW_FIX_SUSPEND BIT(14)
462 #define FW_IP_RESET_EN BIT(9)
465 #define LPM_U1U2_EN BIT(0)
468 #define TX_AGG_MAX_THRESHOLD 0x03
471 #define RX_THR_SUPPER 0x0c350180
472 #define RX_THR_HIGH 0x7a120180
473 #define RX_THR_SLOW 0xffff0180
474 #define RX_THR_B 0x00010001
477 #define TEST_MODE_DISABLE 0x00000001
478 #define TX_SIZE_ADJUST1 0x00000100
481 #define BMU_RESET_EP_IN 0x01
482 #define BMU_RESET_EP_OUT 0x02
485 #define ACT_ODMA BIT(1)
487 /* USB_UPT_RXDMA_OWN */
488 #define OWN_UPDATE BIT(0)
489 #define OWN_CLEAR BIT(1)
492 #define FC_PATCH_TASK BIT(1)
494 /* USB_RX_AGGR_NUM */
495 #define RX_AGGR_NUM_MASK 0x1ff
498 #define POWER_CUT 0x0100
500 /* USB_PM_CTRL_STATUS */
501 #define RESUME_INDICATE 0x0001
504 #define BYPASS_MAC_RESET BIT(5)
507 #define FORCE_SUPER BIT(0)
510 #define UPS_FORCE_PWR_DOWN BIT(0)
513 #define EN_ALL_SPEED BIT(0)
516 #define GPHY_PATCH_DONE BIT(2)
517 #define BYPASS_FLASH BIT(5)
518 #define BACKUP_RESTRORE BIT(6)
520 /* USB_SPEED_OPTION */
521 #define RG_PWRDN_EN BIT(8)
522 #define ALL_SPEED_OFF BIT(9)
525 #define FLOW_CTRL_PATCH_OPT BIT(1)
526 #define AUTO_SPEEDUP BIT(3)
527 #define FLOW_CTRL_PATCH_2 BIT(8)
530 #define CTRL_TIMER_EN BIT(15)
533 #define CDC_ECM_EN BIT(3)
534 #define RX_AGG_DISABLE 0x0010
535 #define RX_ZERO_EN 0x0080
538 #define U2P3_ENABLE 0x0001
539 #define RX_DETECT8 BIT(3)
542 #define PWR_EN 0x0001
543 #define PHASE2_EN 0x0008
544 #define UPS_EN BIT(4)
545 #define USP_PREWAKE BIT(5)
548 #define PCUT_STATUS 0x0001
550 /* USB_RX_EARLY_TIMEOUT */
551 #define COALESCE_SUPER 85000U
552 #define COALESCE_HIGH 250000U
553 #define COALESCE_SLOW 524280U
556 #define WTD1_EN BIT(0)
559 #define TIMER11_EN 0x0001
562 /* bit 4 ~ 5: fifo empty boundary */
563 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
564 /* bit 2 ~ 3: LMP timer */
565 #define LPM_TIMER_MASK 0x0c
566 #define LPM_TIMER_500MS 0x04 /* 500 ms */
567 #define LPM_TIMER_500US 0x0c /* 500 us */
568 #define ROK_EXIT_LPM 0x02
571 #define SEN_VAL_MASK 0xf800
572 #define SEN_VAL_NORMAL 0xa000
573 #define SEL_RXIDLE 0x0100
576 #define OOBS_POLLING BIT(8)
579 #define SAW_CNT_1MS_MASK 0x0fff
580 #define MID_REVERSE BIT(5) /* RTL8156A */
583 #define UPS_FLAGS_R_TUNE BIT(0)
584 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
585 #define UPS_FLAGS_250M_CKDIV BIT(2)
586 #define UPS_FLAGS_EN_ALDPS BIT(3)
587 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
588 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
589 #define ups_flags_speed(x) ((x) << 16)
590 #define UPS_FLAGS_EN_EEE BIT(20)
591 #define UPS_FLAGS_EN_500M_EEE BIT(21)
592 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
593 #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
594 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
595 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
596 #define UPS_FLAGS_EN_GREEN BIT(26)
597 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
613 /* OCP_ALDPS_CONFIG */
614 #define ENPWRSAVE 0x8000
615 #define ENPDNPS 0x0200
616 #define LINKENA 0x0100
617 #define DIS_SDSAVE 0x0010
620 #define PHY_STAT_MASK 0x0007
621 #define PHY_STAT_EXT_INIT 2
622 #define PHY_STAT_LAN_ON 3
623 #define PHY_STAT_PWRDN 5
626 #define INTR_SPEED_FORCE BIT(3)
629 #define PGA_RETURN_EN BIT(1)
632 #define EEE_CLKDIV_EN 0x8000
633 #define EN_ALDPS 0x0004
634 #define EN_10M_PLLOFF 0x0001
636 /* OCP_EEE_CONFIG1 */
637 #define RG_TXLPI_MSK_HFDUP 0x8000
638 #define RG_MATCLR_EN 0x4000
639 #define EEE_10_CAP 0x2000
640 #define EEE_NWAY_EN 0x1000
641 #define TX_QUIET_EN 0x0200
642 #define RX_QUIET_EN 0x0100
643 #define sd_rise_time_mask 0x0070
644 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
645 #define RG_RXLPI_MSK_HFDUP 0x0008
646 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
648 /* OCP_EEE_CONFIG2 */
649 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
650 #define RG_DACQUIET_EN 0x0400
651 #define RG_LDVQUIET_EN 0x0200
652 #define RG_CKRSEL 0x0020
653 #define RG_EEEPRG_EN 0x0010
655 /* OCP_EEE_CONFIG3 */
656 #define fast_snr_mask 0xff80
657 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
658 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
659 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
662 /* bit[15:14] function */
663 #define FUN_ADDR 0x0000
664 #define FUN_DATA 0x4000
665 /* bit[4:0] device addr */
668 #define CTAP_SHORT_EN 0x0040
669 #define EEE10_EN 0x0010
672 #define EN_EEE_CMODE BIT(14)
673 #define EN_EEE_1000 BIT(13)
674 #define EN_EEE_100 BIT(12)
675 #define EN_10M_CLKDIV BIT(11)
676 #define EN_10M_BGOFF 0x0080
679 #define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */
682 #define TXDIS_STATE 0x01
683 #define ABD_STATE 0x02
685 /* OCP_PHY_PATCH_STAT */
686 #define PATCH_READY BIT(6)
688 /* OCP_PHY_PATCH_CMD */
689 #define PATCH_REQUEST BIT(4)
692 #define PATCH_LOCK BIT(0)
695 #define CKADSEL_L 0x0100
696 #define ADC_EN 0x0080
697 #define EN_EMI_L 0x0040
700 #define sysclk_div_expo(x) (min(x, 5) << 8)
701 #define clk_div_expo(x) (min(x, 5) << 4)
704 #define GREEN_ETH_EN BIT(15)
705 #define R_TUNE_EN BIT(11)
708 #define LPF_AUTO_TUNE 0x8000
711 #define GDAC_IB_UPALL 0x0008
714 #define AMP_DN 0x0200
717 #define RX_DRIVING_MASK 0x6000
720 #define PHY_PATCH_LOCK 0x0001
723 #define AD_MASK 0xfee0
724 #define BND_MASK 0x0004
725 #define BD_MASK 0x0001
727 #define PASS_THRU_MASK 0x1
729 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
731 enum rtl_register_content {
744 #define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
745 #define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
747 #define RTL8152_MAX_TX 4
748 #define RTL8152_MAX_RX 10
753 #define RTL8152_RX_MAX_PENDING 4096
754 #define RTL8152_RXFG_HEADSZ 256
756 #define INTR_LINK 0x0004
758 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
759 #define RTL8153_RMS RTL8153_MAX_PACKET
760 #define RTL8152_TX_TIMEOUT (5 * HZ)
761 #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
762 #define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
763 #define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
767 RTL8152_INACCESSIBLE = 0,
777 PROBED_WITH_NO_ERRORS,
781 #define DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB 0x721e
782 #define DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK 0x3054
783 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
784 #define DEVICE_ID_THINKPAD_USB_C_DONGLE 0x720c
785 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
786 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3 0x3062
788 struct tally_counter {
795 __le32 tx_one_collision;
796 __le32 tx_multi_collision;
806 #define RX_LEN_MASK 0x7fff
809 #define RD_UDP_CS BIT(23)
810 #define RD_TCP_CS BIT(22)
811 #define RD_IPV6_CS BIT(20)
812 #define RD_IPV4_CS BIT(19)
815 #define IPF BIT(23) /* IP checksum fail */
816 #define UDPF BIT(22) /* UDP checksum fail */
817 #define TCPF BIT(21) /* TCP checksum fail */
818 #define RX_VLAN_TAG BIT(16)
827 #define TX_FS BIT(31) /* First segment of a packet */
828 #define TX_LS BIT(30) /* Final segment of a packet */
829 #define GTSENDV4 BIT(28)
830 #define GTSENDV6 BIT(27)
831 #define GTTCPHO_SHIFT 18
832 #define GTTCPHO_MAX 0x7fU
833 #define TX_LEN_MAX 0x3ffffU
836 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
837 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
838 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
839 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
841 #define MSS_MAX 0x7ffU
842 #define TCPHO_SHIFT 17
843 #define TCPHO_MAX 0x7ffU
844 #define TX_VLAN_TAG BIT(16)
850 struct list_head list, info_list;
852 struct r8152 *context;
858 struct list_head list;
860 struct r8152 *context;
869 struct usb_device *udev;
870 struct napi_struct napi;
871 struct usb_interface *intf;
872 struct net_device *netdev;
873 struct urb *intr_urb;
874 struct tx_agg tx_info[RTL8152_MAX_TX];
875 struct list_head rx_info, rx_used;
876 struct list_head rx_done, tx_free;
877 struct sk_buff_head tx_queue, rx_queue;
878 spinlock_t rx_lock, tx_lock;
879 struct delayed_work schedule, hw_phy_work;
880 struct mii_if_info mii;
881 struct mutex control; /* use for hw setting */
882 #ifdef CONFIG_PM_SLEEP
883 struct notifier_block pm_notifier;
885 struct tasklet_struct tx_tl;
888 void (*init)(struct r8152 *tp);
889 int (*enable)(struct r8152 *tp);
890 void (*disable)(struct r8152 *tp);
891 void (*up)(struct r8152 *tp);
892 void (*down)(struct r8152 *tp);
893 void (*unload)(struct r8152 *tp);
894 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
895 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
896 bool (*in_nway)(struct r8152 *tp);
897 void (*hw_phy_cfg)(struct r8152 *tp);
898 void (*autosuspend_en)(struct r8152 *tp, bool enable);
899 void (*change_mtu)(struct r8152 *tp);
912 u32 eee_plloff_100:1;
913 u32 eee_plloff_giga:1;
917 u32 ctap_short_off:1;
920 #define RTL_VER_SIZE 32
924 const struct firmware *fw;
926 char version[RTL_VER_SIZE];
927 int (*pre_fw)(struct r8152 *tp);
928 int (*post_fw)(struct r8152 *tp);
945 u32 fc_pause_on, fc_pause_off;
947 unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out;
949 u32 support_2500full:1;
950 u32 lenovo_macpassthru:1;
951 u32 dell_tb_rx_agg_bug:1;
960 unsigned int reg_access_reset_count;
964 * struct fw_block - block type and total length
965 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
966 * RTL_FW_USB and so on.
967 * @length: total length of the current block.
975 * struct fw_header - header of the firmware file
976 * @checksum: checksum of sha256 which is calculated from the whole file
977 * except the checksum field of the file. That is, calculate sha256
978 * from the version field to the end of the file.
979 * @version: version of this firmware.
980 * @blocks: the first firmware block of the file
984 char version[RTL_VER_SIZE];
985 struct fw_block blocks[];
988 enum rtl8152_fw_flags {
1002 enum rtl8152_fw_fixup_cmd {
1014 struct fw_phy_speed_up {
1015 struct fw_block blk_hdr;
1024 struct fw_block blk_hdr;
1025 struct fw_phy_set ver;
1029 struct fw_phy_fixup {
1030 struct fw_block blk_hdr;
1031 struct fw_phy_set setting;
1036 struct fw_phy_union {
1037 struct fw_block blk_hdr;
1040 struct fw_phy_set pre_set[2];
1041 struct fw_phy_set bp[8];
1042 struct fw_phy_set bp_en;
1049 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
1050 * The layout of the firmware block is:
1051 * <struct fw_mac> + <info> + <firmware data>.
1052 * @blk_hdr: firmware descriptor (type, length)
1053 * @fw_offset: offset of the firmware binary data. The start address of
1054 * the data would be the address of struct fw_mac + @fw_offset.
1055 * @fw_reg: the register to load the firmware. Depends on chip.
1056 * @bp_ba_addr: the register to write break point base address. Depends on
1058 * @bp_ba_value: break point base address. Depends on chip.
1059 * @bp_en_addr: the register to write break point enabled mask. Depends
1061 * @bp_en_value: break point enabled mask. Depends on the firmware.
1062 * @bp_start: the start register of break points. Depends on chip.
1063 * @bp_num: the break point number which needs to be set for this firmware.
1064 * Depends on the firmware.
1065 * @bp: break points. Depends on firmware.
1066 * @reserved: reserved space (unused)
1067 * @fw_ver_reg: the register to store the fw version.
1068 * @fw_ver_data: the firmware version of the current type.
1069 * @info: additional information for debugging, and is followed by the
1070 * binary data of firmware.
1073 struct fw_block blk_hdr;
1082 __le16 bp[16]; /* any value determined by firmware */
1090 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
1091 * This is used to set patch key when loading the firmware of PHY.
1092 * @blk_hdr: firmware descriptor (type, length)
1093 * @key_reg: the register to write the patch key.
1094 * @key_data: patch key.
1095 * @reserved: reserved space (unused)
1097 struct fw_phy_patch_key {
1098 struct fw_block blk_hdr;
1105 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
1106 * The layout of the firmware block is:
1107 * <struct fw_phy_nc> + <info> + <firmware data>.
1108 * @blk_hdr: firmware descriptor (type, length)
1109 * @fw_offset: offset of the firmware binary data. The start address of
1110 * the data would be the address of struct fw_phy_nc + @fw_offset.
1111 * @fw_reg: the register to load the firmware. Depends on chip.
1112 * @ba_reg: the register to write the base address. Depends on chip.
1113 * @ba_data: base address. Depends on chip.
1114 * @patch_en_addr: the register of enabling patch mode. Depends on chip.
1115 * @patch_en_value: patch mode enabled mask. Depends on the firmware.
1116 * @mode_reg: the regitster of switching the mode.
1117 * @mode_pre: the mode needing to be set before loading the firmware.
1118 * @mode_post: the mode to be set when finishing to load the firmware.
1119 * @reserved: reserved space (unused)
1120 * @bp_start: the start register of break points. Depends on chip.
1121 * @bp_num: the break point number which needs to be set for this firmware.
1122 * Depends on the firmware.
1123 * @bp: break points. Depends on firmware.
1124 * @info: additional information for debugging, and is followed by the
1125 * binary data of firmware.
1128 struct fw_block blk_hdr;
1133 __le16 patch_en_addr;
1134 __le16 patch_en_value;
1153 RTL_FW_PHY_UNION_NC,
1154 RTL_FW_PHY_UNION_NC1,
1155 RTL_FW_PHY_UNION_NC2,
1156 RTL_FW_PHY_UNION_UC2,
1157 RTL_FW_PHY_UNION_UC,
1158 RTL_FW_PHY_UNION_MISC,
1159 RTL_FW_PHY_SPEED_UP,
1164 RTL_VER_UNKNOWN = 0,
1187 TX_CSUM_SUCCESS = 0,
1192 #define RTL_ADVERTISED_10_HALF BIT(0)
1193 #define RTL_ADVERTISED_10_FULL BIT(1)
1194 #define RTL_ADVERTISED_100_HALF BIT(2)
1195 #define RTL_ADVERTISED_100_FULL BIT(3)
1196 #define RTL_ADVERTISED_1000_HALF BIT(4)
1197 #define RTL_ADVERTISED_1000_FULL BIT(5)
1198 #define RTL_ADVERTISED_2500_FULL BIT(6)
1200 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1201 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1203 static const int multicast_filter_limit = 32;
1204 static unsigned int agg_buf_sz = 16384;
1206 #define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))
1208 /* If register access fails then we block access and issue a reset. If this
1209 * happens too many times in a row without a successful access then we stop
1210 * trying to reset and just leave access blocked.
1212 #define REGISTER_ACCESS_MAX_RESETS 3
1214 static void rtl_set_inaccessible(struct r8152 *tp)
1216 set_bit(RTL8152_INACCESSIBLE, &tp->flags);
1217 smp_mb__after_atomic();
1220 static void rtl_set_accessible(struct r8152 *tp)
1222 clear_bit(RTL8152_INACCESSIBLE, &tp->flags);
1223 smp_mb__after_atomic();
1227 int r8152_control_msg(struct r8152 *tp, unsigned int pipe, __u8 request,
1228 __u8 requesttype, __u16 value, __u16 index, void *data,
1229 __u16 size, const char *msg_tag)
1231 struct usb_device *udev = tp->udev;
1234 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1237 ret = usb_control_msg(udev, pipe, request, requesttype,
1238 value, index, data, size,
1239 USB_CTRL_GET_TIMEOUT);
1241 /* No need to issue a reset to report an error if the USB device got
1242 * unplugged; just return immediately.
1247 /* If the write was successful then we're done */
1249 tp->reg_access_reset_count = 0;
1254 "Failed to %s %d bytes at %#06x/%#06x (%d)\n",
1255 msg_tag, size, value, index, ret);
1257 /* Block all future register access until we reset. Much of the code
1258 * in the driver doesn't check for errors. Notably, many parts of the
1259 * driver do a read/modify/write of a register value without
1260 * confirming that the read succeeded. Writing back modified garbage
1261 * like this can fully wedge the adapter, requiring a power cycle.
1263 rtl_set_inaccessible(tp);
1265 /* If probe hasn't yet finished, then we'll request a retry of the
1266 * whole probe routine if we get any control transfer errors. We
1267 * never have to clear this bit since we free/reallocate the whole "tp"
1268 * structure if we retry probe.
1270 if (!test_bit(PROBED_WITH_NO_ERRORS, &tp->flags)) {
1271 set_bit(PROBE_SHOULD_RETRY, &tp->flags);
1275 /* Failing to access registers in pre-reset is not surprising since we
1276 * wouldn't be resetting if things were behaving normally. The register
1277 * access we do in pre-reset isn't truly mandatory--we're just reusing
1278 * the disable() function and trying to be nice by powering the
1279 * adapter down before resetting it. Thus, if we're in pre-reset,
1280 * we'll return right away and not try to queue up yet another reset.
1281 * We know the post-reset is already coming.
1283 if (test_bit(IN_PRE_RESET, &tp->flags))
1286 if (tp->reg_access_reset_count < REGISTER_ACCESS_MAX_RESETS) {
1287 usb_queue_reset_device(tp->intf);
1288 tp->reg_access_reset_count++;
1289 } else if (tp->reg_access_reset_count == REGISTER_ACCESS_MAX_RESETS) {
1291 "Tried to reset %d times; giving up.\n",
1292 REGISTER_ACCESS_MAX_RESETS);
1299 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1304 tmp = kmalloc(size, GFP_KERNEL);
1308 ret = r8152_control_msg(tp, tp->pipe_ctrl_in,
1309 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1310 value, index, tmp, size, "read");
1313 memset(data, 0xff, size);
1315 memcpy(data, tmp, size);
1323 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1328 tmp = kmemdup(data, size, GFP_KERNEL);
1332 ret = r8152_control_msg(tp, tp->pipe_ctrl_out,
1333 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1334 value, index, tmp, size, "write");
1341 static void rtl_set_unplug(struct r8152 *tp)
1343 if (tp->udev->state == USB_STATE_NOTATTACHED)
1344 rtl_set_inaccessible(tp);
1347 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1348 void *data, u16 type)
1353 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1356 /* both size and indix must be 4 bytes align */
1357 if ((size & 3) || !size || (index & 3) || !data)
1360 if ((u32)index + (u32)size > 0xffff)
1365 ret = get_registers(tp, index, type, limit, data);
1373 ret = get_registers(tp, index, type, size, data);
1390 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1391 u16 size, void *data, u16 type)
1394 u16 byteen_start, byteen_end, byen;
1397 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1400 /* both size and indix must be 4 bytes align */
1401 if ((size & 3) || !size || (index & 3) || !data)
1404 if ((u32)index + (u32)size > 0xffff)
1407 byteen_start = byteen & BYTE_EN_START_MASK;
1408 byteen_end = byteen & BYTE_EN_END_MASK;
1410 byen = byteen_start | (byteen_start << 4);
1412 /* Split the first DWORD if the byte_en is not 0xff */
1413 if (byen != BYTE_EN_DWORD) {
1414 ret = set_registers(tp, index, type | byen, 4, data);
1424 byen = byteen_end | (byteen_end >> 4);
1426 /* Split the last DWORD if the byte_en is not 0xff */
1427 if (byen != BYTE_EN_DWORD)
1432 ret = set_registers(tp, index,
1433 type | BYTE_EN_DWORD,
1442 ret = set_registers(tp, index,
1443 type | BYTE_EN_DWORD,
1455 /* Set the last DWORD */
1456 if (byen != BYTE_EN_DWORD)
1457 ret = set_registers(tp, index, type | byen, 4, data);
1468 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1470 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1474 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1476 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1480 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1482 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1485 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1489 generic_ocp_read(tp, index, sizeof(data), &data, type);
1491 return __le32_to_cpu(data);
1494 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1496 __le32 tmp = __cpu_to_le32(data);
1498 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1501 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1505 u16 byen = BYTE_EN_WORD;
1506 u8 shift = index & 2;
1511 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1513 data = __le32_to_cpu(tmp);
1514 data >>= (shift * 8);
1520 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1524 u16 byen = BYTE_EN_WORD;
1525 u8 shift = index & 2;
1531 mask <<= (shift * 8);
1532 data <<= (shift * 8);
1536 tmp = __cpu_to_le32(data);
1538 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1541 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1545 u8 shift = index & 3;
1549 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1551 data = __le32_to_cpu(tmp);
1552 data >>= (shift * 8);
1558 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1562 u16 byen = BYTE_EN_BYTE;
1563 u8 shift = index & 3;
1569 mask <<= (shift * 8);
1570 data <<= (shift * 8);
1574 tmp = __cpu_to_le32(data);
1576 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1579 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1581 u16 ocp_base, ocp_index;
1583 ocp_base = addr & 0xf000;
1584 if (ocp_base != tp->ocp_base) {
1585 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1586 tp->ocp_base = ocp_base;
1589 ocp_index = (addr & 0x0fff) | 0xb000;
1590 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1593 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1595 u16 ocp_base, ocp_index;
1597 ocp_base = addr & 0xf000;
1598 if (ocp_base != tp->ocp_base) {
1599 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1600 tp->ocp_base = ocp_base;
1603 ocp_index = (addr & 0x0fff) | 0xb000;
1604 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1607 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1609 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1612 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1614 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1617 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1619 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1620 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1623 static u16 sram_read(struct r8152 *tp, u16 addr)
1625 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1626 return ocp_reg_read(tp, OCP_SRAM_DATA);
1629 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1631 struct r8152 *tp = netdev_priv(netdev);
1634 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1637 if (phy_id != R8152_PHY_ID)
1640 ret = r8152_mdio_read(tp, reg);
1646 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1648 struct r8152 *tp = netdev_priv(netdev);
1650 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1653 if (phy_id != R8152_PHY_ID)
1656 r8152_mdio_write(tp, reg, val);
1660 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1663 rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1666 static int __rtl8152_set_mac_address(struct net_device *netdev, void *p,
1669 struct r8152 *tp = netdev_priv(netdev);
1670 struct sockaddr *addr = p;
1671 int ret = -EADDRNOTAVAIL;
1673 if (!is_valid_ether_addr(addr->sa_data))
1677 ret = usb_autopm_get_interface(tp->intf);
1682 mutex_lock(&tp->control);
1684 eth_hw_addr_set(netdev, addr->sa_data);
1686 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1687 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1688 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1690 mutex_unlock(&tp->control);
1693 usb_autopm_put_interface(tp->intf);
1698 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1700 return __rtl8152_set_mac_address(netdev, p, false);
1703 /* Devices containing proper chips can support a persistent
1704 * host system provided MAC address.
1705 * Examples of this are Dell TB15 and Dell WD15 docks
1707 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1710 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1711 union acpi_object *obj;
1714 unsigned char buf[6];
1716 acpi_object_type mac_obj_type;
1719 if (tp->lenovo_macpassthru) {
1720 mac_obj_name = "\\MACA";
1721 mac_obj_type = ACPI_TYPE_STRING;
1724 /* test for -AD variant of RTL8153 */
1725 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1726 if ((ocp_data & AD_MASK) == 0x1000) {
1727 /* test for MAC address pass-through bit */
1728 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1729 if ((ocp_data & PASS_THRU_MASK) != 1) {
1730 netif_dbg(tp, probe, tp->netdev,
1731 "No efuse for RTL8153-AD MAC pass through\n");
1735 /* test for RTL8153-BND and RTL8153-BD */
1736 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1737 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1738 netif_dbg(tp, probe, tp->netdev,
1739 "Invalid variant for MAC pass through\n");
1744 mac_obj_name = "\\_SB.AMAC";
1745 mac_obj_type = ACPI_TYPE_BUFFER;
1749 /* returns _AUXMAC_#AABBCCDDEEFF# */
1750 status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1751 obj = (union acpi_object *)buffer.pointer;
1752 if (!ACPI_SUCCESS(status))
1754 if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1755 netif_warn(tp, probe, tp->netdev,
1756 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1757 obj->type, obj->string.length);
1761 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1762 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1763 netif_warn(tp, probe, tp->netdev,
1764 "Invalid header when reading pass-thru MAC addr\n");
1767 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1768 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1769 netif_warn(tp, probe, tp->netdev,
1770 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1775 memcpy(sa->sa_data, buf, 6);
1776 netif_info(tp, probe, tp->netdev,
1777 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1784 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1786 struct net_device *dev = tp->netdev;
1789 sa->sa_family = dev->type;
1791 ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1793 if (tp->version == RTL_VER_01) {
1794 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1796 /* if device doesn't support MAC pass through this will
1797 * be expected to be non-zero
1799 ret = vendor_mac_passthru_addr_read(tp, sa);
1801 ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1807 netif_err(tp, probe, dev, "Get ether addr fail\n");
1808 } else if (!is_valid_ether_addr(sa->sa_data)) {
1809 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1811 eth_hw_addr_random(dev);
1812 ether_addr_copy(sa->sa_data, dev->dev_addr);
1813 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1821 static int set_ethernet_addr(struct r8152 *tp, bool in_resume)
1823 struct net_device *dev = tp->netdev;
1827 ret = determine_ethernet_addr(tp, &sa);
1831 if (tp->version == RTL_VER_01)
1832 eth_hw_addr_set(dev, sa.sa_data);
1834 ret = __rtl8152_set_mac_address(dev, &sa, in_resume);
1839 static void read_bulk_callback(struct urb *urb)
1841 struct net_device *netdev;
1842 int status = urb->status;
1845 unsigned long flags;
1855 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1858 if (!test_bit(WORK_ENABLE, &tp->flags))
1861 netdev = tp->netdev;
1863 /* When link down, the driver would cancel all bulks. */
1864 /* This avoid the re-submitting bulk */
1865 if (!netif_carrier_ok(netdev))
1868 usb_mark_last_busy(tp->udev);
1872 if (urb->actual_length < ETH_ZLEN)
1875 spin_lock_irqsave(&tp->rx_lock, flags);
1876 list_add_tail(&agg->list, &tp->rx_done);
1877 spin_unlock_irqrestore(&tp->rx_lock, flags);
1878 napi_schedule(&tp->napi);
1882 netif_device_detach(tp->netdev);
1885 urb->actual_length = 0;
1886 spin_lock_irqsave(&tp->rx_lock, flags);
1887 list_add_tail(&agg->list, &tp->rx_done);
1888 spin_unlock_irqrestore(&tp->rx_lock, flags);
1889 set_bit(RX_EPROTO, &tp->flags);
1890 schedule_delayed_work(&tp->schedule, 1);
1893 return; /* the urb is in unlink state */
1895 if (net_ratelimit())
1896 netdev_warn(netdev, "maybe reset is needed?\n");
1899 if (net_ratelimit())
1900 netdev_warn(netdev, "Rx status %d\n", status);
1904 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1907 static void write_bulk_callback(struct urb *urb)
1909 struct net_device_stats *stats;
1910 struct net_device *netdev;
1913 unsigned long flags;
1914 int status = urb->status;
1924 netdev = tp->netdev;
1925 stats = &netdev->stats;
1927 if (net_ratelimit())
1928 netdev_warn(netdev, "Tx status %d\n", status);
1929 stats->tx_errors += agg->skb_num;
1931 stats->tx_packets += agg->skb_num;
1932 stats->tx_bytes += agg->skb_len;
1935 spin_lock_irqsave(&tp->tx_lock, flags);
1936 list_add_tail(&agg->list, &tp->tx_free);
1937 spin_unlock_irqrestore(&tp->tx_lock, flags);
1939 usb_autopm_put_interface_async(tp->intf);
1941 if (!netif_carrier_ok(netdev))
1944 if (!test_bit(WORK_ENABLE, &tp->flags))
1947 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1950 if (!skb_queue_empty(&tp->tx_queue))
1951 tasklet_schedule(&tp->tx_tl);
1954 static void intr_callback(struct urb *urb)
1958 int status = urb->status;
1965 if (!test_bit(WORK_ENABLE, &tp->flags))
1968 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1972 case 0: /* success */
1974 case -ECONNRESET: /* unlink */
1976 netif_device_detach(tp->netdev);
1980 netif_info(tp, intr, tp->netdev,
1981 "Stop submitting intr, status %d\n", status);
1984 if (net_ratelimit())
1985 netif_info(tp, intr, tp->netdev,
1986 "intr status -EOVERFLOW\n");
1988 /* -EPIPE: should clear the halt */
1990 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1994 d = urb->transfer_buffer;
1995 if (INTR_LINK & __le16_to_cpu(d[0])) {
1996 if (!netif_carrier_ok(tp->netdev)) {
1997 set_bit(RTL8152_LINK_CHG, &tp->flags);
1998 schedule_delayed_work(&tp->schedule, 0);
2001 if (netif_carrier_ok(tp->netdev)) {
2002 netif_stop_queue(tp->netdev);
2003 set_bit(RTL8152_LINK_CHG, &tp->flags);
2004 schedule_delayed_work(&tp->schedule, 0);
2009 res = usb_submit_urb(urb, GFP_ATOMIC);
2010 if (res == -ENODEV) {
2012 netif_device_detach(tp->netdev);
2014 netif_err(tp, intr, tp->netdev,
2015 "can't resubmit intr, status %d\n", res);
2019 static inline void *rx_agg_align(void *data)
2021 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
2024 static inline void *tx_agg_align(void *data)
2026 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
2029 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
2031 list_del(&agg->info_list);
2033 usb_free_urb(agg->urb);
2034 put_page(agg->page);
2037 atomic_dec(&tp->rx_count);
2040 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
2042 struct net_device *netdev = tp->netdev;
2043 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
2044 unsigned int order = get_order(tp->rx_buf_sz);
2045 struct rx_agg *rx_agg;
2046 unsigned long flags;
2048 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
2052 rx_agg->page = alloc_pages(mflags | __GFP_COMP | __GFP_NOWARN, order);
2056 rx_agg->buffer = page_address(rx_agg->page);
2058 rx_agg->urb = usb_alloc_urb(0, mflags);
2062 rx_agg->context = tp;
2064 INIT_LIST_HEAD(&rx_agg->list);
2065 INIT_LIST_HEAD(&rx_agg->info_list);
2066 spin_lock_irqsave(&tp->rx_lock, flags);
2067 list_add_tail(&rx_agg->info_list, &tp->rx_info);
2068 spin_unlock_irqrestore(&tp->rx_lock, flags);
2070 atomic_inc(&tp->rx_count);
2075 __free_pages(rx_agg->page, order);
2081 static void free_all_mem(struct r8152 *tp)
2083 struct rx_agg *agg, *agg_next;
2084 unsigned long flags;
2087 spin_lock_irqsave(&tp->rx_lock, flags);
2089 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
2090 free_rx_agg(tp, agg);
2092 spin_unlock_irqrestore(&tp->rx_lock, flags);
2094 WARN_ON(atomic_read(&tp->rx_count));
2096 for (i = 0; i < RTL8152_MAX_TX; i++) {
2097 usb_free_urb(tp->tx_info[i].urb);
2098 tp->tx_info[i].urb = NULL;
2100 kfree(tp->tx_info[i].buffer);
2101 tp->tx_info[i].buffer = NULL;
2102 tp->tx_info[i].head = NULL;
2105 usb_free_urb(tp->intr_urb);
2106 tp->intr_urb = NULL;
2108 kfree(tp->intr_buff);
2109 tp->intr_buff = NULL;
2112 static int alloc_all_mem(struct r8152 *tp)
2114 struct net_device *netdev = tp->netdev;
2115 struct usb_interface *intf = tp->intf;
2116 struct usb_host_interface *alt = intf->cur_altsetting;
2117 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
2120 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
2122 spin_lock_init(&tp->rx_lock);
2123 spin_lock_init(&tp->tx_lock);
2124 INIT_LIST_HEAD(&tp->rx_info);
2125 INIT_LIST_HEAD(&tp->tx_free);
2126 INIT_LIST_HEAD(&tp->rx_done);
2127 skb_queue_head_init(&tp->tx_queue);
2128 skb_queue_head_init(&tp->rx_queue);
2129 atomic_set(&tp->rx_count, 0);
2131 for (i = 0; i < RTL8152_MAX_RX; i++) {
2132 if (!alloc_rx_agg(tp, GFP_KERNEL))
2136 for (i = 0; i < RTL8152_MAX_TX; i++) {
2140 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
2144 if (buf != tx_agg_align(buf)) {
2146 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
2152 urb = usb_alloc_urb(0, GFP_KERNEL);
2158 INIT_LIST_HEAD(&tp->tx_info[i].list);
2159 tp->tx_info[i].context = tp;
2160 tp->tx_info[i].urb = urb;
2161 tp->tx_info[i].buffer = buf;
2162 tp->tx_info[i].head = tx_agg_align(buf);
2164 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
2167 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
2171 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
2175 tp->intr_interval = (int)ep_intr->desc.bInterval;
2176 usb_fill_int_urb(tp->intr_urb, tp->udev, tp->pipe_intr,
2177 tp->intr_buff, INTBUFSIZE, intr_callback,
2178 tp, tp->intr_interval);
2187 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
2189 struct tx_agg *agg = NULL;
2190 unsigned long flags;
2192 if (list_empty(&tp->tx_free))
2195 spin_lock_irqsave(&tp->tx_lock, flags);
2196 if (!list_empty(&tp->tx_free)) {
2197 struct list_head *cursor;
2199 cursor = tp->tx_free.next;
2200 list_del_init(cursor);
2201 agg = list_entry(cursor, struct tx_agg, list);
2203 spin_unlock_irqrestore(&tp->tx_lock, flags);
2208 /* r8152_csum_workaround()
2209 * The hw limits the value of the transport offset. When the offset is out of
2210 * range, calculate the checksum by sw.
2212 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
2213 struct sk_buff_head *list)
2215 if (skb_shinfo(skb)->gso_size) {
2216 netdev_features_t features = tp->netdev->features;
2217 struct sk_buff *segs, *seg, *next;
2218 struct sk_buff_head seg_list;
2220 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
2221 segs = skb_gso_segment(skb, features);
2222 if (IS_ERR(segs) || !segs)
2225 __skb_queue_head_init(&seg_list);
2227 skb_list_walk_safe(segs, seg, next) {
2228 skb_mark_not_on_list(seg);
2229 __skb_queue_tail(&seg_list, seg);
2232 skb_queue_splice(&seg_list, list);
2234 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2235 if (skb_checksum_help(skb) < 0)
2238 __skb_queue_head(list, skb);
2240 struct net_device_stats *stats;
2243 stats = &tp->netdev->stats;
2244 stats->tx_dropped++;
2249 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
2251 if (skb_vlan_tag_present(skb)) {
2254 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
2255 desc->opts2 |= cpu_to_le32(opts2);
2259 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
2261 u32 opts2 = le32_to_cpu(desc->opts2);
2263 if (opts2 & RX_VLAN_TAG)
2264 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2265 swab16(opts2 & 0xffff));
2268 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
2269 struct sk_buff *skb, u32 len)
2271 u32 mss = skb_shinfo(skb)->gso_size;
2272 u32 opts1, opts2 = 0;
2273 int ret = TX_CSUM_SUCCESS;
2275 WARN_ON_ONCE(len > TX_LEN_MAX);
2277 opts1 = len | TX_FS | TX_LS;
2280 u32 transport_offset = (u32)skb_transport_offset(skb);
2282 if (transport_offset > GTTCPHO_MAX) {
2283 netif_warn(tp, tx_err, tp->netdev,
2284 "Invalid transport offset 0x%x for TSO\n",
2290 switch (vlan_get_protocol(skb)) {
2291 case htons(ETH_P_IP):
2295 case htons(ETH_P_IPV6):
2296 if (skb_cow_head(skb, 0)) {
2300 tcp_v6_gso_csum_prep(skb);
2309 opts1 |= transport_offset << GTTCPHO_SHIFT;
2310 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2311 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2312 u32 transport_offset = (u32)skb_transport_offset(skb);
2315 if (transport_offset > TCPHO_MAX) {
2316 netif_warn(tp, tx_err, tp->netdev,
2317 "Invalid transport offset 0x%x\n",
2323 switch (vlan_get_protocol(skb)) {
2324 case htons(ETH_P_IP):
2326 ip_protocol = ip_hdr(skb)->protocol;
2329 case htons(ETH_P_IPV6):
2331 ip_protocol = ipv6_hdr(skb)->nexthdr;
2335 ip_protocol = IPPROTO_RAW;
2339 if (ip_protocol == IPPROTO_TCP)
2341 else if (ip_protocol == IPPROTO_UDP)
2346 opts2 |= transport_offset << TCPHO_SHIFT;
2349 desc->opts2 = cpu_to_le32(opts2);
2350 desc->opts1 = cpu_to_le32(opts1);
2356 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2358 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2362 __skb_queue_head_init(&skb_head);
2363 spin_lock(&tx_queue->lock);
2364 skb_queue_splice_init(tx_queue, &skb_head);
2365 spin_unlock(&tx_queue->lock);
2367 tx_data = agg->head;
2370 remain = agg_buf_sz;
2372 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2373 struct tx_desc *tx_desc;
2374 struct sk_buff *skb;
2377 skb = __skb_dequeue(&skb_head);
2381 len = skb->len + sizeof(*tx_desc);
2384 __skb_queue_head(&skb_head, skb);
2388 tx_data = tx_agg_align(tx_data);
2389 tx_desc = (struct tx_desc *)tx_data;
2391 if (r8152_tx_csum(tp, tx_desc, skb, skb->len)) {
2392 r8152_csum_workaround(tp, skb, &skb_head);
2396 rtl_tx_vlan_tag(tx_desc, skb);
2398 tx_data += sizeof(*tx_desc);
2401 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2402 struct net_device_stats *stats = &tp->netdev->stats;
2404 stats->tx_dropped++;
2405 dev_kfree_skb_any(skb);
2406 tx_data -= sizeof(*tx_desc);
2411 agg->skb_len += len;
2412 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2414 dev_kfree_skb_any(skb);
2416 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2418 if (tp->dell_tb_rx_agg_bug)
2422 if (!skb_queue_empty(&skb_head)) {
2423 spin_lock(&tx_queue->lock);
2424 skb_queue_splice(&skb_head, tx_queue);
2425 spin_unlock(&tx_queue->lock);
2428 netif_tx_lock(tp->netdev);
2430 if (netif_queue_stopped(tp->netdev) &&
2431 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2432 netif_wake_queue(tp->netdev);
2434 netif_tx_unlock(tp->netdev);
2436 ret = usb_autopm_get_interface_async(tp->intf);
2440 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_out,
2441 agg->head, (int)(tx_data - (u8 *)agg->head),
2442 (usb_complete_t)write_bulk_callback, agg);
2444 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2446 usb_autopm_put_interface_async(tp->intf);
2452 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2454 u8 checksum = CHECKSUM_NONE;
2457 if (!(tp->netdev->features & NETIF_F_RXCSUM))
2460 opts2 = le32_to_cpu(rx_desc->opts2);
2461 opts3 = le32_to_cpu(rx_desc->opts3);
2463 if (opts2 & RD_IPV4_CS) {
2465 checksum = CHECKSUM_NONE;
2466 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2467 checksum = CHECKSUM_UNNECESSARY;
2468 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2469 checksum = CHECKSUM_UNNECESSARY;
2470 } else if (opts2 & RD_IPV6_CS) {
2471 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2472 checksum = CHECKSUM_UNNECESSARY;
2473 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2474 checksum = CHECKSUM_UNNECESSARY;
2481 static inline bool rx_count_exceed(struct r8152 *tp)
2483 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2486 static inline int agg_offset(struct rx_agg *agg, void *addr)
2488 return (int)(addr - agg->buffer);
2491 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2493 struct rx_agg *agg, *agg_next, *agg_free = NULL;
2494 unsigned long flags;
2496 spin_lock_irqsave(&tp->rx_lock, flags);
2498 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2499 if (page_count(agg->page) == 1) {
2501 list_del_init(&agg->list);
2505 if (rx_count_exceed(tp)) {
2506 list_del_init(&agg->list);
2507 free_rx_agg(tp, agg);
2513 spin_unlock_irqrestore(&tp->rx_lock, flags);
2515 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2516 agg_free = alloc_rx_agg(tp, mflags);
2521 static int rx_bottom(struct r8152 *tp, int budget)
2523 unsigned long flags;
2524 struct list_head *cursor, *next, rx_queue;
2525 int ret = 0, work_done = 0;
2526 struct napi_struct *napi = &tp->napi;
2528 if (!skb_queue_empty(&tp->rx_queue)) {
2529 while (work_done < budget) {
2530 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2531 struct net_device *netdev = tp->netdev;
2532 struct net_device_stats *stats = &netdev->stats;
2533 unsigned int pkt_len;
2539 napi_gro_receive(napi, skb);
2541 stats->rx_packets++;
2542 stats->rx_bytes += pkt_len;
2546 if (list_empty(&tp->rx_done))
2549 clear_bit(RX_EPROTO, &tp->flags);
2550 INIT_LIST_HEAD(&rx_queue);
2551 spin_lock_irqsave(&tp->rx_lock, flags);
2552 list_splice_init(&tp->rx_done, &rx_queue);
2553 spin_unlock_irqrestore(&tp->rx_lock, flags);
2555 list_for_each_safe(cursor, next, &rx_queue) {
2556 struct rx_desc *rx_desc;
2557 struct rx_agg *agg, *agg_free;
2562 list_del_init(cursor);
2564 agg = list_entry(cursor, struct rx_agg, list);
2566 if (urb->status != 0 || urb->actual_length < ETH_ZLEN)
2569 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2571 rx_desc = agg->buffer;
2572 rx_data = agg->buffer;
2573 len_used += sizeof(struct rx_desc);
2575 while (urb->actual_length > len_used) {
2576 struct net_device *netdev = tp->netdev;
2577 struct net_device_stats *stats = &netdev->stats;
2578 unsigned int pkt_len, rx_frag_head_sz;
2579 struct sk_buff *skb;
2581 /* limit the skb numbers for rx_queue */
2582 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2585 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2586 if (pkt_len < ETH_ZLEN)
2589 len_used += pkt_len;
2590 if (urb->actual_length < len_used)
2593 pkt_len -= ETH_FCS_LEN;
2594 rx_data += sizeof(struct rx_desc);
2596 if (!agg_free || tp->rx_copybreak > pkt_len)
2597 rx_frag_head_sz = pkt_len;
2599 rx_frag_head_sz = tp->rx_copybreak;
2601 skb = napi_alloc_skb(napi, rx_frag_head_sz);
2603 stats->rx_dropped++;
2607 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2608 memcpy(skb->data, rx_data, rx_frag_head_sz);
2609 skb_put(skb, rx_frag_head_sz);
2610 pkt_len -= rx_frag_head_sz;
2611 rx_data += rx_frag_head_sz;
2613 skb_add_rx_frag(skb, 0, agg->page,
2614 agg_offset(agg, rx_data),
2616 SKB_DATA_ALIGN(pkt_len));
2617 get_page(agg->page);
2620 skb->protocol = eth_type_trans(skb, netdev);
2621 rtl_rx_vlan_tag(rx_desc, skb);
2622 if (work_done < budget) {
2624 stats->rx_packets++;
2625 stats->rx_bytes += skb->len;
2626 napi_gro_receive(napi, skb);
2628 __skb_queue_tail(&tp->rx_queue, skb);
2632 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2633 rx_desc = (struct rx_desc *)rx_data;
2634 len_used = agg_offset(agg, rx_data);
2635 len_used += sizeof(struct rx_desc);
2638 WARN_ON(!agg_free && page_count(agg->page) > 1);
2641 spin_lock_irqsave(&tp->rx_lock, flags);
2642 if (page_count(agg->page) == 1) {
2643 list_add(&agg_free->list, &tp->rx_used);
2645 list_add_tail(&agg->list, &tp->rx_used);
2649 spin_unlock_irqrestore(&tp->rx_lock, flags);
2654 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2656 urb->actual_length = 0;
2657 list_add_tail(&agg->list, next);
2661 if (!list_empty(&rx_queue)) {
2662 spin_lock_irqsave(&tp->rx_lock, flags);
2663 list_splice_tail(&rx_queue, &tp->rx_done);
2664 spin_unlock_irqrestore(&tp->rx_lock, flags);
2671 static void tx_bottom(struct r8152 *tp)
2676 struct net_device *netdev = tp->netdev;
2679 if (skb_queue_empty(&tp->tx_queue))
2682 agg = r8152_get_tx_agg(tp);
2686 res = r8152_tx_agg_fill(tp, agg);
2690 if (res == -ENODEV) {
2692 netif_device_detach(netdev);
2694 struct net_device_stats *stats = &netdev->stats;
2695 unsigned long flags;
2697 netif_warn(tp, tx_err, netdev,
2698 "failed tx_urb %d\n", res);
2699 stats->tx_dropped += agg->skb_num;
2701 spin_lock_irqsave(&tp->tx_lock, flags);
2702 list_add_tail(&agg->list, &tp->tx_free);
2703 spin_unlock_irqrestore(&tp->tx_lock, flags);
2708 static void bottom_half(struct tasklet_struct *t)
2710 struct r8152 *tp = from_tasklet(tp, t, tx_tl);
2712 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
2715 if (!test_bit(WORK_ENABLE, &tp->flags))
2718 /* When link down, the driver would cancel all bulks. */
2719 /* This avoid the re-submitting bulk */
2720 if (!netif_carrier_ok(tp->netdev))
2723 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2728 static int r8152_poll(struct napi_struct *napi, int budget)
2730 struct r8152 *tp = container_of(napi, struct r8152, napi);
2736 work_done = rx_bottom(tp, budget);
2738 if (work_done < budget) {
2739 if (!napi_complete_done(napi, work_done))
2741 if (!list_empty(&tp->rx_done))
2742 napi_schedule(napi);
2750 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2754 /* The rx would be stopped, so skip submitting */
2755 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) ||
2756 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2759 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_in,
2760 agg->buffer, tp->rx_buf_sz,
2761 (usb_complete_t)read_bulk_callback, agg);
2763 ret = usb_submit_urb(agg->urb, mem_flags);
2764 if (ret == -ENODEV) {
2766 netif_device_detach(tp->netdev);
2768 struct urb *urb = agg->urb;
2769 unsigned long flags;
2771 urb->actual_length = 0;
2772 spin_lock_irqsave(&tp->rx_lock, flags);
2773 list_add_tail(&agg->list, &tp->rx_done);
2774 spin_unlock_irqrestore(&tp->rx_lock, flags);
2776 netif_err(tp, rx_err, tp->netdev,
2777 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2779 napi_schedule(&tp->napi);
2785 static void rtl_drop_queued_tx(struct r8152 *tp)
2787 struct net_device_stats *stats = &tp->netdev->stats;
2788 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2789 struct sk_buff *skb;
2791 if (skb_queue_empty(tx_queue))
2794 __skb_queue_head_init(&skb_head);
2795 spin_lock_bh(&tx_queue->lock);
2796 skb_queue_splice_init(tx_queue, &skb_head);
2797 spin_unlock_bh(&tx_queue->lock);
2799 while ((skb = __skb_dequeue(&skb_head))) {
2801 stats->tx_dropped++;
2805 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2807 struct r8152 *tp = netdev_priv(netdev);
2809 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2811 usb_queue_reset_device(tp->intf);
2814 static void rtl8152_set_rx_mode(struct net_device *netdev)
2816 struct r8152 *tp = netdev_priv(netdev);
2818 if (netif_carrier_ok(netdev)) {
2819 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2820 schedule_delayed_work(&tp->schedule, 0);
2824 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2826 struct r8152 *tp = netdev_priv(netdev);
2827 u32 mc_filter[2]; /* Multicast hash filter */
2831 netif_stop_queue(netdev);
2832 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2833 ocp_data &= ~RCR_ACPT_ALL;
2834 ocp_data |= RCR_AB | RCR_APM;
2836 if (netdev->flags & IFF_PROMISC) {
2837 /* Unconditionally log net taps. */
2838 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2839 ocp_data |= RCR_AM | RCR_AAP;
2840 mc_filter[1] = 0xffffffff;
2841 mc_filter[0] = 0xffffffff;
2842 } else if ((netdev->flags & IFF_MULTICAST &&
2843 netdev_mc_count(netdev) > multicast_filter_limit) ||
2844 (netdev->flags & IFF_ALLMULTI)) {
2845 /* Too many to filter perfectly -- accept all multicasts. */
2847 mc_filter[1] = 0xffffffff;
2848 mc_filter[0] = 0xffffffff;
2853 if (netdev->flags & IFF_MULTICAST) {
2854 struct netdev_hw_addr *ha;
2856 netdev_for_each_mc_addr(ha, netdev) {
2857 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2859 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2865 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2866 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2868 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2869 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2870 netif_wake_queue(netdev);
2873 static netdev_features_t
2874 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2875 netdev_features_t features)
2877 u32 mss = skb_shinfo(skb)->gso_size;
2878 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2880 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) &&
2881 skb_transport_offset(skb) > max_offset)
2882 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2883 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2884 features &= ~NETIF_F_GSO_MASK;
2889 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2890 struct net_device *netdev)
2892 struct r8152 *tp = netdev_priv(netdev);
2894 skb_tx_timestamp(skb);
2896 skb_queue_tail(&tp->tx_queue, skb);
2898 if (!list_empty(&tp->tx_free)) {
2899 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2900 set_bit(SCHEDULE_TASKLET, &tp->flags);
2901 schedule_delayed_work(&tp->schedule, 0);
2903 usb_mark_last_busy(tp->udev);
2904 tasklet_schedule(&tp->tx_tl);
2906 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2907 netif_stop_queue(netdev);
2910 return NETDEV_TX_OK;
2913 static void r8152b_reset_packet_filter(struct r8152 *tp)
2917 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2918 ocp_data &= ~FMC_FCR_MCU_EN;
2919 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2920 ocp_data |= FMC_FCR_MCU_EN;
2921 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2924 static void rtl8152_nic_reset(struct r8152 *tp)
2929 switch (tp->version) {
2933 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2935 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2937 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2938 ocp_data &= ~BMU_RESET_EP_IN;
2939 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2941 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2942 ocp_data |= CDC_ECM_EN;
2943 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2945 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2947 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2949 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2950 ocp_data |= BMU_RESET_EP_IN;
2951 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2953 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2954 ocp_data &= ~CDC_ECM_EN;
2955 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2959 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2961 for (i = 0; i < 1000; i++) {
2962 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2964 usleep_range(100, 400);
2970 static void set_tx_qlen(struct r8152 *tp)
2972 tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
2975 static inline u16 rtl8152_get_speed(struct r8152 *tp)
2977 return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2980 static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
2984 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2986 ocp_data |= EEEP_CR_EEEP_TX;
2988 ocp_data &= ~EEEP_CR_EEEP_TX;
2989 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2992 static void rtl_set_eee_plus(struct r8152 *tp)
2994 if (rtl8152_get_speed(tp) & _10bps)
2995 rtl_eee_plus_en(tp, true);
2997 rtl_eee_plus_en(tp, false);
3000 static void rxdy_gated_en(struct r8152 *tp, bool enable)
3004 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
3006 ocp_data |= RXDY_GATED_EN;
3008 ocp_data &= ~RXDY_GATED_EN;
3009 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
3012 static int rtl_start_rx(struct r8152 *tp)
3014 struct rx_agg *agg, *agg_next;
3015 struct list_head tmp_list;
3016 unsigned long flags;
3019 INIT_LIST_HEAD(&tmp_list);
3021 spin_lock_irqsave(&tp->rx_lock, flags);
3023 INIT_LIST_HEAD(&tp->rx_done);
3024 INIT_LIST_HEAD(&tp->rx_used);
3026 list_splice_init(&tp->rx_info, &tmp_list);
3028 spin_unlock_irqrestore(&tp->rx_lock, flags);
3030 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
3031 INIT_LIST_HEAD(&agg->list);
3033 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
3034 if (++i > RTL8152_MAX_RX) {
3035 spin_lock_irqsave(&tp->rx_lock, flags);
3036 list_add_tail(&agg->list, &tp->rx_used);
3037 spin_unlock_irqrestore(&tp->rx_lock, flags);
3038 } else if (unlikely(ret < 0)) {
3039 spin_lock_irqsave(&tp->rx_lock, flags);
3040 list_add_tail(&agg->list, &tp->rx_done);
3041 spin_unlock_irqrestore(&tp->rx_lock, flags);
3043 ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
3047 spin_lock_irqsave(&tp->rx_lock, flags);
3048 WARN_ON(!list_empty(&tp->rx_info));
3049 list_splice(&tmp_list, &tp->rx_info);
3050 spin_unlock_irqrestore(&tp->rx_lock, flags);
3055 static int rtl_stop_rx(struct r8152 *tp)
3057 struct rx_agg *agg, *agg_next;
3058 struct list_head tmp_list;
3059 unsigned long flags;
3061 INIT_LIST_HEAD(&tmp_list);
3063 /* The usb_kill_urb() couldn't be used in atomic.
3064 * Therefore, move the list of rx_info to a tmp one.
3065 * Then, list_for_each_entry_safe could be used without
3069 spin_lock_irqsave(&tp->rx_lock, flags);
3070 list_splice_init(&tp->rx_info, &tmp_list);
3071 spin_unlock_irqrestore(&tp->rx_lock, flags);
3073 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
3074 /* At least RTL8152_MAX_RX rx_agg have the page_count being
3075 * equal to 1, so the other ones could be freed safely.
3077 if (page_count(agg->page) > 1)
3078 free_rx_agg(tp, agg);
3080 usb_kill_urb(agg->urb);
3083 /* Move back the list of temp to the rx_info */
3084 spin_lock_irqsave(&tp->rx_lock, flags);
3085 WARN_ON(!list_empty(&tp->rx_info));
3086 list_splice(&tmp_list, &tp->rx_info);
3087 spin_unlock_irqrestore(&tp->rx_lock, flags);
3089 while (!skb_queue_empty(&tp->rx_queue))
3090 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
3095 static void rtl_set_ifg(struct r8152 *tp, u16 speed)
3099 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3100 ocp_data &= ~IFG_MASK;
3101 if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
3102 ocp_data |= IFG_144NS;
3103 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
3105 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3106 ocp_data &= ~TX10MIDLE_EN;
3107 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
3109 ocp_data |= IFG_96NS;
3110 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
3112 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3113 ocp_data |= TX10MIDLE_EN;
3114 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
3118 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
3120 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
3121 OWN_UPDATE | OWN_CLEAR);
3124 static int rtl_enable(struct r8152 *tp)
3128 r8152b_reset_packet_filter(tp);
3130 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
3131 ocp_data |= CR_RE | CR_TE;
3132 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
3134 switch (tp->version) {
3144 r8153b_rx_agg_chg_indicate(tp);
3148 rxdy_gated_en(tp, false);
3153 static int rtl8152_enable(struct r8152 *tp)
3155 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3159 rtl_set_eee_plus(tp);
3161 return rtl_enable(tp);
3164 static void r8153_set_rx_early_timeout(struct r8152 *tp)
3166 u32 ocp_data = tp->coalesce / 8;
3168 switch (tp->version) {
3173 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3180 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
3181 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
3183 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3185 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3194 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3196 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3205 static void r8153_set_rx_early_size(struct r8152 *tp)
3207 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
3209 switch (tp->version) {
3214 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3220 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3229 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3238 static int rtl8153_enable(struct r8152 *tp)
3242 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3246 rtl_set_eee_plus(tp);
3247 r8153_set_rx_early_timeout(tp);
3248 r8153_set_rx_early_size(tp);
3250 rtl_set_ifg(tp, rtl8152_get_speed(tp));
3252 switch (tp->version) {
3255 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
3256 ocp_data &= ~FC_PATCH_TASK;
3257 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3258 usleep_range(1000, 2000);
3259 ocp_data |= FC_PATCH_TASK;
3260 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3266 return rtl_enable(tp);
3269 static void rtl_disable(struct r8152 *tp)
3274 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
3275 rtl_drop_queued_tx(tp);
3279 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3280 ocp_data &= ~RCR_ACPT_ALL;
3281 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3283 rtl_drop_queued_tx(tp);
3285 for (i = 0; i < RTL8152_MAX_TX; i++)
3286 usb_kill_urb(tp->tx_info[i].urb);
3288 rxdy_gated_en(tp, true);
3290 for (i = 0; i < 1000; i++) {
3291 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3292 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
3294 usleep_range(1000, 2000);
3297 for (i = 0; i < 1000; i++) {
3298 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
3300 usleep_range(1000, 2000);
3305 rtl8152_nic_reset(tp);
3308 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
3312 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
3314 ocp_data |= POWER_CUT;
3316 ocp_data &= ~POWER_CUT;
3317 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
3319 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
3320 ocp_data &= ~RESUME_INDICATE;
3321 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
3324 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
3328 switch (tp->version) {
3339 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
3341 ocp_data |= CPCR_RX_VLAN;
3343 ocp_data &= ~CPCR_RX_VLAN;
3344 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
3354 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
3356 ocp_data |= OUTER_VLAN | INNER_VLAN;
3358 ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
3359 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);
3364 static int rtl8152_set_features(struct net_device *dev,
3365 netdev_features_t features)
3367 netdev_features_t changed = features ^ dev->features;
3368 struct r8152 *tp = netdev_priv(dev);
3371 ret = usb_autopm_get_interface(tp->intf);
3375 mutex_lock(&tp->control);
3377 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
3378 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3379 rtl_rx_vlan_en(tp, true);
3381 rtl_rx_vlan_en(tp, false);
3384 mutex_unlock(&tp->control);
3386 usb_autopm_put_interface(tp->intf);
3392 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
3394 static u32 __rtl_get_wol(struct r8152 *tp)
3399 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3400 if (ocp_data & LINK_ON_WAKE_EN)
3401 wolopts |= WAKE_PHY;
3403 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3404 if (ocp_data & UWF_EN)
3405 wolopts |= WAKE_UCAST;
3406 if (ocp_data & BWF_EN)
3407 wolopts |= WAKE_BCAST;
3408 if (ocp_data & MWF_EN)
3409 wolopts |= WAKE_MCAST;
3411 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3412 if (ocp_data & MAGIC_EN)
3413 wolopts |= WAKE_MAGIC;
3418 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3422 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3424 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3425 ocp_data &= ~LINK_ON_WAKE_EN;
3426 if (wolopts & WAKE_PHY)
3427 ocp_data |= LINK_ON_WAKE_EN;
3428 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3430 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3431 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3432 if (wolopts & WAKE_UCAST)
3434 if (wolopts & WAKE_BCAST)
3436 if (wolopts & WAKE_MCAST)
3438 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3440 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3442 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3443 ocp_data &= ~MAGIC_EN;
3444 if (wolopts & WAKE_MAGIC)
3445 ocp_data |= MAGIC_EN;
3446 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3448 if (wolopts & WAKE_ANY)
3449 device_set_wakeup_enable(&tp->udev->dev, true);
3451 device_set_wakeup_enable(&tp->udev->dev, false);
3454 static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
3456 u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3458 /* MAC clock speed down */
3460 ocp_data |= MAC_CLK_SPDWN_EN;
3462 ocp_data &= ~MAC_CLK_SPDWN_EN;
3464 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3467 static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
3471 /* MAC clock speed down */
3473 /* aldps_spdwn_ratio, tp10_spdwn_ratio */
3474 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3477 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3478 ocp_data &= ~EEE_SPDWN_RATIO_MASK;
3479 ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
3480 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3482 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3483 ocp_data &= ~MAC_CLK_SPDWN_EN;
3484 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3488 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3493 memset(u1u2, 0xff, sizeof(u1u2));
3495 memset(u1u2, 0x00, sizeof(u1u2));
3497 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3500 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3504 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3506 ocp_data |= LPM_U1U2_EN;
3508 ocp_data &= ~LPM_U1U2_EN;
3510 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3513 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3517 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3519 ocp_data |= U2P3_ENABLE;
3521 ocp_data &= ~U2P3_ENABLE;
3522 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3525 static void r8153b_ups_flags(struct r8152 *tp)
3529 if (tp->ups_info.green)
3530 ups_flags |= UPS_FLAGS_EN_GREEN;
3532 if (tp->ups_info.aldps)
3533 ups_flags |= UPS_FLAGS_EN_ALDPS;
3535 if (tp->ups_info.eee)
3536 ups_flags |= UPS_FLAGS_EN_EEE;
3538 if (tp->ups_info.flow_control)
3539 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3541 if (tp->ups_info.eee_ckdiv)
3542 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3544 if (tp->ups_info.eee_cmod_lv)
3545 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3547 if (tp->ups_info.r_tune)
3548 ups_flags |= UPS_FLAGS_R_TUNE;
3550 if (tp->ups_info._10m_ckdiv)
3551 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3553 if (tp->ups_info.eee_plloff_100)
3554 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3556 if (tp->ups_info.eee_plloff_giga)
3557 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3559 if (tp->ups_info._250m_ckdiv)
3560 ups_flags |= UPS_FLAGS_250M_CKDIV;
3562 if (tp->ups_info.ctap_short_off)
3563 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3565 switch (tp->ups_info.speed_duplex) {
3567 ups_flags |= ups_flags_speed(1);
3570 ups_flags |= ups_flags_speed(2);
3572 case NWAY_100M_HALF:
3573 ups_flags |= ups_flags_speed(3);
3575 case NWAY_100M_FULL:
3576 ups_flags |= ups_flags_speed(4);
3578 case NWAY_1000M_FULL:
3579 ups_flags |= ups_flags_speed(5);
3581 case FORCE_10M_HALF:
3582 ups_flags |= ups_flags_speed(6);
3584 case FORCE_10M_FULL:
3585 ups_flags |= ups_flags_speed(7);
3587 case FORCE_100M_HALF:
3588 ups_flags |= ups_flags_speed(8);
3590 case FORCE_100M_FULL:
3591 ups_flags |= ups_flags_speed(9);
3597 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3600 static void r8156_ups_flags(struct r8152 *tp)
3604 if (tp->ups_info.green)
3605 ups_flags |= UPS_FLAGS_EN_GREEN;
3607 if (tp->ups_info.aldps)
3608 ups_flags |= UPS_FLAGS_EN_ALDPS;
3610 if (tp->ups_info.eee)
3611 ups_flags |= UPS_FLAGS_EN_EEE;
3613 if (tp->ups_info.flow_control)
3614 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3616 if (tp->ups_info.eee_ckdiv)
3617 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3619 if (tp->ups_info._10m_ckdiv)
3620 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3622 if (tp->ups_info.eee_plloff_100)
3623 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3625 if (tp->ups_info.eee_plloff_giga)
3626 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3628 if (tp->ups_info._250m_ckdiv)
3629 ups_flags |= UPS_FLAGS_250M_CKDIV;
3631 switch (tp->ups_info.speed_duplex) {
3632 case FORCE_10M_HALF:
3633 ups_flags |= ups_flags_speed(0);
3635 case FORCE_10M_FULL:
3636 ups_flags |= ups_flags_speed(1);
3638 case FORCE_100M_HALF:
3639 ups_flags |= ups_flags_speed(2);
3641 case FORCE_100M_FULL:
3642 ups_flags |= ups_flags_speed(3);
3645 ups_flags |= ups_flags_speed(4);
3648 ups_flags |= ups_flags_speed(5);
3650 case NWAY_100M_HALF:
3651 ups_flags |= ups_flags_speed(6);
3653 case NWAY_100M_FULL:
3654 ups_flags |= ups_flags_speed(7);
3656 case NWAY_1000M_FULL:
3657 ups_flags |= ups_flags_speed(8);
3659 case NWAY_2500M_FULL:
3660 ups_flags |= ups_flags_speed(9);
3666 switch (tp->ups_info.lite_mode) {
3668 ups_flags |= 0 << 5;
3671 ups_flags |= 2 << 5;
3675 ups_flags |= 1 << 5;
3679 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3682 static void rtl_green_en(struct r8152 *tp, bool enable)
3686 data = sram_read(tp, SRAM_GREEN_CFG);
3688 data |= GREEN_ETH_EN;
3690 data &= ~GREEN_ETH_EN;
3691 sram_write(tp, SRAM_GREEN_CFG, data);
3693 tp->ups_info.green = enable;
3696 static void r8153b_green_en(struct r8152 *tp, bool enable)
3699 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
3700 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3701 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3703 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3704 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3705 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3708 rtl_green_en(tp, true);
3711 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3716 for (i = 0; i < 500; i++) {
3717 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3718 data &= PHY_STAT_MASK;
3720 if (data == desired)
3722 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3723 data == PHY_STAT_EXT_INIT) {
3728 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3735 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3737 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3740 r8153b_ups_flags(tp);
3742 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3743 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3745 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3746 ocp_data |= UPS_FORCE_PWR_DOWN;
3747 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3749 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3750 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3752 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3753 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3754 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3756 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3759 for (i = 0; i < 500; i++) {
3760 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3762 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3768 tp->rtl_ops.hw_phy_cfg(tp);
3770 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3771 tp->duplex, tp->advertising);
3776 static void r8153c_ups_en(struct r8152 *tp, bool enable)
3778 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3781 r8153b_ups_flags(tp);
3783 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3784 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3786 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3787 ocp_data |= UPS_FORCE_PWR_DOWN;
3788 ocp_data &= ~BIT(7);
3789 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3791 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3792 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3794 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3795 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3796 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3798 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3801 for (i = 0; i < 500; i++) {
3802 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3804 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3810 tp->rtl_ops.hw_phy_cfg(tp);
3812 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3813 tp->duplex, tp->advertising);
3816 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3818 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3820 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3822 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3826 static void r8156_ups_en(struct r8152 *tp, bool enable)
3828 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3831 r8156_ups_flags(tp);
3833 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3834 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3836 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3837 ocp_data |= UPS_FORCE_PWR_DOWN;
3838 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3840 switch (tp->version) {
3843 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
3844 ocp_data &= ~OOBS_POLLING;
3845 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
3851 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3852 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3854 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3855 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3856 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3858 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3859 tp->rtl_ops.hw_phy_cfg(tp);
3861 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3862 tp->duplex, tp->advertising);
3867 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3871 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3873 ocp_data |= PWR_EN | PHASE2_EN;
3875 ocp_data &= ~(PWR_EN | PHASE2_EN);
3876 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3878 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3879 ocp_data &= ~PCUT_STATUS;
3880 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3883 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3887 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3889 ocp_data |= PWR_EN | PHASE2_EN;
3891 ocp_data &= ~PWR_EN;
3892 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3894 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3895 ocp_data &= ~PCUT_STATUS;
3896 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3899 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3903 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3905 ocp_data |= UPCOMING_RUNTIME_D3;
3907 ocp_data &= ~UPCOMING_RUNTIME_D3;
3908 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3910 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3911 ocp_data &= ~LINK_CHG_EVENT;
3912 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3914 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3915 ocp_data &= ~LINK_CHANGE_FLAG;
3916 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3919 static bool rtl_can_wakeup(struct r8152 *tp)
3921 struct usb_device *udev = tp->udev;
3923 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3926 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3931 __rtl_set_wol(tp, WAKE_ANY);
3933 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3935 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3936 ocp_data |= LINK_OFF_WAKE_EN;
3937 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3939 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3943 __rtl_set_wol(tp, tp->saved_wolopts);
3945 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3947 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3948 ocp_data &= ~LINK_OFF_WAKE_EN;
3949 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3951 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3955 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3958 r8153_u1u2en(tp, false);
3959 r8153_u2p3en(tp, false);
3960 rtl_runtime_suspend_enable(tp, true);
3962 rtl_runtime_suspend_enable(tp, false);
3964 switch (tp->version) {
3971 r8153_u2p3en(tp, true);
3975 r8153_u1u2en(tp, true);
3979 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3982 r8153_queue_wake(tp, true);
3983 r8153b_u1u2en(tp, false);
3984 r8153_u2p3en(tp, false);
3985 rtl_runtime_suspend_enable(tp, true);
3986 r8153b_ups_en(tp, true);
3988 r8153b_ups_en(tp, false);
3989 r8153_queue_wake(tp, false);
3990 rtl_runtime_suspend_enable(tp, false);
3991 if (tp->udev->speed >= USB_SPEED_SUPER)
3992 r8153b_u1u2en(tp, true);
3996 static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
3999 r8153_queue_wake(tp, true);
4000 r8153b_u1u2en(tp, false);
4001 r8153_u2p3en(tp, false);
4002 rtl_runtime_suspend_enable(tp, true);
4003 r8153c_ups_en(tp, true);
4005 r8153c_ups_en(tp, false);
4006 r8153_queue_wake(tp, false);
4007 rtl_runtime_suspend_enable(tp, false);
4008 r8153b_u1u2en(tp, true);
4012 static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
4015 r8153_queue_wake(tp, true);
4016 r8153b_u1u2en(tp, false);
4017 r8153_u2p3en(tp, false);
4018 rtl_runtime_suspend_enable(tp, true);
4020 r8153_queue_wake(tp, false);
4021 rtl_runtime_suspend_enable(tp, false);
4022 r8153_u2p3en(tp, true);
4023 if (tp->udev->speed >= USB_SPEED_SUPER)
4024 r8153b_u1u2en(tp, true);
4028 static void r8153_teredo_off(struct r8152 *tp)
4032 switch (tp->version) {
4040 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4041 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
4043 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4056 /* The bit 0 ~ 7 are relative with teredo settings. They are
4057 * W1C (write 1 to clear), so set all 1 to disable it.
4059 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
4063 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
4064 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
4065 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
4068 static void rtl_reset_bmu(struct r8152 *tp)
4072 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
4073 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
4074 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
4075 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
4076 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
4079 /* Clear the bp to stop the firmware before loading a new one */
4080 static void rtl_clear_bp(struct r8152 *tp, u16 type)
4085 switch (tp->version) {
4093 if (type == MCU_TYPE_USB) {
4094 ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
4103 ocp_write_byte(tp, type, PLA_BP_EN, 0);
4112 ocp_write_word(tp, type, USB_BP2_EN, 0);
4117 generic_ocp_write(tp, PLA_BP_0, BYTE_EN_DWORD, bp_num << 1, bp, type);
4119 /* wait 3 ms to make sure the firmware is stopped */
4120 usleep_range(3000, 6000);
4121 ocp_write_word(tp, type, PLA_BP_BA, 0);
4124 static inline void rtl_reset_ocp_base(struct r8152 *tp)
4129 static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
4134 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
4136 data |= PATCH_REQUEST;
4139 data &= ~PATCH_REQUEST;
4140 check = PATCH_READY;
4142 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
4144 for (i = 0; wait && i < 5000; i++) {
4147 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
4150 usleep_range(1000, 2000);
4151 ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
4152 if ((ocp_data & PATCH_READY) ^ check)
4156 if (request && wait &&
4157 !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
4158 dev_err(&tp->intf->dev, "PHY patch request fail\n");
4159 rtl_phy_patch_request(tp, false, false);
4166 static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
4168 if (patch_key && key_addr) {
4169 sram_write(tp, key_addr, patch_key);
4170 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
4171 } else if (key_addr) {
4174 sram_write(tp, 0x0000, 0x0000);
4176 data = ocp_reg_read(tp, OCP_PHY_LOCK);
4177 data &= ~PATCH_LOCK;
4178 ocp_reg_write(tp, OCP_PHY_LOCK, data);
4180 sram_write(tp, key_addr, 0x0000);
4187 rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
4189 if (rtl_phy_patch_request(tp, true, wait))
4192 rtl_patch_key_set(tp, key_addr, patch_key);
4197 static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
4199 rtl_patch_key_set(tp, key_addr, 0);
4201 rtl_phy_patch_request(tp, false, wait);
4206 static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)
4212 switch (tp->version) {
4233 fw_offset = __le16_to_cpu(phy->fw_offset);
4234 length = __le32_to_cpu(phy->blk_hdr.length);
4235 if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4236 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4240 length -= fw_offset;
4242 dev_err(&tp->intf->dev, "invalid block length\n");
4246 if (__le16_to_cpu(phy->fw_reg) != 0x9A00) {
4247 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4256 static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)
4260 switch (tp->version) {
4271 if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {
4272 dev_err(&tp->intf->dev, "invalid block length\n");
4276 if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {
4277 dev_err(&tp->intf->dev, "invalid phy ver addr\n");
4286 static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)
4290 switch (tp->version) {
4301 if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {
4302 dev_err(&tp->intf->dev, "invalid block length\n");
4306 if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||
4307 __le16_to_cpu(fix->setting.data) != BIT(7)) {
4308 dev_err(&tp->intf->dev, "invalid phy fixup\n");
4317 static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)
4323 switch (tp->version) {
4334 fw_offset = __le16_to_cpu(phy->fw_offset);
4335 length = __le32_to_cpu(phy->blk_hdr.length);
4336 if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4337 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4341 length -= fw_offset;
4343 dev_err(&tp->intf->dev, "invalid block length\n");
4347 if (phy->pre_num > 2) {
4348 dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num);
4352 if (phy->bp_num > 8) {
4353 dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num);
4362 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
4365 u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
4368 switch (tp->version) {
4374 patch_en_addr = 0xa01a;
4382 fw_offset = __le16_to_cpu(phy->fw_offset);
4383 if (fw_offset < sizeof(*phy)) {
4384 dev_err(&tp->intf->dev, "fw_offset too small\n");
4388 length = __le32_to_cpu(phy->blk_hdr.length);
4389 if (length < fw_offset) {
4390 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4394 length -= __le16_to_cpu(phy->fw_offset);
4395 if (!length || (length & 1)) {
4396 dev_err(&tp->intf->dev, "invalid block length\n");
4400 if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
4401 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4405 if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
4406 dev_err(&tp->intf->dev, "invalid base address register\n");
4410 if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
4411 dev_err(&tp->intf->dev,
4412 "invalid patch mode enabled register\n");
4416 if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
4417 dev_err(&tp->intf->dev,
4418 "invalid register to switch the mode\n");
4422 if (__le16_to_cpu(phy->bp_start) != bp_start) {
4423 dev_err(&tp->intf->dev,
4424 "invalid start register of break point\n");
4428 if (__le16_to_cpu(phy->bp_num) > 4) {
4429 dev_err(&tp->intf->dev, "invalid break point number\n");
4438 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
4440 u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
4445 type = __le32_to_cpu(mac->blk_hdr.type);
4446 if (type == RTL_FW_PLA) {
4447 switch (tp->version) {
4452 bp_ba_addr = PLA_BP_BA;
4454 bp_start = PLA_BP_0;
4468 bp_ba_addr = PLA_BP_BA;
4469 bp_en_addr = PLA_BP_EN;
4470 bp_start = PLA_BP_0;
4475 bp_ba_addr = PLA_BP_BA;
4476 bp_en_addr = USB_BP2_EN;
4477 bp_start = PLA_BP_0;
4483 } else if (type == RTL_FW_USB) {
4484 switch (tp->version) {
4490 bp_ba_addr = USB_BP_BA;
4491 bp_en_addr = USB_BP_EN;
4492 bp_start = USB_BP_0;
4503 bp_ba_addr = USB_BP_BA;
4504 bp_en_addr = USB_BP2_EN;
4505 bp_start = USB_BP_0;
4518 fw_offset = __le16_to_cpu(mac->fw_offset);
4519 if (fw_offset < sizeof(*mac)) {
4520 dev_err(&tp->intf->dev, "fw_offset too small\n");
4524 length = __le32_to_cpu(mac->blk_hdr.length);
4525 if (length < fw_offset) {
4526 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4530 length -= fw_offset;
4531 if (length < 4 || (length & 3)) {
4532 dev_err(&tp->intf->dev, "invalid block length\n");
4536 if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
4537 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4541 if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
4542 dev_err(&tp->intf->dev, "invalid base address register\n");
4546 if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
4547 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
4551 if (__le16_to_cpu(mac->bp_start) != bp_start) {
4552 dev_err(&tp->intf->dev,
4553 "invalid start register of break point\n");
4557 if (__le16_to_cpu(mac->bp_num) > max_bp) {
4558 dev_err(&tp->intf->dev, "invalid break point number\n");
4562 for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
4564 dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
4574 /* Verify the checksum for the firmware file. It is calculated from the version
4575 * field to the end of the file. Compare the result with the checksum field to
4576 * make sure the file is correct.
4578 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
4579 struct fw_header *fw_hdr, size_t size)
4581 unsigned char checksum[sizeof(fw_hdr->checksum)];
4582 struct crypto_shash *alg;
4583 struct shash_desc *sdesc;
4587 alg = crypto_alloc_shash("sha256", 0, 0);
4593 if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
4595 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
4596 crypto_shash_digestsize(alg));
4600 len = sizeof(*sdesc) + crypto_shash_descsize(alg);
4601 sdesc = kmalloc(len, GFP_KERNEL);
4608 len = size - sizeof(fw_hdr->checksum);
4609 rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
4614 if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
4615 dev_err(&tp->intf->dev, "checksum fail\n");
4620 crypto_free_shash(alg);
4625 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
4627 const struct firmware *fw = rtl_fw->fw;
4628 struct fw_header *fw_hdr = (struct fw_header *)fw->data;
4629 unsigned long fw_flags = 0;
4633 if (fw->size < sizeof(*fw_hdr)) {
4634 dev_err(&tp->intf->dev, "file too small\n");
4638 ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
4644 for (i = sizeof(*fw_hdr); i < fw->size;) {
4645 struct fw_block *block = (struct fw_block *)&fw->data[i];
4648 if ((i + sizeof(*block)) > fw->size)
4651 type = __le32_to_cpu(block->type);
4654 if (__le32_to_cpu(block->length) != sizeof(*block))
4658 if (test_bit(FW_FLAGS_PLA, &fw_flags)) {
4659 dev_err(&tp->intf->dev,
4660 "multiple PLA firmware encountered");
4664 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4665 dev_err(&tp->intf->dev,
4666 "check PLA firmware failed\n");
4669 __set_bit(FW_FLAGS_PLA, &fw_flags);
4672 if (test_bit(FW_FLAGS_USB, &fw_flags)) {
4673 dev_err(&tp->intf->dev,
4674 "multiple USB firmware encountered");
4678 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4679 dev_err(&tp->intf->dev,
4680 "check USB firmware failed\n");
4683 __set_bit(FW_FLAGS_USB, &fw_flags);
4685 case RTL_FW_PHY_START:
4686 if (test_bit(FW_FLAGS_START, &fw_flags) ||
4687 test_bit(FW_FLAGS_NC, &fw_flags) ||
4688 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4689 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4690 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4691 test_bit(FW_FLAGS_UC, &fw_flags) ||
4692 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4693 dev_err(&tp->intf->dev,
4694 "check PHY_START fail\n");
4698 if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {
4699 dev_err(&tp->intf->dev,
4700 "Invalid length for PHY_START\n");
4703 __set_bit(FW_FLAGS_START, &fw_flags);
4705 case RTL_FW_PHY_STOP:
4706 if (test_bit(FW_FLAGS_STOP, &fw_flags) ||
4707 !test_bit(FW_FLAGS_START, &fw_flags)) {
4708 dev_err(&tp->intf->dev,
4709 "Check PHY_STOP fail\n");
4713 if (__le32_to_cpu(block->length) != sizeof(*block)) {
4714 dev_err(&tp->intf->dev,
4715 "Invalid length for PHY_STOP\n");
4718 __set_bit(FW_FLAGS_STOP, &fw_flags);
4721 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4722 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4723 dev_err(&tp->intf->dev,
4724 "check PHY_NC fail\n");
4728 if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4729 dev_err(&tp->intf->dev,
4730 "multiple PHY NC encountered\n");
4734 if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) {
4735 dev_err(&tp->intf->dev,
4736 "check PHY NC firmware failed\n");
4739 __set_bit(FW_FLAGS_NC, &fw_flags);
4741 case RTL_FW_PHY_UNION_NC:
4742 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4743 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4744 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4745 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4746 test_bit(FW_FLAGS_UC, &fw_flags) ||
4747 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4748 dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n");
4752 if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4753 dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n");
4757 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4758 dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n");
4761 __set_bit(FW_FLAGS_NC, &fw_flags);
4763 case RTL_FW_PHY_UNION_NC1:
4764 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4765 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4766 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4767 test_bit(FW_FLAGS_UC, &fw_flags) ||
4768 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4769 dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n");
4773 if (test_bit(FW_FLAGS_NC1, &fw_flags)) {
4774 dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n");
4778 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4779 dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n");
4782 __set_bit(FW_FLAGS_NC1, &fw_flags);
4784 case RTL_FW_PHY_UNION_NC2:
4785 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4786 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4787 test_bit(FW_FLAGS_UC, &fw_flags) ||
4788 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4789 dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n");
4793 if (test_bit(FW_FLAGS_NC2, &fw_flags)) {
4794 dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n");
4798 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4799 dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n");
4802 __set_bit(FW_FLAGS_NC2, &fw_flags);
4804 case RTL_FW_PHY_UNION_UC2:
4805 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4806 test_bit(FW_FLAGS_UC, &fw_flags) ||
4807 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4808 dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n");
4812 if (test_bit(FW_FLAGS_UC2, &fw_flags)) {
4813 dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n");
4817 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4818 dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n");
4821 __set_bit(FW_FLAGS_UC2, &fw_flags);
4823 case RTL_FW_PHY_UNION_UC:
4824 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4825 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4826 dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n");
4830 if (test_bit(FW_FLAGS_UC, &fw_flags)) {
4831 dev_err(&tp->intf->dev, "multiple PHY UC encountered\n");
4835 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4836 dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n");
4839 __set_bit(FW_FLAGS_UC, &fw_flags);
4841 case RTL_FW_PHY_UNION_MISC:
4842 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4843 dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n");
4847 case RTL_FW_PHY_FIXUP:
4848 if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) {
4849 dev_err(&tp->intf->dev, "check PHY fixup failed\n");
4853 case RTL_FW_PHY_SPEED_UP:
4854 if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {
4855 dev_err(&tp->intf->dev, "multiple PHY firmware encountered");
4859 if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) {
4860 dev_err(&tp->intf->dev, "check PHY speed up failed\n");
4863 __set_bit(FW_FLAGS_SPEED_UP, &fw_flags);
4865 case RTL_FW_PHY_VER:
4866 if (test_bit(FW_FLAGS_START, &fw_flags) ||
4867 test_bit(FW_FLAGS_NC, &fw_flags) ||
4868 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4869 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4870 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4871 test_bit(FW_FLAGS_UC, &fw_flags) ||
4872 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4873 dev_err(&tp->intf->dev, "Invalid order to set PHY version\n");
4877 if (test_bit(FW_FLAGS_VER, &fw_flags)) {
4878 dev_err(&tp->intf->dev, "multiple PHY version encountered");
4882 if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) {
4883 dev_err(&tp->intf->dev, "check PHY version failed\n");
4886 __set_bit(FW_FLAGS_VER, &fw_flags);
4889 dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
4895 i += ALIGN(__le32_to_cpu(block->length), 8);
4899 if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {
4900 dev_err(&tp->intf->dev, "without PHY_STOP\n");
4909 static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)
4914 rtl_reset_ocp_base(tp);
4916 if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {
4917 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4921 len = __le32_to_cpu(phy->blk_hdr.length);
4922 len -= __le16_to_cpu(phy->fw_offset);
4923 data = (u8 *)phy + __le16_to_cpu(phy->fw_offset);
4925 if (rtl_phy_patch_request(tp, true, wait))
4937 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);
4938 ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;
4939 ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data);
4941 generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB);
4946 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);
4947 ocp_data |= POL_GPHY_PATCH;
4948 ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data);
4950 for (i = 0; i < 1000; i++) {
4951 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))
4956 dev_err(&tp->intf->dev, "ram code speedup mode timeout\n");
4961 rtl_reset_ocp_base(tp);
4963 rtl_phy_patch_request(tp, false, wait);
4965 if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))
4966 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4968 dev_err(&tp->intf->dev, "ram code speedup mode fail\n");
4971 static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)
4975 ver_addr = __le16_to_cpu(phy_ver->ver.addr);
4976 ver = __le16_to_cpu(phy_ver->ver.data);
4978 rtl_reset_ocp_base(tp);
4980 if (sram_read(tp, ver_addr) >= ver) {
4981 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4985 sram_write(tp, ver_addr, ver);
4987 dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver);
4992 static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)
4996 rtl_reset_ocp_base(tp);
4998 addr = __le16_to_cpu(fix->setting.addr);
4999 data = ocp_reg_read(tp, addr);
5001 switch (__le16_to_cpu(fix->bit_cmd)) {
5003 data &= __le16_to_cpu(fix->setting.data);
5006 data |= __le16_to_cpu(fix->setting.data);
5009 data &= ~__le16_to_cpu(fix->setting.data);
5012 data ^= __le16_to_cpu(fix->setting.data);
5018 ocp_reg_write(tp, addr, data);
5020 dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data);
5023 static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)
5029 rtl_reset_ocp_base(tp);
5032 for (i = 0; i < num; i++)
5033 sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),
5034 __le16_to_cpu(phy->pre_set[i].data));
5036 length = __le32_to_cpu(phy->blk_hdr.length);
5037 length -= __le16_to_cpu(phy->fw_offset);
5039 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
5041 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
5042 for (i = 0; i < num; i++)
5043 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
5046 for (i = 0; i < num; i++)
5047 sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));
5049 if (phy->bp_num && phy->bp_en.addr)
5050 sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));
5052 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
5055 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
5057 u16 mode_reg, bp_index;
5061 rtl_reset_ocp_base(tp);
5063 mode_reg = __le16_to_cpu(phy->mode_reg);
5064 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
5065 sram_write(tp, __le16_to_cpu(phy->ba_reg),
5066 __le16_to_cpu(phy->ba_data));
5068 length = __le32_to_cpu(phy->blk_hdr.length);
5069 length -= __le16_to_cpu(phy->fw_offset);
5071 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
5073 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
5074 for (i = 0; i < num; i++)
5075 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
5077 sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
5078 __le16_to_cpu(phy->patch_en_value));
5080 bp_index = __le16_to_cpu(phy->bp_start);
5081 num = __le16_to_cpu(phy->bp_num);
5082 for (i = 0; i < num; i++) {
5083 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
5087 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
5089 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
5092 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
5094 u16 bp_en_addr, type, fw_ver_reg;
5098 switch (__le32_to_cpu(mac->blk_hdr.type)) {
5100 type = MCU_TYPE_PLA;
5103 type = MCU_TYPE_USB;
5109 fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
5110 if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) {
5111 dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB");
5115 rtl_clear_bp(tp, type);
5117 /* Enable backup/restore of MACDBG. This is required after clearing PLA
5118 * break points and before applying the PLA firmware.
5120 if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
5121 !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
5122 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
5123 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
5126 length = __le32_to_cpu(mac->blk_hdr.length);
5127 length -= __le16_to_cpu(mac->fw_offset);
5130 data += __le16_to_cpu(mac->fw_offset);
5132 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
5135 ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
5136 __le16_to_cpu(mac->bp_ba_value));
5138 generic_ocp_write(tp, __le16_to_cpu(mac->bp_start), BYTE_EN_DWORD,
5139 __le16_to_cpu(mac->bp_num) << 1, mac->bp, type);
5141 bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
5143 ocp_write_word(tp, type, bp_en_addr,
5144 __le16_to_cpu(mac->bp_en_value));
5147 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
5150 dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
5153 static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
5155 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5156 const struct firmware *fw;
5157 struct fw_header *fw_hdr;
5158 struct fw_phy_patch_key *key;
5160 int i, patch_phy = 1;
5162 if (IS_ERR_OR_NULL(rtl_fw->fw))
5166 fw_hdr = (struct fw_header *)fw->data;
5171 for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
5172 struct fw_block *block = (struct fw_block *)&fw->data[i];
5174 switch (__le32_to_cpu(block->type)) {
5179 rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
5181 case RTL_FW_PHY_START:
5184 key = (struct fw_phy_patch_key *)block;
5185 key_addr = __le16_to_cpu(key->key_reg);
5186 rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);
5188 case RTL_FW_PHY_STOP:
5192 rtl_post_ram_code(tp, key_addr, !power_cut);
5195 rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
5197 case RTL_FW_PHY_VER:
5198 patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block);
5200 case RTL_FW_PHY_UNION_NC:
5201 case RTL_FW_PHY_UNION_NC1:
5202 case RTL_FW_PHY_UNION_NC2:
5203 case RTL_FW_PHY_UNION_UC2:
5204 case RTL_FW_PHY_UNION_UC:
5205 case RTL_FW_PHY_UNION_MISC:
5207 rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block);
5209 case RTL_FW_PHY_FIXUP:
5211 rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block);
5213 case RTL_FW_PHY_SPEED_UP:
5214 rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut);
5220 i += ALIGN(__le32_to_cpu(block->length), 8);
5224 if (rtl_fw->post_fw)
5225 rtl_fw->post_fw(tp);
5227 rtl_reset_ocp_base(tp);
5228 strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
5229 dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
5232 static void rtl8152_release_firmware(struct r8152 *tp)
5234 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5236 if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
5237 release_firmware(rtl_fw->fw);
5242 static int rtl8152_request_firmware(struct r8152 *tp)
5244 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5247 if (rtl_fw->fw || !rtl_fw->fw_name) {
5248 dev_info(&tp->intf->dev, "skip request firmware\n");
5253 rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
5257 rc = rtl8152_check_firmware(tp, rtl_fw);
5259 release_firmware(rtl_fw->fw);
5263 rtl_fw->fw = ERR_PTR(rc);
5265 dev_warn(&tp->intf->dev,
5266 "unable to load firmware patch %s (%ld)\n",
5267 rtl_fw->fw_name, rc);
5273 static void r8152_aldps_en(struct r8152 *tp, bool enable)
5276 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
5277 LINKENA | DIS_SDSAVE);
5279 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
5285 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
5287 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
5288 ocp_reg_write(tp, OCP_EEE_DATA, reg);
5289 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
5292 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
5296 r8152_mmd_indirect(tp, dev, reg);
5297 data = ocp_reg_read(tp, OCP_EEE_DATA);
5298 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5303 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
5305 r8152_mmd_indirect(tp, dev, reg);
5306 ocp_reg_write(tp, OCP_EEE_DATA, data);
5307 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5310 static void r8152_eee_en(struct r8152 *tp, bool enable)
5312 u16 config1, config2, config3;
5315 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5316 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
5317 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
5318 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
5321 ocp_data |= EEE_RX_EN | EEE_TX_EN;
5322 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
5323 config1 |= sd_rise_time(1);
5324 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
5325 config3 |= fast_snr(42);
5327 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5328 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
5330 config1 |= sd_rise_time(7);
5331 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
5332 config3 |= fast_snr(511);
5335 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5336 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
5337 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
5338 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
5341 static void r8153_eee_en(struct r8152 *tp, bool enable)
5346 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5347 config = ocp_reg_read(tp, OCP_EEE_CFG);
5350 ocp_data |= EEE_RX_EN | EEE_TX_EN;
5353 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5354 config &= ~EEE10_EN;
5357 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5358 ocp_reg_write(tp, OCP_EEE_CFG, config);
5360 tp->ups_info.eee = enable;
5363 static void r8156_eee_en(struct r8152 *tp, bool enable)
5367 r8153_eee_en(tp, enable);
5369 config = ocp_reg_read(tp, OCP_EEE_ADV2);
5372 config |= MDIO_EEE_2_5GT;
5374 config &= ~MDIO_EEE_2_5GT;
5376 ocp_reg_write(tp, OCP_EEE_ADV2, config);
5379 static void rtl_eee_enable(struct r8152 *tp, bool enable)
5381 switch (tp->version) {
5386 r8152_eee_en(tp, true);
5387 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
5390 r8152_eee_en(tp, false);
5391 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
5402 r8153_eee_en(tp, true);
5403 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5405 r8153_eee_en(tp, false);
5406 ocp_reg_write(tp, OCP_EEE_ADV, 0);
5415 r8156_eee_en(tp, true);
5416 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5418 r8156_eee_en(tp, false);
5419 ocp_reg_write(tp, OCP_EEE_ADV, 0);
5427 static void r8152b_enable_fc(struct r8152 *tp)
5431 anar = r8152_mdio_read(tp, MII_ADVERTISE);
5432 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
5433 r8152_mdio_write(tp, MII_ADVERTISE, anar);
5435 tp->ups_info.flow_control = true;
5438 static void rtl8152_disable(struct r8152 *tp)
5440 r8152_aldps_en(tp, false);
5442 r8152_aldps_en(tp, true);
5445 static void r8152b_hw_phy_cfg(struct r8152 *tp)
5447 rtl8152_apply_firmware(tp, false);
5448 rtl_eee_enable(tp, tp->eee_en);
5449 r8152_aldps_en(tp, true);
5450 r8152b_enable_fc(tp);
5452 set_bit(PHY_RESET, &tp->flags);
5455 static void wait_oob_link_list_ready(struct r8152 *tp)
5460 for (i = 0; i < 1000; i++) {
5461 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5462 if (ocp_data & LINK_LIST_READY)
5464 usleep_range(1000, 2000);
5468 static void r8156b_wait_loading_flash(struct r8152 *tp)
5470 if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
5471 !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
5474 for (i = 0; i < 100; i++) {
5475 if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
5477 usleep_range(1000, 2000);
5482 static void r8152b_exit_oob(struct r8152 *tp)
5486 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5487 ocp_data &= ~RCR_ACPT_ALL;
5488 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5490 rxdy_gated_en(tp, true);
5491 r8153_teredo_off(tp);
5492 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
5493 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
5495 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5496 ocp_data &= ~NOW_IS_OOB;
5497 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5499 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5500 ocp_data &= ~MCU_BORW_EN;
5501 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5503 wait_oob_link_list_ready(tp);
5505 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5506 ocp_data |= RE_INIT_LL;
5507 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5509 wait_oob_link_list_ready(tp);
5511 rtl8152_nic_reset(tp);
5513 /* rx share fifo credit full threshold */
5514 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5516 if (tp->udev->speed == USB_SPEED_FULL ||
5517 tp->udev->speed == USB_SPEED_LOW) {
5518 /* rx share fifo credit near full threshold */
5519 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5521 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5524 /* rx share fifo credit near full threshold */
5525 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5527 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5531 /* TX share fifo free credit full threshold */
5532 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5534 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
5535 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
5536 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
5537 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
5539 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5541 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5543 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5544 ocp_data |= TCR0_AUTO_FIFO;
5545 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5548 static void r8152b_enter_oob(struct r8152 *tp)
5552 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5553 ocp_data &= ~NOW_IS_OOB;
5554 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5556 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
5557 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
5558 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
5562 wait_oob_link_list_ready(tp);
5564 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5565 ocp_data |= RE_INIT_LL;
5566 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5568 wait_oob_link_list_ready(tp);
5570 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5572 rtl_rx_vlan_en(tp, true);
5574 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5575 ocp_data |= ALDPS_PROXY_MODE;
5576 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5578 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5579 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5580 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5582 rxdy_gated_en(tp, false);
5584 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5585 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5586 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5589 static int r8153_pre_firmware_1(struct r8152 *tp)
5593 /* Wait till the WTD timer is ready. It would take at most 104 ms. */
5594 for (i = 0; i < 104; i++) {
5595 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
5597 if (!(ocp_data & WTD1_EN))
5599 usleep_range(1000, 2000);
5605 static int r8153_post_firmware_1(struct r8152 *tp)
5607 /* set USB_BP_4 to support USB_SPEED_SUPER only */
5608 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
5609 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
5611 /* reset UPHY timer to 36 ms */
5612 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5617 static int r8153_pre_firmware_2(struct r8152 *tp)
5621 r8153_pre_firmware_1(tp);
5623 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5624 ocp_data &= ~FW_FIX_SUSPEND;
5625 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5630 static int r8153_post_firmware_2(struct r8152 *tp)
5634 /* enable bp0 if support USB_SPEED_SUPER only */
5635 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
5636 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5638 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5641 /* reset UPHY timer to 36 ms */
5642 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5644 /* enable U3P3 check, set the counter to 4 */
5645 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
5647 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5648 ocp_data |= FW_FIX_SUSPEND;
5649 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5651 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5652 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5653 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5658 static int r8153_post_firmware_3(struct r8152 *tp)
5662 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5663 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5664 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5666 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5667 ocp_data |= FW_IP_RESET_EN;
5668 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5673 static int r8153b_pre_firmware_1(struct r8152 *tp)
5675 /* enable fc timer and set timer to 1 second. */
5676 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
5677 CTRL_TIMER_EN | (1000 / 8));
5682 static int r8153b_post_firmware_1(struct r8152 *tp)
5686 /* enable bp0 for RTL8153-BND */
5687 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
5688 if (ocp_data & BND_MASK) {
5689 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5691 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5694 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5695 ocp_data |= FLOW_CTRL_PATCH_OPT;
5696 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5698 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5699 ocp_data |= FC_PATCH_TASK;
5700 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5702 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5703 ocp_data |= FW_IP_RESET_EN;
5704 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5709 static int r8153c_post_firmware_1(struct r8152 *tp)
5713 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5714 ocp_data |= FLOW_CTRL_PATCH_2;
5715 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5717 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5718 ocp_data |= FC_PATCH_TASK;
5719 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5724 static int r8156a_post_firmware_1(struct r8152 *tp)
5728 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5729 ocp_data |= FW_IP_RESET_EN;
5730 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5732 /* Modify U3PHY parameter for compatibility issue */
5733 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e);
5734 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9);
5739 static void r8153_aldps_en(struct r8152 *tp, bool enable)
5743 data = ocp_reg_read(tp, OCP_POWER_CFG);
5746 ocp_reg_write(tp, OCP_POWER_CFG, data);
5751 ocp_reg_write(tp, OCP_POWER_CFG, data);
5752 for (i = 0; i < 20; i++) {
5753 usleep_range(1000, 2000);
5754 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
5759 tp->ups_info.aldps = enable;
5762 static void r8153_hw_phy_cfg(struct r8152 *tp)
5767 /* disable ALDPS before updating the PHY parameters */
5768 r8153_aldps_en(tp, false);
5770 /* disable EEE before updating the PHY parameters */
5771 rtl_eee_enable(tp, false);
5773 rtl8152_apply_firmware(tp, false);
5775 if (tp->version == RTL_VER_03) {
5776 data = ocp_reg_read(tp, OCP_EEE_CFG);
5777 data &= ~CTAP_SHORT_EN;
5778 ocp_reg_write(tp, OCP_EEE_CFG, data);
5781 data = ocp_reg_read(tp, OCP_POWER_CFG);
5782 data |= EEE_CLKDIV_EN;
5783 ocp_reg_write(tp, OCP_POWER_CFG, data);
5785 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5786 data |= EN_10M_BGOFF;
5787 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5788 data = ocp_reg_read(tp, OCP_POWER_CFG);
5789 data |= EN_10M_PLLOFF;
5790 ocp_reg_write(tp, OCP_POWER_CFG, data);
5791 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
5793 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5794 ocp_data |= PFM_PWM_SWITCH;
5795 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5797 /* Enable LPF corner auto tune */
5798 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
5800 /* Adjust 10M Amplitude */
5801 sram_write(tp, SRAM_10M_AMP1, 0x00af);
5802 sram_write(tp, SRAM_10M_AMP2, 0x0208);
5805 rtl_eee_enable(tp, true);
5807 r8153_aldps_en(tp, true);
5808 r8152b_enable_fc(tp);
5810 switch (tp->version) {
5817 r8153_u2p3en(tp, true);
5821 set_bit(PHY_RESET, &tp->flags);
5824 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
5828 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
5829 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
5830 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
5831 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
5836 static void r8153b_hw_phy_cfg(struct r8152 *tp)
5841 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
5842 if (ocp_data & PCUT_STATUS) {
5843 ocp_data &= ~PCUT_STATUS;
5844 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
5847 /* disable ALDPS before updating the PHY parameters */
5848 r8153_aldps_en(tp, false);
5850 /* disable EEE before updating the PHY parameters */
5851 rtl_eee_enable(tp, false);
5853 /* U1/U2/L1 idle timer. 500 us */
5854 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5856 data = r8153_phy_status(tp, 0);
5859 case PHY_STAT_PWRDN:
5860 case PHY_STAT_EXT_INIT:
5861 rtl8152_apply_firmware(tp, true);
5863 data = r8152_mdio_read(tp, MII_BMCR);
5864 data &= ~BMCR_PDOWN;
5865 r8152_mdio_write(tp, MII_BMCR, data);
5867 case PHY_STAT_LAN_ON:
5869 rtl8152_apply_firmware(tp, false);
5873 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
5875 data = sram_read(tp, SRAM_GREEN_CFG);
5877 sram_write(tp, SRAM_GREEN_CFG, data);
5878 data = ocp_reg_read(tp, OCP_NCTL_CFG);
5879 data |= PGA_RETURN_EN;
5880 ocp_reg_write(tp, OCP_NCTL_CFG, data);
5882 /* ADC Bias Calibration:
5883 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
5884 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
5887 ocp_data = r8152_efuse_read(tp, 0x7d);
5888 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
5890 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
5892 /* ups mode tx-link-pulse timing adjustment:
5893 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
5894 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
5896 ocp_data = ocp_reg_read(tp, 0xc426);
5899 u32 swr_cnt_1ms_ini;
5901 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
5902 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
5903 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
5904 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
5907 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5908 ocp_data |= PFM_PWM_SWITCH;
5909 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5912 if (!rtl_phy_patch_request(tp, true, true)) {
5913 data = ocp_reg_read(tp, OCP_POWER_CFG);
5914 data |= EEE_CLKDIV_EN;
5915 ocp_reg_write(tp, OCP_POWER_CFG, data);
5916 tp->ups_info.eee_ckdiv = true;
5918 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5919 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
5920 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5921 tp->ups_info.eee_cmod_lv = true;
5922 tp->ups_info._10m_ckdiv = true;
5923 tp->ups_info.eee_plloff_giga = true;
5925 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
5926 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
5927 tp->ups_info._250m_ckdiv = true;
5929 rtl_phy_patch_request(tp, false, true);
5933 rtl_eee_enable(tp, true);
5935 r8153_aldps_en(tp, true);
5936 r8152b_enable_fc(tp);
5938 set_bit(PHY_RESET, &tp->flags);
5941 static void r8153c_hw_phy_cfg(struct r8152 *tp)
5943 r8153b_hw_phy_cfg(tp);
5945 tp->ups_info.r_tune = true;
5948 static void rtl8153_change_mtu(struct r8152 *tp)
5950 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5951 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
5954 static void r8153_first_init(struct r8152 *tp)
5958 rxdy_gated_en(tp, true);
5959 r8153_teredo_off(tp);
5961 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5962 ocp_data &= ~RCR_ACPT_ALL;
5963 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5965 rtl8152_nic_reset(tp);
5968 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5969 ocp_data &= ~NOW_IS_OOB;
5970 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5972 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5973 ocp_data &= ~MCU_BORW_EN;
5974 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5976 wait_oob_link_list_ready(tp);
5978 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5979 ocp_data |= RE_INIT_LL;
5980 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5982 wait_oob_link_list_ready(tp);
5984 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5986 rtl8153_change_mtu(tp);
5988 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5989 ocp_data |= TCR0_AUTO_FIFO;
5990 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5992 rtl8152_nic_reset(tp);
5994 /* rx share fifo credit full threshold */
5995 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5996 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
5997 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
5998 /* TX share fifo free credit full threshold */
5999 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
6002 static void r8153_enter_oob(struct r8152 *tp)
6006 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6007 ocp_data &= ~NOW_IS_OOB;
6008 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6010 /* RX FIFO settings for OOB */
6011 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
6012 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
6013 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
6018 wait_oob_link_list_ready(tp);
6020 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6021 ocp_data |= RE_INIT_LL;
6022 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6024 wait_oob_link_list_ready(tp);
6026 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522);
6027 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
6029 switch (tp->version) {
6034 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
6035 ocp_data &= ~TEREDO_WAKE_MASK;
6036 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
6042 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
6043 * type. Set it to zero. bits[7:0] are the W1C bits about
6044 * the events. Set them to all 1 to clear them.
6046 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
6053 rtl_rx_vlan_en(tp, true);
6055 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
6056 ocp_data |= ALDPS_PROXY_MODE;
6057 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
6059 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6060 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
6061 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6063 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6064 ocp_data |= MCU_BORW_EN;
6065 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6067 rxdy_gated_en(tp, false);
6069 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6070 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6071 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6074 static void rtl8153_disable(struct r8152 *tp)
6076 r8153_aldps_en(tp, false);
6079 r8153_aldps_en(tp, true);
6082 static u32 fc_pause_on_auto(struct r8152 *tp)
6084 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
6087 static u32 fc_pause_off_auto(struct r8152 *tp)
6089 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
6092 static void r8156_fc_parameter(struct r8152 *tp)
6094 u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
6095 u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
6097 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16);
6098 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16);
6101 static int rtl8156_enable(struct r8152 *tp)
6106 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6109 r8156_fc_parameter(tp);
6111 rtl_set_eee_plus(tp);
6112 r8153_set_rx_early_timeout(tp);
6113 r8153_set_rx_early_size(tp);
6115 speed = rtl8152_get_speed(tp);
6116 rtl_set_ifg(tp, speed);
6118 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6119 if (speed & _2500bps)
6120 ocp_data &= ~IDLE_SPDWN_EN;
6122 ocp_data |= IDLE_SPDWN_EN;
6123 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
6125 if (speed & _1000bps)
6126 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);
6127 else if (speed & _500bps)
6128 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d);
6130 if (tp->udev->speed == USB_SPEED_HIGH) {
6131 /* USB 0xb45e[3:0] l1_nyet_hird */
6132 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6134 if (is_flow_control(speed))
6138 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6141 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6142 ocp_data &= ~FC_PATCH_TASK;
6143 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6144 usleep_range(1000, 2000);
6145 ocp_data |= FC_PATCH_TASK;
6146 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6148 return rtl_enable(tp);
6151 static void rtl8156_disable(struct r8152 *tp)
6153 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 0);
6154 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 0);
6156 rtl8153_disable(tp);
6159 static int rtl8156b_enable(struct r8152 *tp)
6164 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6168 rtl_set_eee_plus(tp);
6170 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
6171 ocp_data &= ~RX_AGGR_NUM_MASK;
6172 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);
6174 r8153_set_rx_early_timeout(tp);
6175 r8153_set_rx_early_size(tp);
6177 speed = rtl8152_get_speed(tp);
6178 rtl_set_ifg(tp, speed);
6180 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6181 if (speed & _2500bps)
6182 ocp_data &= ~IDLE_SPDWN_EN;
6184 ocp_data |= IDLE_SPDWN_EN;
6185 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
6187 if (tp->udev->speed == USB_SPEED_HIGH) {
6188 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6190 if (is_flow_control(speed))
6194 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6197 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6198 ocp_data &= ~FC_PATCH_TASK;
6199 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6200 usleep_range(1000, 2000);
6201 ocp_data |= FC_PATCH_TASK;
6202 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6204 return rtl_enable(tp);
6207 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
6213 if (autoneg == AUTONEG_DISABLE) {
6214 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
6219 bmcr = BMCR_SPEED10;
6220 if (duplex == DUPLEX_FULL) {
6221 bmcr |= BMCR_FULLDPLX;
6222 tp->ups_info.speed_duplex = FORCE_10M_FULL;
6224 tp->ups_info.speed_duplex = FORCE_10M_HALF;
6228 bmcr = BMCR_SPEED100;
6229 if (duplex == DUPLEX_FULL) {
6230 bmcr |= BMCR_FULLDPLX;
6231 tp->ups_info.speed_duplex = FORCE_100M_FULL;
6233 tp->ups_info.speed_duplex = FORCE_100M_HALF;
6237 if (tp->mii.supports_gmii) {
6238 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
6239 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6248 if (duplex == DUPLEX_FULL)
6249 tp->mii.full_duplex = 1;
6251 tp->mii.full_duplex = 0;
6253 tp->mii.force_media = 1;
6258 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6259 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6261 if (tp->mii.supports_gmii) {
6262 support |= RTL_ADVERTISED_1000_FULL;
6264 if (tp->support_2500full)
6265 support |= RTL_ADVERTISED_2500_FULL;
6268 if (!(advertising & support))
6271 orig = r8152_mdio_read(tp, MII_ADVERTISE);
6272 new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
6273 ADVERTISE_100HALF | ADVERTISE_100FULL);
6274 if (advertising & RTL_ADVERTISED_10_HALF) {
6275 new1 |= ADVERTISE_10HALF;
6276 tp->ups_info.speed_duplex = NWAY_10M_HALF;
6278 if (advertising & RTL_ADVERTISED_10_FULL) {
6279 new1 |= ADVERTISE_10FULL;
6280 tp->ups_info.speed_duplex = NWAY_10M_FULL;
6283 if (advertising & RTL_ADVERTISED_100_HALF) {
6284 new1 |= ADVERTISE_100HALF;
6285 tp->ups_info.speed_duplex = NWAY_100M_HALF;
6287 if (advertising & RTL_ADVERTISED_100_FULL) {
6288 new1 |= ADVERTISE_100FULL;
6289 tp->ups_info.speed_duplex = NWAY_100M_FULL;
6293 r8152_mdio_write(tp, MII_ADVERTISE, new1);
6294 tp->mii.advertising = new1;
6297 if (tp->mii.supports_gmii) {
6298 orig = r8152_mdio_read(tp, MII_CTRL1000);
6299 new1 = orig & ~(ADVERTISE_1000FULL |
6300 ADVERTISE_1000HALF);
6302 if (advertising & RTL_ADVERTISED_1000_FULL) {
6303 new1 |= ADVERTISE_1000FULL;
6304 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6308 r8152_mdio_write(tp, MII_CTRL1000, new1);
6311 if (tp->support_2500full) {
6312 orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
6313 new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
6315 if (advertising & RTL_ADVERTISED_2500_FULL) {
6316 new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
6317 tp->ups_info.speed_duplex = NWAY_2500M_FULL;
6321 ocp_reg_write(tp, OCP_10GBT_CTRL, new1);
6324 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
6326 tp->mii.force_media = 0;
6329 if (test_and_clear_bit(PHY_RESET, &tp->flags))
6332 r8152_mdio_write(tp, MII_BMCR, bmcr);
6334 if (bmcr & BMCR_RESET) {
6337 for (i = 0; i < 50; i++) {
6339 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
6348 static void rtl8152_up(struct r8152 *tp)
6350 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6353 r8152_aldps_en(tp, false);
6354 r8152b_exit_oob(tp);
6355 r8152_aldps_en(tp, true);
6358 static void rtl8152_down(struct r8152 *tp)
6360 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6361 rtl_drop_queued_tx(tp);
6365 r8152_power_cut_en(tp, false);
6366 r8152_aldps_en(tp, false);
6367 r8152b_enter_oob(tp);
6368 r8152_aldps_en(tp, true);
6371 static void rtl8153_up(struct r8152 *tp)
6375 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6378 r8153_u1u2en(tp, false);
6379 r8153_u2p3en(tp, false);
6380 r8153_aldps_en(tp, false);
6381 r8153_first_init(tp);
6383 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6384 ocp_data |= LANWAKE_CLR_EN;
6385 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6387 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6388 ocp_data &= ~LANWAKE_PIN;
6389 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
6391 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
6392 ocp_data &= ~DELAY_PHY_PWR_CHG;
6393 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
6395 r8153_aldps_en(tp, true);
6397 switch (tp->version) {
6404 r8153_u2p3en(tp, true);
6408 r8153_u1u2en(tp, true);
6411 static void rtl8153_down(struct r8152 *tp)
6415 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6416 rtl_drop_queued_tx(tp);
6420 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6421 ocp_data &= ~LANWAKE_CLR_EN;
6422 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6424 r8153_u1u2en(tp, false);
6425 r8153_u2p3en(tp, false);
6426 r8153_power_cut_en(tp, false);
6427 r8153_aldps_en(tp, false);
6428 r8153_enter_oob(tp);
6429 r8153_aldps_en(tp, true);
6432 static void rtl8153b_up(struct r8152 *tp)
6436 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6439 r8153b_u1u2en(tp, false);
6440 r8153_u2p3en(tp, false);
6441 r8153_aldps_en(tp, false);
6443 r8153_first_init(tp);
6444 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6446 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6447 ocp_data &= ~PLA_MCU_SPDWN_EN;
6448 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6450 r8153_aldps_en(tp, true);
6452 if (tp->udev->speed >= USB_SPEED_SUPER)
6453 r8153b_u1u2en(tp, true);
6456 static void rtl8153b_down(struct r8152 *tp)
6460 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6461 rtl_drop_queued_tx(tp);
6465 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6466 ocp_data |= PLA_MCU_SPDWN_EN;
6467 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6469 r8153b_u1u2en(tp, false);
6470 r8153_u2p3en(tp, false);
6471 r8153b_power_cut_en(tp, false);
6472 r8153_aldps_en(tp, false);
6473 r8153_enter_oob(tp);
6474 r8153_aldps_en(tp, true);
6477 static void rtl8153c_change_mtu(struct r8152 *tp)
6479 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
6480 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64);
6482 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6484 /* Adjust the tx fifo free credit full threshold, otherwise
6485 * the fifo would be too small to send a jumbo frame packet.
6487 if (tp->netdev->mtu < 8000)
6488 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8);
6490 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8);
6493 static void rtl8153c_up(struct r8152 *tp)
6497 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6500 r8153b_u1u2en(tp, false);
6501 r8153_u2p3en(tp, false);
6502 r8153_aldps_en(tp, false);
6504 rxdy_gated_en(tp, true);
6505 r8153_teredo_off(tp);
6507 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6508 ocp_data &= ~RCR_ACPT_ALL;
6509 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6511 rtl8152_nic_reset(tp);
6514 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6515 ocp_data &= ~NOW_IS_OOB;
6516 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6518 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6519 ocp_data &= ~MCU_BORW_EN;
6520 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6522 wait_oob_link_list_ready(tp);
6524 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6525 ocp_data |= RE_INIT_LL;
6526 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6528 wait_oob_link_list_ready(tp);
6530 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6532 rtl8153c_change_mtu(tp);
6534 rtl8152_nic_reset(tp);
6536 /* rx share fifo credit full threshold */
6537 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02);
6538 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08);
6539 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6540 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6542 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6544 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
6546 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
6548 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
6550 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
6552 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6553 ocp_data &= ~PLA_MCU_SPDWN_EN;
6554 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6556 r8153_aldps_en(tp, true);
6557 r8153b_u1u2en(tp, true);
6560 static void rtl8156_change_mtu(struct r8152 *tp)
6562 u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
6564 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size);
6565 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
6566 r8156_fc_parameter(tp);
6568 /* TX share fifo free credit full threshold */
6569 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6570 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
6571 ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
6574 static void rtl8156_up(struct r8152 *tp)
6578 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6581 r8153b_u1u2en(tp, false);
6582 r8153_u2p3en(tp, false);
6583 r8153_aldps_en(tp, false);
6585 rxdy_gated_en(tp, true);
6586 r8153_teredo_off(tp);
6588 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6589 ocp_data &= ~RCR_ACPT_ALL;
6590 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6592 rtl8152_nic_reset(tp);
6595 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6596 ocp_data &= ~NOW_IS_OOB;
6597 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6599 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6600 ocp_data &= ~MCU_BORW_EN;
6601 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6603 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6605 rtl8156_change_mtu(tp);
6607 switch (tp->version) {
6611 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
6612 ocp_data |= ACT_ODMA;
6613 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
6619 /* share FIFO settings */
6620 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
6621 ocp_data &= ~RXFIFO_FULL_MASK;
6623 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);
6625 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6626 ocp_data &= ~PLA_MCU_SPDWN_EN;
6627 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6629 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
6630 ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
6631 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);
6633 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);
6635 if (tp->saved_wolopts != __rtl_get_wol(tp)) {
6636 netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
6637 __rtl_set_wol(tp, tp->saved_wolopts);
6640 r8153_aldps_en(tp, true);
6641 r8153_u2p3en(tp, true);
6643 if (tp->udev->speed >= USB_SPEED_SUPER)
6644 r8153b_u1u2en(tp, true);
6647 static void rtl8156_down(struct r8152 *tp)
6651 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6652 rtl_drop_queued_tx(tp);
6656 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6657 ocp_data |= PLA_MCU_SPDWN_EN;
6658 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6660 r8153b_u1u2en(tp, false);
6661 r8153_u2p3en(tp, false);
6662 r8153b_power_cut_en(tp, false);
6663 r8153_aldps_en(tp, false);
6665 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6666 ocp_data &= ~NOW_IS_OOB;
6667 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6669 /* RX FIFO settings for OOB */
6670 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 64 / 16);
6671 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 1024 / 16);
6672 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 4096 / 16);
6677 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522);
6678 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
6680 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
6681 * type. Set it to zero. bits[7:0] are the W1C bits about
6682 * the events. Set them to all 1 to clear them.
6684 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
6686 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6687 ocp_data |= NOW_IS_OOB;
6688 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6690 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6691 ocp_data |= MCU_BORW_EN;
6692 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6694 rtl_rx_vlan_en(tp, true);
6695 rxdy_gated_en(tp, false);
6697 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6698 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6699 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6701 r8153_aldps_en(tp, true);
6704 static bool rtl8152_in_nway(struct r8152 *tp)
6708 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
6709 tp->ocp_base = 0x2000;
6710 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
6711 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
6713 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
6714 if (nway_state & 0xc000)
6720 static bool rtl8153_in_nway(struct r8152 *tp)
6722 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
6724 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
6730 static void r8156_mdio_force_mode(struct r8152 *tp)
6734 /* Select force mode through 0xa5b4 bit 15
6735 * 0: MDIO force mode
6738 data = ocp_reg_read(tp, 0xa5b4);
6739 if (data & BIT(15)) {
6741 ocp_reg_write(tp, 0xa5b4, data);
6745 static void set_carrier(struct r8152 *tp)
6747 struct net_device *netdev = tp->netdev;
6748 struct napi_struct *napi = &tp->napi;
6751 speed = rtl8152_get_speed(tp);
6753 if (speed & LINK_STATUS) {
6754 if (!netif_carrier_ok(netdev)) {
6755 tp->rtl_ops.enable(tp);
6756 netif_stop_queue(netdev);
6758 netif_carrier_on(netdev);
6760 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6761 _rtl8152_set_rx_mode(netdev);
6763 netif_wake_queue(netdev);
6764 netif_info(tp, link, netdev, "carrier on\n");
6765 } else if (netif_queue_stopped(netdev) &&
6766 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
6767 netif_wake_queue(netdev);
6770 if (netif_carrier_ok(netdev)) {
6771 netif_carrier_off(netdev);
6772 tasklet_disable(&tp->tx_tl);
6774 tp->rtl_ops.disable(tp);
6776 tasklet_enable(&tp->tx_tl);
6777 netif_info(tp, link, netdev, "carrier off\n");
6782 static void rtl_work_func_t(struct work_struct *work)
6784 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
6786 /* If the device is unplugged or !netif_running(), the workqueue
6787 * doesn't need to wake the device, and could return directly.
6789 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || !netif_running(tp->netdev))
6792 if (usb_autopm_get_interface(tp->intf) < 0)
6795 if (!test_bit(WORK_ENABLE, &tp->flags))
6798 if (!mutex_trylock(&tp->control)) {
6799 schedule_delayed_work(&tp->schedule, 0);
6803 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
6806 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
6807 _rtl8152_set_rx_mode(tp->netdev);
6809 /* don't schedule tasket before linking */
6810 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
6811 netif_carrier_ok(tp->netdev))
6812 tasklet_schedule(&tp->tx_tl);
6814 if (test_and_clear_bit(RX_EPROTO, &tp->flags) &&
6815 !list_empty(&tp->rx_done))
6816 napi_schedule(&tp->napi);
6818 mutex_unlock(&tp->control);
6821 usb_autopm_put_interface(tp->intf);
6824 static void rtl_hw_phy_work_func_t(struct work_struct *work)
6826 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
6828 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6831 if (usb_autopm_get_interface(tp->intf) < 0)
6834 mutex_lock(&tp->control);
6836 if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
6837 tp->rtl_fw.retry = false;
6838 tp->rtl_fw.fw = NULL;
6840 /* Delay execution in case request_firmware() is not ready yet.
6842 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
6846 tp->rtl_ops.hw_phy_cfg(tp);
6848 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
6852 mutex_unlock(&tp->control);
6854 usb_autopm_put_interface(tp->intf);
6857 #ifdef CONFIG_PM_SLEEP
6858 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
6861 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
6864 case PM_HIBERNATION_PREPARE:
6865 case PM_SUSPEND_PREPARE:
6866 usb_autopm_get_interface(tp->intf);
6869 case PM_POST_HIBERNATION:
6870 case PM_POST_SUSPEND:
6871 usb_autopm_put_interface(tp->intf);
6874 case PM_POST_RESTORE:
6875 case PM_RESTORE_PREPARE:
6884 static int rtl8152_open(struct net_device *netdev)
6886 struct r8152 *tp = netdev_priv(netdev);
6889 if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
6890 cancel_delayed_work_sync(&tp->hw_phy_work);
6891 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
6894 res = alloc_all_mem(tp);
6898 res = usb_autopm_get_interface(tp->intf);
6902 mutex_lock(&tp->control);
6906 netif_carrier_off(netdev);
6907 netif_start_queue(netdev);
6908 set_bit(WORK_ENABLE, &tp->flags);
6910 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
6913 netif_device_detach(tp->netdev);
6914 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
6918 napi_enable(&tp->napi);
6919 tasklet_enable(&tp->tx_tl);
6921 mutex_unlock(&tp->control);
6923 usb_autopm_put_interface(tp->intf);
6924 #ifdef CONFIG_PM_SLEEP
6925 tp->pm_notifier.notifier_call = rtl_notifier;
6926 register_pm_notifier(&tp->pm_notifier);
6931 mutex_unlock(&tp->control);
6932 usb_autopm_put_interface(tp->intf);
6939 static int rtl8152_close(struct net_device *netdev)
6941 struct r8152 *tp = netdev_priv(netdev);
6944 #ifdef CONFIG_PM_SLEEP
6945 unregister_pm_notifier(&tp->pm_notifier);
6947 tasklet_disable(&tp->tx_tl);
6948 clear_bit(WORK_ENABLE, &tp->flags);
6949 usb_kill_urb(tp->intr_urb);
6950 cancel_delayed_work_sync(&tp->schedule);
6951 napi_disable(&tp->napi);
6952 netif_stop_queue(netdev);
6954 res = usb_autopm_get_interface(tp->intf);
6955 if (res < 0 || test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6956 rtl_drop_queued_tx(tp);
6959 mutex_lock(&tp->control);
6961 tp->rtl_ops.down(tp);
6963 mutex_unlock(&tp->control);
6967 usb_autopm_put_interface(tp->intf);
6974 static void rtl_tally_reset(struct r8152 *tp)
6978 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
6979 ocp_data |= TALLY_RESET;
6980 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
6983 static void r8152b_init(struct r8152 *tp)
6988 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6991 data = r8152_mdio_read(tp, MII_BMCR);
6992 if (data & BMCR_PDOWN) {
6993 data &= ~BMCR_PDOWN;
6994 r8152_mdio_write(tp, MII_BMCR, data);
6997 r8152_aldps_en(tp, false);
6999 if (tp->version == RTL_VER_01) {
7000 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
7001 ocp_data &= ~LED_MODE_MASK;
7002 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
7005 r8152_power_cut_en(tp, false);
7007 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7008 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
7009 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7010 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
7011 ocp_data &= ~MCU_CLK_RATIO_MASK;
7012 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
7013 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
7014 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
7015 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
7016 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
7018 rtl_tally_reset(tp);
7020 /* enable rx aggregation */
7021 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7022 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7023 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7026 static void r8153_init(struct r8152 *tp)
7032 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7035 r8153_u1u2en(tp, false);
7037 for (i = 0; i < 500; i++) {
7038 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7043 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7047 data = r8153_phy_status(tp, 0);
7049 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
7050 tp->version == RTL_VER_05)
7051 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
7053 data = r8152_mdio_read(tp, MII_BMCR);
7054 if (data & BMCR_PDOWN) {
7055 data &= ~BMCR_PDOWN;
7056 r8152_mdio_write(tp, MII_BMCR, data);
7059 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7061 r8153_u2p3en(tp, false);
7063 if (tp->version == RTL_VER_04) {
7064 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
7065 ocp_data &= ~pwd_dn_scale_mask;
7066 ocp_data |= pwd_dn_scale(96);
7067 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
7069 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
7070 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
7071 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
7072 } else if (tp->version == RTL_VER_05) {
7073 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
7074 ocp_data &= ~ECM_ALDPS;
7075 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
7077 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
7078 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
7079 ocp_data &= ~DYNAMIC_BURST;
7081 ocp_data |= DYNAMIC_BURST;
7082 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
7083 } else if (tp->version == RTL_VER_06) {
7084 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
7085 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
7086 ocp_data &= ~DYNAMIC_BURST;
7088 ocp_data |= DYNAMIC_BURST;
7089 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
7091 r8153_queue_wake(tp, false);
7093 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7094 if (rtl8152_get_speed(tp) & LINK_STATUS)
7095 ocp_data |= CUR_LINK_OK;
7097 ocp_data &= ~CUR_LINK_OK;
7098 ocp_data |= POLL_LINK_CHG;
7099 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7102 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
7103 ocp_data |= EP4_FULL_FC;
7104 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
7106 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
7107 ocp_data &= ~TIMER11_EN;
7108 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
7110 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
7111 ocp_data &= ~LED_MODE_MASK;
7112 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
7114 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
7115 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
7116 ocp_data |= LPM_TIMER_500MS;
7118 ocp_data |= LPM_TIMER_500US;
7119 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
7121 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
7122 ocp_data &= ~SEN_VAL_MASK;
7123 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
7124 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
7126 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
7128 r8153_power_cut_en(tp, false);
7129 rtl_runtime_suspend_enable(tp, false);
7130 r8153_mac_clk_speed_down(tp, false);
7131 r8153_u1u2en(tp, true);
7132 usb_enable_lpm(tp->udev);
7134 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
7135 ocp_data |= LANWAKE_CLR_EN;
7136 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
7138 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
7139 ocp_data &= ~LANWAKE_PIN;
7140 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
7142 /* rx aggregation */
7143 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7144 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7145 if (tp->dell_tb_rx_agg_bug)
7146 ocp_data |= RX_AGG_DISABLE;
7148 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7150 rtl_tally_reset(tp);
7152 switch (tp->udev->speed) {
7153 case USB_SPEED_SUPER:
7154 case USB_SPEED_SUPER_PLUS:
7155 tp->coalesce = COALESCE_SUPER;
7157 case USB_SPEED_HIGH:
7158 tp->coalesce = COALESCE_HIGH;
7161 tp->coalesce = COALESCE_SLOW;
7166 static void r8153b_init(struct r8152 *tp)
7172 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7175 r8153b_u1u2en(tp, false);
7177 for (i = 0; i < 500; i++) {
7178 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7183 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7187 data = r8153_phy_status(tp, 0);
7189 data = r8152_mdio_read(tp, MII_BMCR);
7190 if (data & BMCR_PDOWN) {
7191 data &= ~BMCR_PDOWN;
7192 r8152_mdio_write(tp, MII_BMCR, data);
7195 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7197 r8153_u2p3en(tp, false);
7199 /* MSC timer = 0xfff * 8ms = 32760 ms */
7200 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7202 r8153b_power_cut_en(tp, false);
7203 r8153b_ups_en(tp, false);
7204 r8153_queue_wake(tp, false);
7205 rtl_runtime_suspend_enable(tp, false);
7207 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7208 if (rtl8152_get_speed(tp) & LINK_STATUS)
7209 ocp_data |= CUR_LINK_OK;
7211 ocp_data &= ~CUR_LINK_OK;
7212 ocp_data |= POLL_LINK_CHG;
7213 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7215 if (tp->udev->speed >= USB_SPEED_SUPER)
7216 r8153b_u1u2en(tp, true);
7218 usb_enable_lpm(tp->udev);
7220 /* MAC clock speed down */
7221 r8153_mac_clk_speed_down(tp, true);
7223 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7224 ocp_data &= ~PLA_MCU_SPDWN_EN;
7225 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
7227 if (tp->version == RTL_VER_09) {
7228 /* Disable Test IO for 32QFN */
7229 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
7230 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7231 ocp_data |= TEST_IO_OFF;
7232 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7236 set_bit(GREEN_ETHERNET, &tp->flags);
7238 /* rx aggregation */
7239 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7240 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7241 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7243 rtl_tally_reset(tp);
7245 tp->coalesce = 15000; /* 15 us */
7248 static void r8153c_init(struct r8152 *tp)
7254 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7257 r8153b_u1u2en(tp, false);
7259 /* Disable spi_en */
7260 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
7261 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
7262 ocp_data &= ~BIT(3);
7263 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
7264 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);
7266 ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);
7268 for (i = 0; i < 500; i++) {
7269 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7274 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7278 data = r8153_phy_status(tp, 0);
7280 data = r8152_mdio_read(tp, MII_BMCR);
7281 if (data & BMCR_PDOWN) {
7282 data &= ~BMCR_PDOWN;
7283 r8152_mdio_write(tp, MII_BMCR, data);
7286 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7288 r8153_u2p3en(tp, false);
7290 /* MSC timer = 0xfff * 8ms = 32760 ms */
7291 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7293 r8153b_power_cut_en(tp, false);
7294 r8153c_ups_en(tp, false);
7295 r8153_queue_wake(tp, false);
7296 rtl_runtime_suspend_enable(tp, false);
7298 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7299 if (rtl8152_get_speed(tp) & LINK_STATUS)
7300 ocp_data |= CUR_LINK_OK;
7302 ocp_data &= ~CUR_LINK_OK;
7304 ocp_data |= POLL_LINK_CHG;
7305 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7307 r8153b_u1u2en(tp, true);
7309 usb_enable_lpm(tp->udev);
7311 /* MAC clock speed down */
7312 r8153_mac_clk_speed_down(tp, true);
7314 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
7315 ocp_data &= ~BIT(7);
7316 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
7318 set_bit(GREEN_ETHERNET, &tp->flags);
7320 /* rx aggregation */
7321 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7322 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7323 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7325 rtl_tally_reset(tp);
7327 tp->coalesce = 15000; /* 15 us */
7330 static void r8156_hw_phy_cfg(struct r8152 *tp)
7335 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7336 if (ocp_data & PCUT_STATUS) {
7337 ocp_data &= ~PCUT_STATUS;
7338 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7341 data = r8153_phy_status(tp, 0);
7343 case PHY_STAT_EXT_INIT:
7344 rtl8152_apply_firmware(tp, true);
7346 data = ocp_reg_read(tp, 0xa468);
7347 data &= ~(BIT(3) | BIT(1));
7348 ocp_reg_write(tp, 0xa468, data);
7350 case PHY_STAT_LAN_ON:
7351 case PHY_STAT_PWRDN:
7353 rtl8152_apply_firmware(tp, false);
7357 /* disable ALDPS before updating the PHY parameters */
7358 r8153_aldps_en(tp, false);
7360 /* disable EEE before updating the PHY parameters */
7361 rtl_eee_enable(tp, false);
7363 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7364 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7366 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7367 ocp_data |= PFM_PWM_SWITCH;
7368 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7370 switch (tp->version) {
7372 data = ocp_reg_read(tp, 0xad40);
7374 data |= BIT(7) | BIT(2);
7375 ocp_reg_write(tp, 0xad40, data);
7377 data = ocp_reg_read(tp, 0xad4e);
7379 ocp_reg_write(tp, 0xad4e, data);
7380 data = ocp_reg_read(tp, 0xad16);
7383 ocp_reg_write(tp, 0xad16, data);
7384 data = ocp_reg_read(tp, 0xad32);
7387 ocp_reg_write(tp, 0xad32, data);
7388 data = ocp_reg_read(tp, 0xac08);
7389 data &= ~(BIT(12) | BIT(8));
7390 ocp_reg_write(tp, 0xac08, data);
7391 data = ocp_reg_read(tp, 0xac8a);
7392 data |= BIT(12) | BIT(13) | BIT(14);
7394 ocp_reg_write(tp, 0xac8a, data);
7395 data = ocp_reg_read(tp, 0xad18);
7397 ocp_reg_write(tp, 0xad18, data);
7398 data = ocp_reg_read(tp, 0xad1a);
7400 ocp_reg_write(tp, 0xad1a, data);
7401 data = ocp_reg_read(tp, 0xad1c);
7403 ocp_reg_write(tp, 0xad1c, data);
7405 data = sram_read(tp, 0x80ea);
7408 sram_write(tp, 0x80ea, data);
7409 data = sram_read(tp, 0x80eb);
7412 sram_write(tp, 0x80eb, data);
7413 data = sram_read(tp, 0x80f8);
7416 sram_write(tp, 0x80f8, data);
7417 data = sram_read(tp, 0x80f1);
7420 sram_write(tp, 0x80f1, data);
7422 data = sram_read(tp, 0x80fe);
7425 sram_write(tp, 0x80fe, data);
7426 data = sram_read(tp, 0x8102);
7429 sram_write(tp, 0x8102, data);
7430 data = sram_read(tp, 0x8015);
7433 sram_write(tp, 0x8015, data);
7434 data = sram_read(tp, 0x8100);
7437 sram_write(tp, 0x8100, data);
7438 data = sram_read(tp, 0x8014);
7441 sram_write(tp, 0x8014, data);
7442 data = sram_read(tp, 0x8016);
7445 sram_write(tp, 0x8016, data);
7446 data = sram_read(tp, 0x80dc);
7449 sram_write(tp, 0x80dc, data);
7450 data = sram_read(tp, 0x80df);
7452 sram_write(tp, 0x80df, data);
7453 data = sram_read(tp, 0x80e1);
7455 sram_write(tp, 0x80e1, data);
7457 data = ocp_reg_read(tp, 0xbf06);
7460 ocp_reg_write(tp, 0xbf06, data);
7462 sram_write(tp, 0x819f, 0xddb6);
7464 ocp_reg_write(tp, 0xbc34, 0x5555);
7465 data = ocp_reg_read(tp, 0xbf0a);
7468 ocp_reg_write(tp, 0xbf0a, data);
7470 data = ocp_reg_read(tp, 0xbd2c);
7472 ocp_reg_write(tp, 0xbd2c, data);
7475 data = ocp_reg_read(tp, 0xad16);
7477 ocp_reg_write(tp, 0xad16, data);
7478 data = ocp_reg_read(tp, 0xad32);
7481 ocp_reg_write(tp, 0xad32, data);
7482 data = ocp_reg_read(tp, 0xac08);
7483 data &= ~(BIT(12) | BIT(8));
7484 ocp_reg_write(tp, 0xac08, data);
7485 data = ocp_reg_read(tp, 0xacc0);
7488 ocp_reg_write(tp, 0xacc0, data);
7489 data = ocp_reg_read(tp, 0xad40);
7491 data |= BIT(6) | BIT(2);
7492 ocp_reg_write(tp, 0xad40, data);
7493 data = ocp_reg_read(tp, 0xac14);
7495 ocp_reg_write(tp, 0xac14, data);
7496 data = ocp_reg_read(tp, 0xac80);
7497 data &= ~(BIT(8) | BIT(9));
7498 ocp_reg_write(tp, 0xac80, data);
7499 data = ocp_reg_read(tp, 0xac5e);
7502 ocp_reg_write(tp, 0xac5e, data);
7503 ocp_reg_write(tp, 0xad4c, 0x00a8);
7504 ocp_reg_write(tp, 0xac5c, 0x01ff);
7505 data = ocp_reg_read(tp, 0xac8a);
7507 data |= BIT(4) | BIT(5);
7508 ocp_reg_write(tp, 0xac8a, data);
7509 ocp_reg_write(tp, 0xb87c, 0x8157);
7510 data = ocp_reg_read(tp, 0xb87e);
7513 ocp_reg_write(tp, 0xb87e, data);
7514 ocp_reg_write(tp, 0xb87c, 0x8159);
7515 data = ocp_reg_read(tp, 0xb87e);
7518 ocp_reg_write(tp, 0xb87e, data);
7521 ocp_reg_write(tp, 0xb87c, 0x80a2);
7522 ocp_reg_write(tp, 0xb87e, 0x0153);
7523 ocp_reg_write(tp, 0xb87c, 0x809c);
7524 ocp_reg_write(tp, 0xb87e, 0x0153);
7527 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
7529 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7530 ocp_data |= EN_XG_LIP | EN_G_LIP;
7531 ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7533 sram_write(tp, 0x8257, 0x020f); /* XG PLL */
7534 sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */
7536 if (rtl_phy_patch_request(tp, true, true))
7540 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7541 ocp_data |= EEE_SPDWN_EN;
7542 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7544 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7545 data &= ~(EN_EEE_100 | EN_EEE_1000);
7546 data |= EN_10M_CLKDIV;
7547 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7548 tp->ups_info._10m_ckdiv = true;
7549 tp->ups_info.eee_plloff_100 = false;
7550 tp->ups_info.eee_plloff_giga = false;
7552 data = ocp_reg_read(tp, OCP_POWER_CFG);
7553 data &= ~EEE_CLKDIV_EN;
7554 ocp_reg_write(tp, OCP_POWER_CFG, data);
7555 tp->ups_info.eee_ckdiv = false;
7557 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
7558 ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
7559 tp->ups_info._250m_ckdiv = false;
7561 rtl_phy_patch_request(tp, false, true);
7563 /* enable ADC Ibias Cal */
7564 data = ocp_reg_read(tp, 0xd068);
7566 ocp_reg_write(tp, 0xd068, data);
7568 /* enable Thermal Sensor */
7569 data = sram_read(tp, 0x81a2);
7571 sram_write(tp, 0x81a2, data);
7572 data = ocp_reg_read(tp, 0xb54c);
7575 ocp_reg_write(tp, 0xb54c, data);
7577 /* Nway 2.5G Lite */
7578 data = ocp_reg_read(tp, 0xa454);
7580 ocp_reg_write(tp, 0xa454, data);
7582 /* CS DSP solution */
7583 data = ocp_reg_read(tp, OCP_10GBT_CTRL);
7584 data |= RTL_ADV2_5G_F_R;
7585 ocp_reg_write(tp, OCP_10GBT_CTRL, data);
7586 data = ocp_reg_read(tp, 0xad4e);
7588 ocp_reg_write(tp, 0xad4e, data);
7589 data = ocp_reg_read(tp, 0xa86a);
7591 ocp_reg_write(tp, 0xa86a, data);
7594 if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
7595 (ocp_reg_read(tp, 0xd068) & BIT(1))) {
7598 data = ocp_reg_read(tp, 0xd068);
7600 data |= 0x1; /* p0 */
7601 ocp_reg_write(tp, 0xd068, data);
7602 swap_a = ocp_reg_read(tp, 0xd06a);
7604 data |= 0x18; /* p3 */
7605 ocp_reg_write(tp, 0xd068, data);
7606 swap_b = ocp_reg_read(tp, 0xd06a);
7607 data &= ~0x18; /* p0 */
7608 ocp_reg_write(tp, 0xd068, data);
7609 ocp_reg_write(tp, 0xd06a,
7610 (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7611 data |= 0x18; /* p3 */
7612 ocp_reg_write(tp, 0xd068, data);
7613 ocp_reg_write(tp, 0xd06a,
7614 (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7616 data |= 0x08; /* p1 */
7617 ocp_reg_write(tp, 0xd068, data);
7618 swap_a = ocp_reg_read(tp, 0xd06a);
7620 data |= 0x10; /* p2 */
7621 ocp_reg_write(tp, 0xd068, data);
7622 swap_b = ocp_reg_read(tp, 0xd06a);
7624 data |= 0x08; /* p1 */
7625 ocp_reg_write(tp, 0xd068, data);
7626 ocp_reg_write(tp, 0xd06a,
7627 (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7629 data |= 0x10; /* p2 */
7630 ocp_reg_write(tp, 0xd068, data);
7631 ocp_reg_write(tp, 0xd06a,
7632 (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7633 swap_a = ocp_reg_read(tp, 0xbd5a);
7634 swap_b = ocp_reg_read(tp, 0xbd5c);
7635 ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) |
7636 ((swap_b & 0x1f) << 8) |
7637 ((swap_b >> 8) & 0x1f));
7638 ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) |
7639 ((swap_a & 0x1f) << 8) |
7640 ((swap_a >> 8) & 0x1f));
7641 swap_a = ocp_reg_read(tp, 0xbc18);
7642 swap_b = ocp_reg_read(tp, 0xbc1a);
7643 ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) |
7644 ((swap_b & 0x1f) << 8) |
7645 ((swap_b >> 8) & 0x1f));
7646 ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) |
7647 ((swap_a & 0x1f) << 8) |
7648 ((swap_a >> 8) & 0x1f));
7651 /* Notify the MAC when the speed is changed to force mode. */
7652 data = ocp_reg_read(tp, OCP_INTR_EN);
7653 data |= INTR_SPEED_FORCE;
7654 ocp_reg_write(tp, OCP_INTR_EN, data);
7660 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7662 data = ocp_reg_read(tp, 0xa428);
7664 ocp_reg_write(tp, 0xa428, data);
7665 data = ocp_reg_read(tp, 0xa5ea);
7667 ocp_reg_write(tp, 0xa5ea, data);
7668 tp->ups_info.lite_mode = 0;
7671 rtl_eee_enable(tp, true);
7673 r8153_aldps_en(tp, true);
7674 r8152b_enable_fc(tp);
7675 r8153_u2p3en(tp, true);
7677 set_bit(PHY_RESET, &tp->flags);
7680 static void r8156b_hw_phy_cfg(struct r8152 *tp)
7685 switch (tp->version) {
7687 ocp_reg_write(tp, 0xbf86, 0x9000);
7688 data = ocp_reg_read(tp, 0xc402);
7690 ocp_reg_write(tp, 0xc402, data);
7692 ocp_reg_write(tp, 0xc402, data);
7693 ocp_reg_write(tp, 0xbd86, 0x1010);
7694 ocp_reg_write(tp, 0xbd88, 0x1010);
7695 data = ocp_reg_read(tp, 0xbd4e);
7696 data &= ~(BIT(10) | BIT(11));
7698 ocp_reg_write(tp, 0xbd4e, data);
7699 data = ocp_reg_read(tp, 0xbf46);
7702 ocp_reg_write(tp, 0xbf46, data);
7706 r8156b_wait_loading_flash(tp);
7712 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7713 if (ocp_data & PCUT_STATUS) {
7714 ocp_data &= ~PCUT_STATUS;
7715 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7718 data = r8153_phy_status(tp, 0);
7720 case PHY_STAT_EXT_INIT:
7721 rtl8152_apply_firmware(tp, true);
7723 data = ocp_reg_read(tp, 0xa466);
7725 ocp_reg_write(tp, 0xa466, data);
7727 data = ocp_reg_read(tp, 0xa468);
7728 data &= ~(BIT(3) | BIT(1));
7729 ocp_reg_write(tp, 0xa468, data);
7731 case PHY_STAT_LAN_ON:
7732 case PHY_STAT_PWRDN:
7734 rtl8152_apply_firmware(tp, false);
7738 data = r8152_mdio_read(tp, MII_BMCR);
7739 if (data & BMCR_PDOWN) {
7740 data &= ~BMCR_PDOWN;
7741 r8152_mdio_write(tp, MII_BMCR, data);
7744 /* disable ALDPS before updating the PHY parameters */
7745 r8153_aldps_en(tp, false);
7747 /* disable EEE before updating the PHY parameters */
7748 rtl_eee_enable(tp, false);
7750 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7751 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7753 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7754 ocp_data |= PFM_PWM_SWITCH;
7755 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7757 switch (tp->version) {
7759 data = ocp_reg_read(tp, 0xbc08);
7760 data |= BIT(3) | BIT(2);
7761 ocp_reg_write(tp, 0xbc08, data);
7763 data = sram_read(tp, 0x8fff);
7766 sram_write(tp, 0x8fff, data);
7768 data = ocp_reg_read(tp, 0xacda);
7770 ocp_reg_write(tp, 0xacda, data);
7771 data = ocp_reg_read(tp, 0xacde);
7773 ocp_reg_write(tp, 0xacde, data);
7774 ocp_reg_write(tp, 0xac8c, 0x0ffc);
7775 ocp_reg_write(tp, 0xac46, 0xb7b4);
7776 ocp_reg_write(tp, 0xac50, 0x0fbc);
7777 ocp_reg_write(tp, 0xac3c, 0x9240);
7778 ocp_reg_write(tp, 0xac4e, 0x0db4);
7779 ocp_reg_write(tp, 0xacc6, 0x0707);
7780 ocp_reg_write(tp, 0xacc8, 0xa0d3);
7781 ocp_reg_write(tp, 0xad08, 0x0007);
7783 ocp_reg_write(tp, 0xb87c, 0x8560);
7784 ocp_reg_write(tp, 0xb87e, 0x19cc);
7785 ocp_reg_write(tp, 0xb87c, 0x8562);
7786 ocp_reg_write(tp, 0xb87e, 0x19cc);
7787 ocp_reg_write(tp, 0xb87c, 0x8564);
7788 ocp_reg_write(tp, 0xb87e, 0x19cc);
7789 ocp_reg_write(tp, 0xb87c, 0x8566);
7790 ocp_reg_write(tp, 0xb87e, 0x147d);
7791 ocp_reg_write(tp, 0xb87c, 0x8568);
7792 ocp_reg_write(tp, 0xb87e, 0x147d);
7793 ocp_reg_write(tp, 0xb87c, 0x856a);
7794 ocp_reg_write(tp, 0xb87e, 0x147d);
7795 ocp_reg_write(tp, 0xb87c, 0x8ffe);
7796 ocp_reg_write(tp, 0xb87e, 0x0907);
7797 ocp_reg_write(tp, 0xb87c, 0x80d6);
7798 ocp_reg_write(tp, 0xb87e, 0x2801);
7799 ocp_reg_write(tp, 0xb87c, 0x80f2);
7800 ocp_reg_write(tp, 0xb87e, 0x2801);
7801 ocp_reg_write(tp, 0xb87c, 0x80f4);
7802 ocp_reg_write(tp, 0xb87e, 0x6077);
7803 ocp_reg_write(tp, 0xb506, 0x01e7);
7805 ocp_reg_write(tp, 0xb87c, 0x8013);
7806 ocp_reg_write(tp, 0xb87e, 0x0700);
7807 ocp_reg_write(tp, 0xb87c, 0x8fb9);
7808 ocp_reg_write(tp, 0xb87e, 0x2801);
7809 ocp_reg_write(tp, 0xb87c, 0x8fba);
7810 ocp_reg_write(tp, 0xb87e, 0x0100);
7811 ocp_reg_write(tp, 0xb87c, 0x8fbc);
7812 ocp_reg_write(tp, 0xb87e, 0x1900);
7813 ocp_reg_write(tp, 0xb87c, 0x8fbe);
7814 ocp_reg_write(tp, 0xb87e, 0xe100);
7815 ocp_reg_write(tp, 0xb87c, 0x8fc0);
7816 ocp_reg_write(tp, 0xb87e, 0x0800);
7817 ocp_reg_write(tp, 0xb87c, 0x8fc2);
7818 ocp_reg_write(tp, 0xb87e, 0xe500);
7819 ocp_reg_write(tp, 0xb87c, 0x8fc4);
7820 ocp_reg_write(tp, 0xb87e, 0x0f00);
7821 ocp_reg_write(tp, 0xb87c, 0x8fc6);
7822 ocp_reg_write(tp, 0xb87e, 0xf100);
7823 ocp_reg_write(tp, 0xb87c, 0x8fc8);
7824 ocp_reg_write(tp, 0xb87e, 0x0400);
7825 ocp_reg_write(tp, 0xb87c, 0x8fca);
7826 ocp_reg_write(tp, 0xb87e, 0xf300);
7827 ocp_reg_write(tp, 0xb87c, 0x8fcc);
7828 ocp_reg_write(tp, 0xb87e, 0xfd00);
7829 ocp_reg_write(tp, 0xb87c, 0x8fce);
7830 ocp_reg_write(tp, 0xb87e, 0xff00);
7831 ocp_reg_write(tp, 0xb87c, 0x8fd0);
7832 ocp_reg_write(tp, 0xb87e, 0xfb00);
7833 ocp_reg_write(tp, 0xb87c, 0x8fd2);
7834 ocp_reg_write(tp, 0xb87e, 0x0100);
7835 ocp_reg_write(tp, 0xb87c, 0x8fd4);
7836 ocp_reg_write(tp, 0xb87e, 0xf400);
7837 ocp_reg_write(tp, 0xb87c, 0x8fd6);
7838 ocp_reg_write(tp, 0xb87e, 0xff00);
7839 ocp_reg_write(tp, 0xb87c, 0x8fd8);
7840 ocp_reg_write(tp, 0xb87e, 0xf600);
7842 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7843 ocp_data |= EN_XG_LIP | EN_G_LIP;
7844 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7845 ocp_reg_write(tp, 0xb87c, 0x813d);
7846 ocp_reg_write(tp, 0xb87e, 0x390e);
7847 ocp_reg_write(tp, 0xb87c, 0x814f);
7848 ocp_reg_write(tp, 0xb87e, 0x790e);
7849 ocp_reg_write(tp, 0xb87c, 0x80b0);
7850 ocp_reg_write(tp, 0xb87e, 0x0f31);
7851 data = ocp_reg_read(tp, 0xbf4c);
7853 ocp_reg_write(tp, 0xbf4c, data);
7854 data = ocp_reg_read(tp, 0xbcca);
7855 data |= BIT(9) | BIT(8);
7856 ocp_reg_write(tp, 0xbcca, data);
7857 ocp_reg_write(tp, 0xb87c, 0x8141);
7858 ocp_reg_write(tp, 0xb87e, 0x320e);
7859 ocp_reg_write(tp, 0xb87c, 0x8153);
7860 ocp_reg_write(tp, 0xb87e, 0x720e);
7861 ocp_reg_write(tp, 0xb87c, 0x8529);
7862 ocp_reg_write(tp, 0xb87e, 0x050e);
7863 data = ocp_reg_read(tp, OCP_EEE_CFG);
7864 data &= ~CTAP_SHORT_EN;
7865 ocp_reg_write(tp, OCP_EEE_CFG, data);
7867 sram_write(tp, 0x816c, 0xc4a0);
7868 sram_write(tp, 0x8170, 0xc4a0);
7869 sram_write(tp, 0x8174, 0x04a0);
7870 sram_write(tp, 0x8178, 0x04a0);
7871 sram_write(tp, 0x817c, 0x0719);
7872 sram_write(tp, 0x8ff4, 0x0400);
7873 sram_write(tp, 0x8ff1, 0x0404);
7875 ocp_reg_write(tp, 0xbf4a, 0x001b);
7876 ocp_reg_write(tp, 0xb87c, 0x8033);
7877 ocp_reg_write(tp, 0xb87e, 0x7c13);
7878 ocp_reg_write(tp, 0xb87c, 0x8037);
7879 ocp_reg_write(tp, 0xb87e, 0x7c13);
7880 ocp_reg_write(tp, 0xb87c, 0x803b);
7881 ocp_reg_write(tp, 0xb87e, 0xfc32);
7882 ocp_reg_write(tp, 0xb87c, 0x803f);
7883 ocp_reg_write(tp, 0xb87e, 0x7c13);
7884 ocp_reg_write(tp, 0xb87c, 0x8043);
7885 ocp_reg_write(tp, 0xb87e, 0x7c13);
7886 ocp_reg_write(tp, 0xb87c, 0x8047);
7887 ocp_reg_write(tp, 0xb87e, 0x7c13);
7889 ocp_reg_write(tp, 0xb87c, 0x8145);
7890 ocp_reg_write(tp, 0xb87e, 0x370e);
7891 ocp_reg_write(tp, 0xb87c, 0x8157);
7892 ocp_reg_write(tp, 0xb87e, 0x770e);
7893 ocp_reg_write(tp, 0xb87c, 0x8169);
7894 ocp_reg_write(tp, 0xb87e, 0x0d0a);
7895 ocp_reg_write(tp, 0xb87c, 0x817b);
7896 ocp_reg_write(tp, 0xb87e, 0x1d0a);
7898 data = sram_read(tp, 0x8217);
7901 sram_write(tp, 0x8217, data);
7902 data = sram_read(tp, 0x821a);
7905 sram_write(tp, 0x821a, data);
7906 sram_write(tp, 0x80da, 0x0403);
7907 data = sram_read(tp, 0x80dc);
7910 sram_write(tp, 0x80dc, data);
7911 sram_write(tp, 0x80b3, 0x0384);
7912 sram_write(tp, 0x80b7, 0x2007);
7913 data = sram_read(tp, 0x80ba);
7916 sram_write(tp, 0x80ba, data);
7917 sram_write(tp, 0x80b5, 0xf009);
7918 data = sram_read(tp, 0x80bd);
7921 sram_write(tp, 0x80bd, data);
7922 sram_write(tp, 0x80c7, 0xf083);
7923 sram_write(tp, 0x80dd, 0x03f0);
7924 data = sram_read(tp, 0x80df);
7927 sram_write(tp, 0x80df, data);
7928 sram_write(tp, 0x80cb, 0x2007);
7929 data = sram_read(tp, 0x80ce);
7932 sram_write(tp, 0x80ce, data);
7933 sram_write(tp, 0x80c9, 0x8009);
7934 data = sram_read(tp, 0x80d1);
7937 sram_write(tp, 0x80d1, data);
7938 sram_write(tp, 0x80a3, 0x200a);
7939 sram_write(tp, 0x80a5, 0xf0ad);
7940 sram_write(tp, 0x809f, 0x6073);
7941 sram_write(tp, 0x80a1, 0x000b);
7942 data = sram_read(tp, 0x80a9);
7945 sram_write(tp, 0x80a9, data);
7947 if (rtl_phy_patch_request(tp, true, true))
7950 data = ocp_reg_read(tp, 0xb896);
7952 ocp_reg_write(tp, 0xb896, data);
7953 data = ocp_reg_read(tp, 0xb892);
7955 ocp_reg_write(tp, 0xb892, data);
7956 ocp_reg_write(tp, 0xb88e, 0xc23e);
7957 ocp_reg_write(tp, 0xb890, 0x0000);
7958 ocp_reg_write(tp, 0xb88e, 0xc240);
7959 ocp_reg_write(tp, 0xb890, 0x0103);
7960 ocp_reg_write(tp, 0xb88e, 0xc242);
7961 ocp_reg_write(tp, 0xb890, 0x0507);
7962 ocp_reg_write(tp, 0xb88e, 0xc244);
7963 ocp_reg_write(tp, 0xb890, 0x090b);
7964 ocp_reg_write(tp, 0xb88e, 0xc246);
7965 ocp_reg_write(tp, 0xb890, 0x0c0e);
7966 ocp_reg_write(tp, 0xb88e, 0xc248);
7967 ocp_reg_write(tp, 0xb890, 0x1012);
7968 ocp_reg_write(tp, 0xb88e, 0xc24a);
7969 ocp_reg_write(tp, 0xb890, 0x1416);
7970 data = ocp_reg_read(tp, 0xb896);
7972 ocp_reg_write(tp, 0xb896, data);
7974 rtl_phy_patch_request(tp, false, true);
7976 data = ocp_reg_read(tp, 0xa86a);
7978 ocp_reg_write(tp, 0xa86a, data);
7979 data = ocp_reg_read(tp, 0xa6f0);
7981 ocp_reg_write(tp, 0xa6f0, data);
7983 ocp_reg_write(tp, 0xbfa0, 0xd70d);
7984 ocp_reg_write(tp, 0xbfa2, 0x4100);
7985 ocp_reg_write(tp, 0xbfa4, 0xe868);
7986 ocp_reg_write(tp, 0xbfa6, 0xdc59);
7987 ocp_reg_write(tp, 0xb54c, 0x3c18);
7988 data = ocp_reg_read(tp, 0xbfa4);
7990 ocp_reg_write(tp, 0xbfa4, data);
7991 data = sram_read(tp, 0x817d);
7993 sram_write(tp, 0x817d, data);
7997 data = ocp_reg_read(tp, 0xac46);
8000 ocp_reg_write(tp, 0xac46, data);
8001 data = ocp_reg_read(tp, 0xad30);
8004 ocp_reg_write(tp, 0xad30, data);
8008 ocp_reg_write(tp, 0xb87c, 0x80f5);
8009 ocp_reg_write(tp, 0xb87e, 0x760e);
8010 ocp_reg_write(tp, 0xb87c, 0x8107);
8011 ocp_reg_write(tp, 0xb87e, 0x360e);
8012 ocp_reg_write(tp, 0xb87c, 0x8551);
8013 data = ocp_reg_read(tp, 0xb87e);
8016 ocp_reg_write(tp, 0xb87e, data);
8018 /* ADC_PGA parameter */
8019 data = ocp_reg_read(tp, 0xbf00);
8022 ocp_reg_write(tp, 0xbf00, data);
8023 data = ocp_reg_read(tp, 0xbf46);
8026 ocp_reg_write(tp, 0xbf46, data);
8028 /* Green Table-PGA, 1G full viterbi */
8029 sram_write(tp, 0x8044, 0x2417);
8030 sram_write(tp, 0x804a, 0x2417);
8031 sram_write(tp, 0x8050, 0x2417);
8032 sram_write(tp, 0x8056, 0x2417);
8033 sram_write(tp, 0x805c, 0x2417);
8034 sram_write(tp, 0x8062, 0x2417);
8035 sram_write(tp, 0x8068, 0x2417);
8036 sram_write(tp, 0x806e, 0x2417);
8037 sram_write(tp, 0x8074, 0x2417);
8038 sram_write(tp, 0x807a, 0x2417);
8041 data = ocp_reg_read(tp, 0xbf84);
8044 ocp_reg_write(tp, 0xbf84, data);
8050 /* Notify the MAC when the speed is changed to force mode. */
8051 data = ocp_reg_read(tp, OCP_INTR_EN);
8052 data |= INTR_SPEED_FORCE;
8053 ocp_reg_write(tp, OCP_INTR_EN, data);
8055 if (rtl_phy_patch_request(tp, true, true))
8058 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
8059 ocp_data |= EEE_SPDWN_EN;
8060 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
8062 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
8063 data &= ~(EN_EEE_100 | EN_EEE_1000);
8064 data |= EN_10M_CLKDIV;
8065 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
8066 tp->ups_info._10m_ckdiv = true;
8067 tp->ups_info.eee_plloff_100 = false;
8068 tp->ups_info.eee_plloff_giga = false;
8070 data = ocp_reg_read(tp, OCP_POWER_CFG);
8071 data &= ~EEE_CLKDIV_EN;
8072 ocp_reg_write(tp, OCP_POWER_CFG, data);
8073 tp->ups_info.eee_ckdiv = false;
8075 rtl_phy_patch_request(tp, false, true);
8077 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
8079 data = ocp_reg_read(tp, 0xa428);
8081 ocp_reg_write(tp, 0xa428, data);
8082 data = ocp_reg_read(tp, 0xa5ea);
8084 ocp_reg_write(tp, 0xa5ea, data);
8085 tp->ups_info.lite_mode = 0;
8088 rtl_eee_enable(tp, true);
8090 r8153_aldps_en(tp, true);
8091 r8152b_enable_fc(tp);
8092 r8153_u2p3en(tp, true);
8094 set_bit(PHY_RESET, &tp->flags);
8097 static void r8156_init(struct r8152 *tp)
8103 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8106 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8107 ocp_data &= ~EN_ALL_SPEED;
8108 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
8110 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
8112 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8113 ocp_data |= BYPASS_MAC_RESET;
8114 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
8116 r8153b_u1u2en(tp, false);
8118 for (i = 0; i < 500; i++) {
8119 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8124 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8128 data = r8153_phy_status(tp, 0);
8129 if (data == PHY_STAT_EXT_INIT) {
8130 data = ocp_reg_read(tp, 0xa468);
8131 data &= ~(BIT(3) | BIT(1));
8132 ocp_reg_write(tp, 0xa468, data);
8135 data = r8152_mdio_read(tp, MII_BMCR);
8136 if (data & BMCR_PDOWN) {
8137 data &= ~BMCR_PDOWN;
8138 r8152_mdio_write(tp, MII_BMCR, data);
8141 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8142 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
8144 r8153_u2p3en(tp, false);
8146 /* MSC timer = 0xfff * 8ms = 32760 ms */
8147 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
8149 /* U1/U2/L1 idle timer. 500 us */
8150 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
8152 r8153b_power_cut_en(tp, false);
8153 r8156_ups_en(tp, false);
8154 r8153_queue_wake(tp, false);
8155 rtl_runtime_suspend_enable(tp, false);
8157 if (tp->udev->speed >= USB_SPEED_SUPER)
8158 r8153b_u1u2en(tp, true);
8160 usb_enable_lpm(tp->udev);
8162 r8156_mac_clk_spd(tp, true);
8164 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8165 ocp_data &= ~PLA_MCU_SPDWN_EN;
8166 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8168 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8169 if (rtl8152_get_speed(tp) & LINK_STATUS)
8170 ocp_data |= CUR_LINK_OK;
8172 ocp_data &= ~CUR_LINK_OK;
8173 ocp_data |= POLL_LINK_CHG;
8174 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8176 set_bit(GREEN_ETHERNET, &tp->flags);
8178 /* rx aggregation */
8179 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8180 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8181 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8183 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
8184 ocp_data |= ACT_ODMA;
8185 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
8187 r8156_mdio_force_mode(tp);
8188 rtl_tally_reset(tp);
8190 tp->coalesce = 15000; /* 15 us */
8193 static void r8156b_init(struct r8152 *tp)
8199 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8202 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8203 ocp_data &= ~EN_ALL_SPEED;
8204 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
8206 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
8208 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8209 ocp_data |= BYPASS_MAC_RESET;
8210 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
8212 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
8213 ocp_data |= RX_DETECT8;
8214 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
8216 r8153b_u1u2en(tp, false);
8218 switch (tp->version) {
8221 r8156b_wait_loading_flash(tp);
8227 for (i = 0; i < 500; i++) {
8228 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8233 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8237 data = r8153_phy_status(tp, 0);
8238 if (data == PHY_STAT_EXT_INIT) {
8239 data = ocp_reg_read(tp, 0xa468);
8240 data &= ~(BIT(3) | BIT(1));
8241 ocp_reg_write(tp, 0xa468, data);
8243 data = ocp_reg_read(tp, 0xa466);
8245 ocp_reg_write(tp, 0xa466, data);
8248 data = r8152_mdio_read(tp, MII_BMCR);
8249 if (data & BMCR_PDOWN) {
8250 data &= ~BMCR_PDOWN;
8251 r8152_mdio_write(tp, MII_BMCR, data);
8254 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8256 r8153_u2p3en(tp, false);
8258 /* MSC timer = 0xfff * 8ms = 32760 ms */
8259 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
8261 /* U1/U2/L1 idle timer. 500 us */
8262 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
8264 r8153b_power_cut_en(tp, false);
8265 r8156_ups_en(tp, false);
8266 r8153_queue_wake(tp, false);
8267 rtl_runtime_suspend_enable(tp, false);
8269 if (tp->udev->speed >= USB_SPEED_SUPER)
8270 r8153b_u1u2en(tp, true);
8272 usb_enable_lpm(tp->udev);
8274 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
8275 ocp_data &= ~SLOT_EN;
8276 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8278 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
8279 ocp_data |= FLOW_CTRL_EN;
8280 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
8282 /* enable fc timer and set timer to 600 ms. */
8283 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
8284 CTRL_TIMER_EN | (600 / 8));
8286 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
8287 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
8288 ocp_data |= FLOW_CTRL_PATCH_2;
8289 ocp_data &= ~AUTO_SPEEDUP;
8290 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
8292 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
8293 ocp_data |= FC_PATCH_TASK;
8294 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
8296 r8156_mac_clk_spd(tp, true);
8298 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8299 ocp_data &= ~PLA_MCU_SPDWN_EN;
8300 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8302 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8303 if (rtl8152_get_speed(tp) & LINK_STATUS)
8304 ocp_data |= CUR_LINK_OK;
8306 ocp_data &= ~CUR_LINK_OK;
8307 ocp_data |= POLL_LINK_CHG;
8308 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8310 set_bit(GREEN_ETHERNET, &tp->flags);
8312 /* rx aggregation */
8313 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8314 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8315 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8317 r8156_mdio_force_mode(tp);
8318 rtl_tally_reset(tp);
8320 tp->coalesce = 15000; /* 15 us */
8323 static bool rtl_check_vendor_ok(struct usb_interface *intf)
8325 struct usb_host_interface *alt = intf->cur_altsetting;
8326 struct usb_endpoint_descriptor *in, *out, *intr;
8328 if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) {
8329 dev_err(&intf->dev, "Expected endpoints are not found\n");
8333 /* Check Rx endpoint address */
8334 if (usb_endpoint_num(in) != 1) {
8335 dev_err(&intf->dev, "Invalid Rx endpoint address\n");
8339 /* Check Tx endpoint address */
8340 if (usb_endpoint_num(out) != 2) {
8341 dev_err(&intf->dev, "Invalid Tx endpoint address\n");
8345 /* Check interrupt endpoint address */
8346 if (usb_endpoint_num(intr) != 3) {
8347 dev_err(&intf->dev, "Invalid interrupt endpoint address\n");
8354 static int rtl8152_pre_reset(struct usb_interface *intf)
8356 struct r8152 *tp = usb_get_intfdata(intf);
8357 struct net_device *netdev;
8359 if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags))
8362 netdev = tp->netdev;
8363 if (!netif_running(netdev))
8366 netif_stop_queue(netdev);
8367 tasklet_disable(&tp->tx_tl);
8368 clear_bit(WORK_ENABLE, &tp->flags);
8369 usb_kill_urb(tp->intr_urb);
8370 cancel_delayed_work_sync(&tp->schedule);
8371 napi_disable(&tp->napi);
8372 if (netif_carrier_ok(netdev)) {
8373 mutex_lock(&tp->control);
8374 set_bit(IN_PRE_RESET, &tp->flags);
8375 tp->rtl_ops.disable(tp);
8376 clear_bit(IN_PRE_RESET, &tp->flags);
8377 mutex_unlock(&tp->control);
8383 static int rtl8152_post_reset(struct usb_interface *intf)
8385 struct r8152 *tp = usb_get_intfdata(intf);
8386 struct net_device *netdev;
8389 if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags))
8392 rtl_set_accessible(tp);
8394 /* reset the MAC address in case of policy change */
8395 if (determine_ethernet_addr(tp, &sa) >= 0) {
8397 dev_set_mac_address (tp->netdev, &sa, NULL);
8401 netdev = tp->netdev;
8402 if (!netif_running(netdev))
8405 set_bit(WORK_ENABLE, &tp->flags);
8406 if (netif_carrier_ok(netdev)) {
8407 mutex_lock(&tp->control);
8408 tp->rtl_ops.enable(tp);
8410 _rtl8152_set_rx_mode(netdev);
8411 mutex_unlock(&tp->control);
8414 napi_enable(&tp->napi);
8415 tasklet_enable(&tp->tx_tl);
8416 netif_wake_queue(netdev);
8417 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
8419 if (!list_empty(&tp->rx_done))
8420 napi_schedule(&tp->napi);
8425 static bool delay_autosuspend(struct r8152 *tp)
8427 bool sw_linking = !!netif_carrier_ok(tp->netdev);
8428 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
8430 /* This means a linking change occurs and the driver doesn't detect it,
8431 * yet. If the driver has disabled tx/rx and hw is linking on, the
8432 * device wouldn't wake up by receiving any packet.
8434 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
8437 /* If the linking down is occurred by nway, the device may miss the
8438 * linking change event. And it wouldn't wake when linking on.
8440 if (!sw_linking && tp->rtl_ops.in_nway(tp))
8442 else if (!skb_queue_empty(&tp->tx_queue))
8448 static int rtl8152_runtime_resume(struct r8152 *tp)
8450 struct net_device *netdev = tp->netdev;
8452 if (netif_running(netdev) && netdev->flags & IFF_UP) {
8453 struct napi_struct *napi = &tp->napi;
8455 tp->rtl_ops.autosuspend_en(tp, false);
8457 set_bit(WORK_ENABLE, &tp->flags);
8459 if (netif_carrier_ok(netdev)) {
8460 if (rtl8152_get_speed(tp) & LINK_STATUS) {
8463 netif_carrier_off(netdev);
8464 tp->rtl_ops.disable(tp);
8465 netif_info(tp, link, netdev, "linking down\n");
8470 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8471 smp_mb__after_atomic();
8473 if (!list_empty(&tp->rx_done))
8474 napi_schedule(&tp->napi);
8476 usb_submit_urb(tp->intr_urb, GFP_NOIO);
8478 if (netdev->flags & IFF_UP)
8479 tp->rtl_ops.autosuspend_en(tp, false);
8481 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8487 static int rtl8152_system_resume(struct r8152 *tp)
8489 struct net_device *netdev = tp->netdev;
8491 netif_device_attach(netdev);
8493 if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
8495 netif_carrier_off(netdev);
8496 set_bit(WORK_ENABLE, &tp->flags);
8497 usb_submit_urb(tp->intr_urb, GFP_NOIO);
8503 static int rtl8152_runtime_suspend(struct r8152 *tp)
8505 struct net_device *netdev = tp->netdev;
8508 if (!tp->rtl_ops.autosuspend_en)
8511 set_bit(SELECTIVE_SUSPEND, &tp->flags);
8512 smp_mb__after_atomic();
8514 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8517 if (netif_carrier_ok(netdev)) {
8520 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
8521 ocp_data = rcr & ~RCR_ACPT_ALL;
8522 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8523 rxdy_gated_en(tp, true);
8524 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
8526 if (!(ocp_data & RXFIFO_EMPTY)) {
8527 rxdy_gated_en(tp, false);
8528 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8529 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8530 smp_mb__after_atomic();
8536 clear_bit(WORK_ENABLE, &tp->flags);
8537 usb_kill_urb(tp->intr_urb);
8539 tp->rtl_ops.autosuspend_en(tp, true);
8541 if (netif_carrier_ok(netdev)) {
8542 struct napi_struct *napi = &tp->napi;
8546 rxdy_gated_en(tp, false);
8547 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8551 if (delay_autosuspend(tp)) {
8552 rtl8152_runtime_resume(tp);
8561 static int rtl8152_system_suspend(struct r8152 *tp)
8563 struct net_device *netdev = tp->netdev;
8565 netif_device_detach(netdev);
8567 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8568 struct napi_struct *napi = &tp->napi;
8570 clear_bit(WORK_ENABLE, &tp->flags);
8571 usb_kill_urb(tp->intr_urb);
8572 tasklet_disable(&tp->tx_tl);
8574 cancel_delayed_work_sync(&tp->schedule);
8575 tp->rtl_ops.down(tp);
8577 tasklet_enable(&tp->tx_tl);
8583 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
8585 struct r8152 *tp = usb_get_intfdata(intf);
8588 mutex_lock(&tp->control);
8590 if (PMSG_IS_AUTO(message))
8591 ret = rtl8152_runtime_suspend(tp);
8593 ret = rtl8152_system_suspend(tp);
8595 mutex_unlock(&tp->control);
8600 static int rtl8152_resume(struct usb_interface *intf)
8602 struct r8152 *tp = usb_get_intfdata(intf);
8605 mutex_lock(&tp->control);
8607 rtl_reset_ocp_base(tp);
8609 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
8610 ret = rtl8152_runtime_resume(tp);
8612 ret = rtl8152_system_resume(tp);
8614 mutex_unlock(&tp->control);
8619 static int rtl8152_reset_resume(struct usb_interface *intf)
8621 struct r8152 *tp = usb_get_intfdata(intf);
8623 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8624 rtl_reset_ocp_base(tp);
8625 tp->rtl_ops.init(tp);
8626 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
8627 set_ethernet_addr(tp, true);
8628 return rtl8152_resume(intf);
8631 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8633 struct r8152 *tp = netdev_priv(dev);
8635 if (usb_autopm_get_interface(tp->intf) < 0)
8638 if (!rtl_can_wakeup(tp)) {
8642 mutex_lock(&tp->control);
8643 wol->supported = WAKE_ANY;
8644 wol->wolopts = __rtl_get_wol(tp);
8645 mutex_unlock(&tp->control);
8648 usb_autopm_put_interface(tp->intf);
8651 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8653 struct r8152 *tp = netdev_priv(dev);
8656 if (!rtl_can_wakeup(tp))
8659 if (wol->wolopts & ~WAKE_ANY)
8662 ret = usb_autopm_get_interface(tp->intf);
8666 mutex_lock(&tp->control);
8668 __rtl_set_wol(tp, wol->wolopts);
8669 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
8671 mutex_unlock(&tp->control);
8673 usb_autopm_put_interface(tp->intf);
8679 static u32 rtl8152_get_msglevel(struct net_device *dev)
8681 struct r8152 *tp = netdev_priv(dev);
8683 return tp->msg_enable;
8686 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
8688 struct r8152 *tp = netdev_priv(dev);
8690 tp->msg_enable = value;
8693 static void rtl8152_get_drvinfo(struct net_device *netdev,
8694 struct ethtool_drvinfo *info)
8696 struct r8152 *tp = netdev_priv(netdev);
8698 strscpy(info->driver, MODULENAME, sizeof(info->driver));
8699 strscpy(info->version, DRIVER_VERSION, sizeof(info->version));
8700 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
8701 if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
8702 strscpy(info->fw_version, tp->rtl_fw.version,
8703 sizeof(info->fw_version));
8707 int rtl8152_get_link_ksettings(struct net_device *netdev,
8708 struct ethtool_link_ksettings *cmd)
8710 struct r8152 *tp = netdev_priv(netdev);
8713 if (!tp->mii.mdio_read)
8716 ret = usb_autopm_get_interface(tp->intf);
8720 mutex_lock(&tp->control);
8722 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
8724 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8725 cmd->link_modes.supported, tp->support_2500full);
8727 if (tp->support_2500full) {
8728 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8729 cmd->link_modes.advertising,
8730 ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
8732 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8733 cmd->link_modes.lp_advertising,
8734 ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
8736 if (is_speed_2500(rtl8152_get_speed(tp)))
8737 cmd->base.speed = SPEED_2500;
8740 mutex_unlock(&tp->control);
8742 usb_autopm_put_interface(tp->intf);
8748 static int rtl8152_set_link_ksettings(struct net_device *dev,
8749 const struct ethtool_link_ksettings *cmd)
8751 struct r8152 *tp = netdev_priv(dev);
8752 u32 advertising = 0;
8755 ret = usb_autopm_get_interface(tp->intf);
8759 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
8760 cmd->link_modes.advertising))
8761 advertising |= RTL_ADVERTISED_10_HALF;
8763 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
8764 cmd->link_modes.advertising))
8765 advertising |= RTL_ADVERTISED_10_FULL;
8767 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
8768 cmd->link_modes.advertising))
8769 advertising |= RTL_ADVERTISED_100_HALF;
8771 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
8772 cmd->link_modes.advertising))
8773 advertising |= RTL_ADVERTISED_100_FULL;
8775 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
8776 cmd->link_modes.advertising))
8777 advertising |= RTL_ADVERTISED_1000_HALF;
8779 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
8780 cmd->link_modes.advertising))
8781 advertising |= RTL_ADVERTISED_1000_FULL;
8783 if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8784 cmd->link_modes.advertising))
8785 advertising |= RTL_ADVERTISED_2500_FULL;
8787 mutex_lock(&tp->control);
8789 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
8790 cmd->base.duplex, advertising);
8792 tp->autoneg = cmd->base.autoneg;
8793 tp->speed = cmd->base.speed;
8794 tp->duplex = cmd->base.duplex;
8795 tp->advertising = advertising;
8798 mutex_unlock(&tp->control);
8800 usb_autopm_put_interface(tp->intf);
8806 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
8813 "tx_single_collisions",
8814 "tx_multi_collisions",
8822 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
8826 return ARRAY_SIZE(rtl8152_gstrings);
8832 static void rtl8152_get_ethtool_stats(struct net_device *dev,
8833 struct ethtool_stats *stats, u64 *data)
8835 struct r8152 *tp = netdev_priv(dev);
8836 struct tally_counter tally;
8838 if (usb_autopm_get_interface(tp->intf) < 0)
8841 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
8843 usb_autopm_put_interface(tp->intf);
8845 data[0] = le64_to_cpu(tally.tx_packets);
8846 data[1] = le64_to_cpu(tally.rx_packets);
8847 data[2] = le64_to_cpu(tally.tx_errors);
8848 data[3] = le32_to_cpu(tally.rx_errors);
8849 data[4] = le16_to_cpu(tally.rx_missed);
8850 data[5] = le16_to_cpu(tally.align_errors);
8851 data[6] = le32_to_cpu(tally.tx_one_collision);
8852 data[7] = le32_to_cpu(tally.tx_multi_collision);
8853 data[8] = le64_to_cpu(tally.rx_unicast);
8854 data[9] = le64_to_cpu(tally.rx_broadcast);
8855 data[10] = le32_to_cpu(tally.rx_multicast);
8856 data[11] = le16_to_cpu(tally.tx_aborted);
8857 data[12] = le16_to_cpu(tally.tx_underrun);
8860 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
8862 switch (stringset) {
8864 memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
8869 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8871 u32 lp, adv, supported = 0;
8874 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
8875 supported = mmd_eee_cap_to_ethtool_sup_t(val);
8877 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
8878 adv = mmd_eee_adv_to_ethtool_adv_t(val);
8880 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
8881 lp = mmd_eee_adv_to_ethtool_adv_t(val);
8883 eee->eee_enabled = tp->eee_en;
8884 eee->eee_active = !!(supported & adv & lp);
8885 eee->supported = supported;
8886 eee->advertised = tp->eee_adv;
8887 eee->lp_advertised = lp;
8892 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
8894 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
8896 tp->eee_en = eee->eee_enabled;
8899 rtl_eee_enable(tp, tp->eee_en);
8904 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8906 u32 lp, adv, supported = 0;
8909 val = ocp_reg_read(tp, OCP_EEE_ABLE);
8910 supported = mmd_eee_cap_to_ethtool_sup_t(val);
8912 val = ocp_reg_read(tp, OCP_EEE_ADV);
8913 adv = mmd_eee_adv_to_ethtool_adv_t(val);
8915 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
8916 lp = mmd_eee_adv_to_ethtool_adv_t(val);
8918 eee->eee_enabled = tp->eee_en;
8919 eee->eee_active = !!(supported & adv & lp);
8920 eee->supported = supported;
8921 eee->advertised = tp->eee_adv;
8922 eee->lp_advertised = lp;
8928 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
8930 struct r8152 *tp = netdev_priv(net);
8933 if (!tp->rtl_ops.eee_get) {
8938 ret = usb_autopm_get_interface(tp->intf);
8942 mutex_lock(&tp->control);
8944 ret = tp->rtl_ops.eee_get(tp, edata);
8946 mutex_unlock(&tp->control);
8948 usb_autopm_put_interface(tp->intf);
8955 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
8957 struct r8152 *tp = netdev_priv(net);
8960 if (!tp->rtl_ops.eee_set) {
8965 ret = usb_autopm_get_interface(tp->intf);
8969 mutex_lock(&tp->control);
8971 ret = tp->rtl_ops.eee_set(tp, edata);
8973 ret = mii_nway_restart(&tp->mii);
8975 mutex_unlock(&tp->control);
8977 usb_autopm_put_interface(tp->intf);
8983 static int rtl8152_nway_reset(struct net_device *dev)
8985 struct r8152 *tp = netdev_priv(dev);
8988 ret = usb_autopm_get_interface(tp->intf);
8992 mutex_lock(&tp->control);
8994 ret = mii_nway_restart(&tp->mii);
8996 mutex_unlock(&tp->control);
8998 usb_autopm_put_interface(tp->intf);
9004 static int rtl8152_get_coalesce(struct net_device *netdev,
9005 struct ethtool_coalesce *coalesce,
9006 struct kernel_ethtool_coalesce *kernel_coal,
9007 struct netlink_ext_ack *extack)
9009 struct r8152 *tp = netdev_priv(netdev);
9011 switch (tp->version) {
9020 coalesce->rx_coalesce_usecs = tp->coalesce;
9025 static int rtl8152_set_coalesce(struct net_device *netdev,
9026 struct ethtool_coalesce *coalesce,
9027 struct kernel_ethtool_coalesce *kernel_coal,
9028 struct netlink_ext_ack *extack)
9030 struct r8152 *tp = netdev_priv(netdev);
9033 switch (tp->version) {
9042 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
9045 ret = usb_autopm_get_interface(tp->intf);
9049 mutex_lock(&tp->control);
9051 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
9052 tp->coalesce = coalesce->rx_coalesce_usecs;
9054 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
9055 netif_stop_queue(netdev);
9056 napi_disable(&tp->napi);
9057 tp->rtl_ops.disable(tp);
9058 tp->rtl_ops.enable(tp);
9060 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
9061 _rtl8152_set_rx_mode(netdev);
9062 napi_enable(&tp->napi);
9063 netif_wake_queue(netdev);
9067 mutex_unlock(&tp->control);
9069 usb_autopm_put_interface(tp->intf);
9074 static int rtl8152_get_tunable(struct net_device *netdev,
9075 const struct ethtool_tunable *tunable, void *d)
9077 struct r8152 *tp = netdev_priv(netdev);
9079 switch (tunable->id) {
9080 case ETHTOOL_RX_COPYBREAK:
9081 *(u32 *)d = tp->rx_copybreak;
9090 static int rtl8152_set_tunable(struct net_device *netdev,
9091 const struct ethtool_tunable *tunable,
9094 struct r8152 *tp = netdev_priv(netdev);
9097 switch (tunable->id) {
9098 case ETHTOOL_RX_COPYBREAK:
9100 if (val < ETH_ZLEN) {
9101 netif_err(tp, rx_err, netdev,
9102 "Invalid rx copy break value\n");
9106 if (tp->rx_copybreak != val) {
9107 if (netdev->flags & IFF_UP) {
9108 mutex_lock(&tp->control);
9109 napi_disable(&tp->napi);
9110 tp->rx_copybreak = val;
9111 napi_enable(&tp->napi);
9112 mutex_unlock(&tp->control);
9114 tp->rx_copybreak = val;
9125 static void rtl8152_get_ringparam(struct net_device *netdev,
9126 struct ethtool_ringparam *ring,
9127 struct kernel_ethtool_ringparam *kernel_ring,
9128 struct netlink_ext_ack *extack)
9130 struct r8152 *tp = netdev_priv(netdev);
9132 ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
9133 ring->rx_pending = tp->rx_pending;
9136 static int rtl8152_set_ringparam(struct net_device *netdev,
9137 struct ethtool_ringparam *ring,
9138 struct kernel_ethtool_ringparam *kernel_ring,
9139 struct netlink_ext_ack *extack)
9141 struct r8152 *tp = netdev_priv(netdev);
9143 if (ring->rx_pending < (RTL8152_MAX_RX * 2))
9146 if (tp->rx_pending != ring->rx_pending) {
9147 if (netdev->flags & IFF_UP) {
9148 mutex_lock(&tp->control);
9149 napi_disable(&tp->napi);
9150 tp->rx_pending = ring->rx_pending;
9151 napi_enable(&tp->napi);
9152 mutex_unlock(&tp->control);
9154 tp->rx_pending = ring->rx_pending;
9161 static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9163 struct r8152 *tp = netdev_priv(netdev);
9164 u16 bmcr, lcladv, rmtadv;
9167 if (usb_autopm_get_interface(tp->intf) < 0)
9170 mutex_lock(&tp->control);
9172 bmcr = r8152_mdio_read(tp, MII_BMCR);
9173 lcladv = r8152_mdio_read(tp, MII_ADVERTISE);
9174 rmtadv = r8152_mdio_read(tp, MII_LPA);
9176 mutex_unlock(&tp->control);
9178 usb_autopm_put_interface(tp->intf);
9180 if (!(bmcr & BMCR_ANENABLE)) {
9182 pause->rx_pause = 0;
9183 pause->tx_pause = 0;
9189 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
9191 if (cap & FLOW_CTRL_RX)
9192 pause->rx_pause = 1;
9194 if (cap & FLOW_CTRL_TX)
9195 pause->tx_pause = 1;
9198 static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9200 struct r8152 *tp = netdev_priv(netdev);
9205 ret = usb_autopm_get_interface(tp->intf);
9209 mutex_lock(&tp->control);
9211 if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) {
9216 if (pause->rx_pause)
9217 cap |= FLOW_CTRL_RX;
9219 if (pause->tx_pause)
9220 cap |= FLOW_CTRL_TX;
9222 old = r8152_mdio_read(tp, MII_ADVERTISE);
9223 new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap);
9225 r8152_mdio_write(tp, MII_ADVERTISE, new1);
9228 mutex_unlock(&tp->control);
9229 usb_autopm_put_interface(tp->intf);
9234 static const struct ethtool_ops ops = {
9235 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
9236 .get_drvinfo = rtl8152_get_drvinfo,
9237 .get_link = ethtool_op_get_link,
9238 .nway_reset = rtl8152_nway_reset,
9239 .get_msglevel = rtl8152_get_msglevel,
9240 .set_msglevel = rtl8152_set_msglevel,
9241 .get_wol = rtl8152_get_wol,
9242 .set_wol = rtl8152_set_wol,
9243 .get_strings = rtl8152_get_strings,
9244 .get_sset_count = rtl8152_get_sset_count,
9245 .get_ethtool_stats = rtl8152_get_ethtool_stats,
9246 .get_coalesce = rtl8152_get_coalesce,
9247 .set_coalesce = rtl8152_set_coalesce,
9248 .get_eee = rtl_ethtool_get_eee,
9249 .set_eee = rtl_ethtool_set_eee,
9250 .get_link_ksettings = rtl8152_get_link_ksettings,
9251 .set_link_ksettings = rtl8152_set_link_ksettings,
9252 .get_tunable = rtl8152_get_tunable,
9253 .set_tunable = rtl8152_set_tunable,
9254 .get_ringparam = rtl8152_get_ringparam,
9255 .set_ringparam = rtl8152_set_ringparam,
9256 .get_pauseparam = rtl8152_get_pauseparam,
9257 .set_pauseparam = rtl8152_set_pauseparam,
9260 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
9262 struct r8152 *tp = netdev_priv(netdev);
9263 struct mii_ioctl_data *data = if_mii(rq);
9266 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9269 res = usb_autopm_get_interface(tp->intf);
9275 data->phy_id = R8152_PHY_ID; /* Internal PHY */
9279 mutex_lock(&tp->control);
9280 data->val_out = r8152_mdio_read(tp, data->reg_num);
9281 mutex_unlock(&tp->control);
9285 if (!capable(CAP_NET_ADMIN)) {
9289 mutex_lock(&tp->control);
9290 r8152_mdio_write(tp, data->reg_num, data->val_in);
9291 mutex_unlock(&tp->control);
9298 usb_autopm_put_interface(tp->intf);
9304 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
9306 struct r8152 *tp = netdev_priv(dev);
9309 switch (tp->version) {
9319 ret = usb_autopm_get_interface(tp->intf);
9323 mutex_lock(&tp->control);
9327 if (netif_running(dev)) {
9328 if (tp->rtl_ops.change_mtu)
9329 tp->rtl_ops.change_mtu(tp);
9331 if (netif_carrier_ok(dev)) {
9332 netif_stop_queue(dev);
9333 napi_disable(&tp->napi);
9334 tasklet_disable(&tp->tx_tl);
9335 tp->rtl_ops.disable(tp);
9336 tp->rtl_ops.enable(tp);
9338 tasklet_enable(&tp->tx_tl);
9339 napi_enable(&tp->napi);
9340 rtl8152_set_rx_mode(dev);
9341 netif_wake_queue(dev);
9345 mutex_unlock(&tp->control);
9347 usb_autopm_put_interface(tp->intf);
9352 static const struct net_device_ops rtl8152_netdev_ops = {
9353 .ndo_open = rtl8152_open,
9354 .ndo_stop = rtl8152_close,
9355 .ndo_eth_ioctl = rtl8152_ioctl,
9356 .ndo_start_xmit = rtl8152_start_xmit,
9357 .ndo_tx_timeout = rtl8152_tx_timeout,
9358 .ndo_set_features = rtl8152_set_features,
9359 .ndo_set_rx_mode = rtl8152_set_rx_mode,
9360 .ndo_set_mac_address = rtl8152_set_mac_address,
9361 .ndo_change_mtu = rtl8152_change_mtu,
9362 .ndo_validate_addr = eth_validate_addr,
9363 .ndo_features_check = rtl8152_features_check,
9366 static void rtl8152_unload(struct r8152 *tp)
9368 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9371 if (tp->version != RTL_VER_01)
9372 r8152_power_cut_en(tp, true);
9375 static void rtl8153_unload(struct r8152 *tp)
9377 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9380 r8153_power_cut_en(tp, false);
9383 static void rtl8153b_unload(struct r8152 *tp)
9385 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9388 r8153b_power_cut_en(tp, false);
9391 static int rtl_ops_init(struct r8152 *tp)
9393 struct rtl_ops *ops = &tp->rtl_ops;
9396 switch (tp->version) {
9400 ops->init = r8152b_init;
9401 ops->enable = rtl8152_enable;
9402 ops->disable = rtl8152_disable;
9403 ops->up = rtl8152_up;
9404 ops->down = rtl8152_down;
9405 ops->unload = rtl8152_unload;
9406 ops->eee_get = r8152_get_eee;
9407 ops->eee_set = r8152_set_eee;
9408 ops->in_nway = rtl8152_in_nway;
9409 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
9410 ops->autosuspend_en = rtl_runtime_suspend_enable;
9411 tp->rx_buf_sz = 16 * 1024;
9413 tp->eee_adv = MDIO_EEE_100TX;
9420 ops->init = r8153_init;
9421 ops->enable = rtl8153_enable;
9422 ops->disable = rtl8153_disable;
9423 ops->up = rtl8153_up;
9424 ops->down = rtl8153_down;
9425 ops->unload = rtl8153_unload;
9426 ops->eee_get = r8153_get_eee;
9427 ops->eee_set = r8152_set_eee;
9428 ops->in_nway = rtl8153_in_nway;
9429 ops->hw_phy_cfg = r8153_hw_phy_cfg;
9430 ops->autosuspend_en = rtl8153_runtime_enable;
9431 ops->change_mtu = rtl8153_change_mtu;
9432 if (tp->udev->speed < USB_SPEED_SUPER)
9433 tp->rx_buf_sz = 16 * 1024;
9435 tp->rx_buf_sz = 32 * 1024;
9437 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9442 ops->init = r8153b_init;
9443 ops->enable = rtl8153_enable;
9444 ops->disable = rtl8153_disable;
9445 ops->up = rtl8153b_up;
9446 ops->down = rtl8153b_down;
9447 ops->unload = rtl8153b_unload;
9448 ops->eee_get = r8153_get_eee;
9449 ops->eee_set = r8152_set_eee;
9450 ops->in_nway = rtl8153_in_nway;
9451 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
9452 ops->autosuspend_en = rtl8153b_runtime_enable;
9453 ops->change_mtu = rtl8153_change_mtu;
9454 tp->rx_buf_sz = 32 * 1024;
9456 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9461 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9464 ops->init = r8156_init;
9465 ops->enable = rtl8156_enable;
9466 ops->disable = rtl8156_disable;
9467 ops->up = rtl8156_up;
9468 ops->down = rtl8156_down;
9469 ops->unload = rtl8153_unload;
9470 ops->eee_get = r8153_get_eee;
9471 ops->eee_set = r8152_set_eee;
9472 ops->in_nway = rtl8153_in_nway;
9473 ops->hw_phy_cfg = r8156_hw_phy_cfg;
9474 ops->autosuspend_en = rtl8156_runtime_enable;
9475 ops->change_mtu = rtl8156_change_mtu;
9476 tp->rx_buf_sz = 48 * 1024;
9477 tp->support_2500full = 1;
9482 tp->support_2500full = 1;
9486 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9487 ops->init = r8156b_init;
9488 ops->enable = rtl8156b_enable;
9489 ops->disable = rtl8153_disable;
9490 ops->up = rtl8156_up;
9491 ops->down = rtl8156_down;
9492 ops->unload = rtl8153_unload;
9493 ops->eee_get = r8153_get_eee;
9494 ops->eee_set = r8152_set_eee;
9495 ops->in_nway = rtl8153_in_nway;
9496 ops->hw_phy_cfg = r8156b_hw_phy_cfg;
9497 ops->autosuspend_en = rtl8156_runtime_enable;
9498 ops->change_mtu = rtl8156_change_mtu;
9499 tp->rx_buf_sz = 48 * 1024;
9503 ops->init = r8153c_init;
9504 ops->enable = rtl8153_enable;
9505 ops->disable = rtl8153_disable;
9506 ops->up = rtl8153c_up;
9507 ops->down = rtl8153b_down;
9508 ops->unload = rtl8153_unload;
9509 ops->eee_get = r8153_get_eee;
9510 ops->eee_set = r8152_set_eee;
9511 ops->in_nway = rtl8153_in_nway;
9512 ops->hw_phy_cfg = r8153c_hw_phy_cfg;
9513 ops->autosuspend_en = rtl8153c_runtime_enable;
9514 ops->change_mtu = rtl8153c_change_mtu;
9515 tp->rx_buf_sz = 32 * 1024;
9517 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9522 dev_err(&tp->intf->dev, "Unknown Device\n");
9529 #define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
9530 #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
9531 #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
9532 #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
9533 #define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw"
9534 #define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw"
9535 #define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw"
9537 MODULE_FIRMWARE(FIRMWARE_8153A_2);
9538 MODULE_FIRMWARE(FIRMWARE_8153A_3);
9539 MODULE_FIRMWARE(FIRMWARE_8153A_4);
9540 MODULE_FIRMWARE(FIRMWARE_8153B_2);
9541 MODULE_FIRMWARE(FIRMWARE_8153C_1);
9542 MODULE_FIRMWARE(FIRMWARE_8156A_2);
9543 MODULE_FIRMWARE(FIRMWARE_8156B_2);
9545 static int rtl_fw_init(struct r8152 *tp)
9547 struct rtl_fw *rtl_fw = &tp->rtl_fw;
9549 switch (tp->version) {
9551 rtl_fw->fw_name = FIRMWARE_8153A_2;
9552 rtl_fw->pre_fw = r8153_pre_firmware_1;
9553 rtl_fw->post_fw = r8153_post_firmware_1;
9556 rtl_fw->fw_name = FIRMWARE_8153A_3;
9557 rtl_fw->pre_fw = r8153_pre_firmware_2;
9558 rtl_fw->post_fw = r8153_post_firmware_2;
9561 rtl_fw->fw_name = FIRMWARE_8153A_4;
9562 rtl_fw->post_fw = r8153_post_firmware_3;
9565 rtl_fw->fw_name = FIRMWARE_8153B_2;
9566 rtl_fw->pre_fw = r8153b_pre_firmware_1;
9567 rtl_fw->post_fw = r8153b_post_firmware_1;
9570 rtl_fw->fw_name = FIRMWARE_8156A_2;
9571 rtl_fw->post_fw = r8156a_post_firmware_1;
9575 rtl_fw->fw_name = FIRMWARE_8156B_2;
9578 rtl_fw->fw_name = FIRMWARE_8153C_1;
9579 rtl_fw->pre_fw = r8153b_pre_firmware_1;
9580 rtl_fw->post_fw = r8153c_post_firmware_1;
9589 static u8 __rtl_get_hw_ver(struct usb_device *udev)
9597 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
9601 /* Retry up to 3 times in case there is a transitory error. We do this
9602 * since retrying a read of the version is always safe and this
9603 * function doesn't take advantage of r8152_control_msg().
9605 for (i = 0; i < 3; i++) {
9606 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
9607 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
9608 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp),
9609 USB_CTRL_GET_TIMEOUT);
9611 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
9616 if (i != 0 && ret > 0)
9617 dev_warn(&udev->dev, "Needed %d retries to read version\n", i);
9623 version = RTL_VER_01;
9626 version = RTL_VER_02;
9629 version = RTL_VER_03;
9632 version = RTL_VER_04;
9635 version = RTL_VER_05;
9638 version = RTL_VER_06;
9641 version = RTL_VER_07;
9644 version = RTL_VER_08;
9647 version = RTL_VER_09;
9650 version = RTL_TEST_01;
9653 version = RTL_VER_10;
9656 version = RTL_VER_11;
9659 version = RTL_VER_12;
9662 version = RTL_VER_13;
9665 version = RTL_VER_14;
9668 version = RTL_VER_15;
9671 version = RTL_VER_UNKNOWN;
9672 dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data);
9679 u8 rtl8152_get_version(struct usb_interface *intf)
9683 version = __rtl_get_hw_ver(interface_to_usbdev(intf));
9685 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
9689 EXPORT_SYMBOL_GPL(rtl8152_get_version);
9691 static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev)
9693 int parent_vendor_id = le16_to_cpu(udev->parent->descriptor.idVendor);
9694 int product_id = le16_to_cpu(udev->descriptor.idProduct);
9695 int vendor_id = le16_to_cpu(udev->descriptor.idVendor);
9697 if (vendor_id == VENDOR_ID_LENOVO) {
9698 switch (product_id) {
9699 case DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB:
9700 case DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK:
9701 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
9702 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
9703 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3:
9704 case DEVICE_ID_THINKPAD_USB_C_DONGLE:
9707 } else if (vendor_id == VENDOR_ID_REALTEK && parent_vendor_id == VENDOR_ID_LENOVO) {
9708 switch (product_id) {
9716 static int rtl8152_probe_once(struct usb_interface *intf,
9717 const struct usb_device_id *id, u8 version)
9719 struct usb_device *udev = interface_to_usbdev(intf);
9721 struct net_device *netdev;
9724 usb_reset_device(udev);
9725 netdev = alloc_etherdev(sizeof(struct r8152));
9727 dev_err(&intf->dev, "Out of memory\n");
9731 SET_NETDEV_DEV(netdev, &intf->dev);
9732 tp = netdev_priv(netdev);
9733 tp->msg_enable = 0x7FFF;
9736 tp->netdev = netdev;
9738 tp->version = version;
9740 tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0);
9741 tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0);
9742 tp->pipe_in = usb_rcvbulkpipe(udev, 1);
9743 tp->pipe_out = usb_sndbulkpipe(udev, 2);
9744 tp->pipe_intr = usb_rcvintpipe(udev, 3);
9750 tp->mii.supports_gmii = 0;
9753 tp->mii.supports_gmii = 1;
9757 ret = rtl_ops_init(tp);
9763 mutex_init(&tp->control);
9764 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
9765 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
9766 tasklet_setup(&tp->tx_tl, bottom_half);
9767 tasklet_disable(&tp->tx_tl);
9769 netdev->netdev_ops = &rtl8152_netdev_ops;
9770 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
9772 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9773 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
9774 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
9775 NETIF_F_HW_VLAN_CTAG_TX;
9776 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9777 NETIF_F_TSO | NETIF_F_FRAGLIST |
9778 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
9779 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
9780 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
9781 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
9782 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
9784 if (tp->version == RTL_VER_01) {
9785 netdev->features &= ~NETIF_F_RXCSUM;
9786 netdev->hw_features &= ~NETIF_F_RXCSUM;
9789 tp->lenovo_macpassthru = rtl8152_supports_lenovo_macpassthru(udev);
9791 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
9792 (!strcmp(udev->serial, "000001000000") ||
9793 !strcmp(udev->serial, "000002000000"))) {
9794 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
9795 tp->dell_tb_rx_agg_bug = 1;
9798 netdev->ethtool_ops = &ops;
9799 netif_set_tso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
9801 /* MTU range: 68 - 1500 or 9194 */
9802 netdev->min_mtu = ETH_MIN_MTU;
9803 switch (tp->version) {
9811 netdev->max_mtu = size_to_mtu(9 * 1024);
9815 netdev->max_mtu = size_to_mtu(15 * 1024);
9820 netdev->max_mtu = size_to_mtu(16 * 1024);
9826 netdev->max_mtu = ETH_DATA_LEN;
9830 tp->mii.dev = netdev;
9831 tp->mii.mdio_read = read_mii_word;
9832 tp->mii.mdio_write = write_mii_word;
9833 tp->mii.phy_id_mask = 0x3f;
9834 tp->mii.reg_num_mask = 0x1f;
9835 tp->mii.phy_id = R8152_PHY_ID;
9837 tp->autoneg = AUTONEG_ENABLE;
9838 tp->speed = SPEED_100;
9839 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
9840 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
9841 if (tp->mii.supports_gmii) {
9842 if (tp->support_2500full &&
9843 tp->udev->speed >= USB_SPEED_SUPER) {
9844 tp->speed = SPEED_2500;
9845 tp->advertising |= RTL_ADVERTISED_2500_FULL;
9847 tp->speed = SPEED_1000;
9849 tp->advertising |= RTL_ADVERTISED_1000_FULL;
9851 tp->duplex = DUPLEX_FULL;
9853 tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
9854 tp->rx_pending = 10 * RTL8152_MAX_RX;
9856 intf->needs_remote_wakeup = 1;
9858 if (!rtl_can_wakeup(tp))
9859 __rtl_set_wol(tp, 0);
9861 tp->saved_wolopts = __rtl_get_wol(tp);
9863 tp->rtl_ops.init(tp);
9864 #if IS_BUILTIN(CONFIG_USB_RTL8152)
9865 /* Retry in case request_firmware() is not ready yet. */
9866 tp->rtl_fw.retry = true;
9868 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
9869 set_ethernet_addr(tp, false);
9871 usb_set_intfdata(intf, tp);
9873 netif_napi_add(netdev, &tp->napi, r8152_poll);
9875 ret = register_netdev(netdev);
9877 dev_err(&intf->dev, "couldn't register the device\n");
9881 if (tp->saved_wolopts)
9882 device_set_wakeup_enable(&udev->dev, true);
9884 device_set_wakeup_enable(&udev->dev, false);
9886 /* If we saw a control transfer error while probing then we may
9887 * want to try probe() again. Consider this an error.
9889 if (test_bit(PROBE_SHOULD_RETRY, &tp->flags))
9892 set_bit(PROBED_WITH_NO_ERRORS, &tp->flags);
9893 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
9898 unregister_netdev(netdev);
9901 tasklet_kill(&tp->tx_tl);
9902 cancel_delayed_work_sync(&tp->hw_phy_work);
9903 if (tp->rtl_ops.unload)
9904 tp->rtl_ops.unload(tp);
9905 rtl8152_release_firmware(tp);
9906 usb_set_intfdata(intf, NULL);
9908 if (test_bit(PROBE_SHOULD_RETRY, &tp->flags))
9911 free_netdev(netdev);
9915 #define RTL8152_PROBE_TRIES 3
9917 static int rtl8152_probe(struct usb_interface *intf,
9918 const struct usb_device_id *id)
9924 if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC)
9927 if (!rtl_check_vendor_ok(intf))
9930 version = rtl8152_get_version(intf);
9931 if (version == RTL_VER_UNKNOWN)
9934 for (i = 0; i < RTL8152_PROBE_TRIES; i++) {
9935 ret = rtl8152_probe_once(intf, id, version);
9939 if (ret == -EAGAIN) {
9941 "r8152 failed probe after %d tries; giving up\n", i);
9948 static void rtl8152_disconnect(struct usb_interface *intf)
9950 struct r8152 *tp = usb_get_intfdata(intf);
9952 usb_set_intfdata(intf, NULL);
9956 unregister_netdev(tp->netdev);
9957 tasklet_kill(&tp->tx_tl);
9958 cancel_delayed_work_sync(&tp->hw_phy_work);
9959 if (tp->rtl_ops.unload)
9960 tp->rtl_ops.unload(tp);
9961 rtl8152_release_firmware(tp);
9962 free_netdev(tp->netdev);
9966 /* table of devices that work with this driver */
9967 static const struct usb_device_id rtl8152_table[] = {
9969 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8050) },
9970 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8053) },
9971 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8152) },
9972 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) },
9973 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) },
9974 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) },
9977 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) },
9978 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6) },
9979 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927) },
9980 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e) },
9981 { USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101) },
9982 { USB_DEVICE(VENDOR_ID_LENOVO, 0x304f) },
9983 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3054) },
9984 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3062) },
9985 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3069) },
9986 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3082) },
9987 { USB_DEVICE(VENDOR_ID_LENOVO, 0x7205) },
9988 { USB_DEVICE(VENDOR_ID_LENOVO, 0x720c) },
9989 { USB_DEVICE(VENDOR_ID_LENOVO, 0x7214) },
9990 { USB_DEVICE(VENDOR_ID_LENOVO, 0x721e) },
9991 { USB_DEVICE(VENDOR_ID_LENOVO, 0xa387) },
9992 { USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) },
9993 { USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff) },
9994 { USB_DEVICE(VENDOR_ID_TPLINK, 0x0601) },
9995 { USB_DEVICE(VENDOR_ID_DLINK, 0xb301) },
9999 MODULE_DEVICE_TABLE(usb, rtl8152_table);
10001 static struct usb_driver rtl8152_driver = {
10002 .name = MODULENAME,
10003 .id_table = rtl8152_table,
10004 .probe = rtl8152_probe,
10005 .disconnect = rtl8152_disconnect,
10006 .suspend = rtl8152_suspend,
10007 .resume = rtl8152_resume,
10008 .reset_resume = rtl8152_reset_resume,
10009 .pre_reset = rtl8152_pre_reset,
10010 .post_reset = rtl8152_post_reset,
10011 .supports_autosuspend = 1,
10012 .disable_hub_initiated_lpm = 1,
10015 static int rtl8152_cfgselector_probe(struct usb_device *udev)
10017 struct usb_host_config *c;
10018 int i, num_configs;
10020 /* Switch the device to vendor mode, if and only if the vendor mode
10021 * driver supports it.
10023 if (__rtl_get_hw_ver(udev) == RTL_VER_UNKNOWN)
10026 /* The vendor mode is not always config #1, so to find it out. */
10028 num_configs = udev->descriptor.bNumConfigurations;
10029 for (i = 0; i < num_configs; (i++, c++)) {
10030 struct usb_interface_descriptor *desc = NULL;
10032 if (!c->desc.bNumInterfaces)
10034 desc = &c->intf_cache[0]->altsetting->desc;
10035 if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC)
10039 if (i == num_configs)
10042 if (usb_set_configuration(udev, c->desc.bConfigurationValue)) {
10043 dev_err(&udev->dev, "Failed to set configuration %d\n",
10044 c->desc.bConfigurationValue);
10051 static struct usb_device_driver rtl8152_cfgselector_driver = {
10052 .name = MODULENAME "-cfgselector",
10053 .probe = rtl8152_cfgselector_probe,
10054 .id_table = rtl8152_table,
10055 .generic_subclass = 1,
10056 .supports_autosuspend = 1,
10059 static int __init rtl8152_driver_init(void)
10063 ret = usb_register_device_driver(&rtl8152_cfgselector_driver, THIS_MODULE);
10066 return usb_register(&rtl8152_driver);
10069 static void __exit rtl8152_driver_exit(void)
10071 usb_deregister(&rtl8152_driver);
10072 usb_deregister_device_driver(&rtl8152_cfgselector_driver);
10075 module_init(rtl8152_driver_init);
10076 module_exit(rtl8152_driver_exit);
10078 MODULE_AUTHOR(DRIVER_AUTHOR);
10079 MODULE_DESCRIPTION(DRIVER_DESC);
10080 MODULE_LICENSE("GPL");
10081 MODULE_VERSION(DRIVER_VERSION);