1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29 #include <linux/usb/r8152.h>
32 /* Information for net-next */
33 #define NETNEXT_VERSION "12"
35 /* Information for net */
36 #define NET_VERSION "13"
38 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
39 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
40 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
41 #define MODULENAME "r8152"
43 #define R8152_PHY_ID 32
45 #define PLA_IDR 0xc000
46 #define PLA_RCR 0xc010
47 #define PLA_RCR1 0xc012
48 #define PLA_RMS 0xc016
49 #define PLA_RXFIFO_CTRL0 0xc0a0
50 #define PLA_RXFIFO_FULL 0xc0a2
51 #define PLA_RXFIFO_CTRL1 0xc0a4
52 #define PLA_RX_FIFO_FULL 0xc0a6
53 #define PLA_RXFIFO_CTRL2 0xc0a8
54 #define PLA_RX_FIFO_EMPTY 0xc0aa
55 #define PLA_DMY_REG0 0xc0b0
56 #define PLA_FMC 0xc0b4
57 #define PLA_CFG_WOL 0xc0b6
58 #define PLA_TEREDO_CFG 0xc0bc
59 #define PLA_TEREDO_WAKE_BASE 0xc0c4
60 #define PLA_MAR 0xcd00
61 #define PLA_BACKUP 0xd000
62 #define PLA_BDC_CR 0xd1a0
63 #define PLA_TEREDO_TIMER 0xd2cc
64 #define PLA_REALWOW_TIMER 0xd2e8
65 #define PLA_UPHY_TIMER 0xd388
66 #define PLA_SUSPEND_FLAG 0xd38a
67 #define PLA_INDICATE_FALG 0xd38c
68 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
69 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
70 #define PLA_EXTRA_STATUS 0xd398
71 #define PLA_GPHY_CTRL 0xd3ae
72 #define PLA_POL_GPIO_CTRL 0xdc6a
73 #define PLA_EFUSE_DATA 0xdd00
74 #define PLA_EFUSE_CMD 0xdd02
75 #define PLA_LEDSEL 0xdd90
76 #define PLA_LED_FEATURE 0xdd92
77 #define PLA_PHYAR 0xde00
78 #define PLA_BOOT_CTRL 0xe004
79 #define PLA_LWAKE_CTRL_REG 0xe007
80 #define PLA_GPHY_INTR_IMR 0xe022
81 #define PLA_EEE_CR 0xe040
82 #define PLA_EEE_TXTWSYS 0xe04c
83 #define PLA_EEE_TXTWSYS_2P5G 0xe058
84 #define PLA_EEEP_CR 0xe080
85 #define PLA_MAC_PWR_CTRL 0xe0c0
86 #define PLA_MAC_PWR_CTRL2 0xe0ca
87 #define PLA_MAC_PWR_CTRL3 0xe0cc
88 #define PLA_MAC_PWR_CTRL4 0xe0ce
89 #define PLA_WDT6_CTRL 0xe428
90 #define PLA_TCR0 0xe610
91 #define PLA_TCR1 0xe612
92 #define PLA_MTPS 0xe615
93 #define PLA_TXFIFO_CTRL 0xe618
94 #define PLA_TXFIFO_FULL 0xe61a
95 #define PLA_RSTTALLY 0xe800
97 #define PLA_CRWECR 0xe81c
98 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
99 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
100 #define PLA_CONFIG5 0xe822
101 #define PLA_PHY_PWR 0xe84c
102 #define PLA_OOB_CTRL 0xe84f
103 #define PLA_CPCR 0xe854
104 #define PLA_MISC_0 0xe858
105 #define PLA_MISC_1 0xe85a
106 #define PLA_OCP_GPHY_BASE 0xe86c
107 #define PLA_TALLYCNT 0xe890
108 #define PLA_SFF_STS_7 0xe8de
109 #define PLA_PHYSTATUS 0xe908
110 #define PLA_CONFIG6 0xe90a /* CONFIG6 */
111 #define PLA_USB_CFG 0xe952
112 #define PLA_BP_BA 0xfc26
113 #define PLA_BP_0 0xfc28
114 #define PLA_BP_1 0xfc2a
115 #define PLA_BP_2 0xfc2c
116 #define PLA_BP_3 0xfc2e
117 #define PLA_BP_4 0xfc30
118 #define PLA_BP_5 0xfc32
119 #define PLA_BP_6 0xfc34
120 #define PLA_BP_7 0xfc36
121 #define PLA_BP_EN 0xfc38
123 #define USB_USB2PHY 0xb41e
124 #define USB_SSPHYLINK1 0xb426
125 #define USB_SSPHYLINK2 0xb428
126 #define USB_L1_CTRL 0xb45e
127 #define USB_U2P3_CTRL 0xb460
128 #define USB_CSR_DUMMY1 0xb464
129 #define USB_CSR_DUMMY2 0xb466
130 #define USB_DEV_STAT 0xb808
131 #define USB_CONNECT_TIMER 0xcbf8
132 #define USB_MSC_TIMER 0xcbfc
133 #define USB_BURST_SIZE 0xcfc0
134 #define USB_FW_FIX_EN0 0xcfca
135 #define USB_FW_FIX_EN1 0xcfcc
136 #define USB_LPM_CONFIG 0xcfd8
137 #define USB_ECM_OPTION 0xcfee
138 #define USB_CSTMR 0xcfef /* RTL8153A */
139 #define USB_MISC_2 0xcfff
140 #define USB_ECM_OP 0xd26b
141 #define USB_GPHY_CTRL 0xd284
142 #define USB_SPEED_OPTION 0xd32a
143 #define USB_FW_CTRL 0xd334 /* RTL8153B */
144 #define USB_FC_TIMER 0xd340
145 #define USB_USB_CTRL 0xd406
146 #define USB_PHY_CTRL 0xd408
147 #define USB_TX_AGG 0xd40a
148 #define USB_RX_BUF_TH 0xd40c
149 #define USB_USB_TIMER 0xd428
150 #define USB_RX_EARLY_TIMEOUT 0xd42c
151 #define USB_RX_EARLY_SIZE 0xd42e
152 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
153 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
154 #define USB_TX_DMA 0xd434
155 #define USB_UPT_RXDMA_OWN 0xd437
156 #define USB_UPHY3_MDCMDIO 0xd480
157 #define USB_TOLERANCE 0xd490
158 #define USB_LPM_CTRL 0xd41a
159 #define USB_BMU_RESET 0xd4b0
160 #define USB_BMU_CONFIG 0xd4b4
161 #define USB_U1U2_TIMER 0xd4da
162 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
163 #define USB_RX_AGGR_NUM 0xd4ee
164 #define USB_UPS_CTRL 0xd800
165 #define USB_POWER_CUT 0xd80a
166 #define USB_MISC_0 0xd81a
167 #define USB_MISC_1 0xd81f
168 #define USB_AFE_CTRL2 0xd824
169 #define USB_UPHY_XTAL 0xd826
170 #define USB_UPS_CFG 0xd842
171 #define USB_UPS_FLAGS 0xd848
172 #define USB_WDT1_CTRL 0xe404
173 #define USB_WDT11_CTRL 0xe43c
174 #define USB_BP_BA PLA_BP_BA
175 #define USB_BP_0 PLA_BP_0
176 #define USB_BP_1 PLA_BP_1
177 #define USB_BP_2 PLA_BP_2
178 #define USB_BP_3 PLA_BP_3
179 #define USB_BP_4 PLA_BP_4
180 #define USB_BP_5 PLA_BP_5
181 #define USB_BP_6 PLA_BP_6
182 #define USB_BP_7 PLA_BP_7
183 #define USB_BP_EN PLA_BP_EN /* RTL8153A */
184 #define USB_BP_8 0xfc38 /* RTL8153B */
185 #define USB_BP_9 0xfc3a
186 #define USB_BP_10 0xfc3c
187 #define USB_BP_11 0xfc3e
188 #define USB_BP_12 0xfc40
189 #define USB_BP_13 0xfc42
190 #define USB_BP_14 0xfc44
191 #define USB_BP_15 0xfc46
192 #define USB_BP2_EN 0xfc48
195 #define OCP_ALDPS_CONFIG 0x2010
196 #define OCP_EEE_CONFIG1 0x2080
197 #define OCP_EEE_CONFIG2 0x2092
198 #define OCP_EEE_CONFIG3 0x2094
199 #define OCP_BASE_MII 0xa400
200 #define OCP_EEE_AR 0xa41a
201 #define OCP_EEE_DATA 0xa41c
202 #define OCP_PHY_STATUS 0xa420
203 #define OCP_INTR_EN 0xa424
204 #define OCP_NCTL_CFG 0xa42c
205 #define OCP_POWER_CFG 0xa430
206 #define OCP_EEE_CFG 0xa432
207 #define OCP_SRAM_ADDR 0xa436
208 #define OCP_SRAM_DATA 0xa438
209 #define OCP_DOWN_SPEED 0xa442
210 #define OCP_EEE_ABLE 0xa5c4
211 #define OCP_EEE_ADV 0xa5d0
212 #define OCP_EEE_LPABLE 0xa5d2
213 #define OCP_10GBT_CTRL 0xa5d4
214 #define OCP_10GBT_STAT 0xa5d6
215 #define OCP_EEE_ADV2 0xa6d4
216 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
217 #define OCP_PHY_PATCH_STAT 0xb800
218 #define OCP_PHY_PATCH_CMD 0xb820
219 #define OCP_PHY_LOCK 0xb82e
220 #define OCP_ADC_IOFFSET 0xbcfc
221 #define OCP_ADC_CFG 0xbc06
222 #define OCP_SYSCLK_CFG 0xc416
225 #define SRAM_GREEN_CFG 0x8011
226 #define SRAM_LPF_CFG 0x8012
227 #define SRAM_GPHY_FW_VER 0x801e
228 #define SRAM_10M_AMP1 0x8080
229 #define SRAM_10M_AMP2 0x8082
230 #define SRAM_IMPEDANCE 0x8084
231 #define SRAM_PHY_LOCK 0xb82e
234 #define RCR_AAP 0x00000001
235 #define RCR_APM 0x00000002
236 #define RCR_AM 0x00000004
237 #define RCR_AB 0x00000008
238 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
239 #define SLOT_EN BIT(11)
242 #define OUTER_VLAN BIT(7)
243 #define INNER_VLAN BIT(6)
245 /* PLA_RXFIFO_CTRL0 */
246 #define RXFIFO_THR1_NORMAL 0x00080002
247 #define RXFIFO_THR1_OOB 0x01800003
249 /* PLA_RXFIFO_FULL */
250 #define RXFIFO_FULL_MASK 0xfff
252 /* PLA_RXFIFO_CTRL1 */
253 #define RXFIFO_THR2_FULL 0x00000060
254 #define RXFIFO_THR2_HIGH 0x00000038
255 #define RXFIFO_THR2_OOB 0x0000004a
256 #define RXFIFO_THR2_NORMAL 0x00a0
258 /* PLA_RXFIFO_CTRL2 */
259 #define RXFIFO_THR3_FULL 0x00000078
260 #define RXFIFO_THR3_HIGH 0x00000048
261 #define RXFIFO_THR3_OOB 0x0000005a
262 #define RXFIFO_THR3_NORMAL 0x0110
264 /* PLA_TXFIFO_CTRL */
265 #define TXFIFO_THR_NORMAL 0x00400008
266 #define TXFIFO_THR_NORMAL2 0x01000008
269 #define ECM_ALDPS 0x0002
272 #define FMC_FCR_MCU_EN 0x0001
275 #define EEEP_CR_EEEP_TX 0x0002
278 #define WDT6_SET_MODE 0x0010
281 #define TCR0_TX_EMPTY 0x0800
282 #define TCR0_AUTO_FIFO 0x0080
285 #define VERSION_MASK 0x7cf0
286 #define IFG_MASK (BIT(3) | BIT(9) | BIT(8))
287 #define IFG_144NS BIT(9)
288 #define IFG_96NS (BIT(9) | BIT(8))
291 #define MTPS_JUMBO (12 * 1024 / 64)
292 #define MTPS_DEFAULT (6 * 1024 / 64)
295 #define TALLY_RESET 0x0001
303 #define CRWECR_NORAML 0x00
304 #define CRWECR_CONFIG 0xc0
307 #define NOW_IS_OOB 0x80
308 #define TXFIFO_EMPTY 0x20
309 #define RXFIFO_EMPTY 0x10
310 #define LINK_LIST_READY 0x02
311 #define DIS_MCU_CLROOB 0x01
312 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
315 #define RXDY_GATED_EN 0x0008
318 #define RE_INIT_LL 0x8000
319 #define MCU_BORW_EN 0x4000
322 #define FLOW_CTRL_EN BIT(0)
323 #define CPCR_RX_VLAN 0x0040
326 #define MAGIC_EN 0x0001
329 #define TEREDO_SEL 0x8000
330 #define TEREDO_WAKE_MASK 0x7f00
331 #define TEREDO_RS_EVENT_MASK 0x00fe
332 #define OOB_TEREDO_EN 0x0001
335 #define ALDPS_PROXY_MODE 0x0001
338 #define EFUSE_READ_CMD BIT(15)
339 #define EFUSE_DATA_BIT16 BIT(7)
342 #define LINK_ON_WAKE_EN 0x0010
343 #define LINK_OFF_WAKE_EN 0x0008
346 #define LANWAKE_CLR_EN BIT(0)
349 #define EN_XG_LIP BIT(1)
350 #define EN_G_LIP BIT(2)
353 #define BWF_EN 0x0040
354 #define MWF_EN 0x0020
355 #define UWF_EN 0x0010
356 #define LAN_WAKE_EN 0x0002
358 /* PLA_LED_FEATURE */
359 #define LED_MODE_MASK 0x0700
362 #define TX_10M_IDLE_EN 0x0080
363 #define PFM_PWM_SWITCH 0x0040
364 #define TEST_IO_OFF BIT(4)
366 /* PLA_MAC_PWR_CTRL */
367 #define D3_CLK_GATED_EN 0x00004000
368 #define MCU_CLK_RATIO 0x07010f07
369 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
370 #define ALDPS_SPDWN_RATIO 0x0f87
372 /* PLA_MAC_PWR_CTRL2 */
373 #define EEE_SPDWN_RATIO 0x8007
374 #define MAC_CLK_SPDWN_EN BIT(15)
375 #define EEE_SPDWN_RATIO_MASK 0xff
377 /* PLA_MAC_PWR_CTRL3 */
378 #define PLA_MCU_SPDWN_EN BIT(14)
379 #define PKT_AVAIL_SPDWN_EN 0x0100
380 #define SUSPEND_SPDWN_EN 0x0004
381 #define U1U2_SPDWN_EN 0x0002
382 #define L1_SPDWN_EN 0x0001
384 /* PLA_MAC_PWR_CTRL4 */
385 #define PWRSAVE_SPDWN_EN 0x1000
386 #define RXDV_SPDWN_EN 0x0800
387 #define TX10MIDLE_EN 0x0100
388 #define IDLE_SPDWN_EN BIT(6)
389 #define TP100_SPDWN_EN 0x0020
390 #define TP500_SPDWN_EN 0x0010
391 #define TP1000_SPDWN_EN 0x0008
392 #define EEE_SPDWN_EN 0x0001
394 /* PLA_GPHY_INTR_IMR */
395 #define GPHY_STS_MSK 0x0001
396 #define SPEED_DOWN_MSK 0x0002
397 #define SPDWN_RXDV_MSK 0x0004
398 #define SPDWN_LINKCHG_MSK 0x0008
401 #define PHYAR_FLAG 0x80000000
404 #define EEE_RX_EN 0x0001
405 #define EEE_TX_EN 0x0002
408 #define AUTOLOAD_DONE 0x0002
410 /* PLA_LWAKE_CTRL_REG */
411 #define LANWAKE_PIN BIT(7)
413 /* PLA_SUSPEND_FLAG */
414 #define LINK_CHG_EVENT BIT(0)
416 /* PLA_INDICATE_FALG */
417 #define UPCOMING_RUNTIME_D3 BIT(0)
419 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
420 #define DEBUG_OE BIT(0)
421 #define DEBUG_LTSSM 0x0082
423 /* PLA_EXTRA_STATUS */
424 #define CUR_LINK_OK BIT(15)
425 #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
426 #define LINK_CHANGE_FLAG BIT(8)
427 #define POLL_LINK_CHG BIT(0)
430 #define GPHY_FLASH BIT(1)
432 /* PLA_POL_GPIO_CTRL */
433 #define DACK_DET_EN BIT(15)
434 #define POL_GPHY_PATCH BIT(4)
437 #define USB2PHY_SUSPEND 0x0001
438 #define USB2PHY_L1 0x0002
441 #define DELAY_PHY_PWR_CHG BIT(1)
444 #define pwd_dn_scale_mask 0x3ffe
445 #define pwd_dn_scale(x) ((x) << 1)
448 #define DYNAMIC_BURST 0x0001
451 #define EP4_FULL_FC 0x0001
454 #define STAT_SPEED_MASK 0x0006
455 #define STAT_SPEED_HIGH 0x0000
456 #define STAT_SPEED_FULL 0x0002
459 #define FW_FIX_SUSPEND BIT(14)
462 #define FW_IP_RESET_EN BIT(9)
465 #define LPM_U1U2_EN BIT(0)
468 #define TX_AGG_MAX_THRESHOLD 0x03
471 #define RX_THR_SUPPER 0x0c350180
472 #define RX_THR_HIGH 0x7a120180
473 #define RX_THR_SLOW 0xffff0180
474 #define RX_THR_B 0x00010001
477 #define TEST_MODE_DISABLE 0x00000001
478 #define TX_SIZE_ADJUST1 0x00000100
481 #define BMU_RESET_EP_IN 0x01
482 #define BMU_RESET_EP_OUT 0x02
485 #define ACT_ODMA BIT(1)
487 /* USB_UPT_RXDMA_OWN */
488 #define OWN_UPDATE BIT(0)
489 #define OWN_CLEAR BIT(1)
492 #define FC_PATCH_TASK BIT(1)
494 /* USB_RX_AGGR_NUM */
495 #define RX_AGGR_NUM_MASK 0x1ff
498 #define POWER_CUT 0x0100
500 /* USB_PM_CTRL_STATUS */
501 #define RESUME_INDICATE 0x0001
504 #define BYPASS_MAC_RESET BIT(5)
507 #define FORCE_SUPER BIT(0)
510 #define UPS_FORCE_PWR_DOWN BIT(0)
513 #define EN_ALL_SPEED BIT(0)
516 #define GPHY_PATCH_DONE BIT(2)
517 #define BYPASS_FLASH BIT(5)
518 #define BACKUP_RESTRORE BIT(6)
520 /* USB_SPEED_OPTION */
521 #define RG_PWRDN_EN BIT(8)
522 #define ALL_SPEED_OFF BIT(9)
525 #define FLOW_CTRL_PATCH_OPT BIT(1)
526 #define AUTO_SPEEDUP BIT(3)
527 #define FLOW_CTRL_PATCH_2 BIT(8)
530 #define CTRL_TIMER_EN BIT(15)
533 #define CDC_ECM_EN BIT(3)
534 #define RX_AGG_DISABLE 0x0010
535 #define RX_ZERO_EN 0x0080
538 #define U2P3_ENABLE 0x0001
539 #define RX_DETECT8 BIT(3)
542 #define PWR_EN 0x0001
543 #define PHASE2_EN 0x0008
544 #define UPS_EN BIT(4)
545 #define USP_PREWAKE BIT(5)
548 #define PCUT_STATUS 0x0001
550 /* USB_RX_EARLY_TIMEOUT */
551 #define COALESCE_SUPER 85000U
552 #define COALESCE_HIGH 250000U
553 #define COALESCE_SLOW 524280U
556 #define WTD1_EN BIT(0)
559 #define TIMER11_EN 0x0001
562 /* bit 4 ~ 5: fifo empty boundary */
563 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
564 /* bit 2 ~ 3: LMP timer */
565 #define LPM_TIMER_MASK 0x0c
566 #define LPM_TIMER_500MS 0x04 /* 500 ms */
567 #define LPM_TIMER_500US 0x0c /* 500 us */
568 #define ROK_EXIT_LPM 0x02
571 #define SEN_VAL_MASK 0xf800
572 #define SEN_VAL_NORMAL 0xa000
573 #define SEL_RXIDLE 0x0100
576 #define OOBS_POLLING BIT(8)
579 #define SAW_CNT_1MS_MASK 0x0fff
580 #define MID_REVERSE BIT(5) /* RTL8156A */
583 #define UPS_FLAGS_R_TUNE BIT(0)
584 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
585 #define UPS_FLAGS_250M_CKDIV BIT(2)
586 #define UPS_FLAGS_EN_ALDPS BIT(3)
587 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
588 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
589 #define ups_flags_speed(x) ((x) << 16)
590 #define UPS_FLAGS_EN_EEE BIT(20)
591 #define UPS_FLAGS_EN_500M_EEE BIT(21)
592 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
593 #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
594 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
595 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
596 #define UPS_FLAGS_EN_GREEN BIT(26)
597 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
613 /* OCP_ALDPS_CONFIG */
614 #define ENPWRSAVE 0x8000
615 #define ENPDNPS 0x0200
616 #define LINKENA 0x0100
617 #define DIS_SDSAVE 0x0010
620 #define PHY_STAT_MASK 0x0007
621 #define PHY_STAT_EXT_INIT 2
622 #define PHY_STAT_LAN_ON 3
623 #define PHY_STAT_PWRDN 5
626 #define INTR_SPEED_FORCE BIT(3)
629 #define PGA_RETURN_EN BIT(1)
632 #define EEE_CLKDIV_EN 0x8000
633 #define EN_ALDPS 0x0004
634 #define EN_10M_PLLOFF 0x0001
636 /* OCP_EEE_CONFIG1 */
637 #define RG_TXLPI_MSK_HFDUP 0x8000
638 #define RG_MATCLR_EN 0x4000
639 #define EEE_10_CAP 0x2000
640 #define EEE_NWAY_EN 0x1000
641 #define TX_QUIET_EN 0x0200
642 #define RX_QUIET_EN 0x0100
643 #define sd_rise_time_mask 0x0070
644 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
645 #define RG_RXLPI_MSK_HFDUP 0x0008
646 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
648 /* OCP_EEE_CONFIG2 */
649 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
650 #define RG_DACQUIET_EN 0x0400
651 #define RG_LDVQUIET_EN 0x0200
652 #define RG_CKRSEL 0x0020
653 #define RG_EEEPRG_EN 0x0010
655 /* OCP_EEE_CONFIG3 */
656 #define fast_snr_mask 0xff80
657 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
658 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
659 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
662 /* bit[15:14] function */
663 #define FUN_ADDR 0x0000
664 #define FUN_DATA 0x4000
665 /* bit[4:0] device addr */
668 #define CTAP_SHORT_EN 0x0040
669 #define EEE10_EN 0x0010
672 #define EN_EEE_CMODE BIT(14)
673 #define EN_EEE_1000 BIT(13)
674 #define EN_EEE_100 BIT(12)
675 #define EN_10M_CLKDIV BIT(11)
676 #define EN_10M_BGOFF 0x0080
679 #define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */
682 #define TXDIS_STATE 0x01
683 #define ABD_STATE 0x02
685 /* OCP_PHY_PATCH_STAT */
686 #define PATCH_READY BIT(6)
688 /* OCP_PHY_PATCH_CMD */
689 #define PATCH_REQUEST BIT(4)
692 #define PATCH_LOCK BIT(0)
695 #define CKADSEL_L 0x0100
696 #define ADC_EN 0x0080
697 #define EN_EMI_L 0x0040
700 #define sysclk_div_expo(x) (min(x, 5) << 8)
701 #define clk_div_expo(x) (min(x, 5) << 4)
704 #define GREEN_ETH_EN BIT(15)
705 #define R_TUNE_EN BIT(11)
708 #define LPF_AUTO_TUNE 0x8000
711 #define GDAC_IB_UPALL 0x0008
714 #define AMP_DN 0x0200
717 #define RX_DRIVING_MASK 0x6000
720 #define PHY_PATCH_LOCK 0x0001
723 #define AD_MASK 0xfee0
724 #define BND_MASK 0x0004
725 #define BD_MASK 0x0001
727 #define PASS_THRU_MASK 0x1
729 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
731 enum rtl_register_content {
744 #define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
745 #define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
747 #define RTL8152_MAX_TX 4
748 #define RTL8152_MAX_RX 10
753 #define RTL8152_RX_MAX_PENDING 4096
754 #define RTL8152_RXFG_HEADSZ 256
756 #define INTR_LINK 0x0004
758 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
759 #define RTL8153_RMS RTL8153_MAX_PACKET
760 #define RTL8152_TX_TIMEOUT (5 * HZ)
761 #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
762 #define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
763 #define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
767 RTL8152_INACCESSIBLE = 0,
777 PROBED_WITH_NO_ERRORS,
781 #define DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB 0x721e
782 #define DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK 0x3054
783 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
784 #define DEVICE_ID_THINKPAD_USB_C_DONGLE 0x720c
785 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
786 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3 0x3062
788 struct tally_counter {
795 __le32 tx_one_collision;
796 __le32 tx_multi_collision;
806 #define RX_LEN_MASK 0x7fff
809 #define RD_UDP_CS BIT(23)
810 #define RD_TCP_CS BIT(22)
811 #define RD_IPV6_CS BIT(20)
812 #define RD_IPV4_CS BIT(19)
815 #define IPF BIT(23) /* IP checksum fail */
816 #define UDPF BIT(22) /* UDP checksum fail */
817 #define TCPF BIT(21) /* TCP checksum fail */
818 #define RX_VLAN_TAG BIT(16)
827 #define TX_FS BIT(31) /* First segment of a packet */
828 #define TX_LS BIT(30) /* Final segment of a packet */
829 #define GTSENDV4 BIT(28)
830 #define GTSENDV6 BIT(27)
831 #define GTTCPHO_SHIFT 18
832 #define GTTCPHO_MAX 0x7fU
833 #define TX_LEN_MAX 0x3ffffU
836 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
837 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
838 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
839 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
841 #define MSS_MAX 0x7ffU
842 #define TCPHO_SHIFT 17
843 #define TCPHO_MAX 0x7ffU
844 #define TX_VLAN_TAG BIT(16)
850 struct list_head list, info_list;
852 struct r8152 *context;
858 struct list_head list;
860 struct r8152 *context;
869 struct usb_device *udev;
870 struct napi_struct napi;
871 struct usb_interface *intf;
872 struct net_device *netdev;
873 struct urb *intr_urb;
874 struct tx_agg tx_info[RTL8152_MAX_TX];
875 struct list_head rx_info, rx_used;
876 struct list_head rx_done, tx_free;
877 struct sk_buff_head tx_queue, rx_queue;
878 spinlock_t rx_lock, tx_lock;
879 struct delayed_work schedule, hw_phy_work;
880 struct mii_if_info mii;
881 struct mutex control; /* use for hw setting */
882 #ifdef CONFIG_PM_SLEEP
883 struct notifier_block pm_notifier;
885 struct tasklet_struct tx_tl;
888 void (*init)(struct r8152 *tp);
889 int (*enable)(struct r8152 *tp);
890 void (*disable)(struct r8152 *tp);
891 void (*up)(struct r8152 *tp);
892 void (*down)(struct r8152 *tp);
893 void (*unload)(struct r8152 *tp);
894 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
895 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
896 bool (*in_nway)(struct r8152 *tp);
897 void (*hw_phy_cfg)(struct r8152 *tp);
898 void (*autosuspend_en)(struct r8152 *tp, bool enable);
899 void (*change_mtu)(struct r8152 *tp);
912 u32 eee_plloff_100:1;
913 u32 eee_plloff_giga:1;
917 u32 ctap_short_off:1;
920 #define RTL_VER_SIZE 32
924 const struct firmware *fw;
926 char version[RTL_VER_SIZE];
927 int (*pre_fw)(struct r8152 *tp);
928 int (*post_fw)(struct r8152 *tp);
945 u32 fc_pause_on, fc_pause_off;
947 unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out;
949 u32 support_2500full:1;
950 u32 lenovo_macpassthru:1;
951 u32 dell_tb_rx_agg_bug:1;
960 unsigned int reg_access_reset_count;
964 * struct fw_block - block type and total length
965 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
966 * RTL_FW_USB and so on.
967 * @length: total length of the current block.
975 * struct fw_header - header of the firmware file
976 * @checksum: checksum of sha256 which is calculated from the whole file
977 * except the checksum field of the file. That is, calculate sha256
978 * from the version field to the end of the file.
979 * @version: version of this firmware.
980 * @blocks: the first firmware block of the file
984 char version[RTL_VER_SIZE];
985 struct fw_block blocks[];
988 enum rtl8152_fw_flags {
1002 enum rtl8152_fw_fixup_cmd {
1014 struct fw_phy_speed_up {
1015 struct fw_block blk_hdr;
1024 struct fw_block blk_hdr;
1025 struct fw_phy_set ver;
1029 struct fw_phy_fixup {
1030 struct fw_block blk_hdr;
1031 struct fw_phy_set setting;
1036 struct fw_phy_union {
1037 struct fw_block blk_hdr;
1040 struct fw_phy_set pre_set[2];
1041 struct fw_phy_set bp[8];
1042 struct fw_phy_set bp_en;
1049 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
1050 * The layout of the firmware block is:
1051 * <struct fw_mac> + <info> + <firmware data>.
1052 * @blk_hdr: firmware descriptor (type, length)
1053 * @fw_offset: offset of the firmware binary data. The start address of
1054 * the data would be the address of struct fw_mac + @fw_offset.
1055 * @fw_reg: the register to load the firmware. Depends on chip.
1056 * @bp_ba_addr: the register to write break point base address. Depends on
1058 * @bp_ba_value: break point base address. Depends on chip.
1059 * @bp_en_addr: the register to write break point enabled mask. Depends
1061 * @bp_en_value: break point enabled mask. Depends on the firmware.
1062 * @bp_start: the start register of break points. Depends on chip.
1063 * @bp_num: the break point number which needs to be set for this firmware.
1064 * Depends on the firmware.
1065 * @bp: break points. Depends on firmware.
1066 * @reserved: reserved space (unused)
1067 * @fw_ver_reg: the register to store the fw version.
1068 * @fw_ver_data: the firmware version of the current type.
1069 * @info: additional information for debugging, and is followed by the
1070 * binary data of firmware.
1073 struct fw_block blk_hdr;
1082 __le16 bp[16]; /* any value determined by firmware */
1090 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
1091 * This is used to set patch key when loading the firmware of PHY.
1092 * @blk_hdr: firmware descriptor (type, length)
1093 * @key_reg: the register to write the patch key.
1094 * @key_data: patch key.
1095 * @reserved: reserved space (unused)
1097 struct fw_phy_patch_key {
1098 struct fw_block blk_hdr;
1105 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
1106 * The layout of the firmware block is:
1107 * <struct fw_phy_nc> + <info> + <firmware data>.
1108 * @blk_hdr: firmware descriptor (type, length)
1109 * @fw_offset: offset of the firmware binary data. The start address of
1110 * the data would be the address of struct fw_phy_nc + @fw_offset.
1111 * @fw_reg: the register to load the firmware. Depends on chip.
1112 * @ba_reg: the register to write the base address. Depends on chip.
1113 * @ba_data: base address. Depends on chip.
1114 * @patch_en_addr: the register of enabling patch mode. Depends on chip.
1115 * @patch_en_value: patch mode enabled mask. Depends on the firmware.
1116 * @mode_reg: the regitster of switching the mode.
1117 * @mode_pre: the mode needing to be set before loading the firmware.
1118 * @mode_post: the mode to be set when finishing to load the firmware.
1119 * @reserved: reserved space (unused)
1120 * @bp_start: the start register of break points. Depends on chip.
1121 * @bp_num: the break point number which needs to be set for this firmware.
1122 * Depends on the firmware.
1123 * @bp: break points. Depends on firmware.
1124 * @info: additional information for debugging, and is followed by the
1125 * binary data of firmware.
1128 struct fw_block blk_hdr;
1133 __le16 patch_en_addr;
1134 __le16 patch_en_value;
1153 RTL_FW_PHY_UNION_NC,
1154 RTL_FW_PHY_UNION_NC1,
1155 RTL_FW_PHY_UNION_NC2,
1156 RTL_FW_PHY_UNION_UC2,
1157 RTL_FW_PHY_UNION_UC,
1158 RTL_FW_PHY_UNION_MISC,
1159 RTL_FW_PHY_SPEED_UP,
1164 RTL_VER_UNKNOWN = 0,
1187 TX_CSUM_SUCCESS = 0,
1192 #define RTL_ADVERTISED_10_HALF BIT(0)
1193 #define RTL_ADVERTISED_10_FULL BIT(1)
1194 #define RTL_ADVERTISED_100_HALF BIT(2)
1195 #define RTL_ADVERTISED_100_FULL BIT(3)
1196 #define RTL_ADVERTISED_1000_HALF BIT(4)
1197 #define RTL_ADVERTISED_1000_FULL BIT(5)
1198 #define RTL_ADVERTISED_2500_FULL BIT(6)
1200 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1201 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1203 static const int multicast_filter_limit = 32;
1204 static unsigned int agg_buf_sz = 16384;
1206 #define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))
1208 /* If register access fails then we block access and issue a reset. If this
1209 * happens too many times in a row without a successful access then we stop
1210 * trying to reset and just leave access blocked.
1212 #define REGISTER_ACCESS_MAX_RESETS 3
1214 static void rtl_set_inaccessible(struct r8152 *tp)
1216 set_bit(RTL8152_INACCESSIBLE, &tp->flags);
1217 smp_mb__after_atomic();
1220 static void rtl_set_accessible(struct r8152 *tp)
1222 clear_bit(RTL8152_INACCESSIBLE, &tp->flags);
1223 smp_mb__after_atomic();
1227 int r8152_control_msg(struct r8152 *tp, unsigned int pipe, __u8 request,
1228 __u8 requesttype, __u16 value, __u16 index, void *data,
1229 __u16 size, const char *msg_tag)
1231 struct usb_device *udev = tp->udev;
1234 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1237 ret = usb_control_msg(udev, pipe, request, requesttype,
1238 value, index, data, size,
1239 USB_CTRL_GET_TIMEOUT);
1241 /* No need to issue a reset to report an error if the USB device got
1242 * unplugged; just return immediately.
1247 /* If the write was successful then we're done */
1249 tp->reg_access_reset_count = 0;
1254 "Failed to %s %d bytes at %#06x/%#06x (%d)\n",
1255 msg_tag, size, value, index, ret);
1257 /* Block all future register access until we reset. Much of the code
1258 * in the driver doesn't check for errors. Notably, many parts of the
1259 * driver do a read/modify/write of a register value without
1260 * confirming that the read succeeded. Writing back modified garbage
1261 * like this can fully wedge the adapter, requiring a power cycle.
1263 rtl_set_inaccessible(tp);
1265 /* If probe hasn't yet finished, then we'll request a retry of the
1266 * whole probe routine if we get any control transfer errors. We
1267 * never have to clear this bit since we free/reallocate the whole "tp"
1268 * structure if we retry probe.
1270 if (!test_bit(PROBED_WITH_NO_ERRORS, &tp->flags)) {
1271 set_bit(PROBE_SHOULD_RETRY, &tp->flags);
1275 /* Failing to access registers in pre-reset is not surprising since we
1276 * wouldn't be resetting if things were behaving normally. The register
1277 * access we do in pre-reset isn't truly mandatory--we're just reusing
1278 * the disable() function and trying to be nice by powering the
1279 * adapter down before resetting it. Thus, if we're in pre-reset,
1280 * we'll return right away and not try to queue up yet another reset.
1281 * We know the post-reset is already coming.
1283 if (test_bit(IN_PRE_RESET, &tp->flags))
1286 if (tp->reg_access_reset_count < REGISTER_ACCESS_MAX_RESETS) {
1287 usb_queue_reset_device(tp->intf);
1288 tp->reg_access_reset_count++;
1289 } else if (tp->reg_access_reset_count == REGISTER_ACCESS_MAX_RESETS) {
1291 "Tried to reset %d times; giving up.\n",
1292 REGISTER_ACCESS_MAX_RESETS);
1299 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1304 tmp = kmalloc(size, GFP_KERNEL);
1308 ret = r8152_control_msg(tp, tp->pipe_ctrl_in,
1309 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1310 value, index, tmp, size, "read");
1313 memset(data, 0xff, size);
1315 memcpy(data, tmp, size);
1323 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1328 tmp = kmemdup(data, size, GFP_KERNEL);
1332 ret = r8152_control_msg(tp, tp->pipe_ctrl_out,
1333 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1334 value, index, tmp, size, "write");
1341 static void rtl_set_unplug(struct r8152 *tp)
1343 if (tp->udev->state == USB_STATE_NOTATTACHED)
1344 rtl_set_inaccessible(tp);
1347 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1348 void *data, u16 type)
1353 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1356 /* both size and indix must be 4 bytes align */
1357 if ((size & 3) || !size || (index & 3) || !data)
1360 if ((u32)index + (u32)size > 0xffff)
1365 ret = get_registers(tp, index, type, limit, data);
1373 ret = get_registers(tp, index, type, size, data);
1390 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1391 u16 size, void *data, u16 type)
1394 u16 byteen_start, byteen_end, byen;
1397 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1400 /* both size and indix must be 4 bytes align */
1401 if ((size & 3) || !size || (index & 3) || !data)
1404 if ((u32)index + (u32)size > 0xffff)
1407 byteen_start = byteen & BYTE_EN_START_MASK;
1408 byteen_end = byteen & BYTE_EN_END_MASK;
1410 byen = byteen_start | (byteen_start << 4);
1412 /* Split the first DWORD if the byte_en is not 0xff */
1413 if (byen != BYTE_EN_DWORD) {
1414 ret = set_registers(tp, index, type | byen, 4, data);
1424 byen = byteen_end | (byteen_end >> 4);
1426 /* Split the last DWORD if the byte_en is not 0xff */
1427 if (byen != BYTE_EN_DWORD)
1432 ret = set_registers(tp, index,
1433 type | BYTE_EN_DWORD,
1442 ret = set_registers(tp, index,
1443 type | BYTE_EN_DWORD,
1455 /* Set the last DWORD */
1456 if (byen != BYTE_EN_DWORD)
1457 ret = set_registers(tp, index, type | byen, 4, data);
1468 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1470 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1474 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1476 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1480 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1482 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1485 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1489 generic_ocp_read(tp, index, sizeof(data), &data, type);
1491 return __le32_to_cpu(data);
1494 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1496 __le32 tmp = __cpu_to_le32(data);
1498 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1501 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1505 u16 byen = BYTE_EN_WORD;
1506 u8 shift = index & 2;
1511 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1513 data = __le32_to_cpu(tmp);
1514 data >>= (shift * 8);
1520 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1524 u16 byen = BYTE_EN_WORD;
1525 u8 shift = index & 2;
1531 mask <<= (shift * 8);
1532 data <<= (shift * 8);
1536 tmp = __cpu_to_le32(data);
1538 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1541 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1545 u8 shift = index & 3;
1549 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1551 data = __le32_to_cpu(tmp);
1552 data >>= (shift * 8);
1558 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1562 u16 byen = BYTE_EN_BYTE;
1563 u8 shift = index & 3;
1569 mask <<= (shift * 8);
1570 data <<= (shift * 8);
1574 tmp = __cpu_to_le32(data);
1576 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1579 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1581 u16 ocp_base, ocp_index;
1583 ocp_base = addr & 0xf000;
1584 if (ocp_base != tp->ocp_base) {
1585 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1586 tp->ocp_base = ocp_base;
1589 ocp_index = (addr & 0x0fff) | 0xb000;
1590 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1593 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1595 u16 ocp_base, ocp_index;
1597 ocp_base = addr & 0xf000;
1598 if (ocp_base != tp->ocp_base) {
1599 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1600 tp->ocp_base = ocp_base;
1603 ocp_index = (addr & 0x0fff) | 0xb000;
1604 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1607 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1609 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1612 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1614 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1617 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1619 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1620 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1623 static u16 sram_read(struct r8152 *tp, u16 addr)
1625 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1626 return ocp_reg_read(tp, OCP_SRAM_DATA);
1629 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1631 struct r8152 *tp = netdev_priv(netdev);
1634 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1637 if (phy_id != R8152_PHY_ID)
1640 ret = r8152_mdio_read(tp, reg);
1646 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1648 struct r8152 *tp = netdev_priv(netdev);
1650 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1653 if (phy_id != R8152_PHY_ID)
1656 r8152_mdio_write(tp, reg, val);
1660 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1663 rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1666 static int __rtl8152_set_mac_address(struct net_device *netdev, void *p,
1669 struct r8152 *tp = netdev_priv(netdev);
1670 struct sockaddr *addr = p;
1671 int ret = -EADDRNOTAVAIL;
1673 if (!is_valid_ether_addr(addr->sa_data))
1677 ret = usb_autopm_get_interface(tp->intf);
1682 mutex_lock(&tp->control);
1684 eth_hw_addr_set(netdev, addr->sa_data);
1686 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1687 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1688 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1690 mutex_unlock(&tp->control);
1693 usb_autopm_put_interface(tp->intf);
1698 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1700 return __rtl8152_set_mac_address(netdev, p, false);
1703 /* Devices containing proper chips can support a persistent
1704 * host system provided MAC address.
1705 * Examples of this are Dell TB15 and Dell WD15 docks
1707 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1710 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1711 union acpi_object *obj;
1714 unsigned char buf[6];
1716 acpi_object_type mac_obj_type;
1719 if (tp->lenovo_macpassthru) {
1720 mac_obj_name = "\\MACA";
1721 mac_obj_type = ACPI_TYPE_STRING;
1724 /* test for -AD variant of RTL8153 */
1725 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1726 if ((ocp_data & AD_MASK) == 0x1000) {
1727 /* test for MAC address pass-through bit */
1728 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1729 if ((ocp_data & PASS_THRU_MASK) != 1) {
1730 netif_dbg(tp, probe, tp->netdev,
1731 "No efuse for RTL8153-AD MAC pass through\n");
1735 /* test for RTL8153-BND and RTL8153-BD */
1736 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1737 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1738 netif_dbg(tp, probe, tp->netdev,
1739 "Invalid variant for MAC pass through\n");
1744 mac_obj_name = "\\_SB.AMAC";
1745 mac_obj_type = ACPI_TYPE_BUFFER;
1749 /* returns _AUXMAC_#AABBCCDDEEFF# */
1750 status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1751 obj = (union acpi_object *)buffer.pointer;
1752 if (!ACPI_SUCCESS(status))
1754 if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1755 netif_warn(tp, probe, tp->netdev,
1756 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1757 obj->type, obj->string.length);
1761 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1762 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1763 netif_warn(tp, probe, tp->netdev,
1764 "Invalid header when reading pass-thru MAC addr\n");
1767 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1768 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1769 netif_warn(tp, probe, tp->netdev,
1770 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1775 memcpy(sa->sa_data, buf, 6);
1776 netif_info(tp, probe, tp->netdev,
1777 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1784 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1786 struct net_device *dev = tp->netdev;
1789 sa->sa_family = dev->type;
1791 ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1793 if (tp->version == RTL_VER_01) {
1794 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1796 /* if device doesn't support MAC pass through this will
1797 * be expected to be non-zero
1799 ret = vendor_mac_passthru_addr_read(tp, sa);
1801 ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1807 netif_err(tp, probe, dev, "Get ether addr fail\n");
1808 } else if (!is_valid_ether_addr(sa->sa_data)) {
1809 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1811 eth_hw_addr_random(dev);
1812 ether_addr_copy(sa->sa_data, dev->dev_addr);
1813 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1821 static int set_ethernet_addr(struct r8152 *tp, bool in_resume)
1823 struct net_device *dev = tp->netdev;
1827 ret = determine_ethernet_addr(tp, &sa);
1831 if (tp->version == RTL_VER_01)
1832 eth_hw_addr_set(dev, sa.sa_data);
1834 ret = __rtl8152_set_mac_address(dev, &sa, in_resume);
1839 static void read_bulk_callback(struct urb *urb)
1841 struct net_device *netdev;
1842 int status = urb->status;
1845 unsigned long flags;
1855 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1858 if (!test_bit(WORK_ENABLE, &tp->flags))
1861 netdev = tp->netdev;
1863 /* When link down, the driver would cancel all bulks. */
1864 /* This avoid the re-submitting bulk */
1865 if (!netif_carrier_ok(netdev))
1868 usb_mark_last_busy(tp->udev);
1872 if (urb->actual_length < ETH_ZLEN)
1875 spin_lock_irqsave(&tp->rx_lock, flags);
1876 list_add_tail(&agg->list, &tp->rx_done);
1877 spin_unlock_irqrestore(&tp->rx_lock, flags);
1878 napi_schedule(&tp->napi);
1882 netif_device_detach(tp->netdev);
1885 urb->actual_length = 0;
1886 spin_lock_irqsave(&tp->rx_lock, flags);
1887 list_add_tail(&agg->list, &tp->rx_done);
1888 spin_unlock_irqrestore(&tp->rx_lock, flags);
1889 set_bit(RX_EPROTO, &tp->flags);
1890 schedule_delayed_work(&tp->schedule, 1);
1893 return; /* the urb is in unlink state */
1895 if (net_ratelimit())
1896 netdev_warn(netdev, "maybe reset is needed?\n");
1899 if (net_ratelimit())
1900 netdev_warn(netdev, "Rx status %d\n", status);
1904 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1907 static void write_bulk_callback(struct urb *urb)
1909 struct net_device_stats *stats;
1910 struct net_device *netdev;
1913 unsigned long flags;
1914 int status = urb->status;
1924 netdev = tp->netdev;
1925 stats = &netdev->stats;
1927 if (net_ratelimit())
1928 netdev_warn(netdev, "Tx status %d\n", status);
1929 stats->tx_errors += agg->skb_num;
1931 stats->tx_packets += agg->skb_num;
1932 stats->tx_bytes += agg->skb_len;
1935 spin_lock_irqsave(&tp->tx_lock, flags);
1936 list_add_tail(&agg->list, &tp->tx_free);
1937 spin_unlock_irqrestore(&tp->tx_lock, flags);
1939 usb_autopm_put_interface_async(tp->intf);
1941 if (!netif_carrier_ok(netdev))
1944 if (!test_bit(WORK_ENABLE, &tp->flags))
1947 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1950 if (!skb_queue_empty(&tp->tx_queue))
1951 tasklet_schedule(&tp->tx_tl);
1954 static void intr_callback(struct urb *urb)
1958 int status = urb->status;
1965 if (!test_bit(WORK_ENABLE, &tp->flags))
1968 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1972 case 0: /* success */
1974 case -ECONNRESET: /* unlink */
1976 netif_device_detach(tp->netdev);
1980 netif_info(tp, intr, tp->netdev,
1981 "Stop submitting intr, status %d\n", status);
1984 if (net_ratelimit())
1985 netif_info(tp, intr, tp->netdev,
1986 "intr status -EOVERFLOW\n");
1988 /* -EPIPE: should clear the halt */
1990 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1994 d = urb->transfer_buffer;
1995 if (INTR_LINK & __le16_to_cpu(d[0])) {
1996 if (!netif_carrier_ok(tp->netdev)) {
1997 set_bit(RTL8152_LINK_CHG, &tp->flags);
1998 schedule_delayed_work(&tp->schedule, 0);
2001 if (netif_carrier_ok(tp->netdev)) {
2002 netif_stop_queue(tp->netdev);
2003 set_bit(RTL8152_LINK_CHG, &tp->flags);
2004 schedule_delayed_work(&tp->schedule, 0);
2009 res = usb_submit_urb(urb, GFP_ATOMIC);
2010 if (res == -ENODEV) {
2012 netif_device_detach(tp->netdev);
2014 netif_err(tp, intr, tp->netdev,
2015 "can't resubmit intr, status %d\n", res);
2019 static inline void *rx_agg_align(void *data)
2021 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
2024 static inline void *tx_agg_align(void *data)
2026 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
2029 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
2031 list_del(&agg->info_list);
2033 usb_free_urb(agg->urb);
2034 put_page(agg->page);
2037 atomic_dec(&tp->rx_count);
2040 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
2042 struct net_device *netdev = tp->netdev;
2043 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
2044 unsigned int order = get_order(tp->rx_buf_sz);
2045 struct rx_agg *rx_agg;
2046 unsigned long flags;
2048 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
2052 rx_agg->page = alloc_pages(mflags | __GFP_COMP | __GFP_NOWARN, order);
2056 rx_agg->buffer = page_address(rx_agg->page);
2058 rx_agg->urb = usb_alloc_urb(0, mflags);
2062 rx_agg->context = tp;
2064 INIT_LIST_HEAD(&rx_agg->list);
2065 INIT_LIST_HEAD(&rx_agg->info_list);
2066 spin_lock_irqsave(&tp->rx_lock, flags);
2067 list_add_tail(&rx_agg->info_list, &tp->rx_info);
2068 spin_unlock_irqrestore(&tp->rx_lock, flags);
2070 atomic_inc(&tp->rx_count);
2075 __free_pages(rx_agg->page, order);
2081 static void free_all_mem(struct r8152 *tp)
2083 struct rx_agg *agg, *agg_next;
2084 unsigned long flags;
2087 spin_lock_irqsave(&tp->rx_lock, flags);
2089 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
2090 free_rx_agg(tp, agg);
2092 spin_unlock_irqrestore(&tp->rx_lock, flags);
2094 WARN_ON(atomic_read(&tp->rx_count));
2096 for (i = 0; i < RTL8152_MAX_TX; i++) {
2097 usb_free_urb(tp->tx_info[i].urb);
2098 tp->tx_info[i].urb = NULL;
2100 kfree(tp->tx_info[i].buffer);
2101 tp->tx_info[i].buffer = NULL;
2102 tp->tx_info[i].head = NULL;
2105 usb_free_urb(tp->intr_urb);
2106 tp->intr_urb = NULL;
2108 kfree(tp->intr_buff);
2109 tp->intr_buff = NULL;
2112 static int alloc_all_mem(struct r8152 *tp)
2114 struct net_device *netdev = tp->netdev;
2115 struct usb_interface *intf = tp->intf;
2116 struct usb_host_interface *alt = intf->cur_altsetting;
2117 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
2120 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
2122 spin_lock_init(&tp->rx_lock);
2123 spin_lock_init(&tp->tx_lock);
2124 INIT_LIST_HEAD(&tp->rx_info);
2125 INIT_LIST_HEAD(&tp->tx_free);
2126 INIT_LIST_HEAD(&tp->rx_done);
2127 skb_queue_head_init(&tp->tx_queue);
2128 skb_queue_head_init(&tp->rx_queue);
2129 atomic_set(&tp->rx_count, 0);
2131 for (i = 0; i < RTL8152_MAX_RX; i++) {
2132 if (!alloc_rx_agg(tp, GFP_KERNEL))
2136 for (i = 0; i < RTL8152_MAX_TX; i++) {
2140 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
2144 if (buf != tx_agg_align(buf)) {
2146 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
2152 urb = usb_alloc_urb(0, GFP_KERNEL);
2158 INIT_LIST_HEAD(&tp->tx_info[i].list);
2159 tp->tx_info[i].context = tp;
2160 tp->tx_info[i].urb = urb;
2161 tp->tx_info[i].buffer = buf;
2162 tp->tx_info[i].head = tx_agg_align(buf);
2164 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
2167 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
2171 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
2175 tp->intr_interval = (int)ep_intr->desc.bInterval;
2176 usb_fill_int_urb(tp->intr_urb, tp->udev, tp->pipe_intr,
2177 tp->intr_buff, INTBUFSIZE, intr_callback,
2178 tp, tp->intr_interval);
2187 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
2189 struct tx_agg *agg = NULL;
2190 unsigned long flags;
2192 if (list_empty(&tp->tx_free))
2195 spin_lock_irqsave(&tp->tx_lock, flags);
2196 if (!list_empty(&tp->tx_free)) {
2197 struct list_head *cursor;
2199 cursor = tp->tx_free.next;
2200 list_del_init(cursor);
2201 agg = list_entry(cursor, struct tx_agg, list);
2203 spin_unlock_irqrestore(&tp->tx_lock, flags);
2208 /* r8152_csum_workaround()
2209 * The hw limits the value of the transport offset. When the offset is out of
2210 * range, calculate the checksum by sw.
2212 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
2213 struct sk_buff_head *list)
2215 if (skb_shinfo(skb)->gso_size) {
2216 netdev_features_t features = tp->netdev->features;
2217 struct sk_buff *segs, *seg, *next;
2218 struct sk_buff_head seg_list;
2220 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
2221 segs = skb_gso_segment(skb, features);
2222 if (IS_ERR(segs) || !segs)
2225 __skb_queue_head_init(&seg_list);
2227 skb_list_walk_safe(segs, seg, next) {
2228 skb_mark_not_on_list(seg);
2229 __skb_queue_tail(&seg_list, seg);
2232 skb_queue_splice(&seg_list, list);
2234 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2235 if (skb_checksum_help(skb) < 0)
2238 __skb_queue_head(list, skb);
2240 struct net_device_stats *stats;
2243 stats = &tp->netdev->stats;
2244 stats->tx_dropped++;
2249 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
2251 if (skb_vlan_tag_present(skb)) {
2254 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
2255 desc->opts2 |= cpu_to_le32(opts2);
2259 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
2261 u32 opts2 = le32_to_cpu(desc->opts2);
2263 if (opts2 & RX_VLAN_TAG)
2264 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2265 swab16(opts2 & 0xffff));
2268 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
2269 struct sk_buff *skb, u32 len)
2271 u32 mss = skb_shinfo(skb)->gso_size;
2272 u32 opts1, opts2 = 0;
2273 int ret = TX_CSUM_SUCCESS;
2275 WARN_ON_ONCE(len > TX_LEN_MAX);
2277 opts1 = len | TX_FS | TX_LS;
2280 u32 transport_offset = (u32)skb_transport_offset(skb);
2282 if (transport_offset > GTTCPHO_MAX) {
2283 netif_warn(tp, tx_err, tp->netdev,
2284 "Invalid transport offset 0x%x for TSO\n",
2290 switch (vlan_get_protocol(skb)) {
2291 case htons(ETH_P_IP):
2295 case htons(ETH_P_IPV6):
2296 if (skb_cow_head(skb, 0)) {
2300 tcp_v6_gso_csum_prep(skb);
2309 opts1 |= transport_offset << GTTCPHO_SHIFT;
2310 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2311 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2312 u32 transport_offset = (u32)skb_transport_offset(skb);
2315 if (transport_offset > TCPHO_MAX) {
2316 netif_warn(tp, tx_err, tp->netdev,
2317 "Invalid transport offset 0x%x\n",
2323 switch (vlan_get_protocol(skb)) {
2324 case htons(ETH_P_IP):
2326 ip_protocol = ip_hdr(skb)->protocol;
2329 case htons(ETH_P_IPV6):
2331 ip_protocol = ipv6_hdr(skb)->nexthdr;
2335 ip_protocol = IPPROTO_RAW;
2339 if (ip_protocol == IPPROTO_TCP)
2341 else if (ip_protocol == IPPROTO_UDP)
2346 opts2 |= transport_offset << TCPHO_SHIFT;
2349 desc->opts2 = cpu_to_le32(opts2);
2350 desc->opts1 = cpu_to_le32(opts1);
2356 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2358 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2362 __skb_queue_head_init(&skb_head);
2363 spin_lock(&tx_queue->lock);
2364 skb_queue_splice_init(tx_queue, &skb_head);
2365 spin_unlock(&tx_queue->lock);
2367 tx_data = agg->head;
2370 remain = agg_buf_sz;
2372 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2373 struct tx_desc *tx_desc;
2374 struct sk_buff *skb;
2377 skb = __skb_dequeue(&skb_head);
2381 len = skb->len + sizeof(*tx_desc);
2384 __skb_queue_head(&skb_head, skb);
2388 tx_data = tx_agg_align(tx_data);
2389 tx_desc = (struct tx_desc *)tx_data;
2391 if (r8152_tx_csum(tp, tx_desc, skb, skb->len)) {
2392 r8152_csum_workaround(tp, skb, &skb_head);
2396 rtl_tx_vlan_tag(tx_desc, skb);
2398 tx_data += sizeof(*tx_desc);
2401 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2402 struct net_device_stats *stats = &tp->netdev->stats;
2404 stats->tx_dropped++;
2405 dev_kfree_skb_any(skb);
2406 tx_data -= sizeof(*tx_desc);
2411 agg->skb_len += len;
2412 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2414 dev_kfree_skb_any(skb);
2416 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2418 if (tp->dell_tb_rx_agg_bug)
2422 if (!skb_queue_empty(&skb_head)) {
2423 spin_lock(&tx_queue->lock);
2424 skb_queue_splice(&skb_head, tx_queue);
2425 spin_unlock(&tx_queue->lock);
2428 netif_tx_lock(tp->netdev);
2430 if (netif_queue_stopped(tp->netdev) &&
2431 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2432 netif_wake_queue(tp->netdev);
2434 netif_tx_unlock(tp->netdev);
2436 ret = usb_autopm_get_interface_async(tp->intf);
2440 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_out,
2441 agg->head, (int)(tx_data - (u8 *)agg->head),
2442 (usb_complete_t)write_bulk_callback, agg);
2444 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2446 usb_autopm_put_interface_async(tp->intf);
2452 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2454 u8 checksum = CHECKSUM_NONE;
2457 if (!(tp->netdev->features & NETIF_F_RXCSUM))
2460 opts2 = le32_to_cpu(rx_desc->opts2);
2461 opts3 = le32_to_cpu(rx_desc->opts3);
2463 if (opts2 & RD_IPV4_CS) {
2465 checksum = CHECKSUM_NONE;
2466 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2467 checksum = CHECKSUM_UNNECESSARY;
2468 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2469 checksum = CHECKSUM_UNNECESSARY;
2470 } else if (opts2 & RD_IPV6_CS) {
2471 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2472 checksum = CHECKSUM_UNNECESSARY;
2473 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2474 checksum = CHECKSUM_UNNECESSARY;
2481 static inline bool rx_count_exceed(struct r8152 *tp)
2483 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2486 static inline int agg_offset(struct rx_agg *agg, void *addr)
2488 return (int)(addr - agg->buffer);
2491 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2493 struct rx_agg *agg, *agg_next, *agg_free = NULL;
2494 unsigned long flags;
2496 spin_lock_irqsave(&tp->rx_lock, flags);
2498 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2499 if (page_count(agg->page) == 1) {
2501 list_del_init(&agg->list);
2505 if (rx_count_exceed(tp)) {
2506 list_del_init(&agg->list);
2507 free_rx_agg(tp, agg);
2513 spin_unlock_irqrestore(&tp->rx_lock, flags);
2515 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2516 agg_free = alloc_rx_agg(tp, mflags);
2521 static int rx_bottom(struct r8152 *tp, int budget)
2523 unsigned long flags;
2524 struct list_head *cursor, *next, rx_queue;
2525 int ret = 0, work_done = 0;
2526 struct napi_struct *napi = &tp->napi;
2528 if (!skb_queue_empty(&tp->rx_queue)) {
2529 while (work_done < budget) {
2530 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2531 struct net_device *netdev = tp->netdev;
2532 struct net_device_stats *stats = &netdev->stats;
2533 unsigned int pkt_len;
2539 napi_gro_receive(napi, skb);
2541 stats->rx_packets++;
2542 stats->rx_bytes += pkt_len;
2546 if (list_empty(&tp->rx_done) || work_done >= budget)
2549 clear_bit(RX_EPROTO, &tp->flags);
2550 INIT_LIST_HEAD(&rx_queue);
2551 spin_lock_irqsave(&tp->rx_lock, flags);
2552 list_splice_init(&tp->rx_done, &rx_queue);
2553 spin_unlock_irqrestore(&tp->rx_lock, flags);
2555 list_for_each_safe(cursor, next, &rx_queue) {
2556 struct rx_desc *rx_desc;
2557 struct rx_agg *agg, *agg_free;
2562 /* A bulk transfer of USB may contain may packets, so the
2563 * total packets may more than the budget. Deal with all
2564 * packets in current bulk transfer, and stop to handle the
2565 * next bulk transfer until next schedule, if budget is
2568 if (work_done >= budget)
2571 list_del_init(cursor);
2573 agg = list_entry(cursor, struct rx_agg, list);
2575 if (urb->status != 0 || urb->actual_length < ETH_ZLEN)
2578 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2580 rx_desc = agg->buffer;
2581 rx_data = agg->buffer;
2582 len_used += sizeof(struct rx_desc);
2584 while (urb->actual_length > len_used) {
2585 struct net_device *netdev = tp->netdev;
2586 struct net_device_stats *stats = &netdev->stats;
2587 unsigned int pkt_len, rx_frag_head_sz;
2588 struct sk_buff *skb;
2590 WARN_ON_ONCE(skb_queue_len(&tp->rx_queue) >= 1000);
2592 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2593 if (pkt_len < ETH_ZLEN)
2596 len_used += pkt_len;
2597 if (urb->actual_length < len_used)
2600 pkt_len -= ETH_FCS_LEN;
2601 rx_data += sizeof(struct rx_desc);
2603 if (!agg_free || tp->rx_copybreak > pkt_len)
2604 rx_frag_head_sz = pkt_len;
2606 rx_frag_head_sz = tp->rx_copybreak;
2608 skb = napi_alloc_skb(napi, rx_frag_head_sz);
2610 stats->rx_dropped++;
2614 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2615 memcpy(skb->data, rx_data, rx_frag_head_sz);
2616 skb_put(skb, rx_frag_head_sz);
2617 pkt_len -= rx_frag_head_sz;
2618 rx_data += rx_frag_head_sz;
2620 skb_add_rx_frag(skb, 0, agg->page,
2621 agg_offset(agg, rx_data),
2623 SKB_DATA_ALIGN(pkt_len));
2624 get_page(agg->page);
2627 skb->protocol = eth_type_trans(skb, netdev);
2628 rtl_rx_vlan_tag(rx_desc, skb);
2629 if (work_done < budget) {
2631 stats->rx_packets++;
2632 stats->rx_bytes += skb->len;
2633 napi_gro_receive(napi, skb);
2635 __skb_queue_tail(&tp->rx_queue, skb);
2639 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2640 rx_desc = (struct rx_desc *)rx_data;
2641 len_used = agg_offset(agg, rx_data);
2642 len_used += sizeof(struct rx_desc);
2645 WARN_ON(!agg_free && page_count(agg->page) > 1);
2648 spin_lock_irqsave(&tp->rx_lock, flags);
2649 if (page_count(agg->page) == 1) {
2650 list_add(&agg_free->list, &tp->rx_used);
2652 list_add_tail(&agg->list, &tp->rx_used);
2656 spin_unlock_irqrestore(&tp->rx_lock, flags);
2661 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2663 urb->actual_length = 0;
2664 list_add_tail(&agg->list, next);
2668 /* Splice the remained list back to rx_done for next schedule */
2669 if (!list_empty(&rx_queue)) {
2670 spin_lock_irqsave(&tp->rx_lock, flags);
2671 list_splice(&rx_queue, &tp->rx_done);
2672 spin_unlock_irqrestore(&tp->rx_lock, flags);
2679 static void tx_bottom(struct r8152 *tp)
2684 struct net_device *netdev = tp->netdev;
2687 if (skb_queue_empty(&tp->tx_queue))
2690 agg = r8152_get_tx_agg(tp);
2694 res = r8152_tx_agg_fill(tp, agg);
2698 if (res == -ENODEV) {
2700 netif_device_detach(netdev);
2702 struct net_device_stats *stats = &netdev->stats;
2703 unsigned long flags;
2705 netif_warn(tp, tx_err, netdev,
2706 "failed tx_urb %d\n", res);
2707 stats->tx_dropped += agg->skb_num;
2709 spin_lock_irqsave(&tp->tx_lock, flags);
2710 list_add_tail(&agg->list, &tp->tx_free);
2711 spin_unlock_irqrestore(&tp->tx_lock, flags);
2716 static void bottom_half(struct tasklet_struct *t)
2718 struct r8152 *tp = from_tasklet(tp, t, tx_tl);
2720 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
2723 if (!test_bit(WORK_ENABLE, &tp->flags))
2726 /* When link down, the driver would cancel all bulks. */
2727 /* This avoid the re-submitting bulk */
2728 if (!netif_carrier_ok(tp->netdev))
2731 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2736 static int r8152_poll(struct napi_struct *napi, int budget)
2738 struct r8152 *tp = container_of(napi, struct r8152, napi);
2744 work_done = rx_bottom(tp, budget);
2746 if (work_done < budget) {
2747 if (!napi_complete_done(napi, work_done))
2749 if (!list_empty(&tp->rx_done))
2750 napi_schedule(napi);
2758 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2762 /* The rx would be stopped, so skip submitting */
2763 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) ||
2764 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2767 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_in,
2768 agg->buffer, tp->rx_buf_sz,
2769 (usb_complete_t)read_bulk_callback, agg);
2771 ret = usb_submit_urb(agg->urb, mem_flags);
2772 if (ret == -ENODEV) {
2774 netif_device_detach(tp->netdev);
2776 struct urb *urb = agg->urb;
2777 unsigned long flags;
2779 urb->actual_length = 0;
2780 spin_lock_irqsave(&tp->rx_lock, flags);
2781 list_add_tail(&agg->list, &tp->rx_done);
2782 spin_unlock_irqrestore(&tp->rx_lock, flags);
2784 netif_err(tp, rx_err, tp->netdev,
2785 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2787 napi_schedule(&tp->napi);
2793 static void rtl_drop_queued_tx(struct r8152 *tp)
2795 struct net_device_stats *stats = &tp->netdev->stats;
2796 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2797 struct sk_buff *skb;
2799 if (skb_queue_empty(tx_queue))
2802 __skb_queue_head_init(&skb_head);
2803 spin_lock_bh(&tx_queue->lock);
2804 skb_queue_splice_init(tx_queue, &skb_head);
2805 spin_unlock_bh(&tx_queue->lock);
2807 while ((skb = __skb_dequeue(&skb_head))) {
2809 stats->tx_dropped++;
2813 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2815 struct r8152 *tp = netdev_priv(netdev);
2817 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2819 usb_queue_reset_device(tp->intf);
2822 static void rtl8152_set_rx_mode(struct net_device *netdev)
2824 struct r8152 *tp = netdev_priv(netdev);
2826 if (netif_carrier_ok(netdev)) {
2827 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2828 schedule_delayed_work(&tp->schedule, 0);
2832 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2834 struct r8152 *tp = netdev_priv(netdev);
2835 u32 mc_filter[2]; /* Multicast hash filter */
2839 netif_stop_queue(netdev);
2840 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2841 ocp_data &= ~RCR_ACPT_ALL;
2842 ocp_data |= RCR_AB | RCR_APM;
2844 if (netdev->flags & IFF_PROMISC) {
2845 /* Unconditionally log net taps. */
2846 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2847 ocp_data |= RCR_AM | RCR_AAP;
2848 mc_filter[1] = 0xffffffff;
2849 mc_filter[0] = 0xffffffff;
2850 } else if ((netdev->flags & IFF_MULTICAST &&
2851 netdev_mc_count(netdev) > multicast_filter_limit) ||
2852 (netdev->flags & IFF_ALLMULTI)) {
2853 /* Too many to filter perfectly -- accept all multicasts. */
2855 mc_filter[1] = 0xffffffff;
2856 mc_filter[0] = 0xffffffff;
2861 if (netdev->flags & IFF_MULTICAST) {
2862 struct netdev_hw_addr *ha;
2864 netdev_for_each_mc_addr(ha, netdev) {
2865 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2867 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2873 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2874 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2876 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2877 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2878 netif_wake_queue(netdev);
2881 static netdev_features_t
2882 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2883 netdev_features_t features)
2885 u32 mss = skb_shinfo(skb)->gso_size;
2886 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2888 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) &&
2889 skb_transport_offset(skb) > max_offset)
2890 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2891 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2892 features &= ~NETIF_F_GSO_MASK;
2897 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2898 struct net_device *netdev)
2900 struct r8152 *tp = netdev_priv(netdev);
2902 skb_tx_timestamp(skb);
2904 skb_queue_tail(&tp->tx_queue, skb);
2906 if (!list_empty(&tp->tx_free)) {
2907 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2908 set_bit(SCHEDULE_TASKLET, &tp->flags);
2909 schedule_delayed_work(&tp->schedule, 0);
2911 usb_mark_last_busy(tp->udev);
2912 tasklet_schedule(&tp->tx_tl);
2914 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2915 netif_stop_queue(netdev);
2918 return NETDEV_TX_OK;
2921 static void r8152b_reset_packet_filter(struct r8152 *tp)
2925 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2926 ocp_data &= ~FMC_FCR_MCU_EN;
2927 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2928 ocp_data |= FMC_FCR_MCU_EN;
2929 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2932 static void rtl8152_nic_reset(struct r8152 *tp)
2937 switch (tp->version) {
2941 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2943 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2945 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2946 ocp_data &= ~BMU_RESET_EP_IN;
2947 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2949 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2950 ocp_data |= CDC_ECM_EN;
2951 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2953 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2955 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2957 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2958 ocp_data |= BMU_RESET_EP_IN;
2959 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2961 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2962 ocp_data &= ~CDC_ECM_EN;
2963 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2967 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2969 for (i = 0; i < 1000; i++) {
2970 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2972 usleep_range(100, 400);
2978 static void set_tx_qlen(struct r8152 *tp)
2980 tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
2983 static inline u16 rtl8152_get_speed(struct r8152 *tp)
2985 return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2988 static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
2992 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2994 ocp_data |= EEEP_CR_EEEP_TX;
2996 ocp_data &= ~EEEP_CR_EEEP_TX;
2997 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
3000 static void rtl_set_eee_plus(struct r8152 *tp)
3002 if (rtl8152_get_speed(tp) & _10bps)
3003 rtl_eee_plus_en(tp, true);
3005 rtl_eee_plus_en(tp, false);
3008 static void rxdy_gated_en(struct r8152 *tp, bool enable)
3012 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
3014 ocp_data |= RXDY_GATED_EN;
3016 ocp_data &= ~RXDY_GATED_EN;
3017 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
3020 static int rtl_start_rx(struct r8152 *tp)
3022 struct rx_agg *agg, *agg_next;
3023 struct list_head tmp_list;
3024 unsigned long flags;
3027 INIT_LIST_HEAD(&tmp_list);
3029 spin_lock_irqsave(&tp->rx_lock, flags);
3031 INIT_LIST_HEAD(&tp->rx_done);
3032 INIT_LIST_HEAD(&tp->rx_used);
3034 list_splice_init(&tp->rx_info, &tmp_list);
3036 spin_unlock_irqrestore(&tp->rx_lock, flags);
3038 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
3039 INIT_LIST_HEAD(&agg->list);
3041 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
3042 if (++i > RTL8152_MAX_RX) {
3043 spin_lock_irqsave(&tp->rx_lock, flags);
3044 list_add_tail(&agg->list, &tp->rx_used);
3045 spin_unlock_irqrestore(&tp->rx_lock, flags);
3046 } else if (unlikely(ret < 0)) {
3047 spin_lock_irqsave(&tp->rx_lock, flags);
3048 list_add_tail(&agg->list, &tp->rx_done);
3049 spin_unlock_irqrestore(&tp->rx_lock, flags);
3051 ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
3055 spin_lock_irqsave(&tp->rx_lock, flags);
3056 WARN_ON(!list_empty(&tp->rx_info));
3057 list_splice(&tmp_list, &tp->rx_info);
3058 spin_unlock_irqrestore(&tp->rx_lock, flags);
3063 static int rtl_stop_rx(struct r8152 *tp)
3065 struct rx_agg *agg, *agg_next;
3066 struct list_head tmp_list;
3067 unsigned long flags;
3069 INIT_LIST_HEAD(&tmp_list);
3071 /* The usb_kill_urb() couldn't be used in atomic.
3072 * Therefore, move the list of rx_info to a tmp one.
3073 * Then, list_for_each_entry_safe could be used without
3077 spin_lock_irqsave(&tp->rx_lock, flags);
3078 list_splice_init(&tp->rx_info, &tmp_list);
3079 spin_unlock_irqrestore(&tp->rx_lock, flags);
3081 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
3082 /* At least RTL8152_MAX_RX rx_agg have the page_count being
3083 * equal to 1, so the other ones could be freed safely.
3085 if (page_count(agg->page) > 1)
3086 free_rx_agg(tp, agg);
3088 usb_kill_urb(agg->urb);
3091 /* Move back the list of temp to the rx_info */
3092 spin_lock_irqsave(&tp->rx_lock, flags);
3093 WARN_ON(!list_empty(&tp->rx_info));
3094 list_splice(&tmp_list, &tp->rx_info);
3095 spin_unlock_irqrestore(&tp->rx_lock, flags);
3097 while (!skb_queue_empty(&tp->rx_queue))
3098 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
3103 static void rtl_set_ifg(struct r8152 *tp, u16 speed)
3107 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3108 ocp_data &= ~IFG_MASK;
3109 if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
3110 ocp_data |= IFG_144NS;
3111 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
3113 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3114 ocp_data &= ~TX10MIDLE_EN;
3115 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
3117 ocp_data |= IFG_96NS;
3118 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
3120 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3121 ocp_data |= TX10MIDLE_EN;
3122 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
3126 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
3128 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
3129 OWN_UPDATE | OWN_CLEAR);
3132 static int rtl_enable(struct r8152 *tp)
3136 r8152b_reset_packet_filter(tp);
3138 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
3139 ocp_data |= CR_RE | CR_TE;
3140 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
3142 switch (tp->version) {
3152 r8153b_rx_agg_chg_indicate(tp);
3156 rxdy_gated_en(tp, false);
3161 static int rtl8152_enable(struct r8152 *tp)
3163 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3167 rtl_set_eee_plus(tp);
3169 return rtl_enable(tp);
3172 static void r8153_set_rx_early_timeout(struct r8152 *tp)
3174 u32 ocp_data = tp->coalesce / 8;
3176 switch (tp->version) {
3181 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3188 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
3189 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
3191 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3193 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3202 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3204 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3213 static void r8153_set_rx_early_size(struct r8152 *tp)
3215 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
3217 switch (tp->version) {
3222 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3228 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3237 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3246 static int rtl8153_enable(struct r8152 *tp)
3250 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3254 rtl_set_eee_plus(tp);
3255 r8153_set_rx_early_timeout(tp);
3256 r8153_set_rx_early_size(tp);
3258 rtl_set_ifg(tp, rtl8152_get_speed(tp));
3260 switch (tp->version) {
3263 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
3264 ocp_data &= ~FC_PATCH_TASK;
3265 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3266 usleep_range(1000, 2000);
3267 ocp_data |= FC_PATCH_TASK;
3268 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3274 return rtl_enable(tp);
3277 static void rtl_disable(struct r8152 *tp)
3282 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
3283 rtl_drop_queued_tx(tp);
3287 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3288 ocp_data &= ~RCR_ACPT_ALL;
3289 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3291 rtl_drop_queued_tx(tp);
3293 for (i = 0; i < RTL8152_MAX_TX; i++)
3294 usb_kill_urb(tp->tx_info[i].urb);
3296 rxdy_gated_en(tp, true);
3298 for (i = 0; i < 1000; i++) {
3299 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3300 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
3302 usleep_range(1000, 2000);
3305 for (i = 0; i < 1000; i++) {
3306 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
3308 usleep_range(1000, 2000);
3313 rtl8152_nic_reset(tp);
3316 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
3320 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
3322 ocp_data |= POWER_CUT;
3324 ocp_data &= ~POWER_CUT;
3325 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
3327 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
3328 ocp_data &= ~RESUME_INDICATE;
3329 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
3332 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
3336 switch (tp->version) {
3347 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
3349 ocp_data |= CPCR_RX_VLAN;
3351 ocp_data &= ~CPCR_RX_VLAN;
3352 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
3362 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
3364 ocp_data |= OUTER_VLAN | INNER_VLAN;
3366 ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
3367 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);
3372 static int rtl8152_set_features(struct net_device *dev,
3373 netdev_features_t features)
3375 netdev_features_t changed = features ^ dev->features;
3376 struct r8152 *tp = netdev_priv(dev);
3379 ret = usb_autopm_get_interface(tp->intf);
3383 mutex_lock(&tp->control);
3385 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
3386 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3387 rtl_rx_vlan_en(tp, true);
3389 rtl_rx_vlan_en(tp, false);
3392 mutex_unlock(&tp->control);
3394 usb_autopm_put_interface(tp->intf);
3400 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
3402 static u32 __rtl_get_wol(struct r8152 *tp)
3407 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3408 if (ocp_data & LINK_ON_WAKE_EN)
3409 wolopts |= WAKE_PHY;
3411 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3412 if (ocp_data & UWF_EN)
3413 wolopts |= WAKE_UCAST;
3414 if (ocp_data & BWF_EN)
3415 wolopts |= WAKE_BCAST;
3416 if (ocp_data & MWF_EN)
3417 wolopts |= WAKE_MCAST;
3419 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3420 if (ocp_data & MAGIC_EN)
3421 wolopts |= WAKE_MAGIC;
3426 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3430 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3432 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3433 ocp_data &= ~LINK_ON_WAKE_EN;
3434 if (wolopts & WAKE_PHY)
3435 ocp_data |= LINK_ON_WAKE_EN;
3436 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3438 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3439 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3440 if (wolopts & WAKE_UCAST)
3442 if (wolopts & WAKE_BCAST)
3444 if (wolopts & WAKE_MCAST)
3446 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3448 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3450 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3451 ocp_data &= ~MAGIC_EN;
3452 if (wolopts & WAKE_MAGIC)
3453 ocp_data |= MAGIC_EN;
3454 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3456 if (wolopts & WAKE_ANY)
3457 device_set_wakeup_enable(&tp->udev->dev, true);
3459 device_set_wakeup_enable(&tp->udev->dev, false);
3462 static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
3464 u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3466 /* MAC clock speed down */
3468 ocp_data |= MAC_CLK_SPDWN_EN;
3470 ocp_data &= ~MAC_CLK_SPDWN_EN;
3472 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3475 static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
3479 /* MAC clock speed down */
3481 /* aldps_spdwn_ratio, tp10_spdwn_ratio */
3482 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3485 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3486 ocp_data &= ~EEE_SPDWN_RATIO_MASK;
3487 ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
3488 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3490 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3491 ocp_data &= ~MAC_CLK_SPDWN_EN;
3492 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3496 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3501 memset(u1u2, 0xff, sizeof(u1u2));
3503 memset(u1u2, 0x00, sizeof(u1u2));
3505 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3508 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3512 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3514 ocp_data |= LPM_U1U2_EN;
3516 ocp_data &= ~LPM_U1U2_EN;
3518 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3521 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3525 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3527 ocp_data |= U2P3_ENABLE;
3529 ocp_data &= ~U2P3_ENABLE;
3530 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3533 static void r8153b_ups_flags(struct r8152 *tp)
3537 if (tp->ups_info.green)
3538 ups_flags |= UPS_FLAGS_EN_GREEN;
3540 if (tp->ups_info.aldps)
3541 ups_flags |= UPS_FLAGS_EN_ALDPS;
3543 if (tp->ups_info.eee)
3544 ups_flags |= UPS_FLAGS_EN_EEE;
3546 if (tp->ups_info.flow_control)
3547 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3549 if (tp->ups_info.eee_ckdiv)
3550 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3552 if (tp->ups_info.eee_cmod_lv)
3553 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3555 if (tp->ups_info.r_tune)
3556 ups_flags |= UPS_FLAGS_R_TUNE;
3558 if (tp->ups_info._10m_ckdiv)
3559 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3561 if (tp->ups_info.eee_plloff_100)
3562 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3564 if (tp->ups_info.eee_plloff_giga)
3565 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3567 if (tp->ups_info._250m_ckdiv)
3568 ups_flags |= UPS_FLAGS_250M_CKDIV;
3570 if (tp->ups_info.ctap_short_off)
3571 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3573 switch (tp->ups_info.speed_duplex) {
3575 ups_flags |= ups_flags_speed(1);
3578 ups_flags |= ups_flags_speed(2);
3580 case NWAY_100M_HALF:
3581 ups_flags |= ups_flags_speed(3);
3583 case NWAY_100M_FULL:
3584 ups_flags |= ups_flags_speed(4);
3586 case NWAY_1000M_FULL:
3587 ups_flags |= ups_flags_speed(5);
3589 case FORCE_10M_HALF:
3590 ups_flags |= ups_flags_speed(6);
3592 case FORCE_10M_FULL:
3593 ups_flags |= ups_flags_speed(7);
3595 case FORCE_100M_HALF:
3596 ups_flags |= ups_flags_speed(8);
3598 case FORCE_100M_FULL:
3599 ups_flags |= ups_flags_speed(9);
3605 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3608 static void r8156_ups_flags(struct r8152 *tp)
3612 if (tp->ups_info.green)
3613 ups_flags |= UPS_FLAGS_EN_GREEN;
3615 if (tp->ups_info.aldps)
3616 ups_flags |= UPS_FLAGS_EN_ALDPS;
3618 if (tp->ups_info.eee)
3619 ups_flags |= UPS_FLAGS_EN_EEE;
3621 if (tp->ups_info.flow_control)
3622 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3624 if (tp->ups_info.eee_ckdiv)
3625 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3627 if (tp->ups_info._10m_ckdiv)
3628 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3630 if (tp->ups_info.eee_plloff_100)
3631 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3633 if (tp->ups_info.eee_plloff_giga)
3634 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3636 if (tp->ups_info._250m_ckdiv)
3637 ups_flags |= UPS_FLAGS_250M_CKDIV;
3639 switch (tp->ups_info.speed_duplex) {
3640 case FORCE_10M_HALF:
3641 ups_flags |= ups_flags_speed(0);
3643 case FORCE_10M_FULL:
3644 ups_flags |= ups_flags_speed(1);
3646 case FORCE_100M_HALF:
3647 ups_flags |= ups_flags_speed(2);
3649 case FORCE_100M_FULL:
3650 ups_flags |= ups_flags_speed(3);
3653 ups_flags |= ups_flags_speed(4);
3656 ups_flags |= ups_flags_speed(5);
3658 case NWAY_100M_HALF:
3659 ups_flags |= ups_flags_speed(6);
3661 case NWAY_100M_FULL:
3662 ups_flags |= ups_flags_speed(7);
3664 case NWAY_1000M_FULL:
3665 ups_flags |= ups_flags_speed(8);
3667 case NWAY_2500M_FULL:
3668 ups_flags |= ups_flags_speed(9);
3674 switch (tp->ups_info.lite_mode) {
3676 ups_flags |= 0 << 5;
3679 ups_flags |= 2 << 5;
3683 ups_flags |= 1 << 5;
3687 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3690 static void rtl_green_en(struct r8152 *tp, bool enable)
3694 data = sram_read(tp, SRAM_GREEN_CFG);
3696 data |= GREEN_ETH_EN;
3698 data &= ~GREEN_ETH_EN;
3699 sram_write(tp, SRAM_GREEN_CFG, data);
3701 tp->ups_info.green = enable;
3704 static void r8153b_green_en(struct r8152 *tp, bool enable)
3707 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
3708 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3709 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3711 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3712 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3713 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3716 rtl_green_en(tp, true);
3719 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3724 for (i = 0; i < 500; i++) {
3725 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3726 data &= PHY_STAT_MASK;
3728 if (data == desired)
3730 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3731 data == PHY_STAT_EXT_INIT) {
3736 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3743 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3745 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3748 r8153b_ups_flags(tp);
3750 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3751 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3753 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3754 ocp_data |= UPS_FORCE_PWR_DOWN;
3755 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3757 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3758 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3760 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3761 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3762 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3764 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3767 for (i = 0; i < 500; i++) {
3768 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3770 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3776 tp->rtl_ops.hw_phy_cfg(tp);
3778 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3779 tp->duplex, tp->advertising);
3784 static void r8153c_ups_en(struct r8152 *tp, bool enable)
3786 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3789 r8153b_ups_flags(tp);
3791 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3792 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3794 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3795 ocp_data |= UPS_FORCE_PWR_DOWN;
3796 ocp_data &= ~BIT(7);
3797 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3799 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3800 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3802 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3803 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3804 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3806 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3809 for (i = 0; i < 500; i++) {
3810 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3812 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3818 tp->rtl_ops.hw_phy_cfg(tp);
3820 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3821 tp->duplex, tp->advertising);
3824 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3826 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3828 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3830 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3834 static void r8156_ups_en(struct r8152 *tp, bool enable)
3836 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3839 r8156_ups_flags(tp);
3841 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3842 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3844 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3845 ocp_data |= UPS_FORCE_PWR_DOWN;
3846 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3848 switch (tp->version) {
3851 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
3852 ocp_data &= ~OOBS_POLLING;
3853 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
3859 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3860 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3862 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3863 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3864 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3866 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3867 tp->rtl_ops.hw_phy_cfg(tp);
3869 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3870 tp->duplex, tp->advertising);
3875 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3879 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3881 ocp_data |= PWR_EN | PHASE2_EN;
3883 ocp_data &= ~(PWR_EN | PHASE2_EN);
3884 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3886 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3887 ocp_data &= ~PCUT_STATUS;
3888 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3891 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3895 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3897 ocp_data |= PWR_EN | PHASE2_EN;
3899 ocp_data &= ~PWR_EN;
3900 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3902 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3903 ocp_data &= ~PCUT_STATUS;
3904 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3907 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3911 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3913 ocp_data |= UPCOMING_RUNTIME_D3;
3915 ocp_data &= ~UPCOMING_RUNTIME_D3;
3916 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3918 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3919 ocp_data &= ~LINK_CHG_EVENT;
3920 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3922 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3923 ocp_data &= ~LINK_CHANGE_FLAG;
3924 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3927 static bool rtl_can_wakeup(struct r8152 *tp)
3929 struct usb_device *udev = tp->udev;
3931 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3934 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3939 __rtl_set_wol(tp, WAKE_ANY);
3941 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3943 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3944 ocp_data |= LINK_OFF_WAKE_EN;
3945 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3947 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3951 __rtl_set_wol(tp, tp->saved_wolopts);
3953 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3955 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3956 ocp_data &= ~LINK_OFF_WAKE_EN;
3957 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3959 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3963 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3966 r8153_u1u2en(tp, false);
3967 r8153_u2p3en(tp, false);
3968 rtl_runtime_suspend_enable(tp, true);
3970 rtl_runtime_suspend_enable(tp, false);
3972 switch (tp->version) {
3979 r8153_u2p3en(tp, true);
3983 r8153_u1u2en(tp, true);
3987 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3990 r8153_queue_wake(tp, true);
3991 r8153b_u1u2en(tp, false);
3992 r8153_u2p3en(tp, false);
3993 rtl_runtime_suspend_enable(tp, true);
3994 r8153b_ups_en(tp, true);
3996 r8153b_ups_en(tp, false);
3997 r8153_queue_wake(tp, false);
3998 rtl_runtime_suspend_enable(tp, false);
3999 if (tp->udev->speed >= USB_SPEED_SUPER)
4000 r8153b_u1u2en(tp, true);
4004 static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
4007 r8153_queue_wake(tp, true);
4008 r8153b_u1u2en(tp, false);
4009 r8153_u2p3en(tp, false);
4010 rtl_runtime_suspend_enable(tp, true);
4011 r8153c_ups_en(tp, true);
4013 r8153c_ups_en(tp, false);
4014 r8153_queue_wake(tp, false);
4015 rtl_runtime_suspend_enable(tp, false);
4016 r8153b_u1u2en(tp, true);
4020 static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
4023 r8153_queue_wake(tp, true);
4024 r8153b_u1u2en(tp, false);
4025 r8153_u2p3en(tp, false);
4026 rtl_runtime_suspend_enable(tp, true);
4028 r8153_queue_wake(tp, false);
4029 rtl_runtime_suspend_enable(tp, false);
4030 r8153_u2p3en(tp, true);
4031 if (tp->udev->speed >= USB_SPEED_SUPER)
4032 r8153b_u1u2en(tp, true);
4036 static void r8153_teredo_off(struct r8152 *tp)
4040 switch (tp->version) {
4048 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4049 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
4051 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4064 /* The bit 0 ~ 7 are relative with teredo settings. They are
4065 * W1C (write 1 to clear), so set all 1 to disable it.
4067 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
4071 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
4072 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
4073 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
4076 static void rtl_reset_bmu(struct r8152 *tp)
4080 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
4081 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
4082 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
4083 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
4084 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
4087 /* Clear the bp to stop the firmware before loading a new one */
4088 static void rtl_clear_bp(struct r8152 *tp, u16 type)
4093 switch (tp->version) {
4101 if (type == MCU_TYPE_USB) {
4102 ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
4111 ocp_write_byte(tp, type, PLA_BP_EN, 0);
4120 ocp_write_word(tp, type, USB_BP2_EN, 0);
4125 generic_ocp_write(tp, PLA_BP_0, BYTE_EN_DWORD, bp_num << 1, bp, type);
4127 /* wait 3 ms to make sure the firmware is stopped */
4128 usleep_range(3000, 6000);
4129 ocp_write_word(tp, type, PLA_BP_BA, 0);
4132 static inline void rtl_reset_ocp_base(struct r8152 *tp)
4137 static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
4142 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
4144 data |= PATCH_REQUEST;
4147 data &= ~PATCH_REQUEST;
4148 check = PATCH_READY;
4150 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
4152 for (i = 0; wait && i < 5000; i++) {
4155 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
4158 usleep_range(1000, 2000);
4159 ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
4160 if ((ocp_data & PATCH_READY) ^ check)
4164 if (request && wait &&
4165 !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
4166 dev_err(&tp->intf->dev, "PHY patch request fail\n");
4167 rtl_phy_patch_request(tp, false, false);
4174 static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
4176 if (patch_key && key_addr) {
4177 sram_write(tp, key_addr, patch_key);
4178 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
4179 } else if (key_addr) {
4182 sram_write(tp, 0x0000, 0x0000);
4184 data = ocp_reg_read(tp, OCP_PHY_LOCK);
4185 data &= ~PATCH_LOCK;
4186 ocp_reg_write(tp, OCP_PHY_LOCK, data);
4188 sram_write(tp, key_addr, 0x0000);
4195 rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
4197 if (rtl_phy_patch_request(tp, true, wait))
4200 rtl_patch_key_set(tp, key_addr, patch_key);
4205 static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
4207 rtl_patch_key_set(tp, key_addr, 0);
4209 rtl_phy_patch_request(tp, false, wait);
4214 static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)
4220 switch (tp->version) {
4241 fw_offset = __le16_to_cpu(phy->fw_offset);
4242 length = __le32_to_cpu(phy->blk_hdr.length);
4243 if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4244 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4248 length -= fw_offset;
4250 dev_err(&tp->intf->dev, "invalid block length\n");
4254 if (__le16_to_cpu(phy->fw_reg) != 0x9A00) {
4255 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4264 static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)
4268 switch (tp->version) {
4279 if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {
4280 dev_err(&tp->intf->dev, "invalid block length\n");
4284 if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {
4285 dev_err(&tp->intf->dev, "invalid phy ver addr\n");
4294 static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)
4298 switch (tp->version) {
4309 if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {
4310 dev_err(&tp->intf->dev, "invalid block length\n");
4314 if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||
4315 __le16_to_cpu(fix->setting.data) != BIT(7)) {
4316 dev_err(&tp->intf->dev, "invalid phy fixup\n");
4325 static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)
4331 switch (tp->version) {
4342 fw_offset = __le16_to_cpu(phy->fw_offset);
4343 length = __le32_to_cpu(phy->blk_hdr.length);
4344 if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4345 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4349 length -= fw_offset;
4351 dev_err(&tp->intf->dev, "invalid block length\n");
4355 if (phy->pre_num > 2) {
4356 dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num);
4360 if (phy->bp_num > 8) {
4361 dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num);
4370 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
4373 u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
4376 switch (tp->version) {
4382 patch_en_addr = 0xa01a;
4390 fw_offset = __le16_to_cpu(phy->fw_offset);
4391 if (fw_offset < sizeof(*phy)) {
4392 dev_err(&tp->intf->dev, "fw_offset too small\n");
4396 length = __le32_to_cpu(phy->blk_hdr.length);
4397 if (length < fw_offset) {
4398 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4402 length -= __le16_to_cpu(phy->fw_offset);
4403 if (!length || (length & 1)) {
4404 dev_err(&tp->intf->dev, "invalid block length\n");
4408 if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
4409 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4413 if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
4414 dev_err(&tp->intf->dev, "invalid base address register\n");
4418 if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
4419 dev_err(&tp->intf->dev,
4420 "invalid patch mode enabled register\n");
4424 if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
4425 dev_err(&tp->intf->dev,
4426 "invalid register to switch the mode\n");
4430 if (__le16_to_cpu(phy->bp_start) != bp_start) {
4431 dev_err(&tp->intf->dev,
4432 "invalid start register of break point\n");
4436 if (__le16_to_cpu(phy->bp_num) > 4) {
4437 dev_err(&tp->intf->dev, "invalid break point number\n");
4446 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
4448 u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
4453 type = __le32_to_cpu(mac->blk_hdr.type);
4454 if (type == RTL_FW_PLA) {
4455 switch (tp->version) {
4460 bp_ba_addr = PLA_BP_BA;
4462 bp_start = PLA_BP_0;
4476 bp_ba_addr = PLA_BP_BA;
4477 bp_en_addr = PLA_BP_EN;
4478 bp_start = PLA_BP_0;
4483 bp_ba_addr = PLA_BP_BA;
4484 bp_en_addr = USB_BP2_EN;
4485 bp_start = PLA_BP_0;
4491 } else if (type == RTL_FW_USB) {
4492 switch (tp->version) {
4498 bp_ba_addr = USB_BP_BA;
4499 bp_en_addr = USB_BP_EN;
4500 bp_start = USB_BP_0;
4511 bp_ba_addr = USB_BP_BA;
4512 bp_en_addr = USB_BP2_EN;
4513 bp_start = USB_BP_0;
4526 fw_offset = __le16_to_cpu(mac->fw_offset);
4527 if (fw_offset < sizeof(*mac)) {
4528 dev_err(&tp->intf->dev, "fw_offset too small\n");
4532 length = __le32_to_cpu(mac->blk_hdr.length);
4533 if (length < fw_offset) {
4534 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4538 length -= fw_offset;
4539 if (length < 4 || (length & 3)) {
4540 dev_err(&tp->intf->dev, "invalid block length\n");
4544 if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
4545 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4549 if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
4550 dev_err(&tp->intf->dev, "invalid base address register\n");
4554 if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
4555 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
4559 if (__le16_to_cpu(mac->bp_start) != bp_start) {
4560 dev_err(&tp->intf->dev,
4561 "invalid start register of break point\n");
4565 if (__le16_to_cpu(mac->bp_num) > max_bp) {
4566 dev_err(&tp->intf->dev, "invalid break point number\n");
4570 for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
4572 dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
4582 /* Verify the checksum for the firmware file. It is calculated from the version
4583 * field to the end of the file. Compare the result with the checksum field to
4584 * make sure the file is correct.
4586 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
4587 struct fw_header *fw_hdr, size_t size)
4589 unsigned char checksum[sizeof(fw_hdr->checksum)];
4590 struct crypto_shash *alg;
4591 struct shash_desc *sdesc;
4595 alg = crypto_alloc_shash("sha256", 0, 0);
4601 if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
4603 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
4604 crypto_shash_digestsize(alg));
4608 len = sizeof(*sdesc) + crypto_shash_descsize(alg);
4609 sdesc = kmalloc(len, GFP_KERNEL);
4616 len = size - sizeof(fw_hdr->checksum);
4617 rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
4622 if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
4623 dev_err(&tp->intf->dev, "checksum fail\n");
4628 crypto_free_shash(alg);
4633 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
4635 const struct firmware *fw = rtl_fw->fw;
4636 struct fw_header *fw_hdr = (struct fw_header *)fw->data;
4637 unsigned long fw_flags = 0;
4641 if (fw->size < sizeof(*fw_hdr)) {
4642 dev_err(&tp->intf->dev, "file too small\n");
4646 ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
4652 for (i = sizeof(*fw_hdr); i < fw->size;) {
4653 struct fw_block *block = (struct fw_block *)&fw->data[i];
4656 if ((i + sizeof(*block)) > fw->size)
4659 type = __le32_to_cpu(block->type);
4662 if (__le32_to_cpu(block->length) != sizeof(*block))
4666 if (test_bit(FW_FLAGS_PLA, &fw_flags)) {
4667 dev_err(&tp->intf->dev,
4668 "multiple PLA firmware encountered");
4672 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4673 dev_err(&tp->intf->dev,
4674 "check PLA firmware failed\n");
4677 __set_bit(FW_FLAGS_PLA, &fw_flags);
4680 if (test_bit(FW_FLAGS_USB, &fw_flags)) {
4681 dev_err(&tp->intf->dev,
4682 "multiple USB firmware encountered");
4686 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4687 dev_err(&tp->intf->dev,
4688 "check USB firmware failed\n");
4691 __set_bit(FW_FLAGS_USB, &fw_flags);
4693 case RTL_FW_PHY_START:
4694 if (test_bit(FW_FLAGS_START, &fw_flags) ||
4695 test_bit(FW_FLAGS_NC, &fw_flags) ||
4696 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4697 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4698 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4699 test_bit(FW_FLAGS_UC, &fw_flags) ||
4700 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4701 dev_err(&tp->intf->dev,
4702 "check PHY_START fail\n");
4706 if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {
4707 dev_err(&tp->intf->dev,
4708 "Invalid length for PHY_START\n");
4711 __set_bit(FW_FLAGS_START, &fw_flags);
4713 case RTL_FW_PHY_STOP:
4714 if (test_bit(FW_FLAGS_STOP, &fw_flags) ||
4715 !test_bit(FW_FLAGS_START, &fw_flags)) {
4716 dev_err(&tp->intf->dev,
4717 "Check PHY_STOP fail\n");
4721 if (__le32_to_cpu(block->length) != sizeof(*block)) {
4722 dev_err(&tp->intf->dev,
4723 "Invalid length for PHY_STOP\n");
4726 __set_bit(FW_FLAGS_STOP, &fw_flags);
4729 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4730 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4731 dev_err(&tp->intf->dev,
4732 "check PHY_NC fail\n");
4736 if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4737 dev_err(&tp->intf->dev,
4738 "multiple PHY NC encountered\n");
4742 if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) {
4743 dev_err(&tp->intf->dev,
4744 "check PHY NC firmware failed\n");
4747 __set_bit(FW_FLAGS_NC, &fw_flags);
4749 case RTL_FW_PHY_UNION_NC:
4750 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4751 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4752 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4753 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4754 test_bit(FW_FLAGS_UC, &fw_flags) ||
4755 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4756 dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n");
4760 if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4761 dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n");
4765 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4766 dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n");
4769 __set_bit(FW_FLAGS_NC, &fw_flags);
4771 case RTL_FW_PHY_UNION_NC1:
4772 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4773 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4774 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4775 test_bit(FW_FLAGS_UC, &fw_flags) ||
4776 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4777 dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n");
4781 if (test_bit(FW_FLAGS_NC1, &fw_flags)) {
4782 dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n");
4786 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4787 dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n");
4790 __set_bit(FW_FLAGS_NC1, &fw_flags);
4792 case RTL_FW_PHY_UNION_NC2:
4793 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4794 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4795 test_bit(FW_FLAGS_UC, &fw_flags) ||
4796 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4797 dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n");
4801 if (test_bit(FW_FLAGS_NC2, &fw_flags)) {
4802 dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n");
4806 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4807 dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n");
4810 __set_bit(FW_FLAGS_NC2, &fw_flags);
4812 case RTL_FW_PHY_UNION_UC2:
4813 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4814 test_bit(FW_FLAGS_UC, &fw_flags) ||
4815 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4816 dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n");
4820 if (test_bit(FW_FLAGS_UC2, &fw_flags)) {
4821 dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n");
4825 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4826 dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n");
4829 __set_bit(FW_FLAGS_UC2, &fw_flags);
4831 case RTL_FW_PHY_UNION_UC:
4832 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4833 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4834 dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n");
4838 if (test_bit(FW_FLAGS_UC, &fw_flags)) {
4839 dev_err(&tp->intf->dev, "multiple PHY UC encountered\n");
4843 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4844 dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n");
4847 __set_bit(FW_FLAGS_UC, &fw_flags);
4849 case RTL_FW_PHY_UNION_MISC:
4850 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4851 dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n");
4855 case RTL_FW_PHY_FIXUP:
4856 if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) {
4857 dev_err(&tp->intf->dev, "check PHY fixup failed\n");
4861 case RTL_FW_PHY_SPEED_UP:
4862 if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {
4863 dev_err(&tp->intf->dev, "multiple PHY firmware encountered");
4867 if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) {
4868 dev_err(&tp->intf->dev, "check PHY speed up failed\n");
4871 __set_bit(FW_FLAGS_SPEED_UP, &fw_flags);
4873 case RTL_FW_PHY_VER:
4874 if (test_bit(FW_FLAGS_START, &fw_flags) ||
4875 test_bit(FW_FLAGS_NC, &fw_flags) ||
4876 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4877 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4878 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4879 test_bit(FW_FLAGS_UC, &fw_flags) ||
4880 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4881 dev_err(&tp->intf->dev, "Invalid order to set PHY version\n");
4885 if (test_bit(FW_FLAGS_VER, &fw_flags)) {
4886 dev_err(&tp->intf->dev, "multiple PHY version encountered");
4890 if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) {
4891 dev_err(&tp->intf->dev, "check PHY version failed\n");
4894 __set_bit(FW_FLAGS_VER, &fw_flags);
4897 dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
4903 i += ALIGN(__le32_to_cpu(block->length), 8);
4907 if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {
4908 dev_err(&tp->intf->dev, "without PHY_STOP\n");
4917 static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)
4922 rtl_reset_ocp_base(tp);
4924 if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {
4925 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4929 len = __le32_to_cpu(phy->blk_hdr.length);
4930 len -= __le16_to_cpu(phy->fw_offset);
4931 data = (u8 *)phy + __le16_to_cpu(phy->fw_offset);
4933 if (rtl_phy_patch_request(tp, true, wait))
4945 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);
4946 ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;
4947 ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data);
4949 generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB);
4954 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);
4955 ocp_data |= POL_GPHY_PATCH;
4956 ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data);
4958 for (i = 0; i < 1000; i++) {
4959 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))
4964 dev_err(&tp->intf->dev, "ram code speedup mode timeout\n");
4969 rtl_reset_ocp_base(tp);
4971 rtl_phy_patch_request(tp, false, wait);
4973 if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))
4974 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4976 dev_err(&tp->intf->dev, "ram code speedup mode fail\n");
4979 static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)
4983 ver_addr = __le16_to_cpu(phy_ver->ver.addr);
4984 ver = __le16_to_cpu(phy_ver->ver.data);
4986 rtl_reset_ocp_base(tp);
4988 if (sram_read(tp, ver_addr) >= ver) {
4989 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4993 sram_write(tp, ver_addr, ver);
4995 dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver);
5000 static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)
5004 rtl_reset_ocp_base(tp);
5006 addr = __le16_to_cpu(fix->setting.addr);
5007 data = ocp_reg_read(tp, addr);
5009 switch (__le16_to_cpu(fix->bit_cmd)) {
5011 data &= __le16_to_cpu(fix->setting.data);
5014 data |= __le16_to_cpu(fix->setting.data);
5017 data &= ~__le16_to_cpu(fix->setting.data);
5020 data ^= __le16_to_cpu(fix->setting.data);
5026 ocp_reg_write(tp, addr, data);
5028 dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data);
5031 static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)
5037 rtl_reset_ocp_base(tp);
5040 for (i = 0; i < num; i++)
5041 sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),
5042 __le16_to_cpu(phy->pre_set[i].data));
5044 length = __le32_to_cpu(phy->blk_hdr.length);
5045 length -= __le16_to_cpu(phy->fw_offset);
5047 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
5049 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
5050 for (i = 0; i < num; i++)
5051 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
5054 for (i = 0; i < num; i++)
5055 sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));
5057 if (phy->bp_num && phy->bp_en.addr)
5058 sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));
5060 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
5063 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
5065 u16 mode_reg, bp_index;
5069 rtl_reset_ocp_base(tp);
5071 mode_reg = __le16_to_cpu(phy->mode_reg);
5072 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
5073 sram_write(tp, __le16_to_cpu(phy->ba_reg),
5074 __le16_to_cpu(phy->ba_data));
5076 length = __le32_to_cpu(phy->blk_hdr.length);
5077 length -= __le16_to_cpu(phy->fw_offset);
5079 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
5081 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
5082 for (i = 0; i < num; i++)
5083 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
5085 sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
5086 __le16_to_cpu(phy->patch_en_value));
5088 bp_index = __le16_to_cpu(phy->bp_start);
5089 num = __le16_to_cpu(phy->bp_num);
5090 for (i = 0; i < num; i++) {
5091 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
5095 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
5097 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
5100 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
5102 u16 bp_en_addr, type, fw_ver_reg;
5106 switch (__le32_to_cpu(mac->blk_hdr.type)) {
5108 type = MCU_TYPE_PLA;
5111 type = MCU_TYPE_USB;
5117 fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
5118 if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) {
5119 dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB");
5123 rtl_clear_bp(tp, type);
5125 /* Enable backup/restore of MACDBG. This is required after clearing PLA
5126 * break points and before applying the PLA firmware.
5128 if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
5129 !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
5130 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
5131 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
5134 length = __le32_to_cpu(mac->blk_hdr.length);
5135 length -= __le16_to_cpu(mac->fw_offset);
5138 data += __le16_to_cpu(mac->fw_offset);
5140 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
5143 ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
5144 __le16_to_cpu(mac->bp_ba_value));
5146 generic_ocp_write(tp, __le16_to_cpu(mac->bp_start), BYTE_EN_DWORD,
5147 __le16_to_cpu(mac->bp_num) << 1, mac->bp, type);
5149 bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
5151 ocp_write_word(tp, type, bp_en_addr,
5152 __le16_to_cpu(mac->bp_en_value));
5155 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
5158 dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
5161 static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
5163 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5164 const struct firmware *fw;
5165 struct fw_header *fw_hdr;
5166 struct fw_phy_patch_key *key;
5168 int i, patch_phy = 1;
5170 if (IS_ERR_OR_NULL(rtl_fw->fw))
5174 fw_hdr = (struct fw_header *)fw->data;
5179 for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
5180 struct fw_block *block = (struct fw_block *)&fw->data[i];
5182 switch (__le32_to_cpu(block->type)) {
5187 rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
5189 case RTL_FW_PHY_START:
5192 key = (struct fw_phy_patch_key *)block;
5193 key_addr = __le16_to_cpu(key->key_reg);
5194 rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);
5196 case RTL_FW_PHY_STOP:
5200 rtl_post_ram_code(tp, key_addr, !power_cut);
5203 rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
5205 case RTL_FW_PHY_VER:
5206 patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block);
5208 case RTL_FW_PHY_UNION_NC:
5209 case RTL_FW_PHY_UNION_NC1:
5210 case RTL_FW_PHY_UNION_NC2:
5211 case RTL_FW_PHY_UNION_UC2:
5212 case RTL_FW_PHY_UNION_UC:
5213 case RTL_FW_PHY_UNION_MISC:
5215 rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block);
5217 case RTL_FW_PHY_FIXUP:
5219 rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block);
5221 case RTL_FW_PHY_SPEED_UP:
5222 rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut);
5228 i += ALIGN(__le32_to_cpu(block->length), 8);
5232 if (rtl_fw->post_fw)
5233 rtl_fw->post_fw(tp);
5235 rtl_reset_ocp_base(tp);
5236 strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
5237 dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
5240 static void rtl8152_release_firmware(struct r8152 *tp)
5242 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5244 if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
5245 release_firmware(rtl_fw->fw);
5250 static int rtl8152_request_firmware(struct r8152 *tp)
5252 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5255 if (rtl_fw->fw || !rtl_fw->fw_name) {
5256 dev_info(&tp->intf->dev, "skip request firmware\n");
5261 rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
5265 rc = rtl8152_check_firmware(tp, rtl_fw);
5267 release_firmware(rtl_fw->fw);
5271 rtl_fw->fw = ERR_PTR(rc);
5273 dev_warn(&tp->intf->dev,
5274 "unable to load firmware patch %s (%ld)\n",
5275 rtl_fw->fw_name, rc);
5281 static void r8152_aldps_en(struct r8152 *tp, bool enable)
5284 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
5285 LINKENA | DIS_SDSAVE);
5287 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
5293 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
5295 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
5296 ocp_reg_write(tp, OCP_EEE_DATA, reg);
5297 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
5300 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
5304 r8152_mmd_indirect(tp, dev, reg);
5305 data = ocp_reg_read(tp, OCP_EEE_DATA);
5306 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5311 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
5313 r8152_mmd_indirect(tp, dev, reg);
5314 ocp_reg_write(tp, OCP_EEE_DATA, data);
5315 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5318 static void r8152_eee_en(struct r8152 *tp, bool enable)
5320 u16 config1, config2, config3;
5323 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5324 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
5325 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
5326 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
5329 ocp_data |= EEE_RX_EN | EEE_TX_EN;
5330 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
5331 config1 |= sd_rise_time(1);
5332 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
5333 config3 |= fast_snr(42);
5335 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5336 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
5338 config1 |= sd_rise_time(7);
5339 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
5340 config3 |= fast_snr(511);
5343 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5344 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
5345 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
5346 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
5349 static void r8153_eee_en(struct r8152 *tp, bool enable)
5354 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5355 config = ocp_reg_read(tp, OCP_EEE_CFG);
5358 ocp_data |= EEE_RX_EN | EEE_TX_EN;
5361 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5362 config &= ~EEE10_EN;
5365 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5366 ocp_reg_write(tp, OCP_EEE_CFG, config);
5368 tp->ups_info.eee = enable;
5371 static void r8156_eee_en(struct r8152 *tp, bool enable)
5375 r8153_eee_en(tp, enable);
5377 config = ocp_reg_read(tp, OCP_EEE_ADV2);
5380 config |= MDIO_EEE_2_5GT;
5382 config &= ~MDIO_EEE_2_5GT;
5384 ocp_reg_write(tp, OCP_EEE_ADV2, config);
5387 static void rtl_eee_enable(struct r8152 *tp, bool enable)
5389 switch (tp->version) {
5394 r8152_eee_en(tp, true);
5395 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
5398 r8152_eee_en(tp, false);
5399 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
5410 r8153_eee_en(tp, true);
5411 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5413 r8153_eee_en(tp, false);
5414 ocp_reg_write(tp, OCP_EEE_ADV, 0);
5423 r8156_eee_en(tp, true);
5424 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5426 r8156_eee_en(tp, false);
5427 ocp_reg_write(tp, OCP_EEE_ADV, 0);
5435 static void r8152b_enable_fc(struct r8152 *tp)
5439 anar = r8152_mdio_read(tp, MII_ADVERTISE);
5440 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
5441 r8152_mdio_write(tp, MII_ADVERTISE, anar);
5443 tp->ups_info.flow_control = true;
5446 static void rtl8152_disable(struct r8152 *tp)
5448 r8152_aldps_en(tp, false);
5450 r8152_aldps_en(tp, true);
5453 static void r8152b_hw_phy_cfg(struct r8152 *tp)
5455 rtl8152_apply_firmware(tp, false);
5456 rtl_eee_enable(tp, tp->eee_en);
5457 r8152_aldps_en(tp, true);
5458 r8152b_enable_fc(tp);
5460 set_bit(PHY_RESET, &tp->flags);
5463 static void wait_oob_link_list_ready(struct r8152 *tp)
5468 for (i = 0; i < 1000; i++) {
5469 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5470 if (ocp_data & LINK_LIST_READY)
5472 usleep_range(1000, 2000);
5476 static void r8156b_wait_loading_flash(struct r8152 *tp)
5478 if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
5479 !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
5482 for (i = 0; i < 100; i++) {
5483 if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
5485 usleep_range(1000, 2000);
5490 static void r8152b_exit_oob(struct r8152 *tp)
5494 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5495 ocp_data &= ~RCR_ACPT_ALL;
5496 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5498 rxdy_gated_en(tp, true);
5499 r8153_teredo_off(tp);
5500 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
5501 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
5503 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5504 ocp_data &= ~NOW_IS_OOB;
5505 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5507 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5508 ocp_data &= ~MCU_BORW_EN;
5509 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5511 wait_oob_link_list_ready(tp);
5513 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5514 ocp_data |= RE_INIT_LL;
5515 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5517 wait_oob_link_list_ready(tp);
5519 rtl8152_nic_reset(tp);
5521 /* rx share fifo credit full threshold */
5522 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5524 if (tp->udev->speed == USB_SPEED_FULL ||
5525 tp->udev->speed == USB_SPEED_LOW) {
5526 /* rx share fifo credit near full threshold */
5527 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5529 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5532 /* rx share fifo credit near full threshold */
5533 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5535 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5539 /* TX share fifo free credit full threshold */
5540 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5542 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
5543 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
5544 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
5545 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
5547 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5549 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5551 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5552 ocp_data |= TCR0_AUTO_FIFO;
5553 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5556 static void r8152b_enter_oob(struct r8152 *tp)
5560 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5561 ocp_data &= ~NOW_IS_OOB;
5562 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5564 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
5565 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
5566 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
5570 wait_oob_link_list_ready(tp);
5572 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5573 ocp_data |= RE_INIT_LL;
5574 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5576 wait_oob_link_list_ready(tp);
5578 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5580 rtl_rx_vlan_en(tp, true);
5582 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5583 ocp_data |= ALDPS_PROXY_MODE;
5584 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5586 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5587 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5588 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5590 rxdy_gated_en(tp, false);
5592 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5593 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5594 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5597 static int r8153_pre_firmware_1(struct r8152 *tp)
5601 /* Wait till the WTD timer is ready. It would take at most 104 ms. */
5602 for (i = 0; i < 104; i++) {
5603 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
5605 if (!(ocp_data & WTD1_EN))
5607 usleep_range(1000, 2000);
5613 static int r8153_post_firmware_1(struct r8152 *tp)
5615 /* set USB_BP_4 to support USB_SPEED_SUPER only */
5616 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
5617 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
5619 /* reset UPHY timer to 36 ms */
5620 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5625 static int r8153_pre_firmware_2(struct r8152 *tp)
5629 r8153_pre_firmware_1(tp);
5631 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5632 ocp_data &= ~FW_FIX_SUSPEND;
5633 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5638 static int r8153_post_firmware_2(struct r8152 *tp)
5642 /* enable bp0 if support USB_SPEED_SUPER only */
5643 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
5644 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5646 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5649 /* reset UPHY timer to 36 ms */
5650 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5652 /* enable U3P3 check, set the counter to 4 */
5653 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
5655 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5656 ocp_data |= FW_FIX_SUSPEND;
5657 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5659 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5660 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5661 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5666 static int r8153_post_firmware_3(struct r8152 *tp)
5670 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5671 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5672 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5674 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5675 ocp_data |= FW_IP_RESET_EN;
5676 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5681 static int r8153b_pre_firmware_1(struct r8152 *tp)
5683 /* enable fc timer and set timer to 1 second. */
5684 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
5685 CTRL_TIMER_EN | (1000 / 8));
5690 static int r8153b_post_firmware_1(struct r8152 *tp)
5694 /* enable bp0 for RTL8153-BND */
5695 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
5696 if (ocp_data & BND_MASK) {
5697 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5699 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5702 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5703 ocp_data |= FLOW_CTRL_PATCH_OPT;
5704 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5706 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5707 ocp_data |= FC_PATCH_TASK;
5708 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5710 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5711 ocp_data |= FW_IP_RESET_EN;
5712 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5717 static int r8153c_post_firmware_1(struct r8152 *tp)
5721 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5722 ocp_data |= FLOW_CTRL_PATCH_2;
5723 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5725 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5726 ocp_data |= FC_PATCH_TASK;
5727 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5732 static int r8156a_post_firmware_1(struct r8152 *tp)
5736 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5737 ocp_data |= FW_IP_RESET_EN;
5738 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5740 /* Modify U3PHY parameter for compatibility issue */
5741 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e);
5742 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9);
5747 static void r8153_aldps_en(struct r8152 *tp, bool enable)
5751 data = ocp_reg_read(tp, OCP_POWER_CFG);
5754 ocp_reg_write(tp, OCP_POWER_CFG, data);
5759 ocp_reg_write(tp, OCP_POWER_CFG, data);
5760 for (i = 0; i < 20; i++) {
5761 usleep_range(1000, 2000);
5762 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
5767 tp->ups_info.aldps = enable;
5770 static void r8153_hw_phy_cfg(struct r8152 *tp)
5775 /* disable ALDPS before updating the PHY parameters */
5776 r8153_aldps_en(tp, false);
5778 /* disable EEE before updating the PHY parameters */
5779 rtl_eee_enable(tp, false);
5781 rtl8152_apply_firmware(tp, false);
5783 if (tp->version == RTL_VER_03) {
5784 data = ocp_reg_read(tp, OCP_EEE_CFG);
5785 data &= ~CTAP_SHORT_EN;
5786 ocp_reg_write(tp, OCP_EEE_CFG, data);
5789 data = ocp_reg_read(tp, OCP_POWER_CFG);
5790 data |= EEE_CLKDIV_EN;
5791 ocp_reg_write(tp, OCP_POWER_CFG, data);
5793 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5794 data |= EN_10M_BGOFF;
5795 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5796 data = ocp_reg_read(tp, OCP_POWER_CFG);
5797 data |= EN_10M_PLLOFF;
5798 ocp_reg_write(tp, OCP_POWER_CFG, data);
5799 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
5801 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5802 ocp_data |= PFM_PWM_SWITCH;
5803 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5805 /* Enable LPF corner auto tune */
5806 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
5808 /* Adjust 10M Amplitude */
5809 sram_write(tp, SRAM_10M_AMP1, 0x00af);
5810 sram_write(tp, SRAM_10M_AMP2, 0x0208);
5813 rtl_eee_enable(tp, true);
5815 r8153_aldps_en(tp, true);
5816 r8152b_enable_fc(tp);
5818 switch (tp->version) {
5825 r8153_u2p3en(tp, true);
5829 set_bit(PHY_RESET, &tp->flags);
5832 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
5836 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
5837 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
5838 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
5839 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
5844 static void r8153b_hw_phy_cfg(struct r8152 *tp)
5849 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
5850 if (ocp_data & PCUT_STATUS) {
5851 ocp_data &= ~PCUT_STATUS;
5852 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
5855 /* disable ALDPS before updating the PHY parameters */
5856 r8153_aldps_en(tp, false);
5858 /* disable EEE before updating the PHY parameters */
5859 rtl_eee_enable(tp, false);
5861 /* U1/U2/L1 idle timer. 500 us */
5862 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5864 data = r8153_phy_status(tp, 0);
5867 case PHY_STAT_PWRDN:
5868 case PHY_STAT_EXT_INIT:
5869 rtl8152_apply_firmware(tp, true);
5871 data = r8152_mdio_read(tp, MII_BMCR);
5872 data &= ~BMCR_PDOWN;
5873 r8152_mdio_write(tp, MII_BMCR, data);
5875 case PHY_STAT_LAN_ON:
5877 rtl8152_apply_firmware(tp, false);
5881 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
5883 data = sram_read(tp, SRAM_GREEN_CFG);
5885 sram_write(tp, SRAM_GREEN_CFG, data);
5886 data = ocp_reg_read(tp, OCP_NCTL_CFG);
5887 data |= PGA_RETURN_EN;
5888 ocp_reg_write(tp, OCP_NCTL_CFG, data);
5890 /* ADC Bias Calibration:
5891 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
5892 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
5895 ocp_data = r8152_efuse_read(tp, 0x7d);
5896 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
5898 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
5900 /* ups mode tx-link-pulse timing adjustment:
5901 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
5902 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
5904 ocp_data = ocp_reg_read(tp, 0xc426);
5907 u32 swr_cnt_1ms_ini;
5909 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
5910 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
5911 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
5912 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
5915 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5916 ocp_data |= PFM_PWM_SWITCH;
5917 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5920 if (!rtl_phy_patch_request(tp, true, true)) {
5921 data = ocp_reg_read(tp, OCP_POWER_CFG);
5922 data |= EEE_CLKDIV_EN;
5923 ocp_reg_write(tp, OCP_POWER_CFG, data);
5924 tp->ups_info.eee_ckdiv = true;
5926 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5927 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
5928 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5929 tp->ups_info.eee_cmod_lv = true;
5930 tp->ups_info._10m_ckdiv = true;
5931 tp->ups_info.eee_plloff_giga = true;
5933 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
5934 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
5935 tp->ups_info._250m_ckdiv = true;
5937 rtl_phy_patch_request(tp, false, true);
5941 rtl_eee_enable(tp, true);
5943 r8153_aldps_en(tp, true);
5944 r8152b_enable_fc(tp);
5946 set_bit(PHY_RESET, &tp->flags);
5949 static void r8153c_hw_phy_cfg(struct r8152 *tp)
5951 r8153b_hw_phy_cfg(tp);
5953 tp->ups_info.r_tune = true;
5956 static void rtl8153_change_mtu(struct r8152 *tp)
5958 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5959 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
5962 static void r8153_first_init(struct r8152 *tp)
5966 rxdy_gated_en(tp, true);
5967 r8153_teredo_off(tp);
5969 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5970 ocp_data &= ~RCR_ACPT_ALL;
5971 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5973 rtl8152_nic_reset(tp);
5976 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5977 ocp_data &= ~NOW_IS_OOB;
5978 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5980 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5981 ocp_data &= ~MCU_BORW_EN;
5982 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5984 wait_oob_link_list_ready(tp);
5986 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5987 ocp_data |= RE_INIT_LL;
5988 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5990 wait_oob_link_list_ready(tp);
5992 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5994 rtl8153_change_mtu(tp);
5996 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5997 ocp_data |= TCR0_AUTO_FIFO;
5998 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
6000 rtl8152_nic_reset(tp);
6002 /* rx share fifo credit full threshold */
6003 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
6004 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6005 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6006 /* TX share fifo free credit full threshold */
6007 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
6010 static void r8153_enter_oob(struct r8152 *tp)
6014 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6015 ocp_data &= ~NOW_IS_OOB;
6016 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6018 /* RX FIFO settings for OOB */
6019 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
6020 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
6021 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
6026 wait_oob_link_list_ready(tp);
6028 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6029 ocp_data |= RE_INIT_LL;
6030 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6032 wait_oob_link_list_ready(tp);
6034 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522);
6035 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
6037 switch (tp->version) {
6042 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
6043 ocp_data &= ~TEREDO_WAKE_MASK;
6044 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
6050 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
6051 * type. Set it to zero. bits[7:0] are the W1C bits about
6052 * the events. Set them to all 1 to clear them.
6054 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
6061 rtl_rx_vlan_en(tp, true);
6063 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
6064 ocp_data |= ALDPS_PROXY_MODE;
6065 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
6067 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6068 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
6069 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6071 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6072 ocp_data |= MCU_BORW_EN;
6073 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6075 rxdy_gated_en(tp, false);
6077 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6078 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6079 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6082 static void rtl8153_disable(struct r8152 *tp)
6084 r8153_aldps_en(tp, false);
6087 r8153_aldps_en(tp, true);
6090 static u32 fc_pause_on_auto(struct r8152 *tp)
6092 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
6095 static u32 fc_pause_off_auto(struct r8152 *tp)
6097 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
6100 static void r8156_fc_parameter(struct r8152 *tp)
6102 u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
6103 u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
6105 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16);
6106 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16);
6109 static int rtl8156_enable(struct r8152 *tp)
6114 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6117 r8156_fc_parameter(tp);
6119 rtl_set_eee_plus(tp);
6120 r8153_set_rx_early_timeout(tp);
6121 r8153_set_rx_early_size(tp);
6123 speed = rtl8152_get_speed(tp);
6124 rtl_set_ifg(tp, speed);
6126 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6127 if (speed & _2500bps)
6128 ocp_data &= ~IDLE_SPDWN_EN;
6130 ocp_data |= IDLE_SPDWN_EN;
6131 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
6133 if (speed & _1000bps)
6134 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);
6135 else if (speed & _500bps)
6136 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d);
6138 if (tp->udev->speed == USB_SPEED_HIGH) {
6139 /* USB 0xb45e[3:0] l1_nyet_hird */
6140 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6142 if (is_flow_control(speed))
6146 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6149 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6150 ocp_data &= ~FC_PATCH_TASK;
6151 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6152 usleep_range(1000, 2000);
6153 ocp_data |= FC_PATCH_TASK;
6154 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6156 return rtl_enable(tp);
6159 static void rtl8156_disable(struct r8152 *tp)
6161 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 0);
6162 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 0);
6164 rtl8153_disable(tp);
6167 static int rtl8156b_enable(struct r8152 *tp)
6172 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6176 rtl_set_eee_plus(tp);
6178 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
6179 ocp_data &= ~RX_AGGR_NUM_MASK;
6180 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);
6182 r8153_set_rx_early_timeout(tp);
6183 r8153_set_rx_early_size(tp);
6185 speed = rtl8152_get_speed(tp);
6186 rtl_set_ifg(tp, speed);
6188 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6189 if (speed & _2500bps)
6190 ocp_data &= ~IDLE_SPDWN_EN;
6192 ocp_data |= IDLE_SPDWN_EN;
6193 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
6195 if (tp->udev->speed == USB_SPEED_HIGH) {
6196 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6198 if (is_flow_control(speed))
6202 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6205 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6206 ocp_data &= ~FC_PATCH_TASK;
6207 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6208 usleep_range(1000, 2000);
6209 ocp_data |= FC_PATCH_TASK;
6210 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6212 return rtl_enable(tp);
6215 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
6221 if (autoneg == AUTONEG_DISABLE) {
6222 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
6227 bmcr = BMCR_SPEED10;
6228 if (duplex == DUPLEX_FULL) {
6229 bmcr |= BMCR_FULLDPLX;
6230 tp->ups_info.speed_duplex = FORCE_10M_FULL;
6232 tp->ups_info.speed_duplex = FORCE_10M_HALF;
6236 bmcr = BMCR_SPEED100;
6237 if (duplex == DUPLEX_FULL) {
6238 bmcr |= BMCR_FULLDPLX;
6239 tp->ups_info.speed_duplex = FORCE_100M_FULL;
6241 tp->ups_info.speed_duplex = FORCE_100M_HALF;
6245 if (tp->mii.supports_gmii) {
6246 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
6247 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6256 if (duplex == DUPLEX_FULL)
6257 tp->mii.full_duplex = 1;
6259 tp->mii.full_duplex = 0;
6261 tp->mii.force_media = 1;
6266 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6267 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6269 if (tp->mii.supports_gmii) {
6270 support |= RTL_ADVERTISED_1000_FULL;
6272 if (tp->support_2500full)
6273 support |= RTL_ADVERTISED_2500_FULL;
6276 if (!(advertising & support))
6279 orig = r8152_mdio_read(tp, MII_ADVERTISE);
6280 new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
6281 ADVERTISE_100HALF | ADVERTISE_100FULL);
6282 if (advertising & RTL_ADVERTISED_10_HALF) {
6283 new1 |= ADVERTISE_10HALF;
6284 tp->ups_info.speed_duplex = NWAY_10M_HALF;
6286 if (advertising & RTL_ADVERTISED_10_FULL) {
6287 new1 |= ADVERTISE_10FULL;
6288 tp->ups_info.speed_duplex = NWAY_10M_FULL;
6291 if (advertising & RTL_ADVERTISED_100_HALF) {
6292 new1 |= ADVERTISE_100HALF;
6293 tp->ups_info.speed_duplex = NWAY_100M_HALF;
6295 if (advertising & RTL_ADVERTISED_100_FULL) {
6296 new1 |= ADVERTISE_100FULL;
6297 tp->ups_info.speed_duplex = NWAY_100M_FULL;
6301 r8152_mdio_write(tp, MII_ADVERTISE, new1);
6302 tp->mii.advertising = new1;
6305 if (tp->mii.supports_gmii) {
6306 orig = r8152_mdio_read(tp, MII_CTRL1000);
6307 new1 = orig & ~(ADVERTISE_1000FULL |
6308 ADVERTISE_1000HALF);
6310 if (advertising & RTL_ADVERTISED_1000_FULL) {
6311 new1 |= ADVERTISE_1000FULL;
6312 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6316 r8152_mdio_write(tp, MII_CTRL1000, new1);
6319 if (tp->support_2500full) {
6320 orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
6321 new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
6323 if (advertising & RTL_ADVERTISED_2500_FULL) {
6324 new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
6325 tp->ups_info.speed_duplex = NWAY_2500M_FULL;
6329 ocp_reg_write(tp, OCP_10GBT_CTRL, new1);
6332 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
6334 tp->mii.force_media = 0;
6337 if (test_and_clear_bit(PHY_RESET, &tp->flags))
6340 r8152_mdio_write(tp, MII_BMCR, bmcr);
6342 if (bmcr & BMCR_RESET) {
6345 for (i = 0; i < 50; i++) {
6347 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
6356 static void rtl8152_up(struct r8152 *tp)
6358 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6361 r8152_aldps_en(tp, false);
6362 r8152b_exit_oob(tp);
6363 r8152_aldps_en(tp, true);
6366 static void rtl8152_down(struct r8152 *tp)
6368 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6369 rtl_drop_queued_tx(tp);
6373 r8152_power_cut_en(tp, false);
6374 r8152_aldps_en(tp, false);
6375 r8152b_enter_oob(tp);
6376 r8152_aldps_en(tp, true);
6379 static void rtl8153_up(struct r8152 *tp)
6383 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6386 r8153_u1u2en(tp, false);
6387 r8153_u2p3en(tp, false);
6388 r8153_aldps_en(tp, false);
6389 r8153_first_init(tp);
6391 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6392 ocp_data |= LANWAKE_CLR_EN;
6393 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6395 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6396 ocp_data &= ~LANWAKE_PIN;
6397 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
6399 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
6400 ocp_data &= ~DELAY_PHY_PWR_CHG;
6401 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
6403 r8153_aldps_en(tp, true);
6405 switch (tp->version) {
6412 r8153_u2p3en(tp, true);
6416 r8153_u1u2en(tp, true);
6419 static void rtl8153_down(struct r8152 *tp)
6423 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6424 rtl_drop_queued_tx(tp);
6428 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6429 ocp_data &= ~LANWAKE_CLR_EN;
6430 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6432 r8153_u1u2en(tp, false);
6433 r8153_u2p3en(tp, false);
6434 r8153_power_cut_en(tp, false);
6435 r8153_aldps_en(tp, false);
6436 r8153_enter_oob(tp);
6437 r8153_aldps_en(tp, true);
6440 static void rtl8153b_up(struct r8152 *tp)
6444 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6447 r8153b_u1u2en(tp, false);
6448 r8153_u2p3en(tp, false);
6449 r8153_aldps_en(tp, false);
6451 r8153_first_init(tp);
6452 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6454 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6455 ocp_data &= ~PLA_MCU_SPDWN_EN;
6456 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6458 r8153_aldps_en(tp, true);
6460 if (tp->udev->speed >= USB_SPEED_SUPER)
6461 r8153b_u1u2en(tp, true);
6464 static void rtl8153b_down(struct r8152 *tp)
6468 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6469 rtl_drop_queued_tx(tp);
6473 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6474 ocp_data |= PLA_MCU_SPDWN_EN;
6475 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6477 r8153b_u1u2en(tp, false);
6478 r8153_u2p3en(tp, false);
6479 r8153b_power_cut_en(tp, false);
6480 r8153_aldps_en(tp, false);
6481 r8153_enter_oob(tp);
6482 r8153_aldps_en(tp, true);
6485 static void rtl8153c_change_mtu(struct r8152 *tp)
6487 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
6488 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64);
6490 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6492 /* Adjust the tx fifo free credit full threshold, otherwise
6493 * the fifo would be too small to send a jumbo frame packet.
6495 if (tp->netdev->mtu < 8000)
6496 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8);
6498 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8);
6501 static void rtl8153c_up(struct r8152 *tp)
6505 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6508 r8153b_u1u2en(tp, false);
6509 r8153_u2p3en(tp, false);
6510 r8153_aldps_en(tp, false);
6512 rxdy_gated_en(tp, true);
6513 r8153_teredo_off(tp);
6515 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6516 ocp_data &= ~RCR_ACPT_ALL;
6517 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6519 rtl8152_nic_reset(tp);
6522 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6523 ocp_data &= ~NOW_IS_OOB;
6524 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6526 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6527 ocp_data &= ~MCU_BORW_EN;
6528 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6530 wait_oob_link_list_ready(tp);
6532 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6533 ocp_data |= RE_INIT_LL;
6534 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6536 wait_oob_link_list_ready(tp);
6538 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6540 rtl8153c_change_mtu(tp);
6542 rtl8152_nic_reset(tp);
6544 /* rx share fifo credit full threshold */
6545 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02);
6546 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08);
6547 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6548 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6550 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6552 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
6554 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
6556 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
6558 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
6560 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6561 ocp_data &= ~PLA_MCU_SPDWN_EN;
6562 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6564 r8153_aldps_en(tp, true);
6565 r8153b_u1u2en(tp, true);
6568 static void rtl8156_change_mtu(struct r8152 *tp)
6570 u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
6572 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size);
6573 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
6574 r8156_fc_parameter(tp);
6576 /* TX share fifo free credit full threshold */
6577 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6578 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
6579 ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
6582 static void rtl8156_up(struct r8152 *tp)
6586 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6589 r8153b_u1u2en(tp, false);
6590 r8153_u2p3en(tp, false);
6591 r8153_aldps_en(tp, false);
6593 rxdy_gated_en(tp, true);
6594 r8153_teredo_off(tp);
6596 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6597 ocp_data &= ~RCR_ACPT_ALL;
6598 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6600 rtl8152_nic_reset(tp);
6603 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6604 ocp_data &= ~NOW_IS_OOB;
6605 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6607 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6608 ocp_data &= ~MCU_BORW_EN;
6609 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6611 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6613 rtl8156_change_mtu(tp);
6615 switch (tp->version) {
6619 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
6620 ocp_data |= ACT_ODMA;
6621 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
6627 /* share FIFO settings */
6628 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
6629 ocp_data &= ~RXFIFO_FULL_MASK;
6631 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);
6633 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6634 ocp_data &= ~PLA_MCU_SPDWN_EN;
6635 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6637 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
6638 ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
6639 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);
6641 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);
6643 if (tp->saved_wolopts != __rtl_get_wol(tp)) {
6644 netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
6645 __rtl_set_wol(tp, tp->saved_wolopts);
6648 r8153_aldps_en(tp, true);
6649 r8153_u2p3en(tp, true);
6651 if (tp->udev->speed >= USB_SPEED_SUPER)
6652 r8153b_u1u2en(tp, true);
6655 static void rtl8156_down(struct r8152 *tp)
6659 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6660 rtl_drop_queued_tx(tp);
6664 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6665 ocp_data |= PLA_MCU_SPDWN_EN;
6666 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6668 r8153b_u1u2en(tp, false);
6669 r8153_u2p3en(tp, false);
6670 r8153b_power_cut_en(tp, false);
6671 r8153_aldps_en(tp, false);
6673 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6674 ocp_data &= ~NOW_IS_OOB;
6675 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6677 /* RX FIFO settings for OOB */
6678 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 64 / 16);
6679 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 1024 / 16);
6680 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 4096 / 16);
6685 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522);
6686 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
6688 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
6689 * type. Set it to zero. bits[7:0] are the W1C bits about
6690 * the events. Set them to all 1 to clear them.
6692 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
6694 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6695 ocp_data |= NOW_IS_OOB;
6696 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6698 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6699 ocp_data |= MCU_BORW_EN;
6700 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6702 rtl_rx_vlan_en(tp, true);
6703 rxdy_gated_en(tp, false);
6705 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6706 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6707 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6709 r8153_aldps_en(tp, true);
6712 static bool rtl8152_in_nway(struct r8152 *tp)
6716 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
6717 tp->ocp_base = 0x2000;
6718 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
6719 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
6721 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
6722 if (nway_state & 0xc000)
6728 static bool rtl8153_in_nway(struct r8152 *tp)
6730 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
6732 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
6738 static void r8156_mdio_force_mode(struct r8152 *tp)
6742 /* Select force mode through 0xa5b4 bit 15
6743 * 0: MDIO force mode
6746 data = ocp_reg_read(tp, 0xa5b4);
6747 if (data & BIT(15)) {
6749 ocp_reg_write(tp, 0xa5b4, data);
6753 static void set_carrier(struct r8152 *tp)
6755 struct net_device *netdev = tp->netdev;
6756 struct napi_struct *napi = &tp->napi;
6759 speed = rtl8152_get_speed(tp);
6761 if (speed & LINK_STATUS) {
6762 if (!netif_carrier_ok(netdev)) {
6763 tp->rtl_ops.enable(tp);
6764 netif_stop_queue(netdev);
6766 netif_carrier_on(netdev);
6768 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6769 _rtl8152_set_rx_mode(netdev);
6771 netif_wake_queue(netdev);
6772 netif_info(tp, link, netdev, "carrier on\n");
6773 } else if (netif_queue_stopped(netdev) &&
6774 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
6775 netif_wake_queue(netdev);
6778 if (netif_carrier_ok(netdev)) {
6779 netif_carrier_off(netdev);
6780 tasklet_disable(&tp->tx_tl);
6782 tp->rtl_ops.disable(tp);
6784 tasklet_enable(&tp->tx_tl);
6785 netif_info(tp, link, netdev, "carrier off\n");
6790 static void rtl_work_func_t(struct work_struct *work)
6792 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
6794 /* If the device is unplugged or !netif_running(), the workqueue
6795 * doesn't need to wake the device, and could return directly.
6797 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || !netif_running(tp->netdev))
6800 if (usb_autopm_get_interface(tp->intf) < 0)
6803 if (!test_bit(WORK_ENABLE, &tp->flags))
6806 if (!mutex_trylock(&tp->control)) {
6807 schedule_delayed_work(&tp->schedule, 0);
6811 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
6814 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
6815 _rtl8152_set_rx_mode(tp->netdev);
6817 /* don't schedule tasket before linking */
6818 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
6819 netif_carrier_ok(tp->netdev))
6820 tasklet_schedule(&tp->tx_tl);
6822 if (test_and_clear_bit(RX_EPROTO, &tp->flags) &&
6823 !list_empty(&tp->rx_done))
6824 napi_schedule(&tp->napi);
6826 mutex_unlock(&tp->control);
6829 usb_autopm_put_interface(tp->intf);
6832 static void rtl_hw_phy_work_func_t(struct work_struct *work)
6834 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
6836 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6839 if (usb_autopm_get_interface(tp->intf) < 0)
6842 mutex_lock(&tp->control);
6844 if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
6845 tp->rtl_fw.retry = false;
6846 tp->rtl_fw.fw = NULL;
6848 /* Delay execution in case request_firmware() is not ready yet.
6850 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
6854 tp->rtl_ops.hw_phy_cfg(tp);
6856 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
6860 mutex_unlock(&tp->control);
6862 usb_autopm_put_interface(tp->intf);
6865 #ifdef CONFIG_PM_SLEEP
6866 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
6869 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
6872 case PM_HIBERNATION_PREPARE:
6873 case PM_SUSPEND_PREPARE:
6874 usb_autopm_get_interface(tp->intf);
6877 case PM_POST_HIBERNATION:
6878 case PM_POST_SUSPEND:
6879 usb_autopm_put_interface(tp->intf);
6882 case PM_POST_RESTORE:
6883 case PM_RESTORE_PREPARE:
6892 static int rtl8152_open(struct net_device *netdev)
6894 struct r8152 *tp = netdev_priv(netdev);
6897 if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
6898 cancel_delayed_work_sync(&tp->hw_phy_work);
6899 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
6902 res = alloc_all_mem(tp);
6906 res = usb_autopm_get_interface(tp->intf);
6910 mutex_lock(&tp->control);
6914 netif_carrier_off(netdev);
6915 netif_start_queue(netdev);
6916 set_bit(WORK_ENABLE, &tp->flags);
6918 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
6921 netif_device_detach(tp->netdev);
6922 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
6926 napi_enable(&tp->napi);
6927 tasklet_enable(&tp->tx_tl);
6929 mutex_unlock(&tp->control);
6931 usb_autopm_put_interface(tp->intf);
6932 #ifdef CONFIG_PM_SLEEP
6933 tp->pm_notifier.notifier_call = rtl_notifier;
6934 register_pm_notifier(&tp->pm_notifier);
6939 mutex_unlock(&tp->control);
6940 usb_autopm_put_interface(tp->intf);
6947 static int rtl8152_close(struct net_device *netdev)
6949 struct r8152 *tp = netdev_priv(netdev);
6952 #ifdef CONFIG_PM_SLEEP
6953 unregister_pm_notifier(&tp->pm_notifier);
6955 tasklet_disable(&tp->tx_tl);
6956 clear_bit(WORK_ENABLE, &tp->flags);
6957 usb_kill_urb(tp->intr_urb);
6958 cancel_delayed_work_sync(&tp->schedule);
6959 napi_disable(&tp->napi);
6960 netif_stop_queue(netdev);
6962 res = usb_autopm_get_interface(tp->intf);
6963 if (res < 0 || test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6964 rtl_drop_queued_tx(tp);
6967 mutex_lock(&tp->control);
6969 tp->rtl_ops.down(tp);
6971 mutex_unlock(&tp->control);
6975 usb_autopm_put_interface(tp->intf);
6982 static void rtl_tally_reset(struct r8152 *tp)
6986 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
6987 ocp_data |= TALLY_RESET;
6988 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
6991 static void r8152b_init(struct r8152 *tp)
6996 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6999 data = r8152_mdio_read(tp, MII_BMCR);
7000 if (data & BMCR_PDOWN) {
7001 data &= ~BMCR_PDOWN;
7002 r8152_mdio_write(tp, MII_BMCR, data);
7005 r8152_aldps_en(tp, false);
7007 if (tp->version == RTL_VER_01) {
7008 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
7009 ocp_data &= ~LED_MODE_MASK;
7010 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
7013 r8152_power_cut_en(tp, false);
7015 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7016 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
7017 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7018 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
7019 ocp_data &= ~MCU_CLK_RATIO_MASK;
7020 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
7021 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
7022 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
7023 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
7024 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
7026 rtl_tally_reset(tp);
7028 /* enable rx aggregation */
7029 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7030 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7031 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7034 static void r8153_init(struct r8152 *tp)
7040 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7043 r8153_u1u2en(tp, false);
7045 for (i = 0; i < 500; i++) {
7046 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7051 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7055 data = r8153_phy_status(tp, 0);
7057 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
7058 tp->version == RTL_VER_05)
7059 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
7061 data = r8152_mdio_read(tp, MII_BMCR);
7062 if (data & BMCR_PDOWN) {
7063 data &= ~BMCR_PDOWN;
7064 r8152_mdio_write(tp, MII_BMCR, data);
7067 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7069 r8153_u2p3en(tp, false);
7071 if (tp->version == RTL_VER_04) {
7072 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
7073 ocp_data &= ~pwd_dn_scale_mask;
7074 ocp_data |= pwd_dn_scale(96);
7075 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
7077 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
7078 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
7079 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
7080 } else if (tp->version == RTL_VER_05) {
7081 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
7082 ocp_data &= ~ECM_ALDPS;
7083 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
7085 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
7086 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
7087 ocp_data &= ~DYNAMIC_BURST;
7089 ocp_data |= DYNAMIC_BURST;
7090 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
7091 } else if (tp->version == RTL_VER_06) {
7092 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
7093 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
7094 ocp_data &= ~DYNAMIC_BURST;
7096 ocp_data |= DYNAMIC_BURST;
7097 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
7099 r8153_queue_wake(tp, false);
7101 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7102 if (rtl8152_get_speed(tp) & LINK_STATUS)
7103 ocp_data |= CUR_LINK_OK;
7105 ocp_data &= ~CUR_LINK_OK;
7106 ocp_data |= POLL_LINK_CHG;
7107 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7110 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
7111 ocp_data |= EP4_FULL_FC;
7112 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
7114 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
7115 ocp_data &= ~TIMER11_EN;
7116 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
7118 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
7119 ocp_data &= ~LED_MODE_MASK;
7120 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
7122 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
7123 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
7124 ocp_data |= LPM_TIMER_500MS;
7126 ocp_data |= LPM_TIMER_500US;
7127 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
7129 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
7130 ocp_data &= ~SEN_VAL_MASK;
7131 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
7132 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
7134 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
7136 r8153_power_cut_en(tp, false);
7137 rtl_runtime_suspend_enable(tp, false);
7138 r8153_mac_clk_speed_down(tp, false);
7139 r8153_u1u2en(tp, true);
7140 usb_enable_lpm(tp->udev);
7142 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
7143 ocp_data |= LANWAKE_CLR_EN;
7144 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
7146 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
7147 ocp_data &= ~LANWAKE_PIN;
7148 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
7150 /* rx aggregation */
7151 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7152 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7153 if (tp->dell_tb_rx_agg_bug)
7154 ocp_data |= RX_AGG_DISABLE;
7156 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7158 rtl_tally_reset(tp);
7160 switch (tp->udev->speed) {
7161 case USB_SPEED_SUPER:
7162 case USB_SPEED_SUPER_PLUS:
7163 tp->coalesce = COALESCE_SUPER;
7165 case USB_SPEED_HIGH:
7166 tp->coalesce = COALESCE_HIGH;
7169 tp->coalesce = COALESCE_SLOW;
7174 static void r8153b_init(struct r8152 *tp)
7180 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7183 r8153b_u1u2en(tp, false);
7185 for (i = 0; i < 500; i++) {
7186 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7191 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7195 data = r8153_phy_status(tp, 0);
7197 data = r8152_mdio_read(tp, MII_BMCR);
7198 if (data & BMCR_PDOWN) {
7199 data &= ~BMCR_PDOWN;
7200 r8152_mdio_write(tp, MII_BMCR, data);
7203 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7205 r8153_u2p3en(tp, false);
7207 /* MSC timer = 0xfff * 8ms = 32760 ms */
7208 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7210 r8153b_power_cut_en(tp, false);
7211 r8153b_ups_en(tp, false);
7212 r8153_queue_wake(tp, false);
7213 rtl_runtime_suspend_enable(tp, false);
7215 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7216 if (rtl8152_get_speed(tp) & LINK_STATUS)
7217 ocp_data |= CUR_LINK_OK;
7219 ocp_data &= ~CUR_LINK_OK;
7220 ocp_data |= POLL_LINK_CHG;
7221 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7223 if (tp->udev->speed >= USB_SPEED_SUPER)
7224 r8153b_u1u2en(tp, true);
7226 usb_enable_lpm(tp->udev);
7228 /* MAC clock speed down */
7229 r8153_mac_clk_speed_down(tp, true);
7231 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7232 ocp_data &= ~PLA_MCU_SPDWN_EN;
7233 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
7235 if (tp->version == RTL_VER_09) {
7236 /* Disable Test IO for 32QFN */
7237 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
7238 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7239 ocp_data |= TEST_IO_OFF;
7240 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7244 set_bit(GREEN_ETHERNET, &tp->flags);
7246 /* rx aggregation */
7247 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7248 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7249 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7251 rtl_tally_reset(tp);
7253 tp->coalesce = 15000; /* 15 us */
7256 static void r8153c_init(struct r8152 *tp)
7262 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7265 r8153b_u1u2en(tp, false);
7267 /* Disable spi_en */
7268 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
7269 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
7270 ocp_data &= ~BIT(3);
7271 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
7272 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);
7274 ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);
7276 for (i = 0; i < 500; i++) {
7277 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7282 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7286 data = r8153_phy_status(tp, 0);
7288 data = r8152_mdio_read(tp, MII_BMCR);
7289 if (data & BMCR_PDOWN) {
7290 data &= ~BMCR_PDOWN;
7291 r8152_mdio_write(tp, MII_BMCR, data);
7294 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7296 r8153_u2p3en(tp, false);
7298 /* MSC timer = 0xfff * 8ms = 32760 ms */
7299 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7301 r8153b_power_cut_en(tp, false);
7302 r8153c_ups_en(tp, false);
7303 r8153_queue_wake(tp, false);
7304 rtl_runtime_suspend_enable(tp, false);
7306 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7307 if (rtl8152_get_speed(tp) & LINK_STATUS)
7308 ocp_data |= CUR_LINK_OK;
7310 ocp_data &= ~CUR_LINK_OK;
7312 ocp_data |= POLL_LINK_CHG;
7313 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7315 r8153b_u1u2en(tp, true);
7317 usb_enable_lpm(tp->udev);
7319 /* MAC clock speed down */
7320 r8153_mac_clk_speed_down(tp, true);
7322 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
7323 ocp_data &= ~BIT(7);
7324 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
7326 set_bit(GREEN_ETHERNET, &tp->flags);
7328 /* rx aggregation */
7329 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7330 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7331 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7333 rtl_tally_reset(tp);
7335 tp->coalesce = 15000; /* 15 us */
7338 static void r8156_hw_phy_cfg(struct r8152 *tp)
7343 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7344 if (ocp_data & PCUT_STATUS) {
7345 ocp_data &= ~PCUT_STATUS;
7346 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7349 data = r8153_phy_status(tp, 0);
7351 case PHY_STAT_EXT_INIT:
7352 rtl8152_apply_firmware(tp, true);
7354 data = ocp_reg_read(tp, 0xa468);
7355 data &= ~(BIT(3) | BIT(1));
7356 ocp_reg_write(tp, 0xa468, data);
7358 case PHY_STAT_LAN_ON:
7359 case PHY_STAT_PWRDN:
7361 rtl8152_apply_firmware(tp, false);
7365 /* disable ALDPS before updating the PHY parameters */
7366 r8153_aldps_en(tp, false);
7368 /* disable EEE before updating the PHY parameters */
7369 rtl_eee_enable(tp, false);
7371 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7372 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7374 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7375 ocp_data |= PFM_PWM_SWITCH;
7376 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7378 switch (tp->version) {
7380 data = ocp_reg_read(tp, 0xad40);
7382 data |= BIT(7) | BIT(2);
7383 ocp_reg_write(tp, 0xad40, data);
7385 data = ocp_reg_read(tp, 0xad4e);
7387 ocp_reg_write(tp, 0xad4e, data);
7388 data = ocp_reg_read(tp, 0xad16);
7391 ocp_reg_write(tp, 0xad16, data);
7392 data = ocp_reg_read(tp, 0xad32);
7395 ocp_reg_write(tp, 0xad32, data);
7396 data = ocp_reg_read(tp, 0xac08);
7397 data &= ~(BIT(12) | BIT(8));
7398 ocp_reg_write(tp, 0xac08, data);
7399 data = ocp_reg_read(tp, 0xac8a);
7400 data |= BIT(12) | BIT(13) | BIT(14);
7402 ocp_reg_write(tp, 0xac8a, data);
7403 data = ocp_reg_read(tp, 0xad18);
7405 ocp_reg_write(tp, 0xad18, data);
7406 data = ocp_reg_read(tp, 0xad1a);
7408 ocp_reg_write(tp, 0xad1a, data);
7409 data = ocp_reg_read(tp, 0xad1c);
7411 ocp_reg_write(tp, 0xad1c, data);
7413 data = sram_read(tp, 0x80ea);
7416 sram_write(tp, 0x80ea, data);
7417 data = sram_read(tp, 0x80eb);
7420 sram_write(tp, 0x80eb, data);
7421 data = sram_read(tp, 0x80f8);
7424 sram_write(tp, 0x80f8, data);
7425 data = sram_read(tp, 0x80f1);
7428 sram_write(tp, 0x80f1, data);
7430 data = sram_read(tp, 0x80fe);
7433 sram_write(tp, 0x80fe, data);
7434 data = sram_read(tp, 0x8102);
7437 sram_write(tp, 0x8102, data);
7438 data = sram_read(tp, 0x8015);
7441 sram_write(tp, 0x8015, data);
7442 data = sram_read(tp, 0x8100);
7445 sram_write(tp, 0x8100, data);
7446 data = sram_read(tp, 0x8014);
7449 sram_write(tp, 0x8014, data);
7450 data = sram_read(tp, 0x8016);
7453 sram_write(tp, 0x8016, data);
7454 data = sram_read(tp, 0x80dc);
7457 sram_write(tp, 0x80dc, data);
7458 data = sram_read(tp, 0x80df);
7460 sram_write(tp, 0x80df, data);
7461 data = sram_read(tp, 0x80e1);
7463 sram_write(tp, 0x80e1, data);
7465 data = ocp_reg_read(tp, 0xbf06);
7468 ocp_reg_write(tp, 0xbf06, data);
7470 sram_write(tp, 0x819f, 0xddb6);
7472 ocp_reg_write(tp, 0xbc34, 0x5555);
7473 data = ocp_reg_read(tp, 0xbf0a);
7476 ocp_reg_write(tp, 0xbf0a, data);
7478 data = ocp_reg_read(tp, 0xbd2c);
7480 ocp_reg_write(tp, 0xbd2c, data);
7483 data = ocp_reg_read(tp, 0xad16);
7485 ocp_reg_write(tp, 0xad16, data);
7486 data = ocp_reg_read(tp, 0xad32);
7489 ocp_reg_write(tp, 0xad32, data);
7490 data = ocp_reg_read(tp, 0xac08);
7491 data &= ~(BIT(12) | BIT(8));
7492 ocp_reg_write(tp, 0xac08, data);
7493 data = ocp_reg_read(tp, 0xacc0);
7496 ocp_reg_write(tp, 0xacc0, data);
7497 data = ocp_reg_read(tp, 0xad40);
7499 data |= BIT(6) | BIT(2);
7500 ocp_reg_write(tp, 0xad40, data);
7501 data = ocp_reg_read(tp, 0xac14);
7503 ocp_reg_write(tp, 0xac14, data);
7504 data = ocp_reg_read(tp, 0xac80);
7505 data &= ~(BIT(8) | BIT(9));
7506 ocp_reg_write(tp, 0xac80, data);
7507 data = ocp_reg_read(tp, 0xac5e);
7510 ocp_reg_write(tp, 0xac5e, data);
7511 ocp_reg_write(tp, 0xad4c, 0x00a8);
7512 ocp_reg_write(tp, 0xac5c, 0x01ff);
7513 data = ocp_reg_read(tp, 0xac8a);
7515 data |= BIT(4) | BIT(5);
7516 ocp_reg_write(tp, 0xac8a, data);
7517 ocp_reg_write(tp, 0xb87c, 0x8157);
7518 data = ocp_reg_read(tp, 0xb87e);
7521 ocp_reg_write(tp, 0xb87e, data);
7522 ocp_reg_write(tp, 0xb87c, 0x8159);
7523 data = ocp_reg_read(tp, 0xb87e);
7526 ocp_reg_write(tp, 0xb87e, data);
7529 ocp_reg_write(tp, 0xb87c, 0x80a2);
7530 ocp_reg_write(tp, 0xb87e, 0x0153);
7531 ocp_reg_write(tp, 0xb87c, 0x809c);
7532 ocp_reg_write(tp, 0xb87e, 0x0153);
7535 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
7537 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7538 ocp_data |= EN_XG_LIP | EN_G_LIP;
7539 ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7541 sram_write(tp, 0x8257, 0x020f); /* XG PLL */
7542 sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */
7544 if (rtl_phy_patch_request(tp, true, true))
7548 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7549 ocp_data |= EEE_SPDWN_EN;
7550 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7552 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7553 data &= ~(EN_EEE_100 | EN_EEE_1000);
7554 data |= EN_10M_CLKDIV;
7555 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7556 tp->ups_info._10m_ckdiv = true;
7557 tp->ups_info.eee_plloff_100 = false;
7558 tp->ups_info.eee_plloff_giga = false;
7560 data = ocp_reg_read(tp, OCP_POWER_CFG);
7561 data &= ~EEE_CLKDIV_EN;
7562 ocp_reg_write(tp, OCP_POWER_CFG, data);
7563 tp->ups_info.eee_ckdiv = false;
7565 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
7566 ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
7567 tp->ups_info._250m_ckdiv = false;
7569 rtl_phy_patch_request(tp, false, true);
7571 /* enable ADC Ibias Cal */
7572 data = ocp_reg_read(tp, 0xd068);
7574 ocp_reg_write(tp, 0xd068, data);
7576 /* enable Thermal Sensor */
7577 data = sram_read(tp, 0x81a2);
7579 sram_write(tp, 0x81a2, data);
7580 data = ocp_reg_read(tp, 0xb54c);
7583 ocp_reg_write(tp, 0xb54c, data);
7585 /* Nway 2.5G Lite */
7586 data = ocp_reg_read(tp, 0xa454);
7588 ocp_reg_write(tp, 0xa454, data);
7590 /* CS DSP solution */
7591 data = ocp_reg_read(tp, OCP_10GBT_CTRL);
7592 data |= RTL_ADV2_5G_F_R;
7593 ocp_reg_write(tp, OCP_10GBT_CTRL, data);
7594 data = ocp_reg_read(tp, 0xad4e);
7596 ocp_reg_write(tp, 0xad4e, data);
7597 data = ocp_reg_read(tp, 0xa86a);
7599 ocp_reg_write(tp, 0xa86a, data);
7602 if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
7603 (ocp_reg_read(tp, 0xd068) & BIT(1))) {
7606 data = ocp_reg_read(tp, 0xd068);
7608 data |= 0x1; /* p0 */
7609 ocp_reg_write(tp, 0xd068, data);
7610 swap_a = ocp_reg_read(tp, 0xd06a);
7612 data |= 0x18; /* p3 */
7613 ocp_reg_write(tp, 0xd068, data);
7614 swap_b = ocp_reg_read(tp, 0xd06a);
7615 data &= ~0x18; /* p0 */
7616 ocp_reg_write(tp, 0xd068, data);
7617 ocp_reg_write(tp, 0xd06a,
7618 (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7619 data |= 0x18; /* p3 */
7620 ocp_reg_write(tp, 0xd068, data);
7621 ocp_reg_write(tp, 0xd06a,
7622 (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7624 data |= 0x08; /* p1 */
7625 ocp_reg_write(tp, 0xd068, data);
7626 swap_a = ocp_reg_read(tp, 0xd06a);
7628 data |= 0x10; /* p2 */
7629 ocp_reg_write(tp, 0xd068, data);
7630 swap_b = ocp_reg_read(tp, 0xd06a);
7632 data |= 0x08; /* p1 */
7633 ocp_reg_write(tp, 0xd068, data);
7634 ocp_reg_write(tp, 0xd06a,
7635 (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7637 data |= 0x10; /* p2 */
7638 ocp_reg_write(tp, 0xd068, data);
7639 ocp_reg_write(tp, 0xd06a,
7640 (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7641 swap_a = ocp_reg_read(tp, 0xbd5a);
7642 swap_b = ocp_reg_read(tp, 0xbd5c);
7643 ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) |
7644 ((swap_b & 0x1f) << 8) |
7645 ((swap_b >> 8) & 0x1f));
7646 ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) |
7647 ((swap_a & 0x1f) << 8) |
7648 ((swap_a >> 8) & 0x1f));
7649 swap_a = ocp_reg_read(tp, 0xbc18);
7650 swap_b = ocp_reg_read(tp, 0xbc1a);
7651 ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) |
7652 ((swap_b & 0x1f) << 8) |
7653 ((swap_b >> 8) & 0x1f));
7654 ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) |
7655 ((swap_a & 0x1f) << 8) |
7656 ((swap_a >> 8) & 0x1f));
7659 /* Notify the MAC when the speed is changed to force mode. */
7660 data = ocp_reg_read(tp, OCP_INTR_EN);
7661 data |= INTR_SPEED_FORCE;
7662 ocp_reg_write(tp, OCP_INTR_EN, data);
7668 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7670 data = ocp_reg_read(tp, 0xa428);
7672 ocp_reg_write(tp, 0xa428, data);
7673 data = ocp_reg_read(tp, 0xa5ea);
7675 ocp_reg_write(tp, 0xa5ea, data);
7676 tp->ups_info.lite_mode = 0;
7679 rtl_eee_enable(tp, true);
7681 r8153_aldps_en(tp, true);
7682 r8152b_enable_fc(tp);
7683 r8153_u2p3en(tp, true);
7685 set_bit(PHY_RESET, &tp->flags);
7688 static void r8156b_hw_phy_cfg(struct r8152 *tp)
7693 switch (tp->version) {
7695 ocp_reg_write(tp, 0xbf86, 0x9000);
7696 data = ocp_reg_read(tp, 0xc402);
7698 ocp_reg_write(tp, 0xc402, data);
7700 ocp_reg_write(tp, 0xc402, data);
7701 ocp_reg_write(tp, 0xbd86, 0x1010);
7702 ocp_reg_write(tp, 0xbd88, 0x1010);
7703 data = ocp_reg_read(tp, 0xbd4e);
7704 data &= ~(BIT(10) | BIT(11));
7706 ocp_reg_write(tp, 0xbd4e, data);
7707 data = ocp_reg_read(tp, 0xbf46);
7710 ocp_reg_write(tp, 0xbf46, data);
7714 r8156b_wait_loading_flash(tp);
7720 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7721 if (ocp_data & PCUT_STATUS) {
7722 ocp_data &= ~PCUT_STATUS;
7723 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7726 data = r8153_phy_status(tp, 0);
7728 case PHY_STAT_EXT_INIT:
7729 rtl8152_apply_firmware(tp, true);
7731 data = ocp_reg_read(tp, 0xa466);
7733 ocp_reg_write(tp, 0xa466, data);
7735 data = ocp_reg_read(tp, 0xa468);
7736 data &= ~(BIT(3) | BIT(1));
7737 ocp_reg_write(tp, 0xa468, data);
7739 case PHY_STAT_LAN_ON:
7740 case PHY_STAT_PWRDN:
7742 rtl8152_apply_firmware(tp, false);
7746 data = r8152_mdio_read(tp, MII_BMCR);
7747 if (data & BMCR_PDOWN) {
7748 data &= ~BMCR_PDOWN;
7749 r8152_mdio_write(tp, MII_BMCR, data);
7752 /* disable ALDPS before updating the PHY parameters */
7753 r8153_aldps_en(tp, false);
7755 /* disable EEE before updating the PHY parameters */
7756 rtl_eee_enable(tp, false);
7758 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7759 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7761 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7762 ocp_data |= PFM_PWM_SWITCH;
7763 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7765 switch (tp->version) {
7767 data = ocp_reg_read(tp, 0xbc08);
7768 data |= BIT(3) | BIT(2);
7769 ocp_reg_write(tp, 0xbc08, data);
7771 data = sram_read(tp, 0x8fff);
7774 sram_write(tp, 0x8fff, data);
7776 data = ocp_reg_read(tp, 0xacda);
7778 ocp_reg_write(tp, 0xacda, data);
7779 data = ocp_reg_read(tp, 0xacde);
7781 ocp_reg_write(tp, 0xacde, data);
7782 ocp_reg_write(tp, 0xac8c, 0x0ffc);
7783 ocp_reg_write(tp, 0xac46, 0xb7b4);
7784 ocp_reg_write(tp, 0xac50, 0x0fbc);
7785 ocp_reg_write(tp, 0xac3c, 0x9240);
7786 ocp_reg_write(tp, 0xac4e, 0x0db4);
7787 ocp_reg_write(tp, 0xacc6, 0x0707);
7788 ocp_reg_write(tp, 0xacc8, 0xa0d3);
7789 ocp_reg_write(tp, 0xad08, 0x0007);
7791 ocp_reg_write(tp, 0xb87c, 0x8560);
7792 ocp_reg_write(tp, 0xb87e, 0x19cc);
7793 ocp_reg_write(tp, 0xb87c, 0x8562);
7794 ocp_reg_write(tp, 0xb87e, 0x19cc);
7795 ocp_reg_write(tp, 0xb87c, 0x8564);
7796 ocp_reg_write(tp, 0xb87e, 0x19cc);
7797 ocp_reg_write(tp, 0xb87c, 0x8566);
7798 ocp_reg_write(tp, 0xb87e, 0x147d);
7799 ocp_reg_write(tp, 0xb87c, 0x8568);
7800 ocp_reg_write(tp, 0xb87e, 0x147d);
7801 ocp_reg_write(tp, 0xb87c, 0x856a);
7802 ocp_reg_write(tp, 0xb87e, 0x147d);
7803 ocp_reg_write(tp, 0xb87c, 0x8ffe);
7804 ocp_reg_write(tp, 0xb87e, 0x0907);
7805 ocp_reg_write(tp, 0xb87c, 0x80d6);
7806 ocp_reg_write(tp, 0xb87e, 0x2801);
7807 ocp_reg_write(tp, 0xb87c, 0x80f2);
7808 ocp_reg_write(tp, 0xb87e, 0x2801);
7809 ocp_reg_write(tp, 0xb87c, 0x80f4);
7810 ocp_reg_write(tp, 0xb87e, 0x6077);
7811 ocp_reg_write(tp, 0xb506, 0x01e7);
7813 ocp_reg_write(tp, 0xb87c, 0x8013);
7814 ocp_reg_write(tp, 0xb87e, 0x0700);
7815 ocp_reg_write(tp, 0xb87c, 0x8fb9);
7816 ocp_reg_write(tp, 0xb87e, 0x2801);
7817 ocp_reg_write(tp, 0xb87c, 0x8fba);
7818 ocp_reg_write(tp, 0xb87e, 0x0100);
7819 ocp_reg_write(tp, 0xb87c, 0x8fbc);
7820 ocp_reg_write(tp, 0xb87e, 0x1900);
7821 ocp_reg_write(tp, 0xb87c, 0x8fbe);
7822 ocp_reg_write(tp, 0xb87e, 0xe100);
7823 ocp_reg_write(tp, 0xb87c, 0x8fc0);
7824 ocp_reg_write(tp, 0xb87e, 0x0800);
7825 ocp_reg_write(tp, 0xb87c, 0x8fc2);
7826 ocp_reg_write(tp, 0xb87e, 0xe500);
7827 ocp_reg_write(tp, 0xb87c, 0x8fc4);
7828 ocp_reg_write(tp, 0xb87e, 0x0f00);
7829 ocp_reg_write(tp, 0xb87c, 0x8fc6);
7830 ocp_reg_write(tp, 0xb87e, 0xf100);
7831 ocp_reg_write(tp, 0xb87c, 0x8fc8);
7832 ocp_reg_write(tp, 0xb87e, 0x0400);
7833 ocp_reg_write(tp, 0xb87c, 0x8fca);
7834 ocp_reg_write(tp, 0xb87e, 0xf300);
7835 ocp_reg_write(tp, 0xb87c, 0x8fcc);
7836 ocp_reg_write(tp, 0xb87e, 0xfd00);
7837 ocp_reg_write(tp, 0xb87c, 0x8fce);
7838 ocp_reg_write(tp, 0xb87e, 0xff00);
7839 ocp_reg_write(tp, 0xb87c, 0x8fd0);
7840 ocp_reg_write(tp, 0xb87e, 0xfb00);
7841 ocp_reg_write(tp, 0xb87c, 0x8fd2);
7842 ocp_reg_write(tp, 0xb87e, 0x0100);
7843 ocp_reg_write(tp, 0xb87c, 0x8fd4);
7844 ocp_reg_write(tp, 0xb87e, 0xf400);
7845 ocp_reg_write(tp, 0xb87c, 0x8fd6);
7846 ocp_reg_write(tp, 0xb87e, 0xff00);
7847 ocp_reg_write(tp, 0xb87c, 0x8fd8);
7848 ocp_reg_write(tp, 0xb87e, 0xf600);
7850 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7851 ocp_data |= EN_XG_LIP | EN_G_LIP;
7852 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7853 ocp_reg_write(tp, 0xb87c, 0x813d);
7854 ocp_reg_write(tp, 0xb87e, 0x390e);
7855 ocp_reg_write(tp, 0xb87c, 0x814f);
7856 ocp_reg_write(tp, 0xb87e, 0x790e);
7857 ocp_reg_write(tp, 0xb87c, 0x80b0);
7858 ocp_reg_write(tp, 0xb87e, 0x0f31);
7859 data = ocp_reg_read(tp, 0xbf4c);
7861 ocp_reg_write(tp, 0xbf4c, data);
7862 data = ocp_reg_read(tp, 0xbcca);
7863 data |= BIT(9) | BIT(8);
7864 ocp_reg_write(tp, 0xbcca, data);
7865 ocp_reg_write(tp, 0xb87c, 0x8141);
7866 ocp_reg_write(tp, 0xb87e, 0x320e);
7867 ocp_reg_write(tp, 0xb87c, 0x8153);
7868 ocp_reg_write(tp, 0xb87e, 0x720e);
7869 ocp_reg_write(tp, 0xb87c, 0x8529);
7870 ocp_reg_write(tp, 0xb87e, 0x050e);
7871 data = ocp_reg_read(tp, OCP_EEE_CFG);
7872 data &= ~CTAP_SHORT_EN;
7873 ocp_reg_write(tp, OCP_EEE_CFG, data);
7875 sram_write(tp, 0x816c, 0xc4a0);
7876 sram_write(tp, 0x8170, 0xc4a0);
7877 sram_write(tp, 0x8174, 0x04a0);
7878 sram_write(tp, 0x8178, 0x04a0);
7879 sram_write(tp, 0x817c, 0x0719);
7880 sram_write(tp, 0x8ff4, 0x0400);
7881 sram_write(tp, 0x8ff1, 0x0404);
7883 ocp_reg_write(tp, 0xbf4a, 0x001b);
7884 ocp_reg_write(tp, 0xb87c, 0x8033);
7885 ocp_reg_write(tp, 0xb87e, 0x7c13);
7886 ocp_reg_write(tp, 0xb87c, 0x8037);
7887 ocp_reg_write(tp, 0xb87e, 0x7c13);
7888 ocp_reg_write(tp, 0xb87c, 0x803b);
7889 ocp_reg_write(tp, 0xb87e, 0xfc32);
7890 ocp_reg_write(tp, 0xb87c, 0x803f);
7891 ocp_reg_write(tp, 0xb87e, 0x7c13);
7892 ocp_reg_write(tp, 0xb87c, 0x8043);
7893 ocp_reg_write(tp, 0xb87e, 0x7c13);
7894 ocp_reg_write(tp, 0xb87c, 0x8047);
7895 ocp_reg_write(tp, 0xb87e, 0x7c13);
7897 ocp_reg_write(tp, 0xb87c, 0x8145);
7898 ocp_reg_write(tp, 0xb87e, 0x370e);
7899 ocp_reg_write(tp, 0xb87c, 0x8157);
7900 ocp_reg_write(tp, 0xb87e, 0x770e);
7901 ocp_reg_write(tp, 0xb87c, 0x8169);
7902 ocp_reg_write(tp, 0xb87e, 0x0d0a);
7903 ocp_reg_write(tp, 0xb87c, 0x817b);
7904 ocp_reg_write(tp, 0xb87e, 0x1d0a);
7906 data = sram_read(tp, 0x8217);
7909 sram_write(tp, 0x8217, data);
7910 data = sram_read(tp, 0x821a);
7913 sram_write(tp, 0x821a, data);
7914 sram_write(tp, 0x80da, 0x0403);
7915 data = sram_read(tp, 0x80dc);
7918 sram_write(tp, 0x80dc, data);
7919 sram_write(tp, 0x80b3, 0x0384);
7920 sram_write(tp, 0x80b7, 0x2007);
7921 data = sram_read(tp, 0x80ba);
7924 sram_write(tp, 0x80ba, data);
7925 sram_write(tp, 0x80b5, 0xf009);
7926 data = sram_read(tp, 0x80bd);
7929 sram_write(tp, 0x80bd, data);
7930 sram_write(tp, 0x80c7, 0xf083);
7931 sram_write(tp, 0x80dd, 0x03f0);
7932 data = sram_read(tp, 0x80df);
7935 sram_write(tp, 0x80df, data);
7936 sram_write(tp, 0x80cb, 0x2007);
7937 data = sram_read(tp, 0x80ce);
7940 sram_write(tp, 0x80ce, data);
7941 sram_write(tp, 0x80c9, 0x8009);
7942 data = sram_read(tp, 0x80d1);
7945 sram_write(tp, 0x80d1, data);
7946 sram_write(tp, 0x80a3, 0x200a);
7947 sram_write(tp, 0x80a5, 0xf0ad);
7948 sram_write(tp, 0x809f, 0x6073);
7949 sram_write(tp, 0x80a1, 0x000b);
7950 data = sram_read(tp, 0x80a9);
7953 sram_write(tp, 0x80a9, data);
7955 if (rtl_phy_patch_request(tp, true, true))
7958 data = ocp_reg_read(tp, 0xb896);
7960 ocp_reg_write(tp, 0xb896, data);
7961 data = ocp_reg_read(tp, 0xb892);
7963 ocp_reg_write(tp, 0xb892, data);
7964 ocp_reg_write(tp, 0xb88e, 0xc23e);
7965 ocp_reg_write(tp, 0xb890, 0x0000);
7966 ocp_reg_write(tp, 0xb88e, 0xc240);
7967 ocp_reg_write(tp, 0xb890, 0x0103);
7968 ocp_reg_write(tp, 0xb88e, 0xc242);
7969 ocp_reg_write(tp, 0xb890, 0x0507);
7970 ocp_reg_write(tp, 0xb88e, 0xc244);
7971 ocp_reg_write(tp, 0xb890, 0x090b);
7972 ocp_reg_write(tp, 0xb88e, 0xc246);
7973 ocp_reg_write(tp, 0xb890, 0x0c0e);
7974 ocp_reg_write(tp, 0xb88e, 0xc248);
7975 ocp_reg_write(tp, 0xb890, 0x1012);
7976 ocp_reg_write(tp, 0xb88e, 0xc24a);
7977 ocp_reg_write(tp, 0xb890, 0x1416);
7978 data = ocp_reg_read(tp, 0xb896);
7980 ocp_reg_write(tp, 0xb896, data);
7982 rtl_phy_patch_request(tp, false, true);
7984 data = ocp_reg_read(tp, 0xa86a);
7986 ocp_reg_write(tp, 0xa86a, data);
7987 data = ocp_reg_read(tp, 0xa6f0);
7989 ocp_reg_write(tp, 0xa6f0, data);
7991 ocp_reg_write(tp, 0xbfa0, 0xd70d);
7992 ocp_reg_write(tp, 0xbfa2, 0x4100);
7993 ocp_reg_write(tp, 0xbfa4, 0xe868);
7994 ocp_reg_write(tp, 0xbfa6, 0xdc59);
7995 ocp_reg_write(tp, 0xb54c, 0x3c18);
7996 data = ocp_reg_read(tp, 0xbfa4);
7998 ocp_reg_write(tp, 0xbfa4, data);
7999 data = sram_read(tp, 0x817d);
8001 sram_write(tp, 0x817d, data);
8005 data = ocp_reg_read(tp, 0xac46);
8008 ocp_reg_write(tp, 0xac46, data);
8009 data = ocp_reg_read(tp, 0xad30);
8012 ocp_reg_write(tp, 0xad30, data);
8016 ocp_reg_write(tp, 0xb87c, 0x80f5);
8017 ocp_reg_write(tp, 0xb87e, 0x760e);
8018 ocp_reg_write(tp, 0xb87c, 0x8107);
8019 ocp_reg_write(tp, 0xb87e, 0x360e);
8020 ocp_reg_write(tp, 0xb87c, 0x8551);
8021 data = ocp_reg_read(tp, 0xb87e);
8024 ocp_reg_write(tp, 0xb87e, data);
8026 /* ADC_PGA parameter */
8027 data = ocp_reg_read(tp, 0xbf00);
8030 ocp_reg_write(tp, 0xbf00, data);
8031 data = ocp_reg_read(tp, 0xbf46);
8034 ocp_reg_write(tp, 0xbf46, data);
8036 /* Green Table-PGA, 1G full viterbi */
8037 sram_write(tp, 0x8044, 0x2417);
8038 sram_write(tp, 0x804a, 0x2417);
8039 sram_write(tp, 0x8050, 0x2417);
8040 sram_write(tp, 0x8056, 0x2417);
8041 sram_write(tp, 0x805c, 0x2417);
8042 sram_write(tp, 0x8062, 0x2417);
8043 sram_write(tp, 0x8068, 0x2417);
8044 sram_write(tp, 0x806e, 0x2417);
8045 sram_write(tp, 0x8074, 0x2417);
8046 sram_write(tp, 0x807a, 0x2417);
8049 data = ocp_reg_read(tp, 0xbf84);
8052 ocp_reg_write(tp, 0xbf84, data);
8058 /* Notify the MAC when the speed is changed to force mode. */
8059 data = ocp_reg_read(tp, OCP_INTR_EN);
8060 data |= INTR_SPEED_FORCE;
8061 ocp_reg_write(tp, OCP_INTR_EN, data);
8063 if (rtl_phy_patch_request(tp, true, true))
8066 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
8067 ocp_data |= EEE_SPDWN_EN;
8068 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
8070 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
8071 data &= ~(EN_EEE_100 | EN_EEE_1000);
8072 data |= EN_10M_CLKDIV;
8073 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
8074 tp->ups_info._10m_ckdiv = true;
8075 tp->ups_info.eee_plloff_100 = false;
8076 tp->ups_info.eee_plloff_giga = false;
8078 data = ocp_reg_read(tp, OCP_POWER_CFG);
8079 data &= ~EEE_CLKDIV_EN;
8080 ocp_reg_write(tp, OCP_POWER_CFG, data);
8081 tp->ups_info.eee_ckdiv = false;
8083 rtl_phy_patch_request(tp, false, true);
8085 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
8087 data = ocp_reg_read(tp, 0xa428);
8089 ocp_reg_write(tp, 0xa428, data);
8090 data = ocp_reg_read(tp, 0xa5ea);
8092 ocp_reg_write(tp, 0xa5ea, data);
8093 tp->ups_info.lite_mode = 0;
8096 rtl_eee_enable(tp, true);
8098 r8153_aldps_en(tp, true);
8099 r8152b_enable_fc(tp);
8100 r8153_u2p3en(tp, true);
8102 set_bit(PHY_RESET, &tp->flags);
8105 static void r8156_init(struct r8152 *tp)
8111 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8114 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8115 ocp_data &= ~EN_ALL_SPEED;
8116 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
8118 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
8120 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8121 ocp_data |= BYPASS_MAC_RESET;
8122 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
8124 r8153b_u1u2en(tp, false);
8126 for (i = 0; i < 500; i++) {
8127 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8132 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8136 data = r8153_phy_status(tp, 0);
8137 if (data == PHY_STAT_EXT_INIT) {
8138 data = ocp_reg_read(tp, 0xa468);
8139 data &= ~(BIT(3) | BIT(1));
8140 ocp_reg_write(tp, 0xa468, data);
8143 data = r8152_mdio_read(tp, MII_BMCR);
8144 if (data & BMCR_PDOWN) {
8145 data &= ~BMCR_PDOWN;
8146 r8152_mdio_write(tp, MII_BMCR, data);
8149 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8150 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
8152 r8153_u2p3en(tp, false);
8154 /* MSC timer = 0xfff * 8ms = 32760 ms */
8155 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
8157 /* U1/U2/L1 idle timer. 500 us */
8158 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
8160 r8153b_power_cut_en(tp, false);
8161 r8156_ups_en(tp, false);
8162 r8153_queue_wake(tp, false);
8163 rtl_runtime_suspend_enable(tp, false);
8165 if (tp->udev->speed >= USB_SPEED_SUPER)
8166 r8153b_u1u2en(tp, true);
8168 usb_enable_lpm(tp->udev);
8170 r8156_mac_clk_spd(tp, true);
8172 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8173 ocp_data &= ~PLA_MCU_SPDWN_EN;
8174 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8176 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8177 if (rtl8152_get_speed(tp) & LINK_STATUS)
8178 ocp_data |= CUR_LINK_OK;
8180 ocp_data &= ~CUR_LINK_OK;
8181 ocp_data |= POLL_LINK_CHG;
8182 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8184 set_bit(GREEN_ETHERNET, &tp->flags);
8186 /* rx aggregation */
8187 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8188 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8189 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8191 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
8192 ocp_data |= ACT_ODMA;
8193 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
8195 r8156_mdio_force_mode(tp);
8196 rtl_tally_reset(tp);
8198 tp->coalesce = 15000; /* 15 us */
8201 static void r8156b_init(struct r8152 *tp)
8207 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8210 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8211 ocp_data &= ~EN_ALL_SPEED;
8212 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
8214 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
8216 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8217 ocp_data |= BYPASS_MAC_RESET;
8218 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
8220 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
8221 ocp_data |= RX_DETECT8;
8222 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
8224 r8153b_u1u2en(tp, false);
8226 switch (tp->version) {
8229 r8156b_wait_loading_flash(tp);
8235 for (i = 0; i < 500; i++) {
8236 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8241 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8245 data = r8153_phy_status(tp, 0);
8246 if (data == PHY_STAT_EXT_INIT) {
8247 data = ocp_reg_read(tp, 0xa468);
8248 data &= ~(BIT(3) | BIT(1));
8249 ocp_reg_write(tp, 0xa468, data);
8251 data = ocp_reg_read(tp, 0xa466);
8253 ocp_reg_write(tp, 0xa466, data);
8256 data = r8152_mdio_read(tp, MII_BMCR);
8257 if (data & BMCR_PDOWN) {
8258 data &= ~BMCR_PDOWN;
8259 r8152_mdio_write(tp, MII_BMCR, data);
8262 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8264 r8153_u2p3en(tp, false);
8266 /* MSC timer = 0xfff * 8ms = 32760 ms */
8267 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
8269 /* U1/U2/L1 idle timer. 500 us */
8270 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
8272 r8153b_power_cut_en(tp, false);
8273 r8156_ups_en(tp, false);
8274 r8153_queue_wake(tp, false);
8275 rtl_runtime_suspend_enable(tp, false);
8277 if (tp->udev->speed >= USB_SPEED_SUPER)
8278 r8153b_u1u2en(tp, true);
8280 usb_enable_lpm(tp->udev);
8282 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
8283 ocp_data &= ~SLOT_EN;
8284 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8286 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
8287 ocp_data |= FLOW_CTRL_EN;
8288 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
8290 /* enable fc timer and set timer to 600 ms. */
8291 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
8292 CTRL_TIMER_EN | (600 / 8));
8294 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
8295 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
8296 ocp_data |= FLOW_CTRL_PATCH_2;
8297 ocp_data &= ~AUTO_SPEEDUP;
8298 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
8300 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
8301 ocp_data |= FC_PATCH_TASK;
8302 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
8304 r8156_mac_clk_spd(tp, true);
8306 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8307 ocp_data &= ~PLA_MCU_SPDWN_EN;
8308 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8310 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8311 if (rtl8152_get_speed(tp) & LINK_STATUS)
8312 ocp_data |= CUR_LINK_OK;
8314 ocp_data &= ~CUR_LINK_OK;
8315 ocp_data |= POLL_LINK_CHG;
8316 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8318 set_bit(GREEN_ETHERNET, &tp->flags);
8320 /* rx aggregation */
8321 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8322 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8323 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8325 r8156_mdio_force_mode(tp);
8326 rtl_tally_reset(tp);
8328 tp->coalesce = 15000; /* 15 us */
8331 static bool rtl_check_vendor_ok(struct usb_interface *intf)
8333 struct usb_host_interface *alt = intf->cur_altsetting;
8334 struct usb_endpoint_descriptor *in, *out, *intr;
8336 if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) {
8337 dev_err(&intf->dev, "Expected endpoints are not found\n");
8341 /* Check Rx endpoint address */
8342 if (usb_endpoint_num(in) != 1) {
8343 dev_err(&intf->dev, "Invalid Rx endpoint address\n");
8347 /* Check Tx endpoint address */
8348 if (usb_endpoint_num(out) != 2) {
8349 dev_err(&intf->dev, "Invalid Tx endpoint address\n");
8353 /* Check interrupt endpoint address */
8354 if (usb_endpoint_num(intr) != 3) {
8355 dev_err(&intf->dev, "Invalid interrupt endpoint address\n");
8362 static int rtl8152_pre_reset(struct usb_interface *intf)
8364 struct r8152 *tp = usb_get_intfdata(intf);
8365 struct net_device *netdev;
8369 if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags))
8372 netdev = tp->netdev;
8373 if (!netif_running(netdev))
8376 netif_stop_queue(netdev);
8377 tasklet_disable(&tp->tx_tl);
8378 clear_bit(WORK_ENABLE, &tp->flags);
8379 usb_kill_urb(tp->intr_urb);
8380 cancel_delayed_work_sync(&tp->schedule);
8381 napi_disable(&tp->napi);
8382 if (netif_carrier_ok(netdev)) {
8383 mutex_lock(&tp->control);
8384 set_bit(IN_PRE_RESET, &tp->flags);
8385 tp->rtl_ops.disable(tp);
8386 clear_bit(IN_PRE_RESET, &tp->flags);
8387 mutex_unlock(&tp->control);
8393 static int rtl8152_post_reset(struct usb_interface *intf)
8395 struct r8152 *tp = usb_get_intfdata(intf);
8396 struct net_device *netdev;
8399 if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags))
8402 rtl_set_accessible(tp);
8404 /* reset the MAC address in case of policy change */
8405 if (determine_ethernet_addr(tp, &sa) >= 0)
8406 dev_set_mac_address (tp->netdev, &sa, NULL);
8408 netdev = tp->netdev;
8409 if (!netif_running(netdev))
8412 set_bit(WORK_ENABLE, &tp->flags);
8413 if (netif_carrier_ok(netdev)) {
8414 mutex_lock(&tp->control);
8415 tp->rtl_ops.enable(tp);
8417 _rtl8152_set_rx_mode(netdev);
8418 mutex_unlock(&tp->control);
8421 napi_enable(&tp->napi);
8422 tasklet_enable(&tp->tx_tl);
8423 netif_wake_queue(netdev);
8424 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
8426 if (!list_empty(&tp->rx_done))
8427 napi_schedule(&tp->napi);
8434 static bool delay_autosuspend(struct r8152 *tp)
8436 bool sw_linking = !!netif_carrier_ok(tp->netdev);
8437 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
8439 /* This means a linking change occurs and the driver doesn't detect it,
8440 * yet. If the driver has disabled tx/rx and hw is linking on, the
8441 * device wouldn't wake up by receiving any packet.
8443 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
8446 /* If the linking down is occurred by nway, the device may miss the
8447 * linking change event. And it wouldn't wake when linking on.
8449 if (!sw_linking && tp->rtl_ops.in_nway(tp))
8451 else if (!skb_queue_empty(&tp->tx_queue))
8457 static int rtl8152_runtime_resume(struct r8152 *tp)
8459 struct net_device *netdev = tp->netdev;
8461 if (netif_running(netdev) && netdev->flags & IFF_UP) {
8462 struct napi_struct *napi = &tp->napi;
8464 tp->rtl_ops.autosuspend_en(tp, false);
8466 set_bit(WORK_ENABLE, &tp->flags);
8468 if (netif_carrier_ok(netdev)) {
8469 if (rtl8152_get_speed(tp) & LINK_STATUS) {
8472 netif_carrier_off(netdev);
8473 tp->rtl_ops.disable(tp);
8474 netif_info(tp, link, netdev, "linking down\n");
8479 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8480 smp_mb__after_atomic();
8482 if (!list_empty(&tp->rx_done))
8483 napi_schedule(&tp->napi);
8485 usb_submit_urb(tp->intr_urb, GFP_NOIO);
8487 if (netdev->flags & IFF_UP)
8488 tp->rtl_ops.autosuspend_en(tp, false);
8490 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8496 static int rtl8152_system_resume(struct r8152 *tp)
8498 struct net_device *netdev = tp->netdev;
8500 netif_device_attach(netdev);
8502 if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
8504 netif_carrier_off(netdev);
8505 set_bit(WORK_ENABLE, &tp->flags);
8506 usb_submit_urb(tp->intr_urb, GFP_NOIO);
8512 static int rtl8152_runtime_suspend(struct r8152 *tp)
8514 struct net_device *netdev = tp->netdev;
8517 if (!tp->rtl_ops.autosuspend_en)
8520 set_bit(SELECTIVE_SUSPEND, &tp->flags);
8521 smp_mb__after_atomic();
8523 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8526 if (netif_carrier_ok(netdev)) {
8529 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
8530 ocp_data = rcr & ~RCR_ACPT_ALL;
8531 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8532 rxdy_gated_en(tp, true);
8533 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
8535 if (!(ocp_data & RXFIFO_EMPTY)) {
8536 rxdy_gated_en(tp, false);
8537 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8538 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8539 smp_mb__after_atomic();
8545 clear_bit(WORK_ENABLE, &tp->flags);
8546 usb_kill_urb(tp->intr_urb);
8548 tp->rtl_ops.autosuspend_en(tp, true);
8550 if (netif_carrier_ok(netdev)) {
8551 struct napi_struct *napi = &tp->napi;
8555 rxdy_gated_en(tp, false);
8556 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8560 if (delay_autosuspend(tp)) {
8561 rtl8152_runtime_resume(tp);
8570 static int rtl8152_system_suspend(struct r8152 *tp)
8572 struct net_device *netdev = tp->netdev;
8574 netif_device_detach(netdev);
8576 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8577 struct napi_struct *napi = &tp->napi;
8579 clear_bit(WORK_ENABLE, &tp->flags);
8580 usb_kill_urb(tp->intr_urb);
8581 tasklet_disable(&tp->tx_tl);
8583 cancel_delayed_work_sync(&tp->schedule);
8584 tp->rtl_ops.down(tp);
8586 tasklet_enable(&tp->tx_tl);
8592 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
8594 struct r8152 *tp = usb_get_intfdata(intf);
8597 mutex_lock(&tp->control);
8599 if (PMSG_IS_AUTO(message))
8600 ret = rtl8152_runtime_suspend(tp);
8602 ret = rtl8152_system_suspend(tp);
8604 mutex_unlock(&tp->control);
8609 static int rtl8152_resume(struct usb_interface *intf)
8611 struct r8152 *tp = usb_get_intfdata(intf);
8614 mutex_lock(&tp->control);
8616 rtl_reset_ocp_base(tp);
8618 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
8619 ret = rtl8152_runtime_resume(tp);
8621 ret = rtl8152_system_resume(tp);
8623 mutex_unlock(&tp->control);
8628 static int rtl8152_reset_resume(struct usb_interface *intf)
8630 struct r8152 *tp = usb_get_intfdata(intf);
8632 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8633 rtl_reset_ocp_base(tp);
8634 tp->rtl_ops.init(tp);
8635 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
8636 set_ethernet_addr(tp, true);
8637 return rtl8152_resume(intf);
8640 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8642 struct r8152 *tp = netdev_priv(dev);
8644 if (usb_autopm_get_interface(tp->intf) < 0)
8647 if (!rtl_can_wakeup(tp)) {
8651 mutex_lock(&tp->control);
8652 wol->supported = WAKE_ANY;
8653 wol->wolopts = __rtl_get_wol(tp);
8654 mutex_unlock(&tp->control);
8657 usb_autopm_put_interface(tp->intf);
8660 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8662 struct r8152 *tp = netdev_priv(dev);
8665 if (!rtl_can_wakeup(tp))
8668 if (wol->wolopts & ~WAKE_ANY)
8671 ret = usb_autopm_get_interface(tp->intf);
8675 mutex_lock(&tp->control);
8677 __rtl_set_wol(tp, wol->wolopts);
8678 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
8680 mutex_unlock(&tp->control);
8682 usb_autopm_put_interface(tp->intf);
8688 static u32 rtl8152_get_msglevel(struct net_device *dev)
8690 struct r8152 *tp = netdev_priv(dev);
8692 return tp->msg_enable;
8695 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
8697 struct r8152 *tp = netdev_priv(dev);
8699 tp->msg_enable = value;
8702 static void rtl8152_get_drvinfo(struct net_device *netdev,
8703 struct ethtool_drvinfo *info)
8705 struct r8152 *tp = netdev_priv(netdev);
8707 strscpy(info->driver, MODULENAME, sizeof(info->driver));
8708 strscpy(info->version, DRIVER_VERSION, sizeof(info->version));
8709 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
8710 if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
8711 strscpy(info->fw_version, tp->rtl_fw.version,
8712 sizeof(info->fw_version));
8716 int rtl8152_get_link_ksettings(struct net_device *netdev,
8717 struct ethtool_link_ksettings *cmd)
8719 struct r8152 *tp = netdev_priv(netdev);
8722 if (!tp->mii.mdio_read)
8725 ret = usb_autopm_get_interface(tp->intf);
8729 mutex_lock(&tp->control);
8731 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
8733 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8734 cmd->link_modes.supported, tp->support_2500full);
8736 if (tp->support_2500full) {
8737 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8738 cmd->link_modes.advertising,
8739 ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
8741 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8742 cmd->link_modes.lp_advertising,
8743 ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
8745 if (is_speed_2500(rtl8152_get_speed(tp)))
8746 cmd->base.speed = SPEED_2500;
8749 mutex_unlock(&tp->control);
8751 usb_autopm_put_interface(tp->intf);
8757 static int rtl8152_set_link_ksettings(struct net_device *dev,
8758 const struct ethtool_link_ksettings *cmd)
8760 struct r8152 *tp = netdev_priv(dev);
8761 u32 advertising = 0;
8764 ret = usb_autopm_get_interface(tp->intf);
8768 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
8769 cmd->link_modes.advertising))
8770 advertising |= RTL_ADVERTISED_10_HALF;
8772 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
8773 cmd->link_modes.advertising))
8774 advertising |= RTL_ADVERTISED_10_FULL;
8776 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
8777 cmd->link_modes.advertising))
8778 advertising |= RTL_ADVERTISED_100_HALF;
8780 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
8781 cmd->link_modes.advertising))
8782 advertising |= RTL_ADVERTISED_100_FULL;
8784 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
8785 cmd->link_modes.advertising))
8786 advertising |= RTL_ADVERTISED_1000_HALF;
8788 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
8789 cmd->link_modes.advertising))
8790 advertising |= RTL_ADVERTISED_1000_FULL;
8792 if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8793 cmd->link_modes.advertising))
8794 advertising |= RTL_ADVERTISED_2500_FULL;
8796 mutex_lock(&tp->control);
8798 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
8799 cmd->base.duplex, advertising);
8801 tp->autoneg = cmd->base.autoneg;
8802 tp->speed = cmd->base.speed;
8803 tp->duplex = cmd->base.duplex;
8804 tp->advertising = advertising;
8807 mutex_unlock(&tp->control);
8809 usb_autopm_put_interface(tp->intf);
8815 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
8822 "tx_single_collisions",
8823 "tx_multi_collisions",
8831 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
8835 return ARRAY_SIZE(rtl8152_gstrings);
8841 static void rtl8152_get_ethtool_stats(struct net_device *dev,
8842 struct ethtool_stats *stats, u64 *data)
8844 struct r8152 *tp = netdev_priv(dev);
8845 struct tally_counter tally;
8847 if (usb_autopm_get_interface(tp->intf) < 0)
8850 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
8852 usb_autopm_put_interface(tp->intf);
8854 data[0] = le64_to_cpu(tally.tx_packets);
8855 data[1] = le64_to_cpu(tally.rx_packets);
8856 data[2] = le64_to_cpu(tally.tx_errors);
8857 data[3] = le32_to_cpu(tally.rx_errors);
8858 data[4] = le16_to_cpu(tally.rx_missed);
8859 data[5] = le16_to_cpu(tally.align_errors);
8860 data[6] = le32_to_cpu(tally.tx_one_collision);
8861 data[7] = le32_to_cpu(tally.tx_multi_collision);
8862 data[8] = le64_to_cpu(tally.rx_unicast);
8863 data[9] = le64_to_cpu(tally.rx_broadcast);
8864 data[10] = le32_to_cpu(tally.rx_multicast);
8865 data[11] = le16_to_cpu(tally.tx_aborted);
8866 data[12] = le16_to_cpu(tally.tx_underrun);
8869 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
8871 switch (stringset) {
8873 memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
8878 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8880 u32 lp, adv, supported = 0;
8883 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
8884 supported = mmd_eee_cap_to_ethtool_sup_t(val);
8886 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
8887 adv = mmd_eee_adv_to_ethtool_adv_t(val);
8889 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
8890 lp = mmd_eee_adv_to_ethtool_adv_t(val);
8892 eee->eee_enabled = tp->eee_en;
8893 eee->eee_active = !!(supported & adv & lp);
8894 eee->supported = supported;
8895 eee->advertised = tp->eee_adv;
8896 eee->lp_advertised = lp;
8901 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
8903 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
8905 tp->eee_en = eee->eee_enabled;
8908 rtl_eee_enable(tp, tp->eee_en);
8913 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8915 u32 lp, adv, supported = 0;
8918 val = ocp_reg_read(tp, OCP_EEE_ABLE);
8919 supported = mmd_eee_cap_to_ethtool_sup_t(val);
8921 val = ocp_reg_read(tp, OCP_EEE_ADV);
8922 adv = mmd_eee_adv_to_ethtool_adv_t(val);
8924 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
8925 lp = mmd_eee_adv_to_ethtool_adv_t(val);
8927 eee->eee_enabled = tp->eee_en;
8928 eee->eee_active = !!(supported & adv & lp);
8929 eee->supported = supported;
8930 eee->advertised = tp->eee_adv;
8931 eee->lp_advertised = lp;
8937 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
8939 struct r8152 *tp = netdev_priv(net);
8942 if (!tp->rtl_ops.eee_get) {
8947 ret = usb_autopm_get_interface(tp->intf);
8951 mutex_lock(&tp->control);
8953 ret = tp->rtl_ops.eee_get(tp, edata);
8955 mutex_unlock(&tp->control);
8957 usb_autopm_put_interface(tp->intf);
8964 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
8966 struct r8152 *tp = netdev_priv(net);
8969 if (!tp->rtl_ops.eee_set) {
8974 ret = usb_autopm_get_interface(tp->intf);
8978 mutex_lock(&tp->control);
8980 ret = tp->rtl_ops.eee_set(tp, edata);
8982 ret = mii_nway_restart(&tp->mii);
8984 mutex_unlock(&tp->control);
8986 usb_autopm_put_interface(tp->intf);
8992 static int rtl8152_nway_reset(struct net_device *dev)
8994 struct r8152 *tp = netdev_priv(dev);
8997 ret = usb_autopm_get_interface(tp->intf);
9001 mutex_lock(&tp->control);
9003 ret = mii_nway_restart(&tp->mii);
9005 mutex_unlock(&tp->control);
9007 usb_autopm_put_interface(tp->intf);
9013 static int rtl8152_get_coalesce(struct net_device *netdev,
9014 struct ethtool_coalesce *coalesce,
9015 struct kernel_ethtool_coalesce *kernel_coal,
9016 struct netlink_ext_ack *extack)
9018 struct r8152 *tp = netdev_priv(netdev);
9020 switch (tp->version) {
9029 coalesce->rx_coalesce_usecs = tp->coalesce;
9034 static int rtl8152_set_coalesce(struct net_device *netdev,
9035 struct ethtool_coalesce *coalesce,
9036 struct kernel_ethtool_coalesce *kernel_coal,
9037 struct netlink_ext_ack *extack)
9039 struct r8152 *tp = netdev_priv(netdev);
9042 switch (tp->version) {
9051 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
9054 ret = usb_autopm_get_interface(tp->intf);
9058 mutex_lock(&tp->control);
9060 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
9061 tp->coalesce = coalesce->rx_coalesce_usecs;
9063 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
9064 netif_stop_queue(netdev);
9065 napi_disable(&tp->napi);
9066 tp->rtl_ops.disable(tp);
9067 tp->rtl_ops.enable(tp);
9069 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
9070 _rtl8152_set_rx_mode(netdev);
9071 napi_enable(&tp->napi);
9072 netif_wake_queue(netdev);
9076 mutex_unlock(&tp->control);
9078 usb_autopm_put_interface(tp->intf);
9083 static int rtl8152_get_tunable(struct net_device *netdev,
9084 const struct ethtool_tunable *tunable, void *d)
9086 struct r8152 *tp = netdev_priv(netdev);
9088 switch (tunable->id) {
9089 case ETHTOOL_RX_COPYBREAK:
9090 *(u32 *)d = tp->rx_copybreak;
9099 static int rtl8152_set_tunable(struct net_device *netdev,
9100 const struct ethtool_tunable *tunable,
9103 struct r8152 *tp = netdev_priv(netdev);
9106 switch (tunable->id) {
9107 case ETHTOOL_RX_COPYBREAK:
9109 if (val < ETH_ZLEN) {
9110 netif_err(tp, rx_err, netdev,
9111 "Invalid rx copy break value\n");
9115 if (tp->rx_copybreak != val) {
9116 if (netdev->flags & IFF_UP) {
9117 mutex_lock(&tp->control);
9118 napi_disable(&tp->napi);
9119 tp->rx_copybreak = val;
9120 napi_enable(&tp->napi);
9121 mutex_unlock(&tp->control);
9123 tp->rx_copybreak = val;
9134 static void rtl8152_get_ringparam(struct net_device *netdev,
9135 struct ethtool_ringparam *ring,
9136 struct kernel_ethtool_ringparam *kernel_ring,
9137 struct netlink_ext_ack *extack)
9139 struct r8152 *tp = netdev_priv(netdev);
9141 ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
9142 ring->rx_pending = tp->rx_pending;
9145 static int rtl8152_set_ringparam(struct net_device *netdev,
9146 struct ethtool_ringparam *ring,
9147 struct kernel_ethtool_ringparam *kernel_ring,
9148 struct netlink_ext_ack *extack)
9150 struct r8152 *tp = netdev_priv(netdev);
9152 if (ring->rx_pending < (RTL8152_MAX_RX * 2))
9155 if (tp->rx_pending != ring->rx_pending) {
9156 if (netdev->flags & IFF_UP) {
9157 mutex_lock(&tp->control);
9158 napi_disable(&tp->napi);
9159 tp->rx_pending = ring->rx_pending;
9160 napi_enable(&tp->napi);
9161 mutex_unlock(&tp->control);
9163 tp->rx_pending = ring->rx_pending;
9170 static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9172 struct r8152 *tp = netdev_priv(netdev);
9173 u16 bmcr, lcladv, rmtadv;
9176 if (usb_autopm_get_interface(tp->intf) < 0)
9179 mutex_lock(&tp->control);
9181 bmcr = r8152_mdio_read(tp, MII_BMCR);
9182 lcladv = r8152_mdio_read(tp, MII_ADVERTISE);
9183 rmtadv = r8152_mdio_read(tp, MII_LPA);
9185 mutex_unlock(&tp->control);
9187 usb_autopm_put_interface(tp->intf);
9189 if (!(bmcr & BMCR_ANENABLE)) {
9191 pause->rx_pause = 0;
9192 pause->tx_pause = 0;
9198 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
9200 if (cap & FLOW_CTRL_RX)
9201 pause->rx_pause = 1;
9203 if (cap & FLOW_CTRL_TX)
9204 pause->tx_pause = 1;
9207 static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9209 struct r8152 *tp = netdev_priv(netdev);
9214 ret = usb_autopm_get_interface(tp->intf);
9218 mutex_lock(&tp->control);
9220 if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) {
9225 if (pause->rx_pause)
9226 cap |= FLOW_CTRL_RX;
9228 if (pause->tx_pause)
9229 cap |= FLOW_CTRL_TX;
9231 old = r8152_mdio_read(tp, MII_ADVERTISE);
9232 new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap);
9234 r8152_mdio_write(tp, MII_ADVERTISE, new1);
9237 mutex_unlock(&tp->control);
9238 usb_autopm_put_interface(tp->intf);
9243 static const struct ethtool_ops ops = {
9244 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
9245 .get_drvinfo = rtl8152_get_drvinfo,
9246 .get_link = ethtool_op_get_link,
9247 .nway_reset = rtl8152_nway_reset,
9248 .get_msglevel = rtl8152_get_msglevel,
9249 .set_msglevel = rtl8152_set_msglevel,
9250 .get_wol = rtl8152_get_wol,
9251 .set_wol = rtl8152_set_wol,
9252 .get_strings = rtl8152_get_strings,
9253 .get_sset_count = rtl8152_get_sset_count,
9254 .get_ethtool_stats = rtl8152_get_ethtool_stats,
9255 .get_coalesce = rtl8152_get_coalesce,
9256 .set_coalesce = rtl8152_set_coalesce,
9257 .get_eee = rtl_ethtool_get_eee,
9258 .set_eee = rtl_ethtool_set_eee,
9259 .get_link_ksettings = rtl8152_get_link_ksettings,
9260 .set_link_ksettings = rtl8152_set_link_ksettings,
9261 .get_tunable = rtl8152_get_tunable,
9262 .set_tunable = rtl8152_set_tunable,
9263 .get_ringparam = rtl8152_get_ringparam,
9264 .set_ringparam = rtl8152_set_ringparam,
9265 .get_pauseparam = rtl8152_get_pauseparam,
9266 .set_pauseparam = rtl8152_set_pauseparam,
9269 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
9271 struct r8152 *tp = netdev_priv(netdev);
9272 struct mii_ioctl_data *data = if_mii(rq);
9275 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9278 res = usb_autopm_get_interface(tp->intf);
9284 data->phy_id = R8152_PHY_ID; /* Internal PHY */
9288 mutex_lock(&tp->control);
9289 data->val_out = r8152_mdio_read(tp, data->reg_num);
9290 mutex_unlock(&tp->control);
9294 if (!capable(CAP_NET_ADMIN)) {
9298 mutex_lock(&tp->control);
9299 r8152_mdio_write(tp, data->reg_num, data->val_in);
9300 mutex_unlock(&tp->control);
9307 usb_autopm_put_interface(tp->intf);
9313 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
9315 struct r8152 *tp = netdev_priv(dev);
9318 switch (tp->version) {
9328 ret = usb_autopm_get_interface(tp->intf);
9332 mutex_lock(&tp->control);
9336 if (netif_running(dev)) {
9337 if (tp->rtl_ops.change_mtu)
9338 tp->rtl_ops.change_mtu(tp);
9340 if (netif_carrier_ok(dev)) {
9341 netif_stop_queue(dev);
9342 napi_disable(&tp->napi);
9343 tasklet_disable(&tp->tx_tl);
9344 tp->rtl_ops.disable(tp);
9345 tp->rtl_ops.enable(tp);
9347 tasklet_enable(&tp->tx_tl);
9348 napi_enable(&tp->napi);
9349 rtl8152_set_rx_mode(dev);
9350 netif_wake_queue(dev);
9354 mutex_unlock(&tp->control);
9356 usb_autopm_put_interface(tp->intf);
9361 static const struct net_device_ops rtl8152_netdev_ops = {
9362 .ndo_open = rtl8152_open,
9363 .ndo_stop = rtl8152_close,
9364 .ndo_eth_ioctl = rtl8152_ioctl,
9365 .ndo_start_xmit = rtl8152_start_xmit,
9366 .ndo_tx_timeout = rtl8152_tx_timeout,
9367 .ndo_set_features = rtl8152_set_features,
9368 .ndo_set_rx_mode = rtl8152_set_rx_mode,
9369 .ndo_set_mac_address = rtl8152_set_mac_address,
9370 .ndo_change_mtu = rtl8152_change_mtu,
9371 .ndo_validate_addr = eth_validate_addr,
9372 .ndo_features_check = rtl8152_features_check,
9375 static void rtl8152_unload(struct r8152 *tp)
9377 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9380 if (tp->version != RTL_VER_01)
9381 r8152_power_cut_en(tp, true);
9384 static void rtl8153_unload(struct r8152 *tp)
9386 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9389 r8153_power_cut_en(tp, false);
9392 static void rtl8153b_unload(struct r8152 *tp)
9394 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9397 r8153b_power_cut_en(tp, false);
9400 static int rtl_ops_init(struct r8152 *tp)
9402 struct rtl_ops *ops = &tp->rtl_ops;
9405 switch (tp->version) {
9409 ops->init = r8152b_init;
9410 ops->enable = rtl8152_enable;
9411 ops->disable = rtl8152_disable;
9412 ops->up = rtl8152_up;
9413 ops->down = rtl8152_down;
9414 ops->unload = rtl8152_unload;
9415 ops->eee_get = r8152_get_eee;
9416 ops->eee_set = r8152_set_eee;
9417 ops->in_nway = rtl8152_in_nway;
9418 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
9419 ops->autosuspend_en = rtl_runtime_suspend_enable;
9420 tp->rx_buf_sz = 16 * 1024;
9422 tp->eee_adv = MDIO_EEE_100TX;
9429 ops->init = r8153_init;
9430 ops->enable = rtl8153_enable;
9431 ops->disable = rtl8153_disable;
9432 ops->up = rtl8153_up;
9433 ops->down = rtl8153_down;
9434 ops->unload = rtl8153_unload;
9435 ops->eee_get = r8153_get_eee;
9436 ops->eee_set = r8152_set_eee;
9437 ops->in_nway = rtl8153_in_nway;
9438 ops->hw_phy_cfg = r8153_hw_phy_cfg;
9439 ops->autosuspend_en = rtl8153_runtime_enable;
9440 ops->change_mtu = rtl8153_change_mtu;
9441 if (tp->udev->speed < USB_SPEED_SUPER)
9442 tp->rx_buf_sz = 16 * 1024;
9444 tp->rx_buf_sz = 32 * 1024;
9446 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9451 ops->init = r8153b_init;
9452 ops->enable = rtl8153_enable;
9453 ops->disable = rtl8153_disable;
9454 ops->up = rtl8153b_up;
9455 ops->down = rtl8153b_down;
9456 ops->unload = rtl8153b_unload;
9457 ops->eee_get = r8153_get_eee;
9458 ops->eee_set = r8152_set_eee;
9459 ops->in_nway = rtl8153_in_nway;
9460 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
9461 ops->autosuspend_en = rtl8153b_runtime_enable;
9462 ops->change_mtu = rtl8153_change_mtu;
9463 tp->rx_buf_sz = 32 * 1024;
9465 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9470 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9473 ops->init = r8156_init;
9474 ops->enable = rtl8156_enable;
9475 ops->disable = rtl8156_disable;
9476 ops->up = rtl8156_up;
9477 ops->down = rtl8156_down;
9478 ops->unload = rtl8153_unload;
9479 ops->eee_get = r8153_get_eee;
9480 ops->eee_set = r8152_set_eee;
9481 ops->in_nway = rtl8153_in_nway;
9482 ops->hw_phy_cfg = r8156_hw_phy_cfg;
9483 ops->autosuspend_en = rtl8156_runtime_enable;
9484 ops->change_mtu = rtl8156_change_mtu;
9485 tp->rx_buf_sz = 48 * 1024;
9486 tp->support_2500full = 1;
9491 tp->support_2500full = 1;
9495 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9496 ops->init = r8156b_init;
9497 ops->enable = rtl8156b_enable;
9498 ops->disable = rtl8153_disable;
9499 ops->up = rtl8156_up;
9500 ops->down = rtl8156_down;
9501 ops->unload = rtl8153_unload;
9502 ops->eee_get = r8153_get_eee;
9503 ops->eee_set = r8152_set_eee;
9504 ops->in_nway = rtl8153_in_nway;
9505 ops->hw_phy_cfg = r8156b_hw_phy_cfg;
9506 ops->autosuspend_en = rtl8156_runtime_enable;
9507 ops->change_mtu = rtl8156_change_mtu;
9508 tp->rx_buf_sz = 48 * 1024;
9512 ops->init = r8153c_init;
9513 ops->enable = rtl8153_enable;
9514 ops->disable = rtl8153_disable;
9515 ops->up = rtl8153c_up;
9516 ops->down = rtl8153b_down;
9517 ops->unload = rtl8153_unload;
9518 ops->eee_get = r8153_get_eee;
9519 ops->eee_set = r8152_set_eee;
9520 ops->in_nway = rtl8153_in_nway;
9521 ops->hw_phy_cfg = r8153c_hw_phy_cfg;
9522 ops->autosuspend_en = rtl8153c_runtime_enable;
9523 ops->change_mtu = rtl8153c_change_mtu;
9524 tp->rx_buf_sz = 32 * 1024;
9526 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9531 dev_err(&tp->intf->dev, "Unknown Device\n");
9538 #define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
9539 #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
9540 #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
9541 #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
9542 #define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw"
9543 #define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw"
9544 #define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw"
9546 MODULE_FIRMWARE(FIRMWARE_8153A_2);
9547 MODULE_FIRMWARE(FIRMWARE_8153A_3);
9548 MODULE_FIRMWARE(FIRMWARE_8153A_4);
9549 MODULE_FIRMWARE(FIRMWARE_8153B_2);
9550 MODULE_FIRMWARE(FIRMWARE_8153C_1);
9551 MODULE_FIRMWARE(FIRMWARE_8156A_2);
9552 MODULE_FIRMWARE(FIRMWARE_8156B_2);
9554 static int rtl_fw_init(struct r8152 *tp)
9556 struct rtl_fw *rtl_fw = &tp->rtl_fw;
9558 switch (tp->version) {
9560 rtl_fw->fw_name = FIRMWARE_8153A_2;
9561 rtl_fw->pre_fw = r8153_pre_firmware_1;
9562 rtl_fw->post_fw = r8153_post_firmware_1;
9565 rtl_fw->fw_name = FIRMWARE_8153A_3;
9566 rtl_fw->pre_fw = r8153_pre_firmware_2;
9567 rtl_fw->post_fw = r8153_post_firmware_2;
9570 rtl_fw->fw_name = FIRMWARE_8153A_4;
9571 rtl_fw->post_fw = r8153_post_firmware_3;
9574 rtl_fw->fw_name = FIRMWARE_8153B_2;
9575 rtl_fw->pre_fw = r8153b_pre_firmware_1;
9576 rtl_fw->post_fw = r8153b_post_firmware_1;
9579 rtl_fw->fw_name = FIRMWARE_8156A_2;
9580 rtl_fw->post_fw = r8156a_post_firmware_1;
9584 rtl_fw->fw_name = FIRMWARE_8156B_2;
9587 rtl_fw->fw_name = FIRMWARE_8153C_1;
9588 rtl_fw->pre_fw = r8153b_pre_firmware_1;
9589 rtl_fw->post_fw = r8153c_post_firmware_1;
9598 static u8 __rtl_get_hw_ver(struct usb_device *udev)
9606 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
9610 /* Retry up to 3 times in case there is a transitory error. We do this
9611 * since retrying a read of the version is always safe and this
9612 * function doesn't take advantage of r8152_control_msg().
9614 for (i = 0; i < 3; i++) {
9615 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
9616 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
9617 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp),
9618 USB_CTRL_GET_TIMEOUT);
9620 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
9625 if (i != 0 && ret > 0)
9626 dev_warn(&udev->dev, "Needed %d retries to read version\n", i);
9632 version = RTL_VER_01;
9635 version = RTL_VER_02;
9638 version = RTL_VER_03;
9641 version = RTL_VER_04;
9644 version = RTL_VER_05;
9647 version = RTL_VER_06;
9650 version = RTL_VER_07;
9653 version = RTL_VER_08;
9656 version = RTL_VER_09;
9659 version = RTL_TEST_01;
9662 version = RTL_VER_10;
9665 version = RTL_VER_11;
9668 version = RTL_VER_12;
9671 version = RTL_VER_13;
9674 version = RTL_VER_14;
9677 version = RTL_VER_15;
9680 version = RTL_VER_UNKNOWN;
9681 dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data);
9688 u8 rtl8152_get_version(struct usb_interface *intf)
9692 version = __rtl_get_hw_ver(interface_to_usbdev(intf));
9694 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
9698 EXPORT_SYMBOL_GPL(rtl8152_get_version);
9700 static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev)
9702 int parent_vendor_id = le16_to_cpu(udev->parent->descriptor.idVendor);
9703 int product_id = le16_to_cpu(udev->descriptor.idProduct);
9704 int vendor_id = le16_to_cpu(udev->descriptor.idVendor);
9706 if (vendor_id == VENDOR_ID_LENOVO) {
9707 switch (product_id) {
9708 case DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB:
9709 case DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK:
9710 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
9711 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
9712 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3:
9713 case DEVICE_ID_THINKPAD_USB_C_DONGLE:
9716 } else if (vendor_id == VENDOR_ID_REALTEK && parent_vendor_id == VENDOR_ID_LENOVO) {
9717 switch (product_id) {
9725 static int rtl8152_probe_once(struct usb_interface *intf,
9726 const struct usb_device_id *id, u8 version)
9728 struct usb_device *udev = interface_to_usbdev(intf);
9730 struct net_device *netdev;
9733 usb_reset_device(udev);
9734 netdev = alloc_etherdev(sizeof(struct r8152));
9736 dev_err(&intf->dev, "Out of memory\n");
9740 SET_NETDEV_DEV(netdev, &intf->dev);
9741 tp = netdev_priv(netdev);
9742 tp->msg_enable = 0x7FFF;
9745 tp->netdev = netdev;
9747 tp->version = version;
9749 tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0);
9750 tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0);
9751 tp->pipe_in = usb_rcvbulkpipe(udev, 1);
9752 tp->pipe_out = usb_sndbulkpipe(udev, 2);
9753 tp->pipe_intr = usb_rcvintpipe(udev, 3);
9759 tp->mii.supports_gmii = 0;
9762 tp->mii.supports_gmii = 1;
9766 ret = rtl_ops_init(tp);
9772 mutex_init(&tp->control);
9773 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
9774 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
9775 tasklet_setup(&tp->tx_tl, bottom_half);
9776 tasklet_disable(&tp->tx_tl);
9778 netdev->netdev_ops = &rtl8152_netdev_ops;
9779 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
9781 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9782 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
9783 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
9784 NETIF_F_HW_VLAN_CTAG_TX;
9785 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9786 NETIF_F_TSO | NETIF_F_FRAGLIST |
9787 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
9788 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
9789 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
9790 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
9791 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
9793 if (tp->version == RTL_VER_01) {
9794 netdev->features &= ~NETIF_F_RXCSUM;
9795 netdev->hw_features &= ~NETIF_F_RXCSUM;
9798 tp->lenovo_macpassthru = rtl8152_supports_lenovo_macpassthru(udev);
9800 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
9801 (!strcmp(udev->serial, "000001000000") ||
9802 !strcmp(udev->serial, "000002000000"))) {
9803 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
9804 tp->dell_tb_rx_agg_bug = 1;
9807 netdev->ethtool_ops = &ops;
9808 netif_set_tso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
9810 /* MTU range: 68 - 1500 or 9194 */
9811 netdev->min_mtu = ETH_MIN_MTU;
9812 switch (tp->version) {
9820 netdev->max_mtu = size_to_mtu(9 * 1024);
9824 netdev->max_mtu = size_to_mtu(15 * 1024);
9829 netdev->max_mtu = size_to_mtu(16 * 1024);
9835 netdev->max_mtu = ETH_DATA_LEN;
9839 tp->mii.dev = netdev;
9840 tp->mii.mdio_read = read_mii_word;
9841 tp->mii.mdio_write = write_mii_word;
9842 tp->mii.phy_id_mask = 0x3f;
9843 tp->mii.reg_num_mask = 0x1f;
9844 tp->mii.phy_id = R8152_PHY_ID;
9846 tp->autoneg = AUTONEG_ENABLE;
9847 tp->speed = SPEED_100;
9848 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
9849 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
9850 if (tp->mii.supports_gmii) {
9851 if (tp->support_2500full &&
9852 tp->udev->speed >= USB_SPEED_SUPER) {
9853 tp->speed = SPEED_2500;
9854 tp->advertising |= RTL_ADVERTISED_2500_FULL;
9856 tp->speed = SPEED_1000;
9858 tp->advertising |= RTL_ADVERTISED_1000_FULL;
9860 tp->duplex = DUPLEX_FULL;
9862 tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
9863 tp->rx_pending = 10 * RTL8152_MAX_RX;
9865 intf->needs_remote_wakeup = 1;
9867 if (!rtl_can_wakeup(tp))
9868 __rtl_set_wol(tp, 0);
9870 tp->saved_wolopts = __rtl_get_wol(tp);
9872 tp->rtl_ops.init(tp);
9873 #if IS_BUILTIN(CONFIG_USB_RTL8152)
9874 /* Retry in case request_firmware() is not ready yet. */
9875 tp->rtl_fw.retry = true;
9877 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
9878 set_ethernet_addr(tp, false);
9880 usb_set_intfdata(intf, tp);
9882 netif_napi_add(netdev, &tp->napi, r8152_poll);
9884 ret = register_netdev(netdev);
9886 dev_err(&intf->dev, "couldn't register the device\n");
9890 if (tp->saved_wolopts)
9891 device_set_wakeup_enable(&udev->dev, true);
9893 device_set_wakeup_enable(&udev->dev, false);
9895 /* If we saw a control transfer error while probing then we may
9896 * want to try probe() again. Consider this an error.
9898 if (test_bit(PROBE_SHOULD_RETRY, &tp->flags))
9901 set_bit(PROBED_WITH_NO_ERRORS, &tp->flags);
9902 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
9907 unregister_netdev(netdev);
9910 tasklet_kill(&tp->tx_tl);
9911 cancel_delayed_work_sync(&tp->hw_phy_work);
9912 if (tp->rtl_ops.unload)
9913 tp->rtl_ops.unload(tp);
9914 rtl8152_release_firmware(tp);
9915 usb_set_intfdata(intf, NULL);
9917 if (test_bit(PROBE_SHOULD_RETRY, &tp->flags))
9920 free_netdev(netdev);
9924 #define RTL8152_PROBE_TRIES 3
9926 static int rtl8152_probe(struct usb_interface *intf,
9927 const struct usb_device_id *id)
9933 if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC)
9936 if (!rtl_check_vendor_ok(intf))
9939 version = rtl8152_get_version(intf);
9940 if (version == RTL_VER_UNKNOWN)
9943 for (i = 0; i < RTL8152_PROBE_TRIES; i++) {
9944 ret = rtl8152_probe_once(intf, id, version);
9948 if (ret == -EAGAIN) {
9950 "r8152 failed probe after %d tries; giving up\n", i);
9957 static void rtl8152_disconnect(struct usb_interface *intf)
9959 struct r8152 *tp = usb_get_intfdata(intf);
9961 usb_set_intfdata(intf, NULL);
9965 unregister_netdev(tp->netdev);
9966 tasklet_kill(&tp->tx_tl);
9967 cancel_delayed_work_sync(&tp->hw_phy_work);
9968 if (tp->rtl_ops.unload)
9969 tp->rtl_ops.unload(tp);
9970 rtl8152_release_firmware(tp);
9971 free_netdev(tp->netdev);
9975 /* table of devices that work with this driver */
9976 static const struct usb_device_id rtl8152_table[] = {
9978 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8050) },
9979 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8053) },
9980 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8152) },
9981 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) },
9982 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) },
9983 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) },
9986 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) },
9987 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6) },
9988 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927) },
9989 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e) },
9990 { USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101) },
9991 { USB_DEVICE(VENDOR_ID_LENOVO, 0x304f) },
9992 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3054) },
9993 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3062) },
9994 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3069) },
9995 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3082) },
9996 { USB_DEVICE(VENDOR_ID_LENOVO, 0x7205) },
9997 { USB_DEVICE(VENDOR_ID_LENOVO, 0x720c) },
9998 { USB_DEVICE(VENDOR_ID_LENOVO, 0x7214) },
9999 { USB_DEVICE(VENDOR_ID_LENOVO, 0x721e) },
10000 { USB_DEVICE(VENDOR_ID_LENOVO, 0xa387) },
10001 { USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) },
10002 { USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff) },
10003 { USB_DEVICE(VENDOR_ID_TPLINK, 0x0601) },
10004 { USB_DEVICE(VENDOR_ID_DLINK, 0xb301) },
10008 MODULE_DEVICE_TABLE(usb, rtl8152_table);
10010 static struct usb_driver rtl8152_driver = {
10011 .name = MODULENAME,
10012 .id_table = rtl8152_table,
10013 .probe = rtl8152_probe,
10014 .disconnect = rtl8152_disconnect,
10015 .suspend = rtl8152_suspend,
10016 .resume = rtl8152_resume,
10017 .reset_resume = rtl8152_reset_resume,
10018 .pre_reset = rtl8152_pre_reset,
10019 .post_reset = rtl8152_post_reset,
10020 .supports_autosuspend = 1,
10021 .disable_hub_initiated_lpm = 1,
10024 static int rtl8152_cfgselector_probe(struct usb_device *udev)
10026 struct usb_host_config *c;
10027 int i, num_configs;
10029 /* Switch the device to vendor mode, if and only if the vendor mode
10030 * driver supports it.
10032 if (__rtl_get_hw_ver(udev) == RTL_VER_UNKNOWN)
10035 /* The vendor mode is not always config #1, so to find it out. */
10037 num_configs = udev->descriptor.bNumConfigurations;
10038 for (i = 0; i < num_configs; (i++, c++)) {
10039 struct usb_interface_descriptor *desc = NULL;
10041 if (!c->desc.bNumInterfaces)
10043 desc = &c->intf_cache[0]->altsetting->desc;
10044 if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC)
10048 if (i == num_configs)
10051 if (usb_set_configuration(udev, c->desc.bConfigurationValue)) {
10052 dev_err(&udev->dev, "Failed to set configuration %d\n",
10053 c->desc.bConfigurationValue);
10060 static struct usb_device_driver rtl8152_cfgselector_driver = {
10061 .name = MODULENAME "-cfgselector",
10062 .probe = rtl8152_cfgselector_probe,
10063 .id_table = rtl8152_table,
10064 .generic_subclass = 1,
10065 .supports_autosuspend = 1,
10068 static int __init rtl8152_driver_init(void)
10072 ret = usb_register_device_driver(&rtl8152_cfgselector_driver, THIS_MODULE);
10075 return usb_register(&rtl8152_driver);
10078 static void __exit rtl8152_driver_exit(void)
10080 usb_deregister(&rtl8152_driver);
10081 usb_deregister_device_driver(&rtl8152_cfgselector_driver);
10084 module_init(rtl8152_driver_init);
10085 module_exit(rtl8152_driver_exit);
10087 MODULE_AUTHOR(DRIVER_AUTHOR);
10088 MODULE_DESCRIPTION(DRIVER_DESC);
10089 MODULE_LICENSE("GPL");
10090 MODULE_VERSION(DRIVER_VERSION);