1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29 #include <linux/usb/r8152.h>
32 /* Information for net-next */
33 #define NETNEXT_VERSION "12"
35 /* Information for net */
36 #define NET_VERSION "13"
38 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
39 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
40 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
41 #define MODULENAME "r8152"
43 #define R8152_PHY_ID 32
45 #define PLA_IDR 0xc000
46 #define PLA_RCR 0xc010
47 #define PLA_RCR1 0xc012
48 #define PLA_RMS 0xc016
49 #define PLA_RXFIFO_CTRL0 0xc0a0
50 #define PLA_RXFIFO_FULL 0xc0a2
51 #define PLA_RXFIFO_CTRL1 0xc0a4
52 #define PLA_RX_FIFO_FULL 0xc0a6
53 #define PLA_RXFIFO_CTRL2 0xc0a8
54 #define PLA_RX_FIFO_EMPTY 0xc0aa
55 #define PLA_DMY_REG0 0xc0b0
56 #define PLA_FMC 0xc0b4
57 #define PLA_CFG_WOL 0xc0b6
58 #define PLA_TEREDO_CFG 0xc0bc
59 #define PLA_TEREDO_WAKE_BASE 0xc0c4
60 #define PLA_MAR 0xcd00
61 #define PLA_BACKUP 0xd000
62 #define PLA_BDC_CR 0xd1a0
63 #define PLA_TEREDO_TIMER 0xd2cc
64 #define PLA_REALWOW_TIMER 0xd2e8
65 #define PLA_UPHY_TIMER 0xd388
66 #define PLA_SUSPEND_FLAG 0xd38a
67 #define PLA_INDICATE_FALG 0xd38c
68 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
69 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
70 #define PLA_EXTRA_STATUS 0xd398
71 #define PLA_GPHY_CTRL 0xd3ae
72 #define PLA_POL_GPIO_CTRL 0xdc6a
73 #define PLA_EFUSE_DATA 0xdd00
74 #define PLA_EFUSE_CMD 0xdd02
75 #define PLA_LEDSEL 0xdd90
76 #define PLA_LED_FEATURE 0xdd92
77 #define PLA_PHYAR 0xde00
78 #define PLA_BOOT_CTRL 0xe004
79 #define PLA_LWAKE_CTRL_REG 0xe007
80 #define PLA_GPHY_INTR_IMR 0xe022
81 #define PLA_EEE_CR 0xe040
82 #define PLA_EEE_TXTWSYS 0xe04c
83 #define PLA_EEE_TXTWSYS_2P5G 0xe058
84 #define PLA_EEEP_CR 0xe080
85 #define PLA_MAC_PWR_CTRL 0xe0c0
86 #define PLA_MAC_PWR_CTRL2 0xe0ca
87 #define PLA_MAC_PWR_CTRL3 0xe0cc
88 #define PLA_MAC_PWR_CTRL4 0xe0ce
89 #define PLA_WDT6_CTRL 0xe428
90 #define PLA_TCR0 0xe610
91 #define PLA_TCR1 0xe612
92 #define PLA_MTPS 0xe615
93 #define PLA_TXFIFO_CTRL 0xe618
94 #define PLA_TXFIFO_FULL 0xe61a
95 #define PLA_RSTTALLY 0xe800
97 #define PLA_CRWECR 0xe81c
98 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
99 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
100 #define PLA_CONFIG5 0xe822
101 #define PLA_PHY_PWR 0xe84c
102 #define PLA_OOB_CTRL 0xe84f
103 #define PLA_CPCR 0xe854
104 #define PLA_MISC_0 0xe858
105 #define PLA_MISC_1 0xe85a
106 #define PLA_OCP_GPHY_BASE 0xe86c
107 #define PLA_TALLYCNT 0xe890
108 #define PLA_SFF_STS_7 0xe8de
109 #define PLA_PHYSTATUS 0xe908
110 #define PLA_CONFIG6 0xe90a /* CONFIG6 */
111 #define PLA_USB_CFG 0xe952
112 #define PLA_BP_BA 0xfc26
113 #define PLA_BP_0 0xfc28
114 #define PLA_BP_1 0xfc2a
115 #define PLA_BP_2 0xfc2c
116 #define PLA_BP_3 0xfc2e
117 #define PLA_BP_4 0xfc30
118 #define PLA_BP_5 0xfc32
119 #define PLA_BP_6 0xfc34
120 #define PLA_BP_7 0xfc36
121 #define PLA_BP_EN 0xfc38
123 #define USB_USB2PHY 0xb41e
124 #define USB_SSPHYLINK1 0xb426
125 #define USB_SSPHYLINK2 0xb428
126 #define USB_L1_CTRL 0xb45e
127 #define USB_U2P3_CTRL 0xb460
128 #define USB_CSR_DUMMY1 0xb464
129 #define USB_CSR_DUMMY2 0xb466
130 #define USB_DEV_STAT 0xb808
131 #define USB_CONNECT_TIMER 0xcbf8
132 #define USB_MSC_TIMER 0xcbfc
133 #define USB_BURST_SIZE 0xcfc0
134 #define USB_FW_FIX_EN0 0xcfca
135 #define USB_FW_FIX_EN1 0xcfcc
136 #define USB_LPM_CONFIG 0xcfd8
137 #define USB_ECM_OPTION 0xcfee
138 #define USB_CSTMR 0xcfef /* RTL8153A */
139 #define USB_MISC_2 0xcfff
140 #define USB_ECM_OP 0xd26b
141 #define USB_GPHY_CTRL 0xd284
142 #define USB_SPEED_OPTION 0xd32a
143 #define USB_FW_CTRL 0xd334 /* RTL8153B */
144 #define USB_FC_TIMER 0xd340
145 #define USB_USB_CTRL 0xd406
146 #define USB_PHY_CTRL 0xd408
147 #define USB_TX_AGG 0xd40a
148 #define USB_RX_BUF_TH 0xd40c
149 #define USB_USB_TIMER 0xd428
150 #define USB_RX_EARLY_TIMEOUT 0xd42c
151 #define USB_RX_EARLY_SIZE 0xd42e
152 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
153 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
154 #define USB_TX_DMA 0xd434
155 #define USB_UPT_RXDMA_OWN 0xd437
156 #define USB_UPHY3_MDCMDIO 0xd480
157 #define USB_TOLERANCE 0xd490
158 #define USB_LPM_CTRL 0xd41a
159 #define USB_BMU_RESET 0xd4b0
160 #define USB_BMU_CONFIG 0xd4b4
161 #define USB_U1U2_TIMER 0xd4da
162 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
163 #define USB_RX_AGGR_NUM 0xd4ee
164 #define USB_UPS_CTRL 0xd800
165 #define USB_POWER_CUT 0xd80a
166 #define USB_MISC_0 0xd81a
167 #define USB_MISC_1 0xd81f
168 #define USB_AFE_CTRL2 0xd824
169 #define USB_UPHY_XTAL 0xd826
170 #define USB_UPS_CFG 0xd842
171 #define USB_UPS_FLAGS 0xd848
172 #define USB_WDT1_CTRL 0xe404
173 #define USB_WDT11_CTRL 0xe43c
174 #define USB_BP_BA PLA_BP_BA
175 #define USB_BP_0 PLA_BP_0
176 #define USB_BP_1 PLA_BP_1
177 #define USB_BP_2 PLA_BP_2
178 #define USB_BP_3 PLA_BP_3
179 #define USB_BP_4 PLA_BP_4
180 #define USB_BP_5 PLA_BP_5
181 #define USB_BP_6 PLA_BP_6
182 #define USB_BP_7 PLA_BP_7
183 #define USB_BP_EN PLA_BP_EN /* RTL8153A */
184 #define USB_BP_8 0xfc38 /* RTL8153B */
185 #define USB_BP_9 0xfc3a
186 #define USB_BP_10 0xfc3c
187 #define USB_BP_11 0xfc3e
188 #define USB_BP_12 0xfc40
189 #define USB_BP_13 0xfc42
190 #define USB_BP_14 0xfc44
191 #define USB_BP_15 0xfc46
192 #define USB_BP2_EN 0xfc48
195 #define OCP_ALDPS_CONFIG 0x2010
196 #define OCP_EEE_CONFIG1 0x2080
197 #define OCP_EEE_CONFIG2 0x2092
198 #define OCP_EEE_CONFIG3 0x2094
199 #define OCP_BASE_MII 0xa400
200 #define OCP_EEE_AR 0xa41a
201 #define OCP_EEE_DATA 0xa41c
202 #define OCP_PHY_STATUS 0xa420
203 #define OCP_INTR_EN 0xa424
204 #define OCP_NCTL_CFG 0xa42c
205 #define OCP_POWER_CFG 0xa430
206 #define OCP_EEE_CFG 0xa432
207 #define OCP_SRAM_ADDR 0xa436
208 #define OCP_SRAM_DATA 0xa438
209 #define OCP_DOWN_SPEED 0xa442
210 #define OCP_EEE_ABLE 0xa5c4
211 #define OCP_EEE_ADV 0xa5d0
212 #define OCP_EEE_LPABLE 0xa5d2
213 #define OCP_10GBT_CTRL 0xa5d4
214 #define OCP_10GBT_STAT 0xa5d6
215 #define OCP_EEE_ADV2 0xa6d4
216 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
217 #define OCP_PHY_PATCH_STAT 0xb800
218 #define OCP_PHY_PATCH_CMD 0xb820
219 #define OCP_PHY_LOCK 0xb82e
220 #define OCP_ADC_IOFFSET 0xbcfc
221 #define OCP_ADC_CFG 0xbc06
222 #define OCP_SYSCLK_CFG 0xc416
225 #define SRAM_GREEN_CFG 0x8011
226 #define SRAM_LPF_CFG 0x8012
227 #define SRAM_GPHY_FW_VER 0x801e
228 #define SRAM_10M_AMP1 0x8080
229 #define SRAM_10M_AMP2 0x8082
230 #define SRAM_IMPEDANCE 0x8084
231 #define SRAM_PHY_LOCK 0xb82e
234 #define RCR_AAP 0x00000001
235 #define RCR_APM 0x00000002
236 #define RCR_AM 0x00000004
237 #define RCR_AB 0x00000008
238 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
239 #define SLOT_EN BIT(11)
242 #define OUTER_VLAN BIT(7)
243 #define INNER_VLAN BIT(6)
245 /* PLA_RXFIFO_CTRL0 */
246 #define RXFIFO_THR1_NORMAL 0x00080002
247 #define RXFIFO_THR1_OOB 0x01800003
249 /* PLA_RXFIFO_FULL */
250 #define RXFIFO_FULL_MASK 0xfff
252 /* PLA_RXFIFO_CTRL1 */
253 #define RXFIFO_THR2_FULL 0x00000060
254 #define RXFIFO_THR2_HIGH 0x00000038
255 #define RXFIFO_THR2_OOB 0x0000004a
256 #define RXFIFO_THR2_NORMAL 0x00a0
258 /* PLA_RXFIFO_CTRL2 */
259 #define RXFIFO_THR3_FULL 0x00000078
260 #define RXFIFO_THR3_HIGH 0x00000048
261 #define RXFIFO_THR3_OOB 0x0000005a
262 #define RXFIFO_THR3_NORMAL 0x0110
264 /* PLA_TXFIFO_CTRL */
265 #define TXFIFO_THR_NORMAL 0x00400008
266 #define TXFIFO_THR_NORMAL2 0x01000008
269 #define ECM_ALDPS 0x0002
272 #define FMC_FCR_MCU_EN 0x0001
275 #define EEEP_CR_EEEP_TX 0x0002
278 #define WDT6_SET_MODE 0x0010
281 #define TCR0_TX_EMPTY 0x0800
282 #define TCR0_AUTO_FIFO 0x0080
285 #define VERSION_MASK 0x7cf0
286 #define IFG_MASK (BIT(3) | BIT(9) | BIT(8))
287 #define IFG_144NS BIT(9)
288 #define IFG_96NS (BIT(9) | BIT(8))
291 #define MTPS_JUMBO (12 * 1024 / 64)
292 #define MTPS_DEFAULT (6 * 1024 / 64)
295 #define TALLY_RESET 0x0001
303 #define CRWECR_NORAML 0x00
304 #define CRWECR_CONFIG 0xc0
307 #define NOW_IS_OOB 0x80
308 #define TXFIFO_EMPTY 0x20
309 #define RXFIFO_EMPTY 0x10
310 #define LINK_LIST_READY 0x02
311 #define DIS_MCU_CLROOB 0x01
312 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
315 #define RXDY_GATED_EN 0x0008
318 #define RE_INIT_LL 0x8000
319 #define MCU_BORW_EN 0x4000
322 #define FLOW_CTRL_EN BIT(0)
323 #define CPCR_RX_VLAN 0x0040
326 #define MAGIC_EN 0x0001
329 #define TEREDO_SEL 0x8000
330 #define TEREDO_WAKE_MASK 0x7f00
331 #define TEREDO_RS_EVENT_MASK 0x00fe
332 #define OOB_TEREDO_EN 0x0001
335 #define ALDPS_PROXY_MODE 0x0001
338 #define EFUSE_READ_CMD BIT(15)
339 #define EFUSE_DATA_BIT16 BIT(7)
342 #define LINK_ON_WAKE_EN 0x0010
343 #define LINK_OFF_WAKE_EN 0x0008
346 #define LANWAKE_CLR_EN BIT(0)
349 #define EN_XG_LIP BIT(1)
350 #define EN_G_LIP BIT(2)
353 #define BWF_EN 0x0040
354 #define MWF_EN 0x0020
355 #define UWF_EN 0x0010
356 #define LAN_WAKE_EN 0x0002
358 /* PLA_LED_FEATURE */
359 #define LED_MODE_MASK 0x0700
362 #define TX_10M_IDLE_EN 0x0080
363 #define PFM_PWM_SWITCH 0x0040
364 #define TEST_IO_OFF BIT(4)
366 /* PLA_MAC_PWR_CTRL */
367 #define D3_CLK_GATED_EN 0x00004000
368 #define MCU_CLK_RATIO 0x07010f07
369 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
370 #define ALDPS_SPDWN_RATIO 0x0f87
372 /* PLA_MAC_PWR_CTRL2 */
373 #define EEE_SPDWN_RATIO 0x8007
374 #define MAC_CLK_SPDWN_EN BIT(15)
375 #define EEE_SPDWN_RATIO_MASK 0xff
377 /* PLA_MAC_PWR_CTRL3 */
378 #define PLA_MCU_SPDWN_EN BIT(14)
379 #define PKT_AVAIL_SPDWN_EN 0x0100
380 #define SUSPEND_SPDWN_EN 0x0004
381 #define U1U2_SPDWN_EN 0x0002
382 #define L1_SPDWN_EN 0x0001
384 /* PLA_MAC_PWR_CTRL4 */
385 #define PWRSAVE_SPDWN_EN 0x1000
386 #define RXDV_SPDWN_EN 0x0800
387 #define TX10MIDLE_EN 0x0100
388 #define IDLE_SPDWN_EN BIT(6)
389 #define TP100_SPDWN_EN 0x0020
390 #define TP500_SPDWN_EN 0x0010
391 #define TP1000_SPDWN_EN 0x0008
392 #define EEE_SPDWN_EN 0x0001
394 /* PLA_GPHY_INTR_IMR */
395 #define GPHY_STS_MSK 0x0001
396 #define SPEED_DOWN_MSK 0x0002
397 #define SPDWN_RXDV_MSK 0x0004
398 #define SPDWN_LINKCHG_MSK 0x0008
401 #define PHYAR_FLAG 0x80000000
404 #define EEE_RX_EN 0x0001
405 #define EEE_TX_EN 0x0002
408 #define AUTOLOAD_DONE 0x0002
410 /* PLA_LWAKE_CTRL_REG */
411 #define LANWAKE_PIN BIT(7)
413 /* PLA_SUSPEND_FLAG */
414 #define LINK_CHG_EVENT BIT(0)
416 /* PLA_INDICATE_FALG */
417 #define UPCOMING_RUNTIME_D3 BIT(0)
419 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
420 #define DEBUG_OE BIT(0)
421 #define DEBUG_LTSSM 0x0082
423 /* PLA_EXTRA_STATUS */
424 #define CUR_LINK_OK BIT(15)
425 #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
426 #define LINK_CHANGE_FLAG BIT(8)
427 #define POLL_LINK_CHG BIT(0)
430 #define GPHY_FLASH BIT(1)
432 /* PLA_POL_GPIO_CTRL */
433 #define DACK_DET_EN BIT(15)
434 #define POL_GPHY_PATCH BIT(4)
437 #define USB2PHY_SUSPEND 0x0001
438 #define USB2PHY_L1 0x0002
441 #define DELAY_PHY_PWR_CHG BIT(1)
444 #define pwd_dn_scale_mask 0x3ffe
445 #define pwd_dn_scale(x) ((x) << 1)
448 #define DYNAMIC_BURST 0x0001
451 #define EP4_FULL_FC 0x0001
454 #define STAT_SPEED_MASK 0x0006
455 #define STAT_SPEED_HIGH 0x0000
456 #define STAT_SPEED_FULL 0x0002
459 #define FW_FIX_SUSPEND BIT(14)
462 #define FW_IP_RESET_EN BIT(9)
465 #define LPM_U1U2_EN BIT(0)
468 #define TX_AGG_MAX_THRESHOLD 0x03
471 #define RX_THR_SUPPER 0x0c350180
472 #define RX_THR_HIGH 0x7a120180
473 #define RX_THR_SLOW 0xffff0180
474 #define RX_THR_B 0x00010001
477 #define TEST_MODE_DISABLE 0x00000001
478 #define TX_SIZE_ADJUST1 0x00000100
481 #define BMU_RESET_EP_IN 0x01
482 #define BMU_RESET_EP_OUT 0x02
485 #define ACT_ODMA BIT(1)
487 /* USB_UPT_RXDMA_OWN */
488 #define OWN_UPDATE BIT(0)
489 #define OWN_CLEAR BIT(1)
492 #define FC_PATCH_TASK BIT(1)
494 /* USB_RX_AGGR_NUM */
495 #define RX_AGGR_NUM_MASK 0x1ff
498 #define POWER_CUT 0x0100
500 /* USB_PM_CTRL_STATUS */
501 #define RESUME_INDICATE 0x0001
504 #define BYPASS_MAC_RESET BIT(5)
507 #define FORCE_SUPER BIT(0)
510 #define UPS_FORCE_PWR_DOWN BIT(0)
513 #define EN_ALL_SPEED BIT(0)
516 #define GPHY_PATCH_DONE BIT(2)
517 #define BYPASS_FLASH BIT(5)
518 #define BACKUP_RESTRORE BIT(6)
520 /* USB_SPEED_OPTION */
521 #define RG_PWRDN_EN BIT(8)
522 #define ALL_SPEED_OFF BIT(9)
525 #define FLOW_CTRL_PATCH_OPT BIT(1)
526 #define AUTO_SPEEDUP BIT(3)
527 #define FLOW_CTRL_PATCH_2 BIT(8)
530 #define CTRL_TIMER_EN BIT(15)
533 #define CDC_ECM_EN BIT(3)
534 #define RX_AGG_DISABLE 0x0010
535 #define RX_ZERO_EN 0x0080
538 #define U2P3_ENABLE 0x0001
539 #define RX_DETECT8 BIT(3)
542 #define PWR_EN 0x0001
543 #define PHASE2_EN 0x0008
544 #define UPS_EN BIT(4)
545 #define USP_PREWAKE BIT(5)
548 #define PCUT_STATUS 0x0001
550 /* USB_RX_EARLY_TIMEOUT */
551 #define COALESCE_SUPER 85000U
552 #define COALESCE_HIGH 250000U
553 #define COALESCE_SLOW 524280U
556 #define WTD1_EN BIT(0)
559 #define TIMER11_EN 0x0001
562 /* bit 4 ~ 5: fifo empty boundary */
563 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
564 /* bit 2 ~ 3: LMP timer */
565 #define LPM_TIMER_MASK 0x0c
566 #define LPM_TIMER_500MS 0x04 /* 500 ms */
567 #define LPM_TIMER_500US 0x0c /* 500 us */
568 #define ROK_EXIT_LPM 0x02
571 #define SEN_VAL_MASK 0xf800
572 #define SEN_VAL_NORMAL 0xa000
573 #define SEL_RXIDLE 0x0100
576 #define OOBS_POLLING BIT(8)
579 #define SAW_CNT_1MS_MASK 0x0fff
580 #define MID_REVERSE BIT(5) /* RTL8156A */
583 #define UPS_FLAGS_R_TUNE BIT(0)
584 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
585 #define UPS_FLAGS_250M_CKDIV BIT(2)
586 #define UPS_FLAGS_EN_ALDPS BIT(3)
587 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
588 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
589 #define ups_flags_speed(x) ((x) << 16)
590 #define UPS_FLAGS_EN_EEE BIT(20)
591 #define UPS_FLAGS_EN_500M_EEE BIT(21)
592 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
593 #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
594 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
595 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
596 #define UPS_FLAGS_EN_GREEN BIT(26)
597 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
613 /* OCP_ALDPS_CONFIG */
614 #define ENPWRSAVE 0x8000
615 #define ENPDNPS 0x0200
616 #define LINKENA 0x0100
617 #define DIS_SDSAVE 0x0010
620 #define PHY_STAT_MASK 0x0007
621 #define PHY_STAT_EXT_INIT 2
622 #define PHY_STAT_LAN_ON 3
623 #define PHY_STAT_PWRDN 5
626 #define INTR_SPEED_FORCE BIT(3)
629 #define PGA_RETURN_EN BIT(1)
632 #define EEE_CLKDIV_EN 0x8000
633 #define EN_ALDPS 0x0004
634 #define EN_10M_PLLOFF 0x0001
636 /* OCP_EEE_CONFIG1 */
637 #define RG_TXLPI_MSK_HFDUP 0x8000
638 #define RG_MATCLR_EN 0x4000
639 #define EEE_10_CAP 0x2000
640 #define EEE_NWAY_EN 0x1000
641 #define TX_QUIET_EN 0x0200
642 #define RX_QUIET_EN 0x0100
643 #define sd_rise_time_mask 0x0070
644 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
645 #define RG_RXLPI_MSK_HFDUP 0x0008
646 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
648 /* OCP_EEE_CONFIG2 */
649 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
650 #define RG_DACQUIET_EN 0x0400
651 #define RG_LDVQUIET_EN 0x0200
652 #define RG_CKRSEL 0x0020
653 #define RG_EEEPRG_EN 0x0010
655 /* OCP_EEE_CONFIG3 */
656 #define fast_snr_mask 0xff80
657 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
658 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
659 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
662 /* bit[15:14] function */
663 #define FUN_ADDR 0x0000
664 #define FUN_DATA 0x4000
665 /* bit[4:0] device addr */
668 #define CTAP_SHORT_EN 0x0040
669 #define EEE10_EN 0x0010
672 #define EN_EEE_CMODE BIT(14)
673 #define EN_EEE_1000 BIT(13)
674 #define EN_EEE_100 BIT(12)
675 #define EN_10M_CLKDIV BIT(11)
676 #define EN_10M_BGOFF 0x0080
679 #define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */
682 #define TXDIS_STATE 0x01
683 #define ABD_STATE 0x02
685 /* OCP_PHY_PATCH_STAT */
686 #define PATCH_READY BIT(6)
688 /* OCP_PHY_PATCH_CMD */
689 #define PATCH_REQUEST BIT(4)
692 #define PATCH_LOCK BIT(0)
695 #define CKADSEL_L 0x0100
696 #define ADC_EN 0x0080
697 #define EN_EMI_L 0x0040
700 #define sysclk_div_expo(x) (min(x, 5) << 8)
701 #define clk_div_expo(x) (min(x, 5) << 4)
704 #define GREEN_ETH_EN BIT(15)
705 #define R_TUNE_EN BIT(11)
708 #define LPF_AUTO_TUNE 0x8000
711 #define GDAC_IB_UPALL 0x0008
714 #define AMP_DN 0x0200
717 #define RX_DRIVING_MASK 0x6000
720 #define PHY_PATCH_LOCK 0x0001
723 #define AD_MASK 0xfee0
724 #define BND_MASK 0x0004
725 #define BD_MASK 0x0001
727 #define PASS_THRU_MASK 0x1
729 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
731 enum rtl_register_content {
744 #define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
745 #define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
747 #define RTL8152_MAX_TX 4
748 #define RTL8152_MAX_RX 10
753 #define RTL8152_RX_MAX_PENDING 4096
754 #define RTL8152_RXFG_HEADSZ 256
756 #define INTR_LINK 0x0004
758 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
759 #define RTL8153_RMS RTL8153_MAX_PACKET
760 #define RTL8152_TX_TIMEOUT (5 * HZ)
761 #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
762 #define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
763 #define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
778 #define DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB 0x721e
779 #define DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK 0x3054
780 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
781 #define DEVICE_ID_THINKPAD_USB_C_DONGLE 0x720c
782 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
783 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3 0x3062
785 struct tally_counter {
792 __le32 tx_one_collision;
793 __le32 tx_multi_collision;
803 #define RX_LEN_MASK 0x7fff
806 #define RD_UDP_CS BIT(23)
807 #define RD_TCP_CS BIT(22)
808 #define RD_IPV6_CS BIT(20)
809 #define RD_IPV4_CS BIT(19)
812 #define IPF BIT(23) /* IP checksum fail */
813 #define UDPF BIT(22) /* UDP checksum fail */
814 #define TCPF BIT(21) /* TCP checksum fail */
815 #define RX_VLAN_TAG BIT(16)
824 #define TX_FS BIT(31) /* First segment of a packet */
825 #define TX_LS BIT(30) /* Final segment of a packet */
826 #define GTSENDV4 BIT(28)
827 #define GTSENDV6 BIT(27)
828 #define GTTCPHO_SHIFT 18
829 #define GTTCPHO_MAX 0x7fU
830 #define TX_LEN_MAX 0x3ffffU
833 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
834 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
835 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
836 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
838 #define MSS_MAX 0x7ffU
839 #define TCPHO_SHIFT 17
840 #define TCPHO_MAX 0x7ffU
841 #define TX_VLAN_TAG BIT(16)
847 struct list_head list, info_list;
849 struct r8152 *context;
855 struct list_head list;
857 struct r8152 *context;
866 struct usb_device *udev;
867 struct napi_struct napi;
868 struct usb_interface *intf;
869 struct net_device *netdev;
870 struct urb *intr_urb;
871 struct tx_agg tx_info[RTL8152_MAX_TX];
872 struct list_head rx_info, rx_used;
873 struct list_head rx_done, tx_free;
874 struct sk_buff_head tx_queue, rx_queue;
875 spinlock_t rx_lock, tx_lock;
876 struct delayed_work schedule, hw_phy_work;
877 struct mii_if_info mii;
878 struct mutex control; /* use for hw setting */
879 #ifdef CONFIG_PM_SLEEP
880 struct notifier_block pm_notifier;
882 struct tasklet_struct tx_tl;
885 void (*init)(struct r8152 *tp);
886 int (*enable)(struct r8152 *tp);
887 void (*disable)(struct r8152 *tp);
888 void (*up)(struct r8152 *tp);
889 void (*down)(struct r8152 *tp);
890 void (*unload)(struct r8152 *tp);
891 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
892 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
893 bool (*in_nway)(struct r8152 *tp);
894 void (*hw_phy_cfg)(struct r8152 *tp);
895 void (*autosuspend_en)(struct r8152 *tp, bool enable);
896 void (*change_mtu)(struct r8152 *tp);
909 u32 eee_plloff_100:1;
910 u32 eee_plloff_giga:1;
914 u32 ctap_short_off:1;
917 #define RTL_VER_SIZE 32
921 const struct firmware *fw;
923 char version[RTL_VER_SIZE];
924 int (*pre_fw)(struct r8152 *tp);
925 int (*post_fw)(struct r8152 *tp);
942 u32 fc_pause_on, fc_pause_off;
944 unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out;
946 u32 support_2500full:1;
947 u32 lenovo_macpassthru:1;
948 u32 dell_tb_rx_agg_bug:1;
959 * struct fw_block - block type and total length
960 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
961 * RTL_FW_USB and so on.
962 * @length: total length of the current block.
970 * struct fw_header - header of the firmware file
971 * @checksum: checksum of sha256 which is calculated from the whole file
972 * except the checksum field of the file. That is, calculate sha256
973 * from the version field to the end of the file.
974 * @version: version of this firmware.
975 * @blocks: the first firmware block of the file
979 char version[RTL_VER_SIZE];
980 struct fw_block blocks[];
983 enum rtl8152_fw_flags {
997 enum rtl8152_fw_fixup_cmd {
1009 struct fw_phy_speed_up {
1010 struct fw_block blk_hdr;
1019 struct fw_block blk_hdr;
1020 struct fw_phy_set ver;
1024 struct fw_phy_fixup {
1025 struct fw_block blk_hdr;
1026 struct fw_phy_set setting;
1031 struct fw_phy_union {
1032 struct fw_block blk_hdr;
1035 struct fw_phy_set pre_set[2];
1036 struct fw_phy_set bp[8];
1037 struct fw_phy_set bp_en;
1044 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
1045 * The layout of the firmware block is:
1046 * <struct fw_mac> + <info> + <firmware data>.
1047 * @blk_hdr: firmware descriptor (type, length)
1048 * @fw_offset: offset of the firmware binary data. The start address of
1049 * the data would be the address of struct fw_mac + @fw_offset.
1050 * @fw_reg: the register to load the firmware. Depends on chip.
1051 * @bp_ba_addr: the register to write break point base address. Depends on
1053 * @bp_ba_value: break point base address. Depends on chip.
1054 * @bp_en_addr: the register to write break point enabled mask. Depends
1056 * @bp_en_value: break point enabled mask. Depends on the firmware.
1057 * @bp_start: the start register of break points. Depends on chip.
1058 * @bp_num: the break point number which needs to be set for this firmware.
1059 * Depends on the firmware.
1060 * @bp: break points. Depends on firmware.
1061 * @reserved: reserved space (unused)
1062 * @fw_ver_reg: the register to store the fw version.
1063 * @fw_ver_data: the firmware version of the current type.
1064 * @info: additional information for debugging, and is followed by the
1065 * binary data of firmware.
1068 struct fw_block blk_hdr;
1077 __le16 bp[16]; /* any value determined by firmware */
1085 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
1086 * This is used to set patch key when loading the firmware of PHY.
1087 * @blk_hdr: firmware descriptor (type, length)
1088 * @key_reg: the register to write the patch key.
1089 * @key_data: patch key.
1090 * @reserved: reserved space (unused)
1092 struct fw_phy_patch_key {
1093 struct fw_block blk_hdr;
1100 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
1101 * The layout of the firmware block is:
1102 * <struct fw_phy_nc> + <info> + <firmware data>.
1103 * @blk_hdr: firmware descriptor (type, length)
1104 * @fw_offset: offset of the firmware binary data. The start address of
1105 * the data would be the address of struct fw_phy_nc + @fw_offset.
1106 * @fw_reg: the register to load the firmware. Depends on chip.
1107 * @ba_reg: the register to write the base address. Depends on chip.
1108 * @ba_data: base address. Depends on chip.
1109 * @patch_en_addr: the register of enabling patch mode. Depends on chip.
1110 * @patch_en_value: patch mode enabled mask. Depends on the firmware.
1111 * @mode_reg: the regitster of switching the mode.
1112 * @mode_pre: the mode needing to be set before loading the firmware.
1113 * @mode_post: the mode to be set when finishing to load the firmware.
1114 * @reserved: reserved space (unused)
1115 * @bp_start: the start register of break points. Depends on chip.
1116 * @bp_num: the break point number which needs to be set for this firmware.
1117 * Depends on the firmware.
1118 * @bp: break points. Depends on firmware.
1119 * @info: additional information for debugging, and is followed by the
1120 * binary data of firmware.
1123 struct fw_block blk_hdr;
1128 __le16 patch_en_addr;
1129 __le16 patch_en_value;
1148 RTL_FW_PHY_UNION_NC,
1149 RTL_FW_PHY_UNION_NC1,
1150 RTL_FW_PHY_UNION_NC2,
1151 RTL_FW_PHY_UNION_UC2,
1152 RTL_FW_PHY_UNION_UC,
1153 RTL_FW_PHY_UNION_MISC,
1154 RTL_FW_PHY_SPEED_UP,
1159 RTL_VER_UNKNOWN = 0,
1182 TX_CSUM_SUCCESS = 0,
1187 #define RTL_ADVERTISED_10_HALF BIT(0)
1188 #define RTL_ADVERTISED_10_FULL BIT(1)
1189 #define RTL_ADVERTISED_100_HALF BIT(2)
1190 #define RTL_ADVERTISED_100_FULL BIT(3)
1191 #define RTL_ADVERTISED_1000_HALF BIT(4)
1192 #define RTL_ADVERTISED_1000_FULL BIT(5)
1193 #define RTL_ADVERTISED_2500_FULL BIT(6)
1195 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1196 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1198 static const int multicast_filter_limit = 32;
1199 static unsigned int agg_buf_sz = 16384;
1201 #define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))
1204 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1209 tmp = kmalloc(size, GFP_KERNEL);
1213 ret = usb_control_msg(tp->udev, tp->pipe_ctrl_in,
1214 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1215 value, index, tmp, size, 500);
1217 memset(data, 0xff, size);
1219 memcpy(data, tmp, size);
1227 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1232 tmp = kmemdup(data, size, GFP_KERNEL);
1236 ret = usb_control_msg(tp->udev, tp->pipe_ctrl_out,
1237 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1238 value, index, tmp, size, 500);
1245 static void rtl_set_unplug(struct r8152 *tp)
1247 if (tp->udev->state == USB_STATE_NOTATTACHED) {
1248 set_bit(RTL8152_UNPLUG, &tp->flags);
1249 smp_mb__after_atomic();
1253 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1254 void *data, u16 type)
1259 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1262 /* both size and indix must be 4 bytes align */
1263 if ((size & 3) || !size || (index & 3) || !data)
1266 if ((u32)index + (u32)size > 0xffff)
1271 ret = get_registers(tp, index, type, limit, data);
1279 ret = get_registers(tp, index, type, size, data);
1296 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1297 u16 size, void *data, u16 type)
1300 u16 byteen_start, byteen_end, byen;
1303 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1306 /* both size and indix must be 4 bytes align */
1307 if ((size & 3) || !size || (index & 3) || !data)
1310 if ((u32)index + (u32)size > 0xffff)
1313 byteen_start = byteen & BYTE_EN_START_MASK;
1314 byteen_end = byteen & BYTE_EN_END_MASK;
1316 byen = byteen_start | (byteen_start << 4);
1318 /* Split the first DWORD if the byte_en is not 0xff */
1319 if (byen != BYTE_EN_DWORD) {
1320 ret = set_registers(tp, index, type | byen, 4, data);
1330 byen = byteen_end | (byteen_end >> 4);
1332 /* Split the last DWORD if the byte_en is not 0xff */
1333 if (byen != BYTE_EN_DWORD)
1338 ret = set_registers(tp, index,
1339 type | BYTE_EN_DWORD,
1348 ret = set_registers(tp, index,
1349 type | BYTE_EN_DWORD,
1361 /* Set the last DWORD */
1362 if (byen != BYTE_EN_DWORD)
1363 ret = set_registers(tp, index, type | byen, 4, data);
1374 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1376 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1380 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1382 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1386 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1388 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1391 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1395 generic_ocp_read(tp, index, sizeof(data), &data, type);
1397 return __le32_to_cpu(data);
1400 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1402 __le32 tmp = __cpu_to_le32(data);
1404 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1407 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1411 u16 byen = BYTE_EN_WORD;
1412 u8 shift = index & 2;
1417 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1419 data = __le32_to_cpu(tmp);
1420 data >>= (shift * 8);
1426 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1430 u16 byen = BYTE_EN_WORD;
1431 u8 shift = index & 2;
1437 mask <<= (shift * 8);
1438 data <<= (shift * 8);
1442 tmp = __cpu_to_le32(data);
1444 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1447 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1451 u8 shift = index & 3;
1455 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1457 data = __le32_to_cpu(tmp);
1458 data >>= (shift * 8);
1464 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1468 u16 byen = BYTE_EN_BYTE;
1469 u8 shift = index & 3;
1475 mask <<= (shift * 8);
1476 data <<= (shift * 8);
1480 tmp = __cpu_to_le32(data);
1482 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1485 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1487 u16 ocp_base, ocp_index;
1489 ocp_base = addr & 0xf000;
1490 if (ocp_base != tp->ocp_base) {
1491 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1492 tp->ocp_base = ocp_base;
1495 ocp_index = (addr & 0x0fff) | 0xb000;
1496 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1499 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1501 u16 ocp_base, ocp_index;
1503 ocp_base = addr & 0xf000;
1504 if (ocp_base != tp->ocp_base) {
1505 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1506 tp->ocp_base = ocp_base;
1509 ocp_index = (addr & 0x0fff) | 0xb000;
1510 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1513 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1515 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1518 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1520 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1523 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1525 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1526 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1529 static u16 sram_read(struct r8152 *tp, u16 addr)
1531 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1532 return ocp_reg_read(tp, OCP_SRAM_DATA);
1535 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1537 struct r8152 *tp = netdev_priv(netdev);
1540 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1543 if (phy_id != R8152_PHY_ID)
1546 ret = r8152_mdio_read(tp, reg);
1552 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1554 struct r8152 *tp = netdev_priv(netdev);
1556 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1559 if (phy_id != R8152_PHY_ID)
1562 r8152_mdio_write(tp, reg, val);
1566 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1569 rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1572 static int __rtl8152_set_mac_address(struct net_device *netdev, void *p,
1575 struct r8152 *tp = netdev_priv(netdev);
1576 struct sockaddr *addr = p;
1577 int ret = -EADDRNOTAVAIL;
1579 if (!is_valid_ether_addr(addr->sa_data))
1583 ret = usb_autopm_get_interface(tp->intf);
1588 mutex_lock(&tp->control);
1590 eth_hw_addr_set(netdev, addr->sa_data);
1592 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1593 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1594 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1596 mutex_unlock(&tp->control);
1599 usb_autopm_put_interface(tp->intf);
1604 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1606 return __rtl8152_set_mac_address(netdev, p, false);
1609 /* Devices containing proper chips can support a persistent
1610 * host system provided MAC address.
1611 * Examples of this are Dell TB15 and Dell WD15 docks
1613 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1616 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1617 union acpi_object *obj;
1620 unsigned char buf[6];
1622 acpi_object_type mac_obj_type;
1625 if (tp->lenovo_macpassthru) {
1626 mac_obj_name = "\\MACA";
1627 mac_obj_type = ACPI_TYPE_STRING;
1630 /* test for -AD variant of RTL8153 */
1631 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1632 if ((ocp_data & AD_MASK) == 0x1000) {
1633 /* test for MAC address pass-through bit */
1634 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1635 if ((ocp_data & PASS_THRU_MASK) != 1) {
1636 netif_dbg(tp, probe, tp->netdev,
1637 "No efuse for RTL8153-AD MAC pass through\n");
1641 /* test for RTL8153-BND and RTL8153-BD */
1642 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1643 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1644 netif_dbg(tp, probe, tp->netdev,
1645 "Invalid variant for MAC pass through\n");
1650 mac_obj_name = "\\_SB.AMAC";
1651 mac_obj_type = ACPI_TYPE_BUFFER;
1655 /* returns _AUXMAC_#AABBCCDDEEFF# */
1656 status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1657 obj = (union acpi_object *)buffer.pointer;
1658 if (!ACPI_SUCCESS(status))
1660 if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1661 netif_warn(tp, probe, tp->netdev,
1662 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1663 obj->type, obj->string.length);
1667 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1668 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1669 netif_warn(tp, probe, tp->netdev,
1670 "Invalid header when reading pass-thru MAC addr\n");
1673 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1674 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1675 netif_warn(tp, probe, tp->netdev,
1676 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1681 memcpy(sa->sa_data, buf, 6);
1682 netif_info(tp, probe, tp->netdev,
1683 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1690 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1692 struct net_device *dev = tp->netdev;
1695 sa->sa_family = dev->type;
1697 ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1699 if (tp->version == RTL_VER_01) {
1700 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1702 /* if device doesn't support MAC pass through this will
1703 * be expected to be non-zero
1705 ret = vendor_mac_passthru_addr_read(tp, sa);
1707 ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1713 netif_err(tp, probe, dev, "Get ether addr fail\n");
1714 } else if (!is_valid_ether_addr(sa->sa_data)) {
1715 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1717 eth_hw_addr_random(dev);
1718 ether_addr_copy(sa->sa_data, dev->dev_addr);
1719 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1727 static int set_ethernet_addr(struct r8152 *tp, bool in_resume)
1729 struct net_device *dev = tp->netdev;
1733 ret = determine_ethernet_addr(tp, &sa);
1737 if (tp->version == RTL_VER_01)
1738 eth_hw_addr_set(dev, sa.sa_data);
1740 ret = __rtl8152_set_mac_address(dev, &sa, in_resume);
1745 static void read_bulk_callback(struct urb *urb)
1747 struct net_device *netdev;
1748 int status = urb->status;
1751 unsigned long flags;
1761 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1764 if (!test_bit(WORK_ENABLE, &tp->flags))
1767 netdev = tp->netdev;
1769 /* When link down, the driver would cancel all bulks. */
1770 /* This avoid the re-submitting bulk */
1771 if (!netif_carrier_ok(netdev))
1774 usb_mark_last_busy(tp->udev);
1778 if (urb->actual_length < ETH_ZLEN)
1781 spin_lock_irqsave(&tp->rx_lock, flags);
1782 list_add_tail(&agg->list, &tp->rx_done);
1783 spin_unlock_irqrestore(&tp->rx_lock, flags);
1784 napi_schedule(&tp->napi);
1788 netif_device_detach(tp->netdev);
1791 urb->actual_length = 0;
1792 spin_lock_irqsave(&tp->rx_lock, flags);
1793 list_add_tail(&agg->list, &tp->rx_done);
1794 spin_unlock_irqrestore(&tp->rx_lock, flags);
1795 set_bit(RX_EPROTO, &tp->flags);
1796 schedule_delayed_work(&tp->schedule, 1);
1799 return; /* the urb is in unlink state */
1801 if (net_ratelimit())
1802 netdev_warn(netdev, "maybe reset is needed?\n");
1805 if (net_ratelimit())
1806 netdev_warn(netdev, "Rx status %d\n", status);
1810 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1813 static void write_bulk_callback(struct urb *urb)
1815 struct net_device_stats *stats;
1816 struct net_device *netdev;
1819 unsigned long flags;
1820 int status = urb->status;
1830 netdev = tp->netdev;
1831 stats = &netdev->stats;
1833 if (net_ratelimit())
1834 netdev_warn(netdev, "Tx status %d\n", status);
1835 stats->tx_errors += agg->skb_num;
1837 stats->tx_packets += agg->skb_num;
1838 stats->tx_bytes += agg->skb_len;
1841 spin_lock_irqsave(&tp->tx_lock, flags);
1842 list_add_tail(&agg->list, &tp->tx_free);
1843 spin_unlock_irqrestore(&tp->tx_lock, flags);
1845 usb_autopm_put_interface_async(tp->intf);
1847 if (!netif_carrier_ok(netdev))
1850 if (!test_bit(WORK_ENABLE, &tp->flags))
1853 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1856 if (!skb_queue_empty(&tp->tx_queue))
1857 tasklet_schedule(&tp->tx_tl);
1860 static void intr_callback(struct urb *urb)
1864 int status = urb->status;
1871 if (!test_bit(WORK_ENABLE, &tp->flags))
1874 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1878 case 0: /* success */
1880 case -ECONNRESET: /* unlink */
1882 netif_device_detach(tp->netdev);
1886 netif_info(tp, intr, tp->netdev,
1887 "Stop submitting intr, status %d\n", status);
1890 if (net_ratelimit())
1891 netif_info(tp, intr, tp->netdev,
1892 "intr status -EOVERFLOW\n");
1894 /* -EPIPE: should clear the halt */
1896 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1900 d = urb->transfer_buffer;
1901 if (INTR_LINK & __le16_to_cpu(d[0])) {
1902 if (!netif_carrier_ok(tp->netdev)) {
1903 set_bit(RTL8152_LINK_CHG, &tp->flags);
1904 schedule_delayed_work(&tp->schedule, 0);
1907 if (netif_carrier_ok(tp->netdev)) {
1908 netif_stop_queue(tp->netdev);
1909 set_bit(RTL8152_LINK_CHG, &tp->flags);
1910 schedule_delayed_work(&tp->schedule, 0);
1915 res = usb_submit_urb(urb, GFP_ATOMIC);
1916 if (res == -ENODEV) {
1918 netif_device_detach(tp->netdev);
1920 netif_err(tp, intr, tp->netdev,
1921 "can't resubmit intr, status %d\n", res);
1925 static inline void *rx_agg_align(void *data)
1927 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1930 static inline void *tx_agg_align(void *data)
1932 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1935 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1937 list_del(&agg->info_list);
1939 usb_free_urb(agg->urb);
1940 put_page(agg->page);
1943 atomic_dec(&tp->rx_count);
1946 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1948 struct net_device *netdev = tp->netdev;
1949 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1950 unsigned int order = get_order(tp->rx_buf_sz);
1951 struct rx_agg *rx_agg;
1952 unsigned long flags;
1954 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1958 rx_agg->page = alloc_pages(mflags | __GFP_COMP | __GFP_NOWARN, order);
1962 rx_agg->buffer = page_address(rx_agg->page);
1964 rx_agg->urb = usb_alloc_urb(0, mflags);
1968 rx_agg->context = tp;
1970 INIT_LIST_HEAD(&rx_agg->list);
1971 INIT_LIST_HEAD(&rx_agg->info_list);
1972 spin_lock_irqsave(&tp->rx_lock, flags);
1973 list_add_tail(&rx_agg->info_list, &tp->rx_info);
1974 spin_unlock_irqrestore(&tp->rx_lock, flags);
1976 atomic_inc(&tp->rx_count);
1981 __free_pages(rx_agg->page, order);
1987 static void free_all_mem(struct r8152 *tp)
1989 struct rx_agg *agg, *agg_next;
1990 unsigned long flags;
1993 spin_lock_irqsave(&tp->rx_lock, flags);
1995 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1996 free_rx_agg(tp, agg);
1998 spin_unlock_irqrestore(&tp->rx_lock, flags);
2000 WARN_ON(atomic_read(&tp->rx_count));
2002 for (i = 0; i < RTL8152_MAX_TX; i++) {
2003 usb_free_urb(tp->tx_info[i].urb);
2004 tp->tx_info[i].urb = NULL;
2006 kfree(tp->tx_info[i].buffer);
2007 tp->tx_info[i].buffer = NULL;
2008 tp->tx_info[i].head = NULL;
2011 usb_free_urb(tp->intr_urb);
2012 tp->intr_urb = NULL;
2014 kfree(tp->intr_buff);
2015 tp->intr_buff = NULL;
2018 static int alloc_all_mem(struct r8152 *tp)
2020 struct net_device *netdev = tp->netdev;
2021 struct usb_interface *intf = tp->intf;
2022 struct usb_host_interface *alt = intf->cur_altsetting;
2023 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
2026 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
2028 spin_lock_init(&tp->rx_lock);
2029 spin_lock_init(&tp->tx_lock);
2030 INIT_LIST_HEAD(&tp->rx_info);
2031 INIT_LIST_HEAD(&tp->tx_free);
2032 INIT_LIST_HEAD(&tp->rx_done);
2033 skb_queue_head_init(&tp->tx_queue);
2034 skb_queue_head_init(&tp->rx_queue);
2035 atomic_set(&tp->rx_count, 0);
2037 for (i = 0; i < RTL8152_MAX_RX; i++) {
2038 if (!alloc_rx_agg(tp, GFP_KERNEL))
2042 for (i = 0; i < RTL8152_MAX_TX; i++) {
2046 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
2050 if (buf != tx_agg_align(buf)) {
2052 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
2058 urb = usb_alloc_urb(0, GFP_KERNEL);
2064 INIT_LIST_HEAD(&tp->tx_info[i].list);
2065 tp->tx_info[i].context = tp;
2066 tp->tx_info[i].urb = urb;
2067 tp->tx_info[i].buffer = buf;
2068 tp->tx_info[i].head = tx_agg_align(buf);
2070 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
2073 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
2077 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
2081 tp->intr_interval = (int)ep_intr->desc.bInterval;
2082 usb_fill_int_urb(tp->intr_urb, tp->udev, tp->pipe_intr,
2083 tp->intr_buff, INTBUFSIZE, intr_callback,
2084 tp, tp->intr_interval);
2093 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
2095 struct tx_agg *agg = NULL;
2096 unsigned long flags;
2098 if (list_empty(&tp->tx_free))
2101 spin_lock_irqsave(&tp->tx_lock, flags);
2102 if (!list_empty(&tp->tx_free)) {
2103 struct list_head *cursor;
2105 cursor = tp->tx_free.next;
2106 list_del_init(cursor);
2107 agg = list_entry(cursor, struct tx_agg, list);
2109 spin_unlock_irqrestore(&tp->tx_lock, flags);
2114 /* r8152_csum_workaround()
2115 * The hw limits the value of the transport offset. When the offset is out of
2116 * range, calculate the checksum by sw.
2118 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
2119 struct sk_buff_head *list)
2121 if (skb_shinfo(skb)->gso_size) {
2122 netdev_features_t features = tp->netdev->features;
2123 struct sk_buff *segs, *seg, *next;
2124 struct sk_buff_head seg_list;
2126 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
2127 segs = skb_gso_segment(skb, features);
2128 if (IS_ERR(segs) || !segs)
2131 __skb_queue_head_init(&seg_list);
2133 skb_list_walk_safe(segs, seg, next) {
2134 skb_mark_not_on_list(seg);
2135 __skb_queue_tail(&seg_list, seg);
2138 skb_queue_splice(&seg_list, list);
2140 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2141 if (skb_checksum_help(skb) < 0)
2144 __skb_queue_head(list, skb);
2146 struct net_device_stats *stats;
2149 stats = &tp->netdev->stats;
2150 stats->tx_dropped++;
2155 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
2157 if (skb_vlan_tag_present(skb)) {
2160 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
2161 desc->opts2 |= cpu_to_le32(opts2);
2165 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
2167 u32 opts2 = le32_to_cpu(desc->opts2);
2169 if (opts2 & RX_VLAN_TAG)
2170 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2171 swab16(opts2 & 0xffff));
2174 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
2175 struct sk_buff *skb, u32 len)
2177 u32 mss = skb_shinfo(skb)->gso_size;
2178 u32 opts1, opts2 = 0;
2179 int ret = TX_CSUM_SUCCESS;
2181 WARN_ON_ONCE(len > TX_LEN_MAX);
2183 opts1 = len | TX_FS | TX_LS;
2186 u32 transport_offset = (u32)skb_transport_offset(skb);
2188 if (transport_offset > GTTCPHO_MAX) {
2189 netif_warn(tp, tx_err, tp->netdev,
2190 "Invalid transport offset 0x%x for TSO\n",
2196 switch (vlan_get_protocol(skb)) {
2197 case htons(ETH_P_IP):
2201 case htons(ETH_P_IPV6):
2202 if (skb_cow_head(skb, 0)) {
2206 tcp_v6_gso_csum_prep(skb);
2215 opts1 |= transport_offset << GTTCPHO_SHIFT;
2216 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2217 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2218 u32 transport_offset = (u32)skb_transport_offset(skb);
2221 if (transport_offset > TCPHO_MAX) {
2222 netif_warn(tp, tx_err, tp->netdev,
2223 "Invalid transport offset 0x%x\n",
2229 switch (vlan_get_protocol(skb)) {
2230 case htons(ETH_P_IP):
2232 ip_protocol = ip_hdr(skb)->protocol;
2235 case htons(ETH_P_IPV6):
2237 ip_protocol = ipv6_hdr(skb)->nexthdr;
2241 ip_protocol = IPPROTO_RAW;
2245 if (ip_protocol == IPPROTO_TCP)
2247 else if (ip_protocol == IPPROTO_UDP)
2252 opts2 |= transport_offset << TCPHO_SHIFT;
2255 desc->opts2 = cpu_to_le32(opts2);
2256 desc->opts1 = cpu_to_le32(opts1);
2262 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2264 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2268 __skb_queue_head_init(&skb_head);
2269 spin_lock(&tx_queue->lock);
2270 skb_queue_splice_init(tx_queue, &skb_head);
2271 spin_unlock(&tx_queue->lock);
2273 tx_data = agg->head;
2276 remain = agg_buf_sz;
2278 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2279 struct tx_desc *tx_desc;
2280 struct sk_buff *skb;
2283 skb = __skb_dequeue(&skb_head);
2287 len = skb->len + sizeof(*tx_desc);
2290 __skb_queue_head(&skb_head, skb);
2294 tx_data = tx_agg_align(tx_data);
2295 tx_desc = (struct tx_desc *)tx_data;
2297 if (r8152_tx_csum(tp, tx_desc, skb, skb->len)) {
2298 r8152_csum_workaround(tp, skb, &skb_head);
2302 rtl_tx_vlan_tag(tx_desc, skb);
2304 tx_data += sizeof(*tx_desc);
2307 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2308 struct net_device_stats *stats = &tp->netdev->stats;
2310 stats->tx_dropped++;
2311 dev_kfree_skb_any(skb);
2312 tx_data -= sizeof(*tx_desc);
2317 agg->skb_len += len;
2318 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2320 dev_kfree_skb_any(skb);
2322 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2324 if (tp->dell_tb_rx_agg_bug)
2328 if (!skb_queue_empty(&skb_head)) {
2329 spin_lock(&tx_queue->lock);
2330 skb_queue_splice(&skb_head, tx_queue);
2331 spin_unlock(&tx_queue->lock);
2334 netif_tx_lock(tp->netdev);
2336 if (netif_queue_stopped(tp->netdev) &&
2337 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2338 netif_wake_queue(tp->netdev);
2340 netif_tx_unlock(tp->netdev);
2342 ret = usb_autopm_get_interface_async(tp->intf);
2346 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_out,
2347 agg->head, (int)(tx_data - (u8 *)agg->head),
2348 (usb_complete_t)write_bulk_callback, agg);
2350 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2352 usb_autopm_put_interface_async(tp->intf);
2358 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2360 u8 checksum = CHECKSUM_NONE;
2363 if (!(tp->netdev->features & NETIF_F_RXCSUM))
2366 opts2 = le32_to_cpu(rx_desc->opts2);
2367 opts3 = le32_to_cpu(rx_desc->opts3);
2369 if (opts2 & RD_IPV4_CS) {
2371 checksum = CHECKSUM_NONE;
2372 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2373 checksum = CHECKSUM_UNNECESSARY;
2374 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2375 checksum = CHECKSUM_UNNECESSARY;
2376 } else if (opts2 & RD_IPV6_CS) {
2377 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2378 checksum = CHECKSUM_UNNECESSARY;
2379 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2380 checksum = CHECKSUM_UNNECESSARY;
2387 static inline bool rx_count_exceed(struct r8152 *tp)
2389 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2392 static inline int agg_offset(struct rx_agg *agg, void *addr)
2394 return (int)(addr - agg->buffer);
2397 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2399 struct rx_agg *agg, *agg_next, *agg_free = NULL;
2400 unsigned long flags;
2402 spin_lock_irqsave(&tp->rx_lock, flags);
2404 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2405 if (page_count(agg->page) == 1) {
2407 list_del_init(&agg->list);
2411 if (rx_count_exceed(tp)) {
2412 list_del_init(&agg->list);
2413 free_rx_agg(tp, agg);
2419 spin_unlock_irqrestore(&tp->rx_lock, flags);
2421 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2422 agg_free = alloc_rx_agg(tp, mflags);
2427 static int rx_bottom(struct r8152 *tp, int budget)
2429 unsigned long flags;
2430 struct list_head *cursor, *next, rx_queue;
2431 int ret = 0, work_done = 0;
2432 struct napi_struct *napi = &tp->napi;
2434 if (!skb_queue_empty(&tp->rx_queue)) {
2435 while (work_done < budget) {
2436 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2437 struct net_device *netdev = tp->netdev;
2438 struct net_device_stats *stats = &netdev->stats;
2439 unsigned int pkt_len;
2445 napi_gro_receive(napi, skb);
2447 stats->rx_packets++;
2448 stats->rx_bytes += pkt_len;
2452 if (list_empty(&tp->rx_done))
2455 clear_bit(RX_EPROTO, &tp->flags);
2456 INIT_LIST_HEAD(&rx_queue);
2457 spin_lock_irqsave(&tp->rx_lock, flags);
2458 list_splice_init(&tp->rx_done, &rx_queue);
2459 spin_unlock_irqrestore(&tp->rx_lock, flags);
2461 list_for_each_safe(cursor, next, &rx_queue) {
2462 struct rx_desc *rx_desc;
2463 struct rx_agg *agg, *agg_free;
2468 list_del_init(cursor);
2470 agg = list_entry(cursor, struct rx_agg, list);
2472 if (urb->status != 0 || urb->actual_length < ETH_ZLEN)
2475 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2477 rx_desc = agg->buffer;
2478 rx_data = agg->buffer;
2479 len_used += sizeof(struct rx_desc);
2481 while (urb->actual_length > len_used) {
2482 struct net_device *netdev = tp->netdev;
2483 struct net_device_stats *stats = &netdev->stats;
2484 unsigned int pkt_len, rx_frag_head_sz;
2485 struct sk_buff *skb;
2487 /* limit the skb numbers for rx_queue */
2488 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2491 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2492 if (pkt_len < ETH_ZLEN)
2495 len_used += pkt_len;
2496 if (urb->actual_length < len_used)
2499 pkt_len -= ETH_FCS_LEN;
2500 rx_data += sizeof(struct rx_desc);
2502 if (!agg_free || tp->rx_copybreak > pkt_len)
2503 rx_frag_head_sz = pkt_len;
2505 rx_frag_head_sz = tp->rx_copybreak;
2507 skb = napi_alloc_skb(napi, rx_frag_head_sz);
2509 stats->rx_dropped++;
2513 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2514 memcpy(skb->data, rx_data, rx_frag_head_sz);
2515 skb_put(skb, rx_frag_head_sz);
2516 pkt_len -= rx_frag_head_sz;
2517 rx_data += rx_frag_head_sz;
2519 skb_add_rx_frag(skb, 0, agg->page,
2520 agg_offset(agg, rx_data),
2522 SKB_DATA_ALIGN(pkt_len));
2523 get_page(agg->page);
2526 skb->protocol = eth_type_trans(skb, netdev);
2527 rtl_rx_vlan_tag(rx_desc, skb);
2528 if (work_done < budget) {
2530 stats->rx_packets++;
2531 stats->rx_bytes += skb->len;
2532 napi_gro_receive(napi, skb);
2534 __skb_queue_tail(&tp->rx_queue, skb);
2538 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2539 rx_desc = (struct rx_desc *)rx_data;
2540 len_used = agg_offset(agg, rx_data);
2541 len_used += sizeof(struct rx_desc);
2544 WARN_ON(!agg_free && page_count(agg->page) > 1);
2547 spin_lock_irqsave(&tp->rx_lock, flags);
2548 if (page_count(agg->page) == 1) {
2549 list_add(&agg_free->list, &tp->rx_used);
2551 list_add_tail(&agg->list, &tp->rx_used);
2555 spin_unlock_irqrestore(&tp->rx_lock, flags);
2560 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2562 urb->actual_length = 0;
2563 list_add_tail(&agg->list, next);
2567 if (!list_empty(&rx_queue)) {
2568 spin_lock_irqsave(&tp->rx_lock, flags);
2569 list_splice_tail(&rx_queue, &tp->rx_done);
2570 spin_unlock_irqrestore(&tp->rx_lock, flags);
2577 static void tx_bottom(struct r8152 *tp)
2582 struct net_device *netdev = tp->netdev;
2585 if (skb_queue_empty(&tp->tx_queue))
2588 agg = r8152_get_tx_agg(tp);
2592 res = r8152_tx_agg_fill(tp, agg);
2596 if (res == -ENODEV) {
2598 netif_device_detach(netdev);
2600 struct net_device_stats *stats = &netdev->stats;
2601 unsigned long flags;
2603 netif_warn(tp, tx_err, netdev,
2604 "failed tx_urb %d\n", res);
2605 stats->tx_dropped += agg->skb_num;
2607 spin_lock_irqsave(&tp->tx_lock, flags);
2608 list_add_tail(&agg->list, &tp->tx_free);
2609 spin_unlock_irqrestore(&tp->tx_lock, flags);
2614 static void bottom_half(struct tasklet_struct *t)
2616 struct r8152 *tp = from_tasklet(tp, t, tx_tl);
2618 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2621 if (!test_bit(WORK_ENABLE, &tp->flags))
2624 /* When link down, the driver would cancel all bulks. */
2625 /* This avoid the re-submitting bulk */
2626 if (!netif_carrier_ok(tp->netdev))
2629 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2634 static int r8152_poll(struct napi_struct *napi, int budget)
2636 struct r8152 *tp = container_of(napi, struct r8152, napi);
2639 work_done = rx_bottom(tp, budget);
2641 if (work_done < budget) {
2642 if (!napi_complete_done(napi, work_done))
2644 if (!list_empty(&tp->rx_done))
2645 napi_schedule(napi);
2653 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2657 /* The rx would be stopped, so skip submitting */
2658 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2659 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2662 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_in,
2663 agg->buffer, tp->rx_buf_sz,
2664 (usb_complete_t)read_bulk_callback, agg);
2666 ret = usb_submit_urb(agg->urb, mem_flags);
2667 if (ret == -ENODEV) {
2669 netif_device_detach(tp->netdev);
2671 struct urb *urb = agg->urb;
2672 unsigned long flags;
2674 urb->actual_length = 0;
2675 spin_lock_irqsave(&tp->rx_lock, flags);
2676 list_add_tail(&agg->list, &tp->rx_done);
2677 spin_unlock_irqrestore(&tp->rx_lock, flags);
2679 netif_err(tp, rx_err, tp->netdev,
2680 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2682 napi_schedule(&tp->napi);
2688 static void rtl_drop_queued_tx(struct r8152 *tp)
2690 struct net_device_stats *stats = &tp->netdev->stats;
2691 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2692 struct sk_buff *skb;
2694 if (skb_queue_empty(tx_queue))
2697 __skb_queue_head_init(&skb_head);
2698 spin_lock_bh(&tx_queue->lock);
2699 skb_queue_splice_init(tx_queue, &skb_head);
2700 spin_unlock_bh(&tx_queue->lock);
2702 while ((skb = __skb_dequeue(&skb_head))) {
2704 stats->tx_dropped++;
2708 static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2710 struct r8152 *tp = netdev_priv(netdev);
2712 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2714 usb_queue_reset_device(tp->intf);
2717 static void rtl8152_set_rx_mode(struct net_device *netdev)
2719 struct r8152 *tp = netdev_priv(netdev);
2721 if (netif_carrier_ok(netdev)) {
2722 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2723 schedule_delayed_work(&tp->schedule, 0);
2727 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2729 struct r8152 *tp = netdev_priv(netdev);
2730 u32 mc_filter[2]; /* Multicast hash filter */
2734 netif_stop_queue(netdev);
2735 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2736 ocp_data &= ~RCR_ACPT_ALL;
2737 ocp_data |= RCR_AB | RCR_APM;
2739 if (netdev->flags & IFF_PROMISC) {
2740 /* Unconditionally log net taps. */
2741 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2742 ocp_data |= RCR_AM | RCR_AAP;
2743 mc_filter[1] = 0xffffffff;
2744 mc_filter[0] = 0xffffffff;
2745 } else if ((netdev->flags & IFF_MULTICAST &&
2746 netdev_mc_count(netdev) > multicast_filter_limit) ||
2747 (netdev->flags & IFF_ALLMULTI)) {
2748 /* Too many to filter perfectly -- accept all multicasts. */
2750 mc_filter[1] = 0xffffffff;
2751 mc_filter[0] = 0xffffffff;
2756 if (netdev->flags & IFF_MULTICAST) {
2757 struct netdev_hw_addr *ha;
2759 netdev_for_each_mc_addr(ha, netdev) {
2760 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2762 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2768 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2769 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2771 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2772 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2773 netif_wake_queue(netdev);
2776 static netdev_features_t
2777 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2778 netdev_features_t features)
2780 u32 mss = skb_shinfo(skb)->gso_size;
2781 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2783 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) &&
2784 skb_transport_offset(skb) > max_offset)
2785 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2786 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2787 features &= ~NETIF_F_GSO_MASK;
2792 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2793 struct net_device *netdev)
2795 struct r8152 *tp = netdev_priv(netdev);
2797 skb_tx_timestamp(skb);
2799 skb_queue_tail(&tp->tx_queue, skb);
2801 if (!list_empty(&tp->tx_free)) {
2802 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2803 set_bit(SCHEDULE_TASKLET, &tp->flags);
2804 schedule_delayed_work(&tp->schedule, 0);
2806 usb_mark_last_busy(tp->udev);
2807 tasklet_schedule(&tp->tx_tl);
2809 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2810 netif_stop_queue(netdev);
2813 return NETDEV_TX_OK;
2816 static void r8152b_reset_packet_filter(struct r8152 *tp)
2820 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2821 ocp_data &= ~FMC_FCR_MCU_EN;
2822 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2823 ocp_data |= FMC_FCR_MCU_EN;
2824 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2827 static void rtl8152_nic_reset(struct r8152 *tp)
2832 switch (tp->version) {
2836 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2838 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2840 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2841 ocp_data &= ~BMU_RESET_EP_IN;
2842 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2844 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2845 ocp_data |= CDC_ECM_EN;
2846 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2848 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2850 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2852 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2853 ocp_data |= BMU_RESET_EP_IN;
2854 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2856 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2857 ocp_data &= ~CDC_ECM_EN;
2858 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2862 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2864 for (i = 0; i < 1000; i++) {
2865 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2867 usleep_range(100, 400);
2873 static void set_tx_qlen(struct r8152 *tp)
2875 tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
2878 static inline u16 rtl8152_get_speed(struct r8152 *tp)
2880 return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2883 static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
2887 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2889 ocp_data |= EEEP_CR_EEEP_TX;
2891 ocp_data &= ~EEEP_CR_EEEP_TX;
2892 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2895 static void rtl_set_eee_plus(struct r8152 *tp)
2897 if (rtl8152_get_speed(tp) & _10bps)
2898 rtl_eee_plus_en(tp, true);
2900 rtl_eee_plus_en(tp, false);
2903 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2907 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2909 ocp_data |= RXDY_GATED_EN;
2911 ocp_data &= ~RXDY_GATED_EN;
2912 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2915 static int rtl_start_rx(struct r8152 *tp)
2917 struct rx_agg *agg, *agg_next;
2918 struct list_head tmp_list;
2919 unsigned long flags;
2922 INIT_LIST_HEAD(&tmp_list);
2924 spin_lock_irqsave(&tp->rx_lock, flags);
2926 INIT_LIST_HEAD(&tp->rx_done);
2927 INIT_LIST_HEAD(&tp->rx_used);
2929 list_splice_init(&tp->rx_info, &tmp_list);
2931 spin_unlock_irqrestore(&tp->rx_lock, flags);
2933 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2934 INIT_LIST_HEAD(&agg->list);
2936 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2937 if (++i > RTL8152_MAX_RX) {
2938 spin_lock_irqsave(&tp->rx_lock, flags);
2939 list_add_tail(&agg->list, &tp->rx_used);
2940 spin_unlock_irqrestore(&tp->rx_lock, flags);
2941 } else if (unlikely(ret < 0)) {
2942 spin_lock_irqsave(&tp->rx_lock, flags);
2943 list_add_tail(&agg->list, &tp->rx_done);
2944 spin_unlock_irqrestore(&tp->rx_lock, flags);
2946 ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2950 spin_lock_irqsave(&tp->rx_lock, flags);
2951 WARN_ON(!list_empty(&tp->rx_info));
2952 list_splice(&tmp_list, &tp->rx_info);
2953 spin_unlock_irqrestore(&tp->rx_lock, flags);
2958 static int rtl_stop_rx(struct r8152 *tp)
2960 struct rx_agg *agg, *agg_next;
2961 struct list_head tmp_list;
2962 unsigned long flags;
2964 INIT_LIST_HEAD(&tmp_list);
2966 /* The usb_kill_urb() couldn't be used in atomic.
2967 * Therefore, move the list of rx_info to a tmp one.
2968 * Then, list_for_each_entry_safe could be used without
2972 spin_lock_irqsave(&tp->rx_lock, flags);
2973 list_splice_init(&tp->rx_info, &tmp_list);
2974 spin_unlock_irqrestore(&tp->rx_lock, flags);
2976 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2977 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2978 * equal to 1, so the other ones could be freed safely.
2980 if (page_count(agg->page) > 1)
2981 free_rx_agg(tp, agg);
2983 usb_kill_urb(agg->urb);
2986 /* Move back the list of temp to the rx_info */
2987 spin_lock_irqsave(&tp->rx_lock, flags);
2988 WARN_ON(!list_empty(&tp->rx_info));
2989 list_splice(&tmp_list, &tp->rx_info);
2990 spin_unlock_irqrestore(&tp->rx_lock, flags);
2992 while (!skb_queue_empty(&tp->rx_queue))
2993 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2998 static void rtl_set_ifg(struct r8152 *tp, u16 speed)
3002 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3003 ocp_data &= ~IFG_MASK;
3004 if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
3005 ocp_data |= IFG_144NS;
3006 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
3008 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3009 ocp_data &= ~TX10MIDLE_EN;
3010 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
3012 ocp_data |= IFG_96NS;
3013 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
3015 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3016 ocp_data |= TX10MIDLE_EN;
3017 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
3021 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
3023 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
3024 OWN_UPDATE | OWN_CLEAR);
3027 static int rtl_enable(struct r8152 *tp)
3031 r8152b_reset_packet_filter(tp);
3033 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
3034 ocp_data |= CR_RE | CR_TE;
3035 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
3037 switch (tp->version) {
3047 r8153b_rx_agg_chg_indicate(tp);
3051 rxdy_gated_en(tp, false);
3056 static int rtl8152_enable(struct r8152 *tp)
3058 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3062 rtl_set_eee_plus(tp);
3064 return rtl_enable(tp);
3067 static void r8153_set_rx_early_timeout(struct r8152 *tp)
3069 u32 ocp_data = tp->coalesce / 8;
3071 switch (tp->version) {
3076 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3083 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
3084 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
3086 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3088 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3097 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3099 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3108 static void r8153_set_rx_early_size(struct r8152 *tp)
3110 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
3112 switch (tp->version) {
3117 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3123 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3132 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3141 static int rtl8153_enable(struct r8152 *tp)
3145 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3149 rtl_set_eee_plus(tp);
3150 r8153_set_rx_early_timeout(tp);
3151 r8153_set_rx_early_size(tp);
3153 rtl_set_ifg(tp, rtl8152_get_speed(tp));
3155 switch (tp->version) {
3158 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
3159 ocp_data &= ~FC_PATCH_TASK;
3160 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3161 usleep_range(1000, 2000);
3162 ocp_data |= FC_PATCH_TASK;
3163 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3169 return rtl_enable(tp);
3172 static void rtl_disable(struct r8152 *tp)
3177 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3178 rtl_drop_queued_tx(tp);
3182 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3183 ocp_data &= ~RCR_ACPT_ALL;
3184 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3186 rtl_drop_queued_tx(tp);
3188 for (i = 0; i < RTL8152_MAX_TX; i++)
3189 usb_kill_urb(tp->tx_info[i].urb);
3191 rxdy_gated_en(tp, true);
3193 for (i = 0; i < 1000; i++) {
3194 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3195 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
3197 usleep_range(1000, 2000);
3200 for (i = 0; i < 1000; i++) {
3201 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
3203 usleep_range(1000, 2000);
3208 rtl8152_nic_reset(tp);
3211 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
3215 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
3217 ocp_data |= POWER_CUT;
3219 ocp_data &= ~POWER_CUT;
3220 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
3222 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
3223 ocp_data &= ~RESUME_INDICATE;
3224 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
3227 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
3231 switch (tp->version) {
3242 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
3244 ocp_data |= CPCR_RX_VLAN;
3246 ocp_data &= ~CPCR_RX_VLAN;
3247 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
3257 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
3259 ocp_data |= OUTER_VLAN | INNER_VLAN;
3261 ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
3262 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);
3267 static int rtl8152_set_features(struct net_device *dev,
3268 netdev_features_t features)
3270 netdev_features_t changed = features ^ dev->features;
3271 struct r8152 *tp = netdev_priv(dev);
3274 ret = usb_autopm_get_interface(tp->intf);
3278 mutex_lock(&tp->control);
3280 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
3281 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3282 rtl_rx_vlan_en(tp, true);
3284 rtl_rx_vlan_en(tp, false);
3287 mutex_unlock(&tp->control);
3289 usb_autopm_put_interface(tp->intf);
3295 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
3297 static u32 __rtl_get_wol(struct r8152 *tp)
3302 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3303 if (ocp_data & LINK_ON_WAKE_EN)
3304 wolopts |= WAKE_PHY;
3306 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3307 if (ocp_data & UWF_EN)
3308 wolopts |= WAKE_UCAST;
3309 if (ocp_data & BWF_EN)
3310 wolopts |= WAKE_BCAST;
3311 if (ocp_data & MWF_EN)
3312 wolopts |= WAKE_MCAST;
3314 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3315 if (ocp_data & MAGIC_EN)
3316 wolopts |= WAKE_MAGIC;
3321 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3325 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3327 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3328 ocp_data &= ~LINK_ON_WAKE_EN;
3329 if (wolopts & WAKE_PHY)
3330 ocp_data |= LINK_ON_WAKE_EN;
3331 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3333 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3334 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3335 if (wolopts & WAKE_UCAST)
3337 if (wolopts & WAKE_BCAST)
3339 if (wolopts & WAKE_MCAST)
3341 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3343 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3345 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3346 ocp_data &= ~MAGIC_EN;
3347 if (wolopts & WAKE_MAGIC)
3348 ocp_data |= MAGIC_EN;
3349 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3351 if (wolopts & WAKE_ANY)
3352 device_set_wakeup_enable(&tp->udev->dev, true);
3354 device_set_wakeup_enable(&tp->udev->dev, false);
3357 static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
3359 u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3361 /* MAC clock speed down */
3363 ocp_data |= MAC_CLK_SPDWN_EN;
3365 ocp_data &= ~MAC_CLK_SPDWN_EN;
3367 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3370 static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
3374 /* MAC clock speed down */
3376 /* aldps_spdwn_ratio, tp10_spdwn_ratio */
3377 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3380 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3381 ocp_data &= ~EEE_SPDWN_RATIO_MASK;
3382 ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
3383 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3385 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3386 ocp_data &= ~MAC_CLK_SPDWN_EN;
3387 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3391 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3396 memset(u1u2, 0xff, sizeof(u1u2));
3398 memset(u1u2, 0x00, sizeof(u1u2));
3400 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3403 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3407 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3409 ocp_data |= LPM_U1U2_EN;
3411 ocp_data &= ~LPM_U1U2_EN;
3413 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3416 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3420 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3422 ocp_data |= U2P3_ENABLE;
3424 ocp_data &= ~U2P3_ENABLE;
3425 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3428 static void r8153b_ups_flags(struct r8152 *tp)
3432 if (tp->ups_info.green)
3433 ups_flags |= UPS_FLAGS_EN_GREEN;
3435 if (tp->ups_info.aldps)
3436 ups_flags |= UPS_FLAGS_EN_ALDPS;
3438 if (tp->ups_info.eee)
3439 ups_flags |= UPS_FLAGS_EN_EEE;
3441 if (tp->ups_info.flow_control)
3442 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3444 if (tp->ups_info.eee_ckdiv)
3445 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3447 if (tp->ups_info.eee_cmod_lv)
3448 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3450 if (tp->ups_info.r_tune)
3451 ups_flags |= UPS_FLAGS_R_TUNE;
3453 if (tp->ups_info._10m_ckdiv)
3454 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3456 if (tp->ups_info.eee_plloff_100)
3457 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3459 if (tp->ups_info.eee_plloff_giga)
3460 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3462 if (tp->ups_info._250m_ckdiv)
3463 ups_flags |= UPS_FLAGS_250M_CKDIV;
3465 if (tp->ups_info.ctap_short_off)
3466 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3468 switch (tp->ups_info.speed_duplex) {
3470 ups_flags |= ups_flags_speed(1);
3473 ups_flags |= ups_flags_speed(2);
3475 case NWAY_100M_HALF:
3476 ups_flags |= ups_flags_speed(3);
3478 case NWAY_100M_FULL:
3479 ups_flags |= ups_flags_speed(4);
3481 case NWAY_1000M_FULL:
3482 ups_flags |= ups_flags_speed(5);
3484 case FORCE_10M_HALF:
3485 ups_flags |= ups_flags_speed(6);
3487 case FORCE_10M_FULL:
3488 ups_flags |= ups_flags_speed(7);
3490 case FORCE_100M_HALF:
3491 ups_flags |= ups_flags_speed(8);
3493 case FORCE_100M_FULL:
3494 ups_flags |= ups_flags_speed(9);
3500 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3503 static void r8156_ups_flags(struct r8152 *tp)
3507 if (tp->ups_info.green)
3508 ups_flags |= UPS_FLAGS_EN_GREEN;
3510 if (tp->ups_info.aldps)
3511 ups_flags |= UPS_FLAGS_EN_ALDPS;
3513 if (tp->ups_info.eee)
3514 ups_flags |= UPS_FLAGS_EN_EEE;
3516 if (tp->ups_info.flow_control)
3517 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3519 if (tp->ups_info.eee_ckdiv)
3520 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3522 if (tp->ups_info._10m_ckdiv)
3523 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3525 if (tp->ups_info.eee_plloff_100)
3526 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3528 if (tp->ups_info.eee_plloff_giga)
3529 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3531 if (tp->ups_info._250m_ckdiv)
3532 ups_flags |= UPS_FLAGS_250M_CKDIV;
3534 switch (tp->ups_info.speed_duplex) {
3535 case FORCE_10M_HALF:
3536 ups_flags |= ups_flags_speed(0);
3538 case FORCE_10M_FULL:
3539 ups_flags |= ups_flags_speed(1);
3541 case FORCE_100M_HALF:
3542 ups_flags |= ups_flags_speed(2);
3544 case FORCE_100M_FULL:
3545 ups_flags |= ups_flags_speed(3);
3548 ups_flags |= ups_flags_speed(4);
3551 ups_flags |= ups_flags_speed(5);
3553 case NWAY_100M_HALF:
3554 ups_flags |= ups_flags_speed(6);
3556 case NWAY_100M_FULL:
3557 ups_flags |= ups_flags_speed(7);
3559 case NWAY_1000M_FULL:
3560 ups_flags |= ups_flags_speed(8);
3562 case NWAY_2500M_FULL:
3563 ups_flags |= ups_flags_speed(9);
3569 switch (tp->ups_info.lite_mode) {
3571 ups_flags |= 0 << 5;
3574 ups_flags |= 2 << 5;
3578 ups_flags |= 1 << 5;
3582 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3585 static void rtl_green_en(struct r8152 *tp, bool enable)
3589 data = sram_read(tp, SRAM_GREEN_CFG);
3591 data |= GREEN_ETH_EN;
3593 data &= ~GREEN_ETH_EN;
3594 sram_write(tp, SRAM_GREEN_CFG, data);
3596 tp->ups_info.green = enable;
3599 static void r8153b_green_en(struct r8152 *tp, bool enable)
3602 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
3603 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3604 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3606 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3607 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3608 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3611 rtl_green_en(tp, true);
3614 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3619 for (i = 0; i < 500; i++) {
3620 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3621 data &= PHY_STAT_MASK;
3623 if (data == desired)
3625 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3626 data == PHY_STAT_EXT_INIT) {
3631 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3638 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3640 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3643 r8153b_ups_flags(tp);
3645 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3646 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3648 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3649 ocp_data |= UPS_FORCE_PWR_DOWN;
3650 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3652 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3653 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3655 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3656 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3657 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3659 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3662 for (i = 0; i < 500; i++) {
3663 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3669 tp->rtl_ops.hw_phy_cfg(tp);
3671 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3672 tp->duplex, tp->advertising);
3677 static void r8153c_ups_en(struct r8152 *tp, bool enable)
3679 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3682 r8153b_ups_flags(tp);
3684 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3685 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3687 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3688 ocp_data |= UPS_FORCE_PWR_DOWN;
3689 ocp_data &= ~BIT(7);
3690 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3692 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3693 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3695 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3696 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3697 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3699 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3702 for (i = 0; i < 500; i++) {
3703 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3709 tp->rtl_ops.hw_phy_cfg(tp);
3711 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3712 tp->duplex, tp->advertising);
3715 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3717 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3719 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3721 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3725 static void r8156_ups_en(struct r8152 *tp, bool enable)
3727 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3730 r8156_ups_flags(tp);
3732 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3733 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3735 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3736 ocp_data |= UPS_FORCE_PWR_DOWN;
3737 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3739 switch (tp->version) {
3742 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
3743 ocp_data &= ~OOBS_POLLING;
3744 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
3750 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3751 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3753 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3754 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3755 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3757 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3758 tp->rtl_ops.hw_phy_cfg(tp);
3760 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3761 tp->duplex, tp->advertising);
3766 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3770 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3772 ocp_data |= PWR_EN | PHASE2_EN;
3774 ocp_data &= ~(PWR_EN | PHASE2_EN);
3775 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3777 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3778 ocp_data &= ~PCUT_STATUS;
3779 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3782 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3786 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3788 ocp_data |= PWR_EN | PHASE2_EN;
3790 ocp_data &= ~PWR_EN;
3791 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3793 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3794 ocp_data &= ~PCUT_STATUS;
3795 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3798 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3802 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3804 ocp_data |= UPCOMING_RUNTIME_D3;
3806 ocp_data &= ~UPCOMING_RUNTIME_D3;
3807 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3809 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3810 ocp_data &= ~LINK_CHG_EVENT;
3811 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3813 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3814 ocp_data &= ~LINK_CHANGE_FLAG;
3815 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3818 static bool rtl_can_wakeup(struct r8152 *tp)
3820 struct usb_device *udev = tp->udev;
3822 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3825 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3830 __rtl_set_wol(tp, WAKE_ANY);
3832 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3834 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3835 ocp_data |= LINK_OFF_WAKE_EN;
3836 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3838 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3842 __rtl_set_wol(tp, tp->saved_wolopts);
3844 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3846 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3847 ocp_data &= ~LINK_OFF_WAKE_EN;
3848 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3850 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3854 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3857 r8153_u1u2en(tp, false);
3858 r8153_u2p3en(tp, false);
3859 rtl_runtime_suspend_enable(tp, true);
3861 rtl_runtime_suspend_enable(tp, false);
3863 switch (tp->version) {
3870 r8153_u2p3en(tp, true);
3874 r8153_u1u2en(tp, true);
3878 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3881 r8153_queue_wake(tp, true);
3882 r8153b_u1u2en(tp, false);
3883 r8153_u2p3en(tp, false);
3884 rtl_runtime_suspend_enable(tp, true);
3885 r8153b_ups_en(tp, true);
3887 r8153b_ups_en(tp, false);
3888 r8153_queue_wake(tp, false);
3889 rtl_runtime_suspend_enable(tp, false);
3890 if (tp->udev->speed >= USB_SPEED_SUPER)
3891 r8153b_u1u2en(tp, true);
3895 static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
3898 r8153_queue_wake(tp, true);
3899 r8153b_u1u2en(tp, false);
3900 r8153_u2p3en(tp, false);
3901 rtl_runtime_suspend_enable(tp, true);
3902 r8153c_ups_en(tp, true);
3904 r8153c_ups_en(tp, false);
3905 r8153_queue_wake(tp, false);
3906 rtl_runtime_suspend_enable(tp, false);
3907 r8153b_u1u2en(tp, true);
3911 static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
3914 r8153_queue_wake(tp, true);
3915 r8153b_u1u2en(tp, false);
3916 r8153_u2p3en(tp, false);
3917 rtl_runtime_suspend_enable(tp, true);
3919 r8153_queue_wake(tp, false);
3920 rtl_runtime_suspend_enable(tp, false);
3921 r8153_u2p3en(tp, true);
3922 if (tp->udev->speed >= USB_SPEED_SUPER)
3923 r8153b_u1u2en(tp, true);
3927 static void r8153_teredo_off(struct r8152 *tp)
3931 switch (tp->version) {
3939 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3940 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3942 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3955 /* The bit 0 ~ 7 are relative with teredo settings. They are
3956 * W1C (write 1 to clear), so set all 1 to disable it.
3958 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3962 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3963 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3964 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3967 static void rtl_reset_bmu(struct r8152 *tp)
3971 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3972 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3973 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3974 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3975 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3978 /* Clear the bp to stop the firmware before loading a new one */
3979 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3984 switch (tp->version) {
3992 if (type == MCU_TYPE_USB) {
3993 ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
4002 ocp_write_byte(tp, type, PLA_BP_EN, 0);
4011 ocp_write_word(tp, type, USB_BP2_EN, 0);
4016 generic_ocp_write(tp, PLA_BP_0, BYTE_EN_DWORD, bp_num << 1, bp, type);
4018 /* wait 3 ms to make sure the firmware is stopped */
4019 usleep_range(3000, 6000);
4020 ocp_write_word(tp, type, PLA_BP_BA, 0);
4023 static inline void rtl_reset_ocp_base(struct r8152 *tp)
4028 static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
4033 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
4035 data |= PATCH_REQUEST;
4038 data &= ~PATCH_REQUEST;
4039 check = PATCH_READY;
4041 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
4043 for (i = 0; wait && i < 5000; i++) {
4046 usleep_range(1000, 2000);
4047 ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
4048 if ((ocp_data & PATCH_READY) ^ check)
4052 if (request && wait &&
4053 !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
4054 dev_err(&tp->intf->dev, "PHY patch request fail\n");
4055 rtl_phy_patch_request(tp, false, false);
4062 static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
4064 if (patch_key && key_addr) {
4065 sram_write(tp, key_addr, patch_key);
4066 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
4067 } else if (key_addr) {
4070 sram_write(tp, 0x0000, 0x0000);
4072 data = ocp_reg_read(tp, OCP_PHY_LOCK);
4073 data &= ~PATCH_LOCK;
4074 ocp_reg_write(tp, OCP_PHY_LOCK, data);
4076 sram_write(tp, key_addr, 0x0000);
4083 rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
4085 if (rtl_phy_patch_request(tp, true, wait))
4088 rtl_patch_key_set(tp, key_addr, patch_key);
4093 static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
4095 rtl_patch_key_set(tp, key_addr, 0);
4097 rtl_phy_patch_request(tp, false, wait);
4102 static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)
4108 switch (tp->version) {
4129 fw_offset = __le16_to_cpu(phy->fw_offset);
4130 length = __le32_to_cpu(phy->blk_hdr.length);
4131 if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4132 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4136 length -= fw_offset;
4138 dev_err(&tp->intf->dev, "invalid block length\n");
4142 if (__le16_to_cpu(phy->fw_reg) != 0x9A00) {
4143 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4152 static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)
4156 switch (tp->version) {
4167 if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {
4168 dev_err(&tp->intf->dev, "invalid block length\n");
4172 if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {
4173 dev_err(&tp->intf->dev, "invalid phy ver addr\n");
4182 static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)
4186 switch (tp->version) {
4197 if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {
4198 dev_err(&tp->intf->dev, "invalid block length\n");
4202 if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||
4203 __le16_to_cpu(fix->setting.data) != BIT(7)) {
4204 dev_err(&tp->intf->dev, "invalid phy fixup\n");
4213 static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)
4219 switch (tp->version) {
4230 fw_offset = __le16_to_cpu(phy->fw_offset);
4231 length = __le32_to_cpu(phy->blk_hdr.length);
4232 if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4233 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4237 length -= fw_offset;
4239 dev_err(&tp->intf->dev, "invalid block length\n");
4243 if (phy->pre_num > 2) {
4244 dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num);
4248 if (phy->bp_num > 8) {
4249 dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num);
4258 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
4261 u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
4264 switch (tp->version) {
4270 patch_en_addr = 0xa01a;
4278 fw_offset = __le16_to_cpu(phy->fw_offset);
4279 if (fw_offset < sizeof(*phy)) {
4280 dev_err(&tp->intf->dev, "fw_offset too small\n");
4284 length = __le32_to_cpu(phy->blk_hdr.length);
4285 if (length < fw_offset) {
4286 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4290 length -= __le16_to_cpu(phy->fw_offset);
4291 if (!length || (length & 1)) {
4292 dev_err(&tp->intf->dev, "invalid block length\n");
4296 if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
4297 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4301 if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
4302 dev_err(&tp->intf->dev, "invalid base address register\n");
4306 if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
4307 dev_err(&tp->intf->dev,
4308 "invalid patch mode enabled register\n");
4312 if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
4313 dev_err(&tp->intf->dev,
4314 "invalid register to switch the mode\n");
4318 if (__le16_to_cpu(phy->bp_start) != bp_start) {
4319 dev_err(&tp->intf->dev,
4320 "invalid start register of break point\n");
4324 if (__le16_to_cpu(phy->bp_num) > 4) {
4325 dev_err(&tp->intf->dev, "invalid break point number\n");
4334 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
4336 u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
4341 type = __le32_to_cpu(mac->blk_hdr.type);
4342 if (type == RTL_FW_PLA) {
4343 switch (tp->version) {
4348 bp_ba_addr = PLA_BP_BA;
4350 bp_start = PLA_BP_0;
4364 bp_ba_addr = PLA_BP_BA;
4365 bp_en_addr = PLA_BP_EN;
4366 bp_start = PLA_BP_0;
4371 bp_ba_addr = PLA_BP_BA;
4372 bp_en_addr = USB_BP2_EN;
4373 bp_start = PLA_BP_0;
4379 } else if (type == RTL_FW_USB) {
4380 switch (tp->version) {
4386 bp_ba_addr = USB_BP_BA;
4387 bp_en_addr = USB_BP_EN;
4388 bp_start = USB_BP_0;
4399 bp_ba_addr = USB_BP_BA;
4400 bp_en_addr = USB_BP2_EN;
4401 bp_start = USB_BP_0;
4414 fw_offset = __le16_to_cpu(mac->fw_offset);
4415 if (fw_offset < sizeof(*mac)) {
4416 dev_err(&tp->intf->dev, "fw_offset too small\n");
4420 length = __le32_to_cpu(mac->blk_hdr.length);
4421 if (length < fw_offset) {
4422 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4426 length -= fw_offset;
4427 if (length < 4 || (length & 3)) {
4428 dev_err(&tp->intf->dev, "invalid block length\n");
4432 if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
4433 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4437 if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
4438 dev_err(&tp->intf->dev, "invalid base address register\n");
4442 if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
4443 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
4447 if (__le16_to_cpu(mac->bp_start) != bp_start) {
4448 dev_err(&tp->intf->dev,
4449 "invalid start register of break point\n");
4453 if (__le16_to_cpu(mac->bp_num) > max_bp) {
4454 dev_err(&tp->intf->dev, "invalid break point number\n");
4458 for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
4460 dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
4470 /* Verify the checksum for the firmware file. It is calculated from the version
4471 * field to the end of the file. Compare the result with the checksum field to
4472 * make sure the file is correct.
4474 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
4475 struct fw_header *fw_hdr, size_t size)
4477 unsigned char checksum[sizeof(fw_hdr->checksum)];
4478 struct crypto_shash *alg;
4479 struct shash_desc *sdesc;
4483 alg = crypto_alloc_shash("sha256", 0, 0);
4489 if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
4491 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
4492 crypto_shash_digestsize(alg));
4496 len = sizeof(*sdesc) + crypto_shash_descsize(alg);
4497 sdesc = kmalloc(len, GFP_KERNEL);
4504 len = size - sizeof(fw_hdr->checksum);
4505 rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
4510 if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
4511 dev_err(&tp->intf->dev, "checksum fail\n");
4516 crypto_free_shash(alg);
4521 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
4523 const struct firmware *fw = rtl_fw->fw;
4524 struct fw_header *fw_hdr = (struct fw_header *)fw->data;
4525 unsigned long fw_flags = 0;
4529 if (fw->size < sizeof(*fw_hdr)) {
4530 dev_err(&tp->intf->dev, "file too small\n");
4534 ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
4540 for (i = sizeof(*fw_hdr); i < fw->size;) {
4541 struct fw_block *block = (struct fw_block *)&fw->data[i];
4544 if ((i + sizeof(*block)) > fw->size)
4547 type = __le32_to_cpu(block->type);
4550 if (__le32_to_cpu(block->length) != sizeof(*block))
4554 if (test_bit(FW_FLAGS_PLA, &fw_flags)) {
4555 dev_err(&tp->intf->dev,
4556 "multiple PLA firmware encountered");
4560 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4561 dev_err(&tp->intf->dev,
4562 "check PLA firmware failed\n");
4565 __set_bit(FW_FLAGS_PLA, &fw_flags);
4568 if (test_bit(FW_FLAGS_USB, &fw_flags)) {
4569 dev_err(&tp->intf->dev,
4570 "multiple USB firmware encountered");
4574 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4575 dev_err(&tp->intf->dev,
4576 "check USB firmware failed\n");
4579 __set_bit(FW_FLAGS_USB, &fw_flags);
4581 case RTL_FW_PHY_START:
4582 if (test_bit(FW_FLAGS_START, &fw_flags) ||
4583 test_bit(FW_FLAGS_NC, &fw_flags) ||
4584 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4585 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4586 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4587 test_bit(FW_FLAGS_UC, &fw_flags) ||
4588 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4589 dev_err(&tp->intf->dev,
4590 "check PHY_START fail\n");
4594 if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {
4595 dev_err(&tp->intf->dev,
4596 "Invalid length for PHY_START\n");
4599 __set_bit(FW_FLAGS_START, &fw_flags);
4601 case RTL_FW_PHY_STOP:
4602 if (test_bit(FW_FLAGS_STOP, &fw_flags) ||
4603 !test_bit(FW_FLAGS_START, &fw_flags)) {
4604 dev_err(&tp->intf->dev,
4605 "Check PHY_STOP fail\n");
4609 if (__le32_to_cpu(block->length) != sizeof(*block)) {
4610 dev_err(&tp->intf->dev,
4611 "Invalid length for PHY_STOP\n");
4614 __set_bit(FW_FLAGS_STOP, &fw_flags);
4617 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4618 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4619 dev_err(&tp->intf->dev,
4620 "check PHY_NC fail\n");
4624 if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4625 dev_err(&tp->intf->dev,
4626 "multiple PHY NC encountered\n");
4630 if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) {
4631 dev_err(&tp->intf->dev,
4632 "check PHY NC firmware failed\n");
4635 __set_bit(FW_FLAGS_NC, &fw_flags);
4637 case RTL_FW_PHY_UNION_NC:
4638 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4639 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4640 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4641 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4642 test_bit(FW_FLAGS_UC, &fw_flags) ||
4643 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4644 dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n");
4648 if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4649 dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n");
4653 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4654 dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n");
4657 __set_bit(FW_FLAGS_NC, &fw_flags);
4659 case RTL_FW_PHY_UNION_NC1:
4660 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4661 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4662 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4663 test_bit(FW_FLAGS_UC, &fw_flags) ||
4664 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4665 dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n");
4669 if (test_bit(FW_FLAGS_NC1, &fw_flags)) {
4670 dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n");
4674 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4675 dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n");
4678 __set_bit(FW_FLAGS_NC1, &fw_flags);
4680 case RTL_FW_PHY_UNION_NC2:
4681 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4682 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4683 test_bit(FW_FLAGS_UC, &fw_flags) ||
4684 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4685 dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n");
4689 if (test_bit(FW_FLAGS_NC2, &fw_flags)) {
4690 dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n");
4694 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4695 dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n");
4698 __set_bit(FW_FLAGS_NC2, &fw_flags);
4700 case RTL_FW_PHY_UNION_UC2:
4701 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4702 test_bit(FW_FLAGS_UC, &fw_flags) ||
4703 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4704 dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n");
4708 if (test_bit(FW_FLAGS_UC2, &fw_flags)) {
4709 dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n");
4713 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4714 dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n");
4717 __set_bit(FW_FLAGS_UC2, &fw_flags);
4719 case RTL_FW_PHY_UNION_UC:
4720 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4721 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4722 dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n");
4726 if (test_bit(FW_FLAGS_UC, &fw_flags)) {
4727 dev_err(&tp->intf->dev, "multiple PHY UC encountered\n");
4731 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4732 dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n");
4735 __set_bit(FW_FLAGS_UC, &fw_flags);
4737 case RTL_FW_PHY_UNION_MISC:
4738 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4739 dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n");
4743 case RTL_FW_PHY_FIXUP:
4744 if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) {
4745 dev_err(&tp->intf->dev, "check PHY fixup failed\n");
4749 case RTL_FW_PHY_SPEED_UP:
4750 if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {
4751 dev_err(&tp->intf->dev, "multiple PHY firmware encountered");
4755 if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) {
4756 dev_err(&tp->intf->dev, "check PHY speed up failed\n");
4759 __set_bit(FW_FLAGS_SPEED_UP, &fw_flags);
4761 case RTL_FW_PHY_VER:
4762 if (test_bit(FW_FLAGS_START, &fw_flags) ||
4763 test_bit(FW_FLAGS_NC, &fw_flags) ||
4764 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4765 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4766 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4767 test_bit(FW_FLAGS_UC, &fw_flags) ||
4768 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4769 dev_err(&tp->intf->dev, "Invalid order to set PHY version\n");
4773 if (test_bit(FW_FLAGS_VER, &fw_flags)) {
4774 dev_err(&tp->intf->dev, "multiple PHY version encountered");
4778 if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) {
4779 dev_err(&tp->intf->dev, "check PHY version failed\n");
4782 __set_bit(FW_FLAGS_VER, &fw_flags);
4785 dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
4791 i += ALIGN(__le32_to_cpu(block->length), 8);
4795 if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {
4796 dev_err(&tp->intf->dev, "without PHY_STOP\n");
4805 static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)
4810 rtl_reset_ocp_base(tp);
4812 if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {
4813 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4817 len = __le32_to_cpu(phy->blk_hdr.length);
4818 len -= __le16_to_cpu(phy->fw_offset);
4819 data = (u8 *)phy + __le16_to_cpu(phy->fw_offset);
4821 if (rtl_phy_patch_request(tp, true, wait))
4833 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);
4834 ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;
4835 ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data);
4837 generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB);
4842 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);
4843 ocp_data |= POL_GPHY_PATCH;
4844 ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data);
4846 for (i = 0; i < 1000; i++) {
4847 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))
4852 dev_err(&tp->intf->dev, "ram code speedup mode timeout\n");
4857 rtl_reset_ocp_base(tp);
4859 rtl_phy_patch_request(tp, false, wait);
4861 if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))
4862 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4864 dev_err(&tp->intf->dev, "ram code speedup mode fail\n");
4867 static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)
4871 ver_addr = __le16_to_cpu(phy_ver->ver.addr);
4872 ver = __le16_to_cpu(phy_ver->ver.data);
4874 rtl_reset_ocp_base(tp);
4876 if (sram_read(tp, ver_addr) >= ver) {
4877 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4881 sram_write(tp, ver_addr, ver);
4883 dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver);
4888 static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)
4892 rtl_reset_ocp_base(tp);
4894 addr = __le16_to_cpu(fix->setting.addr);
4895 data = ocp_reg_read(tp, addr);
4897 switch (__le16_to_cpu(fix->bit_cmd)) {
4899 data &= __le16_to_cpu(fix->setting.data);
4902 data |= __le16_to_cpu(fix->setting.data);
4905 data &= ~__le16_to_cpu(fix->setting.data);
4908 data ^= __le16_to_cpu(fix->setting.data);
4914 ocp_reg_write(tp, addr, data);
4916 dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data);
4919 static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)
4925 rtl_reset_ocp_base(tp);
4928 for (i = 0; i < num; i++)
4929 sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),
4930 __le16_to_cpu(phy->pre_set[i].data));
4932 length = __le32_to_cpu(phy->blk_hdr.length);
4933 length -= __le16_to_cpu(phy->fw_offset);
4935 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
4937 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
4938 for (i = 0; i < num; i++)
4939 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
4942 for (i = 0; i < num; i++)
4943 sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));
4945 if (phy->bp_num && phy->bp_en.addr)
4946 sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));
4948 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4951 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
4953 u16 mode_reg, bp_index;
4957 rtl_reset_ocp_base(tp);
4959 mode_reg = __le16_to_cpu(phy->mode_reg);
4960 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
4961 sram_write(tp, __le16_to_cpu(phy->ba_reg),
4962 __le16_to_cpu(phy->ba_data));
4964 length = __le32_to_cpu(phy->blk_hdr.length);
4965 length -= __le16_to_cpu(phy->fw_offset);
4967 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
4969 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
4970 for (i = 0; i < num; i++)
4971 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
4973 sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
4974 __le16_to_cpu(phy->patch_en_value));
4976 bp_index = __le16_to_cpu(phy->bp_start);
4977 num = __le16_to_cpu(phy->bp_num);
4978 for (i = 0; i < num; i++) {
4979 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
4983 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
4985 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4988 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
4990 u16 bp_en_addr, type, fw_ver_reg;
4994 switch (__le32_to_cpu(mac->blk_hdr.type)) {
4996 type = MCU_TYPE_PLA;
4999 type = MCU_TYPE_USB;
5005 fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
5006 if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) {
5007 dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB");
5011 rtl_clear_bp(tp, type);
5013 /* Enable backup/restore of MACDBG. This is required after clearing PLA
5014 * break points and before applying the PLA firmware.
5016 if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
5017 !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
5018 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
5019 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
5022 length = __le32_to_cpu(mac->blk_hdr.length);
5023 length -= __le16_to_cpu(mac->fw_offset);
5026 data += __le16_to_cpu(mac->fw_offset);
5028 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
5031 ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
5032 __le16_to_cpu(mac->bp_ba_value));
5034 generic_ocp_write(tp, __le16_to_cpu(mac->bp_start), BYTE_EN_DWORD,
5035 __le16_to_cpu(mac->bp_num) << 1, mac->bp, type);
5037 bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
5039 ocp_write_word(tp, type, bp_en_addr,
5040 __le16_to_cpu(mac->bp_en_value));
5043 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
5046 dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
5049 static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
5051 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5052 const struct firmware *fw;
5053 struct fw_header *fw_hdr;
5054 struct fw_phy_patch_key *key;
5056 int i, patch_phy = 1;
5058 if (IS_ERR_OR_NULL(rtl_fw->fw))
5062 fw_hdr = (struct fw_header *)fw->data;
5067 for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
5068 struct fw_block *block = (struct fw_block *)&fw->data[i];
5070 switch (__le32_to_cpu(block->type)) {
5075 rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
5077 case RTL_FW_PHY_START:
5080 key = (struct fw_phy_patch_key *)block;
5081 key_addr = __le16_to_cpu(key->key_reg);
5082 rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);
5084 case RTL_FW_PHY_STOP:
5088 rtl_post_ram_code(tp, key_addr, !power_cut);
5091 rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
5093 case RTL_FW_PHY_VER:
5094 patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block);
5096 case RTL_FW_PHY_UNION_NC:
5097 case RTL_FW_PHY_UNION_NC1:
5098 case RTL_FW_PHY_UNION_NC2:
5099 case RTL_FW_PHY_UNION_UC2:
5100 case RTL_FW_PHY_UNION_UC:
5101 case RTL_FW_PHY_UNION_MISC:
5103 rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block);
5105 case RTL_FW_PHY_FIXUP:
5107 rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block);
5109 case RTL_FW_PHY_SPEED_UP:
5110 rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut);
5116 i += ALIGN(__le32_to_cpu(block->length), 8);
5120 if (rtl_fw->post_fw)
5121 rtl_fw->post_fw(tp);
5123 rtl_reset_ocp_base(tp);
5124 strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
5125 dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
5128 static void rtl8152_release_firmware(struct r8152 *tp)
5130 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5132 if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
5133 release_firmware(rtl_fw->fw);
5138 static int rtl8152_request_firmware(struct r8152 *tp)
5140 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5143 if (rtl_fw->fw || !rtl_fw->fw_name) {
5144 dev_info(&tp->intf->dev, "skip request firmware\n");
5149 rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
5153 rc = rtl8152_check_firmware(tp, rtl_fw);
5155 release_firmware(rtl_fw->fw);
5159 rtl_fw->fw = ERR_PTR(rc);
5161 dev_warn(&tp->intf->dev,
5162 "unable to load firmware patch %s (%ld)\n",
5163 rtl_fw->fw_name, rc);
5169 static void r8152_aldps_en(struct r8152 *tp, bool enable)
5172 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
5173 LINKENA | DIS_SDSAVE);
5175 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
5181 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
5183 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
5184 ocp_reg_write(tp, OCP_EEE_DATA, reg);
5185 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
5188 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
5192 r8152_mmd_indirect(tp, dev, reg);
5193 data = ocp_reg_read(tp, OCP_EEE_DATA);
5194 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5199 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
5201 r8152_mmd_indirect(tp, dev, reg);
5202 ocp_reg_write(tp, OCP_EEE_DATA, data);
5203 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5206 static void r8152_eee_en(struct r8152 *tp, bool enable)
5208 u16 config1, config2, config3;
5211 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5212 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
5213 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
5214 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
5217 ocp_data |= EEE_RX_EN | EEE_TX_EN;
5218 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
5219 config1 |= sd_rise_time(1);
5220 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
5221 config3 |= fast_snr(42);
5223 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5224 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
5226 config1 |= sd_rise_time(7);
5227 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
5228 config3 |= fast_snr(511);
5231 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5232 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
5233 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
5234 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
5237 static void r8153_eee_en(struct r8152 *tp, bool enable)
5242 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5243 config = ocp_reg_read(tp, OCP_EEE_CFG);
5246 ocp_data |= EEE_RX_EN | EEE_TX_EN;
5249 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5250 config &= ~EEE10_EN;
5253 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5254 ocp_reg_write(tp, OCP_EEE_CFG, config);
5256 tp->ups_info.eee = enable;
5259 static void r8156_eee_en(struct r8152 *tp, bool enable)
5263 r8153_eee_en(tp, enable);
5265 config = ocp_reg_read(tp, OCP_EEE_ADV2);
5268 config |= MDIO_EEE_2_5GT;
5270 config &= ~MDIO_EEE_2_5GT;
5272 ocp_reg_write(tp, OCP_EEE_ADV2, config);
5275 static void rtl_eee_enable(struct r8152 *tp, bool enable)
5277 switch (tp->version) {
5282 r8152_eee_en(tp, true);
5283 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
5286 r8152_eee_en(tp, false);
5287 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
5298 r8153_eee_en(tp, true);
5299 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5301 r8153_eee_en(tp, false);
5302 ocp_reg_write(tp, OCP_EEE_ADV, 0);
5311 r8156_eee_en(tp, true);
5312 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5314 r8156_eee_en(tp, false);
5315 ocp_reg_write(tp, OCP_EEE_ADV, 0);
5323 static void r8152b_enable_fc(struct r8152 *tp)
5327 anar = r8152_mdio_read(tp, MII_ADVERTISE);
5328 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
5329 r8152_mdio_write(tp, MII_ADVERTISE, anar);
5331 tp->ups_info.flow_control = true;
5334 static void rtl8152_disable(struct r8152 *tp)
5336 r8152_aldps_en(tp, false);
5338 r8152_aldps_en(tp, true);
5341 static void r8152b_hw_phy_cfg(struct r8152 *tp)
5343 rtl8152_apply_firmware(tp, false);
5344 rtl_eee_enable(tp, tp->eee_en);
5345 r8152_aldps_en(tp, true);
5346 r8152b_enable_fc(tp);
5348 set_bit(PHY_RESET, &tp->flags);
5351 static void wait_oob_link_list_ready(struct r8152 *tp)
5356 for (i = 0; i < 1000; i++) {
5357 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5358 if (ocp_data & LINK_LIST_READY)
5360 usleep_range(1000, 2000);
5364 static void r8156b_wait_loading_flash(struct r8152 *tp)
5366 if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
5367 !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
5370 for (i = 0; i < 100; i++) {
5371 if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
5373 usleep_range(1000, 2000);
5378 static void r8152b_exit_oob(struct r8152 *tp)
5382 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5383 ocp_data &= ~RCR_ACPT_ALL;
5384 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5386 rxdy_gated_en(tp, true);
5387 r8153_teredo_off(tp);
5388 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
5389 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
5391 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5392 ocp_data &= ~NOW_IS_OOB;
5393 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5395 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5396 ocp_data &= ~MCU_BORW_EN;
5397 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5399 wait_oob_link_list_ready(tp);
5401 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5402 ocp_data |= RE_INIT_LL;
5403 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5405 wait_oob_link_list_ready(tp);
5407 rtl8152_nic_reset(tp);
5409 /* rx share fifo credit full threshold */
5410 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5412 if (tp->udev->speed == USB_SPEED_FULL ||
5413 tp->udev->speed == USB_SPEED_LOW) {
5414 /* rx share fifo credit near full threshold */
5415 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5417 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5420 /* rx share fifo credit near full threshold */
5421 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5423 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5427 /* TX share fifo free credit full threshold */
5428 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5430 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
5431 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
5432 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
5433 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
5435 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5437 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5439 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5440 ocp_data |= TCR0_AUTO_FIFO;
5441 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5444 static void r8152b_enter_oob(struct r8152 *tp)
5448 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5449 ocp_data &= ~NOW_IS_OOB;
5450 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5452 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
5453 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
5454 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
5458 wait_oob_link_list_ready(tp);
5460 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5461 ocp_data |= RE_INIT_LL;
5462 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5464 wait_oob_link_list_ready(tp);
5466 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5468 rtl_rx_vlan_en(tp, true);
5470 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5471 ocp_data |= ALDPS_PROXY_MODE;
5472 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5474 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5475 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5476 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5478 rxdy_gated_en(tp, false);
5480 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5481 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5482 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5485 static int r8153_pre_firmware_1(struct r8152 *tp)
5489 /* Wait till the WTD timer is ready. It would take at most 104 ms. */
5490 for (i = 0; i < 104; i++) {
5491 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
5493 if (!(ocp_data & WTD1_EN))
5495 usleep_range(1000, 2000);
5501 static int r8153_post_firmware_1(struct r8152 *tp)
5503 /* set USB_BP_4 to support USB_SPEED_SUPER only */
5504 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
5505 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
5507 /* reset UPHY timer to 36 ms */
5508 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5513 static int r8153_pre_firmware_2(struct r8152 *tp)
5517 r8153_pre_firmware_1(tp);
5519 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5520 ocp_data &= ~FW_FIX_SUSPEND;
5521 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5526 static int r8153_post_firmware_2(struct r8152 *tp)
5530 /* enable bp0 if support USB_SPEED_SUPER only */
5531 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
5532 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5534 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5537 /* reset UPHY timer to 36 ms */
5538 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5540 /* enable U3P3 check, set the counter to 4 */
5541 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
5543 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5544 ocp_data |= FW_FIX_SUSPEND;
5545 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5547 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5548 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5549 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5554 static int r8153_post_firmware_3(struct r8152 *tp)
5558 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5559 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5560 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5562 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5563 ocp_data |= FW_IP_RESET_EN;
5564 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5569 static int r8153b_pre_firmware_1(struct r8152 *tp)
5571 /* enable fc timer and set timer to 1 second. */
5572 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
5573 CTRL_TIMER_EN | (1000 / 8));
5578 static int r8153b_post_firmware_1(struct r8152 *tp)
5582 /* enable bp0 for RTL8153-BND */
5583 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
5584 if (ocp_data & BND_MASK) {
5585 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5587 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5590 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5591 ocp_data |= FLOW_CTRL_PATCH_OPT;
5592 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5594 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5595 ocp_data |= FC_PATCH_TASK;
5596 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5598 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5599 ocp_data |= FW_IP_RESET_EN;
5600 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5605 static int r8153c_post_firmware_1(struct r8152 *tp)
5609 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5610 ocp_data |= FLOW_CTRL_PATCH_2;
5611 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5613 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5614 ocp_data |= FC_PATCH_TASK;
5615 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5620 static int r8156a_post_firmware_1(struct r8152 *tp)
5624 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5625 ocp_data |= FW_IP_RESET_EN;
5626 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5628 /* Modify U3PHY parameter for compatibility issue */
5629 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e);
5630 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9);
5635 static void r8153_aldps_en(struct r8152 *tp, bool enable)
5639 data = ocp_reg_read(tp, OCP_POWER_CFG);
5642 ocp_reg_write(tp, OCP_POWER_CFG, data);
5647 ocp_reg_write(tp, OCP_POWER_CFG, data);
5648 for (i = 0; i < 20; i++) {
5649 usleep_range(1000, 2000);
5650 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
5655 tp->ups_info.aldps = enable;
5658 static void r8153_hw_phy_cfg(struct r8152 *tp)
5663 /* disable ALDPS before updating the PHY parameters */
5664 r8153_aldps_en(tp, false);
5666 /* disable EEE before updating the PHY parameters */
5667 rtl_eee_enable(tp, false);
5669 rtl8152_apply_firmware(tp, false);
5671 if (tp->version == RTL_VER_03) {
5672 data = ocp_reg_read(tp, OCP_EEE_CFG);
5673 data &= ~CTAP_SHORT_EN;
5674 ocp_reg_write(tp, OCP_EEE_CFG, data);
5677 data = ocp_reg_read(tp, OCP_POWER_CFG);
5678 data |= EEE_CLKDIV_EN;
5679 ocp_reg_write(tp, OCP_POWER_CFG, data);
5681 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5682 data |= EN_10M_BGOFF;
5683 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5684 data = ocp_reg_read(tp, OCP_POWER_CFG);
5685 data |= EN_10M_PLLOFF;
5686 ocp_reg_write(tp, OCP_POWER_CFG, data);
5687 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
5689 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5690 ocp_data |= PFM_PWM_SWITCH;
5691 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5693 /* Enable LPF corner auto tune */
5694 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
5696 /* Adjust 10M Amplitude */
5697 sram_write(tp, SRAM_10M_AMP1, 0x00af);
5698 sram_write(tp, SRAM_10M_AMP2, 0x0208);
5701 rtl_eee_enable(tp, true);
5703 r8153_aldps_en(tp, true);
5704 r8152b_enable_fc(tp);
5706 switch (tp->version) {
5713 r8153_u2p3en(tp, true);
5717 set_bit(PHY_RESET, &tp->flags);
5720 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
5724 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
5725 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
5726 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
5727 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
5732 static void r8153b_hw_phy_cfg(struct r8152 *tp)
5737 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
5738 if (ocp_data & PCUT_STATUS) {
5739 ocp_data &= ~PCUT_STATUS;
5740 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
5743 /* disable ALDPS before updating the PHY parameters */
5744 r8153_aldps_en(tp, false);
5746 /* disable EEE before updating the PHY parameters */
5747 rtl_eee_enable(tp, false);
5749 /* U1/U2/L1 idle timer. 500 us */
5750 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5752 data = r8153_phy_status(tp, 0);
5755 case PHY_STAT_PWRDN:
5756 case PHY_STAT_EXT_INIT:
5757 rtl8152_apply_firmware(tp, true);
5759 data = r8152_mdio_read(tp, MII_BMCR);
5760 data &= ~BMCR_PDOWN;
5761 r8152_mdio_write(tp, MII_BMCR, data);
5763 case PHY_STAT_LAN_ON:
5765 rtl8152_apply_firmware(tp, false);
5769 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
5771 data = sram_read(tp, SRAM_GREEN_CFG);
5773 sram_write(tp, SRAM_GREEN_CFG, data);
5774 data = ocp_reg_read(tp, OCP_NCTL_CFG);
5775 data |= PGA_RETURN_EN;
5776 ocp_reg_write(tp, OCP_NCTL_CFG, data);
5778 /* ADC Bias Calibration:
5779 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
5780 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
5783 ocp_data = r8152_efuse_read(tp, 0x7d);
5784 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
5786 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
5788 /* ups mode tx-link-pulse timing adjustment:
5789 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
5790 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
5792 ocp_data = ocp_reg_read(tp, 0xc426);
5795 u32 swr_cnt_1ms_ini;
5797 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
5798 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
5799 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
5800 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
5803 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5804 ocp_data |= PFM_PWM_SWITCH;
5805 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5808 if (!rtl_phy_patch_request(tp, true, true)) {
5809 data = ocp_reg_read(tp, OCP_POWER_CFG);
5810 data |= EEE_CLKDIV_EN;
5811 ocp_reg_write(tp, OCP_POWER_CFG, data);
5812 tp->ups_info.eee_ckdiv = true;
5814 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5815 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
5816 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5817 tp->ups_info.eee_cmod_lv = true;
5818 tp->ups_info._10m_ckdiv = true;
5819 tp->ups_info.eee_plloff_giga = true;
5821 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
5822 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
5823 tp->ups_info._250m_ckdiv = true;
5825 rtl_phy_patch_request(tp, false, true);
5829 rtl_eee_enable(tp, true);
5831 r8153_aldps_en(tp, true);
5832 r8152b_enable_fc(tp);
5834 set_bit(PHY_RESET, &tp->flags);
5837 static void r8153c_hw_phy_cfg(struct r8152 *tp)
5839 r8153b_hw_phy_cfg(tp);
5841 tp->ups_info.r_tune = true;
5844 static void rtl8153_change_mtu(struct r8152 *tp)
5846 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5847 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
5850 static void r8153_first_init(struct r8152 *tp)
5854 rxdy_gated_en(tp, true);
5855 r8153_teredo_off(tp);
5857 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5858 ocp_data &= ~RCR_ACPT_ALL;
5859 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5861 rtl8152_nic_reset(tp);
5864 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5865 ocp_data &= ~NOW_IS_OOB;
5866 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5868 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5869 ocp_data &= ~MCU_BORW_EN;
5870 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5872 wait_oob_link_list_ready(tp);
5874 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5875 ocp_data |= RE_INIT_LL;
5876 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5878 wait_oob_link_list_ready(tp);
5880 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5882 rtl8153_change_mtu(tp);
5884 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5885 ocp_data |= TCR0_AUTO_FIFO;
5886 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5888 rtl8152_nic_reset(tp);
5890 /* rx share fifo credit full threshold */
5891 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5892 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
5893 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
5894 /* TX share fifo free credit full threshold */
5895 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5898 static void r8153_enter_oob(struct r8152 *tp)
5902 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5903 ocp_data &= ~NOW_IS_OOB;
5904 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5906 /* RX FIFO settings for OOB */
5907 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
5908 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
5909 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
5914 wait_oob_link_list_ready(tp);
5916 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5917 ocp_data |= RE_INIT_LL;
5918 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5920 wait_oob_link_list_ready(tp);
5922 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522);
5923 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
5925 switch (tp->version) {
5930 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
5931 ocp_data &= ~TEREDO_WAKE_MASK;
5932 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
5938 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
5939 * type. Set it to zero. bits[7:0] are the W1C bits about
5940 * the events. Set them to all 1 to clear them.
5942 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
5949 rtl_rx_vlan_en(tp, true);
5951 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5952 ocp_data |= ALDPS_PROXY_MODE;
5953 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5955 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5956 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5957 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5959 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5960 ocp_data |= MCU_BORW_EN;
5961 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5963 rxdy_gated_en(tp, false);
5965 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5966 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5967 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5970 static void rtl8153_disable(struct r8152 *tp)
5972 r8153_aldps_en(tp, false);
5975 r8153_aldps_en(tp, true);
5978 static u32 fc_pause_on_auto(struct r8152 *tp)
5980 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
5983 static u32 fc_pause_off_auto(struct r8152 *tp)
5985 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
5988 static void r8156_fc_parameter(struct r8152 *tp)
5990 u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
5991 u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
5993 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16);
5994 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16);
5997 static int rtl8156_enable(struct r8152 *tp)
6002 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6005 r8156_fc_parameter(tp);
6007 rtl_set_eee_plus(tp);
6008 r8153_set_rx_early_timeout(tp);
6009 r8153_set_rx_early_size(tp);
6011 speed = rtl8152_get_speed(tp);
6012 rtl_set_ifg(tp, speed);
6014 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6015 if (speed & _2500bps)
6016 ocp_data &= ~IDLE_SPDWN_EN;
6018 ocp_data |= IDLE_SPDWN_EN;
6019 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
6021 if (speed & _1000bps)
6022 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);
6023 else if (speed & _500bps)
6024 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d);
6026 if (tp->udev->speed == USB_SPEED_HIGH) {
6027 /* USB 0xb45e[3:0] l1_nyet_hird */
6028 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6030 if (is_flow_control(speed))
6034 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6037 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6038 ocp_data &= ~FC_PATCH_TASK;
6039 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6040 usleep_range(1000, 2000);
6041 ocp_data |= FC_PATCH_TASK;
6042 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6044 return rtl_enable(tp);
6047 static void rtl8156_disable(struct r8152 *tp)
6049 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 0);
6050 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 0);
6052 rtl8153_disable(tp);
6055 static int rtl8156b_enable(struct r8152 *tp)
6060 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6064 rtl_set_eee_plus(tp);
6066 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
6067 ocp_data &= ~RX_AGGR_NUM_MASK;
6068 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);
6070 r8153_set_rx_early_timeout(tp);
6071 r8153_set_rx_early_size(tp);
6073 speed = rtl8152_get_speed(tp);
6074 rtl_set_ifg(tp, speed);
6076 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6077 if (speed & _2500bps)
6078 ocp_data &= ~IDLE_SPDWN_EN;
6080 ocp_data |= IDLE_SPDWN_EN;
6081 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
6083 if (tp->udev->speed == USB_SPEED_HIGH) {
6084 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6086 if (is_flow_control(speed))
6090 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6093 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6094 ocp_data &= ~FC_PATCH_TASK;
6095 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6096 usleep_range(1000, 2000);
6097 ocp_data |= FC_PATCH_TASK;
6098 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6100 return rtl_enable(tp);
6103 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
6109 if (autoneg == AUTONEG_DISABLE) {
6110 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
6115 bmcr = BMCR_SPEED10;
6116 if (duplex == DUPLEX_FULL) {
6117 bmcr |= BMCR_FULLDPLX;
6118 tp->ups_info.speed_duplex = FORCE_10M_FULL;
6120 tp->ups_info.speed_duplex = FORCE_10M_HALF;
6124 bmcr = BMCR_SPEED100;
6125 if (duplex == DUPLEX_FULL) {
6126 bmcr |= BMCR_FULLDPLX;
6127 tp->ups_info.speed_duplex = FORCE_100M_FULL;
6129 tp->ups_info.speed_duplex = FORCE_100M_HALF;
6133 if (tp->mii.supports_gmii) {
6134 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
6135 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6144 if (duplex == DUPLEX_FULL)
6145 tp->mii.full_duplex = 1;
6147 tp->mii.full_duplex = 0;
6149 tp->mii.force_media = 1;
6154 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6155 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6157 if (tp->mii.supports_gmii) {
6158 support |= RTL_ADVERTISED_1000_FULL;
6160 if (tp->support_2500full)
6161 support |= RTL_ADVERTISED_2500_FULL;
6164 if (!(advertising & support))
6167 orig = r8152_mdio_read(tp, MII_ADVERTISE);
6168 new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
6169 ADVERTISE_100HALF | ADVERTISE_100FULL);
6170 if (advertising & RTL_ADVERTISED_10_HALF) {
6171 new1 |= ADVERTISE_10HALF;
6172 tp->ups_info.speed_duplex = NWAY_10M_HALF;
6174 if (advertising & RTL_ADVERTISED_10_FULL) {
6175 new1 |= ADVERTISE_10FULL;
6176 tp->ups_info.speed_duplex = NWAY_10M_FULL;
6179 if (advertising & RTL_ADVERTISED_100_HALF) {
6180 new1 |= ADVERTISE_100HALF;
6181 tp->ups_info.speed_duplex = NWAY_100M_HALF;
6183 if (advertising & RTL_ADVERTISED_100_FULL) {
6184 new1 |= ADVERTISE_100FULL;
6185 tp->ups_info.speed_duplex = NWAY_100M_FULL;
6189 r8152_mdio_write(tp, MII_ADVERTISE, new1);
6190 tp->mii.advertising = new1;
6193 if (tp->mii.supports_gmii) {
6194 orig = r8152_mdio_read(tp, MII_CTRL1000);
6195 new1 = orig & ~(ADVERTISE_1000FULL |
6196 ADVERTISE_1000HALF);
6198 if (advertising & RTL_ADVERTISED_1000_FULL) {
6199 new1 |= ADVERTISE_1000FULL;
6200 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6204 r8152_mdio_write(tp, MII_CTRL1000, new1);
6207 if (tp->support_2500full) {
6208 orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
6209 new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
6211 if (advertising & RTL_ADVERTISED_2500_FULL) {
6212 new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
6213 tp->ups_info.speed_duplex = NWAY_2500M_FULL;
6217 ocp_reg_write(tp, OCP_10GBT_CTRL, new1);
6220 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
6222 tp->mii.force_media = 0;
6225 if (test_and_clear_bit(PHY_RESET, &tp->flags))
6228 r8152_mdio_write(tp, MII_BMCR, bmcr);
6230 if (bmcr & BMCR_RESET) {
6233 for (i = 0; i < 50; i++) {
6235 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
6244 static void rtl8152_up(struct r8152 *tp)
6246 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6249 r8152_aldps_en(tp, false);
6250 r8152b_exit_oob(tp);
6251 r8152_aldps_en(tp, true);
6254 static void rtl8152_down(struct r8152 *tp)
6256 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6257 rtl_drop_queued_tx(tp);
6261 r8152_power_cut_en(tp, false);
6262 r8152_aldps_en(tp, false);
6263 r8152b_enter_oob(tp);
6264 r8152_aldps_en(tp, true);
6267 static void rtl8153_up(struct r8152 *tp)
6271 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6274 r8153_u1u2en(tp, false);
6275 r8153_u2p3en(tp, false);
6276 r8153_aldps_en(tp, false);
6277 r8153_first_init(tp);
6279 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6280 ocp_data |= LANWAKE_CLR_EN;
6281 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6283 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6284 ocp_data &= ~LANWAKE_PIN;
6285 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
6287 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
6288 ocp_data &= ~DELAY_PHY_PWR_CHG;
6289 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
6291 r8153_aldps_en(tp, true);
6293 switch (tp->version) {
6300 r8153_u2p3en(tp, true);
6304 r8153_u1u2en(tp, true);
6307 static void rtl8153_down(struct r8152 *tp)
6311 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6312 rtl_drop_queued_tx(tp);
6316 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6317 ocp_data &= ~LANWAKE_CLR_EN;
6318 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6320 r8153_u1u2en(tp, false);
6321 r8153_u2p3en(tp, false);
6322 r8153_power_cut_en(tp, false);
6323 r8153_aldps_en(tp, false);
6324 r8153_enter_oob(tp);
6325 r8153_aldps_en(tp, true);
6328 static void rtl8153b_up(struct r8152 *tp)
6332 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6335 r8153b_u1u2en(tp, false);
6336 r8153_u2p3en(tp, false);
6337 r8153_aldps_en(tp, false);
6339 r8153_first_init(tp);
6340 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6342 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6343 ocp_data &= ~PLA_MCU_SPDWN_EN;
6344 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6346 r8153_aldps_en(tp, true);
6348 if (tp->udev->speed >= USB_SPEED_SUPER)
6349 r8153b_u1u2en(tp, true);
6352 static void rtl8153b_down(struct r8152 *tp)
6356 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6357 rtl_drop_queued_tx(tp);
6361 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6362 ocp_data |= PLA_MCU_SPDWN_EN;
6363 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6365 r8153b_u1u2en(tp, false);
6366 r8153_u2p3en(tp, false);
6367 r8153b_power_cut_en(tp, false);
6368 r8153_aldps_en(tp, false);
6369 r8153_enter_oob(tp);
6370 r8153_aldps_en(tp, true);
6373 static void rtl8153c_change_mtu(struct r8152 *tp)
6375 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
6376 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64);
6378 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6380 /* Adjust the tx fifo free credit full threshold, otherwise
6381 * the fifo would be too small to send a jumbo frame packet.
6383 if (tp->netdev->mtu < 8000)
6384 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8);
6386 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8);
6389 static void rtl8153c_up(struct r8152 *tp)
6393 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6396 r8153b_u1u2en(tp, false);
6397 r8153_u2p3en(tp, false);
6398 r8153_aldps_en(tp, false);
6400 rxdy_gated_en(tp, true);
6401 r8153_teredo_off(tp);
6403 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6404 ocp_data &= ~RCR_ACPT_ALL;
6405 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6407 rtl8152_nic_reset(tp);
6410 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6411 ocp_data &= ~NOW_IS_OOB;
6412 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6414 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6415 ocp_data &= ~MCU_BORW_EN;
6416 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6418 wait_oob_link_list_ready(tp);
6420 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6421 ocp_data |= RE_INIT_LL;
6422 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6424 wait_oob_link_list_ready(tp);
6426 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6428 rtl8153c_change_mtu(tp);
6430 rtl8152_nic_reset(tp);
6432 /* rx share fifo credit full threshold */
6433 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02);
6434 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08);
6435 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6436 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6438 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6440 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
6442 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
6444 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
6446 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
6448 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6449 ocp_data &= ~PLA_MCU_SPDWN_EN;
6450 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6452 r8153_aldps_en(tp, true);
6453 r8153b_u1u2en(tp, true);
6456 static void rtl8156_change_mtu(struct r8152 *tp)
6458 u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
6460 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size);
6461 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
6462 r8156_fc_parameter(tp);
6464 /* TX share fifo free credit full threshold */
6465 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6466 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
6467 ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
6470 static void rtl8156_up(struct r8152 *tp)
6474 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6477 r8153b_u1u2en(tp, false);
6478 r8153_u2p3en(tp, false);
6479 r8153_aldps_en(tp, false);
6481 rxdy_gated_en(tp, true);
6482 r8153_teredo_off(tp);
6484 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6485 ocp_data &= ~RCR_ACPT_ALL;
6486 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6488 rtl8152_nic_reset(tp);
6491 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6492 ocp_data &= ~NOW_IS_OOB;
6493 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6495 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6496 ocp_data &= ~MCU_BORW_EN;
6497 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6499 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6501 rtl8156_change_mtu(tp);
6503 switch (tp->version) {
6507 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
6508 ocp_data |= ACT_ODMA;
6509 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
6515 /* share FIFO settings */
6516 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
6517 ocp_data &= ~RXFIFO_FULL_MASK;
6519 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);
6521 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6522 ocp_data &= ~PLA_MCU_SPDWN_EN;
6523 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6525 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
6526 ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
6527 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);
6529 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);
6531 if (tp->saved_wolopts != __rtl_get_wol(tp)) {
6532 netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
6533 __rtl_set_wol(tp, tp->saved_wolopts);
6536 r8153_aldps_en(tp, true);
6537 r8153_u2p3en(tp, true);
6539 if (tp->udev->speed >= USB_SPEED_SUPER)
6540 r8153b_u1u2en(tp, true);
6543 static void rtl8156_down(struct r8152 *tp)
6547 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6548 rtl_drop_queued_tx(tp);
6552 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6553 ocp_data |= PLA_MCU_SPDWN_EN;
6554 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6556 r8153b_u1u2en(tp, false);
6557 r8153_u2p3en(tp, false);
6558 r8153b_power_cut_en(tp, false);
6559 r8153_aldps_en(tp, false);
6561 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6562 ocp_data &= ~NOW_IS_OOB;
6563 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6565 /* RX FIFO settings for OOB */
6566 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 64 / 16);
6567 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 1024 / 16);
6568 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 4096 / 16);
6573 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522);
6574 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
6576 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
6577 * type. Set it to zero. bits[7:0] are the W1C bits about
6578 * the events. Set them to all 1 to clear them.
6580 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
6582 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6583 ocp_data |= NOW_IS_OOB;
6584 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6586 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6587 ocp_data |= MCU_BORW_EN;
6588 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6590 rtl_rx_vlan_en(tp, true);
6591 rxdy_gated_en(tp, false);
6593 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6594 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6595 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6597 r8153_aldps_en(tp, true);
6600 static bool rtl8152_in_nway(struct r8152 *tp)
6604 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
6605 tp->ocp_base = 0x2000;
6606 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
6607 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
6609 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
6610 if (nway_state & 0xc000)
6616 static bool rtl8153_in_nway(struct r8152 *tp)
6618 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
6620 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
6626 static void r8156_mdio_force_mode(struct r8152 *tp)
6630 /* Select force mode through 0xa5b4 bit 15
6631 * 0: MDIO force mode
6634 data = ocp_reg_read(tp, 0xa5b4);
6635 if (data & BIT(15)) {
6637 ocp_reg_write(tp, 0xa5b4, data);
6641 static void set_carrier(struct r8152 *tp)
6643 struct net_device *netdev = tp->netdev;
6644 struct napi_struct *napi = &tp->napi;
6647 speed = rtl8152_get_speed(tp);
6649 if (speed & LINK_STATUS) {
6650 if (!netif_carrier_ok(netdev)) {
6651 tp->rtl_ops.enable(tp);
6652 netif_stop_queue(netdev);
6654 netif_carrier_on(netdev);
6656 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6657 _rtl8152_set_rx_mode(netdev);
6659 netif_wake_queue(netdev);
6660 netif_info(tp, link, netdev, "carrier on\n");
6661 } else if (netif_queue_stopped(netdev) &&
6662 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
6663 netif_wake_queue(netdev);
6666 if (netif_carrier_ok(netdev)) {
6667 netif_carrier_off(netdev);
6668 tasklet_disable(&tp->tx_tl);
6670 tp->rtl_ops.disable(tp);
6672 tasklet_enable(&tp->tx_tl);
6673 netif_info(tp, link, netdev, "carrier off\n");
6678 static void rtl_work_func_t(struct work_struct *work)
6680 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
6682 /* If the device is unplugged or !netif_running(), the workqueue
6683 * doesn't need to wake the device, and could return directly.
6685 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
6688 if (usb_autopm_get_interface(tp->intf) < 0)
6691 if (!test_bit(WORK_ENABLE, &tp->flags))
6694 if (!mutex_trylock(&tp->control)) {
6695 schedule_delayed_work(&tp->schedule, 0);
6699 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
6702 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
6703 _rtl8152_set_rx_mode(tp->netdev);
6705 /* don't schedule tasket before linking */
6706 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
6707 netif_carrier_ok(tp->netdev))
6708 tasklet_schedule(&tp->tx_tl);
6710 if (test_and_clear_bit(RX_EPROTO, &tp->flags) &&
6711 !list_empty(&tp->rx_done))
6712 napi_schedule(&tp->napi);
6714 mutex_unlock(&tp->control);
6717 usb_autopm_put_interface(tp->intf);
6720 static void rtl_hw_phy_work_func_t(struct work_struct *work)
6722 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
6724 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6727 if (usb_autopm_get_interface(tp->intf) < 0)
6730 mutex_lock(&tp->control);
6732 if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
6733 tp->rtl_fw.retry = false;
6734 tp->rtl_fw.fw = NULL;
6736 /* Delay execution in case request_firmware() is not ready yet.
6738 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
6742 tp->rtl_ops.hw_phy_cfg(tp);
6744 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
6748 mutex_unlock(&tp->control);
6750 usb_autopm_put_interface(tp->intf);
6753 #ifdef CONFIG_PM_SLEEP
6754 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
6757 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
6760 case PM_HIBERNATION_PREPARE:
6761 case PM_SUSPEND_PREPARE:
6762 usb_autopm_get_interface(tp->intf);
6765 case PM_POST_HIBERNATION:
6766 case PM_POST_SUSPEND:
6767 usb_autopm_put_interface(tp->intf);
6770 case PM_POST_RESTORE:
6771 case PM_RESTORE_PREPARE:
6780 static int rtl8152_open(struct net_device *netdev)
6782 struct r8152 *tp = netdev_priv(netdev);
6785 if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
6786 cancel_delayed_work_sync(&tp->hw_phy_work);
6787 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
6790 res = alloc_all_mem(tp);
6794 res = usb_autopm_get_interface(tp->intf);
6798 mutex_lock(&tp->control);
6802 netif_carrier_off(netdev);
6803 netif_start_queue(netdev);
6804 set_bit(WORK_ENABLE, &tp->flags);
6806 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
6809 netif_device_detach(tp->netdev);
6810 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
6814 napi_enable(&tp->napi);
6815 tasklet_enable(&tp->tx_tl);
6817 mutex_unlock(&tp->control);
6819 usb_autopm_put_interface(tp->intf);
6820 #ifdef CONFIG_PM_SLEEP
6821 tp->pm_notifier.notifier_call = rtl_notifier;
6822 register_pm_notifier(&tp->pm_notifier);
6827 mutex_unlock(&tp->control);
6828 usb_autopm_put_interface(tp->intf);
6835 static int rtl8152_close(struct net_device *netdev)
6837 struct r8152 *tp = netdev_priv(netdev);
6840 #ifdef CONFIG_PM_SLEEP
6841 unregister_pm_notifier(&tp->pm_notifier);
6843 tasklet_disable(&tp->tx_tl);
6844 clear_bit(WORK_ENABLE, &tp->flags);
6845 usb_kill_urb(tp->intr_urb);
6846 cancel_delayed_work_sync(&tp->schedule);
6847 napi_disable(&tp->napi);
6848 netif_stop_queue(netdev);
6850 res = usb_autopm_get_interface(tp->intf);
6851 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
6852 rtl_drop_queued_tx(tp);
6855 mutex_lock(&tp->control);
6857 tp->rtl_ops.down(tp);
6859 mutex_unlock(&tp->control);
6863 usb_autopm_put_interface(tp->intf);
6870 static void rtl_tally_reset(struct r8152 *tp)
6874 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
6875 ocp_data |= TALLY_RESET;
6876 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
6879 static void r8152b_init(struct r8152 *tp)
6884 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6887 data = r8152_mdio_read(tp, MII_BMCR);
6888 if (data & BMCR_PDOWN) {
6889 data &= ~BMCR_PDOWN;
6890 r8152_mdio_write(tp, MII_BMCR, data);
6893 r8152_aldps_en(tp, false);
6895 if (tp->version == RTL_VER_01) {
6896 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
6897 ocp_data &= ~LED_MODE_MASK;
6898 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
6901 r8152_power_cut_en(tp, false);
6903 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
6904 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
6905 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
6906 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
6907 ocp_data &= ~MCU_CLK_RATIO_MASK;
6908 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
6909 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
6910 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
6911 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
6912 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
6914 rtl_tally_reset(tp);
6916 /* enable rx aggregation */
6917 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
6918 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
6919 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
6922 static void r8153_init(struct r8152 *tp)
6928 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6931 r8153_u1u2en(tp, false);
6933 for (i = 0; i < 500; i++) {
6934 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
6939 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6943 data = r8153_phy_status(tp, 0);
6945 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
6946 tp->version == RTL_VER_05)
6947 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
6949 data = r8152_mdio_read(tp, MII_BMCR);
6950 if (data & BMCR_PDOWN) {
6951 data &= ~BMCR_PDOWN;
6952 r8152_mdio_write(tp, MII_BMCR, data);
6955 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
6957 r8153_u2p3en(tp, false);
6959 if (tp->version == RTL_VER_04) {
6960 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
6961 ocp_data &= ~pwd_dn_scale_mask;
6962 ocp_data |= pwd_dn_scale(96);
6963 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
6965 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
6966 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
6967 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
6968 } else if (tp->version == RTL_VER_05) {
6969 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
6970 ocp_data &= ~ECM_ALDPS;
6971 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
6973 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
6974 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
6975 ocp_data &= ~DYNAMIC_BURST;
6977 ocp_data |= DYNAMIC_BURST;
6978 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
6979 } else if (tp->version == RTL_VER_06) {
6980 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
6981 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
6982 ocp_data &= ~DYNAMIC_BURST;
6984 ocp_data |= DYNAMIC_BURST;
6985 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
6987 r8153_queue_wake(tp, false);
6989 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
6990 if (rtl8152_get_speed(tp) & LINK_STATUS)
6991 ocp_data |= CUR_LINK_OK;
6993 ocp_data &= ~CUR_LINK_OK;
6994 ocp_data |= POLL_LINK_CHG;
6995 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
6998 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
6999 ocp_data |= EP4_FULL_FC;
7000 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
7002 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
7003 ocp_data &= ~TIMER11_EN;
7004 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
7006 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
7007 ocp_data &= ~LED_MODE_MASK;
7008 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
7010 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
7011 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
7012 ocp_data |= LPM_TIMER_500MS;
7014 ocp_data |= LPM_TIMER_500US;
7015 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
7017 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
7018 ocp_data &= ~SEN_VAL_MASK;
7019 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
7020 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
7022 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
7024 r8153_power_cut_en(tp, false);
7025 rtl_runtime_suspend_enable(tp, false);
7026 r8153_mac_clk_speed_down(tp, false);
7027 r8153_u1u2en(tp, true);
7028 usb_enable_lpm(tp->udev);
7030 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
7031 ocp_data |= LANWAKE_CLR_EN;
7032 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
7034 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
7035 ocp_data &= ~LANWAKE_PIN;
7036 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
7038 /* rx aggregation */
7039 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7040 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7041 if (tp->dell_tb_rx_agg_bug)
7042 ocp_data |= RX_AGG_DISABLE;
7044 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7046 rtl_tally_reset(tp);
7048 switch (tp->udev->speed) {
7049 case USB_SPEED_SUPER:
7050 case USB_SPEED_SUPER_PLUS:
7051 tp->coalesce = COALESCE_SUPER;
7053 case USB_SPEED_HIGH:
7054 tp->coalesce = COALESCE_HIGH;
7057 tp->coalesce = COALESCE_SLOW;
7062 static void r8153b_init(struct r8152 *tp)
7068 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7071 r8153b_u1u2en(tp, false);
7073 for (i = 0; i < 500; i++) {
7074 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7079 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7083 data = r8153_phy_status(tp, 0);
7085 data = r8152_mdio_read(tp, MII_BMCR);
7086 if (data & BMCR_PDOWN) {
7087 data &= ~BMCR_PDOWN;
7088 r8152_mdio_write(tp, MII_BMCR, data);
7091 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7093 r8153_u2p3en(tp, false);
7095 /* MSC timer = 0xfff * 8ms = 32760 ms */
7096 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7098 r8153b_power_cut_en(tp, false);
7099 r8153b_ups_en(tp, false);
7100 r8153_queue_wake(tp, false);
7101 rtl_runtime_suspend_enable(tp, false);
7103 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7104 if (rtl8152_get_speed(tp) & LINK_STATUS)
7105 ocp_data |= CUR_LINK_OK;
7107 ocp_data &= ~CUR_LINK_OK;
7108 ocp_data |= POLL_LINK_CHG;
7109 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7111 if (tp->udev->speed >= USB_SPEED_SUPER)
7112 r8153b_u1u2en(tp, true);
7114 usb_enable_lpm(tp->udev);
7116 /* MAC clock speed down */
7117 r8153_mac_clk_speed_down(tp, true);
7119 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7120 ocp_data &= ~PLA_MCU_SPDWN_EN;
7121 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
7123 if (tp->version == RTL_VER_09) {
7124 /* Disable Test IO for 32QFN */
7125 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
7126 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7127 ocp_data |= TEST_IO_OFF;
7128 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7132 set_bit(GREEN_ETHERNET, &tp->flags);
7134 /* rx aggregation */
7135 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7136 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7137 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7139 rtl_tally_reset(tp);
7141 tp->coalesce = 15000; /* 15 us */
7144 static void r8153c_init(struct r8152 *tp)
7150 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7153 r8153b_u1u2en(tp, false);
7155 /* Disable spi_en */
7156 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
7157 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
7158 ocp_data &= ~BIT(3);
7159 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
7160 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);
7162 ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);
7164 for (i = 0; i < 500; i++) {
7165 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7170 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7174 data = r8153_phy_status(tp, 0);
7176 data = r8152_mdio_read(tp, MII_BMCR);
7177 if (data & BMCR_PDOWN) {
7178 data &= ~BMCR_PDOWN;
7179 r8152_mdio_write(tp, MII_BMCR, data);
7182 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7184 r8153_u2p3en(tp, false);
7186 /* MSC timer = 0xfff * 8ms = 32760 ms */
7187 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7189 r8153b_power_cut_en(tp, false);
7190 r8153c_ups_en(tp, false);
7191 r8153_queue_wake(tp, false);
7192 rtl_runtime_suspend_enable(tp, false);
7194 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7195 if (rtl8152_get_speed(tp) & LINK_STATUS)
7196 ocp_data |= CUR_LINK_OK;
7198 ocp_data &= ~CUR_LINK_OK;
7200 ocp_data |= POLL_LINK_CHG;
7201 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7203 r8153b_u1u2en(tp, true);
7205 usb_enable_lpm(tp->udev);
7207 /* MAC clock speed down */
7208 r8153_mac_clk_speed_down(tp, true);
7210 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
7211 ocp_data &= ~BIT(7);
7212 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
7214 set_bit(GREEN_ETHERNET, &tp->flags);
7216 /* rx aggregation */
7217 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7218 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7219 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7221 rtl_tally_reset(tp);
7223 tp->coalesce = 15000; /* 15 us */
7226 static void r8156_hw_phy_cfg(struct r8152 *tp)
7231 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7232 if (ocp_data & PCUT_STATUS) {
7233 ocp_data &= ~PCUT_STATUS;
7234 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7237 data = r8153_phy_status(tp, 0);
7239 case PHY_STAT_EXT_INIT:
7240 rtl8152_apply_firmware(tp, true);
7242 data = ocp_reg_read(tp, 0xa468);
7243 data &= ~(BIT(3) | BIT(1));
7244 ocp_reg_write(tp, 0xa468, data);
7246 case PHY_STAT_LAN_ON:
7247 case PHY_STAT_PWRDN:
7249 rtl8152_apply_firmware(tp, false);
7253 /* disable ALDPS before updating the PHY parameters */
7254 r8153_aldps_en(tp, false);
7256 /* disable EEE before updating the PHY parameters */
7257 rtl_eee_enable(tp, false);
7259 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7260 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7262 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7263 ocp_data |= PFM_PWM_SWITCH;
7264 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7266 switch (tp->version) {
7268 data = ocp_reg_read(tp, 0xad40);
7270 data |= BIT(7) | BIT(2);
7271 ocp_reg_write(tp, 0xad40, data);
7273 data = ocp_reg_read(tp, 0xad4e);
7275 ocp_reg_write(tp, 0xad4e, data);
7276 data = ocp_reg_read(tp, 0xad16);
7279 ocp_reg_write(tp, 0xad16, data);
7280 data = ocp_reg_read(tp, 0xad32);
7283 ocp_reg_write(tp, 0xad32, data);
7284 data = ocp_reg_read(tp, 0xac08);
7285 data &= ~(BIT(12) | BIT(8));
7286 ocp_reg_write(tp, 0xac08, data);
7287 data = ocp_reg_read(tp, 0xac8a);
7288 data |= BIT(12) | BIT(13) | BIT(14);
7290 ocp_reg_write(tp, 0xac8a, data);
7291 data = ocp_reg_read(tp, 0xad18);
7293 ocp_reg_write(tp, 0xad18, data);
7294 data = ocp_reg_read(tp, 0xad1a);
7296 ocp_reg_write(tp, 0xad1a, data);
7297 data = ocp_reg_read(tp, 0xad1c);
7299 ocp_reg_write(tp, 0xad1c, data);
7301 data = sram_read(tp, 0x80ea);
7304 sram_write(tp, 0x80ea, data);
7305 data = sram_read(tp, 0x80eb);
7308 sram_write(tp, 0x80eb, data);
7309 data = sram_read(tp, 0x80f8);
7312 sram_write(tp, 0x80f8, data);
7313 data = sram_read(tp, 0x80f1);
7316 sram_write(tp, 0x80f1, data);
7318 data = sram_read(tp, 0x80fe);
7321 sram_write(tp, 0x80fe, data);
7322 data = sram_read(tp, 0x8102);
7325 sram_write(tp, 0x8102, data);
7326 data = sram_read(tp, 0x8015);
7329 sram_write(tp, 0x8015, data);
7330 data = sram_read(tp, 0x8100);
7333 sram_write(tp, 0x8100, data);
7334 data = sram_read(tp, 0x8014);
7337 sram_write(tp, 0x8014, data);
7338 data = sram_read(tp, 0x8016);
7341 sram_write(tp, 0x8016, data);
7342 data = sram_read(tp, 0x80dc);
7345 sram_write(tp, 0x80dc, data);
7346 data = sram_read(tp, 0x80df);
7348 sram_write(tp, 0x80df, data);
7349 data = sram_read(tp, 0x80e1);
7351 sram_write(tp, 0x80e1, data);
7353 data = ocp_reg_read(tp, 0xbf06);
7356 ocp_reg_write(tp, 0xbf06, data);
7358 sram_write(tp, 0x819f, 0xddb6);
7360 ocp_reg_write(tp, 0xbc34, 0x5555);
7361 data = ocp_reg_read(tp, 0xbf0a);
7364 ocp_reg_write(tp, 0xbf0a, data);
7366 data = ocp_reg_read(tp, 0xbd2c);
7368 ocp_reg_write(tp, 0xbd2c, data);
7371 data = ocp_reg_read(tp, 0xad16);
7373 ocp_reg_write(tp, 0xad16, data);
7374 data = ocp_reg_read(tp, 0xad32);
7377 ocp_reg_write(tp, 0xad32, data);
7378 data = ocp_reg_read(tp, 0xac08);
7379 data &= ~(BIT(12) | BIT(8));
7380 ocp_reg_write(tp, 0xac08, data);
7381 data = ocp_reg_read(tp, 0xacc0);
7384 ocp_reg_write(tp, 0xacc0, data);
7385 data = ocp_reg_read(tp, 0xad40);
7387 data |= BIT(6) | BIT(2);
7388 ocp_reg_write(tp, 0xad40, data);
7389 data = ocp_reg_read(tp, 0xac14);
7391 ocp_reg_write(tp, 0xac14, data);
7392 data = ocp_reg_read(tp, 0xac80);
7393 data &= ~(BIT(8) | BIT(9));
7394 ocp_reg_write(tp, 0xac80, data);
7395 data = ocp_reg_read(tp, 0xac5e);
7398 ocp_reg_write(tp, 0xac5e, data);
7399 ocp_reg_write(tp, 0xad4c, 0x00a8);
7400 ocp_reg_write(tp, 0xac5c, 0x01ff);
7401 data = ocp_reg_read(tp, 0xac8a);
7403 data |= BIT(4) | BIT(5);
7404 ocp_reg_write(tp, 0xac8a, data);
7405 ocp_reg_write(tp, 0xb87c, 0x8157);
7406 data = ocp_reg_read(tp, 0xb87e);
7409 ocp_reg_write(tp, 0xb87e, data);
7410 ocp_reg_write(tp, 0xb87c, 0x8159);
7411 data = ocp_reg_read(tp, 0xb87e);
7414 ocp_reg_write(tp, 0xb87e, data);
7417 ocp_reg_write(tp, 0xb87c, 0x80a2);
7418 ocp_reg_write(tp, 0xb87e, 0x0153);
7419 ocp_reg_write(tp, 0xb87c, 0x809c);
7420 ocp_reg_write(tp, 0xb87e, 0x0153);
7423 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
7425 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7426 ocp_data |= EN_XG_LIP | EN_G_LIP;
7427 ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7429 sram_write(tp, 0x8257, 0x020f); /* XG PLL */
7430 sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */
7432 if (rtl_phy_patch_request(tp, true, true))
7436 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7437 ocp_data |= EEE_SPDWN_EN;
7438 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7440 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7441 data &= ~(EN_EEE_100 | EN_EEE_1000);
7442 data |= EN_10M_CLKDIV;
7443 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7444 tp->ups_info._10m_ckdiv = true;
7445 tp->ups_info.eee_plloff_100 = false;
7446 tp->ups_info.eee_plloff_giga = false;
7448 data = ocp_reg_read(tp, OCP_POWER_CFG);
7449 data &= ~EEE_CLKDIV_EN;
7450 ocp_reg_write(tp, OCP_POWER_CFG, data);
7451 tp->ups_info.eee_ckdiv = false;
7453 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
7454 ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
7455 tp->ups_info._250m_ckdiv = false;
7457 rtl_phy_patch_request(tp, false, true);
7459 /* enable ADC Ibias Cal */
7460 data = ocp_reg_read(tp, 0xd068);
7462 ocp_reg_write(tp, 0xd068, data);
7464 /* enable Thermal Sensor */
7465 data = sram_read(tp, 0x81a2);
7467 sram_write(tp, 0x81a2, data);
7468 data = ocp_reg_read(tp, 0xb54c);
7471 ocp_reg_write(tp, 0xb54c, data);
7473 /* Nway 2.5G Lite */
7474 data = ocp_reg_read(tp, 0xa454);
7476 ocp_reg_write(tp, 0xa454, data);
7478 /* CS DSP solution */
7479 data = ocp_reg_read(tp, OCP_10GBT_CTRL);
7480 data |= RTL_ADV2_5G_F_R;
7481 ocp_reg_write(tp, OCP_10GBT_CTRL, data);
7482 data = ocp_reg_read(tp, 0xad4e);
7484 ocp_reg_write(tp, 0xad4e, data);
7485 data = ocp_reg_read(tp, 0xa86a);
7487 ocp_reg_write(tp, 0xa86a, data);
7490 if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
7491 (ocp_reg_read(tp, 0xd068) & BIT(1))) {
7494 data = ocp_reg_read(tp, 0xd068);
7496 data |= 0x1; /* p0 */
7497 ocp_reg_write(tp, 0xd068, data);
7498 swap_a = ocp_reg_read(tp, 0xd06a);
7500 data |= 0x18; /* p3 */
7501 ocp_reg_write(tp, 0xd068, data);
7502 swap_b = ocp_reg_read(tp, 0xd06a);
7503 data &= ~0x18; /* p0 */
7504 ocp_reg_write(tp, 0xd068, data);
7505 ocp_reg_write(tp, 0xd06a,
7506 (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7507 data |= 0x18; /* p3 */
7508 ocp_reg_write(tp, 0xd068, data);
7509 ocp_reg_write(tp, 0xd06a,
7510 (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7512 data |= 0x08; /* p1 */
7513 ocp_reg_write(tp, 0xd068, data);
7514 swap_a = ocp_reg_read(tp, 0xd06a);
7516 data |= 0x10; /* p2 */
7517 ocp_reg_write(tp, 0xd068, data);
7518 swap_b = ocp_reg_read(tp, 0xd06a);
7520 data |= 0x08; /* p1 */
7521 ocp_reg_write(tp, 0xd068, data);
7522 ocp_reg_write(tp, 0xd06a,
7523 (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7525 data |= 0x10; /* p2 */
7526 ocp_reg_write(tp, 0xd068, data);
7527 ocp_reg_write(tp, 0xd06a,
7528 (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7529 swap_a = ocp_reg_read(tp, 0xbd5a);
7530 swap_b = ocp_reg_read(tp, 0xbd5c);
7531 ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) |
7532 ((swap_b & 0x1f) << 8) |
7533 ((swap_b >> 8) & 0x1f));
7534 ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) |
7535 ((swap_a & 0x1f) << 8) |
7536 ((swap_a >> 8) & 0x1f));
7537 swap_a = ocp_reg_read(tp, 0xbc18);
7538 swap_b = ocp_reg_read(tp, 0xbc1a);
7539 ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) |
7540 ((swap_b & 0x1f) << 8) |
7541 ((swap_b >> 8) & 0x1f));
7542 ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) |
7543 ((swap_a & 0x1f) << 8) |
7544 ((swap_a >> 8) & 0x1f));
7547 /* Notify the MAC when the speed is changed to force mode. */
7548 data = ocp_reg_read(tp, OCP_INTR_EN);
7549 data |= INTR_SPEED_FORCE;
7550 ocp_reg_write(tp, OCP_INTR_EN, data);
7556 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7558 data = ocp_reg_read(tp, 0xa428);
7560 ocp_reg_write(tp, 0xa428, data);
7561 data = ocp_reg_read(tp, 0xa5ea);
7563 ocp_reg_write(tp, 0xa5ea, data);
7564 tp->ups_info.lite_mode = 0;
7567 rtl_eee_enable(tp, true);
7569 r8153_aldps_en(tp, true);
7570 r8152b_enable_fc(tp);
7571 r8153_u2p3en(tp, true);
7573 set_bit(PHY_RESET, &tp->flags);
7576 static void r8156b_hw_phy_cfg(struct r8152 *tp)
7581 switch (tp->version) {
7583 ocp_reg_write(tp, 0xbf86, 0x9000);
7584 data = ocp_reg_read(tp, 0xc402);
7586 ocp_reg_write(tp, 0xc402, data);
7588 ocp_reg_write(tp, 0xc402, data);
7589 ocp_reg_write(tp, 0xbd86, 0x1010);
7590 ocp_reg_write(tp, 0xbd88, 0x1010);
7591 data = ocp_reg_read(tp, 0xbd4e);
7592 data &= ~(BIT(10) | BIT(11));
7594 ocp_reg_write(tp, 0xbd4e, data);
7595 data = ocp_reg_read(tp, 0xbf46);
7598 ocp_reg_write(tp, 0xbf46, data);
7602 r8156b_wait_loading_flash(tp);
7608 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7609 if (ocp_data & PCUT_STATUS) {
7610 ocp_data &= ~PCUT_STATUS;
7611 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7614 data = r8153_phy_status(tp, 0);
7616 case PHY_STAT_EXT_INIT:
7617 rtl8152_apply_firmware(tp, true);
7619 data = ocp_reg_read(tp, 0xa466);
7621 ocp_reg_write(tp, 0xa466, data);
7623 data = ocp_reg_read(tp, 0xa468);
7624 data &= ~(BIT(3) | BIT(1));
7625 ocp_reg_write(tp, 0xa468, data);
7627 case PHY_STAT_LAN_ON:
7628 case PHY_STAT_PWRDN:
7630 rtl8152_apply_firmware(tp, false);
7634 data = r8152_mdio_read(tp, MII_BMCR);
7635 if (data & BMCR_PDOWN) {
7636 data &= ~BMCR_PDOWN;
7637 r8152_mdio_write(tp, MII_BMCR, data);
7640 /* disable ALDPS before updating the PHY parameters */
7641 r8153_aldps_en(tp, false);
7643 /* disable EEE before updating the PHY parameters */
7644 rtl_eee_enable(tp, false);
7646 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7647 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7649 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7650 ocp_data |= PFM_PWM_SWITCH;
7651 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7653 switch (tp->version) {
7655 data = ocp_reg_read(tp, 0xbc08);
7656 data |= BIT(3) | BIT(2);
7657 ocp_reg_write(tp, 0xbc08, data);
7659 data = sram_read(tp, 0x8fff);
7662 sram_write(tp, 0x8fff, data);
7664 data = ocp_reg_read(tp, 0xacda);
7666 ocp_reg_write(tp, 0xacda, data);
7667 data = ocp_reg_read(tp, 0xacde);
7669 ocp_reg_write(tp, 0xacde, data);
7670 ocp_reg_write(tp, 0xac8c, 0x0ffc);
7671 ocp_reg_write(tp, 0xac46, 0xb7b4);
7672 ocp_reg_write(tp, 0xac50, 0x0fbc);
7673 ocp_reg_write(tp, 0xac3c, 0x9240);
7674 ocp_reg_write(tp, 0xac4e, 0x0db4);
7675 ocp_reg_write(tp, 0xacc6, 0x0707);
7676 ocp_reg_write(tp, 0xacc8, 0xa0d3);
7677 ocp_reg_write(tp, 0xad08, 0x0007);
7679 ocp_reg_write(tp, 0xb87c, 0x8560);
7680 ocp_reg_write(tp, 0xb87e, 0x19cc);
7681 ocp_reg_write(tp, 0xb87c, 0x8562);
7682 ocp_reg_write(tp, 0xb87e, 0x19cc);
7683 ocp_reg_write(tp, 0xb87c, 0x8564);
7684 ocp_reg_write(tp, 0xb87e, 0x19cc);
7685 ocp_reg_write(tp, 0xb87c, 0x8566);
7686 ocp_reg_write(tp, 0xb87e, 0x147d);
7687 ocp_reg_write(tp, 0xb87c, 0x8568);
7688 ocp_reg_write(tp, 0xb87e, 0x147d);
7689 ocp_reg_write(tp, 0xb87c, 0x856a);
7690 ocp_reg_write(tp, 0xb87e, 0x147d);
7691 ocp_reg_write(tp, 0xb87c, 0x8ffe);
7692 ocp_reg_write(tp, 0xb87e, 0x0907);
7693 ocp_reg_write(tp, 0xb87c, 0x80d6);
7694 ocp_reg_write(tp, 0xb87e, 0x2801);
7695 ocp_reg_write(tp, 0xb87c, 0x80f2);
7696 ocp_reg_write(tp, 0xb87e, 0x2801);
7697 ocp_reg_write(tp, 0xb87c, 0x80f4);
7698 ocp_reg_write(tp, 0xb87e, 0x6077);
7699 ocp_reg_write(tp, 0xb506, 0x01e7);
7701 ocp_reg_write(tp, 0xb87c, 0x8013);
7702 ocp_reg_write(tp, 0xb87e, 0x0700);
7703 ocp_reg_write(tp, 0xb87c, 0x8fb9);
7704 ocp_reg_write(tp, 0xb87e, 0x2801);
7705 ocp_reg_write(tp, 0xb87c, 0x8fba);
7706 ocp_reg_write(tp, 0xb87e, 0x0100);
7707 ocp_reg_write(tp, 0xb87c, 0x8fbc);
7708 ocp_reg_write(tp, 0xb87e, 0x1900);
7709 ocp_reg_write(tp, 0xb87c, 0x8fbe);
7710 ocp_reg_write(tp, 0xb87e, 0xe100);
7711 ocp_reg_write(tp, 0xb87c, 0x8fc0);
7712 ocp_reg_write(tp, 0xb87e, 0x0800);
7713 ocp_reg_write(tp, 0xb87c, 0x8fc2);
7714 ocp_reg_write(tp, 0xb87e, 0xe500);
7715 ocp_reg_write(tp, 0xb87c, 0x8fc4);
7716 ocp_reg_write(tp, 0xb87e, 0x0f00);
7717 ocp_reg_write(tp, 0xb87c, 0x8fc6);
7718 ocp_reg_write(tp, 0xb87e, 0xf100);
7719 ocp_reg_write(tp, 0xb87c, 0x8fc8);
7720 ocp_reg_write(tp, 0xb87e, 0x0400);
7721 ocp_reg_write(tp, 0xb87c, 0x8fca);
7722 ocp_reg_write(tp, 0xb87e, 0xf300);
7723 ocp_reg_write(tp, 0xb87c, 0x8fcc);
7724 ocp_reg_write(tp, 0xb87e, 0xfd00);
7725 ocp_reg_write(tp, 0xb87c, 0x8fce);
7726 ocp_reg_write(tp, 0xb87e, 0xff00);
7727 ocp_reg_write(tp, 0xb87c, 0x8fd0);
7728 ocp_reg_write(tp, 0xb87e, 0xfb00);
7729 ocp_reg_write(tp, 0xb87c, 0x8fd2);
7730 ocp_reg_write(tp, 0xb87e, 0x0100);
7731 ocp_reg_write(tp, 0xb87c, 0x8fd4);
7732 ocp_reg_write(tp, 0xb87e, 0xf400);
7733 ocp_reg_write(tp, 0xb87c, 0x8fd6);
7734 ocp_reg_write(tp, 0xb87e, 0xff00);
7735 ocp_reg_write(tp, 0xb87c, 0x8fd8);
7736 ocp_reg_write(tp, 0xb87e, 0xf600);
7738 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7739 ocp_data |= EN_XG_LIP | EN_G_LIP;
7740 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7741 ocp_reg_write(tp, 0xb87c, 0x813d);
7742 ocp_reg_write(tp, 0xb87e, 0x390e);
7743 ocp_reg_write(tp, 0xb87c, 0x814f);
7744 ocp_reg_write(tp, 0xb87e, 0x790e);
7745 ocp_reg_write(tp, 0xb87c, 0x80b0);
7746 ocp_reg_write(tp, 0xb87e, 0x0f31);
7747 data = ocp_reg_read(tp, 0xbf4c);
7749 ocp_reg_write(tp, 0xbf4c, data);
7750 data = ocp_reg_read(tp, 0xbcca);
7751 data |= BIT(9) | BIT(8);
7752 ocp_reg_write(tp, 0xbcca, data);
7753 ocp_reg_write(tp, 0xb87c, 0x8141);
7754 ocp_reg_write(tp, 0xb87e, 0x320e);
7755 ocp_reg_write(tp, 0xb87c, 0x8153);
7756 ocp_reg_write(tp, 0xb87e, 0x720e);
7757 ocp_reg_write(tp, 0xb87c, 0x8529);
7758 ocp_reg_write(tp, 0xb87e, 0x050e);
7759 data = ocp_reg_read(tp, OCP_EEE_CFG);
7760 data &= ~CTAP_SHORT_EN;
7761 ocp_reg_write(tp, OCP_EEE_CFG, data);
7763 sram_write(tp, 0x816c, 0xc4a0);
7764 sram_write(tp, 0x8170, 0xc4a0);
7765 sram_write(tp, 0x8174, 0x04a0);
7766 sram_write(tp, 0x8178, 0x04a0);
7767 sram_write(tp, 0x817c, 0x0719);
7768 sram_write(tp, 0x8ff4, 0x0400);
7769 sram_write(tp, 0x8ff1, 0x0404);
7771 ocp_reg_write(tp, 0xbf4a, 0x001b);
7772 ocp_reg_write(tp, 0xb87c, 0x8033);
7773 ocp_reg_write(tp, 0xb87e, 0x7c13);
7774 ocp_reg_write(tp, 0xb87c, 0x8037);
7775 ocp_reg_write(tp, 0xb87e, 0x7c13);
7776 ocp_reg_write(tp, 0xb87c, 0x803b);
7777 ocp_reg_write(tp, 0xb87e, 0xfc32);
7778 ocp_reg_write(tp, 0xb87c, 0x803f);
7779 ocp_reg_write(tp, 0xb87e, 0x7c13);
7780 ocp_reg_write(tp, 0xb87c, 0x8043);
7781 ocp_reg_write(tp, 0xb87e, 0x7c13);
7782 ocp_reg_write(tp, 0xb87c, 0x8047);
7783 ocp_reg_write(tp, 0xb87e, 0x7c13);
7785 ocp_reg_write(tp, 0xb87c, 0x8145);
7786 ocp_reg_write(tp, 0xb87e, 0x370e);
7787 ocp_reg_write(tp, 0xb87c, 0x8157);
7788 ocp_reg_write(tp, 0xb87e, 0x770e);
7789 ocp_reg_write(tp, 0xb87c, 0x8169);
7790 ocp_reg_write(tp, 0xb87e, 0x0d0a);
7791 ocp_reg_write(tp, 0xb87c, 0x817b);
7792 ocp_reg_write(tp, 0xb87e, 0x1d0a);
7794 data = sram_read(tp, 0x8217);
7797 sram_write(tp, 0x8217, data);
7798 data = sram_read(tp, 0x821a);
7801 sram_write(tp, 0x821a, data);
7802 sram_write(tp, 0x80da, 0x0403);
7803 data = sram_read(tp, 0x80dc);
7806 sram_write(tp, 0x80dc, data);
7807 sram_write(tp, 0x80b3, 0x0384);
7808 sram_write(tp, 0x80b7, 0x2007);
7809 data = sram_read(tp, 0x80ba);
7812 sram_write(tp, 0x80ba, data);
7813 sram_write(tp, 0x80b5, 0xf009);
7814 data = sram_read(tp, 0x80bd);
7817 sram_write(tp, 0x80bd, data);
7818 sram_write(tp, 0x80c7, 0xf083);
7819 sram_write(tp, 0x80dd, 0x03f0);
7820 data = sram_read(tp, 0x80df);
7823 sram_write(tp, 0x80df, data);
7824 sram_write(tp, 0x80cb, 0x2007);
7825 data = sram_read(tp, 0x80ce);
7828 sram_write(tp, 0x80ce, data);
7829 sram_write(tp, 0x80c9, 0x8009);
7830 data = sram_read(tp, 0x80d1);
7833 sram_write(tp, 0x80d1, data);
7834 sram_write(tp, 0x80a3, 0x200a);
7835 sram_write(tp, 0x80a5, 0xf0ad);
7836 sram_write(tp, 0x809f, 0x6073);
7837 sram_write(tp, 0x80a1, 0x000b);
7838 data = sram_read(tp, 0x80a9);
7841 sram_write(tp, 0x80a9, data);
7843 if (rtl_phy_patch_request(tp, true, true))
7846 data = ocp_reg_read(tp, 0xb896);
7848 ocp_reg_write(tp, 0xb896, data);
7849 data = ocp_reg_read(tp, 0xb892);
7851 ocp_reg_write(tp, 0xb892, data);
7852 ocp_reg_write(tp, 0xb88e, 0xc23e);
7853 ocp_reg_write(tp, 0xb890, 0x0000);
7854 ocp_reg_write(tp, 0xb88e, 0xc240);
7855 ocp_reg_write(tp, 0xb890, 0x0103);
7856 ocp_reg_write(tp, 0xb88e, 0xc242);
7857 ocp_reg_write(tp, 0xb890, 0x0507);
7858 ocp_reg_write(tp, 0xb88e, 0xc244);
7859 ocp_reg_write(tp, 0xb890, 0x090b);
7860 ocp_reg_write(tp, 0xb88e, 0xc246);
7861 ocp_reg_write(tp, 0xb890, 0x0c0e);
7862 ocp_reg_write(tp, 0xb88e, 0xc248);
7863 ocp_reg_write(tp, 0xb890, 0x1012);
7864 ocp_reg_write(tp, 0xb88e, 0xc24a);
7865 ocp_reg_write(tp, 0xb890, 0x1416);
7866 data = ocp_reg_read(tp, 0xb896);
7868 ocp_reg_write(tp, 0xb896, data);
7870 rtl_phy_patch_request(tp, false, true);
7872 data = ocp_reg_read(tp, 0xa86a);
7874 ocp_reg_write(tp, 0xa86a, data);
7875 data = ocp_reg_read(tp, 0xa6f0);
7877 ocp_reg_write(tp, 0xa6f0, data);
7879 ocp_reg_write(tp, 0xbfa0, 0xd70d);
7880 ocp_reg_write(tp, 0xbfa2, 0x4100);
7881 ocp_reg_write(tp, 0xbfa4, 0xe868);
7882 ocp_reg_write(tp, 0xbfa6, 0xdc59);
7883 ocp_reg_write(tp, 0xb54c, 0x3c18);
7884 data = ocp_reg_read(tp, 0xbfa4);
7886 ocp_reg_write(tp, 0xbfa4, data);
7887 data = sram_read(tp, 0x817d);
7889 sram_write(tp, 0x817d, data);
7893 data = ocp_reg_read(tp, 0xac46);
7896 ocp_reg_write(tp, 0xac46, data);
7897 data = ocp_reg_read(tp, 0xad30);
7900 ocp_reg_write(tp, 0xad30, data);
7904 ocp_reg_write(tp, 0xb87c, 0x80f5);
7905 ocp_reg_write(tp, 0xb87e, 0x760e);
7906 ocp_reg_write(tp, 0xb87c, 0x8107);
7907 ocp_reg_write(tp, 0xb87e, 0x360e);
7908 ocp_reg_write(tp, 0xb87c, 0x8551);
7909 data = ocp_reg_read(tp, 0xb87e);
7912 ocp_reg_write(tp, 0xb87e, data);
7914 /* ADC_PGA parameter */
7915 data = ocp_reg_read(tp, 0xbf00);
7918 ocp_reg_write(tp, 0xbf00, data);
7919 data = ocp_reg_read(tp, 0xbf46);
7922 ocp_reg_write(tp, 0xbf46, data);
7924 /* Green Table-PGA, 1G full viterbi */
7925 sram_write(tp, 0x8044, 0x2417);
7926 sram_write(tp, 0x804a, 0x2417);
7927 sram_write(tp, 0x8050, 0x2417);
7928 sram_write(tp, 0x8056, 0x2417);
7929 sram_write(tp, 0x805c, 0x2417);
7930 sram_write(tp, 0x8062, 0x2417);
7931 sram_write(tp, 0x8068, 0x2417);
7932 sram_write(tp, 0x806e, 0x2417);
7933 sram_write(tp, 0x8074, 0x2417);
7934 sram_write(tp, 0x807a, 0x2417);
7937 data = ocp_reg_read(tp, 0xbf84);
7940 ocp_reg_write(tp, 0xbf84, data);
7946 /* Notify the MAC when the speed is changed to force mode. */
7947 data = ocp_reg_read(tp, OCP_INTR_EN);
7948 data |= INTR_SPEED_FORCE;
7949 ocp_reg_write(tp, OCP_INTR_EN, data);
7951 if (rtl_phy_patch_request(tp, true, true))
7954 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7955 ocp_data |= EEE_SPDWN_EN;
7956 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7958 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7959 data &= ~(EN_EEE_100 | EN_EEE_1000);
7960 data |= EN_10M_CLKDIV;
7961 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7962 tp->ups_info._10m_ckdiv = true;
7963 tp->ups_info.eee_plloff_100 = false;
7964 tp->ups_info.eee_plloff_giga = false;
7966 data = ocp_reg_read(tp, OCP_POWER_CFG);
7967 data &= ~EEE_CLKDIV_EN;
7968 ocp_reg_write(tp, OCP_POWER_CFG, data);
7969 tp->ups_info.eee_ckdiv = false;
7971 rtl_phy_patch_request(tp, false, true);
7973 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7975 data = ocp_reg_read(tp, 0xa428);
7977 ocp_reg_write(tp, 0xa428, data);
7978 data = ocp_reg_read(tp, 0xa5ea);
7980 ocp_reg_write(tp, 0xa5ea, data);
7981 tp->ups_info.lite_mode = 0;
7984 rtl_eee_enable(tp, true);
7986 r8153_aldps_en(tp, true);
7987 r8152b_enable_fc(tp);
7988 r8153_u2p3en(tp, true);
7990 set_bit(PHY_RESET, &tp->flags);
7993 static void r8156_init(struct r8152 *tp)
7999 if (test_bit(RTL8152_UNPLUG, &tp->flags))
8002 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8003 ocp_data &= ~EN_ALL_SPEED;
8004 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
8006 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
8008 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8009 ocp_data |= BYPASS_MAC_RESET;
8010 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
8012 r8153b_u1u2en(tp, false);
8014 for (i = 0; i < 500; i++) {
8015 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8020 if (test_bit(RTL8152_UNPLUG, &tp->flags))
8024 data = r8153_phy_status(tp, 0);
8025 if (data == PHY_STAT_EXT_INIT) {
8026 data = ocp_reg_read(tp, 0xa468);
8027 data &= ~(BIT(3) | BIT(1));
8028 ocp_reg_write(tp, 0xa468, data);
8031 data = r8152_mdio_read(tp, MII_BMCR);
8032 if (data & BMCR_PDOWN) {
8033 data &= ~BMCR_PDOWN;
8034 r8152_mdio_write(tp, MII_BMCR, data);
8037 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8038 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
8040 r8153_u2p3en(tp, false);
8042 /* MSC timer = 0xfff * 8ms = 32760 ms */
8043 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
8045 /* U1/U2/L1 idle timer. 500 us */
8046 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
8048 r8153b_power_cut_en(tp, false);
8049 r8156_ups_en(tp, false);
8050 r8153_queue_wake(tp, false);
8051 rtl_runtime_suspend_enable(tp, false);
8053 if (tp->udev->speed >= USB_SPEED_SUPER)
8054 r8153b_u1u2en(tp, true);
8056 usb_enable_lpm(tp->udev);
8058 r8156_mac_clk_spd(tp, true);
8060 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8061 ocp_data &= ~PLA_MCU_SPDWN_EN;
8062 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8064 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8065 if (rtl8152_get_speed(tp) & LINK_STATUS)
8066 ocp_data |= CUR_LINK_OK;
8068 ocp_data &= ~CUR_LINK_OK;
8069 ocp_data |= POLL_LINK_CHG;
8070 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8072 set_bit(GREEN_ETHERNET, &tp->flags);
8074 /* rx aggregation */
8075 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8076 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8077 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8079 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
8080 ocp_data |= ACT_ODMA;
8081 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
8083 r8156_mdio_force_mode(tp);
8084 rtl_tally_reset(tp);
8086 tp->coalesce = 15000; /* 15 us */
8089 static void r8156b_init(struct r8152 *tp)
8095 if (test_bit(RTL8152_UNPLUG, &tp->flags))
8098 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8099 ocp_data &= ~EN_ALL_SPEED;
8100 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
8102 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
8104 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8105 ocp_data |= BYPASS_MAC_RESET;
8106 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
8108 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
8109 ocp_data |= RX_DETECT8;
8110 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
8112 r8153b_u1u2en(tp, false);
8114 switch (tp->version) {
8117 r8156b_wait_loading_flash(tp);
8123 for (i = 0; i < 500; i++) {
8124 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8129 if (test_bit(RTL8152_UNPLUG, &tp->flags))
8133 data = r8153_phy_status(tp, 0);
8134 if (data == PHY_STAT_EXT_INIT) {
8135 data = ocp_reg_read(tp, 0xa468);
8136 data &= ~(BIT(3) | BIT(1));
8137 ocp_reg_write(tp, 0xa468, data);
8139 data = ocp_reg_read(tp, 0xa466);
8141 ocp_reg_write(tp, 0xa466, data);
8144 data = r8152_mdio_read(tp, MII_BMCR);
8145 if (data & BMCR_PDOWN) {
8146 data &= ~BMCR_PDOWN;
8147 r8152_mdio_write(tp, MII_BMCR, data);
8150 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8152 r8153_u2p3en(tp, false);
8154 /* MSC timer = 0xfff * 8ms = 32760 ms */
8155 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
8157 /* U1/U2/L1 idle timer. 500 us */
8158 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
8160 r8153b_power_cut_en(tp, false);
8161 r8156_ups_en(tp, false);
8162 r8153_queue_wake(tp, false);
8163 rtl_runtime_suspend_enable(tp, false);
8165 if (tp->udev->speed >= USB_SPEED_SUPER)
8166 r8153b_u1u2en(tp, true);
8168 usb_enable_lpm(tp->udev);
8170 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
8171 ocp_data &= ~SLOT_EN;
8172 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8174 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
8175 ocp_data |= FLOW_CTRL_EN;
8176 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
8178 /* enable fc timer and set timer to 600 ms. */
8179 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
8180 CTRL_TIMER_EN | (600 / 8));
8182 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
8183 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
8184 ocp_data |= FLOW_CTRL_PATCH_2;
8185 ocp_data &= ~AUTO_SPEEDUP;
8186 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
8188 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
8189 ocp_data |= FC_PATCH_TASK;
8190 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
8192 r8156_mac_clk_spd(tp, true);
8194 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8195 ocp_data &= ~PLA_MCU_SPDWN_EN;
8196 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8198 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8199 if (rtl8152_get_speed(tp) & LINK_STATUS)
8200 ocp_data |= CUR_LINK_OK;
8202 ocp_data &= ~CUR_LINK_OK;
8203 ocp_data |= POLL_LINK_CHG;
8204 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8206 set_bit(GREEN_ETHERNET, &tp->flags);
8208 /* rx aggregation */
8209 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8210 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8211 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8213 r8156_mdio_force_mode(tp);
8214 rtl_tally_reset(tp);
8216 tp->coalesce = 15000; /* 15 us */
8219 static bool rtl_check_vendor_ok(struct usb_interface *intf)
8221 struct usb_host_interface *alt = intf->cur_altsetting;
8222 struct usb_endpoint_descriptor *in, *out, *intr;
8224 if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) {
8225 dev_err(&intf->dev, "Expected endpoints are not found\n");
8229 /* Check Rx endpoint address */
8230 if (usb_endpoint_num(in) != 1) {
8231 dev_err(&intf->dev, "Invalid Rx endpoint address\n");
8235 /* Check Tx endpoint address */
8236 if (usb_endpoint_num(out) != 2) {
8237 dev_err(&intf->dev, "Invalid Tx endpoint address\n");
8241 /* Check interrupt endpoint address */
8242 if (usb_endpoint_num(intr) != 3) {
8243 dev_err(&intf->dev, "Invalid interrupt endpoint address\n");
8250 static int rtl8152_pre_reset(struct usb_interface *intf)
8252 struct r8152 *tp = usb_get_intfdata(intf);
8253 struct net_device *netdev;
8258 netdev = tp->netdev;
8259 if (!netif_running(netdev))
8262 netif_stop_queue(netdev);
8263 tasklet_disable(&tp->tx_tl);
8264 clear_bit(WORK_ENABLE, &tp->flags);
8265 usb_kill_urb(tp->intr_urb);
8266 cancel_delayed_work_sync(&tp->schedule);
8267 napi_disable(&tp->napi);
8268 if (netif_carrier_ok(netdev)) {
8269 mutex_lock(&tp->control);
8270 tp->rtl_ops.disable(tp);
8271 mutex_unlock(&tp->control);
8277 static int rtl8152_post_reset(struct usb_interface *intf)
8279 struct r8152 *tp = usb_get_intfdata(intf);
8280 struct net_device *netdev;
8286 /* reset the MAC address in case of policy change */
8287 if (determine_ethernet_addr(tp, &sa) >= 0) {
8289 dev_set_mac_address (tp->netdev, &sa, NULL);
8293 netdev = tp->netdev;
8294 if (!netif_running(netdev))
8297 set_bit(WORK_ENABLE, &tp->flags);
8298 if (netif_carrier_ok(netdev)) {
8299 mutex_lock(&tp->control);
8300 tp->rtl_ops.enable(tp);
8302 _rtl8152_set_rx_mode(netdev);
8303 mutex_unlock(&tp->control);
8306 napi_enable(&tp->napi);
8307 tasklet_enable(&tp->tx_tl);
8308 netif_wake_queue(netdev);
8309 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
8311 if (!list_empty(&tp->rx_done))
8312 napi_schedule(&tp->napi);
8317 static bool delay_autosuspend(struct r8152 *tp)
8319 bool sw_linking = !!netif_carrier_ok(tp->netdev);
8320 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
8322 /* This means a linking change occurs and the driver doesn't detect it,
8323 * yet. If the driver has disabled tx/rx and hw is linking on, the
8324 * device wouldn't wake up by receiving any packet.
8326 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
8329 /* If the linking down is occurred by nway, the device may miss the
8330 * linking change event. And it wouldn't wake when linking on.
8332 if (!sw_linking && tp->rtl_ops.in_nway(tp))
8334 else if (!skb_queue_empty(&tp->tx_queue))
8340 static int rtl8152_runtime_resume(struct r8152 *tp)
8342 struct net_device *netdev = tp->netdev;
8344 if (netif_running(netdev) && netdev->flags & IFF_UP) {
8345 struct napi_struct *napi = &tp->napi;
8347 tp->rtl_ops.autosuspend_en(tp, false);
8349 set_bit(WORK_ENABLE, &tp->flags);
8351 if (netif_carrier_ok(netdev)) {
8352 if (rtl8152_get_speed(tp) & LINK_STATUS) {
8355 netif_carrier_off(netdev);
8356 tp->rtl_ops.disable(tp);
8357 netif_info(tp, link, netdev, "linking down\n");
8362 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8363 smp_mb__after_atomic();
8365 if (!list_empty(&tp->rx_done))
8366 napi_schedule(&tp->napi);
8368 usb_submit_urb(tp->intr_urb, GFP_NOIO);
8370 if (netdev->flags & IFF_UP)
8371 tp->rtl_ops.autosuspend_en(tp, false);
8373 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8379 static int rtl8152_system_resume(struct r8152 *tp)
8381 struct net_device *netdev = tp->netdev;
8383 netif_device_attach(netdev);
8385 if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
8387 netif_carrier_off(netdev);
8388 set_bit(WORK_ENABLE, &tp->flags);
8389 usb_submit_urb(tp->intr_urb, GFP_NOIO);
8395 static int rtl8152_runtime_suspend(struct r8152 *tp)
8397 struct net_device *netdev = tp->netdev;
8400 if (!tp->rtl_ops.autosuspend_en)
8403 set_bit(SELECTIVE_SUSPEND, &tp->flags);
8404 smp_mb__after_atomic();
8406 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8409 if (netif_carrier_ok(netdev)) {
8412 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
8413 ocp_data = rcr & ~RCR_ACPT_ALL;
8414 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8415 rxdy_gated_en(tp, true);
8416 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
8418 if (!(ocp_data & RXFIFO_EMPTY)) {
8419 rxdy_gated_en(tp, false);
8420 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8421 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8422 smp_mb__after_atomic();
8428 clear_bit(WORK_ENABLE, &tp->flags);
8429 usb_kill_urb(tp->intr_urb);
8431 tp->rtl_ops.autosuspend_en(tp, true);
8433 if (netif_carrier_ok(netdev)) {
8434 struct napi_struct *napi = &tp->napi;
8438 rxdy_gated_en(tp, false);
8439 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8443 if (delay_autosuspend(tp)) {
8444 rtl8152_runtime_resume(tp);
8453 static int rtl8152_system_suspend(struct r8152 *tp)
8455 struct net_device *netdev = tp->netdev;
8457 netif_device_detach(netdev);
8459 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8460 struct napi_struct *napi = &tp->napi;
8462 clear_bit(WORK_ENABLE, &tp->flags);
8463 usb_kill_urb(tp->intr_urb);
8464 tasklet_disable(&tp->tx_tl);
8466 cancel_delayed_work_sync(&tp->schedule);
8467 tp->rtl_ops.down(tp);
8469 tasklet_enable(&tp->tx_tl);
8475 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
8477 struct r8152 *tp = usb_get_intfdata(intf);
8480 mutex_lock(&tp->control);
8482 if (PMSG_IS_AUTO(message))
8483 ret = rtl8152_runtime_suspend(tp);
8485 ret = rtl8152_system_suspend(tp);
8487 mutex_unlock(&tp->control);
8492 static int rtl8152_resume(struct usb_interface *intf)
8494 struct r8152 *tp = usb_get_intfdata(intf);
8497 mutex_lock(&tp->control);
8499 rtl_reset_ocp_base(tp);
8501 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
8502 ret = rtl8152_runtime_resume(tp);
8504 ret = rtl8152_system_resume(tp);
8506 mutex_unlock(&tp->control);
8511 static int rtl8152_reset_resume(struct usb_interface *intf)
8513 struct r8152 *tp = usb_get_intfdata(intf);
8515 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8516 rtl_reset_ocp_base(tp);
8517 tp->rtl_ops.init(tp);
8518 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
8519 set_ethernet_addr(tp, true);
8520 return rtl8152_resume(intf);
8523 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8525 struct r8152 *tp = netdev_priv(dev);
8527 if (usb_autopm_get_interface(tp->intf) < 0)
8530 if (!rtl_can_wakeup(tp)) {
8534 mutex_lock(&tp->control);
8535 wol->supported = WAKE_ANY;
8536 wol->wolopts = __rtl_get_wol(tp);
8537 mutex_unlock(&tp->control);
8540 usb_autopm_put_interface(tp->intf);
8543 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8545 struct r8152 *tp = netdev_priv(dev);
8548 if (!rtl_can_wakeup(tp))
8551 if (wol->wolopts & ~WAKE_ANY)
8554 ret = usb_autopm_get_interface(tp->intf);
8558 mutex_lock(&tp->control);
8560 __rtl_set_wol(tp, wol->wolopts);
8561 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
8563 mutex_unlock(&tp->control);
8565 usb_autopm_put_interface(tp->intf);
8571 static u32 rtl8152_get_msglevel(struct net_device *dev)
8573 struct r8152 *tp = netdev_priv(dev);
8575 return tp->msg_enable;
8578 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
8580 struct r8152 *tp = netdev_priv(dev);
8582 tp->msg_enable = value;
8585 static void rtl8152_get_drvinfo(struct net_device *netdev,
8586 struct ethtool_drvinfo *info)
8588 struct r8152 *tp = netdev_priv(netdev);
8590 strscpy(info->driver, MODULENAME, sizeof(info->driver));
8591 strscpy(info->version, DRIVER_VERSION, sizeof(info->version));
8592 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
8593 if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
8594 strscpy(info->fw_version, tp->rtl_fw.version,
8595 sizeof(info->fw_version));
8599 int rtl8152_get_link_ksettings(struct net_device *netdev,
8600 struct ethtool_link_ksettings *cmd)
8602 struct r8152 *tp = netdev_priv(netdev);
8605 if (!tp->mii.mdio_read)
8608 ret = usb_autopm_get_interface(tp->intf);
8612 mutex_lock(&tp->control);
8614 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
8616 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8617 cmd->link_modes.supported, tp->support_2500full);
8619 if (tp->support_2500full) {
8620 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8621 cmd->link_modes.advertising,
8622 ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
8624 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8625 cmd->link_modes.lp_advertising,
8626 ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
8628 if (is_speed_2500(rtl8152_get_speed(tp)))
8629 cmd->base.speed = SPEED_2500;
8632 mutex_unlock(&tp->control);
8634 usb_autopm_put_interface(tp->intf);
8640 static int rtl8152_set_link_ksettings(struct net_device *dev,
8641 const struct ethtool_link_ksettings *cmd)
8643 struct r8152 *tp = netdev_priv(dev);
8644 u32 advertising = 0;
8647 ret = usb_autopm_get_interface(tp->intf);
8651 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
8652 cmd->link_modes.advertising))
8653 advertising |= RTL_ADVERTISED_10_HALF;
8655 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
8656 cmd->link_modes.advertising))
8657 advertising |= RTL_ADVERTISED_10_FULL;
8659 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
8660 cmd->link_modes.advertising))
8661 advertising |= RTL_ADVERTISED_100_HALF;
8663 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
8664 cmd->link_modes.advertising))
8665 advertising |= RTL_ADVERTISED_100_FULL;
8667 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
8668 cmd->link_modes.advertising))
8669 advertising |= RTL_ADVERTISED_1000_HALF;
8671 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
8672 cmd->link_modes.advertising))
8673 advertising |= RTL_ADVERTISED_1000_FULL;
8675 if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8676 cmd->link_modes.advertising))
8677 advertising |= RTL_ADVERTISED_2500_FULL;
8679 mutex_lock(&tp->control);
8681 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
8682 cmd->base.duplex, advertising);
8684 tp->autoneg = cmd->base.autoneg;
8685 tp->speed = cmd->base.speed;
8686 tp->duplex = cmd->base.duplex;
8687 tp->advertising = advertising;
8690 mutex_unlock(&tp->control);
8692 usb_autopm_put_interface(tp->intf);
8698 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
8705 "tx_single_collisions",
8706 "tx_multi_collisions",
8714 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
8718 return ARRAY_SIZE(rtl8152_gstrings);
8724 static void rtl8152_get_ethtool_stats(struct net_device *dev,
8725 struct ethtool_stats *stats, u64 *data)
8727 struct r8152 *tp = netdev_priv(dev);
8728 struct tally_counter tally;
8730 if (usb_autopm_get_interface(tp->intf) < 0)
8733 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
8735 usb_autopm_put_interface(tp->intf);
8737 data[0] = le64_to_cpu(tally.tx_packets);
8738 data[1] = le64_to_cpu(tally.rx_packets);
8739 data[2] = le64_to_cpu(tally.tx_errors);
8740 data[3] = le32_to_cpu(tally.rx_errors);
8741 data[4] = le16_to_cpu(tally.rx_missed);
8742 data[5] = le16_to_cpu(tally.align_errors);
8743 data[6] = le32_to_cpu(tally.tx_one_collision);
8744 data[7] = le32_to_cpu(tally.tx_multi_collision);
8745 data[8] = le64_to_cpu(tally.rx_unicast);
8746 data[9] = le64_to_cpu(tally.rx_broadcast);
8747 data[10] = le32_to_cpu(tally.rx_multicast);
8748 data[11] = le16_to_cpu(tally.tx_aborted);
8749 data[12] = le16_to_cpu(tally.tx_underrun);
8752 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
8754 switch (stringset) {
8756 memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
8761 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8763 u32 lp, adv, supported = 0;
8766 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
8767 supported = mmd_eee_cap_to_ethtool_sup_t(val);
8769 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
8770 adv = mmd_eee_adv_to_ethtool_adv_t(val);
8772 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
8773 lp = mmd_eee_adv_to_ethtool_adv_t(val);
8775 eee->eee_enabled = tp->eee_en;
8776 eee->eee_active = !!(supported & adv & lp);
8777 eee->supported = supported;
8778 eee->advertised = tp->eee_adv;
8779 eee->lp_advertised = lp;
8784 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
8786 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
8788 tp->eee_en = eee->eee_enabled;
8791 rtl_eee_enable(tp, tp->eee_en);
8796 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8798 u32 lp, adv, supported = 0;
8801 val = ocp_reg_read(tp, OCP_EEE_ABLE);
8802 supported = mmd_eee_cap_to_ethtool_sup_t(val);
8804 val = ocp_reg_read(tp, OCP_EEE_ADV);
8805 adv = mmd_eee_adv_to_ethtool_adv_t(val);
8807 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
8808 lp = mmd_eee_adv_to_ethtool_adv_t(val);
8810 eee->eee_enabled = tp->eee_en;
8811 eee->eee_active = !!(supported & adv & lp);
8812 eee->supported = supported;
8813 eee->advertised = tp->eee_adv;
8814 eee->lp_advertised = lp;
8820 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
8822 struct r8152 *tp = netdev_priv(net);
8825 if (!tp->rtl_ops.eee_get) {
8830 ret = usb_autopm_get_interface(tp->intf);
8834 mutex_lock(&tp->control);
8836 ret = tp->rtl_ops.eee_get(tp, edata);
8838 mutex_unlock(&tp->control);
8840 usb_autopm_put_interface(tp->intf);
8847 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
8849 struct r8152 *tp = netdev_priv(net);
8852 if (!tp->rtl_ops.eee_set) {
8857 ret = usb_autopm_get_interface(tp->intf);
8861 mutex_lock(&tp->control);
8863 ret = tp->rtl_ops.eee_set(tp, edata);
8865 ret = mii_nway_restart(&tp->mii);
8867 mutex_unlock(&tp->control);
8869 usb_autopm_put_interface(tp->intf);
8875 static int rtl8152_nway_reset(struct net_device *dev)
8877 struct r8152 *tp = netdev_priv(dev);
8880 ret = usb_autopm_get_interface(tp->intf);
8884 mutex_lock(&tp->control);
8886 ret = mii_nway_restart(&tp->mii);
8888 mutex_unlock(&tp->control);
8890 usb_autopm_put_interface(tp->intf);
8896 static int rtl8152_get_coalesce(struct net_device *netdev,
8897 struct ethtool_coalesce *coalesce,
8898 struct kernel_ethtool_coalesce *kernel_coal,
8899 struct netlink_ext_ack *extack)
8901 struct r8152 *tp = netdev_priv(netdev);
8903 switch (tp->version) {
8912 coalesce->rx_coalesce_usecs = tp->coalesce;
8917 static int rtl8152_set_coalesce(struct net_device *netdev,
8918 struct ethtool_coalesce *coalesce,
8919 struct kernel_ethtool_coalesce *kernel_coal,
8920 struct netlink_ext_ack *extack)
8922 struct r8152 *tp = netdev_priv(netdev);
8925 switch (tp->version) {
8934 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
8937 ret = usb_autopm_get_interface(tp->intf);
8941 mutex_lock(&tp->control);
8943 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
8944 tp->coalesce = coalesce->rx_coalesce_usecs;
8946 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
8947 netif_stop_queue(netdev);
8948 napi_disable(&tp->napi);
8949 tp->rtl_ops.disable(tp);
8950 tp->rtl_ops.enable(tp);
8952 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
8953 _rtl8152_set_rx_mode(netdev);
8954 napi_enable(&tp->napi);
8955 netif_wake_queue(netdev);
8959 mutex_unlock(&tp->control);
8961 usb_autopm_put_interface(tp->intf);
8966 static int rtl8152_get_tunable(struct net_device *netdev,
8967 const struct ethtool_tunable *tunable, void *d)
8969 struct r8152 *tp = netdev_priv(netdev);
8971 switch (tunable->id) {
8972 case ETHTOOL_RX_COPYBREAK:
8973 *(u32 *)d = tp->rx_copybreak;
8982 static int rtl8152_set_tunable(struct net_device *netdev,
8983 const struct ethtool_tunable *tunable,
8986 struct r8152 *tp = netdev_priv(netdev);
8989 switch (tunable->id) {
8990 case ETHTOOL_RX_COPYBREAK:
8992 if (val < ETH_ZLEN) {
8993 netif_err(tp, rx_err, netdev,
8994 "Invalid rx copy break value\n");
8998 if (tp->rx_copybreak != val) {
8999 if (netdev->flags & IFF_UP) {
9000 mutex_lock(&tp->control);
9001 napi_disable(&tp->napi);
9002 tp->rx_copybreak = val;
9003 napi_enable(&tp->napi);
9004 mutex_unlock(&tp->control);
9006 tp->rx_copybreak = val;
9017 static void rtl8152_get_ringparam(struct net_device *netdev,
9018 struct ethtool_ringparam *ring,
9019 struct kernel_ethtool_ringparam *kernel_ring,
9020 struct netlink_ext_ack *extack)
9022 struct r8152 *tp = netdev_priv(netdev);
9024 ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
9025 ring->rx_pending = tp->rx_pending;
9028 static int rtl8152_set_ringparam(struct net_device *netdev,
9029 struct ethtool_ringparam *ring,
9030 struct kernel_ethtool_ringparam *kernel_ring,
9031 struct netlink_ext_ack *extack)
9033 struct r8152 *tp = netdev_priv(netdev);
9035 if (ring->rx_pending < (RTL8152_MAX_RX * 2))
9038 if (tp->rx_pending != ring->rx_pending) {
9039 if (netdev->flags & IFF_UP) {
9040 mutex_lock(&tp->control);
9041 napi_disable(&tp->napi);
9042 tp->rx_pending = ring->rx_pending;
9043 napi_enable(&tp->napi);
9044 mutex_unlock(&tp->control);
9046 tp->rx_pending = ring->rx_pending;
9053 static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9055 struct r8152 *tp = netdev_priv(netdev);
9056 u16 bmcr, lcladv, rmtadv;
9059 if (usb_autopm_get_interface(tp->intf) < 0)
9062 mutex_lock(&tp->control);
9064 bmcr = r8152_mdio_read(tp, MII_BMCR);
9065 lcladv = r8152_mdio_read(tp, MII_ADVERTISE);
9066 rmtadv = r8152_mdio_read(tp, MII_LPA);
9068 mutex_unlock(&tp->control);
9070 usb_autopm_put_interface(tp->intf);
9072 if (!(bmcr & BMCR_ANENABLE)) {
9074 pause->rx_pause = 0;
9075 pause->tx_pause = 0;
9081 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
9083 if (cap & FLOW_CTRL_RX)
9084 pause->rx_pause = 1;
9086 if (cap & FLOW_CTRL_TX)
9087 pause->tx_pause = 1;
9090 static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9092 struct r8152 *tp = netdev_priv(netdev);
9097 ret = usb_autopm_get_interface(tp->intf);
9101 mutex_lock(&tp->control);
9103 if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) {
9108 if (pause->rx_pause)
9109 cap |= FLOW_CTRL_RX;
9111 if (pause->tx_pause)
9112 cap |= FLOW_CTRL_TX;
9114 old = r8152_mdio_read(tp, MII_ADVERTISE);
9115 new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap);
9117 r8152_mdio_write(tp, MII_ADVERTISE, new1);
9120 mutex_unlock(&tp->control);
9121 usb_autopm_put_interface(tp->intf);
9126 static const struct ethtool_ops ops = {
9127 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
9128 .get_drvinfo = rtl8152_get_drvinfo,
9129 .get_link = ethtool_op_get_link,
9130 .nway_reset = rtl8152_nway_reset,
9131 .get_msglevel = rtl8152_get_msglevel,
9132 .set_msglevel = rtl8152_set_msglevel,
9133 .get_wol = rtl8152_get_wol,
9134 .set_wol = rtl8152_set_wol,
9135 .get_strings = rtl8152_get_strings,
9136 .get_sset_count = rtl8152_get_sset_count,
9137 .get_ethtool_stats = rtl8152_get_ethtool_stats,
9138 .get_coalesce = rtl8152_get_coalesce,
9139 .set_coalesce = rtl8152_set_coalesce,
9140 .get_eee = rtl_ethtool_get_eee,
9141 .set_eee = rtl_ethtool_set_eee,
9142 .get_link_ksettings = rtl8152_get_link_ksettings,
9143 .set_link_ksettings = rtl8152_set_link_ksettings,
9144 .get_tunable = rtl8152_get_tunable,
9145 .set_tunable = rtl8152_set_tunable,
9146 .get_ringparam = rtl8152_get_ringparam,
9147 .set_ringparam = rtl8152_set_ringparam,
9148 .get_pauseparam = rtl8152_get_pauseparam,
9149 .set_pauseparam = rtl8152_set_pauseparam,
9152 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
9154 struct r8152 *tp = netdev_priv(netdev);
9155 struct mii_ioctl_data *data = if_mii(rq);
9158 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9161 res = usb_autopm_get_interface(tp->intf);
9167 data->phy_id = R8152_PHY_ID; /* Internal PHY */
9171 mutex_lock(&tp->control);
9172 data->val_out = r8152_mdio_read(tp, data->reg_num);
9173 mutex_unlock(&tp->control);
9177 if (!capable(CAP_NET_ADMIN)) {
9181 mutex_lock(&tp->control);
9182 r8152_mdio_write(tp, data->reg_num, data->val_in);
9183 mutex_unlock(&tp->control);
9190 usb_autopm_put_interface(tp->intf);
9196 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
9198 struct r8152 *tp = netdev_priv(dev);
9201 switch (tp->version) {
9211 ret = usb_autopm_get_interface(tp->intf);
9215 mutex_lock(&tp->control);
9219 if (netif_running(dev)) {
9220 if (tp->rtl_ops.change_mtu)
9221 tp->rtl_ops.change_mtu(tp);
9223 if (netif_carrier_ok(dev)) {
9224 netif_stop_queue(dev);
9225 napi_disable(&tp->napi);
9226 tasklet_disable(&tp->tx_tl);
9227 tp->rtl_ops.disable(tp);
9228 tp->rtl_ops.enable(tp);
9230 tasklet_enable(&tp->tx_tl);
9231 napi_enable(&tp->napi);
9232 rtl8152_set_rx_mode(dev);
9233 netif_wake_queue(dev);
9237 mutex_unlock(&tp->control);
9239 usb_autopm_put_interface(tp->intf);
9244 static const struct net_device_ops rtl8152_netdev_ops = {
9245 .ndo_open = rtl8152_open,
9246 .ndo_stop = rtl8152_close,
9247 .ndo_eth_ioctl = rtl8152_ioctl,
9248 .ndo_start_xmit = rtl8152_start_xmit,
9249 .ndo_tx_timeout = rtl8152_tx_timeout,
9250 .ndo_set_features = rtl8152_set_features,
9251 .ndo_set_rx_mode = rtl8152_set_rx_mode,
9252 .ndo_set_mac_address = rtl8152_set_mac_address,
9253 .ndo_change_mtu = rtl8152_change_mtu,
9254 .ndo_validate_addr = eth_validate_addr,
9255 .ndo_features_check = rtl8152_features_check,
9258 static void rtl8152_unload(struct r8152 *tp)
9260 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9263 if (tp->version != RTL_VER_01)
9264 r8152_power_cut_en(tp, true);
9267 static void rtl8153_unload(struct r8152 *tp)
9269 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9272 r8153_power_cut_en(tp, false);
9275 static void rtl8153b_unload(struct r8152 *tp)
9277 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9280 r8153b_power_cut_en(tp, false);
9283 static int rtl_ops_init(struct r8152 *tp)
9285 struct rtl_ops *ops = &tp->rtl_ops;
9288 switch (tp->version) {
9292 ops->init = r8152b_init;
9293 ops->enable = rtl8152_enable;
9294 ops->disable = rtl8152_disable;
9295 ops->up = rtl8152_up;
9296 ops->down = rtl8152_down;
9297 ops->unload = rtl8152_unload;
9298 ops->eee_get = r8152_get_eee;
9299 ops->eee_set = r8152_set_eee;
9300 ops->in_nway = rtl8152_in_nway;
9301 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
9302 ops->autosuspend_en = rtl_runtime_suspend_enable;
9303 tp->rx_buf_sz = 16 * 1024;
9305 tp->eee_adv = MDIO_EEE_100TX;
9312 ops->init = r8153_init;
9313 ops->enable = rtl8153_enable;
9314 ops->disable = rtl8153_disable;
9315 ops->up = rtl8153_up;
9316 ops->down = rtl8153_down;
9317 ops->unload = rtl8153_unload;
9318 ops->eee_get = r8153_get_eee;
9319 ops->eee_set = r8152_set_eee;
9320 ops->in_nway = rtl8153_in_nway;
9321 ops->hw_phy_cfg = r8153_hw_phy_cfg;
9322 ops->autosuspend_en = rtl8153_runtime_enable;
9323 ops->change_mtu = rtl8153_change_mtu;
9324 if (tp->udev->speed < USB_SPEED_SUPER)
9325 tp->rx_buf_sz = 16 * 1024;
9327 tp->rx_buf_sz = 32 * 1024;
9329 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9334 ops->init = r8153b_init;
9335 ops->enable = rtl8153_enable;
9336 ops->disable = rtl8153_disable;
9337 ops->up = rtl8153b_up;
9338 ops->down = rtl8153b_down;
9339 ops->unload = rtl8153b_unload;
9340 ops->eee_get = r8153_get_eee;
9341 ops->eee_set = r8152_set_eee;
9342 ops->in_nway = rtl8153_in_nway;
9343 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
9344 ops->autosuspend_en = rtl8153b_runtime_enable;
9345 ops->change_mtu = rtl8153_change_mtu;
9346 tp->rx_buf_sz = 32 * 1024;
9348 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9353 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9356 ops->init = r8156_init;
9357 ops->enable = rtl8156_enable;
9358 ops->disable = rtl8156_disable;
9359 ops->up = rtl8156_up;
9360 ops->down = rtl8156_down;
9361 ops->unload = rtl8153_unload;
9362 ops->eee_get = r8153_get_eee;
9363 ops->eee_set = r8152_set_eee;
9364 ops->in_nway = rtl8153_in_nway;
9365 ops->hw_phy_cfg = r8156_hw_phy_cfg;
9366 ops->autosuspend_en = rtl8156_runtime_enable;
9367 ops->change_mtu = rtl8156_change_mtu;
9368 tp->rx_buf_sz = 48 * 1024;
9369 tp->support_2500full = 1;
9374 tp->support_2500full = 1;
9378 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9379 ops->init = r8156b_init;
9380 ops->enable = rtl8156b_enable;
9381 ops->disable = rtl8153_disable;
9382 ops->up = rtl8156_up;
9383 ops->down = rtl8156_down;
9384 ops->unload = rtl8153_unload;
9385 ops->eee_get = r8153_get_eee;
9386 ops->eee_set = r8152_set_eee;
9387 ops->in_nway = rtl8153_in_nway;
9388 ops->hw_phy_cfg = r8156b_hw_phy_cfg;
9389 ops->autosuspend_en = rtl8156_runtime_enable;
9390 ops->change_mtu = rtl8156_change_mtu;
9391 tp->rx_buf_sz = 48 * 1024;
9395 ops->init = r8153c_init;
9396 ops->enable = rtl8153_enable;
9397 ops->disable = rtl8153_disable;
9398 ops->up = rtl8153c_up;
9399 ops->down = rtl8153b_down;
9400 ops->unload = rtl8153_unload;
9401 ops->eee_get = r8153_get_eee;
9402 ops->eee_set = r8152_set_eee;
9403 ops->in_nway = rtl8153_in_nway;
9404 ops->hw_phy_cfg = r8153c_hw_phy_cfg;
9405 ops->autosuspend_en = rtl8153c_runtime_enable;
9406 ops->change_mtu = rtl8153c_change_mtu;
9407 tp->rx_buf_sz = 32 * 1024;
9409 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9414 dev_err(&tp->intf->dev, "Unknown Device\n");
9421 #define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
9422 #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
9423 #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
9424 #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
9425 #define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw"
9426 #define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw"
9427 #define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw"
9429 MODULE_FIRMWARE(FIRMWARE_8153A_2);
9430 MODULE_FIRMWARE(FIRMWARE_8153A_3);
9431 MODULE_FIRMWARE(FIRMWARE_8153A_4);
9432 MODULE_FIRMWARE(FIRMWARE_8153B_2);
9433 MODULE_FIRMWARE(FIRMWARE_8153C_1);
9434 MODULE_FIRMWARE(FIRMWARE_8156A_2);
9435 MODULE_FIRMWARE(FIRMWARE_8156B_2);
9437 static int rtl_fw_init(struct r8152 *tp)
9439 struct rtl_fw *rtl_fw = &tp->rtl_fw;
9441 switch (tp->version) {
9443 rtl_fw->fw_name = FIRMWARE_8153A_2;
9444 rtl_fw->pre_fw = r8153_pre_firmware_1;
9445 rtl_fw->post_fw = r8153_post_firmware_1;
9448 rtl_fw->fw_name = FIRMWARE_8153A_3;
9449 rtl_fw->pre_fw = r8153_pre_firmware_2;
9450 rtl_fw->post_fw = r8153_post_firmware_2;
9453 rtl_fw->fw_name = FIRMWARE_8153A_4;
9454 rtl_fw->post_fw = r8153_post_firmware_3;
9457 rtl_fw->fw_name = FIRMWARE_8153B_2;
9458 rtl_fw->pre_fw = r8153b_pre_firmware_1;
9459 rtl_fw->post_fw = r8153b_post_firmware_1;
9462 rtl_fw->fw_name = FIRMWARE_8156A_2;
9463 rtl_fw->post_fw = r8156a_post_firmware_1;
9467 rtl_fw->fw_name = FIRMWARE_8156B_2;
9470 rtl_fw->fw_name = FIRMWARE_8153C_1;
9471 rtl_fw->pre_fw = r8153b_pre_firmware_1;
9472 rtl_fw->post_fw = r8153c_post_firmware_1;
9481 static u8 __rtl_get_hw_ver(struct usb_device *udev)
9488 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
9492 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
9493 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
9494 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
9496 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
9502 version = RTL_VER_01;
9505 version = RTL_VER_02;
9508 version = RTL_VER_03;
9511 version = RTL_VER_04;
9514 version = RTL_VER_05;
9517 version = RTL_VER_06;
9520 version = RTL_VER_07;
9523 version = RTL_VER_08;
9526 version = RTL_VER_09;
9529 version = RTL_TEST_01;
9532 version = RTL_VER_10;
9535 version = RTL_VER_11;
9538 version = RTL_VER_12;
9541 version = RTL_VER_13;
9544 version = RTL_VER_14;
9547 version = RTL_VER_15;
9550 version = RTL_VER_UNKNOWN;
9551 dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data);
9558 u8 rtl8152_get_version(struct usb_interface *intf)
9562 version = __rtl_get_hw_ver(interface_to_usbdev(intf));
9564 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
9568 EXPORT_SYMBOL_GPL(rtl8152_get_version);
9570 static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev)
9572 int parent_vendor_id = le16_to_cpu(udev->parent->descriptor.idVendor);
9573 int product_id = le16_to_cpu(udev->descriptor.idProduct);
9574 int vendor_id = le16_to_cpu(udev->descriptor.idVendor);
9576 if (vendor_id == VENDOR_ID_LENOVO) {
9577 switch (product_id) {
9578 case DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB:
9579 case DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK:
9580 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
9581 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
9582 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3:
9583 case DEVICE_ID_THINKPAD_USB_C_DONGLE:
9586 } else if (vendor_id == VENDOR_ID_REALTEK && parent_vendor_id == VENDOR_ID_LENOVO) {
9587 switch (product_id) {
9595 static int rtl8152_probe(struct usb_interface *intf,
9596 const struct usb_device_id *id)
9598 struct usb_device *udev = interface_to_usbdev(intf);
9600 struct net_device *netdev;
9604 if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC)
9607 if (!rtl_check_vendor_ok(intf))
9610 version = rtl8152_get_version(intf);
9611 if (version == RTL_VER_UNKNOWN)
9614 usb_reset_device(udev);
9615 netdev = alloc_etherdev(sizeof(struct r8152));
9617 dev_err(&intf->dev, "Out of memory\n");
9621 SET_NETDEV_DEV(netdev, &intf->dev);
9622 tp = netdev_priv(netdev);
9623 tp->msg_enable = 0x7FFF;
9626 tp->netdev = netdev;
9628 tp->version = version;
9630 tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0);
9631 tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0);
9632 tp->pipe_in = usb_rcvbulkpipe(udev, 1);
9633 tp->pipe_out = usb_sndbulkpipe(udev, 2);
9634 tp->pipe_intr = usb_rcvintpipe(udev, 3);
9640 tp->mii.supports_gmii = 0;
9643 tp->mii.supports_gmii = 1;
9647 ret = rtl_ops_init(tp);
9653 mutex_init(&tp->control);
9654 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
9655 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
9656 tasklet_setup(&tp->tx_tl, bottom_half);
9657 tasklet_disable(&tp->tx_tl);
9659 netdev->netdev_ops = &rtl8152_netdev_ops;
9660 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
9662 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9663 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
9664 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
9665 NETIF_F_HW_VLAN_CTAG_TX;
9666 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9667 NETIF_F_TSO | NETIF_F_FRAGLIST |
9668 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
9669 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
9670 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
9671 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
9672 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
9674 if (tp->version == RTL_VER_01) {
9675 netdev->features &= ~NETIF_F_RXCSUM;
9676 netdev->hw_features &= ~NETIF_F_RXCSUM;
9679 tp->lenovo_macpassthru = rtl8152_supports_lenovo_macpassthru(udev);
9681 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
9682 (!strcmp(udev->serial, "000001000000") ||
9683 !strcmp(udev->serial, "000002000000"))) {
9684 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
9685 tp->dell_tb_rx_agg_bug = 1;
9688 netdev->ethtool_ops = &ops;
9689 netif_set_tso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
9691 /* MTU range: 68 - 1500 or 9194 */
9692 netdev->min_mtu = ETH_MIN_MTU;
9693 switch (tp->version) {
9701 netdev->max_mtu = size_to_mtu(9 * 1024);
9705 netdev->max_mtu = size_to_mtu(15 * 1024);
9710 netdev->max_mtu = size_to_mtu(16 * 1024);
9716 netdev->max_mtu = ETH_DATA_LEN;
9720 tp->mii.dev = netdev;
9721 tp->mii.mdio_read = read_mii_word;
9722 tp->mii.mdio_write = write_mii_word;
9723 tp->mii.phy_id_mask = 0x3f;
9724 tp->mii.reg_num_mask = 0x1f;
9725 tp->mii.phy_id = R8152_PHY_ID;
9727 tp->autoneg = AUTONEG_ENABLE;
9728 tp->speed = SPEED_100;
9729 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
9730 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
9731 if (tp->mii.supports_gmii) {
9732 if (tp->support_2500full &&
9733 tp->udev->speed >= USB_SPEED_SUPER) {
9734 tp->speed = SPEED_2500;
9735 tp->advertising |= RTL_ADVERTISED_2500_FULL;
9737 tp->speed = SPEED_1000;
9739 tp->advertising |= RTL_ADVERTISED_1000_FULL;
9741 tp->duplex = DUPLEX_FULL;
9743 tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
9744 tp->rx_pending = 10 * RTL8152_MAX_RX;
9746 intf->needs_remote_wakeup = 1;
9748 if (!rtl_can_wakeup(tp))
9749 __rtl_set_wol(tp, 0);
9751 tp->saved_wolopts = __rtl_get_wol(tp);
9753 tp->rtl_ops.init(tp);
9754 #if IS_BUILTIN(CONFIG_USB_RTL8152)
9755 /* Retry in case request_firmware() is not ready yet. */
9756 tp->rtl_fw.retry = true;
9758 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
9759 set_ethernet_addr(tp, false);
9761 usb_set_intfdata(intf, tp);
9763 netif_napi_add(netdev, &tp->napi, r8152_poll);
9765 ret = register_netdev(netdev);
9767 dev_err(&intf->dev, "couldn't register the device\n");
9771 if (tp->saved_wolopts)
9772 device_set_wakeup_enable(&udev->dev, true);
9774 device_set_wakeup_enable(&udev->dev, false);
9776 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
9781 tasklet_kill(&tp->tx_tl);
9782 usb_set_intfdata(intf, NULL);
9784 free_netdev(netdev);
9788 static void rtl8152_disconnect(struct usb_interface *intf)
9790 struct r8152 *tp = usb_get_intfdata(intf);
9792 usb_set_intfdata(intf, NULL);
9796 unregister_netdev(tp->netdev);
9797 tasklet_kill(&tp->tx_tl);
9798 cancel_delayed_work_sync(&tp->hw_phy_work);
9799 if (tp->rtl_ops.unload)
9800 tp->rtl_ops.unload(tp);
9801 rtl8152_release_firmware(tp);
9802 free_netdev(tp->netdev);
9806 /* table of devices that work with this driver */
9807 static const struct usb_device_id rtl8152_table[] = {
9809 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8050) },
9810 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8053) },
9811 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8152) },
9812 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) },
9813 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) },
9814 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) },
9817 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) },
9818 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6) },
9819 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927) },
9820 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e) },
9821 { USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101) },
9822 { USB_DEVICE(VENDOR_ID_LENOVO, 0x304f) },
9823 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3054) },
9824 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3062) },
9825 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3069) },
9826 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3082) },
9827 { USB_DEVICE(VENDOR_ID_LENOVO, 0x7205) },
9828 { USB_DEVICE(VENDOR_ID_LENOVO, 0x720c) },
9829 { USB_DEVICE(VENDOR_ID_LENOVO, 0x7214) },
9830 { USB_DEVICE(VENDOR_ID_LENOVO, 0x721e) },
9831 { USB_DEVICE(VENDOR_ID_LENOVO, 0xa387) },
9832 { USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) },
9833 { USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff) },
9834 { USB_DEVICE(VENDOR_ID_TPLINK, 0x0601) },
9835 { USB_DEVICE(VENDOR_ID_DLINK, 0xb301) },
9839 MODULE_DEVICE_TABLE(usb, rtl8152_table);
9841 static struct usb_driver rtl8152_driver = {
9843 .id_table = rtl8152_table,
9844 .probe = rtl8152_probe,
9845 .disconnect = rtl8152_disconnect,
9846 .suspend = rtl8152_suspend,
9847 .resume = rtl8152_resume,
9848 .reset_resume = rtl8152_reset_resume,
9849 .pre_reset = rtl8152_pre_reset,
9850 .post_reset = rtl8152_post_reset,
9851 .supports_autosuspend = 1,
9852 .disable_hub_initiated_lpm = 1,
9855 static int rtl8152_cfgselector_probe(struct usb_device *udev)
9857 struct usb_host_config *c;
9860 /* Switch the device to vendor mode, if and only if the vendor mode
9861 * driver supports it.
9863 if (__rtl_get_hw_ver(udev) == RTL_VER_UNKNOWN)
9866 /* The vendor mode is not always config #1, so to find it out. */
9868 num_configs = udev->descriptor.bNumConfigurations;
9869 for (i = 0; i < num_configs; (i++, c++)) {
9870 struct usb_interface_descriptor *desc = NULL;
9872 if (!c->desc.bNumInterfaces)
9874 desc = &c->intf_cache[0]->altsetting->desc;
9875 if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC)
9879 if (i == num_configs)
9882 if (usb_set_configuration(udev, c->desc.bConfigurationValue)) {
9883 dev_err(&udev->dev, "Failed to set configuration %d\n",
9884 c->desc.bConfigurationValue);
9891 static struct usb_device_driver rtl8152_cfgselector_driver = {
9892 .name = MODULENAME "-cfgselector",
9893 .probe = rtl8152_cfgselector_probe,
9894 .id_table = rtl8152_table,
9895 .generic_subclass = 1,
9896 .supports_autosuspend = 1,
9899 static int __init rtl8152_driver_init(void)
9903 ret = usb_register_device_driver(&rtl8152_cfgselector_driver, THIS_MODULE);
9906 return usb_register(&rtl8152_driver);
9909 static void __exit rtl8152_driver_exit(void)
9911 usb_deregister(&rtl8152_driver);
9912 usb_deregister_device_driver(&rtl8152_cfgselector_driver);
9915 module_init(rtl8152_driver_init);
9916 module_exit(rtl8152_driver_exit);
9918 MODULE_AUTHOR(DRIVER_AUTHOR);
9919 MODULE_DESCRIPTION(DRIVER_DESC);
9920 MODULE_LICENSE("GPL");
9921 MODULE_VERSION(DRIVER_VERSION);