1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale Three Speed Ethernet Controller driver
5 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
6 * (C) Copyright 2003, Motorola, Inc.
18 #include <linux/bitops.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <asm/processor.h>
25 /* Default initializations for TSEC controllers. */
27 static struct tsec_info_struct tsec_info[] = {
29 STD_TSEC_INFO(1), /* TSEC1 */
32 STD_TSEC_INFO(2), /* TSEC2 */
34 #ifdef CONFIG_MPC85XX_FEC
36 .regs = TSEC_GET_REGS(2, 0x2000),
37 .devname = CONFIG_MPC85XX_FEC_NAME,
38 .phyaddr = FEC_PHY_ADDR,
40 .mii_devname = DEFAULT_MII_NAME
44 STD_TSEC_INFO(3), /* TSEC3 */
47 STD_TSEC_INFO(4), /* TSEC4 */
50 #endif /* CONFIG_DM_ETH */
52 #define TBIANA_SETTINGS ( \
53 TBIANA_ASYMMETRIC_PAUSE \
54 | TBIANA_SYMMETRIC_PAUSE \
55 | TBIANA_FULL_DUPLEX \
58 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
59 #ifndef CONFIG_TSEC_TBICR_SETTINGS
60 #define CONFIG_TSEC_TBICR_SETTINGS ( \
66 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
68 /* Configure the TBI for SGMII operation */
69 static void tsec_configure_serdes(struct tsec_private *priv)
72 * Access TBI PHY registers at given TSEC register offset as opposed
73 * to the register offset used for external PHY accesses
75 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
76 0, TBI_ANA, TBIANA_SETTINGS);
77 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
78 0, TBI_TBICON, TBICON_CLK_SELECT);
79 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
80 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
83 /* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
84 * and this is the ethernet-crc method needed for TSEC -- and perhaps
85 * some other adapter -- hash tables
87 #define CRCPOLY_LE 0xedb88320
88 static u32 ether_crc(size_t len, unsigned char const *p)
96 for (i = 0; i < 8; i++)
97 crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
99 /* an reverse the bits, cuz of way they arrive -- last-first */
100 crc = (crc >> 16) | (crc << 16);
101 crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
102 crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
103 crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
104 crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
108 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
110 /* Set the appropriate hash bit for the given addr */
113 * The algorithm works like so:
114 * 1) Take the Destination Address (ie the multicast address), and
115 * do a CRC on it (little endian), and reverse the bits of the
117 * 2) Use the 8 most significant bits as a hash into a 256-entry
118 * table. The table is controlled through 8 32-bit registers:
119 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
120 * 255. This means that the 3 most significant bits in the
121 * hash index which gaddr register to use, and the 5 other bits
122 * indicate which bit (assuming an IBM numbering scheme, which
123 * for PowerPC (tm) is usually the case) in the register holds
126 #ifndef CONFIG_DM_ETH
127 static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac,
130 static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
133 struct tsec_private *priv = (struct tsec_private *)dev->priv;
134 struct tsec __iomem *regs = priv->regs;
136 u8 whichbit, whichreg;
138 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
139 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
140 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
142 value = BIT(31 - whichbit);
145 setbits_be32(®s->hash.gaddr0 + whichreg, value);
147 clrbits_be32(®s->hash.gaddr0 + whichreg, value);
153 * Initialized required registers to appropriate values, zeroing
154 * those we don't care about (unless zero is bad, in which case,
155 * choose a more appropriate value)
157 static void init_registers(struct tsec __iomem *regs)
160 out_be32(®s->ievent, IEVENT_INIT_CLEAR);
162 out_be32(®s->imask, IMASK_INIT_CLEAR);
164 out_be32(®s->hash.iaddr0, 0);
165 out_be32(®s->hash.iaddr1, 0);
166 out_be32(®s->hash.iaddr2, 0);
167 out_be32(®s->hash.iaddr3, 0);
168 out_be32(®s->hash.iaddr4, 0);
169 out_be32(®s->hash.iaddr5, 0);
170 out_be32(®s->hash.iaddr6, 0);
171 out_be32(®s->hash.iaddr7, 0);
173 out_be32(®s->hash.gaddr0, 0);
174 out_be32(®s->hash.gaddr1, 0);
175 out_be32(®s->hash.gaddr2, 0);
176 out_be32(®s->hash.gaddr3, 0);
177 out_be32(®s->hash.gaddr4, 0);
178 out_be32(®s->hash.gaddr5, 0);
179 out_be32(®s->hash.gaddr6, 0);
180 out_be32(®s->hash.gaddr7, 0);
182 out_be32(®s->rctrl, 0x00000000);
184 /* Init RMON mib registers */
185 memset((void *)®s->rmon, 0, sizeof(regs->rmon));
187 out_be32(®s->rmon.cam1, 0xffffffff);
188 out_be32(®s->rmon.cam2, 0xffffffff);
190 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
192 out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
194 out_be32(®s->attr, ATTR_INIT_SETTINGS);
195 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
199 * Configure maccfg2 based on negotiated speed and duplex
200 * reported by PHY handling code
202 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
204 struct tsec __iomem *regs = priv->regs;
208 printf("%s: No link.\n", phydev->dev->name);
212 /* clear all bits relative with interface mode */
213 ecntrl = in_be32(®s->ecntrl);
214 ecntrl &= ~ECNTRL_R100;
216 maccfg2 = in_be32(®s->maccfg2);
217 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
220 maccfg2 |= MACCFG2_FULL_DUPLEX;
222 switch (phydev->speed) {
224 maccfg2 |= MACCFG2_GMII;
228 maccfg2 |= MACCFG2_MII;
231 * Set R100 bit in all modes although
232 * it is only used in RGMII mode
234 if (phydev->speed == 100)
235 ecntrl |= ECNTRL_R100;
238 printf("%s: Speed was bad\n", phydev->dev->name);
242 out_be32(®s->ecntrl, ecntrl);
243 out_be32(®s->maccfg2, maccfg2);
245 printf("Speed: %d, %s duplex%s\n", phydev->speed,
246 (phydev->duplex) ? "full" : "half",
247 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
251 * This returns the status bits of the device. The return value
252 * is never checked, and this is what the 8260 driver did, so we
253 * do the same. Presumably, this would be zero if there were no
256 #ifndef CONFIG_DM_ETH
257 static int tsec_send(struct eth_device *dev, void *packet, int length)
259 static int tsec_send(struct udevice *dev, void *packet, int length)
262 struct tsec_private *priv = (struct tsec_private *)dev->priv;
263 struct tsec __iomem *regs = priv->regs;
268 /* Find an empty buffer descriptor */
270 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
272 if (i >= TOUT_LOOP) {
273 printf("%s: tsec: tx buffers full\n", dev->name);
278 out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
279 out_be16(&priv->txbd[priv->tx_idx].length, length);
280 status = in_be16(&priv->txbd[priv->tx_idx].status);
281 out_be16(&priv->txbd[priv->tx_idx].status, status |
282 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
284 /* Tell the DMA to go */
285 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
287 /* Wait for buffer to be transmitted */
289 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
291 if (i >= TOUT_LOOP) {
292 printf("%s: tsec: tx error\n", dev->name);
297 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
298 result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
303 #ifndef CONFIG_DM_ETH
304 static int tsec_recv(struct eth_device *dev)
306 struct tsec_private *priv = (struct tsec_private *)dev->priv;
307 struct tsec __iomem *regs = priv->regs;
309 while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
310 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
311 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
312 uchar *packet = net_rx_packets[priv->rx_idx];
314 /* Send the packet up if there were no errors */
315 if (!(status & RXBD_STATS))
316 net_process_received_packet(packet, length - 4);
318 printf("Got error %x\n", (status & RXBD_STATS));
320 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
323 /* Set the wrap bit if this is the last element in the list */
324 if ((priv->rx_idx + 1) == PKTBUFSRX)
326 out_be16(&priv->rxbd[priv->rx_idx].status, status);
328 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
331 if (in_be32(®s->ievent) & IEVENT_BSY) {
332 out_be32(®s->ievent, IEVENT_BSY);
333 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
339 static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
341 struct tsec_private *priv = (struct tsec_private *)dev->priv;
342 struct tsec __iomem *regs = priv->regs;
345 if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
346 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
347 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
350 /* Send the packet up if there were no errors */
351 if (!(status & RXBD_STATS)) {
352 buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
353 *packetp = (uchar *)buf;
356 printf("Got error %x\n", (status & RXBD_STATS));
360 if (in_be32(®s->ievent) & IEVENT_BSY) {
361 out_be32(®s->ievent, IEVENT_BSY);
362 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
368 static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
370 struct tsec_private *priv = (struct tsec_private *)dev->priv;
373 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
376 /* Set the wrap bit if this is the last element in the list */
377 if ((priv->rx_idx + 1) == PKTBUFSRX)
379 out_be16(&priv->rxbd[priv->rx_idx].status, status);
381 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
387 /* Stop the interface */
388 #ifndef CONFIG_DM_ETH
389 static void tsec_halt(struct eth_device *dev)
391 static void tsec_halt(struct udevice *dev)
394 struct tsec_private *priv = (struct tsec_private *)dev->priv;
395 struct tsec __iomem *regs = priv->regs;
397 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
398 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
400 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
401 != (IEVENT_GRSC | IEVENT_GTSC))
404 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
406 /* Shut down the PHY, as needed */
407 phy_shutdown(priv->phydev);
410 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
412 * When MACCFG1[Rx_EN] is enabled during system boot as part
413 * of the eTSEC port initialization sequence,
414 * the eTSEC Rx logic may not be properly initialized.
416 void redundant_init(struct tsec_private *priv)
418 struct tsec __iomem *regs = priv->regs;
421 static const u8 pkt[] = {
422 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
423 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
424 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
425 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
426 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
427 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
428 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
429 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
430 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
431 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
432 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
433 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
434 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
437 /* Enable promiscuous mode */
438 setbits_be32(®s->rctrl, 0x8);
439 /* Enable loopback mode */
440 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
441 /* Enable transmit and receive */
442 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
444 /* Tell the DMA it is clear to go */
445 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
446 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
447 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
448 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
453 tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
455 /* Wait for buffer to be received */
457 in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
459 if (t >= 10 * TOUT_LOOP) {
460 printf("%s: tsec: rx error\n", priv->dev->name);
465 if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
468 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
470 if ((priv->rx_idx + 1) == PKTBUFSRX)
472 out_be16(&priv->rxbd[priv->rx_idx].status, status);
473 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
475 if (in_be32(®s->ievent) & IEVENT_BSY) {
476 out_be32(®s->ievent, IEVENT_BSY);
477 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
480 printf("loopback recv packet error!\n");
481 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
483 setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
485 } while ((count++ < 4) && (fail == 1));
488 panic("eTSEC init fail!\n");
489 /* Disable promiscuous mode */
490 clrbits_be32(®s->rctrl, 0x8);
491 /* Disable loopback mode */
492 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
497 * Set up the buffers and their descriptors, and bring up the
500 static void startup_tsec(struct tsec_private *priv)
502 struct tsec __iomem *regs = priv->regs;
506 /* reset the indices to zero */
509 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
513 /* Point to the buffer descriptors */
514 out_be32(®s->tbase, (u32)&priv->txbd[0]);
515 out_be32(®s->rbase, (u32)&priv->rxbd[0]);
517 /* Initialize the Rx Buffer descriptors */
518 for (i = 0; i < PKTBUFSRX; i++) {
519 out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
520 out_be16(&priv->rxbd[i].length, 0);
521 out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
523 status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
524 out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
526 /* Initialize the TX Buffer Descriptors */
527 for (i = 0; i < TX_BUF_CNT; i++) {
528 out_be16(&priv->txbd[i].status, 0);
529 out_be16(&priv->txbd[i].length, 0);
530 out_be32(&priv->txbd[i].bufptr, 0);
532 status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
533 out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
535 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
537 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
538 redundant_init(priv);
540 /* Enable Transmit and Receive */
541 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
543 /* Tell the DMA it is clear to go */
544 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
545 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
546 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
547 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
551 * Initializes data structures and registers for the controller,
552 * and brings the interface up. Returns the link status, meaning
553 * that it returns success if the link is up, failure otherwise.
554 * This allows U-Boot to find the first active controller.
556 #ifndef CONFIG_DM_ETH
557 static int tsec_init(struct eth_device *dev, bd_t *bd)
559 static int tsec_init(struct udevice *dev)
562 struct tsec_private *priv = (struct tsec_private *)dev->priv;
564 struct eth_pdata *pdata = dev_get_platdata(dev);
566 struct eth_device *pdata = dev;
568 struct tsec __iomem *regs = priv->regs;
572 /* Make sure the controller is stopped */
575 /* Init MACCFG2. Defaults to GMII */
576 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
579 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
582 * Copy the station address into the address registers.
583 * For a station address of 0x12345678ABCD in transmission
584 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
585 * MACnADDR2 is set to 0x34120000.
587 tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
588 (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
590 out_be32(®s->macstnaddr1, tempval);
592 tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
594 out_be32(®s->macstnaddr2, tempval);
596 /* Clear out (for the most part) the other registers */
597 init_registers(regs);
599 /* Ready the device for tx/rx */
602 /* Start up the PHY */
603 ret = phy_startup(priv->phydev);
605 printf("Could not initialize PHY %s\n",
606 priv->phydev->dev->name);
610 adjust_link(priv, priv->phydev);
612 /* If there's no link, fail */
613 return priv->phydev->link ? 0 : -1;
616 static phy_interface_t tsec_get_interface(struct tsec_private *priv)
618 struct tsec __iomem *regs = priv->regs;
621 ecntrl = in_be32(®s->ecntrl);
623 if (ecntrl & ECNTRL_SGMII_MODE)
624 return PHY_INTERFACE_MODE_SGMII;
626 if (ecntrl & ECNTRL_TBI_MODE) {
627 if (ecntrl & ECNTRL_REDUCED_MODE)
628 return PHY_INTERFACE_MODE_RTBI;
630 return PHY_INTERFACE_MODE_TBI;
633 if (ecntrl & ECNTRL_REDUCED_MODE) {
634 phy_interface_t interface;
636 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
637 return PHY_INTERFACE_MODE_RMII;
639 interface = priv->interface;
642 * This isn't autodetected, so it must
643 * be set by the platform code.
645 if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
646 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
647 interface == PHY_INTERFACE_MODE_RGMII_RXID)
650 return PHY_INTERFACE_MODE_RGMII;
653 if (priv->flags & TSEC_GIGABIT)
654 return PHY_INTERFACE_MODE_GMII;
656 return PHY_INTERFACE_MODE_MII;
660 * Discover which PHY is attached to the device, and configure it
661 * properly. If the PHY is not recognized, then return 0
662 * (failure). Otherwise, return 1
664 static int init_phy(struct tsec_private *priv)
666 struct phy_device *phydev;
667 struct tsec __iomem *regs = priv->regs;
668 u32 supported = (SUPPORTED_10baseT_Half |
669 SUPPORTED_10baseT_Full |
670 SUPPORTED_100baseT_Half |
671 SUPPORTED_100baseT_Full);
673 if (priv->flags & TSEC_GIGABIT)
674 supported |= SUPPORTED_1000baseT_Full;
676 /* Assign a Physical address to the TBI */
677 out_be32(®s->tbipa, priv->tbiaddr);
679 priv->interface = tsec_get_interface(priv);
681 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
682 tsec_configure_serdes(priv);
684 phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
689 phydev->supported &= supported;
690 phydev->advertising = phydev->supported;
692 priv->phydev = phydev;
699 #ifndef CONFIG_DM_ETH
701 * Initialize device structure. Returns success if PHY
702 * initialization succeeded (i.e. if it recognizes the PHY)
704 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
706 struct tsec_private *priv;
707 struct eth_device *dev;
710 dev = (struct eth_device *)malloc(sizeof(*dev));
715 memset(dev, 0, sizeof(*dev));
717 priv = (struct tsec_private *)malloc(sizeof(*priv));
724 priv->regs = tsec_info->regs;
725 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
727 priv->phyaddr = tsec_info->phyaddr;
728 priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
729 priv->flags = tsec_info->flags;
731 strcpy(dev->name, tsec_info->devname);
732 priv->interface = tsec_info->interface;
733 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
737 dev->init = tsec_init;
738 dev->halt = tsec_halt;
739 dev->send = tsec_send;
740 dev->recv = tsec_recv;
741 dev->mcast = tsec_mcast_addr;
743 /* Tell U-Boot to get the addr from the env */
744 for (i = 0; i < 6; i++)
745 dev->enetaddr[i] = 0;
750 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
751 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
752 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
754 /* Try to initialize PHY here, and return */
755 return init_phy(priv);
759 * Initialize all the TSEC devices
761 * Returns the number of TSEC devices that were initialized
763 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
768 for (i = 0; i < num; i++) {
769 int ret = tsec_initialize(bis, &tsecs[i]);
778 int tsec_standard_init(bd_t *bis)
780 struct fsl_pq_mdio_info info;
782 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
783 info.name = DEFAULT_MII_NAME;
785 fsl_pq_mdio_init(bis, &info);
787 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
789 #else /* CONFIG_DM_ETH */
790 int tsec_probe(struct udevice *dev)
792 struct eth_pdata *pdata = dev_get_platdata(dev);
793 struct tsec_private *priv = dev_get_priv(dev);
794 struct ofnode_phandle_args phandle_args;
795 u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
796 struct fsl_pq_mdio_info mdio_info;
797 const char *phy_mode;
802 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
803 priv->regs = (struct tsec *)pdata->iobase;
805 if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
807 printf("phy-handle does not exist under tsec %s\n", dev->name);
810 int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
815 parent = ofnode_get_parent(phandle_args.node);
816 if (!ofnode_valid(parent)) {
817 printf("No parent node for PHY?\n");
821 reg = ofnode_get_addr_index(parent, 0);
822 priv->phyregs_sgmii = (struct tsec_mii_mng *)
823 (reg + TSEC_MDIO_REGS_OFFSET);
825 ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
828 ofnode_read_u32(phandle_args.node, "reg", &tbiaddr);
830 priv->tbiaddr = tbiaddr;
832 phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
834 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
835 if (pdata->phy_interface == -1) {
836 printf("Invalid PHY interface '%s'\n", phy_mode);
839 priv->interface = pdata->phy_interface;
841 /* Initialize flags */
842 priv->flags = TSEC_GIGABIT;
843 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
844 priv->flags |= TSEC_SGMII;
846 mdio_info.regs = priv->phyregs_sgmii;
847 mdio_info.name = (char *)dev->name;
848 ret = fsl_pq_mdio_init(NULL, &mdio_info);
853 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
854 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
855 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
858 priv->bus = miiphy_get_dev_by_name(dev->name);
860 /* Try to initialize PHY here, and return */
861 return !init_phy(priv);
864 int tsec_remove(struct udevice *dev)
866 struct tsec_private *priv = dev->priv;
869 mdio_unregister(priv->bus);
870 mdio_free(priv->bus);
875 static const struct eth_ops tsec_ops = {
879 .free_pkt = tsec_free_pkt,
881 .mcast = tsec_mcast_addr,
884 static const struct udevice_id tsec_ids[] = {
885 { .compatible = "fsl,etsec2" },
889 U_BOOT_DRIVER(eth_tsec) = {
892 .of_match = tsec_ids,
894 .remove = tsec_remove,
896 .priv_auto_alloc_size = sizeof(struct tsec_private),
897 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
898 .flags = DM_FLAG_ALLOC_PRIV_DMA,
900 #endif /* CONFIG_DM_ETH */