drivers/net/tsec.c

   1 /*
   2  * Freescale Three Speed Ethernet Controller driver
   3  *
   4  * This software may be used and distributed according to the
   5  * terms of the GNU Public License, Version 2, incorporated
   6  * herein by reference.
   7  *
   8  * Copyright 2004, 2007 Freescale Semiconductor, Inc.
   9  * (C) Copyright 2003, Motorola, Inc.
  10  * author Andy Fleming
  11  *
  12  */
  13
  14 #include <config.h>
  15 #include <common.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <command.h>
  19 #include <tsec.h>
  20
  21 #include "miiphy.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define TX_BUF_CNT              2
  26
  27 static uint rxIdx;              /* index of the current RX buffer */
  28 static uint txIdx;              /* index of the current TX buffer */
  29
  30 typedef volatile struct rtxbd {
  31         txbd8_t txbd[TX_BUF_CNT];
  32         rxbd8_t rxbd[PKTBUFSRX];
  33 } RTXBD;
  34
  35 #define MAXCONTROLLERS  (8)
  36
  37 static int relocated = 0;
  38
  39 static struct tsec_private *privlist[MAXCONTROLLERS];
  40 static int num_tsecs = 0;
  41
  42 #ifdef __GNUC__
  43 static RTXBD rtx __attribute__ ((aligned(8)));
  44 #else
  45 #error "rtx must be 64-bit aligned"
  46 #endif
  47
  48 static int tsec_send(struct eth_device *dev,
  49                      volatile void *packet, int length);
  50 static int tsec_recv(struct eth_device *dev);
  51 static int tsec_init(struct eth_device *dev, bd_t * bd);
  52 static void tsec_halt(struct eth_device *dev);
  53 static void init_registers(volatile tsec_t * regs);
  54 static void startup_tsec(struct eth_device *dev);
  55 static int init_phy(struct eth_device *dev);
  56 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
  57 uint read_phy_reg(struct tsec_private *priv, uint regnum);
  58 struct phy_info *get_phy_info(struct eth_device *dev);
  59 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
  60 static void adjust_link(struct eth_device *dev);
  61 static void relocate_cmds(void);
  62 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
  63         && !defined(BITBANGMII)
  64 static int tsec_miiphy_write(char *devname, unsigned char addr,
  65                              unsigned char reg, unsigned short value);
  66 static int tsec_miiphy_read(char *devname, unsigned char addr,
  67                             unsigned char reg, unsigned short *value);
  68 #endif
  69 #ifdef CONFIG_MCAST_TFTP
  70 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
  71 #endif
  72
  73 /* Default initializations for TSEC controllers. */
  74
  75 static struct tsec_info_struct tsec_info[] = {
  76 #ifdef CONFIG_TSEC1
  77         STD_TSEC_INFO(1),       /* TSEC1 */
  78 #endif
  79 #ifdef CONFIG_TSEC2
  80         STD_TSEC_INFO(2),       /* TSEC2 */
  81 #endif
  82 #ifdef CONFIG_MPC85XX_FEC
  83         {
  84                 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
  85                 .miiregs = (tsec_t *)(TSEC_BASE_ADDR),
  86                 .devname = CONFIG_MPC85XX_FEC_NAME,
  87                 .phyaddr = FEC_PHY_ADDR,
  88                 .flags = FEC_FLAGS
  89         },                      /* FEC */
  90 #endif
  91 #ifdef CONFIG_TSEC3
  92         STD_TSEC_INFO(3),       /* TSEC3 */
  93 #endif
  94 #ifdef CONFIG_TSEC4
  95         STD_TSEC_INFO(4),       /* TSEC4 */
  96 #endif
  97 };
  98
  99 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
 100 {
 101         int i;
 102
 103         for (i = 0; i < num; i++)
 104                 tsec_initialize(bis, &tsecs[i]);
 105
 106         return 0;
 107 }
 108
 109 int tsec_standard_init(bd_t *bis)
 110 {
 111         return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
 112 }
 113
 114 /* Initialize device structure. Returns success if PHY
 115  * initialization succeeded (i.e. if it recognizes the PHY)
 116  */
 117 int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info)
 118 {
 119         struct eth_device *dev;
 120         int i;
 121         struct tsec_private *priv;
 122
 123         dev = (struct eth_device *)malloc(sizeof *dev);
 124
 125         if (NULL == dev)
 126                 return 0;
 127
 128         memset(dev, 0, sizeof *dev);
 129
 130         priv = (struct tsec_private *)malloc(sizeof(*priv));
 131
 132         if (NULL == priv)
 133                 return 0;
 134
 135         privlist[num_tsecs++] = priv;
 136         priv->regs = tsec_info->regs;
 137         priv->phyregs = tsec_info->miiregs;
 138
 139         priv->phyaddr = tsec_info->phyaddr;
 140         priv->flags = tsec_info->flags;
 141
 142         sprintf(dev->name, tsec_info->devname);
 143         dev->iobase = 0;
 144         dev->priv = priv;
 145         dev->init = tsec_init;
 146         dev->halt = tsec_halt;
 147         dev->send = tsec_send;
 148         dev->recv = tsec_recv;
 149 #ifdef CONFIG_MCAST_TFTP
 150         dev->mcast = tsec_mcast_addr;
 151 #endif
 152
 153         /* Tell u-boot to get the addr from the env */
 154         for (i = 0; i < 6; i++)
 155                 dev->enetaddr[i] = 0;
 156
 157         eth_register(dev);
 158
 159         /* Reset the MAC */
 160         priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
 161         udelay(2);  /* Soft Reset must be asserted for 3 TX clocks */
 162         priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
 163
 164 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
 165         && !defined(BITBANGMII)
 166         miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
 167 #endif
 168
 169         /* Try to initialize PHY here, and return */
 170         return init_phy(dev);
 171 }
 172
 173 /* Initializes data structures and registers for the controller,
 174  * and brings the interface up.  Returns the link status, meaning
 175  * that it returns success if the link is up, failure otherwise.
 176  * This allows u-boot to find the first active controller.
 177  */
 178 int tsec_init(struct eth_device *dev, bd_t * bd)
 179 {
 180         uint tempval;
 181         char tmpbuf[MAC_ADDR_LEN];
 182         int i;
 183         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 184         volatile tsec_t *regs = priv->regs;
 185
 186         /* Make sure the controller is stopped */
 187         tsec_halt(dev);
 188
 189         /* Init MACCFG2.  Defaults to GMII */
 190         regs->maccfg2 = MACCFG2_INIT_SETTINGS;
 191
 192         /* Init ECNTRL */
 193         regs->ecntrl = ECNTRL_INIT_SETTINGS;
 194
 195         /* Copy the station address into the address registers.
 196          * Backwards, because little endian MACS are dumb */
 197         for (i = 0; i < MAC_ADDR_LEN; i++) {
 198                 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
 199         }
 200         regs->macstnaddr1 = *((uint *) (tmpbuf));
 201
 202         tempval = *((uint *) (tmpbuf + 4));
 203
 204         regs->macstnaddr2 = tempval;
 205
 206         /* reset the indices to zero */
 207         rxIdx = 0;
 208         txIdx = 0;
 209
 210         /* Clear out (for the most part) the other registers */
 211         init_registers(regs);
 212
 213         /* Ready the device for tx/rx */
 214         startup_tsec(dev);
 215
 216         /* If there's no link, fail */
 217         return (priv->link ? 0 : -1);
 218 }
 219
 220 /* Writes the given phy's reg with value, using the specified MDIO regs */
 221 static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr,
 222                 uint reg, uint value)
 223 {
 224         int timeout = 1000000;
 225
 226         phyregs->miimadd = (addr << 8) | reg;
 227         phyregs->miimcon = value;
 228         asm("sync");
 229
 230         timeout = 1000000;
 231         while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ;
 232 }
 233
 234
 235 /* Provide the default behavior of writing the PHY of this ethernet device */
 236 #define write_phy_reg(priv, regnum, value) tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value)
 237
 238 /* Reads register regnum on the device's PHY through the
 239  * specified registers.  It lowers and raises the read
 240  * command, and waits for the data to become valid (miimind
 241  * notvalid bit cleared), and the bus to cease activity (miimind
 242  * busy bit cleared), and then returns the value
 243  */
 244 uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum)
 245 {
 246         uint value;
 247
 248         /* Put the address of the phy, and the register
 249          * number into MIIMADD */
 250         phyregs->miimadd = (phyid << 8) | regnum;
 251
 252         /* Clear the command register, and wait */
 253         phyregs->miimcom = 0;
 254         asm("sync");
 255
 256         /* Initiate a read command, and wait */
 257         phyregs->miimcom = MIIM_READ_COMMAND;
 258         asm("sync");
 259
 260         /* Wait for the the indication that the read is done */
 261         while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
 262
 263         /* Grab the value read from the PHY */
 264         value = phyregs->miimstat;
 265
 266         return value;
 267 }
 268
 269 /* #define to provide old read_phy_reg functionality without duplicating code */
 270 #define read_phy_reg(priv,regnum) tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum)
 271
 272 #define TBIANA_SETTINGS ( \
 273                 TBIANA_ASYMMETRIC_PAUSE \
 274                 | TBIANA_SYMMETRIC_PAUSE \
 275                 | TBIANA_FULL_DUPLEX \
 276                 )
 277
 278 #define TBICR_SETTINGS ( \
 279                 TBICR_PHY_RESET \
 280                 | TBICR_ANEG_ENABLE \
 281                 | TBICR_FULL_DUPLEX \
 282                 | TBICR_SPEED1_SET \
 283                 )
 284 /* Configure the TBI for SGMII operation */
 285 static void tsec_configure_serdes(struct tsec_private *priv)
 286 {
 287         /* Access TBI PHY registers at given TSEC register offset as opposed to the
 288          * register offset used for external PHY accesses */
 289         tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA,
 290                         TBIANA_SETTINGS);
 291         tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON,
 292                         TBICON_CLK_SELECT);
 293         tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR,
 294                         TBICR_SETTINGS);
 295 }
 296
 297 /* Discover which PHY is attached to the device, and configure it
 298  * properly.  If the PHY is not recognized, then return 0
 299  * (failure).  Otherwise, return 1
 300  */
 301 static int init_phy(struct eth_device *dev)
 302 {
 303         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 304         struct phy_info *curphy;
 305         volatile tsec_t *phyregs = priv->phyregs;
 306         volatile tsec_t *regs = priv->regs;
 307
 308         /* Assign a Physical address to the TBI */
 309         regs->tbipa = CONFIG_SYS_TBIPA_VALUE;
 310         phyregs->tbipa = CONFIG_SYS_TBIPA_VALUE;
 311         asm("sync");
 312
 313         /* Reset MII (due to new addresses) */
 314         priv->phyregs->miimcfg = MIIMCFG_RESET;
 315         asm("sync");
 316         priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
 317         asm("sync");
 318         while (priv->phyregs->miimind & MIIMIND_BUSY) ;
 319
 320         if (0 == relocated)
 321                 relocate_cmds();
 322
 323         /* Get the cmd structure corresponding to the attached
 324          * PHY */
 325         curphy = get_phy_info(dev);
 326
 327         if (curphy == NULL) {
 328                 priv->phyinfo = NULL;
 329                 printf("%s: No PHY found\n", dev->name);
 330
 331                 return 0;
 332         }
 333
 334         if (regs->ecntrl & ECNTRL_SGMII_MODE)
 335                 tsec_configure_serdes(priv);
 336
 337         priv->phyinfo = curphy;
 338
 339         phy_run_commands(priv, priv->phyinfo->config);
 340
 341         return 1;
 342 }
 343
 344 /*
 345  * Returns which value to write to the control register.
 346  * For 10/100, the value is slightly different
 347  */
 348 uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
 349 {
 350         if (priv->flags & TSEC_GIGABIT)
 351                 return MIIM_CONTROL_INIT;
 352         else
 353                 return MIIM_CR_INIT;
 354 }
 355
 356 /* Parse the status register for link, and then do
 357  * auto-negotiation
 358  */
 359 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
 360 {
 361         /*
 362          * Wait if the link is up, and autonegotiation is in progress
 363          * (ie - we're capable and it's not done)
 364          */
 365         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 366         if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE)
 367             && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
 368                 int i = 0;
 369
 370                 puts("Waiting for PHY auto negotiation to complete");
 371                 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) {
 372                         /*
 373                          * Timeout reached ?
 374                          */
 375                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 376                                 puts(" TIMEOUT !\n");
 377                                 priv->link = 0;
 378                                 return 0;
 379                         }
 380
 381                         if ((i++ % 1000) == 0) {
 382                                 putc('.');
 383                         }
 384                         udelay(1000);   /* 1 ms */
 385                         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 386                 }
 387                 puts(" done\n");
 388                 priv->link = 1;
 389                 udelay(500000); /* another 500 ms (results in faster booting) */
 390         } else {
 391                 if (mii_reg & MIIM_STATUS_LINK)
 392                         priv->link = 1;
 393                 else
 394                         priv->link = 0;
 395         }
 396
 397         return 0;
 398 }
 399
 400 /* Generic function which updates the speed and duplex.  If
 401  * autonegotiation is enabled, it uses the AND of the link
 402  * partner's advertised capabilities and our advertised
 403  * capabilities.  If autonegotiation is disabled, we use the
 404  * appropriate bits in the control register.
 405  *
 406  * Stolen from Linux's mii.c and phy_device.c
 407  */
 408 uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
 409 {
 410         /* We're using autonegotiation */
 411         if (mii_reg & PHY_BMSR_AUTN_ABLE) {
 412                 uint lpa = 0;
 413                 uint gblpa = 0;
 414
 415                 /* Check for gigabit capability */
 416                 if (mii_reg & PHY_BMSR_EXT) {
 417                         /* We want a list of states supported by
 418                          * both PHYs in the link
 419                          */
 420                         gblpa = read_phy_reg(priv, PHY_1000BTSR);
 421                         gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
 422                 }
 423
 424                 /* Set the baseline so we only have to set them
 425                  * if they're different
 426                  */
 427                 priv->speed = 10;
 428                 priv->duplexity = 0;
 429
 430                 /* Check the gigabit fields */
 431                 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
 432                         priv->speed = 1000;
 433
 434                         if (gblpa & PHY_1000BTSR_1000FD)
 435                                 priv->duplexity = 1;
 436
 437                         /* We're done! */
 438                         return 0;
 439                 }
 440
 441                 lpa = read_phy_reg(priv, PHY_ANAR);
 442                 lpa &= read_phy_reg(priv, PHY_ANLPAR);
 443
 444                 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
 445                         priv->speed = 100;
 446
 447                         if (lpa & PHY_ANLPAR_TXFD)
 448                                 priv->duplexity = 1;
 449
 450                 } else if (lpa & PHY_ANLPAR_10FD)
 451                         priv->duplexity = 1;
 452         } else {
 453                 uint bmcr = read_phy_reg(priv, PHY_BMCR);
 454
 455                 priv->speed = 10;
 456                 priv->duplexity = 0;
 457
 458                 if (bmcr & PHY_BMCR_DPLX)
 459                         priv->duplexity = 1;
 460
 461                 if (bmcr & PHY_BMCR_1000_MBPS)
 462                         priv->speed = 1000;
 463                 else if (bmcr & PHY_BMCR_100_MBPS)
 464                         priv->speed = 100;
 465         }
 466
 467         return 0;
 468 }
 469
 470 /*
 471  * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
 472  * circumstances.  eg a gigabit TSEC connected to a gigabit switch with
 473  * a 4-wire ethernet cable.  Both ends advertise gigabit, but can't
 474  * link.  "Ethernet@Wirespeed" reduces advertised speed until link
 475  * can be achieved.
 476  */
 477 uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv)
 478 {
 479         return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010;
 480 }
 481
 482 /*
 483  * Parse the BCM54xx status register for speed and duplex information.
 484  * The linux sungem_phy has this information, but in a table format.
 485  */
 486 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
 487 {
 488
 489         switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){
 490
 491                 case 1:
 492                         printf("Enet starting in 10BT/HD\n");
 493                         priv->duplexity = 0;
 494                         priv->speed = 10;
 495                         break;
 496
 497                 case 2:
 498                         printf("Enet starting in 10BT/FD\n");
 499                         priv->duplexity = 1;
 500                         priv->speed = 10;
 501                         break;
 502
 503                 case 3:
 504                         printf("Enet starting in 100BT/HD\n");
 505                         priv->duplexity = 0;
 506                         priv->speed = 100;
 507                         break;
 508
 509                 case 5:
 510                         printf("Enet starting in 100BT/FD\n");
 511                         priv->duplexity = 1;
 512                         priv->speed = 100;
 513                         break;
 514
 515                 case 6:
 516                         printf("Enet starting in 1000BT/HD\n");
 517                         priv->duplexity = 0;
 518                         priv->speed = 1000;
 519                         break;
 520
 521                 case 7:
 522                         printf("Enet starting in 1000BT/FD\n");
 523                         priv->duplexity = 1;
 524                         priv->speed = 1000;
 525                         break;
 526
 527                 default:
 528                         printf("Auto-neg error, defaulting to 10BT/HD\n");
 529                         priv->duplexity = 0;
 530                         priv->speed = 10;
 531                         break;
 532         }
 533
 534         return 0;
 535
 536 }
 537 /* Parse the 88E1011's status register for speed and duplex
 538  * information
 539  */
 540 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
 541 {
 542         uint speed;
 543
 544         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 545
 546         if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
 547                 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
 548                 int i = 0;
 549
 550                 puts("Waiting for PHY realtime link");
 551                 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
 552                         /* Timeout reached ? */
 553                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 554                                 puts(" TIMEOUT !\n");
 555                                 priv->link = 0;
 556                                 break;
 557                         }
 558
 559                         if ((i++ % 1000) == 0) {
 560                                 putc('.');
 561                         }
 562                         udelay(1000);   /* 1 ms */
 563                         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 564                 }
 565                 puts(" done\n");
 566                 udelay(500000); /* another 500 ms (results in faster booting) */
 567         } else {
 568                 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
 569                         priv->link = 1;
 570                 else
 571                         priv->link = 0;
 572         }
 573
 574         if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
 575                 priv->duplexity = 1;
 576         else
 577                 priv->duplexity = 0;
 578
 579         speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
 580
 581         switch (speed) {
 582         case MIIM_88E1011_PHYSTAT_GBIT:
 583                 priv->speed = 1000;
 584                 break;
 585         case MIIM_88E1011_PHYSTAT_100:
 586                 priv->speed = 100;
 587                 break;
 588         default:
 589                 priv->speed = 10;
 590         }
 591
 592         return 0;
 593 }
 594
 595 /* Parse the RTL8211B's status register for speed and duplex
 596  * information
 597  */
 598 uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv)
 599 {
 600         uint speed;
 601
 602         mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
 603         if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
 604                 int i = 0;
 605
 606                 /* in case of timeout ->link is cleared */
 607                 priv->link = 1;
 608                 puts("Waiting for PHY realtime link");
 609                 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
 610                         /* Timeout reached ? */
 611                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 612                                 puts(" TIMEOUT !\n");
 613                                 priv->link = 0;
 614                                 break;
 615                         }
 616
 617                         if ((i++ % 1000) == 0) {
 618                                 putc('.');
 619                         }
 620                         udelay(1000);   /* 1 ms */
 621                         mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
 622                 }
 623                 puts(" done\n");
 624                 udelay(500000); /* another 500 ms (results in faster booting) */
 625         } else {
 626                 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK)
 627                         priv->link = 1;
 628                 else
 629                         priv->link = 0;
 630         }
 631
 632         if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX)
 633                 priv->duplexity = 1;
 634         else
 635                 priv->duplexity = 0;
 636
 637         speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED);
 638
 639         switch (speed) {
 640         case MIIM_RTL8211B_PHYSTAT_GBIT:
 641                 priv->speed = 1000;
 642                 break;
 643         case MIIM_RTL8211B_PHYSTAT_100:
 644                 priv->speed = 100;
 645                 break;
 646         default:
 647                 priv->speed = 10;
 648         }
 649
 650         return 0;
 651 }
 652
 653 /* Parse the cis8201's status register for speed and duplex
 654  * information
 655  */
 656 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
 657 {
 658         uint speed;
 659
 660         if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
 661                 priv->duplexity = 1;
 662         else
 663                 priv->duplexity = 0;
 664
 665         speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
 666         switch (speed) {
 667         case MIIM_CIS8201_AUXCONSTAT_GBIT:
 668                 priv->speed = 1000;
 669                 break;
 670         case MIIM_CIS8201_AUXCONSTAT_100:
 671                 priv->speed = 100;
 672                 break;
 673         default:
 674                 priv->speed = 10;
 675                 break;
 676         }
 677
 678         return 0;
 679 }
 680
 681 /* Parse the vsc8244's status register for speed and duplex
 682  * information
 683  */
 684 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
 685 {
 686         uint speed;
 687
 688         if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
 689                 priv->duplexity = 1;
 690         else
 691                 priv->duplexity = 0;
 692
 693         speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
 694         switch (speed) {
 695         case MIIM_VSC8244_AUXCONSTAT_GBIT:
 696                 priv->speed = 1000;
 697                 break;
 698         case MIIM_VSC8244_AUXCONSTAT_100:
 699                 priv->speed = 100;
 700                 break;
 701         default:
 702                 priv->speed = 10;
 703                 break;
 704         }
 705
 706         return 0;
 707 }
 708
 709 /* Parse the DM9161's status register for speed and duplex
 710  * information
 711  */
 712 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
 713 {
 714         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
 715                 priv->speed = 100;
 716         else
 717                 priv->speed = 10;
 718
 719         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
 720                 priv->duplexity = 1;
 721         else
 722                 priv->duplexity = 0;
 723
 724         return 0;
 725 }
 726
 727 /*
 728  * Hack to write all 4 PHYs with the LED values
 729  */
 730 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
 731 {
 732         uint phyid;
 733         volatile tsec_t *regbase = priv->phyregs;
 734         int timeout = 1000000;
 735
 736         for (phyid = 0; phyid < 4; phyid++) {
 737                 regbase->miimadd = (phyid << 8) | mii_reg;
 738                 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
 739                 asm("sync");
 740
 741                 timeout = 1000000;
 742                 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
 743         }
 744
 745         return MIIM_CIS8204_SLEDCON_INIT;
 746 }
 747
 748 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
 749 {
 750         if (priv->flags & TSEC_REDUCED)
 751                 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
 752         else
 753                 return MIIM_CIS8204_EPHYCON_INIT;
 754 }
 755
 756 uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv)
 757 {
 758         uint mii_data = read_phy_reg(priv, mii_reg);
 759
 760         if (priv->flags & TSEC_REDUCED)
 761                 mii_data = (mii_data & 0xfff0) | 0x000b;
 762         return mii_data;
 763 }
 764
 765 /* Initialized required registers to appropriate values, zeroing
 766  * those we don't care about (unless zero is bad, in which case,
 767  * choose a more appropriate value)
 768  */
 769 static void init_registers(volatile tsec_t * regs)
 770 {
 771         /* Clear IEVENT */
 772         regs->ievent = IEVENT_INIT_CLEAR;
 773
 774         regs->imask = IMASK_INIT_CLEAR;
 775
 776         regs->hash.iaddr0 = 0;
 777         regs->hash.iaddr1 = 0;
 778         regs->hash.iaddr2 = 0;
 779         regs->hash.iaddr3 = 0;
 780         regs->hash.iaddr4 = 0;
 781         regs->hash.iaddr5 = 0;
 782         regs->hash.iaddr6 = 0;
 783         regs->hash.iaddr7 = 0;
 784
 785         regs->hash.gaddr0 = 0;
 786         regs->hash.gaddr1 = 0;
 787         regs->hash.gaddr2 = 0;
 788         regs->hash.gaddr3 = 0;
 789         regs->hash.gaddr4 = 0;
 790         regs->hash.gaddr5 = 0;
 791         regs->hash.gaddr6 = 0;
 792         regs->hash.gaddr7 = 0;
 793
 794         regs->rctrl = 0x00000000;
 795
 796         /* Init RMON mib registers */
 797         memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
 798
 799         regs->rmon.cam1 = 0xffffffff;
 800         regs->rmon.cam2 = 0xffffffff;
 801
 802         regs->mrblr = MRBLR_INIT_SETTINGS;
 803
 804         regs->minflr = MINFLR_INIT_SETTINGS;
 805
 806         regs->attr = ATTR_INIT_SETTINGS;
 807         regs->attreli = ATTRELI_INIT_SETTINGS;
 808
 809 }
 810
 811 /* Configure maccfg2 based on negotiated speed and duplex
 812  * reported by PHY handling code
 813  */
 814 static void adjust_link(struct eth_device *dev)
 815 {
 816         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 817         volatile tsec_t *regs = priv->regs;
 818
 819         if (priv->link) {
 820                 if (priv->duplexity != 0)
 821                         regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
 822                 else
 823                         regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
 824
 825                 switch (priv->speed) {
 826                 case 1000:
 827                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 828                                          | MACCFG2_GMII);
 829                         break;
 830                 case 100:
 831                 case 10:
 832                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 833                                          | MACCFG2_MII);
 834
 835                         /* Set R100 bit in all modes although
 836                          * it is only used in RGMII mode
 837                          */
 838                         if (priv->speed == 100)
 839                                 regs->ecntrl |= ECNTRL_R100;
 840                         else
 841                                 regs->ecntrl &= ~(ECNTRL_R100);
 842                         break;
 843                 default:
 844                         printf("%s: Speed was bad\n", dev->name);
 845                         break;
 846                 }
 847
 848                 printf("Speed: %d, %s duplex\n", priv->speed,
 849                        (priv->duplexity) ? "full" : "half");
 850
 851         } else {
 852                 printf("%s: No link.\n", dev->name);
 853         }
 854 }
 855
 856 /* Set up the buffers and their descriptors, and bring up the
 857  * interface
 858  */
 859 static void startup_tsec(struct eth_device *dev)
 860 {
 861         int i;
 862         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 863         volatile tsec_t *regs = priv->regs;
 864
 865         /* Point to the buffer descriptors */
 866         regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
 867         regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
 868
 869         /* Initialize the Rx Buffer descriptors */
 870         for (i = 0; i < PKTBUFSRX; i++) {
 871                 rtx.rxbd[i].status = RXBD_EMPTY;
 872                 rtx.rxbd[i].length = 0;
 873                 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
 874         }
 875         rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
 876
 877         /* Initialize the TX Buffer Descriptors */
 878         for (i = 0; i < TX_BUF_CNT; i++) {
 879                 rtx.txbd[i].status = 0;
 880                 rtx.txbd[i].length = 0;
 881                 rtx.txbd[i].bufPtr = 0;
 882         }
 883         rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
 884
 885         /* Start up the PHY */
 886         if(priv->phyinfo)
 887                 phy_run_commands(priv, priv->phyinfo->startup);
 888
 889         adjust_link(dev);
 890
 891         /* Enable Transmit and Receive */
 892         regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 893
 894         /* Tell the DMA it is clear to go */
 895         regs->dmactrl |= DMACTRL_INIT_SETTINGS;
 896         regs->tstat = TSTAT_CLEAR_THALT;
 897         regs->rstat = RSTAT_CLEAR_RHALT;
 898         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 899 }
 900
 901 /* This returns the status bits of the device.  The return value
 902  * is never checked, and this is what the 8260 driver did, so we
 903  * do the same.  Presumably, this would be zero if there were no
 904  * errors
 905  */
 906 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
 907 {
 908         int i;
 909         int result = 0;
 910         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 911         volatile tsec_t *regs = priv->regs;
 912
 913         /* Find an empty buffer descriptor */
 914         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 915                 if (i >= TOUT_LOOP) {
 916                         debug("%s: tsec: tx buffers full\n", dev->name);
 917                         return result;
 918                 }
 919         }
 920
 921         rtx.txbd[txIdx].bufPtr = (uint) packet;
 922         rtx.txbd[txIdx].length = length;
 923         rtx.txbd[txIdx].status |=
 924             (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
 925
 926         /* Tell the DMA to go */
 927         regs->tstat = TSTAT_CLEAR_THALT;
 928
 929         /* Wait for buffer to be transmitted */
 930         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 931                 if (i >= TOUT_LOOP) {
 932                         debug("%s: tsec: tx error\n", dev->name);
 933                         return result;
 934                 }
 935         }
 936
 937         txIdx = (txIdx + 1) % TX_BUF_CNT;
 938         result = rtx.txbd[txIdx].status & TXBD_STATS;
 939
 940         return result;
 941 }
 942
 943 static int tsec_recv(struct eth_device *dev)
 944 {
 945         int length;
 946         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 947         volatile tsec_t *regs = priv->regs;
 948
 949         while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
 950
 951                 length = rtx.rxbd[rxIdx].length;
 952
 953                 /* Send the packet up if there were no errors */
 954                 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
 955                         NetReceive(NetRxPackets[rxIdx], length - 4);
 956                 } else {
 957                         printf("Got error %x\n",
 958                                (rtx.rxbd[rxIdx].status & RXBD_STATS));
 959                 }
 960
 961                 rtx.rxbd[rxIdx].length = 0;
 962
 963                 /* Set the wrap bit if this is the last element in the list */
 964                 rtx.rxbd[rxIdx].status =
 965                     RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
 966
 967                 rxIdx = (rxIdx + 1) % PKTBUFSRX;
 968         }
 969
 970         if (regs->ievent & IEVENT_BSY) {
 971                 regs->ievent = IEVENT_BSY;
 972                 regs->rstat = RSTAT_CLEAR_RHALT;
 973         }
 974
 975         return -1;
 976
 977 }
 978
 979 /* Stop the interface */
 980 static void tsec_halt(struct eth_device *dev)
 981 {
 982         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 983         volatile tsec_t *regs = priv->regs;
 984
 985         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 986         regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
 987
 988         while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
 989
 990         regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
 991
 992         /* Shut down the PHY, as needed */
 993         if(priv->phyinfo)
 994                 phy_run_commands(priv, priv->phyinfo->shutdown);
 995 }
 996
 997 struct phy_info phy_info_M88E1149S = {
 998         0x1410ca,
 999         "Marvell 88E1149S",
1000         4,
1001         (struct phy_cmd[]){     /* config */
1002                 /* Reset and configure the PHY */
1003                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1004                 {0x1d, 0x1f, NULL},
1005                 {0x1e, 0x200c, NULL},
1006                 {0x1d, 0x5, NULL},
1007                 {0x1e, 0x0, NULL},
1008                 {0x1e, 0x100, NULL},
1009                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1010                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1011                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1012                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1013                 {miim_end,}
1014         },
1015         (struct phy_cmd[]){     /* startup */
1016                 /* Status is read once to clear old link state */
1017                 {MIIM_STATUS, miim_read, NULL},
1018                 /* Auto-negotiate */
1019                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1020                 /* Read the status */
1021                 {MIIM_88E1011_PHY_STATUS, miim_read,
1022                  &mii_parse_88E1011_psr},
1023                 {miim_end,}
1024         },
1025         (struct phy_cmd[]){     /* shutdown */
1026                 {miim_end,}
1027         },
1028 };
1029
1030 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
1031 struct phy_info phy_info_BCM5461S = {
1032         0x02060c1,      /* 5461 ID */
1033         "Broadcom BCM5461S",
1034         0, /* not clear to me what minor revisions we can shift away */
1035         (struct phy_cmd[]) { /* config */
1036                 /* Reset and configure the PHY */
1037                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1038                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1039                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1040                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1041                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1042                 {miim_end,}
1043         },
1044         (struct phy_cmd[]) { /* startup */
1045                 /* Status is read once to clear old link state */
1046                 {MIIM_STATUS, miim_read, NULL},
1047                 /* Auto-negotiate */
1048                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1049                 /* Read the status */
1050                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1051                 {miim_end,}
1052         },
1053         (struct phy_cmd[]) { /* shutdown */
1054                 {miim_end,}
1055         },
1056 };
1057
1058 struct phy_info phy_info_BCM5464S = {
1059         0x02060b1,      /* 5464 ID */
1060         "Broadcom BCM5464S",
1061         0, /* not clear to me what minor revisions we can shift away */
1062         (struct phy_cmd[]) { /* config */
1063                 /* Reset and configure the PHY */
1064                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1065                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1066                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1067                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1068                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1069                 {miim_end,}
1070         },
1071         (struct phy_cmd[]) { /* startup */
1072                 /* Status is read once to clear old link state */
1073                 {MIIM_STATUS, miim_read, NULL},
1074                 /* Auto-negotiate */
1075                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1076                 /* Read the status */
1077                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1078                 {miim_end,}
1079         },
1080         (struct phy_cmd[]) { /* shutdown */
1081                 {miim_end,}
1082         },
1083 };
1084
1085 struct phy_info phy_info_BCM5482S =  {
1086         0x0143bcb,
1087         "Broadcom BCM5482S",
1088         4,
1089         (struct phy_cmd[]) { /* config */
1090                 /* Reset and configure the PHY */
1091                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1092                 /* Setup read from auxilary control shadow register 7 */
1093                 {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL},
1094                 /* Read Misc Control register and or in Ethernet@Wirespeed */
1095                 {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed},
1096                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1097                 {miim_end,}
1098         },
1099         (struct phy_cmd[]) { /* startup */
1100                 /* Status is read once to clear old link state */
1101                 {MIIM_STATUS, miim_read, NULL},
1102                 /* Auto-negotiate */
1103                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1104                 /* Read the status */
1105                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1106                 {miim_end,}
1107         },
1108         (struct phy_cmd[]) { /* shutdown */
1109                 {miim_end,}
1110         },
1111 };
1112
1113 struct phy_info phy_info_M88E1011S = {
1114         0x01410c6,
1115         "Marvell 88E1011S",
1116         4,
1117         (struct phy_cmd[]){     /* config */
1118                            /* Reset and configure the PHY */
1119                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1120                            {0x1d, 0x1f, NULL},
1121                            {0x1e, 0x200c, NULL},
1122                            {0x1d, 0x5, NULL},
1123                            {0x1e, 0x0, NULL},
1124                            {0x1e, 0x100, NULL},
1125                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1126                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1127                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1128                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1129                            {miim_end,}
1130                            },
1131         (struct phy_cmd[]){     /* startup */
1132                            /* Status is read once to clear old link state */
1133                            {MIIM_STATUS, miim_read, NULL},
1134                            /* Auto-negotiate */
1135                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1136                            /* Read the status */
1137                            {MIIM_88E1011_PHY_STATUS, miim_read,
1138                             &mii_parse_88E1011_psr},
1139                            {miim_end,}
1140                            },
1141         (struct phy_cmd[]){     /* shutdown */
1142                            {miim_end,}
1143                            },
1144 };
1145
1146 struct phy_info phy_info_M88E1111S = {
1147         0x01410cc,
1148         "Marvell 88E1111S",
1149         4,
1150         (struct phy_cmd[]){     /* config */
1151                            /* Reset and configure the PHY */
1152                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1153                            {0x1b, 0x848f, &mii_m88e1111s_setmode},
1154                            {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
1155                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1156                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1157                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1158                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1159                            {miim_end,}
1160                            },
1161         (struct phy_cmd[]){     /* startup */
1162                            /* Status is read once to clear old link state */
1163                            {MIIM_STATUS, miim_read, NULL},
1164                            /* Auto-negotiate */
1165                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1166                            /* Read the status */
1167                            {MIIM_88E1011_PHY_STATUS, miim_read,
1168                             &mii_parse_88E1011_psr},
1169                            {miim_end,}
1170                            },
1171         (struct phy_cmd[]){     /* shutdown */
1172                            {miim_end,}
1173                            },
1174 };
1175
1176 struct phy_info phy_info_M88E1118 = {
1177         0x01410e1,
1178         "Marvell 88E1118",
1179         4,
1180         (struct phy_cmd[]){     /* config */
1181                 /* Reset and configure the PHY */
1182                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1183                 {0x16, 0x0002, NULL}, /* Change Page Number */
1184                 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */
1185                 {0x16, 0x0003, NULL}, /* Change Page Number */
1186                 {0x10, 0x021e, NULL}, /* Adjust LED control */
1187                 {0x16, 0x0000, NULL}, /* Change Page Number */
1188                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1189                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1190                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1191                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1192                 {miim_end,}
1193                 },
1194         (struct phy_cmd[]){     /* startup */
1195                 {0x16, 0x0000, NULL}, /* Change Page Number */
1196                 /* Status is read once to clear old link state */
1197                 {MIIM_STATUS, miim_read, NULL},
1198                 /* Auto-negotiate */
1199                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1200                 /* Read the status */
1201                 {MIIM_88E1011_PHY_STATUS, miim_read,
1202                  &mii_parse_88E1011_psr},
1203                 {miim_end,}
1204                 },
1205         (struct phy_cmd[]){     /* shutdown */
1206                 {miim_end,}
1207                 },
1208 };
1209
1210 /*
1211  *  Since to access LED register we need do switch the page, we
1212  * do LED configuring in the miim_read-like function as follows
1213  */
1214 uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv)
1215 {
1216         uint pg;
1217
1218         /* Switch the page to access the led register */
1219         pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE);
1220         write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE);
1221
1222         /* Configure leds */
1223         write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL,
1224                       MIIM_88E1121_PHY_LED_DEF);
1225
1226         /* Restore the page pointer */
1227         write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg);
1228         return 0;
1229 }
1230
1231 struct phy_info phy_info_M88E1121R = {
1232         0x01410cb,
1233         "Marvell 88E1121R",
1234         4,
1235         (struct phy_cmd[]){     /* config */
1236                            /* Reset and configure the PHY */
1237                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1238                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1239                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1240                            /* Configure leds */
1241                            {MIIM_88E1121_PHY_LED_CTRL, miim_read,
1242                             &mii_88E1121_set_led},
1243                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1244                            /* Disable IRQs and de-assert interrupt */
1245                            {MIIM_88E1121_PHY_IRQ_EN, 0, NULL},
1246                            {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL},
1247                            {miim_end,}
1248                            },
1249         (struct phy_cmd[]){     /* startup */
1250                            /* Status is read once to clear old link state */
1251                            {MIIM_STATUS, miim_read, NULL},
1252                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1253                            {MIIM_STATUS, miim_read, &mii_parse_link},
1254                            {miim_end,}
1255                            },
1256         (struct phy_cmd[]){     /* shutdown */
1257                            {miim_end,}
1258                            },
1259 };
1260
1261 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
1262 {
1263         uint mii_data = read_phy_reg(priv, mii_reg);
1264
1265         /* Setting MIIM_88E1145_PHY_EXT_CR */
1266         if (priv->flags & TSEC_REDUCED)
1267                 return mii_data |
1268                     MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
1269         else
1270                 return mii_data;
1271 }
1272
1273 static struct phy_info phy_info_M88E1145 = {
1274         0x01410cd,
1275         "Marvell 88E1145",
1276         4,
1277         (struct phy_cmd[]){     /* config */
1278                            /* Reset the PHY */
1279                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1280
1281                            /* Errata E0, E1 */
1282                            {29, 0x001b, NULL},
1283                            {30, 0x418f, NULL},
1284                            {29, 0x0016, NULL},
1285                            {30, 0xa2da, NULL},
1286
1287                            /* Configure the PHY */
1288                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1289                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1290                            {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
1291                             NULL},
1292                            {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
1293                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1294                            {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
1295                            {miim_end,}
1296                            },
1297         (struct phy_cmd[]){     /* startup */
1298                            /* Status is read once to clear old link state */
1299                            {MIIM_STATUS, miim_read, NULL},
1300                            /* Auto-negotiate */
1301                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1302                            {MIIM_88E1111_PHY_LED_CONTROL,
1303                             MIIM_88E1111_PHY_LED_DIRECT, NULL},
1304                            /* Read the Status */
1305                            {MIIM_88E1011_PHY_STATUS, miim_read,
1306                             &mii_parse_88E1011_psr},
1307                            {miim_end,}
1308                            },
1309         (struct phy_cmd[]){     /* shutdown */
1310                            {miim_end,}
1311                            },
1312 };
1313
1314 struct phy_info phy_info_cis8204 = {
1315         0x3f11,
1316         "Cicada Cis8204",
1317         6,
1318         (struct phy_cmd[]){     /* config */
1319                            /* Override PHY config settings */
1320                            {MIIM_CIS8201_AUX_CONSTAT,
1321                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1322                            /* Configure some basic stuff */
1323                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1324                            {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
1325                             &mii_cis8204_fixled},
1326                            {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
1327                             &mii_cis8204_setmode},
1328                            {miim_end,}
1329                            },
1330         (struct phy_cmd[]){     /* startup */
1331                            /* Read the Status (2x to make sure link is right) */
1332                            {MIIM_STATUS, miim_read, NULL},
1333                            /* Auto-negotiate */
1334                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1335                            /* Read the status */
1336                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1337                             &mii_parse_cis8201},
1338                            {miim_end,}
1339                            },
1340         (struct phy_cmd[]){     /* shutdown */
1341                            {miim_end,}
1342                            },
1343 };
1344
1345 /* Cicada 8201 */
1346 struct phy_info phy_info_cis8201 = {
1347         0xfc41,
1348         "CIS8201",
1349         4,
1350         (struct phy_cmd[]){     /* config */
1351                            /* Override PHY config settings */
1352                            {MIIM_CIS8201_AUX_CONSTAT,
1353                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1354                            /* Set up the interface mode */
1355                            {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
1356                             NULL},
1357                            /* Configure some basic stuff */
1358                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1359                            {miim_end,}
1360                            },
1361         (struct phy_cmd[]){     /* startup */
1362                            /* Read the Status (2x to make sure link is right) */
1363                            {MIIM_STATUS, miim_read, NULL},
1364                            /* Auto-negotiate */
1365                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1366                            /* Read the status */
1367                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1368                             &mii_parse_cis8201},
1369                            {miim_end,}
1370                            },
1371         (struct phy_cmd[]){     /* shutdown */
1372                            {miim_end,}
1373                            },
1374 };
1375 struct phy_info phy_info_VSC8211 = {
1376         0xfc4b,
1377         "Vitesse VSC8211",
1378         4,
1379         (struct phy_cmd[]) { /* config */
1380                            /* Override PHY config settings */
1381                            {MIIM_CIS8201_AUX_CONSTAT,
1382                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1383                            /* Set up the interface mode */
1384                            {MIIM_CIS8201_EXT_CON1,
1385                             MIIM_CIS8201_EXTCON1_INIT, NULL},
1386                            /* Configure some basic stuff */
1387                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1388                            {miim_end,}
1389                            },
1390         (struct phy_cmd[]) { /* startup */
1391                            /* Read the Status (2x to make sure link is right) */
1392                            {MIIM_STATUS, miim_read, NULL},
1393                            /* Auto-negotiate */
1394                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1395                            /* Read the status */
1396                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1397                             &mii_parse_cis8201},
1398                            {miim_end,}
1399                            },
1400         (struct phy_cmd[]) { /* shutdown */
1401                            {miim_end,}
1402         },
1403 };
1404 struct phy_info phy_info_VSC8244 = {
1405         0x3f1b,
1406         "Vitesse VSC8244",
1407         6,
1408         (struct phy_cmd[]){     /* config */
1409                            /* Override PHY config settings */
1410                            /* Configure some basic stuff */
1411                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1412                            {miim_end,}
1413                            },
1414         (struct phy_cmd[]){     /* startup */
1415                            /* Read the Status (2x to make sure link is right) */
1416                            {MIIM_STATUS, miim_read, NULL},
1417                            /* Auto-negotiate */
1418                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1419                            /* Read the status */
1420                            {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1421                             &mii_parse_vsc8244},
1422                            {miim_end,}
1423                            },
1424         (struct phy_cmd[]){     /* shutdown */
1425                            {miim_end,}
1426                            },
1427 };
1428
1429 struct phy_info phy_info_VSC8601 = {
1430                 0x00007042,
1431                 "Vitesse VSC8601",
1432                 4,
1433                 (struct phy_cmd[]){     /* config */
1434                                 /* Override PHY config settings */
1435                                 /* Configure some basic stuff */
1436                                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1437 #ifdef CONFIG_SYS_VSC8601_SKEWFIX
1438                                 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
1439 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
1440                                 {MIIM_EXT_PAGE_ACCESS,1,NULL},
1441 #define VSC8101_SKEW    (CONFIG_SYS_VSC8601_SKEW_TX<<14)|(CONFIG_SYS_VSC8601_SKEW_RX<<12)
1442                                 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
1443                                 {MIIM_EXT_PAGE_ACCESS,0,NULL},
1444 #endif
1445 #endif
1446                                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1447                                 {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init},
1448                                 {miim_end,}
1449                                  },
1450                 (struct phy_cmd[]){     /* startup */
1451                                 /* Read the Status (2x to make sure link is right) */
1452                                 {MIIM_STATUS, miim_read, NULL},
1453                                 /* Auto-negotiate */
1454                                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1455                                 /* Read the status */
1456                                 {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1457                                                 &mii_parse_vsc8244},
1458                                 {miim_end,}
1459                                 },
1460                 (struct phy_cmd[]){     /* shutdown */
1461                                 {miim_end,}
1462                                 },
1463 };
1464
1465
1466 struct phy_info phy_info_dm9161 = {
1467         0x0181b88,
1468         "Davicom DM9161E",
1469         4,
1470         (struct phy_cmd[]){     /* config */
1471                            {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1472                            /* Do not bypass the scrambler/descrambler */
1473                            {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1474                            /* Clear 10BTCSR to default */
1475                            {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
1476                             NULL},
1477                            /* Configure some basic stuff */
1478                            {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1479                            /* Restart Auto Negotiation */
1480                            {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1481                            {miim_end,}
1482                            },
1483         (struct phy_cmd[]){     /* startup */
1484                            /* Status is read once to clear old link state */
1485                            {MIIM_STATUS, miim_read, NULL},
1486                            /* Auto-negotiate */
1487                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1488                            /* Read the status */
1489                            {MIIM_DM9161_SCSR, miim_read,
1490                             &mii_parse_dm9161_scsr},
1491                            {miim_end,}
1492                            },
1493         (struct phy_cmd[]){     /* shutdown */
1494                            {miim_end,}
1495                            },
1496 };
1497 /* a generic flavor.  */
1498 struct phy_info phy_info_generic =  {
1499         0,
1500         "Unknown/Generic PHY",
1501         32,
1502         (struct phy_cmd[]) { /* config */
1503                 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1504                 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1505                 {miim_end,}
1506         },
1507         (struct phy_cmd[]) { /* startup */
1508                 {PHY_BMSR, miim_read, NULL},
1509                 {PHY_BMSR, miim_read, &mii_parse_sr},
1510                 {PHY_BMSR, miim_read, &mii_parse_link},
1511                 {miim_end,}
1512         },
1513         (struct phy_cmd[]) { /* shutdown */
1514                 {miim_end,}
1515         }
1516 };
1517
1518
1519 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1520 {
1521         unsigned int speed;
1522         if (priv->link) {
1523                 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1524
1525                 switch (speed) {
1526                 case MIIM_LXT971_SR2_10HDX:
1527                         priv->speed = 10;
1528                         priv->duplexity = 0;
1529                         break;
1530                 case MIIM_LXT971_SR2_10FDX:
1531                         priv->speed = 10;
1532                         priv->duplexity = 1;
1533                         break;
1534                 case MIIM_LXT971_SR2_100HDX:
1535                         priv->speed = 100;
1536                         priv->duplexity = 0;
1537                         break;
1538                 default:
1539                         priv->speed = 100;
1540                         priv->duplexity = 1;
1541                 }
1542         } else {
1543                 priv->speed = 0;
1544                 priv->duplexity = 0;
1545         }
1546
1547         return 0;
1548 }
1549
1550 static struct phy_info phy_info_lxt971 = {
1551         0x0001378e,
1552         "LXT971",
1553         4,
1554         (struct phy_cmd[]){     /* config */
1555                            {MIIM_CR, MIIM_CR_INIT, mii_cr_init},        /* autonegotiate */
1556                            {miim_end,}
1557                            },
1558         (struct phy_cmd[]){     /* startup - enable interrupts */
1559                            /* { 0x12, 0x00f2, NULL }, */
1560                            {MIIM_STATUS, miim_read, NULL},
1561                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1562                            {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1563                            {miim_end,}
1564                            },
1565         (struct phy_cmd[]){     /* shutdown - disable interrupts */
1566                            {miim_end,}
1567                            },
1568 };
1569
1570 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1571  * information
1572  */
1573 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1574 {
1575         switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1576
1577         case MIIM_DP83865_SPD_1000:
1578                 priv->speed = 1000;
1579                 break;
1580
1581         case MIIM_DP83865_SPD_100:
1582                 priv->speed = 100;
1583                 break;
1584
1585         default:
1586                 priv->speed = 10;
1587                 break;
1588
1589         }
1590
1591         if (mii_reg & MIIM_DP83865_DPX_FULL)
1592                 priv->duplexity = 1;
1593         else
1594                 priv->duplexity = 0;
1595
1596         return 0;
1597 }
1598
1599 struct phy_info phy_info_dp83865 = {
1600         0x20005c7,
1601         "NatSemi DP83865",
1602         4,
1603         (struct phy_cmd[]){     /* config */
1604                            {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1605                            {miim_end,}
1606                            },
1607         (struct phy_cmd[]){     /* startup */
1608                            /* Status is read once to clear old link state */
1609                            {MIIM_STATUS, miim_read, NULL},
1610                            /* Auto-negotiate */
1611                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1612                            /* Read the link and auto-neg status */
1613                            {MIIM_DP83865_LANR, miim_read,
1614                             &mii_parse_dp83865_lanr},
1615                            {miim_end,}
1616                            },
1617         (struct phy_cmd[]){     /* shutdown */
1618                            {miim_end,}
1619                            },
1620 };
1621
1622 struct phy_info phy_info_rtl8211b = {
1623         0x001cc91,
1624         "RealTek RTL8211B",
1625         4,
1626         (struct phy_cmd[]){     /* config */
1627                 /* Reset and configure the PHY */
1628                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1629                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1630                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1631                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1632                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1633                 {miim_end,}
1634         },
1635         (struct phy_cmd[]){     /* startup */
1636                 /* Status is read once to clear old link state */
1637                 {MIIM_STATUS, miim_read, NULL},
1638                 /* Auto-negotiate */
1639                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1640                 /* Read the status */
1641                 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr},
1642                 {miim_end,}
1643         },
1644         (struct phy_cmd[]){     /* shutdown */
1645                 {miim_end,}
1646         },
1647 };
1648
1649 struct phy_info *phy_info[] = {
1650         &phy_info_cis8204,
1651         &phy_info_cis8201,
1652         &phy_info_BCM5461S,
1653         &phy_info_BCM5464S,
1654         &phy_info_BCM5482S,
1655         &phy_info_M88E1011S,
1656         &phy_info_M88E1111S,
1657         &phy_info_M88E1118,
1658         &phy_info_M88E1121R,
1659         &phy_info_M88E1145,
1660         &phy_info_M88E1149S,
1661         &phy_info_dm9161,
1662         &phy_info_lxt971,
1663         &phy_info_VSC8211,
1664         &phy_info_VSC8244,
1665         &phy_info_VSC8601,
1666         &phy_info_dp83865,
1667         &phy_info_rtl8211b,
1668         &phy_info_generic,      /* must be last; has ID 0 and 32 bit mask */
1669         NULL
1670 };
1671
1672 /* Grab the identifier of the device's PHY, and search through
1673  * all of the known PHYs to see if one matches.  If so, return
1674  * it, if not, return NULL
1675  */
1676 struct phy_info *get_phy_info(struct eth_device *dev)
1677 {
1678         struct tsec_private *priv = (struct tsec_private *)dev->priv;
1679         uint phy_reg, phy_ID;
1680         int i;
1681         struct phy_info *theInfo = NULL;
1682
1683         /* Grab the bits from PHYIR1, and put them in the upper half */
1684         phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1685         phy_ID = (phy_reg & 0xffff) << 16;
1686
1687         /* Grab the bits from PHYIR2, and put them in the lower half */
1688         phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1689         phy_ID |= (phy_reg & 0xffff);
1690
1691         /* loop through all the known PHY types, and find one that */
1692         /* matches the ID we read from the PHY. */
1693         for (i = 0; phy_info[i]; i++) {
1694                 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
1695                         theInfo = phy_info[i];
1696                         break;
1697                 }
1698         }
1699
1700         if (theInfo == &phy_info_generic) {
1701                 printf("%s: No support for PHY id %x; assuming generic\n", dev->name, phy_ID);
1702         } else {
1703                 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1704         }
1705
1706         return theInfo;
1707 }
1708
1709 /* Execute the given series of commands on the given device's
1710  * PHY, running functions as necessary
1711  */
1712 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1713 {
1714         int i;
1715         uint result;
1716         volatile tsec_t *phyregs = priv->phyregs;
1717
1718         phyregs->miimcfg = MIIMCFG_RESET;
1719
1720         phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1721
1722         while (phyregs->miimind & MIIMIND_BUSY) ;
1723
1724         for (i = 0; cmd->mii_reg != miim_end; i++) {
1725                 if (cmd->mii_data == miim_read) {
1726                         result = read_phy_reg(priv, cmd->mii_reg);
1727
1728                         if (cmd->funct != NULL)
1729                                 (*(cmd->funct)) (result, priv);
1730
1731                 } else {
1732                         if (cmd->funct != NULL)
1733                                 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1734                         else
1735                                 result = cmd->mii_data;
1736
1737                         write_phy_reg(priv, cmd->mii_reg, result);
1738
1739                 }
1740                 cmd++;
1741         }
1742 }
1743
1744 /* Relocate the function pointers in the phy cmd lists */
1745 static void relocate_cmds(void)
1746 {
1747         struct phy_cmd **cmdlistptr;
1748         struct phy_cmd *cmd;
1749         int i, j, k;
1750
1751         for (i = 0; phy_info[i]; i++) {
1752                 /* First thing's first: relocate the pointers to the
1753                  * PHY command structures (the structs were done) */
1754                 phy_info[i] = (struct phy_info *)((uint) phy_info[i]
1755                                                   + gd->reloc_off);
1756                 phy_info[i]->name += gd->reloc_off;
1757                 phy_info[i]->config =
1758                     (struct phy_cmd *)((uint) phy_info[i]->config
1759                                        + gd->reloc_off);
1760                 phy_info[i]->startup =
1761                     (struct phy_cmd *)((uint) phy_info[i]->startup
1762                                        + gd->reloc_off);
1763                 phy_info[i]->shutdown =
1764                     (struct phy_cmd *)((uint) phy_info[i]->shutdown
1765                                        + gd->reloc_off);
1766
1767                 cmdlistptr = &phy_info[i]->config;
1768                 j = 0;
1769                 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
1770                         k = 0;
1771                         for (cmd = *cmdlistptr;
1772                              cmd->mii_reg != miim_end;
1773                              cmd++) {
1774                                 /* Only relocate non-NULL pointers */
1775                                 if (cmd->funct)
1776                                         cmd->funct += gd->reloc_off;
1777
1778                                 k++;
1779                         }
1780                         j++;
1781                 }
1782         }
1783
1784         relocated = 1;
1785 }
1786
1787 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1788         && !defined(BITBANGMII)
1789
1790 /*
1791  * Read a MII PHY register.
1792  *
1793  * Returns:
1794  *  0 on success
1795  */
1796 static int tsec_miiphy_read(char *devname, unsigned char addr,
1797                             unsigned char reg, unsigned short *value)
1798 {
1799         unsigned short ret;
1800         struct tsec_private *priv = privlist[0];
1801
1802         if (NULL == priv) {
1803                 printf("Can't read PHY at address %d\n", addr);
1804                 return -1;
1805         }
1806
1807         ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg);
1808         *value = ret;
1809
1810         return 0;
1811 }
1812
1813 /*
1814  * Write a MII PHY register.
1815  *
1816  * Returns:
1817  *  0 on success
1818  */
1819 static int tsec_miiphy_write(char *devname, unsigned char addr,
1820                              unsigned char reg, unsigned short value)
1821 {
1822         struct tsec_private *priv = privlist[0];
1823
1824         if (NULL == priv) {
1825                 printf("Can't write PHY at address %d\n", addr);
1826                 return -1;
1827         }
1828
1829         tsec_local_mdio_write(priv->phyregs, addr, reg, value);
1830
1831         return 0;
1832 }
1833
1834 #endif
1835
1836 #ifdef CONFIG_MCAST_TFTP
1837
1838 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
1839
1840 /* Set the appropriate hash bit for the given addr */
1841
1842 /* The algorithm works like so:
1843  * 1) Take the Destination Address (ie the multicast address), and
1844  * do a CRC on it (little endian), and reverse the bits of the
1845  * result.
1846  * 2) Use the 8 most significant bits as a hash into a 256-entry
1847  * table.  The table is controlled through 8 32-bit registers:
1848  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1849  * gaddr7.  This means that the 3 most significant bits in the
1850  * hash index which gaddr register to use, and the 5 other bits
1851  * indicate which bit (assuming an IBM numbering scheme, which
1852  * for PowerPC (tm) is usually the case) in the tregister holds
1853  * the entry. */
1854 static int
1855 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
1856 {
1857  struct tsec_private *priv = privlist[1];
1858  volatile tsec_t *regs = priv->regs;
1859  volatile u32  *reg_array, value;
1860  u8 result, whichbit, whichreg;
1861
1862         result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
1863         whichbit = result & 0x1f;       /* the 5 LSB = which bit to set */
1864         whichreg = result >> 5;         /* the 3 MSB = which reg to set it in */
1865         value = (1 << (31-whichbit));
1866
1867         reg_array = &(regs->hash.gaddr0);
1868
1869         if (set) {
1870                 reg_array[whichreg] |= value;
1871         } else {
1872                 reg_array[whichreg] &= ~value;
1873         }
1874         return 0;
1875 }
1876 #endif /* Multicast TFTP ? */