1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale Three Speed Ethernet Controller driver
5 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
6 * (C) Copyright 2003, Motorola, Inc.
18 #include <linux/bitops.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
22 #include <asm/processor.h>
25 #define TBIANA_SETTINGS ( \
26 TBIANA_ASYMMETRIC_PAUSE \
27 | TBIANA_SYMMETRIC_PAUSE \
28 | TBIANA_FULL_DUPLEX \
31 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
32 #ifndef CFG_TSEC_TBICR_SETTINGS
33 #define CFG_TSEC_TBICR_SETTINGS ( \
39 #endif /* CFG_TSEC_TBICR_SETTINGS */
41 /* Configure the TBI for SGMII operation */
42 static void tsec_configure_serdes(struct tsec_private *priv)
45 * Access TBI PHY registers at given TSEC register offset as opposed
46 * to the register offset used for external PHY accesses
48 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
49 0, TBI_ANA, TBIANA_SETTINGS);
50 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
51 0, TBI_TBICON, TBICON_CLK_SELECT);
52 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
53 0, TBI_CR, CFG_TSEC_TBICR_SETTINGS);
56 /* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
57 * and this is the ethernet-crc method needed for TSEC -- and perhaps
58 * some other adapter -- hash tables
60 #define CRCPOLY_LE 0xedb88320
61 static u32 ether_crc(size_t len, unsigned char const *p)
69 for (i = 0; i < 8; i++)
70 crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
72 /* an reverse the bits, cuz of way they arrive -- last-first */
73 crc = (crc >> 16) | (crc << 16);
74 crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
75 crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
76 crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
77 crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
81 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
83 /* Set the appropriate hash bit for the given addr */
86 * The algorithm works like so:
87 * 1) Take the Destination Address (ie the multicast address), and
88 * do a CRC on it (little endian), and reverse the bits of the
90 * 2) Use the 8 most significant bits as a hash into a 256-entry
91 * table. The table is controlled through 8 32-bit registers:
92 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
93 * 255. This means that the 3 most significant bits in the
94 * hash index which gaddr register to use, and the 5 other bits
95 * indicate which bit (assuming an IBM numbering scheme, which
96 * for PowerPC (tm) is usually the case) in the register holds
99 static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
101 struct tsec_private *priv;
102 struct tsec __iomem *regs;
104 u8 whichbit, whichreg;
106 priv = dev_get_priv(dev);
108 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
109 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
110 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
112 value = BIT(31 - whichbit);
115 setbits_be32(®s->hash.gaddr0 + whichreg, value);
117 clrbits_be32(®s->hash.gaddr0 + whichreg, value);
122 static int __maybe_unused tsec_set_promisc(struct udevice *dev, bool enable)
124 struct tsec_private *priv = dev_get_priv(dev);
125 struct tsec __iomem *regs = priv->regs;
128 setbits_be32(®s->rctrl, RCTRL_PROM);
130 clrbits_be32(®s->rctrl, RCTRL_PROM);
136 * Initialized required registers to appropriate values, zeroing
137 * those we don't care about (unless zero is bad, in which case,
138 * choose a more appropriate value)
140 static void init_registers(struct tsec __iomem *regs)
143 out_be32(®s->ievent, IEVENT_INIT_CLEAR);
145 out_be32(®s->imask, IMASK_INIT_CLEAR);
147 out_be32(®s->hash.iaddr0, 0);
148 out_be32(®s->hash.iaddr1, 0);
149 out_be32(®s->hash.iaddr2, 0);
150 out_be32(®s->hash.iaddr3, 0);
151 out_be32(®s->hash.iaddr4, 0);
152 out_be32(®s->hash.iaddr5, 0);
153 out_be32(®s->hash.iaddr6, 0);
154 out_be32(®s->hash.iaddr7, 0);
156 out_be32(®s->hash.gaddr0, 0);
157 out_be32(®s->hash.gaddr1, 0);
158 out_be32(®s->hash.gaddr2, 0);
159 out_be32(®s->hash.gaddr3, 0);
160 out_be32(®s->hash.gaddr4, 0);
161 out_be32(®s->hash.gaddr5, 0);
162 out_be32(®s->hash.gaddr6, 0);
163 out_be32(®s->hash.gaddr7, 0);
165 /* Init RMON mib registers */
166 memset((void *)®s->rmon, 0, sizeof(regs->rmon));
168 out_be32(®s->rmon.cam1, 0xffffffff);
169 out_be32(®s->rmon.cam2, 0xffffffff);
171 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
173 out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
175 out_be32(®s->attr, ATTR_INIT_SETTINGS);
176 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
180 * Configure maccfg2 based on negotiated speed and duplex
181 * reported by PHY handling code
183 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
185 struct tsec __iomem *regs = priv->regs;
189 printf("%s: No link.\n", phydev->dev->name);
193 /* clear all bits relative with interface mode */
194 ecntrl = in_be32(®s->ecntrl);
195 ecntrl &= ~ECNTRL_R100;
197 maccfg2 = in_be32(®s->maccfg2);
198 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
201 maccfg2 |= MACCFG2_FULL_DUPLEX;
203 switch (phydev->speed) {
205 maccfg2 |= MACCFG2_GMII;
209 maccfg2 |= MACCFG2_MII;
212 * Set R100 bit in all modes although
213 * it is only used in RGMII mode
215 if (phydev->speed == 100)
216 ecntrl |= ECNTRL_R100;
219 printf("%s: Speed was bad\n", phydev->dev->name);
223 out_be32(®s->ecntrl, ecntrl);
224 out_be32(®s->maccfg2, maccfg2);
226 printf("Speed: %d, %s duplex%s\n", phydev->speed,
227 (phydev->duplex) ? "full" : "half",
228 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
232 * This returns the status bits of the device. The return value
233 * is never checked, and this is what the 8260 driver did, so we
234 * do the same. Presumably, this would be zero if there were no
237 static int tsec_send(struct udevice *dev, void *packet, int length)
239 struct tsec_private *priv;
240 struct tsec __iomem *regs;
245 priv = dev_get_priv(dev);
247 /* Find an empty buffer descriptor */
249 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
251 if (i >= TOUT_LOOP) {
252 printf("%s: tsec: tx buffers full\n", dev->name);
257 out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
258 out_be16(&priv->txbd[priv->tx_idx].length, length);
259 status = in_be16(&priv->txbd[priv->tx_idx].status);
260 out_be16(&priv->txbd[priv->tx_idx].status, status |
261 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
263 /* Tell the DMA to go */
264 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
266 /* Wait for buffer to be transmitted */
268 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
270 if (i >= TOUT_LOOP) {
271 printf("%s: tsec: tx error\n", dev->name);
276 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
277 result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
282 static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
284 struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
285 struct tsec __iomem *regs = priv->regs;
288 if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
289 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
290 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
293 /* Send the packet up if there were no errors */
294 if (!(status & RXBD_STATS)) {
295 buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
296 *packetp = (uchar *)buf;
299 printf("Got error %x\n", (status & RXBD_STATS));
303 if (in_be32(®s->ievent) & IEVENT_BSY) {
304 out_be32(®s->ievent, IEVENT_BSY);
305 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
311 static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
313 struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
316 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
319 /* Set the wrap bit if this is the last element in the list */
320 if ((priv->rx_idx + 1) == PKTBUFSRX)
322 out_be16(&priv->rxbd[priv->rx_idx].status, status);
324 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
329 static void tsec_halt(struct udevice *dev)
331 struct tsec_private *priv;
332 struct tsec __iomem *regs;
333 priv = dev_get_priv(dev);
336 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
337 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
339 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
340 != (IEVENT_GRSC | IEVENT_GTSC))
343 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
345 /* Shut down the PHY, as needed */
346 phy_shutdown(priv->phydev);
349 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
351 * When MACCFG1[Rx_EN] is enabled during system boot as part
352 * of the eTSEC port initialization sequence,
353 * the eTSEC Rx logic may not be properly initialized.
355 static void redundant_init(struct tsec_private *priv)
357 struct tsec __iomem *regs = priv->regs;
360 static const u8 pkt[] = {
361 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
362 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
363 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
364 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
365 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
366 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
367 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
368 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
369 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
370 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
371 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
372 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
373 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
376 /* Enable promiscuous mode */
377 setbits_be32(®s->rctrl, RCTRL_PROM);
378 /* Enable loopback mode */
379 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
380 /* Enable transmit and receive */
381 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
383 /* Tell the DMA it is clear to go */
384 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
385 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
386 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
387 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
392 tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
394 /* Wait for buffer to be received */
396 in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
398 if (t >= 10 * TOUT_LOOP) {
399 printf("%s: tsec: rx error\n", priv->dev->name);
404 if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
407 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
409 if ((priv->rx_idx + 1) == PKTBUFSRX)
411 out_be16(&priv->rxbd[priv->rx_idx].status, status);
412 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
414 if (in_be32(®s->ievent) & IEVENT_BSY) {
415 out_be32(®s->ievent, IEVENT_BSY);
416 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
419 printf("loopback recv packet error!\n");
420 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
422 setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
424 } while ((count++ < 4) && (fail == 1));
427 panic("eTSEC init fail!\n");
428 /* Disable promiscuous mode */
429 clrbits_be32(®s->rctrl, RCTRL_PROM);
430 /* Disable loopback mode */
431 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
436 * Set up the buffers and their descriptors, and bring up the
439 static void startup_tsec(struct tsec_private *priv)
441 struct tsec __iomem *regs = priv->regs;
445 /* reset the indices to zero */
448 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
452 /* Point to the buffer descriptors */
453 out_be32(®s->tbase, (u32)&priv->txbd[0]);
454 out_be32(®s->rbase, (u32)&priv->rxbd[0]);
456 /* Initialize the Rx Buffer descriptors */
457 for (i = 0; i < PKTBUFSRX; i++) {
458 out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
459 out_be16(&priv->rxbd[i].length, 0);
460 out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
462 status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
463 out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
465 /* Initialize the TX Buffer Descriptors */
466 for (i = 0; i < TX_BUF_CNT; i++) {
467 out_be16(&priv->txbd[i].status, 0);
468 out_be16(&priv->txbd[i].length, 0);
469 out_be32(&priv->txbd[i].bufptr, 0);
471 status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
472 out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
474 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
476 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
477 redundant_init(priv);
479 /* Enable Transmit and Receive */
480 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
482 /* Tell the DMA it is clear to go */
483 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
484 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
485 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
486 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
490 * Initializes data structures and registers for the controller,
491 * and brings the interface up. Returns the link status, meaning
492 * that it returns success if the link is up, failure otherwise.
493 * This allows U-Boot to find the first active controller.
495 static int tsec_init(struct udevice *dev)
497 struct tsec_private *priv;
498 struct tsec __iomem *regs;
499 struct eth_pdata *pdata = dev_get_plat(dev);
503 priv = dev_get_priv(dev);
505 /* Make sure the controller is stopped */
508 /* Init MACCFG2. Defaults to GMII */
509 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
512 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
515 * Copy the station address into the address registers.
516 * For a station address of 0x12345678ABCD in transmission
517 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
518 * MACnADDR2 is set to 0x34120000.
520 tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
521 (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
523 out_be32(®s->macstnaddr1, tempval);
525 tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
527 out_be32(®s->macstnaddr2, tempval);
529 /* Clear out (for the most part) the other registers */
530 init_registers(regs);
532 /* Ready the device for tx/rx */
535 /* Start up the PHY */
536 ret = phy_startup(priv->phydev);
538 printf("Could not initialize PHY %s\n",
539 priv->phydev->dev->name);
543 adjust_link(priv, priv->phydev);
545 /* If there's no link, fail */
546 return priv->phydev->link ? 0 : -1;
549 static phy_interface_t __maybe_unused tsec_get_interface(struct tsec_private *priv)
551 struct tsec __iomem *regs = priv->regs;
554 ecntrl = in_be32(®s->ecntrl);
556 if (ecntrl & ECNTRL_SGMII_MODE)
557 return PHY_INTERFACE_MODE_SGMII;
559 if (ecntrl & ECNTRL_TBI_MODE) {
560 if (ecntrl & ECNTRL_REDUCED_MODE)
561 return PHY_INTERFACE_MODE_RTBI;
563 return PHY_INTERFACE_MODE_TBI;
566 if (ecntrl & ECNTRL_REDUCED_MODE) {
567 phy_interface_t interface;
569 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
570 return PHY_INTERFACE_MODE_RMII;
572 interface = priv->interface;
575 * This isn't autodetected, so it must
576 * be set by the platform code.
578 if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
579 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
580 interface == PHY_INTERFACE_MODE_RGMII_RXID)
583 return PHY_INTERFACE_MODE_RGMII;
586 if (priv->flags & TSEC_GIGABIT)
587 return PHY_INTERFACE_MODE_GMII;
589 return PHY_INTERFACE_MODE_MII;
593 * Discover which PHY is attached to the device, and configure it
594 * properly. If the PHY is not recognized, then return 0
595 * (failure). Otherwise, return 1
597 static int init_phy(struct tsec_private *priv)
599 struct phy_device *phydev;
600 struct tsec __iomem *regs = priv->regs;
601 u32 supported = (SUPPORTED_10baseT_Half |
602 SUPPORTED_10baseT_Full |
603 SUPPORTED_100baseT_Half |
604 SUPPORTED_100baseT_Full);
606 if (priv->flags & TSEC_GIGABIT)
607 supported |= SUPPORTED_1000baseT_Full;
609 /* Assign a Physical address to the TBI */
610 out_be32(®s->tbipa, priv->tbiaddr);
612 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
613 tsec_configure_serdes(priv);
615 #if defined(CONFIG_DM_MDIO)
616 phydev = dm_eth_phy_connect(priv->dev);
618 phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
624 phydev->supported &= supported;
625 phydev->advertising = phydev->supported;
627 priv->phydev = phydev;
634 int tsec_probe(struct udevice *dev)
636 struct eth_pdata *pdata = dev_get_plat(dev);
637 struct tsec_private *priv = dev_get_priv(dev);
638 struct ofnode_phandle_args phandle_args;
639 u32 tbiaddr = CFG_SYS_TBIPA_VALUE;
640 struct tsec_data *data;
641 ofnode parent, child;
646 data = (struct tsec_data *)dev_get_driver_data(dev);
648 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
649 if (pdata->iobase == FDT_ADDR_T_NONE) {
650 ofnode_for_each_subnode(child, dev_ofnode(dev)) {
651 if (strncmp(ofnode_get_name(child), "queue-group",
652 strlen("queue-group")))
655 reg = ofnode_get_addr(child);
656 if (reg == FDT_ADDR_T_NONE) {
657 printf("No 'reg' property of <queue-group>\n");
663 * if there are multiple queue groups,
664 * only the first one is used.
669 if (!ofnode_valid(child)) {
670 printf("No child node for <queue-group>?\n");
675 priv->regs = map_physmem(pdata->iobase, 0, MAP_NOCACHE);
677 ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
680 ofnode_read_u32(phandle_args.node, "reg", &tbiaddr);
682 parent = ofnode_get_parent(phandle_args.node);
683 if (!ofnode_valid(parent)) {
684 printf("No parent node for TBI PHY?\n");
688 reg = ofnode_get_addr_index(parent, 0);
689 if (reg == FDT_ADDR_T_NONE) {
690 printf("No 'reg' property of MII for TBI PHY\n");
694 priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off,
698 priv->tbiaddr = tbiaddr;
700 pdata->phy_interface = dev_read_phy_mode(dev);
701 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
702 pdata->phy_interface = tsec_get_interface(priv);
704 priv->interface = pdata->phy_interface;
706 /* Check for speed limit, default is 1000Mbps */
707 max_speed = dev_read_u32_default(dev, "max-speed", 1000);
709 /* Initialize flags */
710 if (max_speed == 1000)
711 priv->flags = TSEC_GIGABIT;
712 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
713 priv->flags |= TSEC_SGMII;
716 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
717 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
718 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
721 priv->bus = miiphy_get_dev_by_name(dev->name);
723 /* Try to initialize PHY here, and return */
724 return !init_phy(priv);
727 int tsec_remove(struct udevice *dev)
729 struct tsec_private *priv = dev_get_priv(dev);
732 mdio_unregister(priv->bus);
733 mdio_free(priv->bus);
738 static const struct eth_ops tsec_ops = {
742 .free_pkt = tsec_free_pkt,
744 .mcast = tsec_mcast_addr,
745 .set_promisc = tsec_set_promisc,
748 static struct tsec_data etsec2_data = {
749 .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
752 static struct tsec_data gianfar_data = {
753 .mdio_regs_off = 0x0,
756 static const struct udevice_id tsec_ids[] = {
757 { .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data },
758 { .compatible = "gianfar", .data = (ulong)&gianfar_data },
762 U_BOOT_DRIVER(eth_tsec) = {
765 .of_match = tsec_ids,
767 .remove = tsec_remove,
769 .priv_auto = sizeof(struct tsec_private),
770 .plat_auto = sizeof(struct eth_pdata),
771 .flags = DM_FLAG_ALLOC_PRIV_DMA,