1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale Three Speed Ethernet Controller driver
5 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
6 * (C) Copyright 2003, Motorola, Inc.
18 #include <linux/bitops.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
22 #include <asm/processor.h>
26 /* Default initializations for TSEC controllers. */
28 static struct tsec_info_struct tsec_info[] = {
30 STD_TSEC_INFO(1), /* TSEC1 */
33 STD_TSEC_INFO(2), /* TSEC2 */
35 #ifdef CONFIG_MPC85XX_FEC
37 .regs = TSEC_GET_REGS(2, 0x2000),
38 .devname = CONFIG_MPC85XX_FEC_NAME,
39 .phyaddr = FEC_PHY_ADDR,
41 .mii_devname = DEFAULT_MII_NAME
45 STD_TSEC_INFO(3), /* TSEC3 */
48 STD_TSEC_INFO(4), /* TSEC4 */
51 #endif /* CONFIG_DM_ETH */
53 #define TBIANA_SETTINGS ( \
54 TBIANA_ASYMMETRIC_PAUSE \
55 | TBIANA_SYMMETRIC_PAUSE \
56 | TBIANA_FULL_DUPLEX \
59 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
60 #ifndef CONFIG_TSEC_TBICR_SETTINGS
61 #define CONFIG_TSEC_TBICR_SETTINGS ( \
67 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
69 /* Configure the TBI for SGMII operation */
70 static void tsec_configure_serdes(struct tsec_private *priv)
73 * Access TBI PHY registers at given TSEC register offset as opposed
74 * to the register offset used for external PHY accesses
76 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
77 0, TBI_ANA, TBIANA_SETTINGS);
78 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
79 0, TBI_TBICON, TBICON_CLK_SELECT);
80 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
81 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
84 /* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
85 * and this is the ethernet-crc method needed for TSEC -- and perhaps
86 * some other adapter -- hash tables
88 #define CRCPOLY_LE 0xedb88320
89 static u32 ether_crc(size_t len, unsigned char const *p)
97 for (i = 0; i < 8; i++)
98 crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
100 /* an reverse the bits, cuz of way they arrive -- last-first */
101 crc = (crc >> 16) | (crc << 16);
102 crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
103 crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
104 crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
105 crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
109 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
111 /* Set the appropriate hash bit for the given addr */
114 * The algorithm works like so:
115 * 1) Take the Destination Address (ie the multicast address), and
116 * do a CRC on it (little endian), and reverse the bits of the
118 * 2) Use the 8 most significant bits as a hash into a 256-entry
119 * table. The table is controlled through 8 32-bit registers:
120 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
121 * 255. This means that the 3 most significant bits in the
122 * hash index which gaddr register to use, and the 5 other bits
123 * indicate which bit (assuming an IBM numbering scheme, which
124 * for PowerPC (tm) is usually the case) in the register holds
127 #ifndef CONFIG_DM_ETH
128 static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac,
131 static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
134 struct tsec_private *priv;
135 struct tsec __iomem *regs;
137 u8 whichbit, whichreg;
139 #ifndef CONFIG_DM_ETH
140 priv = (struct tsec_private *)dev->priv;
142 priv = dev_get_priv(dev);
145 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
146 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
147 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
149 value = BIT(31 - whichbit);
152 setbits_be32(®s->hash.gaddr0 + whichreg, value);
154 clrbits_be32(®s->hash.gaddr0 + whichreg, value);
159 static int tsec_set_promisc(struct udevice *dev, bool enable)
161 struct tsec_private *priv = dev_get_priv(dev);
162 struct tsec __iomem *regs = priv->regs;
165 setbits_be32(®s->rctrl, RCTRL_PROM);
167 clrbits_be32(®s->rctrl, RCTRL_PROM);
173 * Initialized required registers to appropriate values, zeroing
174 * those we don't care about (unless zero is bad, in which case,
175 * choose a more appropriate value)
177 static void init_registers(struct tsec __iomem *regs)
180 out_be32(®s->ievent, IEVENT_INIT_CLEAR);
182 out_be32(®s->imask, IMASK_INIT_CLEAR);
184 out_be32(®s->hash.iaddr0, 0);
185 out_be32(®s->hash.iaddr1, 0);
186 out_be32(®s->hash.iaddr2, 0);
187 out_be32(®s->hash.iaddr3, 0);
188 out_be32(®s->hash.iaddr4, 0);
189 out_be32(®s->hash.iaddr5, 0);
190 out_be32(®s->hash.iaddr6, 0);
191 out_be32(®s->hash.iaddr7, 0);
193 out_be32(®s->hash.gaddr0, 0);
194 out_be32(®s->hash.gaddr1, 0);
195 out_be32(®s->hash.gaddr2, 0);
196 out_be32(®s->hash.gaddr3, 0);
197 out_be32(®s->hash.gaddr4, 0);
198 out_be32(®s->hash.gaddr5, 0);
199 out_be32(®s->hash.gaddr6, 0);
200 out_be32(®s->hash.gaddr7, 0);
202 /* Init RMON mib registers */
203 memset((void *)®s->rmon, 0, sizeof(regs->rmon));
205 out_be32(®s->rmon.cam1, 0xffffffff);
206 out_be32(®s->rmon.cam2, 0xffffffff);
208 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
210 out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
212 out_be32(®s->attr, ATTR_INIT_SETTINGS);
213 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
217 * Configure maccfg2 based on negotiated speed and duplex
218 * reported by PHY handling code
220 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
222 struct tsec __iomem *regs = priv->regs;
226 printf("%s: No link.\n", phydev->dev->name);
230 /* clear all bits relative with interface mode */
231 ecntrl = in_be32(®s->ecntrl);
232 ecntrl &= ~ECNTRL_R100;
234 maccfg2 = in_be32(®s->maccfg2);
235 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
238 maccfg2 |= MACCFG2_FULL_DUPLEX;
240 switch (phydev->speed) {
242 maccfg2 |= MACCFG2_GMII;
246 maccfg2 |= MACCFG2_MII;
249 * Set R100 bit in all modes although
250 * it is only used in RGMII mode
252 if (phydev->speed == 100)
253 ecntrl |= ECNTRL_R100;
256 printf("%s: Speed was bad\n", phydev->dev->name);
260 out_be32(®s->ecntrl, ecntrl);
261 out_be32(®s->maccfg2, maccfg2);
263 printf("Speed: %d, %s duplex%s\n", phydev->speed,
264 (phydev->duplex) ? "full" : "half",
265 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
269 * This returns the status bits of the device. The return value
270 * is never checked, and this is what the 8260 driver did, so we
271 * do the same. Presumably, this would be zero if there were no
274 #ifndef CONFIG_DM_ETH
275 static int tsec_send(struct eth_device *dev, void *packet, int length)
277 static int tsec_send(struct udevice *dev, void *packet, int length)
280 struct tsec_private *priv;
281 struct tsec __iomem *regs;
286 #ifndef CONFIG_DM_ETH
287 priv = (struct tsec_private *)dev->priv;
289 priv = dev_get_priv(dev);
292 /* Find an empty buffer descriptor */
294 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
296 if (i >= TOUT_LOOP) {
297 printf("%s: tsec: tx buffers full\n", dev->name);
302 out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
303 out_be16(&priv->txbd[priv->tx_idx].length, length);
304 status = in_be16(&priv->txbd[priv->tx_idx].status);
305 out_be16(&priv->txbd[priv->tx_idx].status, status |
306 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
308 /* Tell the DMA to go */
309 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
311 /* Wait for buffer to be transmitted */
313 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
315 if (i >= TOUT_LOOP) {
316 printf("%s: tsec: tx error\n", dev->name);
321 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
322 result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
327 #ifndef CONFIG_DM_ETH
328 static int tsec_recv(struct eth_device *dev)
330 struct tsec_private *priv = (struct tsec_private *)dev->priv;
331 struct tsec __iomem *regs = priv->regs;
333 while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
334 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
335 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
336 uchar *packet = net_rx_packets[priv->rx_idx];
338 /* Send the packet up if there were no errors */
339 if (!(status & RXBD_STATS))
340 net_process_received_packet(packet, length - 4);
342 printf("Got error %x\n", (status & RXBD_STATS));
344 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
347 /* Set the wrap bit if this is the last element in the list */
348 if ((priv->rx_idx + 1) == PKTBUFSRX)
350 out_be16(&priv->rxbd[priv->rx_idx].status, status);
352 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
355 if (in_be32(®s->ievent) & IEVENT_BSY) {
356 out_be32(®s->ievent, IEVENT_BSY);
357 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
363 static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
365 struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
366 struct tsec __iomem *regs = priv->regs;
369 if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
370 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
371 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
374 /* Send the packet up if there were no errors */
375 if (!(status & RXBD_STATS)) {
376 buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
377 *packetp = (uchar *)buf;
380 printf("Got error %x\n", (status & RXBD_STATS));
384 if (in_be32(®s->ievent) & IEVENT_BSY) {
385 out_be32(®s->ievent, IEVENT_BSY);
386 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
392 static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
394 struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
397 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
400 /* Set the wrap bit if this is the last element in the list */
401 if ((priv->rx_idx + 1) == PKTBUFSRX)
403 out_be16(&priv->rxbd[priv->rx_idx].status, status);
405 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
411 /* Stop the interface */
412 #ifndef CONFIG_DM_ETH
413 static void tsec_halt(struct eth_device *dev)
415 static void tsec_halt(struct udevice *dev)
418 struct tsec_private *priv;
419 struct tsec __iomem *regs;
420 #ifndef CONFIG_DM_ETH
421 priv = (struct tsec_private *)dev->priv;
423 priv = dev_get_priv(dev);
427 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
428 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
430 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
431 != (IEVENT_GRSC | IEVENT_GTSC))
434 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
436 /* Shut down the PHY, as needed */
437 phy_shutdown(priv->phydev);
440 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
442 * When MACCFG1[Rx_EN] is enabled during system boot as part
443 * of the eTSEC port initialization sequence,
444 * the eTSEC Rx logic may not be properly initialized.
446 void redundant_init(struct tsec_private *priv)
448 struct tsec __iomem *regs = priv->regs;
451 static const u8 pkt[] = {
452 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
453 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
454 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
455 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
456 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
457 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
458 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
459 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
460 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
461 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
462 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
463 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
464 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
467 /* Enable promiscuous mode */
468 setbits_be32(®s->rctrl, RCTRL_PROM);
469 /* Enable loopback mode */
470 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
471 /* Enable transmit and receive */
472 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
474 /* Tell the DMA it is clear to go */
475 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
476 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
477 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
478 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
483 tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
485 /* Wait for buffer to be received */
487 in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
489 if (t >= 10 * TOUT_LOOP) {
490 printf("%s: tsec: rx error\n", priv->dev->name);
495 if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
498 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
500 if ((priv->rx_idx + 1) == PKTBUFSRX)
502 out_be16(&priv->rxbd[priv->rx_idx].status, status);
503 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
505 if (in_be32(®s->ievent) & IEVENT_BSY) {
506 out_be32(®s->ievent, IEVENT_BSY);
507 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
510 printf("loopback recv packet error!\n");
511 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
513 setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
515 } while ((count++ < 4) && (fail == 1));
518 panic("eTSEC init fail!\n");
519 /* Disable promiscuous mode */
520 clrbits_be32(®s->rctrl, RCTRL_PROM);
521 /* Disable loopback mode */
522 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
527 * Set up the buffers and their descriptors, and bring up the
530 static void startup_tsec(struct tsec_private *priv)
532 struct tsec __iomem *regs = priv->regs;
536 /* reset the indices to zero */
539 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
543 /* Point to the buffer descriptors */
544 out_be32(®s->tbase, (u32)&priv->txbd[0]);
545 out_be32(®s->rbase, (u32)&priv->rxbd[0]);
547 /* Initialize the Rx Buffer descriptors */
548 for (i = 0; i < PKTBUFSRX; i++) {
549 out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
550 out_be16(&priv->rxbd[i].length, 0);
551 out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
553 status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
554 out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
556 /* Initialize the TX Buffer Descriptors */
557 for (i = 0; i < TX_BUF_CNT; i++) {
558 out_be16(&priv->txbd[i].status, 0);
559 out_be16(&priv->txbd[i].length, 0);
560 out_be32(&priv->txbd[i].bufptr, 0);
562 status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
563 out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
565 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
567 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
568 redundant_init(priv);
570 /* Enable Transmit and Receive */
571 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
573 /* Tell the DMA it is clear to go */
574 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
575 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
576 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
577 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
581 * Initializes data structures and registers for the controller,
582 * and brings the interface up. Returns the link status, meaning
583 * that it returns success if the link is up, failure otherwise.
584 * This allows U-Boot to find the first active controller.
586 #ifndef CONFIG_DM_ETH
587 static int tsec_init(struct eth_device *dev, struct bd_info *bd)
589 static int tsec_init(struct udevice *dev)
592 struct tsec_private *priv;
593 struct tsec __iomem *regs;
595 struct eth_pdata *pdata = dev_get_plat(dev);
597 struct eth_device *pdata = dev;
602 #ifndef CONFIG_DM_ETH
603 priv = (struct tsec_private *)dev->priv;
605 priv = dev_get_priv(dev);
608 /* Make sure the controller is stopped */
611 /* Init MACCFG2. Defaults to GMII */
612 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
615 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
618 * Copy the station address into the address registers.
619 * For a station address of 0x12345678ABCD in transmission
620 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
621 * MACnADDR2 is set to 0x34120000.
623 tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
624 (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
626 out_be32(®s->macstnaddr1, tempval);
628 tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
630 out_be32(®s->macstnaddr2, tempval);
632 /* Clear out (for the most part) the other registers */
633 init_registers(regs);
635 /* Ready the device for tx/rx */
638 /* Start up the PHY */
639 ret = phy_startup(priv->phydev);
641 printf("Could not initialize PHY %s\n",
642 priv->phydev->dev->name);
646 adjust_link(priv, priv->phydev);
648 /* If there's no link, fail */
649 return priv->phydev->link ? 0 : -1;
652 static phy_interface_t __maybe_unused tsec_get_interface(struct tsec_private *priv)
654 struct tsec __iomem *regs = priv->regs;
657 ecntrl = in_be32(®s->ecntrl);
659 if (ecntrl & ECNTRL_SGMII_MODE)
660 return PHY_INTERFACE_MODE_SGMII;
662 if (ecntrl & ECNTRL_TBI_MODE) {
663 if (ecntrl & ECNTRL_REDUCED_MODE)
664 return PHY_INTERFACE_MODE_RTBI;
666 return PHY_INTERFACE_MODE_TBI;
669 if (ecntrl & ECNTRL_REDUCED_MODE) {
670 phy_interface_t interface;
672 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
673 return PHY_INTERFACE_MODE_RMII;
675 interface = priv->interface;
678 * This isn't autodetected, so it must
679 * be set by the platform code.
681 if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
682 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
683 interface == PHY_INTERFACE_MODE_RGMII_RXID)
686 return PHY_INTERFACE_MODE_RGMII;
689 if (priv->flags & TSEC_GIGABIT)
690 return PHY_INTERFACE_MODE_GMII;
692 return PHY_INTERFACE_MODE_MII;
696 * Discover which PHY is attached to the device, and configure it
697 * properly. If the PHY is not recognized, then return 0
698 * (failure). Otherwise, return 1
700 static int init_phy(struct tsec_private *priv)
702 struct phy_device *phydev;
703 struct tsec __iomem *regs = priv->regs;
704 u32 supported = (SUPPORTED_10baseT_Half |
705 SUPPORTED_10baseT_Full |
706 SUPPORTED_100baseT_Half |
707 SUPPORTED_100baseT_Full);
709 if (priv->flags & TSEC_GIGABIT)
710 supported |= SUPPORTED_1000baseT_Full;
712 /* Assign a Physical address to the TBI */
713 out_be32(®s->tbipa, priv->tbiaddr);
715 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
716 tsec_configure_serdes(priv);
718 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_MDIO)
719 phydev = dm_eth_phy_connect(priv->dev);
721 phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
727 phydev->supported &= supported;
728 phydev->advertising = phydev->supported;
730 priv->phydev = phydev;
737 #ifndef CONFIG_DM_ETH
739 * Initialize device structure. Returns success if PHY
740 * initialization succeeded (i.e. if it recognizes the PHY)
742 static int tsec_initialize(struct bd_info *bis,
743 struct tsec_info_struct *tsec_info)
745 struct tsec_private *priv;
746 struct eth_device *dev;
749 dev = (struct eth_device *)malloc(sizeof(*dev));
754 memset(dev, 0, sizeof(*dev));
756 priv = (struct tsec_private *)malloc(sizeof(*priv));
763 priv->regs = tsec_info->regs;
764 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
766 priv->phyaddr = tsec_info->phyaddr;
767 priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
768 priv->flags = tsec_info->flags;
770 strcpy(dev->name, tsec_info->devname);
771 priv->interface = tsec_info->interface;
772 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
776 dev->init = tsec_init;
777 dev->halt = tsec_halt;
778 dev->send = tsec_send;
779 dev->recv = tsec_recv;
780 dev->mcast = tsec_mcast_addr;
782 /* Tell U-Boot to get the addr from the env */
783 for (i = 0; i < 6; i++)
784 dev->enetaddr[i] = 0;
789 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
790 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
791 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
793 /* Try to initialize PHY here, and return */
794 return init_phy(priv);
798 * Initialize all the TSEC devices
800 * Returns the number of TSEC devices that were initialized
802 int tsec_eth_init(struct bd_info *bis, struct tsec_info_struct *tsecs,
808 for (i = 0; i < num; i++) {
809 int ret = tsec_initialize(bis, &tsecs[i]);
818 int tsec_standard_init(struct bd_info *bis)
820 struct fsl_pq_mdio_info info;
822 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
823 info.name = DEFAULT_MII_NAME;
825 fsl_pq_mdio_init(bis, &info);
827 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
829 #else /* CONFIG_DM_ETH */
830 int tsec_probe(struct udevice *dev)
832 struct eth_pdata *pdata = dev_get_plat(dev);
833 struct tsec_private *priv = dev_get_priv(dev);
834 struct ofnode_phandle_args phandle_args;
835 u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
836 struct tsec_data *data;
837 const char *phy_mode;
838 ofnode parent, child;
843 data = (struct tsec_data *)dev_get_driver_data(dev);
845 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
846 if (pdata->iobase == FDT_ADDR_T_NONE) {
847 ofnode_for_each_subnode(child, dev_ofnode(dev)) {
848 if (strncmp(ofnode_get_name(child), "queue-group",
849 strlen("queue-group")))
852 reg = ofnode_get_addr(child);
853 if (reg == FDT_ADDR_T_NONE) {
854 printf("No 'reg' property of <queue-group>\n");
860 * if there are multiple queue groups,
861 * only the first one is used.
866 if (!ofnode_valid(child)) {
867 printf("No child node for <queue-group>?\n");
872 priv->regs = map_physmem(pdata->iobase, 0, MAP_NOCACHE);
874 ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
877 ofnode_read_u32(phandle_args.node, "reg", &tbiaddr);
879 parent = ofnode_get_parent(phandle_args.node);
880 if (!ofnode_valid(parent)) {
881 printf("No parent node for TBI PHY?\n");
885 reg = ofnode_get_addr_index(parent, 0);
886 if (reg == FDT_ADDR_T_NONE) {
887 printf("No 'reg' property of MII for TBI PHY\n");
891 priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off,
895 priv->tbiaddr = tbiaddr;
897 phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
899 phy_mode = dev_read_prop(dev, "phy-mode", NULL);
901 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
902 if (pdata->phy_interface == -1)
903 pdata->phy_interface = tsec_get_interface(priv);
905 priv->interface = pdata->phy_interface;
907 /* Check for speed limit, default is 1000Mbps */
908 max_speed = dev_read_u32_default(dev, "max-speed", 1000);
910 /* Initialize flags */
911 if (max_speed == 1000)
912 priv->flags = TSEC_GIGABIT;
913 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
914 priv->flags |= TSEC_SGMII;
917 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
918 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
919 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
922 priv->bus = miiphy_get_dev_by_name(dev->name);
924 /* Try to initialize PHY here, and return */
925 return !init_phy(priv);
928 int tsec_remove(struct udevice *dev)
930 struct tsec_private *priv = dev_get_priv(dev);
933 mdio_unregister(priv->bus);
934 mdio_free(priv->bus);
939 static const struct eth_ops tsec_ops = {
943 .free_pkt = tsec_free_pkt,
945 .mcast = tsec_mcast_addr,
946 .set_promisc = tsec_set_promisc,
949 static struct tsec_data etsec2_data = {
950 .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
953 static struct tsec_data gianfar_data = {
954 .mdio_regs_off = 0x0,
957 static const struct udevice_id tsec_ids[] = {
958 { .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data },
959 { .compatible = "gianfar", .data = (ulong)&gianfar_data },
963 U_BOOT_DRIVER(eth_tsec) = {
966 .of_match = tsec_ids,
968 .remove = tsec_remove,
970 .priv_auto = sizeof(struct tsec_private),
971 .plat_auto = sizeof(struct eth_pdata),
972 .flags = DM_FLAG_ALLOC_PRIV_DMA,
974 #endif /* CONFIG_DM_ETH */