1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale Three Speed Ethernet Controller driver
5 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
6 * (C) Copyright 2003, Motorola, Inc.
18 #include <linux/errno.h>
19 #include <asm/processor.h>
23 /* Default initializations for TSEC controllers. */
25 static struct tsec_info_struct tsec_info[] = {
27 STD_TSEC_INFO(1), /* TSEC1 */
30 STD_TSEC_INFO(2), /* TSEC2 */
32 #ifdef CONFIG_MPC85XX_FEC
34 .regs = TSEC_GET_REGS(2, 0x2000),
35 .devname = CONFIG_MPC85XX_FEC_NAME,
36 .phyaddr = FEC_PHY_ADDR,
38 .mii_devname = DEFAULT_MII_NAME
42 STD_TSEC_INFO(3), /* TSEC3 */
45 STD_TSEC_INFO(4), /* TSEC4 */
48 #endif /* CONFIG_DM_ETH */
50 #define TBIANA_SETTINGS ( \
51 TBIANA_ASYMMETRIC_PAUSE \
52 | TBIANA_SYMMETRIC_PAUSE \
53 | TBIANA_FULL_DUPLEX \
56 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
57 #ifndef CONFIG_TSEC_TBICR_SETTINGS
58 #define CONFIG_TSEC_TBICR_SETTINGS ( \
64 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
66 /* Configure the TBI for SGMII operation */
67 static void tsec_configure_serdes(struct tsec_private *priv)
70 * Access TBI PHY registers at given TSEC register offset as opposed
71 * to the register offset used for external PHY accesses
73 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
74 0, TBI_ANA, TBIANA_SETTINGS);
75 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
76 0, TBI_TBICON, TBICON_CLK_SELECT);
77 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
78 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
81 #ifdef CONFIG_MCAST_TFTP
83 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
85 /* Set the appropriate hash bit for the given addr */
88 * The algorithm works like so:
89 * 1) Take the Destination Address (ie the multicast address), and
90 * do a CRC on it (little endian), and reverse the bits of the
92 * 2) Use the 8 most significant bits as a hash into a 256-entry
93 * table. The table is controlled through 8 32-bit registers:
94 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
95 * 255. This means that the 3 most significant bits in the
96 * hash index which gaddr register to use, and the 5 other bits
97 * indicate which bit (assuming an IBM numbering scheme, which
98 * for PowerPC (tm) is usually the case) in the register holds
101 #ifndef CONFIG_DM_ETH
102 static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
104 static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int set)
107 struct tsec_private *priv = (struct tsec_private *)dev->priv;
108 struct tsec __iomem *regs = priv->regs;
110 u8 whichbit, whichreg;
112 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
113 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
114 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
116 value = BIT(31 - whichbit);
119 setbits_be32(®s->hash.gaddr0 + whichreg, value);
121 clrbits_be32(®s->hash.gaddr0 + whichreg, value);
125 #endif /* Multicast TFTP ? */
128 * Initialized required registers to appropriate values, zeroing
129 * those we don't care about (unless zero is bad, in which case,
130 * choose a more appropriate value)
132 static void init_registers(struct tsec __iomem *regs)
135 out_be32(®s->ievent, IEVENT_INIT_CLEAR);
137 out_be32(®s->imask, IMASK_INIT_CLEAR);
139 out_be32(®s->hash.iaddr0, 0);
140 out_be32(®s->hash.iaddr1, 0);
141 out_be32(®s->hash.iaddr2, 0);
142 out_be32(®s->hash.iaddr3, 0);
143 out_be32(®s->hash.iaddr4, 0);
144 out_be32(®s->hash.iaddr5, 0);
145 out_be32(®s->hash.iaddr6, 0);
146 out_be32(®s->hash.iaddr7, 0);
148 out_be32(®s->hash.gaddr0, 0);
149 out_be32(®s->hash.gaddr1, 0);
150 out_be32(®s->hash.gaddr2, 0);
151 out_be32(®s->hash.gaddr3, 0);
152 out_be32(®s->hash.gaddr4, 0);
153 out_be32(®s->hash.gaddr5, 0);
154 out_be32(®s->hash.gaddr6, 0);
155 out_be32(®s->hash.gaddr7, 0);
157 out_be32(®s->rctrl, 0x00000000);
159 /* Init RMON mib registers */
160 memset((void *)®s->rmon, 0, sizeof(regs->rmon));
162 out_be32(®s->rmon.cam1, 0xffffffff);
163 out_be32(®s->rmon.cam2, 0xffffffff);
165 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
167 out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
169 out_be32(®s->attr, ATTR_INIT_SETTINGS);
170 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
174 * Configure maccfg2 based on negotiated speed and duplex
175 * reported by PHY handling code
177 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
179 struct tsec __iomem *regs = priv->regs;
183 printf("%s: No link.\n", phydev->dev->name);
187 /* clear all bits relative with interface mode */
188 ecntrl = in_be32(®s->ecntrl);
189 ecntrl &= ~ECNTRL_R100;
191 maccfg2 = in_be32(®s->maccfg2);
192 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
195 maccfg2 |= MACCFG2_FULL_DUPLEX;
197 switch (phydev->speed) {
199 maccfg2 |= MACCFG2_GMII;
203 maccfg2 |= MACCFG2_MII;
206 * Set R100 bit in all modes although
207 * it is only used in RGMII mode
209 if (phydev->speed == 100)
210 ecntrl |= ECNTRL_R100;
213 printf("%s: Speed was bad\n", phydev->dev->name);
217 out_be32(®s->ecntrl, ecntrl);
218 out_be32(®s->maccfg2, maccfg2);
220 printf("Speed: %d, %s duplex%s\n", phydev->speed,
221 (phydev->duplex) ? "full" : "half",
222 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
226 * This returns the status bits of the device. The return value
227 * is never checked, and this is what the 8260 driver did, so we
228 * do the same. Presumably, this would be zero if there were no
231 #ifndef CONFIG_DM_ETH
232 static int tsec_send(struct eth_device *dev, void *packet, int length)
234 static int tsec_send(struct udevice *dev, void *packet, int length)
237 struct tsec_private *priv = (struct tsec_private *)dev->priv;
238 struct tsec __iomem *regs = priv->regs;
243 /* Find an empty buffer descriptor */
245 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
247 if (i >= TOUT_LOOP) {
248 debug("%s: tsec: tx buffers full\n", dev->name);
253 out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
254 out_be16(&priv->txbd[priv->tx_idx].length, length);
255 status = in_be16(&priv->txbd[priv->tx_idx].status);
256 out_be16(&priv->txbd[priv->tx_idx].status, status |
257 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
259 /* Tell the DMA to go */
260 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
262 /* Wait for buffer to be transmitted */
264 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
266 if (i >= TOUT_LOOP) {
267 debug("%s: tsec: tx error\n", dev->name);
272 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
273 result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
278 #ifndef CONFIG_DM_ETH
279 static int tsec_recv(struct eth_device *dev)
281 struct tsec_private *priv = (struct tsec_private *)dev->priv;
282 struct tsec __iomem *regs = priv->regs;
284 while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
285 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
286 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
287 uchar *packet = net_rx_packets[priv->rx_idx];
289 /* Send the packet up if there were no errors */
290 if (!(status & RXBD_STATS))
291 net_process_received_packet(packet, length - 4);
293 printf("Got error %x\n", (status & RXBD_STATS));
295 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
298 /* Set the wrap bit if this is the last element in the list */
299 if ((priv->rx_idx + 1) == PKTBUFSRX)
301 out_be16(&priv->rxbd[priv->rx_idx].status, status);
303 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
306 if (in_be32(®s->ievent) & IEVENT_BSY) {
307 out_be32(®s->ievent, IEVENT_BSY);
308 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
314 static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
316 struct tsec_private *priv = (struct tsec_private *)dev->priv;
317 struct tsec __iomem *regs = priv->regs;
320 if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
321 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
322 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
325 /* Send the packet up if there were no errors */
326 if (!(status & RXBD_STATS)) {
327 buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
328 *packetp = (uchar *)buf;
331 printf("Got error %x\n", (status & RXBD_STATS));
335 if (in_be32(®s->ievent) & IEVENT_BSY) {
336 out_be32(®s->ievent, IEVENT_BSY);
337 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
343 static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
345 struct tsec_private *priv = (struct tsec_private *)dev->priv;
348 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
351 /* Set the wrap bit if this is the last element in the list */
352 if ((priv->rx_idx + 1) == PKTBUFSRX)
354 out_be16(&priv->rxbd[priv->rx_idx].status, status);
356 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
362 /* Stop the interface */
363 #ifndef CONFIG_DM_ETH
364 static void tsec_halt(struct eth_device *dev)
366 static void tsec_halt(struct udevice *dev)
369 struct tsec_private *priv = (struct tsec_private *)dev->priv;
370 struct tsec __iomem *regs = priv->regs;
372 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
373 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
375 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
376 != (IEVENT_GRSC | IEVENT_GTSC))
379 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
381 /* Shut down the PHY, as needed */
382 phy_shutdown(priv->phydev);
385 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
387 * When MACCFG1[Rx_EN] is enabled during system boot as part
388 * of the eTSEC port initialization sequence,
389 * the eTSEC Rx logic may not be properly initialized.
391 void redundant_init(struct tsec_private *priv)
393 struct tsec __iomem *regs = priv->regs;
396 static const u8 pkt[] = {
397 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
398 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
399 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
400 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
401 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
402 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
403 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
404 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
405 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
406 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
407 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
408 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
409 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
412 /* Enable promiscuous mode */
413 setbits_be32(®s->rctrl, 0x8);
414 /* Enable loopback mode */
415 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
416 /* Enable transmit and receive */
417 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
419 /* Tell the DMA it is clear to go */
420 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
421 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
422 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
423 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
428 tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
430 /* Wait for buffer to be received */
432 in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
434 if (t >= 10 * TOUT_LOOP) {
435 printf("%s: tsec: rx error\n", priv->dev->name);
440 if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
443 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
445 if ((priv->rx_idx + 1) == PKTBUFSRX)
447 out_be16(&priv->rxbd[priv->rx_idx].status, status);
448 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
450 if (in_be32(®s->ievent) & IEVENT_BSY) {
451 out_be32(®s->ievent, IEVENT_BSY);
452 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
455 printf("loopback recv packet error!\n");
456 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
458 setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
460 } while ((count++ < 4) && (fail == 1));
463 panic("eTSEC init fail!\n");
464 /* Disable promiscuous mode */
465 clrbits_be32(®s->rctrl, 0x8);
466 /* Disable loopback mode */
467 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
472 * Set up the buffers and their descriptors, and bring up the
475 static void startup_tsec(struct tsec_private *priv)
477 struct tsec __iomem *regs = priv->regs;
481 /* reset the indices to zero */
484 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
488 /* Point to the buffer descriptors */
489 out_be32(®s->tbase, (u32)&priv->txbd[0]);
490 out_be32(®s->rbase, (u32)&priv->rxbd[0]);
492 /* Initialize the Rx Buffer descriptors */
493 for (i = 0; i < PKTBUFSRX; i++) {
494 out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
495 out_be16(&priv->rxbd[i].length, 0);
496 out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
498 status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
499 out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
501 /* Initialize the TX Buffer Descriptors */
502 for (i = 0; i < TX_BUF_CNT; i++) {
503 out_be16(&priv->txbd[i].status, 0);
504 out_be16(&priv->txbd[i].length, 0);
505 out_be32(&priv->txbd[i].bufptr, 0);
507 status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
508 out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
510 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
512 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
513 redundant_init(priv);
515 /* Enable Transmit and Receive */
516 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
518 /* Tell the DMA it is clear to go */
519 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
520 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
521 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
522 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
526 * Initializes data structures and registers for the controller,
527 * and brings the interface up. Returns the link status, meaning
528 * that it returns success if the link is up, failure otherwise.
529 * This allows U-Boot to find the first active controller.
531 #ifndef CONFIG_DM_ETH
532 static int tsec_init(struct eth_device *dev, bd_t *bd)
534 static int tsec_init(struct udevice *dev)
537 struct tsec_private *priv = (struct tsec_private *)dev->priv;
539 struct eth_pdata *pdata = dev_get_platdata(dev);
541 struct tsec __iomem *regs = priv->regs;
545 /* Make sure the controller is stopped */
548 /* Init MACCFG2. Defaults to GMII */
549 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
552 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
555 * Copy the station address into the address registers.
556 * For a station address of 0x12345678ABCD in transmission
557 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
558 * MACnADDR2 is set to 0x34120000.
560 #ifndef CONFIG_DM_ETH
561 tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
562 (dev->enetaddr[3] << 8) | dev->enetaddr[2];
564 tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
565 (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
568 out_be32(®s->macstnaddr1, tempval);
570 #ifndef CONFIG_DM_ETH
571 tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
573 tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
576 out_be32(®s->macstnaddr2, tempval);
578 /* Clear out (for the most part) the other registers */
579 init_registers(regs);
581 /* Ready the device for tx/rx */
584 /* Start up the PHY */
585 ret = phy_startup(priv->phydev);
587 printf("Could not initialize PHY %s\n",
588 priv->phydev->dev->name);
592 adjust_link(priv, priv->phydev);
594 /* If there's no link, fail */
595 return priv->phydev->link ? 0 : -1;
598 static phy_interface_t tsec_get_interface(struct tsec_private *priv)
600 struct tsec __iomem *regs = priv->regs;
603 ecntrl = in_be32(®s->ecntrl);
605 if (ecntrl & ECNTRL_SGMII_MODE)
606 return PHY_INTERFACE_MODE_SGMII;
608 if (ecntrl & ECNTRL_TBI_MODE) {
609 if (ecntrl & ECNTRL_REDUCED_MODE)
610 return PHY_INTERFACE_MODE_RTBI;
612 return PHY_INTERFACE_MODE_TBI;
615 if (ecntrl & ECNTRL_REDUCED_MODE) {
616 phy_interface_t interface;
618 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
619 return PHY_INTERFACE_MODE_RMII;
621 interface = priv->interface;
624 * This isn't autodetected, so it must
625 * be set by the platform code.
627 if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
628 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
629 interface == PHY_INTERFACE_MODE_RGMII_RXID)
632 return PHY_INTERFACE_MODE_RGMII;
635 if (priv->flags & TSEC_GIGABIT)
636 return PHY_INTERFACE_MODE_GMII;
638 return PHY_INTERFACE_MODE_MII;
642 * Discover which PHY is attached to the device, and configure it
643 * properly. If the PHY is not recognized, then return 0
644 * (failure). Otherwise, return 1
646 static int init_phy(struct tsec_private *priv)
648 struct phy_device *phydev;
649 struct tsec __iomem *regs = priv->regs;
650 u32 supported = (SUPPORTED_10baseT_Half |
651 SUPPORTED_10baseT_Full |
652 SUPPORTED_100baseT_Half |
653 SUPPORTED_100baseT_Full);
655 if (priv->flags & TSEC_GIGABIT)
656 supported |= SUPPORTED_1000baseT_Full;
658 /* Assign a Physical address to the TBI */
659 out_be32(®s->tbipa, priv->tbiaddr);
661 priv->interface = tsec_get_interface(priv);
663 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
664 tsec_configure_serdes(priv);
666 phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
671 phydev->supported &= supported;
672 phydev->advertising = phydev->supported;
674 priv->phydev = phydev;
681 #ifndef CONFIG_DM_ETH
683 * Initialize device structure. Returns success if PHY
684 * initialization succeeded (i.e. if it recognizes the PHY)
686 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
688 struct eth_device *dev;
690 struct tsec_private *priv;
692 dev = (struct eth_device *)malloc(sizeof(*dev));
697 memset(dev, 0, sizeof(*dev));
699 priv = (struct tsec_private *)malloc(sizeof(*priv));
706 priv->regs = tsec_info->regs;
707 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
709 priv->phyaddr = tsec_info->phyaddr;
710 priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
711 priv->flags = tsec_info->flags;
713 strcpy(dev->name, tsec_info->devname);
714 priv->interface = tsec_info->interface;
715 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
719 dev->init = tsec_init;
720 dev->halt = tsec_halt;
721 dev->send = tsec_send;
722 dev->recv = tsec_recv;
723 #ifdef CONFIG_MCAST_TFTP
724 dev->mcast = tsec_mcast_addr;
727 /* Tell U-Boot to get the addr from the env */
728 for (i = 0; i < 6; i++)
729 dev->enetaddr[i] = 0;
734 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
735 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
736 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
738 /* Try to initialize PHY here, and return */
739 return init_phy(priv);
743 * Initialize all the TSEC devices
745 * Returns the number of TSEC devices that were initialized
747 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
752 for (i = 0; i < num; i++) {
753 int ret = tsec_initialize(bis, &tsecs[i]);
762 int tsec_standard_init(bd_t *bis)
764 struct fsl_pq_mdio_info info;
766 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
767 info.name = DEFAULT_MII_NAME;
769 fsl_pq_mdio_init(bis, &info);
771 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
773 #else /* CONFIG_DM_ETH */
774 int tsec_probe(struct udevice *dev)
776 struct tsec_private *priv = dev_get_priv(dev);
777 struct eth_pdata *pdata = dev_get_platdata(dev);
778 struct fsl_pq_mdio_info mdio_info;
779 struct ofnode_phandle_args phandle_args;
781 const char *phy_mode;
784 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
785 priv->regs = (struct tsec *)pdata->iobase;
787 if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
789 debug("phy-handle does not exist under tsec %s\n", dev->name);
792 int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
797 parent = ofnode_get_parent(phandle_args.node);
798 if (ofnode_valid(parent)) {
799 int reg = ofnode_get_addr_index(parent, 0);
801 priv->phyregs_sgmii = (struct tsec_mii_mng *)reg;
803 debug("No parent node for PHY?\n");
807 if (dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
809 priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
811 int reg = ofnode_read_u32_default(phandle_args.node, "reg",
812 CONFIG_SYS_TBIPA_VALUE);
816 phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
818 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
819 if (pdata->phy_interface == -1) {
820 debug("Invalid PHY interface '%s'\n", phy_mode);
823 priv->interface = pdata->phy_interface;
825 /* Initialize flags */
826 priv->flags = TSEC_GIGABIT;
827 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
828 priv->flags |= TSEC_SGMII;
830 mdio_info.regs = priv->phyregs_sgmii;
831 mdio_info.name = (char *)dev->name;
832 ret = fsl_pq_mdio_init(NULL, &mdio_info);
837 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
838 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
839 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
842 priv->bus = miiphy_get_dev_by_name(dev->name);
844 /* Try to initialize PHY here, and return */
845 return !init_phy(priv);
848 int tsec_remove(struct udevice *dev)
850 struct tsec_private *priv = dev->priv;
853 mdio_unregister(priv->bus);
854 mdio_free(priv->bus);
859 static const struct eth_ops tsec_ops = {
863 .free_pkt = tsec_free_pkt,
865 #ifdef CONFIG_MCAST_TFTP
866 .mcast = tsec_mcast_addr,
870 static const struct udevice_id tsec_ids[] = {
871 { .compatible = "fsl,tsec" },
875 U_BOOT_DRIVER(eth_tsec) = {
878 .of_match = tsec_ids,
880 .remove = tsec_remove,
882 .priv_auto_alloc_size = sizeof(struct tsec_private),
883 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
884 .flags = DM_FLAG_ALLOC_PRIV_DMA,
886 #endif /* CONFIG_DM_ETH */