drivers/net/tsec.c

   1 /*
   2  * Freescale Three Speed Ethernet Controller driver
   3  *
   4  * This software may be used and distributed according to the
   5  * terms of the GNU Public License, Version 2, incorporated
   6  * herein by reference.
   7  *
   8  * Copyright 2004, 2007 Freescale Semiconductor, Inc.
   9  * (C) Copyright 2003, Motorola, Inc.
  10  * author Andy Fleming
  11  *
  12  */
  13
  14 #include <config.h>
  15 #include <common.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <command.h>
  19
  20 #if defined(CONFIG_TSEC_ENET)
  21 #include "tsec.h"
  22 #include "miiphy.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define TX_BUF_CNT              2
  27
  28 static uint rxIdx;              /* index of the current RX buffer */
  29 static uint txIdx;              /* index of the current TX buffer */
  30
  31 typedef volatile struct rtxbd {
  32         txbd8_t txbd[TX_BUF_CNT];
  33         rxbd8_t rxbd[PKTBUFSRX];
  34 } RTXBD;
  35
  36 struct tsec_info_struct {
  37         unsigned int phyaddr;
  38         u32 flags;
  39         unsigned int phyregidx;
  40 };
  41
  42 /* The tsec_info structure contains 3 values which the
  43  * driver uses to determine how to operate a given ethernet
  44  * device. The information needed is:
  45  *  phyaddr - The address of the PHY which is attached to
  46  *      the given device.
  47  *
  48  *  flags - This variable indicates whether the device
  49  *      supports gigabit speed ethernet, and whether it should be
  50  *      in reduced mode.
  51  *
  52  *  phyregidx - This variable specifies which ethernet device
  53  *      controls the MII Management registers which are connected
  54  *      to the PHY.  For now, only TSEC1 (index 0) has
  55  *      access to the PHYs, so all of the entries have "0".
  56  *
  57  * The values specified in the table are taken from the board's
  58  * config file in include/configs/.  When implementing a new
  59  * board with ethernet capability, it is necessary to define:
  60  *   TSECn_PHY_ADDR
  61  *   TSECn_PHYIDX
  62  *
  63  * for n = 1,2,3, etc.  And for FEC:
  64  *   FEC_PHY_ADDR
  65  *   FEC_PHYIDX
  66  */
  67 static struct tsec_info_struct tsec_info[] = {
  68 #ifdef CONFIG_TSEC1
  69         {TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX},
  70 #else
  71         {0, 0, 0},
  72 #endif
  73 #ifdef CONFIG_TSEC2
  74         {TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX},
  75 #else
  76         {0, 0, 0},
  77 #endif
  78 #ifdef CONFIG_MPC85XX_FEC
  79         {FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX},
  80 #else
  81 #ifdef CONFIG_TSEC3
  82         {TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX},
  83 #else
  84         {0, 0, 0},
  85 #endif
  86 #ifdef CONFIG_TSEC4
  87         {TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX},
  88 #else
  89         {0, 0, 0},
  90 #endif  /* CONFIG_TSEC4 */
  91 #endif  /* CONFIG_MPC85XX_FEC */
  92 };
  93
  94 #define MAXCONTROLLERS  (4)
  95
  96 static int relocated = 0;
  97
  98 static struct tsec_private *privlist[MAXCONTROLLERS];
  99
 100 #ifdef __GNUC__
 101 static RTXBD rtx __attribute__ ((aligned(8)));
 102 #else
 103 #error "rtx must be 64-bit aligned"
 104 #endif
 105
 106 static int tsec_send(struct eth_device *dev,
 107                      volatile void *packet, int length);
 108 static int tsec_recv(struct eth_device *dev);
 109 static int tsec_init(struct eth_device *dev, bd_t * bd);
 110 static void tsec_halt(struct eth_device *dev);
 111 static void init_registers(volatile tsec_t * regs);
 112 static void startup_tsec(struct eth_device *dev);
 113 static int init_phy(struct eth_device *dev);
 114 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
 115 uint read_phy_reg(struct tsec_private *priv, uint regnum);
 116 struct phy_info *get_phy_info(struct eth_device *dev);
 117 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
 118 static void adjust_link(struct eth_device *dev);
 119 static void relocate_cmds(void);
 120 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
 121         && !defined(BITBANGMII)
 122 static int tsec_miiphy_write(char *devname, unsigned char addr,
 123                              unsigned char reg, unsigned short value);
 124 static int tsec_miiphy_read(char *devname, unsigned char addr,
 125                             unsigned char reg, unsigned short *value);
 126 #endif
 127 #ifdef CONFIG_MCAST_TFTP
 128 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
 129 #endif
 130
 131 /* Initialize device structure. Returns success if PHY
 132  * initialization succeeded (i.e. if it recognizes the PHY)
 133  */
 134 int tsec_initialize(bd_t * bis, int index, char *devname)
 135 {
 136         struct eth_device *dev;
 137         int i;
 138         struct tsec_private *priv;
 139
 140         dev = (struct eth_device *)malloc(sizeof *dev);
 141
 142         if (NULL == dev)
 143                 return 0;
 144
 145         memset(dev, 0, sizeof *dev);
 146
 147         priv = (struct tsec_private *)malloc(sizeof(*priv));
 148
 149         if (NULL == priv)
 150                 return 0;
 151
 152         privlist[index] = priv;
 153         priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
 154         priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
 155                                             tsec_info[index].phyregidx *
 156                                             TSEC_SIZE);
 157
 158         priv->phyaddr = tsec_info[index].phyaddr;
 159         priv->flags = tsec_info[index].flags;
 160
 161         sprintf(dev->name, devname);
 162         dev->iobase = 0;
 163         dev->priv = priv;
 164         dev->init = tsec_init;
 165         dev->halt = tsec_halt;
 166         dev->send = tsec_send;
 167         dev->recv = tsec_recv;
 168 #ifdef CONFIG_MCAST_TFTP
 169         dev->mcast = tsec_mcast_addr;
 170 #endif
 171
 172         /* Tell u-boot to get the addr from the env */
 173         for (i = 0; i < 6; i++)
 174                 dev->enetaddr[i] = 0;
 175
 176         eth_register(dev);
 177
 178         /* Reset the MAC */
 179         priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
 180         priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
 181
 182 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
 183         && !defined(BITBANGMII)
 184         miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
 185 #endif
 186
 187         /* Try to initialize PHY here, and return */
 188         return init_phy(dev);
 189 }
 190
 191 /* Initializes data structures and registers for the controller,
 192  * and brings the interface up.  Returns the link status, meaning
 193  * that it returns success if the link is up, failure otherwise.
 194  * This allows u-boot to find the first active controller.
 195  */
 196 int tsec_init(struct eth_device *dev, bd_t * bd)
 197 {
 198         uint tempval;
 199         char tmpbuf[MAC_ADDR_LEN];
 200         int i;
 201         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 202         volatile tsec_t *regs = priv->regs;
 203
 204         /* Make sure the controller is stopped */
 205         tsec_halt(dev);
 206
 207         /* Init MACCFG2.  Defaults to GMII */
 208         regs->maccfg2 = MACCFG2_INIT_SETTINGS;
 209
 210         /* Init ECNTRL */
 211         regs->ecntrl = ECNTRL_INIT_SETTINGS;
 212
 213         /* Copy the station address into the address registers.
 214          * Backwards, because little endian MACS are dumb */
 215         for (i = 0; i < MAC_ADDR_LEN; i++) {
 216                 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
 217         }
 218         regs->macstnaddr1 = *((uint *) (tmpbuf));
 219
 220         tempval = *((uint *) (tmpbuf + 4));
 221
 222         regs->macstnaddr2 = tempval;
 223
 224         /* reset the indices to zero */
 225         rxIdx = 0;
 226         txIdx = 0;
 227
 228         /* Clear out (for the most part) the other registers */
 229         init_registers(regs);
 230
 231         /* Ready the device for tx/rx */
 232         startup_tsec(dev);
 233
 234         /* If there's no link, fail */
 235         return (priv->link ? 0 : -1);
 236
 237 }
 238
 239 /* Write value to the device's PHY through the registers
 240  * specified in priv, modifying the register specified in regnum.
 241  * It will wait for the write to be done (or for a timeout to
 242  * expire) before exiting
 243  */
 244 void write_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum, uint value)
 245 {
 246         volatile tsec_t *regbase = priv->phyregs;
 247         int timeout = 1000000;
 248
 249         regbase->miimadd = (phyid << 8) | regnum;
 250         regbase->miimcon = value;
 251         asm("sync");
 252
 253         timeout = 1000000;
 254         while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
 255 }
 256
 257 /* #define to provide old write_phy_reg functionality without duplicating code */
 258 #define write_phy_reg(priv, regnum, value) write_any_phy_reg(priv,priv->phyaddr,regnum,value)
 259
 260 /* Reads register regnum on the device's PHY through the
 261  * registers specified in priv.  It lowers and raises the read
 262  * command, and waits for the data to become valid (miimind
 263  * notvalid bit cleared), and the bus to cease activity (miimind
 264  * busy bit cleared), and then returns the value
 265  */
 266 uint read_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum)
 267 {
 268         uint value;
 269         volatile tsec_t *regbase = priv->phyregs;
 270
 271         /* Put the address of the phy, and the register
 272          * number into MIIMADD */
 273         regbase->miimadd = (phyid << 8) | regnum;
 274
 275         /* Clear the command register, and wait */
 276         regbase->miimcom = 0;
 277         asm("sync");
 278
 279         /* Initiate a read command, and wait */
 280         regbase->miimcom = MIIM_READ_COMMAND;
 281         asm("sync");
 282
 283         /* Wait for the the indication that the read is done */
 284         while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
 285
 286         /* Grab the value read from the PHY */
 287         value = regbase->miimstat;
 288
 289         return value;
 290 }
 291
 292 /* #define to provide old read_phy_reg functionality without duplicating code */
 293 #define read_phy_reg(priv,regnum) read_any_phy_reg(priv,priv->phyaddr,regnum)
 294
 295 /* Discover which PHY is attached to the device, and configure it
 296  * properly.  If the PHY is not recognized, then return 0
 297  * (failure).  Otherwise, return 1
 298  */
 299 static int init_phy(struct eth_device *dev)
 300 {
 301         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 302         struct phy_info *curphy;
 303         volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
 304
 305         /* Assign a Physical address to the TBI */
 306         regs->tbipa = CFG_TBIPA_VALUE;
 307         regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
 308         regs->tbipa = CFG_TBIPA_VALUE;
 309         asm("sync");
 310
 311         /* Reset MII (due to new addresses) */
 312         priv->phyregs->miimcfg = MIIMCFG_RESET;
 313         asm("sync");
 314         priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
 315         asm("sync");
 316         while (priv->phyregs->miimind & MIIMIND_BUSY) ;
 317
 318         if (0 == relocated)
 319                 relocate_cmds();
 320
 321         /* Get the cmd structure corresponding to the attached
 322          * PHY */
 323         curphy = get_phy_info(dev);
 324
 325         if (curphy == NULL) {
 326                 priv->phyinfo = NULL;
 327                 printf("%s: No PHY found\n", dev->name);
 328
 329                 return 0;
 330         }
 331
 332         priv->phyinfo = curphy;
 333
 334         phy_run_commands(priv, priv->phyinfo->config);
 335
 336         return 1;
 337 }
 338
 339 /*
 340  * Returns which value to write to the control register.
 341  * For 10/100, the value is slightly different
 342  */
 343 uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
 344 {
 345         if (priv->flags & TSEC_GIGABIT)
 346                 return MIIM_CONTROL_INIT;
 347         else
 348                 return MIIM_CR_INIT;
 349 }
 350
 351 /* Parse the status register for link, and then do
 352  * auto-negotiation
 353  */
 354 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
 355 {
 356         /*
 357          * Wait if the link is up, and autonegotiation is in progress
 358          * (ie - we're capable and it's not done)
 359          */
 360         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 361         if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE)
 362             && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
 363                 int i = 0;
 364
 365                 puts("Waiting for PHY auto negotiation to complete");
 366                 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) {
 367                         /*
 368                          * Timeout reached ?
 369                          */
 370                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 371                                 puts(" TIMEOUT !\n");
 372                                 priv->link = 0;
 373                                 return 0;
 374                         }
 375
 376                         if ((i++ % 1000) == 0) {
 377                                 putc('.');
 378                         }
 379                         udelay(1000);   /* 1 ms */
 380                         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 381                 }
 382                 puts(" done\n");
 383                 priv->link = 1;
 384                 udelay(500000); /* another 500 ms (results in faster booting) */
 385         } else {
 386                 if (mii_reg & MIIM_STATUS_LINK)
 387                         priv->link = 1;
 388                 else
 389                         priv->link = 0;
 390         }
 391
 392         return 0;
 393 }
 394
 395 /* Generic function which updates the speed and duplex.  If
 396  * autonegotiation is enabled, it uses the AND of the link
 397  * partner's advertised capabilities and our advertised
 398  * capabilities.  If autonegotiation is disabled, we use the
 399  * appropriate bits in the control register.
 400  *
 401  * Stolen from Linux's mii.c and phy_device.c
 402  */
 403 uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
 404 {
 405         /* We're using autonegotiation */
 406         if (mii_reg & PHY_BMSR_AUTN_ABLE) {
 407                 uint lpa = 0;
 408                 uint gblpa = 0;
 409
 410                 /* Check for gigabit capability */
 411                 if (mii_reg & PHY_BMSR_EXT) {
 412                         /* We want a list of states supported by
 413                          * both PHYs in the link
 414                          */
 415                         gblpa = read_phy_reg(priv, PHY_1000BTSR);
 416                         gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
 417                 }
 418
 419                 /* Set the baseline so we only have to set them
 420                  * if they're different
 421                  */
 422                 priv->speed = 10;
 423                 priv->duplexity = 0;
 424
 425                 /* Check the gigabit fields */
 426                 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
 427                         priv->speed = 1000;
 428
 429                         if (gblpa & PHY_1000BTSR_1000FD)
 430                                 priv->duplexity = 1;
 431
 432                         /* We're done! */
 433                         return 0;
 434                 }
 435
 436                 lpa = read_phy_reg(priv, PHY_ANAR);
 437                 lpa &= read_phy_reg(priv, PHY_ANLPAR);
 438
 439                 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
 440                         priv->speed = 100;
 441
 442                         if (lpa & PHY_ANLPAR_TXFD)
 443                                 priv->duplexity = 1;
 444
 445                 } else if (lpa & PHY_ANLPAR_10FD)
 446                         priv->duplexity = 1;
 447         } else {
 448                 uint bmcr = read_phy_reg(priv, PHY_BMCR);
 449
 450                 priv->speed = 10;
 451                 priv->duplexity = 0;
 452
 453                 if (bmcr & PHY_BMCR_DPLX)
 454                         priv->duplexity = 1;
 455
 456                 if (bmcr & PHY_BMCR_1000_MBPS)
 457                         priv->speed = 1000;
 458                 else if (bmcr & PHY_BMCR_100_MBPS)
 459                         priv->speed = 100;
 460         }
 461
 462         return 0;
 463 }
 464
 465 /*
 466  * Parse the BCM54xx status register for speed and duplex information.
 467  * The linux sungem_phy has this information, but in a table format.
 468  */
 469 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
 470 {
 471
 472         switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){
 473
 474                 case 1:
 475                         printf("Enet starting in 10BT/HD\n");
 476                         priv->duplexity = 0;
 477                         priv->speed = 10;
 478                         break;
 479
 480                 case 2:
 481                         printf("Enet starting in 10BT/FD\n");
 482                         priv->duplexity = 1;
 483                         priv->speed = 10;
 484                         break;
 485
 486                 case 3:
 487                         printf("Enet starting in 100BT/HD\n");
 488                         priv->duplexity = 0;
 489                         priv->speed = 100;
 490                         break;
 491
 492                 case 5:
 493                         printf("Enet starting in 100BT/FD\n");
 494                         priv->duplexity = 1;
 495                         priv->speed = 100;
 496                         break;
 497
 498                 case 6:
 499                         printf("Enet starting in 1000BT/HD\n");
 500                         priv->duplexity = 0;
 501                         priv->speed = 1000;
 502                         break;
 503
 504                 case 7:
 505                         printf("Enet starting in 1000BT/FD\n");
 506                         priv->duplexity = 1;
 507                         priv->speed = 1000;
 508                         break;
 509
 510                 default:
 511                         printf("Auto-neg error, defaulting to 10BT/HD\n");
 512                         priv->duplexity = 0;
 513                         priv->speed = 10;
 514                         break;
 515         }
 516
 517         return 0;
 518
 519 }
 520 /* Parse the 88E1011's status register for speed and duplex
 521  * information
 522  */
 523 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
 524 {
 525         uint speed;
 526
 527         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 528
 529         if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
 530                 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
 531                 int i = 0;
 532
 533                 puts("Waiting for PHY realtime link");
 534                 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
 535                         /* Timeout reached ? */
 536                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 537                                 puts(" TIMEOUT !\n");
 538                                 priv->link = 0;
 539                                 break;
 540                         }
 541
 542                         if ((i++ % 1000) == 0) {
 543                                 putc('.');
 544                         }
 545                         udelay(1000);   /* 1 ms */
 546                         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 547                 }
 548                 puts(" done\n");
 549                 udelay(500000); /* another 500 ms (results in faster booting) */
 550         } else {
 551                 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
 552                         priv->link = 1;
 553                 else
 554                         priv->link = 0;
 555         }
 556
 557         if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
 558                 priv->duplexity = 1;
 559         else
 560                 priv->duplexity = 0;
 561
 562         speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
 563
 564         switch (speed) {
 565         case MIIM_88E1011_PHYSTAT_GBIT:
 566                 priv->speed = 1000;
 567                 break;
 568         case MIIM_88E1011_PHYSTAT_100:
 569                 priv->speed = 100;
 570                 break;
 571         default:
 572                 priv->speed = 10;
 573         }
 574
 575         return 0;
 576 }
 577
 578 /* Parse the cis8201's status register for speed and duplex
 579  * information
 580  */
 581 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
 582 {
 583         uint speed;
 584
 585         if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
 586                 priv->duplexity = 1;
 587         else
 588                 priv->duplexity = 0;
 589
 590         speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
 591         switch (speed) {
 592         case MIIM_CIS8201_AUXCONSTAT_GBIT:
 593                 priv->speed = 1000;
 594                 break;
 595         case MIIM_CIS8201_AUXCONSTAT_100:
 596                 priv->speed = 100;
 597                 break;
 598         default:
 599                 priv->speed = 10;
 600                 break;
 601         }
 602
 603         return 0;
 604 }
 605
 606 /* Parse the vsc8244's status register for speed and duplex
 607  * information
 608  */
 609 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
 610 {
 611         uint speed;
 612
 613         if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
 614                 priv->duplexity = 1;
 615         else
 616                 priv->duplexity = 0;
 617
 618         speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
 619         switch (speed) {
 620         case MIIM_VSC8244_AUXCONSTAT_GBIT:
 621                 priv->speed = 1000;
 622                 break;
 623         case MIIM_VSC8244_AUXCONSTAT_100:
 624                 priv->speed = 100;
 625                 break;
 626         default:
 627                 priv->speed = 10;
 628                 break;
 629         }
 630
 631         return 0;
 632 }
 633
 634 /* Parse the DM9161's status register for speed and duplex
 635  * information
 636  */
 637 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
 638 {
 639         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
 640                 priv->speed = 100;
 641         else
 642                 priv->speed = 10;
 643
 644         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
 645                 priv->duplexity = 1;
 646         else
 647                 priv->duplexity = 0;
 648
 649         return 0;
 650 }
 651
 652 /*
 653  * Hack to write all 4 PHYs with the LED values
 654  */
 655 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
 656 {
 657         uint phyid;
 658         volatile tsec_t *regbase = priv->phyregs;
 659         int timeout = 1000000;
 660
 661         for (phyid = 0; phyid < 4; phyid++) {
 662                 regbase->miimadd = (phyid << 8) | mii_reg;
 663                 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
 664                 asm("sync");
 665
 666                 timeout = 1000000;
 667                 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
 668         }
 669
 670         return MIIM_CIS8204_SLEDCON_INIT;
 671 }
 672
 673 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
 674 {
 675         if (priv->flags & TSEC_REDUCED)
 676                 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
 677         else
 678                 return MIIM_CIS8204_EPHYCON_INIT;
 679 }
 680
 681 uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv)
 682 {
 683         uint mii_data = read_phy_reg(priv, mii_reg);
 684
 685         if (priv->flags & TSEC_REDUCED)
 686                 mii_data = (mii_data & 0xfff0) | 0x000b;
 687         return mii_data;
 688 }
 689
 690 /* Initialized required registers to appropriate values, zeroing
 691  * those we don't care about (unless zero is bad, in which case,
 692  * choose a more appropriate value)
 693  */
 694 static void init_registers(volatile tsec_t * regs)
 695 {
 696         /* Clear IEVENT */
 697         regs->ievent = IEVENT_INIT_CLEAR;
 698
 699         regs->imask = IMASK_INIT_CLEAR;
 700
 701         regs->hash.iaddr0 = 0;
 702         regs->hash.iaddr1 = 0;
 703         regs->hash.iaddr2 = 0;
 704         regs->hash.iaddr3 = 0;
 705         regs->hash.iaddr4 = 0;
 706         regs->hash.iaddr5 = 0;
 707         regs->hash.iaddr6 = 0;
 708         regs->hash.iaddr7 = 0;
 709
 710         regs->hash.gaddr0 = 0;
 711         regs->hash.gaddr1 = 0;
 712         regs->hash.gaddr2 = 0;
 713         regs->hash.gaddr3 = 0;
 714         regs->hash.gaddr4 = 0;
 715         regs->hash.gaddr5 = 0;
 716         regs->hash.gaddr6 = 0;
 717         regs->hash.gaddr7 = 0;
 718
 719         regs->rctrl = 0x00000000;
 720
 721         /* Init RMON mib registers */
 722         memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
 723
 724         regs->rmon.cam1 = 0xffffffff;
 725         regs->rmon.cam2 = 0xffffffff;
 726
 727         regs->mrblr = MRBLR_INIT_SETTINGS;
 728
 729         regs->minflr = MINFLR_INIT_SETTINGS;
 730
 731         regs->attr = ATTR_INIT_SETTINGS;
 732         regs->attreli = ATTRELI_INIT_SETTINGS;
 733
 734 }
 735
 736 /* Configure maccfg2 based on negotiated speed and duplex
 737  * reported by PHY handling code
 738  */
 739 static void adjust_link(struct eth_device *dev)
 740 {
 741         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 742         volatile tsec_t *regs = priv->regs;
 743
 744         if (priv->link) {
 745                 if (priv->duplexity != 0)
 746                         regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
 747                 else
 748                         regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
 749
 750                 switch (priv->speed) {
 751                 case 1000:
 752                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 753                                          | MACCFG2_GMII);
 754                         break;
 755                 case 100:
 756                 case 10:
 757                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 758                                          | MACCFG2_MII);
 759
 760                         /* Set R100 bit in all modes although
 761                          * it is only used in RGMII mode
 762                          */
 763                         if (priv->speed == 100)
 764                                 regs->ecntrl |= ECNTRL_R100;
 765                         else
 766                                 regs->ecntrl &= ~(ECNTRL_R100);
 767                         break;
 768                 default:
 769                         printf("%s: Speed was bad\n", dev->name);
 770                         break;
 771                 }
 772
 773                 printf("Speed: %d, %s duplex\n", priv->speed,
 774                        (priv->duplexity) ? "full" : "half");
 775
 776         } else {
 777                 printf("%s: No link.\n", dev->name);
 778         }
 779 }
 780
 781 /* Set up the buffers and their descriptors, and bring up the
 782  * interface
 783  */
 784 static void startup_tsec(struct eth_device *dev)
 785 {
 786         int i;
 787         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 788         volatile tsec_t *regs = priv->regs;
 789
 790         /* Point to the buffer descriptors */
 791         regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
 792         regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
 793
 794         /* Initialize the Rx Buffer descriptors */
 795         for (i = 0; i < PKTBUFSRX; i++) {
 796                 rtx.rxbd[i].status = RXBD_EMPTY;
 797                 rtx.rxbd[i].length = 0;
 798                 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
 799         }
 800         rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
 801
 802         /* Initialize the TX Buffer Descriptors */
 803         for (i = 0; i < TX_BUF_CNT; i++) {
 804                 rtx.txbd[i].status = 0;
 805                 rtx.txbd[i].length = 0;
 806                 rtx.txbd[i].bufPtr = 0;
 807         }
 808         rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
 809
 810         /* Start up the PHY */
 811         if(priv->phyinfo)
 812                 phy_run_commands(priv, priv->phyinfo->startup);
 813
 814         adjust_link(dev);
 815
 816         /* Enable Transmit and Receive */
 817         regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 818
 819         /* Tell the DMA it is clear to go */
 820         regs->dmactrl |= DMACTRL_INIT_SETTINGS;
 821         regs->tstat = TSTAT_CLEAR_THALT;
 822         regs->rstat = RSTAT_CLEAR_RHALT;
 823         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 824 }
 825
 826 /* This returns the status bits of the device.  The return value
 827  * is never checked, and this is what the 8260 driver did, so we
 828  * do the same.  Presumably, this would be zero if there were no
 829  * errors
 830  */
 831 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
 832 {
 833         int i;
 834         int result = 0;
 835         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 836         volatile tsec_t *regs = priv->regs;
 837
 838         /* Find an empty buffer descriptor */
 839         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 840                 if (i >= TOUT_LOOP) {
 841                         debug("%s: tsec: tx buffers full\n", dev->name);
 842                         return result;
 843                 }
 844         }
 845
 846         rtx.txbd[txIdx].bufPtr = (uint) packet;
 847         rtx.txbd[txIdx].length = length;
 848         rtx.txbd[txIdx].status |=
 849             (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
 850
 851         /* Tell the DMA to go */
 852         regs->tstat = TSTAT_CLEAR_THALT;
 853
 854         /* Wait for buffer to be transmitted */
 855         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 856                 if (i >= TOUT_LOOP) {
 857                         debug("%s: tsec: tx error\n", dev->name);
 858                         return result;
 859                 }
 860         }
 861
 862         txIdx = (txIdx + 1) % TX_BUF_CNT;
 863         result = rtx.txbd[txIdx].status & TXBD_STATS;
 864
 865         return result;
 866 }
 867
 868 static int tsec_recv(struct eth_device *dev)
 869 {
 870         int length;
 871         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 872         volatile tsec_t *regs = priv->regs;
 873
 874         while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
 875
 876                 length = rtx.rxbd[rxIdx].length;
 877
 878                 /* Send the packet up if there were no errors */
 879                 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
 880                         NetReceive(NetRxPackets[rxIdx], length - 4);
 881                 } else {
 882                         printf("Got error %x\n",
 883                                (rtx.rxbd[rxIdx].status & RXBD_STATS));
 884                 }
 885
 886                 rtx.rxbd[rxIdx].length = 0;
 887
 888                 /* Set the wrap bit if this is the last element in the list */
 889                 rtx.rxbd[rxIdx].status =
 890                     RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
 891
 892                 rxIdx = (rxIdx + 1) % PKTBUFSRX;
 893         }
 894
 895         if (regs->ievent & IEVENT_BSY) {
 896                 regs->ievent = IEVENT_BSY;
 897                 regs->rstat = RSTAT_CLEAR_RHALT;
 898         }
 899
 900         return -1;
 901
 902 }
 903
 904 /* Stop the interface */
 905 static void tsec_halt(struct eth_device *dev)
 906 {
 907         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 908         volatile tsec_t *regs = priv->regs;
 909
 910         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 911         regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
 912
 913         while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
 914
 915         regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
 916
 917         /* Shut down the PHY, as needed */
 918         if(priv->phyinfo)
 919                 phy_run_commands(priv, priv->phyinfo->shutdown);
 920 }
 921
 922 struct phy_info phy_info_M88E1149S = {
 923         0x1410ca,
 924         "Marvell 88E1149S",
 925         4,
 926         (struct phy_cmd[]){     /* config */
 927                 /* Reset and configure the PHY */
 928                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 929                 {0x1d, 0x1f, NULL},
 930                 {0x1e, 0x200c, NULL},
 931                 {0x1d, 0x5, NULL},
 932                 {0x1e, 0x0, NULL},
 933                 {0x1e, 0x100, NULL},
 934                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 935                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 936                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 937                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 938                 {miim_end,}
 939         },
 940         (struct phy_cmd[]){     /* startup */
 941                 /* Status is read once to clear old link state */
 942                 {MIIM_STATUS, miim_read, NULL},
 943                 /* Auto-negotiate */
 944                 {MIIM_STATUS, miim_read, &mii_parse_sr},
 945                 /* Read the status */
 946                 {MIIM_88E1011_PHY_STATUS, miim_read,
 947                  &mii_parse_88E1011_psr},
 948                 {miim_end,}
 949         },
 950         (struct phy_cmd[]){     /* shutdown */
 951                 {miim_end,}
 952         },
 953 };
 954
 955 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
 956 struct phy_info phy_info_BCM5461S = {
 957         0x02060c1,      /* 5461 ID */
 958         "Broadcom BCM5461S",
 959         0, /* not clear to me what minor revisions we can shift away */
 960         (struct phy_cmd[]) { /* config */
 961                 /* Reset and configure the PHY */
 962                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 963                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 964                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 965                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 966                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 967                 {miim_end,}
 968         },
 969         (struct phy_cmd[]) { /* startup */
 970                 /* Status is read once to clear old link state */
 971                 {MIIM_STATUS, miim_read, NULL},
 972                 /* Auto-negotiate */
 973                 {MIIM_STATUS, miim_read, &mii_parse_sr},
 974                 /* Read the status */
 975                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
 976                 {miim_end,}
 977         },
 978         (struct phy_cmd[]) { /* shutdown */
 979                 {miim_end,}
 980         },
 981 };
 982
 983 struct phy_info phy_info_BCM5464S = {
 984         0x02060b1,      /* 5464 ID */
 985         "Broadcom BCM5464S",
 986         0, /* not clear to me what minor revisions we can shift away */
 987         (struct phy_cmd[]) { /* config */
 988                 /* Reset and configure the PHY */
 989                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 990                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 991                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 992                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 993                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 994                 {miim_end,}
 995         },
 996         (struct phy_cmd[]) { /* startup */
 997                 /* Status is read once to clear old link state */
 998                 {MIIM_STATUS, miim_read, NULL},
 999                 /* Auto-negotiate */
1000                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1001                 /* Read the status */
1002                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1003                 {miim_end,}
1004         },
1005         (struct phy_cmd[]) { /* shutdown */
1006                 {miim_end,}
1007         },
1008 };
1009
1010 struct phy_info phy_info_M88E1011S = {
1011         0x01410c6,
1012         "Marvell 88E1011S",
1013         4,
1014         (struct phy_cmd[]){     /* config */
1015                            /* Reset and configure the PHY */
1016                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1017                            {0x1d, 0x1f, NULL},
1018                            {0x1e, 0x200c, NULL},
1019                            {0x1d, 0x5, NULL},
1020                            {0x1e, 0x0, NULL},
1021                            {0x1e, 0x100, NULL},
1022                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1023                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1024                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1025                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1026                            {miim_end,}
1027                            },
1028         (struct phy_cmd[]){     /* startup */
1029                            /* Status is read once to clear old link state */
1030                            {MIIM_STATUS, miim_read, NULL},
1031                            /* Auto-negotiate */
1032                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1033                            /* Read the status */
1034                            {MIIM_88E1011_PHY_STATUS, miim_read,
1035                             &mii_parse_88E1011_psr},
1036                            {miim_end,}
1037                            },
1038         (struct phy_cmd[]){     /* shutdown */
1039                            {miim_end,}
1040                            },
1041 };
1042
1043 struct phy_info phy_info_M88E1111S = {
1044         0x01410cc,
1045         "Marvell 88E1111S",
1046         4,
1047         (struct phy_cmd[]){     /* config */
1048                            /* Reset and configure the PHY */
1049                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1050                            {0x1b, 0x848f, &mii_m88e1111s_setmode},
1051                            {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
1052                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1053                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1054                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1055                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1056                            {miim_end,}
1057                            },
1058         (struct phy_cmd[]){     /* startup */
1059                            /* Status is read once to clear old link state */
1060                            {MIIM_STATUS, miim_read, NULL},
1061                            /* Auto-negotiate */
1062                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1063                            /* Read the status */
1064                            {MIIM_88E1011_PHY_STATUS, miim_read,
1065                             &mii_parse_88E1011_psr},
1066                            {miim_end,}
1067                            },
1068         (struct phy_cmd[]){     /* shutdown */
1069                            {miim_end,}
1070                            },
1071 };
1072
1073 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
1074 {
1075         uint mii_data = read_phy_reg(priv, mii_reg);
1076
1077         /* Setting MIIM_88E1145_PHY_EXT_CR */
1078         if (priv->flags & TSEC_REDUCED)
1079                 return mii_data |
1080                     MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
1081         else
1082                 return mii_data;
1083 }
1084
1085 static struct phy_info phy_info_M88E1145 = {
1086         0x01410cd,
1087         "Marvell 88E1145",
1088         4,
1089         (struct phy_cmd[]){     /* config */
1090                            /* Reset the PHY */
1091                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1092
1093                            /* Errata E0, E1 */
1094                            {29, 0x001b, NULL},
1095                            {30, 0x418f, NULL},
1096                            {29, 0x0016, NULL},
1097                            {30, 0xa2da, NULL},
1098
1099                            /* Configure the PHY */
1100                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1101                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1102                            {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
1103                             NULL},
1104                            {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
1105                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1106                            {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
1107                            {miim_end,}
1108                            },
1109         (struct phy_cmd[]){     /* startup */
1110                            /* Status is read once to clear old link state */
1111                            {MIIM_STATUS, miim_read, NULL},
1112                            /* Auto-negotiate */
1113                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1114                            {MIIM_88E1111_PHY_LED_CONTROL,
1115                             MIIM_88E1111_PHY_LED_DIRECT, NULL},
1116                            /* Read the Status */
1117                            {MIIM_88E1011_PHY_STATUS, miim_read,
1118                             &mii_parse_88E1011_psr},
1119                            {miim_end,}
1120                            },
1121         (struct phy_cmd[]){     /* shutdown */
1122                            {miim_end,}
1123                            },
1124 };
1125
1126 struct phy_info phy_info_cis8204 = {
1127         0x3f11,
1128         "Cicada Cis8204",
1129         6,
1130         (struct phy_cmd[]){     /* config */
1131                            /* Override PHY config settings */
1132                            {MIIM_CIS8201_AUX_CONSTAT,
1133                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1134                            /* Configure some basic stuff */
1135                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1136                            {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
1137                             &mii_cis8204_fixled},
1138                            {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
1139                             &mii_cis8204_setmode},
1140                            {miim_end,}
1141                            },
1142         (struct phy_cmd[]){     /* startup */
1143                            /* Read the Status (2x to make sure link is right) */
1144                            {MIIM_STATUS, miim_read, NULL},
1145                            /* Auto-negotiate */
1146                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1147                            /* Read the status */
1148                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1149                             &mii_parse_cis8201},
1150                            {miim_end,}
1151                            },
1152         (struct phy_cmd[]){     /* shutdown */
1153                            {miim_end,}
1154                            },
1155 };
1156
1157 /* Cicada 8201 */
1158 struct phy_info phy_info_cis8201 = {
1159         0xfc41,
1160         "CIS8201",
1161         4,
1162         (struct phy_cmd[]){     /* config */
1163                            /* Override PHY config settings */
1164                            {MIIM_CIS8201_AUX_CONSTAT,
1165                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1166                            /* Set up the interface mode */
1167                            {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
1168                             NULL},
1169                            /* Configure some basic stuff */
1170                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1171                            {miim_end,}
1172                            },
1173         (struct phy_cmd[]){     /* startup */
1174                            /* Read the Status (2x to make sure link is right) */
1175                            {MIIM_STATUS, miim_read, NULL},
1176                            /* Auto-negotiate */
1177                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1178                            /* Read the status */
1179                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1180                             &mii_parse_cis8201},
1181                            {miim_end,}
1182                            },
1183         (struct phy_cmd[]){     /* shutdown */
1184                            {miim_end,}
1185                            },
1186 };
1187 struct phy_info phy_info_VSC8244 = {
1188         0x3f1b,
1189         "Vitesse VSC8244",
1190         6,
1191         (struct phy_cmd[]){     /* config */
1192                            /* Override PHY config settings */
1193                            /* Configure some basic stuff */
1194                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1195                            {miim_end,}
1196                            },
1197         (struct phy_cmd[]){     /* startup */
1198                            /* Read the Status (2x to make sure link is right) */
1199                            {MIIM_STATUS, miim_read, NULL},
1200                            /* Auto-negotiate */
1201                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1202                            /* Read the status */
1203                            {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1204                             &mii_parse_vsc8244},
1205                            {miim_end,}
1206                            },
1207         (struct phy_cmd[]){     /* shutdown */
1208                            {miim_end,}
1209                            },
1210 };
1211
1212 struct phy_info phy_info_dm9161 = {
1213         0x0181b88,
1214         "Davicom DM9161E",
1215         4,
1216         (struct phy_cmd[]){     /* config */
1217                            {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1218                            /* Do not bypass the scrambler/descrambler */
1219                            {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1220                            /* Clear 10BTCSR to default */
1221                            {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
1222                             NULL},
1223                            /* Configure some basic stuff */
1224                            {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1225                            /* Restart Auto Negotiation */
1226                            {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1227                            {miim_end,}
1228                            },
1229         (struct phy_cmd[]){     /* startup */
1230                            /* Status is read once to clear old link state */
1231                            {MIIM_STATUS, miim_read, NULL},
1232                            /* Auto-negotiate */
1233                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1234                            /* Read the status */
1235                            {MIIM_DM9161_SCSR, miim_read,
1236                             &mii_parse_dm9161_scsr},
1237                            {miim_end,}
1238                            },
1239         (struct phy_cmd[]){     /* shutdown */
1240                            {miim_end,}
1241                            },
1242 };
1243 /* a generic flavor.  */
1244 struct phy_info phy_info_generic =  {
1245         0,
1246         "Unknown/Generic PHY",
1247         32,
1248         (struct phy_cmd[]) { /* config */
1249                 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1250                 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1251                 {miim_end,}
1252         },
1253         (struct phy_cmd[]) { /* startup */
1254                 {PHY_BMSR, miim_read, NULL},
1255                 {PHY_BMSR, miim_read, &mii_parse_sr},
1256                 {PHY_BMSR, miim_read, &mii_parse_link},
1257                 {miim_end,}
1258         },
1259         (struct phy_cmd[]) { /* shutdown */
1260                 {miim_end,}
1261         }
1262 };
1263
1264
1265 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1266 {
1267         unsigned int speed;
1268         if (priv->link) {
1269                 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1270
1271                 switch (speed) {
1272                 case MIIM_LXT971_SR2_10HDX:
1273                         priv->speed = 10;
1274                         priv->duplexity = 0;
1275                         break;
1276                 case MIIM_LXT971_SR2_10FDX:
1277                         priv->speed = 10;
1278                         priv->duplexity = 1;
1279                         break;
1280                 case MIIM_LXT971_SR2_100HDX:
1281                         priv->speed = 100;
1282                         priv->duplexity = 0;
1283                         break;
1284                 default:
1285                         priv->speed = 100;
1286                         priv->duplexity = 1;
1287                 }
1288         } else {
1289                 priv->speed = 0;
1290                 priv->duplexity = 0;
1291         }
1292
1293         return 0;
1294 }
1295
1296 static struct phy_info phy_info_lxt971 = {
1297         0x0001378e,
1298         "LXT971",
1299         4,
1300         (struct phy_cmd[]){     /* config */
1301                            {MIIM_CR, MIIM_CR_INIT, mii_cr_init},        /* autonegotiate */
1302                            {miim_end,}
1303                            },
1304         (struct phy_cmd[]){     /* startup - enable interrupts */
1305                            /* { 0x12, 0x00f2, NULL }, */
1306                            {MIIM_STATUS, miim_read, NULL},
1307                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1308                            {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1309                            {miim_end,}
1310                            },
1311         (struct phy_cmd[]){     /* shutdown - disable interrupts */
1312                            {miim_end,}
1313                            },
1314 };
1315
1316 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1317  * information
1318  */
1319 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1320 {
1321         switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1322
1323         case MIIM_DP83865_SPD_1000:
1324                 priv->speed = 1000;
1325                 break;
1326
1327         case MIIM_DP83865_SPD_100:
1328                 priv->speed = 100;
1329                 break;
1330
1331         default:
1332                 priv->speed = 10;
1333                 break;
1334
1335         }
1336
1337         if (mii_reg & MIIM_DP83865_DPX_FULL)
1338                 priv->duplexity = 1;
1339         else
1340                 priv->duplexity = 0;
1341
1342         return 0;
1343 }
1344
1345 struct phy_info phy_info_dp83865 = {
1346         0x20005c7,
1347         "NatSemi DP83865",
1348         4,
1349         (struct phy_cmd[]){     /* config */
1350                            {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1351                            {miim_end,}
1352                            },
1353         (struct phy_cmd[]){     /* startup */
1354                            /* Status is read once to clear old link state */
1355                            {MIIM_STATUS, miim_read, NULL},
1356                            /* Auto-negotiate */
1357                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1358                            /* Read the link and auto-neg status */
1359                            {MIIM_DP83865_LANR, miim_read,
1360                             &mii_parse_dp83865_lanr},
1361                            {miim_end,}
1362                            },
1363         (struct phy_cmd[]){     /* shutdown */
1364                            {miim_end,}
1365                            },
1366 };
1367
1368 struct phy_info *phy_info[] = {
1369         &phy_info_cis8204,
1370         &phy_info_cis8201,
1371         &phy_info_BCM5461S,
1372         &phy_info_BCM5464S,
1373         &phy_info_M88E1011S,
1374         &phy_info_M88E1111S,
1375         &phy_info_M88E1145,
1376         &phy_info_M88E1149S,
1377         &phy_info_dm9161,
1378         &phy_info_lxt971,
1379         &phy_info_VSC8244,
1380         &phy_info_dp83865,
1381         &phy_info_generic,
1382         NULL
1383 };
1384
1385 /* Grab the identifier of the device's PHY, and search through
1386  * all of the known PHYs to see if one matches.  If so, return
1387  * it, if not, return NULL
1388  */
1389 struct phy_info *get_phy_info(struct eth_device *dev)
1390 {
1391         struct tsec_private *priv = (struct tsec_private *)dev->priv;
1392         uint phy_reg, phy_ID;
1393         int i;
1394         struct phy_info *theInfo = NULL;
1395
1396         /* Grab the bits from PHYIR1, and put them in the upper half */
1397         phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1398         phy_ID = (phy_reg & 0xffff) << 16;
1399
1400         /* Grab the bits from PHYIR2, and put them in the lower half */
1401         phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1402         phy_ID |= (phy_reg & 0xffff);
1403
1404         /* loop through all the known PHY types, and find one that */
1405         /* matches the ID we read from the PHY. */
1406         for (i = 0; phy_info[i]; i++) {
1407                 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
1408                         theInfo = phy_info[i];
1409                         break;
1410                 }
1411         }
1412
1413         if (theInfo == NULL) {
1414                 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
1415                 return NULL;
1416         } else {
1417                 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1418         }
1419
1420         return theInfo;
1421 }
1422
1423 /* Execute the given series of commands on the given device's
1424  * PHY, running functions as necessary
1425  */
1426 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1427 {
1428         int i;
1429         uint result;
1430         volatile tsec_t *phyregs = priv->phyregs;
1431
1432         phyregs->miimcfg = MIIMCFG_RESET;
1433
1434         phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1435
1436         while (phyregs->miimind & MIIMIND_BUSY) ;
1437
1438         for (i = 0; cmd->mii_reg != miim_end; i++) {
1439                 if (cmd->mii_data == miim_read) {
1440                         result = read_phy_reg(priv, cmd->mii_reg);
1441
1442                         if (cmd->funct != NULL)
1443                                 (*(cmd->funct)) (result, priv);
1444
1445                 } else {
1446                         if (cmd->funct != NULL)
1447                                 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1448                         else
1449                                 result = cmd->mii_data;
1450
1451                         write_phy_reg(priv, cmd->mii_reg, result);
1452
1453                 }
1454                 cmd++;
1455         }
1456 }
1457
1458 /* Relocate the function pointers in the phy cmd lists */
1459 static void relocate_cmds(void)
1460 {
1461         struct phy_cmd **cmdlistptr;
1462         struct phy_cmd *cmd;
1463         int i, j, k;
1464
1465         for (i = 0; phy_info[i]; i++) {
1466                 /* First thing's first: relocate the pointers to the
1467                  * PHY command structures (the structs were done) */
1468                 phy_info[i] = (struct phy_info *)((uint) phy_info[i]
1469                                                   + gd->reloc_off);
1470                 phy_info[i]->name += gd->reloc_off;
1471                 phy_info[i]->config =
1472                     (struct phy_cmd *)((uint) phy_info[i]->config
1473                                        + gd->reloc_off);
1474                 phy_info[i]->startup =
1475                     (struct phy_cmd *)((uint) phy_info[i]->startup
1476                                        + gd->reloc_off);
1477                 phy_info[i]->shutdown =
1478                     (struct phy_cmd *)((uint) phy_info[i]->shutdown
1479                                        + gd->reloc_off);
1480
1481                 cmdlistptr = &phy_info[i]->config;
1482                 j = 0;
1483                 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
1484                         k = 0;
1485                         for (cmd = *cmdlistptr;
1486                              cmd->mii_reg != miim_end;
1487                              cmd++) {
1488                                 /* Only relocate non-NULL pointers */
1489                                 if (cmd->funct)
1490                                         cmd->funct += gd->reloc_off;
1491
1492                                 k++;
1493                         }
1494                         j++;
1495                 }
1496         }
1497
1498         relocated = 1;
1499 }
1500
1501 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1502         && !defined(BITBANGMII)
1503
1504 /*
1505  * Read a MII PHY register.
1506  *
1507  * Returns:
1508  *  0 on success
1509  */
1510 static int tsec_miiphy_read(char *devname, unsigned char addr,
1511                             unsigned char reg, unsigned short *value)
1512 {
1513         unsigned short ret;
1514         struct tsec_private *priv = privlist[0];
1515
1516         if (NULL == priv) {
1517                 printf("Can't read PHY at address %d\n", addr);
1518                 return -1;
1519         }
1520
1521         ret = (unsigned short)read_any_phy_reg(priv, addr, reg);
1522         *value = ret;
1523
1524         return 0;
1525 }
1526
1527 /*
1528  * Write a MII PHY register.
1529  *
1530  * Returns:
1531  *  0 on success
1532  */
1533 static int tsec_miiphy_write(char *devname, unsigned char addr,
1534                              unsigned char reg, unsigned short value)
1535 {
1536         struct tsec_private *priv = privlist[0];
1537
1538         if (NULL == priv) {
1539                 printf("Can't write PHY at address %d\n", addr);
1540                 return -1;
1541         }
1542
1543         write_any_phy_reg(priv, addr, reg, value);
1544
1545         return 0;
1546 }
1547
1548 #endif
1549
1550 #ifdef CONFIG_MCAST_TFTP
1551
1552 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
1553
1554 /* Set the appropriate hash bit for the given addr */
1555
1556 /* The algorithm works like so:
1557  * 1) Take the Destination Address (ie the multicast address), and
1558  * do a CRC on it (little endian), and reverse the bits of the
1559  * result.
1560  * 2) Use the 8 most significant bits as a hash into a 256-entry
1561  * table.  The table is controlled through 8 32-bit registers:
1562  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1563  * gaddr7.  This means that the 3 most significant bits in the
1564  * hash index which gaddr register to use, and the 5 other bits
1565  * indicate which bit (assuming an IBM numbering scheme, which
1566  * for PowerPC (tm) is usually the case) in the tregister holds
1567  * the entry. */
1568 static int
1569 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
1570 {
1571  struct tsec_private *priv = privlist[1];
1572  volatile tsec_t *regs = priv->regs;
1573  volatile u32  *reg_array, value;
1574  u8 result, whichbit, whichreg;
1575
1576         result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
1577         whichbit = result & 0x1f;       /* the 5 LSB = which bit to set */
1578         whichreg = result >> 5;         /* the 3 MSB = which reg to set it in */
1579         value = (1 << (31-whichbit));
1580
1581         reg_array = &(regs->hash.gaddr0);
1582
1583         if (set) {
1584                 reg_array[whichreg] |= value;
1585         } else {
1586                 reg_array[whichreg] &= ~value;
1587         }
1588         return 0;
1589 }
1590 #endif /* Multicast TFTP ? */
1591
1592 #endif /* CONFIG_TSEC_ENET */