2 * Freescale Three Speed Ethernet Controller driver
4 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
5 * (C) Copyright 2003, Motorola, Inc.
8 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/errno.h>
19 #include <asm/processor.h>
22 DECLARE_GLOBAL_DATA_PTR;
26 static uint rx_idx; /* index of the current RX buffer */
27 static uint tx_idx; /* index of the current TX buffer */
30 static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8);
31 static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8);
34 #error "rtx must be 64-bit aligned"
37 static int tsec_send(struct eth_device *dev, void *packet, int length);
39 /* Default initializations for TSEC controllers. */
41 static struct tsec_info_struct tsec_info[] = {
43 STD_TSEC_INFO(1), /* TSEC1 */
46 STD_TSEC_INFO(2), /* TSEC2 */
48 #ifdef CONFIG_MPC85XX_FEC
50 .regs = TSEC_GET_REGS(2, 0x2000),
51 .devname = CONFIG_MPC85XX_FEC_NAME,
52 .phyaddr = FEC_PHY_ADDR,
54 .mii_devname = DEFAULT_MII_NAME
58 STD_TSEC_INFO(3), /* TSEC3 */
61 STD_TSEC_INFO(4), /* TSEC4 */
65 #define TBIANA_SETTINGS ( \
66 TBIANA_ASYMMETRIC_PAUSE \
67 | TBIANA_SYMMETRIC_PAUSE \
68 | TBIANA_FULL_DUPLEX \
71 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
72 #ifndef CONFIG_TSEC_TBICR_SETTINGS
73 #define CONFIG_TSEC_TBICR_SETTINGS ( \
79 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
81 /* Configure the TBI for SGMII operation */
82 static void tsec_configure_serdes(struct tsec_private *priv)
85 * Access TBI PHY registers at given TSEC register offset as opposed
86 * to the register offset used for external PHY accesses
88 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
89 0, TBI_ANA, TBIANA_SETTINGS);
90 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
91 0, TBI_TBICON, TBICON_CLK_SELECT);
92 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
93 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
96 #ifdef CONFIG_MCAST_TFTP
98 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
100 /* Set the appropriate hash bit for the given addr */
103 * The algorithm works like so:
104 * 1) Take the Destination Address (ie the multicast address), and
105 * do a CRC on it (little endian), and reverse the bits of the
107 * 2) Use the 8 most significant bits as a hash into a 256-entry
108 * table. The table is controlled through 8 32-bit registers:
109 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
110 * 255. This means that the 3 most significant bits in the
111 * hash index which gaddr register to use, and the 5 other bits
112 * indicate which bit (assuming an IBM numbering scheme, which
113 * for PowerPC (tm) is usually the case) in the register holds
116 static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
118 struct tsec_private *priv = (struct tsec_private *)dev->priv;
119 struct tsec __iomem *regs = priv->regs;
121 u8 whichbit, whichreg;
123 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
124 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
125 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
127 value = 1 << (31-whichbit);
130 setbits_be32(®s->hash.gaddr0 + whichreg, value);
132 clrbits_be32(®s->hash.gaddr0 + whichreg, value);
136 #endif /* Multicast TFTP ? */
139 * Initialized required registers to appropriate values, zeroing
140 * those we don't care about (unless zero is bad, in which case,
141 * choose a more appropriate value)
143 static void init_registers(struct tsec __iomem *regs)
146 out_be32(®s->ievent, IEVENT_INIT_CLEAR);
148 out_be32(®s->imask, IMASK_INIT_CLEAR);
150 out_be32(®s->hash.iaddr0, 0);
151 out_be32(®s->hash.iaddr1, 0);
152 out_be32(®s->hash.iaddr2, 0);
153 out_be32(®s->hash.iaddr3, 0);
154 out_be32(®s->hash.iaddr4, 0);
155 out_be32(®s->hash.iaddr5, 0);
156 out_be32(®s->hash.iaddr6, 0);
157 out_be32(®s->hash.iaddr7, 0);
159 out_be32(®s->hash.gaddr0, 0);
160 out_be32(®s->hash.gaddr1, 0);
161 out_be32(®s->hash.gaddr2, 0);
162 out_be32(®s->hash.gaddr3, 0);
163 out_be32(®s->hash.gaddr4, 0);
164 out_be32(®s->hash.gaddr5, 0);
165 out_be32(®s->hash.gaddr6, 0);
166 out_be32(®s->hash.gaddr7, 0);
168 out_be32(®s->rctrl, 0x00000000);
170 /* Init RMON mib registers */
171 memset((void *)®s->rmon, 0, sizeof(regs->rmon));
173 out_be32(®s->rmon.cam1, 0xffffffff);
174 out_be32(®s->rmon.cam2, 0xffffffff);
176 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
178 out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
180 out_be32(®s->attr, ATTR_INIT_SETTINGS);
181 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
186 * Configure maccfg2 based on negotiated speed and duplex
187 * reported by PHY handling code
189 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
191 struct tsec __iomem *regs = priv->regs;
195 printf("%s: No link.\n", phydev->dev->name);
199 /* clear all bits relative with interface mode */
200 ecntrl = in_be32(®s->ecntrl);
201 ecntrl &= ~ECNTRL_R100;
203 maccfg2 = in_be32(®s->maccfg2);
204 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
207 maccfg2 |= MACCFG2_FULL_DUPLEX;
209 switch (phydev->speed) {
211 maccfg2 |= MACCFG2_GMII;
215 maccfg2 |= MACCFG2_MII;
218 * Set R100 bit in all modes although
219 * it is only used in RGMII mode
221 if (phydev->speed == 100)
222 ecntrl |= ECNTRL_R100;
225 printf("%s: Speed was bad\n", phydev->dev->name);
229 out_be32(®s->ecntrl, ecntrl);
230 out_be32(®s->maccfg2, maccfg2);
232 printf("Speed: %d, %s duplex%s\n", phydev->speed,
233 (phydev->duplex) ? "full" : "half",
234 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
237 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
239 * When MACCFG1[Rx_EN] is enabled during system boot as part
240 * of the eTSEC port initialization sequence,
241 * the eTSEC Rx logic may not be properly initialized.
243 void redundant_init(struct eth_device *dev)
245 struct tsec_private *priv = dev->priv;
246 struct tsec __iomem *regs = priv->regs;
249 static const u8 pkt[] = {
250 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
251 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
252 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
253 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
254 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
255 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
256 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
257 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
258 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
259 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
260 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
261 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
262 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
265 /* Enable promiscuous mode */
266 setbits_be32(®s->rctrl, 0x8);
267 /* Enable loopback mode */
268 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
269 /* Enable transmit and receive */
270 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
272 /* Tell the DMA it is clear to go */
273 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
274 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
275 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
276 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
280 tsec_send(dev, (void *)pkt, sizeof(pkt));
282 /* Wait for buffer to be received */
283 for (t = 0; in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY; t++) {
284 if (t >= 10 * TOUT_LOOP) {
285 printf("%s: tsec: rx error\n", dev->name);
290 if (!memcmp(pkt, (void *)net_rx_packets[rx_idx], sizeof(pkt)))
293 out_be16(&rxbd[rx_idx].length, 0);
295 if ((rx_idx + 1) == PKTBUFSRX)
297 out_be16(&rxbd[rx_idx].status, status);
298 rx_idx = (rx_idx + 1) % PKTBUFSRX;
300 if (in_be32(®s->ievent) & IEVENT_BSY) {
301 out_be32(®s->ievent, IEVENT_BSY);
302 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
305 printf("loopback recv packet error!\n");
306 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
308 setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
310 } while ((count++ < 4) && (fail == 1));
313 panic("eTSEC init fail!\n");
314 /* Disable promiscuous mode */
315 clrbits_be32(®s->rctrl, 0x8);
316 /* Disable loopback mode */
317 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
322 * Set up the buffers and their descriptors, and bring up the
325 static void startup_tsec(struct eth_device *dev)
327 struct tsec_private *priv = (struct tsec_private *)dev->priv;
328 struct tsec __iomem *regs = priv->regs;
332 /* reset the indices to zero */
335 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
339 /* Point to the buffer descriptors */
340 out_be32(®s->tbase, (u32)&txbd[0]);
341 out_be32(®s->rbase, (u32)&rxbd[0]);
343 /* Initialize the Rx Buffer descriptors */
344 for (i = 0; i < PKTBUFSRX; i++) {
345 out_be16(&rxbd[i].status, RXBD_EMPTY);
346 out_be16(&rxbd[i].length, 0);
347 out_be32(&rxbd[i].bufptr, (u32)net_rx_packets[i]);
349 status = in_be16(&rxbd[PKTBUFSRX - 1].status);
350 out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
352 /* Initialize the TX Buffer Descriptors */
353 for (i = 0; i < TX_BUF_CNT; i++) {
354 out_be16(&txbd[i].status, 0);
355 out_be16(&txbd[i].length, 0);
356 out_be32(&txbd[i].bufptr, 0);
358 status = in_be16(&txbd[TX_BUF_CNT - 1].status);
359 out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
361 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
363 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
366 /* Enable Transmit and Receive */
367 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
369 /* Tell the DMA it is clear to go */
370 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
371 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
372 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
373 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
377 * This returns the status bits of the device. The return value
378 * is never checked, and this is what the 8260 driver did, so we
379 * do the same. Presumably, this would be zero if there were no
382 static int tsec_send(struct eth_device *dev, void *packet, int length)
384 struct tsec_private *priv = (struct tsec_private *)dev->priv;
385 struct tsec __iomem *regs = priv->regs;
390 /* Find an empty buffer descriptor */
391 for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
392 if (i >= TOUT_LOOP) {
393 debug("%s: tsec: tx buffers full\n", dev->name);
398 out_be32(&txbd[tx_idx].bufptr, (u32)packet);
399 out_be16(&txbd[tx_idx].length, length);
400 status = in_be16(&txbd[tx_idx].status);
401 out_be16(&txbd[tx_idx].status, status |
402 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
404 /* Tell the DMA to go */
405 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
407 /* Wait for buffer to be transmitted */
408 for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
409 if (i >= TOUT_LOOP) {
410 debug("%s: tsec: tx error\n", dev->name);
415 tx_idx = (tx_idx + 1) % TX_BUF_CNT;
416 result = in_be16(&txbd[tx_idx].status) & TXBD_STATS;
421 static int tsec_recv(struct eth_device *dev)
423 struct tsec_private *priv = (struct tsec_private *)dev->priv;
424 struct tsec __iomem *regs = priv->regs;
426 while (!(in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY)) {
427 int length = in_be16(&rxbd[rx_idx].length);
428 uint16_t status = in_be16(&rxbd[rx_idx].status);
430 /* Send the packet up if there were no errors */
431 if (!(status & RXBD_STATS))
432 net_process_received_packet(net_rx_packets[rx_idx],
435 printf("Got error %x\n", (status & RXBD_STATS));
437 out_be16(&rxbd[rx_idx].length, 0);
440 /* Set the wrap bit if this is the last element in the list */
441 if ((rx_idx + 1) == PKTBUFSRX)
443 out_be16(&rxbd[rx_idx].status, status);
445 rx_idx = (rx_idx + 1) % PKTBUFSRX;
448 if (in_be32(®s->ievent) & IEVENT_BSY) {
449 out_be32(®s->ievent, IEVENT_BSY);
450 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
456 /* Stop the interface */
457 static void tsec_halt(struct eth_device *dev)
459 struct tsec_private *priv = (struct tsec_private *)dev->priv;
460 struct tsec __iomem *regs = priv->regs;
462 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
463 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
465 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
466 != (IEVENT_GRSC | IEVENT_GTSC))
469 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
471 /* Shut down the PHY, as needed */
472 phy_shutdown(priv->phydev);
476 * Initializes data structures and registers for the controller,
477 * and brings the interface up. Returns the link status, meaning
478 * that it returns success if the link is up, failure otherwise.
479 * This allows U-Boot to find the first active controller.
481 static int tsec_init(struct eth_device *dev, bd_t * bd)
483 struct tsec_private *priv = (struct tsec_private *)dev->priv;
484 struct tsec __iomem *regs = priv->regs;
488 /* Make sure the controller is stopped */
491 /* Init MACCFG2. Defaults to GMII */
492 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
495 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
498 * Copy the station address into the address registers.
499 * For a station address of 0x12345678ABCD in transmission
500 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
501 * MACnADDR2 is set to 0x34120000.
503 tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
504 (dev->enetaddr[3] << 8) | dev->enetaddr[2];
506 out_be32(®s->macstnaddr1, tempval);
508 tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
510 out_be32(®s->macstnaddr2, tempval);
512 /* Clear out (for the most part) the other registers */
513 init_registers(regs);
515 /* Ready the device for tx/rx */
518 /* Start up the PHY */
519 ret = phy_startup(priv->phydev);
521 printf("Could not initialize PHY %s\n",
522 priv->phydev->dev->name);
526 adjust_link(priv, priv->phydev);
528 /* If there's no link, fail */
529 return priv->phydev->link ? 0 : -1;
532 static phy_interface_t tsec_get_interface(struct tsec_private *priv)
534 struct tsec __iomem *regs = priv->regs;
537 ecntrl = in_be32(®s->ecntrl);
539 if (ecntrl & ECNTRL_SGMII_MODE)
540 return PHY_INTERFACE_MODE_SGMII;
542 if (ecntrl & ECNTRL_TBI_MODE) {
543 if (ecntrl & ECNTRL_REDUCED_MODE)
544 return PHY_INTERFACE_MODE_RTBI;
546 return PHY_INTERFACE_MODE_TBI;
549 if (ecntrl & ECNTRL_REDUCED_MODE) {
550 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
551 return PHY_INTERFACE_MODE_RMII;
553 phy_interface_t interface = priv->interface;
556 * This isn't autodetected, so it must
557 * be set by the platform code.
559 if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
560 (interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
561 (interface == PHY_INTERFACE_MODE_RGMII_RXID))
564 return PHY_INTERFACE_MODE_RGMII;
568 if (priv->flags & TSEC_GIGABIT)
569 return PHY_INTERFACE_MODE_GMII;
571 return PHY_INTERFACE_MODE_MII;
575 * Discover which PHY is attached to the device, and configure it
576 * properly. If the PHY is not recognized, then return 0
577 * (failure). Otherwise, return 1
579 static int init_phy(struct eth_device *dev)
581 struct tsec_private *priv = (struct tsec_private *)dev->priv;
582 struct phy_device *phydev;
583 struct tsec __iomem *regs = priv->regs;
584 u32 supported = (SUPPORTED_10baseT_Half |
585 SUPPORTED_10baseT_Full |
586 SUPPORTED_100baseT_Half |
587 SUPPORTED_100baseT_Full);
589 if (priv->flags & TSEC_GIGABIT)
590 supported |= SUPPORTED_1000baseT_Full;
592 /* Assign a Physical address to the TBI */
593 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
595 priv->interface = tsec_get_interface(priv);
597 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
598 tsec_configure_serdes(priv);
600 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
604 phydev->supported &= supported;
605 phydev->advertising = phydev->supported;
607 priv->phydev = phydev;
615 * Initialize device structure. Returns success if PHY
616 * initialization succeeded (i.e. if it recognizes the PHY)
618 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
620 struct eth_device *dev;
622 struct tsec_private *priv;
624 dev = (struct eth_device *)malloc(sizeof *dev);
629 memset(dev, 0, sizeof *dev);
631 priv = (struct tsec_private *)malloc(sizeof(*priv));
636 priv->regs = tsec_info->regs;
637 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
639 priv->phyaddr = tsec_info->phyaddr;
640 priv->flags = tsec_info->flags;
642 sprintf(dev->name, tsec_info->devname);
643 priv->interface = tsec_info->interface;
644 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
647 dev->init = tsec_init;
648 dev->halt = tsec_halt;
649 dev->send = tsec_send;
650 dev->recv = tsec_recv;
651 #ifdef CONFIG_MCAST_TFTP
652 dev->mcast = tsec_mcast_addr;
655 /* Tell U-Boot to get the addr from the env */
656 for (i = 0; i < 6; i++)
657 dev->enetaddr[i] = 0;
662 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
663 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
664 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
666 /* Try to initialize PHY here, and return */
667 return init_phy(dev);
671 * Initialize all the TSEC devices
673 * Returns the number of TSEC devices that were initialized
675 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
680 for (i = 0; i < num; i++) {
681 ret = tsec_initialize(bis, &tsecs[i]);
689 int tsec_standard_init(bd_t *bis)
691 struct fsl_pq_mdio_info info;
693 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
694 info.name = DEFAULT_MII_NAME;
696 fsl_pq_mdio_init(bis, &info);
698 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));