1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale Three Speed Ethernet Controller driver
5 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
6 * (C) Copyright 2003, Motorola, Inc.
18 #include <linux/errno.h>
19 #include <asm/processor.h>
23 /* Default initializations for TSEC controllers. */
25 static struct tsec_info_struct tsec_info[] = {
27 STD_TSEC_INFO(1), /* TSEC1 */
30 STD_TSEC_INFO(2), /* TSEC2 */
32 #ifdef CONFIG_MPC85XX_FEC
34 .regs = TSEC_GET_REGS(2, 0x2000),
35 .devname = CONFIG_MPC85XX_FEC_NAME,
36 .phyaddr = FEC_PHY_ADDR,
38 .mii_devname = DEFAULT_MII_NAME
42 STD_TSEC_INFO(3), /* TSEC3 */
45 STD_TSEC_INFO(4), /* TSEC4 */
48 #endif /* CONFIG_DM_ETH */
50 #define TBIANA_SETTINGS ( \
51 TBIANA_ASYMMETRIC_PAUSE \
52 | TBIANA_SYMMETRIC_PAUSE \
53 | TBIANA_FULL_DUPLEX \
56 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
57 #ifndef CONFIG_TSEC_TBICR_SETTINGS
58 #define CONFIG_TSEC_TBICR_SETTINGS ( \
64 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
66 /* Configure the TBI for SGMII operation */
67 static void tsec_configure_serdes(struct tsec_private *priv)
70 * Access TBI PHY registers at given TSEC register offset as opposed
71 * to the register offset used for external PHY accesses
73 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
74 0, TBI_ANA, TBIANA_SETTINGS);
75 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
76 0, TBI_TBICON, TBICON_CLK_SELECT);
77 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
78 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
81 /* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
82 * and this is the ethernet-crc method needed for TSEC -- and perhaps
83 * some other adapter -- hash tables
85 #define CRCPOLY_LE 0xedb88320
86 static u32 ether_crc(size_t len, unsigned char const *p)
94 for (i = 0; i < 8; i++)
95 crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
97 /* an reverse the bits, cuz of way they arrive -- last-first */
98 crc = (crc >> 16) | (crc << 16);
99 crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
100 crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
101 crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
102 crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
106 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
108 /* Set the appropriate hash bit for the given addr */
111 * The algorithm works like so:
112 * 1) Take the Destination Address (ie the multicast address), and
113 * do a CRC on it (little endian), and reverse the bits of the
115 * 2) Use the 8 most significant bits as a hash into a 256-entry
116 * table. The table is controlled through 8 32-bit registers:
117 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
118 * 255. This means that the 3 most significant bits in the
119 * hash index which gaddr register to use, and the 5 other bits
120 * indicate which bit (assuming an IBM numbering scheme, which
121 * for PowerPC (tm) is usually the case) in the register holds
124 #ifndef CONFIG_DM_ETH
125 static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac,
128 static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
131 struct tsec_private *priv = (struct tsec_private *)dev->priv;
132 struct tsec __iomem *regs = priv->regs;
134 u8 whichbit, whichreg;
136 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
137 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
138 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
140 value = BIT(31 - whichbit);
143 setbits_be32(®s->hash.gaddr0 + whichreg, value);
145 clrbits_be32(®s->hash.gaddr0 + whichreg, value);
151 * Initialized required registers to appropriate values, zeroing
152 * those we don't care about (unless zero is bad, in which case,
153 * choose a more appropriate value)
155 static void init_registers(struct tsec __iomem *regs)
158 out_be32(®s->ievent, IEVENT_INIT_CLEAR);
160 out_be32(®s->imask, IMASK_INIT_CLEAR);
162 out_be32(®s->hash.iaddr0, 0);
163 out_be32(®s->hash.iaddr1, 0);
164 out_be32(®s->hash.iaddr2, 0);
165 out_be32(®s->hash.iaddr3, 0);
166 out_be32(®s->hash.iaddr4, 0);
167 out_be32(®s->hash.iaddr5, 0);
168 out_be32(®s->hash.iaddr6, 0);
169 out_be32(®s->hash.iaddr7, 0);
171 out_be32(®s->hash.gaddr0, 0);
172 out_be32(®s->hash.gaddr1, 0);
173 out_be32(®s->hash.gaddr2, 0);
174 out_be32(®s->hash.gaddr3, 0);
175 out_be32(®s->hash.gaddr4, 0);
176 out_be32(®s->hash.gaddr5, 0);
177 out_be32(®s->hash.gaddr6, 0);
178 out_be32(®s->hash.gaddr7, 0);
180 out_be32(®s->rctrl, 0x00000000);
182 /* Init RMON mib registers */
183 memset((void *)®s->rmon, 0, sizeof(regs->rmon));
185 out_be32(®s->rmon.cam1, 0xffffffff);
186 out_be32(®s->rmon.cam2, 0xffffffff);
188 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
190 out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
192 out_be32(®s->attr, ATTR_INIT_SETTINGS);
193 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
197 * Configure maccfg2 based on negotiated speed and duplex
198 * reported by PHY handling code
200 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
202 struct tsec __iomem *regs = priv->regs;
206 printf("%s: No link.\n", phydev->dev->name);
210 /* clear all bits relative with interface mode */
211 ecntrl = in_be32(®s->ecntrl);
212 ecntrl &= ~ECNTRL_R100;
214 maccfg2 = in_be32(®s->maccfg2);
215 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
218 maccfg2 |= MACCFG2_FULL_DUPLEX;
220 switch (phydev->speed) {
222 maccfg2 |= MACCFG2_GMII;
226 maccfg2 |= MACCFG2_MII;
229 * Set R100 bit in all modes although
230 * it is only used in RGMII mode
232 if (phydev->speed == 100)
233 ecntrl |= ECNTRL_R100;
236 printf("%s: Speed was bad\n", phydev->dev->name);
240 out_be32(®s->ecntrl, ecntrl);
241 out_be32(®s->maccfg2, maccfg2);
243 printf("Speed: %d, %s duplex%s\n", phydev->speed,
244 (phydev->duplex) ? "full" : "half",
245 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
249 * This returns the status bits of the device. The return value
250 * is never checked, and this is what the 8260 driver did, so we
251 * do the same. Presumably, this would be zero if there were no
254 #ifndef CONFIG_DM_ETH
255 static int tsec_send(struct eth_device *dev, void *packet, int length)
257 static int tsec_send(struct udevice *dev, void *packet, int length)
260 struct tsec_private *priv = (struct tsec_private *)dev->priv;
261 struct tsec __iomem *regs = priv->regs;
266 /* Find an empty buffer descriptor */
268 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
270 if (i >= TOUT_LOOP) {
271 debug("%s: tsec: tx buffers full\n", dev->name);
276 out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
277 out_be16(&priv->txbd[priv->tx_idx].length, length);
278 status = in_be16(&priv->txbd[priv->tx_idx].status);
279 out_be16(&priv->txbd[priv->tx_idx].status, status |
280 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
282 /* Tell the DMA to go */
283 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
285 /* Wait for buffer to be transmitted */
287 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
289 if (i >= TOUT_LOOP) {
290 debug("%s: tsec: tx error\n", dev->name);
295 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
296 result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
301 #ifndef CONFIG_DM_ETH
302 static int tsec_recv(struct eth_device *dev)
304 struct tsec_private *priv = (struct tsec_private *)dev->priv;
305 struct tsec __iomem *regs = priv->regs;
307 while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
308 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
309 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
310 uchar *packet = net_rx_packets[priv->rx_idx];
312 /* Send the packet up if there were no errors */
313 if (!(status & RXBD_STATS))
314 net_process_received_packet(packet, length - 4);
316 printf("Got error %x\n", (status & RXBD_STATS));
318 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
321 /* Set the wrap bit if this is the last element in the list */
322 if ((priv->rx_idx + 1) == PKTBUFSRX)
324 out_be16(&priv->rxbd[priv->rx_idx].status, status);
326 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
329 if (in_be32(®s->ievent) & IEVENT_BSY) {
330 out_be32(®s->ievent, IEVENT_BSY);
331 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
337 static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
339 struct tsec_private *priv = (struct tsec_private *)dev->priv;
340 struct tsec __iomem *regs = priv->regs;
343 if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
344 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
345 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
348 /* Send the packet up if there were no errors */
349 if (!(status & RXBD_STATS)) {
350 buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
351 *packetp = (uchar *)buf;
354 printf("Got error %x\n", (status & RXBD_STATS));
358 if (in_be32(®s->ievent) & IEVENT_BSY) {
359 out_be32(®s->ievent, IEVENT_BSY);
360 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
366 static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
368 struct tsec_private *priv = (struct tsec_private *)dev->priv;
371 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
374 /* Set the wrap bit if this is the last element in the list */
375 if ((priv->rx_idx + 1) == PKTBUFSRX)
377 out_be16(&priv->rxbd[priv->rx_idx].status, status);
379 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
385 /* Stop the interface */
386 #ifndef CONFIG_DM_ETH
387 static void tsec_halt(struct eth_device *dev)
389 static void tsec_halt(struct udevice *dev)
392 struct tsec_private *priv = (struct tsec_private *)dev->priv;
393 struct tsec __iomem *regs = priv->regs;
395 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
396 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
398 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
399 != (IEVENT_GRSC | IEVENT_GTSC))
402 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
404 /* Shut down the PHY, as needed */
405 phy_shutdown(priv->phydev);
408 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
410 * When MACCFG1[Rx_EN] is enabled during system boot as part
411 * of the eTSEC port initialization sequence,
412 * the eTSEC Rx logic may not be properly initialized.
414 void redundant_init(struct tsec_private *priv)
416 struct tsec __iomem *regs = priv->regs;
419 static const u8 pkt[] = {
420 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
421 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
422 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
423 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
424 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
425 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
426 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
427 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
428 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
429 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
430 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
431 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
432 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
435 /* Enable promiscuous mode */
436 setbits_be32(®s->rctrl, 0x8);
437 /* Enable loopback mode */
438 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
439 /* Enable transmit and receive */
440 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
442 /* Tell the DMA it is clear to go */
443 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
444 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
445 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
446 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
451 tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
453 /* Wait for buffer to be received */
455 in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
457 if (t >= 10 * TOUT_LOOP) {
458 printf("%s: tsec: rx error\n", priv->dev->name);
463 if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
466 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
468 if ((priv->rx_idx + 1) == PKTBUFSRX)
470 out_be16(&priv->rxbd[priv->rx_idx].status, status);
471 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
473 if (in_be32(®s->ievent) & IEVENT_BSY) {
474 out_be32(®s->ievent, IEVENT_BSY);
475 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
478 printf("loopback recv packet error!\n");
479 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
481 setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
483 } while ((count++ < 4) && (fail == 1));
486 panic("eTSEC init fail!\n");
487 /* Disable promiscuous mode */
488 clrbits_be32(®s->rctrl, 0x8);
489 /* Disable loopback mode */
490 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
495 * Set up the buffers and their descriptors, and bring up the
498 static void startup_tsec(struct tsec_private *priv)
500 struct tsec __iomem *regs = priv->regs;
504 /* reset the indices to zero */
507 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
511 /* Point to the buffer descriptors */
512 out_be32(®s->tbase, (u32)&priv->txbd[0]);
513 out_be32(®s->rbase, (u32)&priv->rxbd[0]);
515 /* Initialize the Rx Buffer descriptors */
516 for (i = 0; i < PKTBUFSRX; i++) {
517 out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
518 out_be16(&priv->rxbd[i].length, 0);
519 out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
521 status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
522 out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
524 /* Initialize the TX Buffer Descriptors */
525 for (i = 0; i < TX_BUF_CNT; i++) {
526 out_be16(&priv->txbd[i].status, 0);
527 out_be16(&priv->txbd[i].length, 0);
528 out_be32(&priv->txbd[i].bufptr, 0);
530 status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
531 out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
533 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
535 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
536 redundant_init(priv);
538 /* Enable Transmit and Receive */
539 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
541 /* Tell the DMA it is clear to go */
542 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
543 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
544 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
545 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
549 * Initializes data structures and registers for the controller,
550 * and brings the interface up. Returns the link status, meaning
551 * that it returns success if the link is up, failure otherwise.
552 * This allows U-Boot to find the first active controller.
554 #ifndef CONFIG_DM_ETH
555 static int tsec_init(struct eth_device *dev, bd_t *bd)
557 static int tsec_init(struct udevice *dev)
560 struct tsec_private *priv = (struct tsec_private *)dev->priv;
562 struct eth_pdata *pdata = dev_get_platdata(dev);
564 struct tsec __iomem *regs = priv->regs;
568 /* Make sure the controller is stopped */
571 /* Init MACCFG2. Defaults to GMII */
572 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
575 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
578 * Copy the station address into the address registers.
579 * For a station address of 0x12345678ABCD in transmission
580 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
581 * MACnADDR2 is set to 0x34120000.
583 #ifndef CONFIG_DM_ETH
584 tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
585 (dev->enetaddr[3] << 8) | dev->enetaddr[2];
587 tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
588 (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
591 out_be32(®s->macstnaddr1, tempval);
593 #ifndef CONFIG_DM_ETH
594 tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
596 tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
599 out_be32(®s->macstnaddr2, tempval);
601 /* Clear out (for the most part) the other registers */
602 init_registers(regs);
604 /* Ready the device for tx/rx */
607 /* Start up the PHY */
608 ret = phy_startup(priv->phydev);
610 printf("Could not initialize PHY %s\n",
611 priv->phydev->dev->name);
615 adjust_link(priv, priv->phydev);
617 /* If there's no link, fail */
618 return priv->phydev->link ? 0 : -1;
621 static phy_interface_t tsec_get_interface(struct tsec_private *priv)
623 struct tsec __iomem *regs = priv->regs;
626 ecntrl = in_be32(®s->ecntrl);
628 if (ecntrl & ECNTRL_SGMII_MODE)
629 return PHY_INTERFACE_MODE_SGMII;
631 if (ecntrl & ECNTRL_TBI_MODE) {
632 if (ecntrl & ECNTRL_REDUCED_MODE)
633 return PHY_INTERFACE_MODE_RTBI;
635 return PHY_INTERFACE_MODE_TBI;
638 if (ecntrl & ECNTRL_REDUCED_MODE) {
639 phy_interface_t interface;
641 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
642 return PHY_INTERFACE_MODE_RMII;
644 interface = priv->interface;
647 * This isn't autodetected, so it must
648 * be set by the platform code.
650 if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
651 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
652 interface == PHY_INTERFACE_MODE_RGMII_RXID)
655 return PHY_INTERFACE_MODE_RGMII;
658 if (priv->flags & TSEC_GIGABIT)
659 return PHY_INTERFACE_MODE_GMII;
661 return PHY_INTERFACE_MODE_MII;
665 * Discover which PHY is attached to the device, and configure it
666 * properly. If the PHY is not recognized, then return 0
667 * (failure). Otherwise, return 1
669 static int init_phy(struct tsec_private *priv)
671 struct phy_device *phydev;
672 struct tsec __iomem *regs = priv->regs;
673 u32 supported = (SUPPORTED_10baseT_Half |
674 SUPPORTED_10baseT_Full |
675 SUPPORTED_100baseT_Half |
676 SUPPORTED_100baseT_Full);
678 if (priv->flags & TSEC_GIGABIT)
679 supported |= SUPPORTED_1000baseT_Full;
681 /* Assign a Physical address to the TBI */
682 out_be32(®s->tbipa, priv->tbiaddr);
684 priv->interface = tsec_get_interface(priv);
686 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
687 tsec_configure_serdes(priv);
689 phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
694 phydev->supported &= supported;
695 phydev->advertising = phydev->supported;
697 priv->phydev = phydev;
704 #ifndef CONFIG_DM_ETH
706 * Initialize device structure. Returns success if PHY
707 * initialization succeeded (i.e. if it recognizes the PHY)
709 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
711 struct eth_device *dev;
713 struct tsec_private *priv;
715 dev = (struct eth_device *)malloc(sizeof(*dev));
720 memset(dev, 0, sizeof(*dev));
722 priv = (struct tsec_private *)malloc(sizeof(*priv));
729 priv->regs = tsec_info->regs;
730 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
732 priv->phyaddr = tsec_info->phyaddr;
733 priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
734 priv->flags = tsec_info->flags;
736 strcpy(dev->name, tsec_info->devname);
737 priv->interface = tsec_info->interface;
738 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
742 dev->init = tsec_init;
743 dev->halt = tsec_halt;
744 dev->send = tsec_send;
745 dev->recv = tsec_recv;
746 dev->mcast = tsec_mcast_addr;
748 /* Tell U-Boot to get the addr from the env */
749 for (i = 0; i < 6; i++)
750 dev->enetaddr[i] = 0;
755 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
756 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
757 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
759 /* Try to initialize PHY here, and return */
760 return init_phy(priv);
764 * Initialize all the TSEC devices
766 * Returns the number of TSEC devices that were initialized
768 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
773 for (i = 0; i < num; i++) {
774 int ret = tsec_initialize(bis, &tsecs[i]);
783 int tsec_standard_init(bd_t *bis)
785 struct fsl_pq_mdio_info info;
787 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
788 info.name = DEFAULT_MII_NAME;
790 fsl_pq_mdio_init(bis, &info);
792 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
794 #else /* CONFIG_DM_ETH */
795 int tsec_probe(struct udevice *dev)
797 struct tsec_private *priv = dev_get_priv(dev);
798 struct eth_pdata *pdata = dev_get_platdata(dev);
799 struct fsl_pq_mdio_info mdio_info;
800 struct ofnode_phandle_args phandle_args;
802 const char *phy_mode;
805 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
806 priv->regs = (struct tsec *)pdata->iobase;
808 if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
810 debug("phy-handle does not exist under tsec %s\n", dev->name);
813 int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
818 parent = ofnode_get_parent(phandle_args.node);
819 if (ofnode_valid(parent)) {
820 int reg = ofnode_get_addr_index(parent, 0);
822 priv->phyregs_sgmii = (struct tsec_mii_mng *)reg;
824 debug("No parent node for PHY?\n");
828 if (dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
830 priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
832 int reg = ofnode_read_u32_default(phandle_args.node, "reg",
833 CONFIG_SYS_TBIPA_VALUE);
837 phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
839 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
840 if (pdata->phy_interface == -1) {
841 debug("Invalid PHY interface '%s'\n", phy_mode);
844 priv->interface = pdata->phy_interface;
846 /* Initialize flags */
847 priv->flags = TSEC_GIGABIT;
848 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
849 priv->flags |= TSEC_SGMII;
851 mdio_info.regs = priv->phyregs_sgmii;
852 mdio_info.name = (char *)dev->name;
853 ret = fsl_pq_mdio_init(NULL, &mdio_info);
858 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
859 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
860 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
863 priv->bus = miiphy_get_dev_by_name(dev->name);
865 /* Try to initialize PHY here, and return */
866 return !init_phy(priv);
869 int tsec_remove(struct udevice *dev)
871 struct tsec_private *priv = dev->priv;
874 mdio_unregister(priv->bus);
875 mdio_free(priv->bus);
880 static const struct eth_ops tsec_ops = {
884 .free_pkt = tsec_free_pkt,
886 .mcast = tsec_mcast_addr,
889 static const struct udevice_id tsec_ids[] = {
890 { .compatible = "fsl,tsec" },
894 U_BOOT_DRIVER(eth_tsec) = {
897 .of_match = tsec_ids,
899 .remove = tsec_remove,
901 .priv_auto_alloc_size = sizeof(struct tsec_private),
902 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
903 .flags = DM_FLAG_ALLOC_PRIV_DMA,
905 #endif /* CONFIG_DM_ETH */