drivers/net/tigon3.c

   1 /******************************************************************************/
   2 /*                                                                            */
   3 /* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom         */
   4 /* Corporation.                                                               */
   5 /* All rights reserved.                                                       */
   6 /*                                                                            */
   7 /* This program is free software; you can redistribute it and/or modify       */
   8 /* it under the terms of the GNU General Public License as published by       */
   9 /* the Free Software Foundation, located in the file LICENSE.                 */
  10 /*                                                                            */
  11 /* History:                                                                   */
  12 /******************************************************************************/
  13 #include <common.h>
  14 #include <asm/types.h>
  15 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_NET_MULTI) && \
  16         defined(CONFIG_TIGON3)
  17 #ifdef CONFIG_BMW
  18 #include <mpc824x.h>
  19 #endif
  20 #include <malloc.h>
  21 #include <linux/byteorder/big_endian.h>
  22 #include "bcm570x_mm.h"
  23
  24 #define EMBEDDED 1
  25 /******************************************************************************/
  26 /* Local functions. */
  27 /******************************************************************************/
  28
  29 LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice);
  30 LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice);
  31
  32 static LM_STATUS LM_TranslateRequestedMediaType (LM_REQUESTED_MEDIA_TYPE
  33                                                  RequestedMediaType,
  34                                                  PLM_MEDIA_TYPE pMediaType,
  35                                                  PLM_LINE_SPEED pLineSpeed,
  36                                                  PLM_DUPLEX_MODE pDuplexMode);
  37
  38 static LM_STATUS LM_InitBcm540xPhy (PLM_DEVICE_BLOCK pDevice);
  39
  40 __inline static LM_VOID LM_ServiceRxInterrupt (PLM_DEVICE_BLOCK pDevice);
  41 __inline static LM_VOID LM_ServiceTxInterrupt (PLM_DEVICE_BLOCK pDevice);
  42
  43 static LM_STATUS LM_ForceAutoNegBcm540xPhy (PLM_DEVICE_BLOCK pDevice,
  44                                             LM_REQUESTED_MEDIA_TYPE
  45                                             RequestedMediaType);
  46 static LM_STATUS LM_ForceAutoNeg (PLM_DEVICE_BLOCK pDevice,
  47                                   LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
  48 static LM_UINT32 GetPhyAdFlowCntrlSettings (PLM_DEVICE_BLOCK pDevice);
  49 STATIC LM_STATUS LM_SetFlowControl (PLM_DEVICE_BLOCK pDevice,
  50                                     LM_UINT32 LocalPhyAd,
  51                                     LM_UINT32 RemotePhyAd);
  52 #if INCLUDE_TBI_SUPPORT
  53 STATIC LM_STATUS LM_SetupFiberPhy (PLM_DEVICE_BLOCK pDevice);
  54 STATIC LM_STATUS LM_InitBcm800xPhy (PLM_DEVICE_BLOCK pDevice);
  55 #endif
  56 STATIC LM_STATUS LM_SetupCopperPhy (PLM_DEVICE_BLOCK pDevice);
  57 STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid (LM_UINT16 Svid,
  58                                                  LM_UINT16 Ssid);
  59 STATIC LM_STATUS LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
  60                              LM_PHYSICAL_ADDRESS BufferPhy,
  61                              LM_UINT32 BufferSize);
  62 STATIC LM_STATUS LM_HaltCpu (PLM_DEVICE_BLOCK pDevice, LM_UINT32 cpu_number);
  63 STATIC LM_STATUS LM_ResetChip (PLM_DEVICE_BLOCK pDevice);
  64 STATIC LM_STATUS LM_Test4GBoundary (PLM_DEVICE_BLOCK pDevice,
  65                                     PLM_PACKET pPacket, PT3_SND_BD pSendBd);
  66
  67 /******************************************************************************/
  68 /* External functions. */
  69 /******************************************************************************/
  70
  71 LM_STATUS LM_LoadRlsFirmware (PLM_DEVICE_BLOCK pDevice);
  72
  73 /******************************************************************************/
  74 /* Description:                                                               */
  75 /*                                                                            */
  76 /* Return:                                                                    */
  77 /******************************************************************************/
  78 LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register)
  79 {
  80         LM_UINT32 Value32;
  81
  82 #if PCIX_TARGET_WORKAROUND
  83         MM_ACQUIRE_UNDI_LOCK (pDevice);
  84 #endif
  85         MM_WriteConfig32 (pDevice, T3_PCI_REG_ADDR_REG, Register);
  86         MM_ReadConfig32 (pDevice, T3_PCI_REG_DATA_REG, &Value32);
  87 #if PCIX_TARGET_WORKAROUND
  88         MM_RELEASE_UNDI_LOCK (pDevice);
  89 #endif
  90
  91         return Value32;
  92 }                               /* LM_RegRdInd */
  93
  94 /******************************************************************************/
  95 /* Description:                                                               */
  96 /*                                                                            */
  97 /* Return:                                                                    */
  98 /******************************************************************************/
  99 LM_VOID
 100 LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, LM_UINT32 Value32)
 101 {
 102
 103 #if PCIX_TARGET_WORKAROUND
 104         MM_ACQUIRE_UNDI_LOCK (pDevice);
 105 #endif
 106         MM_WriteConfig32 (pDevice, T3_PCI_REG_ADDR_REG, Register);
 107         MM_WriteConfig32 (pDevice, T3_PCI_REG_DATA_REG, Value32);
 108 #if PCIX_TARGET_WORKAROUND
 109         MM_RELEASE_UNDI_LOCK (pDevice);
 110 #endif
 111 }                               /* LM_RegWrInd */
 112
 113 /******************************************************************************/
 114 /* Description:                                                               */
 115 /*                                                                            */
 116 /* Return:                                                                    */
 117 /******************************************************************************/
 118 LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr)
 119 {
 120         LM_UINT32 Value32;
 121
 122         MM_ACQUIRE_UNDI_LOCK (pDevice);
 123 #ifdef BIG_ENDIAN_HOST
 124         MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
 125         Value32 = REG_RD (pDevice, PciCfg.MemWindowData);
 126         /*    Value32 = REG_RD(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4]); */
 127 #else
 128         MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
 129         MM_ReadConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32);
 130 #endif
 131         MM_RELEASE_UNDI_LOCK (pDevice);
 132
 133         return Value32;
 134 }                               /* LM_MemRdInd */
 135
 136 /******************************************************************************/
 137 /* Description:                                                               */
 138 /*                                                                            */
 139 /* Return:                                                                    */
 140 /******************************************************************************/
 141 LM_VOID
 142 LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, LM_UINT32 Value32)
 143 {
 144         MM_ACQUIRE_UNDI_LOCK (pDevice);
 145 #ifdef BIG_ENDIAN_HOST
 146         REG_WR (pDevice, PciCfg.MemWindowBaseAddr, MemAddr);
 147         REG_WR (pDevice, uIntMem.Mbuf[(MemAddr & 0x7fff) / 4], Value32);
 148 #else
 149         MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
 150         MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, Value32);
 151 #endif
 152         MM_RELEASE_UNDI_LOCK (pDevice);
 153 }                               /* LM_MemWrInd */
 154
 155 /******************************************************************************/
 156 /* Description:                                                               */
 157 /*                                                                            */
 158 /* Return:                                                                    */
 159 /******************************************************************************/
 160 LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice)
 161 {
 162         LM_STATUS Lmstatus;
 163         PLM_PACKET pPacket;
 164         PT3_RCV_BD pRcvBd;
 165         LM_UINT32 StdBdAdded = 0;
 166 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 167         LM_UINT32 JumboBdAdded = 0;
 168 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
 169
 170         Lmstatus = LM_STATUS_SUCCESS;
 171
 172         pPacket = (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
 173         while (pPacket) {
 174                 switch (pPacket->u.Rx.RcvProdRing) {
 175 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 176                 case T3_JUMBO_RCV_PROD_RING:    /* Jumbo Receive Ring. */
 177                         /* Initialize the buffer descriptor. */
 178                         pRcvBd =
 179                             &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx];
 180                         pRcvBd->Flags =
 181                             RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING;
 182                         pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize;
 183
 184                         /* Initialize the receive buffer pointer */
 185 #if 0                           /* Jimmy, deleted in new */
 186                         pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
 187                         pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;
 188 #endif
 189                         MM_MapRxDma (pDevice, pPacket, &pRcvBd->HostAddr);
 190
 191                         /* The opaque field may point to an offset from a fix addr. */
 192                         pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR (pPacket) -
 193                                                       MM_UINT_PTR (pDevice->
 194                                                                    pPacketDescBase));
 195
 196                         /* Update the producer index. */
 197                         pDevice->RxJumboProdIdx =
 198                             (pDevice->RxJumboProdIdx +
 199                              1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
 200
 201                         JumboBdAdded++;
 202                         break;
 203 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
 204
 205                 case T3_STD_RCV_PROD_RING:      /* Standard Receive Ring. */
 206                         /* Initialize the buffer descriptor. */
 207                         pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx];
 208                         pRcvBd->Flags = RCV_BD_FLAG_END;
 209                         pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE;
 210
 211                         /* Initialize the receive buffer pointer */
 212 #if 0                           /* Jimmy, deleted in new replaced with MM_MapRxDma */
 213                         pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
 214                         pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;
 215 #endif
 216                         MM_MapRxDma (pDevice, pPacket, &pRcvBd->HostAddr);
 217
 218                         /* The opaque field may point to an offset from a fix addr. */
 219                         pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR (pPacket) -
 220                                                       MM_UINT_PTR (pDevice->
 221                                                                    pPacketDescBase));
 222
 223                         /* Update the producer index. */
 224                         pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) &
 225                             T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
 226
 227                         StdBdAdded++;
 228                         break;
 229
 230                 case T3_UNKNOWN_RCV_PROD_RING:
 231                 default:
 232                         Lmstatus = LM_STATUS_FAILURE;
 233                         break;
 234                 }               /* switch */
 235
 236                 /* Bail out if there is any error. */
 237                 if (Lmstatus != LM_STATUS_SUCCESS) {
 238                         break;
 239                 }
 240
 241                 pPacket =
 242                     (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
 243         }                       /* while */
 244
 245         wmb ();
 246         /* Update the procedure index. */
 247         if (StdBdAdded) {
 248                 MB_REG_WR (pDevice, Mailbox.RcvStdProdIdx.Low,
 249                            pDevice->RxStdProdIdx);
 250         }
 251 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 252         if (JumboBdAdded) {
 253                 MB_REG_WR (pDevice, Mailbox.RcvJumboProdIdx.Low,
 254                            pDevice->RxJumboProdIdx);
 255         }
 256 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
 257
 258         return Lmstatus;
 259 }                               /* LM_QueueRxPackets */
 260
 261 /******************************************************************************/
 262 /* Description:                                                               */
 263 /*                                                                            */
 264 /* Return:                                                                    */
 265 /******************************************************************************/
 266 STATIC LM_VOID LM_NvramInit (PLM_DEVICE_BLOCK pDevice)
 267 {
 268         LM_UINT32 Value32;
 269         LM_UINT32 j;
 270
 271         /* Intialize clock period and state machine. */
 272         Value32 = SEEPROM_ADDR_CLK_PERD (SEEPROM_CLOCK_PERIOD) |
 273             SEEPROM_ADDR_FSM_RESET;
 274         REG_WR (pDevice, Grc.EepromAddr, Value32);
 275
 276         for (j = 0; j < 100; j++) {
 277                 MM_Wait (10);
 278         }
 279
 280         /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */
 281         Value32 = REG_RD (pDevice, Grc.LocalCtrl);
 282         REG_WR (pDevice, Grc.LocalCtrl,
 283                 Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM);
 284
 285         /* Set the 5701 compatibility mode if we are using EEPROM. */
 286         if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
 287             T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
 288                 Value32 = REG_RD (pDevice, Nvram.Config1);
 289                 if ((Value32 & FLASH_INTERFACE_ENABLE) == 0) {
 290                         /* Use the new interface to read EEPROM. */
 291                         Value32 &= ~FLASH_COMPAT_BYPASS;
 292
 293                         REG_WR (pDevice, Nvram.Config1, Value32);
 294                 }
 295         }
 296 }                               /* LM_NvRamInit */
 297
 298 /******************************************************************************/
 299 /* Description:                                                               */
 300 /*                                                                            */
 301 /* Return:                                                                    */
 302 /******************************************************************************/
 303 STATIC LM_STATUS
 304 LM_EepromRead (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 * pData)
 305 {
 306         LM_UINT32 Value32;
 307         LM_UINT32 Addr;
 308         LM_UINT32 Dev;
 309         LM_UINT32 j;
 310
 311         if (Offset > SEEPROM_CHIP_SIZE) {
 312                 return LM_STATUS_FAILURE;
 313         }
 314
 315         Dev = Offset / SEEPROM_CHIP_SIZE;
 316         Addr = Offset % SEEPROM_CHIP_SIZE;
 317
 318         Value32 = REG_RD (pDevice, Grc.EepromAddr);
 319         Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK |
 320                      SEEPROM_ADDR_RW_MASK);
 321         REG_WR (pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID (Dev) |
 322                 SEEPROM_ADDR_ADDRESS (Addr) | SEEPROM_ADDR_START |
 323                 SEEPROM_ADDR_READ);
 324
 325         for (j = 0; j < 1000; j++) {
 326                 Value32 = REG_RD (pDevice, Grc.EepromAddr);
 327                 if (Value32 & SEEPROM_ADDR_COMPLETE) {
 328                         break;
 329                 }
 330                 MM_Wait (10);
 331         }
 332
 333         if (Value32 & SEEPROM_ADDR_COMPLETE) {
 334                 Value32 = REG_RD (pDevice, Grc.EepromData);
 335                 *pData = Value32;
 336
 337                 return LM_STATUS_SUCCESS;
 338         }
 339
 340         return LM_STATUS_FAILURE;
 341 }                               /* LM_EepromRead */
 342
 343 /******************************************************************************/
 344 /* Description:                                                               */
 345 /*                                                                            */
 346 /* Return:                                                                    */
 347 /******************************************************************************/
 348 STATIC LM_STATUS
 349 LM_NvramRead (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 * pData)
 350 {
 351         LM_UINT32 Value32;
 352         LM_STATUS Status;
 353         LM_UINT32 j;
 354
 355         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
 356             T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
 357                 Status = LM_EepromRead (pDevice, Offset, pData);
 358         } else {
 359                 /* Determine if we have flash or EEPROM. */
 360                 Value32 = REG_RD (pDevice, Nvram.Config1);
 361                 if (Value32 & FLASH_INTERFACE_ENABLE) {
 362                         if (Value32 & FLASH_SSRAM_BUFFERRED_MODE) {
 363                                 Offset = ((Offset / BUFFERED_FLASH_PAGE_SIZE) <<
 364                                           BUFFERED_FLASH_PAGE_POS) +
 365                                     (Offset % BUFFERED_FLASH_PAGE_SIZE);
 366                         }
 367                 }
 368
 369                 REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
 370                 for (j = 0; j < 1000; j++) {
 371                         if (REG_RD (pDevice, Nvram.SwArb) & SW_ARB_GNT1) {
 372                                 break;
 373                         }
 374                         MM_Wait (20);
 375                 }
 376                 if (j == 1000) {
 377                         return LM_STATUS_FAILURE;
 378                 }
 379
 380                 /* Read from flash or EEPROM with the new 5703/02 interface. */
 381                 REG_WR (pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK);
 382
 383                 REG_WR (pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT |
 384                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
 385
 386                 /* Wait for the done bit to clear. */
 387                 for (j = 0; j < 500; j++) {
 388                         MM_Wait (10);
 389
 390                         Value32 = REG_RD (pDevice, Nvram.Cmd);
 391                         if (!(Value32 & NVRAM_CMD_DONE)) {
 392                                 break;
 393                         }
 394                 }
 395
 396                 /* Wait for the done bit. */
 397                 if (!(Value32 & NVRAM_CMD_DONE)) {
 398                         for (j = 0; j < 500; j++) {
 399                                 MM_Wait (10);
 400
 401                                 Value32 = REG_RD (pDevice, Nvram.Cmd);
 402                                 if (Value32 & NVRAM_CMD_DONE) {
 403                                         MM_Wait (10);
 404
 405                                         *pData =
 406                                             REG_RD (pDevice, Nvram.ReadData);
 407
 408                                         /* Change the endianess. */
 409                                         *pData =
 410                                             ((*pData & 0xff) << 24) |
 411                                             ((*pData & 0xff00) << 8) |
 412                                             ((*pData & 0xff0000) >> 8) |
 413                                             ((*pData >> 24) & 0xff);
 414
 415                                         break;
 416                                 }
 417                         }
 418                 }
 419
 420                 REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1);
 421                 if (Value32 & NVRAM_CMD_DONE) {
 422                         Status = LM_STATUS_SUCCESS;
 423                 } else {
 424                         Status = LM_STATUS_FAILURE;
 425                 }
 426         }
 427
 428         return Status;
 429 }                               /* LM_NvramRead */
 430
 431 STATIC void LM_ReadVPD (PLM_DEVICE_BLOCK pDevice)
 432 {
 433         LM_UINT32 Vpd_arr[256 / 4];
 434         LM_UINT8 *Vpd = (LM_UINT8 *) & Vpd_arr[0];
 435         LM_UINT32 *Vpd_dptr = &Vpd_arr[0];
 436         LM_UINT32 Value32;
 437         unsigned int j;
 438
 439         /* Read PN from VPD */
 440         for (j = 0; j < 256; j += 4, Vpd_dptr++) {
 441                 if (LM_NvramRead (pDevice, 0x100 + j, &Value32) !=
 442                     LM_STATUS_SUCCESS) {
 443                         printf ("BCM570x: LM_ReadVPD: VPD read failed"
 444                                 " (no EEPROM onboard)\n");
 445                         return;
 446                 }
 447                 *Vpd_dptr = cpu_to_le32 (Value32);
 448         }
 449         for (j = 0; j < 256;) {
 450                 unsigned int Vpd_r_len;
 451                 unsigned int Vpd_r_end;
 452
 453                 if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91)) {
 454                         j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8);
 455                 } else if (Vpd[j] == 0x90) {
 456                         Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8);
 457                         j += 3;
 458                         Vpd_r_end = Vpd_r_len + j;
 459                         while (j < Vpd_r_end) {
 460                                 if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N')) {
 461                                         unsigned int len = Vpd[j + 2];
 462
 463                                         if (len <= 24) {
 464                                                 memcpy (pDevice->PartNo,
 465                                                         &Vpd[j + 3], len);
 466                                         }
 467                                         break;
 468                                 } else {
 469                                         if (Vpd[j + 2] == 0) {
 470                                                 break;
 471                                         }
 472                                         j = j + Vpd[j + 2];
 473                                 }
 474                         }
 475                         break;
 476                 } else {
 477                         break;
 478                 }
 479         }
 480 }
 481
 482 STATIC void LM_ReadBootCodeVersion (PLM_DEVICE_BLOCK pDevice)
 483 {
 484         LM_UINT32 Value32, offset, ver_offset;
 485         int i;
 486
 487         if (LM_NvramRead (pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS)
 488                 return;
 489         if (Value32 != 0xaa559966)
 490                 return;
 491         if (LM_NvramRead (pDevice, 0xc, &offset) != LM_STATUS_SUCCESS)
 492                 return;
 493
 494         offset = ((offset & 0xff) << 24) | ((offset & 0xff00) << 8) |
 495             ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff);
 496         if (LM_NvramRead (pDevice, offset, &Value32) != LM_STATUS_SUCCESS)
 497                 return;
 498         if ((Value32 == 0x0300000e) &&
 499             (LM_NvramRead (pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS)
 500             && (Value32 == 0)) {
 501
 502                 if (LM_NvramRead (pDevice, offset + 8, &ver_offset) !=
 503                     LM_STATUS_SUCCESS)
 504                         return;
 505                 ver_offset = ((ver_offset & 0xff0000) >> 8) |
 506                     ((ver_offset >> 24) & 0xff);
 507                 for (i = 0; i < 16; i += 4) {
 508                         if (LM_NvramRead
 509                             (pDevice, offset + ver_offset + i,
 510                              &Value32) != LM_STATUS_SUCCESS) {
 511                                 return;
 512                         }
 513                         *((LM_UINT32 *) & pDevice->BootCodeVer[i]) =
 514                             cpu_to_le32 (Value32);
 515                 }
 516         } else {
 517                 char c;
 518
 519                 if (LM_NvramRead (pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS)
 520                         return;
 521
 522                 i = 0;
 523                 c = ((Value32 & 0xff0000) >> 16);
 524
 525                 if (c < 10) {
 526                         pDevice->BootCodeVer[i++] = c + '0';
 527                 } else {
 528                         pDevice->BootCodeVer[i++] = (c / 10) + '0';
 529                         pDevice->BootCodeVer[i++] = (c % 10) + '0';
 530                 }
 531                 pDevice->BootCodeVer[i++] = '.';
 532                 c = (Value32 & 0xff000000) >> 24;
 533                 if (c < 10) {
 534                         pDevice->BootCodeVer[i++] = c + '0';
 535                 } else {
 536                         pDevice->BootCodeVer[i++] = (c / 10) + '0';
 537                         pDevice->BootCodeVer[i++] = (c % 10) + '0';
 538                 }
 539                 pDevice->BootCodeVer[i] = 0;
 540         }
 541 }
 542
 543 STATIC void LM_GetBusSpeed (PLM_DEVICE_BLOCK pDevice)
 544 {
 545         LM_UINT32 PciState = pDevice->PciState;
 546         LM_UINT32 ClockCtrl;
 547         char *SpeedStr = "";
 548
 549         if (PciState & T3_PCI_STATE_32BIT_PCI_BUS) {
 550                 strcpy (pDevice->BusSpeedStr, "32-bit ");
 551         } else {
 552                 strcpy (pDevice->BusSpeedStr, "64-bit ");
 553         }
 554         if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) {
 555                 strcat (pDevice->BusSpeedStr, "PCI ");
 556                 if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED) {
 557                         SpeedStr = "66MHz";
 558                 } else {
 559                         SpeedStr = "33MHz";
 560                 }
 561         } else {
 562                 strcat (pDevice->BusSpeedStr, "PCIX ");
 563                 if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE) {
 564                         SpeedStr = "133MHz";
 565                 } else {
 566                         ClockCtrl = REG_RD (pDevice, PciCfg.ClockCtrl) & 0x1f;
 567                         switch (ClockCtrl) {
 568                         case 0:
 569                                 SpeedStr = "33MHz";
 570                                 break;
 571
 572                         case 2:
 573                                 SpeedStr = "50MHz";
 574                                 break;
 575
 576                         case 4:
 577                                 SpeedStr = "66MHz";
 578                                 break;
 579
 580                         case 6:
 581                                 SpeedStr = "100MHz";
 582                                 break;
 583
 584                         case 7:
 585                                 SpeedStr = "133MHz";
 586                                 break;
 587                         }
 588                 }
 589         }
 590         strcat (pDevice->BusSpeedStr, SpeedStr);
 591 }
 592
 593 /******************************************************************************/
 594 /* Description:                                                               */
 595 /*    This routine initializes default parameters and reads the PCI           */
 596 /*    configurations.                                                         */
 597 /*                                                                            */
 598 /* Return:                                                                    */
 599 /*    LM_STATUS_SUCCESS                                                       */
 600 /******************************************************************************/
 601 LM_STATUS LM_GetAdapterInfo (PLM_DEVICE_BLOCK pDevice)
 602 {
 603         PLM_ADAPTER_INFO pAdapterInfo;
 604         LM_UINT32 Value32;
 605         LM_STATUS Status;
 606         LM_UINT32 j;
 607         LM_UINT32 EeSigFound;
 608         LM_UINT32 EePhyTypeSerdes = 0;
 609         LM_UINT32 EePhyLedMode = 0;
 610         LM_UINT32 EePhyId = 0;
 611
 612         /* Get Device Id and Vendor Id */
 613         Status = MM_ReadConfig32 (pDevice, PCI_VENDOR_ID_REG, &Value32);
 614         if (Status != LM_STATUS_SUCCESS) {
 615                 return Status;
 616         }
 617         pDevice->PciVendorId = (LM_UINT16) Value32;
 618         pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16);
 619
 620         /* If we are not getting the write adapter, exit. */
 621         if ((Value32 != T3_PCI_ID_BCM5700) &&
 622             (Value32 != T3_PCI_ID_BCM5701) &&
 623             (Value32 != T3_PCI_ID_BCM5702) &&
 624             (Value32 != T3_PCI_ID_BCM5702x) &&
 625             (Value32 != T3_PCI_ID_BCM5702FE) &&
 626             (Value32 != T3_PCI_ID_BCM5703) &&
 627             (Value32 != T3_PCI_ID_BCM5703x) && (Value32 != T3_PCI_ID_BCM5704)) {
 628                 return LM_STATUS_FAILURE;
 629         }
 630
 631         Status = MM_ReadConfig32 (pDevice, PCI_REV_ID_REG, &Value32);
 632         if (Status != LM_STATUS_SUCCESS) {
 633                 return Status;
 634         }
 635         pDevice->PciRevId = (LM_UINT8) Value32;
 636
 637         /* Get IRQ. */
 638         Status = MM_ReadConfig32 (pDevice, PCI_INT_LINE_REG, &Value32);
 639         if (Status != LM_STATUS_SUCCESS) {
 640                 return Status;
 641         }
 642         pDevice->Irq = (LM_UINT8) Value32;
 643
 644         /* Get interrupt pin. */
 645         pDevice->IntPin = (LM_UINT8) (Value32 >> 8);
 646
 647         /* Get chip revision id. */
 648         Status = MM_ReadConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
 649         pDevice->ChipRevId = Value32 >> 16;
 650
 651         /* Get subsystem vendor. */
 652         Status =
 653             MM_ReadConfig32 (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32);
 654         if (Status != LM_STATUS_SUCCESS) {
 655                 return Status;
 656         }
 657         pDevice->SubsystemVendorId = (LM_UINT16) Value32;
 658
 659         /* Get PCI subsystem id. */
 660         pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16);
 661
 662         /* Get the cache line size. */
 663         MM_ReadConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32);
 664         pDevice->CacheLineSize = (LM_UINT8) Value32;
 665         pDevice->SavedCacheLineReg = Value32;
 666
 667         if (pDevice->ChipRevId != T3_CHIP_ID_5703_A1 &&
 668             pDevice->ChipRevId != T3_CHIP_ID_5703_A2 &&
 669             pDevice->ChipRevId != T3_CHIP_ID_5704_A0) {
 670                 pDevice->UndiFix = FALSE;
 671         }
 672 #if !PCIX_TARGET_WORKAROUND
 673         pDevice->UndiFix = FALSE;
 674 #endif
 675         /* Map the memory base to system address space. */
 676         if (!pDevice->UndiFix) {
 677                 Status = MM_MapMemBase (pDevice);
 678                 if (Status != LM_STATUS_SUCCESS) {
 679                         return Status;
 680                 }
 681                 /* Initialize the memory view pointer. */
 682                 pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase;
 683         }
 684 #if PCIX_TARGET_WORKAROUND
 685         /* store whether we are in PCI are PCI-X mode */
 686         pDevice->EnablePciXFix = FALSE;
 687
 688         MM_ReadConfig32 (pDevice, T3_PCI_STATE_REG, &Value32);
 689         if ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0) {
 690                 /* Enable PCI-X workaround only if we are running on 5700 BX. */
 691                 if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
 692                         pDevice->EnablePciXFix = TRUE;
 693                 }
 694         }
 695         if (pDevice->UndiFix) {
 696                 pDevice->EnablePciXFix = TRUE;
 697         }
 698 #endif
 699         /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */
 700         /* management register may be clobbered which may cause the */
 701         /* BCM5700 to go into D3 state.  While in this state, we will */
 702         /* not have memory mapped register access.  As a workaround, we */
 703         /* need to restore the device to D0 state. */
 704         MM_ReadConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32);
 705         Value32 |= T3_PM_PME_ASSERTED;
 706         Value32 &= ~T3_PM_POWER_STATE_MASK;
 707         Value32 |= T3_PM_POWER_STATE_D0;
 708         MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32);
 709
 710         /* read the current PCI command word */
 711         MM_ReadConfig32 (pDevice, PCI_COMMAND_REG, &Value32);
 712
 713         /* Make sure bus-mastering is enabled. */
 714         Value32 |= PCI_BUSMASTER_ENABLE;
 715
 716 #if PCIX_TARGET_WORKAROUND
 717         /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR#
 718            are enabled */
 719         if (pDevice->EnablePciXFix == TRUE) {
 720                 Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE |
 721                             PCI_PARITY_ERROR_ENABLE);
 722         }
 723         if (pDevice->UndiFix) {
 724                 Value32 &= ~PCI_MEM_SPACE_ENABLE;
 725         }
 726 #endif
 727
 728         if (pDevice->EnableMWI) {
 729                 Value32 |= PCI_MEMORY_WRITE_INVALIDATE;
 730         } else {
 731                 Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE);
 732         }
 733
 734         /* Error out if mem-mapping is NOT enabled for PCI systems */
 735         if (!(Value32 | PCI_MEM_SPACE_ENABLE)) {
 736                 return LM_STATUS_FAILURE;
 737         }
 738
 739         /* save the value we are going to write into the PCI command word */
 740         pDevice->PciCommandStatusWords = Value32;
 741
 742         Status = MM_WriteConfig32 (pDevice, PCI_COMMAND_REG, Value32);
 743         if (Status != LM_STATUS_SUCCESS) {
 744                 return Status;
 745         }
 746
 747         /* Set power state to D0. */
 748         LM_SetPowerState (pDevice, LM_POWER_STATE_D0);
 749
 750 #ifdef BIG_ENDIAN_PCI
 751         pDevice->MiscHostCtrl =
 752             MISC_HOST_CTRL_MASK_PCI_INT |
 753             MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
 754             MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
 755             MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
 756 #else                           /* No CPU Swap modes for PCI IO */
 757
 758         /* Setup the mode registers. */
 759         pDevice->MiscHostCtrl =
 760             MISC_HOST_CTRL_MASK_PCI_INT |
 761             MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
 762 #ifdef BIG_ENDIAN_HOST
 763             MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP |
 764 #endif                          /* BIG_ENDIAN_HOST */
 765             MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
 766             MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
 767 #endif                          /* !BIG_ENDIAN_PCI */
 768
 769         /* write to PCI misc host ctr first in order to enable indirect accesses */
 770         MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG,
 771                           pDevice->MiscHostCtrl);
 772
 773         REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl);
 774
 775 #ifdef BIG_ENDIAN_PCI
 776         Value32 = GRC_MODE_WORD_SWAP_DATA | GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
 777 #else
 778 /* No CPU Swap modes for PCI IO */
 779 #ifdef BIG_ENDIAN_HOST
 780         Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
 781             GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
 782 #else
 783         Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
 784 #endif
 785 #endif                          /* !BIG_ENDIAN_PCI */
 786
 787         REG_WR (pDevice, Grc.Mode, Value32);
 788
 789         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
 790                 REG_WR (pDevice, Grc.LocalCtrl,
 791                         GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
 792                         GRC_MISC_LOCAL_CTRL_GPIO_OE1);
 793         }
 794         MM_Wait (40);
 795
 796         /* Enable indirect memory access */
 797         REG_WR (pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
 798
 799         if (REG_RD (pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK) {
 800                 REG_WR (pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK |
 801                         T3_PCI_SELECT_ALTERNATE_CLOCK);
 802                 REG_WR (pDevice, PciCfg.ClockCtrl,
 803                         T3_PCI_SELECT_ALTERNATE_CLOCK);
 804                 MM_Wait (40);   /* required delay is 27usec */
 805         }
 806         REG_WR (pDevice, PciCfg.ClockCtrl, 0);
 807         REG_WR (pDevice, PciCfg.MemWindowBaseAddr, 0);
 808
 809 #if PCIX_TARGET_WORKAROUND
 810         MM_ReadConfig32 (pDevice, T3_PCI_STATE_REG, &Value32);
 811         if ((pDevice->EnablePciXFix == FALSE) &&
 812             ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)) {
 813                 if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
 814                     pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
 815                     pDevice->ChipRevId == T3_CHIP_ID_5701_B2 ||
 816                     pDevice->ChipRevId == T3_CHIP_ID_5701_B5) {
 817                         __raw_writel (0,
 818                                       &(pDevice->pMemView->uIntMem.
 819                                         MemBlock32K[0x300]));
 820                         __raw_writel (0,
 821                                       &(pDevice->pMemView->uIntMem.
 822                                         MemBlock32K[0x301]));
 823                         __raw_writel (0xffffffff,
 824                                       &(pDevice->pMemView->uIntMem.
 825                                         MemBlock32K[0x301]));
 826                         if (__raw_readl
 827                             (&(pDevice->pMemView->uIntMem.MemBlock32K[0x300])))
 828                         {
 829                                 pDevice->EnablePciXFix = TRUE;
 830                         }
 831                 }
 832         }
 833 #endif
 834 #if 1
 835         /*
 836          *  This code was at the beginning of else block below, but that's
 837          *  a bug if node address in shared memory.
 838          */
 839         MM_Wait (50);
 840         LM_NvramInit (pDevice);
 841 #endif
 842         /* Get the node address.  First try to get in from the shared memory. */
 843         /* If the signature is not present, then get it from the NVRAM. */
 844         Value32 = MEM_RD_OFFSET (pDevice, T3_MAC_ADDR_HIGH_MAILBOX);
 845         if ((Value32 >> 16) == 0x484b) {
 846
 847                 pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8);
 848                 pDevice->NodeAddress[1] = (LM_UINT8) Value32;
 849
 850                 Value32 = MEM_RD_OFFSET (pDevice, T3_MAC_ADDR_LOW_MAILBOX);
 851
 852                 pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24);
 853                 pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16);
 854                 pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8);
 855                 pDevice->NodeAddress[5] = (LM_UINT8) Value32;
 856
 857                 Status = LM_STATUS_SUCCESS;
 858         } else {
 859                 Status = LM_NvramRead (pDevice, 0x7c, &Value32);
 860                 if (Status == LM_STATUS_SUCCESS) {
 861                         pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16);
 862                         pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24);
 863
 864                         Status = LM_NvramRead (pDevice, 0x80, &Value32);
 865
 866                         pDevice->NodeAddress[2] = (LM_UINT8) Value32;
 867                         pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8);
 868                         pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16);
 869                         pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24);
 870                 }
 871         }
 872
 873         /* Assign a default address. */
 874         if (Status != LM_STATUS_SUCCESS) {
 875 #ifndef EMBEDDED
 876                 printk (KERN_ERR
 877                         "Cannot get MAC addr from NVRAM. Using default.\n");
 878 #endif
 879                 pDevice->NodeAddress[0] = 0x00;
 880                 pDevice->NodeAddress[1] = 0x10;
 881                 pDevice->NodeAddress[2] = 0x18;
 882                 pDevice->NodeAddress[3] = 0x68;
 883                 pDevice->NodeAddress[4] = 0x61;
 884                 pDevice->NodeAddress[5] = 0x76;
 885         }
 886
 887         pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0];
 888         pDevice->PermanentNodeAddress[1] = pDevice->NodeAddress[1];
 889         pDevice->PermanentNodeAddress[2] = pDevice->NodeAddress[2];
 890         pDevice->PermanentNodeAddress[3] = pDevice->NodeAddress[3];
 891         pDevice->PermanentNodeAddress[4] = pDevice->NodeAddress[4];
 892         pDevice->PermanentNodeAddress[5] = pDevice->NodeAddress[5];
 893
 894         /* Initialize the default values. */
 895         pDevice->NoTxPseudoHdrChksum = FALSE;
 896         pDevice->NoRxPseudoHdrChksum = FALSE;
 897         pDevice->NicSendBd = FALSE;
 898         pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT;
 899         pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT;
 900         pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS;
 901         pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS;
 902         pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES;
 903         pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES;
 904         pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
 905         pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
 906         pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
 907         pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
 908         pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS;
 909         pDevice->EnableMWI = FALSE;
 910         pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
 911         pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
 912         pDevice->DisableAutoNeg = FALSE;
 913         pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO;
 914         pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO;
 915         pDevice->LedMode = LED_MODE_AUTO;
 916         pDevice->ResetPhyOnInit = TRUE;
 917         pDevice->DelayPciGrant = TRUE;
 918         pDevice->UseTaggedStatus = FALSE;
 919         pDevice->OneDmaAtOnce = BAD_DEFAULT_VALUE;
 920
 921         pDevice->DmaMbufLowMark = T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO;
 922         pDevice->RxMacMbufLowMark = T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO;
 923         pDevice->MbufHighMark = T3_DEF_MBUF_HIGH_WMARK_JUMBO;
 924
 925         pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO;
 926         pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE;
 927         pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE;
 928         pDevice->EnableTbi = FALSE;
 929 #if INCLUDE_TBI_SUPPORT
 930         pDevice->PollTbiLink = BAD_DEFAULT_VALUE;
 931 #endif
 932
 933         switch (T3_ASIC_REV (pDevice->ChipRevId)) {
 934         case T3_ASIC_REV_5704:
 935                 pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
 936                 pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64;
 937                 break;
 938         default:
 939                 pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
 940                 pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96;
 941                 break;
 942         }
 943
 944         pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
 945         pDevice->QueueRxPackets = TRUE;
 946
 947         pDevice->EnableWireSpeed = TRUE;
 948
 949 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 950         pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
 951 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
 952
 953         /* Make this is a known adapter. */
 954         pAdapterInfo = LM_GetAdapterInfoBySsid (pDevice->SubsystemVendorId,
 955                                                 pDevice->SubsystemId);
 956
 957         pDevice->BondId = REG_RD (pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK;
 958         if (pDevice->BondId != GRC_MISC_BD_ID_5700 &&
 959             pDevice->BondId != GRC_MISC_BD_ID_5701 &&
 960             pDevice->BondId != GRC_MISC_BD_ID_5702FE &&
 961             pDevice->BondId != GRC_MISC_BD_ID_5703 &&
 962             pDevice->BondId != GRC_MISC_BD_ID_5703S &&
 963             pDevice->BondId != GRC_MISC_BD_ID_5704 &&
 964             pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE) {
 965                 return LM_STATUS_UNKNOWN_ADAPTER;
 966         }
 967
 968         pDevice->SplitModeEnable = SPLIT_MODE_DISABLE;
 969         if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) &&
 970             (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) {
 971                 pDevice->SplitModeEnable = SPLIT_MODE_ENABLE;
 972                 pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ;
 973         }
 974
 975         /* Get Eeprom info. */
 976         Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_SIG_ADDR);
 977         if (Value32 == T3_NIC_DATA_SIG) {
 978                 EeSigFound = TRUE;
 979                 Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
 980
 981                 /* Determine PHY type. */
 982                 switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK) {
 983                 case T3_NIC_CFG_PHY_TYPE_COPPER:
 984                         EePhyTypeSerdes = FALSE;
 985                         break;
 986
 987                 case T3_NIC_CFG_PHY_TYPE_FIBER:
 988                         EePhyTypeSerdes = TRUE;
 989                         break;
 990
 991                 default:
 992                         EePhyTypeSerdes = FALSE;
 993                         break;
 994                 }
 995
 996                 /* Determine PHY led mode. */
 997                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
 998                     T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
 999                         switch (Value32 & T3_NIC_CFG_LED_MODE_MASK) {
1000                         case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED:
1001                                 EePhyLedMode = LED_MODE_THREE_LINK;
1002                                 break;
1003
1004                         case T3_NIC_CFG_LED_MODE_LINK_SPEED:
1005                                 EePhyLedMode = LED_MODE_LINK10;
1006                                 break;
1007
1008                         default:
1009                                 EePhyLedMode = LED_MODE_AUTO;
1010                                 break;
1011                         }
1012                 } else {
1013                         switch (Value32 & T3_NIC_CFG_LED_MODE_MASK) {
1014                         case T3_NIC_CFG_LED_MODE_OPEN_DRAIN:
1015                                 EePhyLedMode = LED_MODE_OPEN_DRAIN;
1016                                 break;
1017
1018                         case T3_NIC_CFG_LED_MODE_OUTPUT:
1019                                 EePhyLedMode = LED_MODE_OUTPUT;
1020                                 break;
1021
1022                         default:
1023                                 EePhyLedMode = LED_MODE_AUTO;
1024                                 break;
1025                         }
1026                 }
1027                 if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
1028                     pDevice->ChipRevId == T3_CHIP_ID_5703_A2) {
1029                         /* Enable EEPROM write protection. */
1030                         if (Value32 & T3_NIC_EEPROM_WP) {
1031                                 pDevice->EepromWp = TRUE;
1032                         }
1033                 }
1034
1035                 /* Get the PHY Id. */
1036                 Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_PHY_ID_ADDR);
1037                 if (Value32) {
1038                         EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) &
1039                                    PHY_ID1_OUI_MASK) << 10;
1040
1041                         Value32 = Value32 & T3_NIC_PHY_ID2_MASK;
1042
1043                         EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
1044                             (Value32 & PHY_ID2_MODEL_MASK) | (Value32 &
1045                                                               PHY_ID2_REV_MASK);
1046                 } else {
1047                         EePhyId = 0;
1048                 }
1049         } else {
1050                 EeSigFound = FALSE;
1051         }
1052
1053         /* Set the PHY address. */
1054         pDevice->PhyAddr = PHY_DEVICE_ID;
1055
1056         /* Disable auto polling. */
1057         pDevice->MiMode = 0xc0000;
1058         REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
1059         MM_Wait (40);
1060
1061         /* Get the PHY id. */
1062         LM_ReadPhy (pDevice, PHY_ID1_REG, &Value32);
1063         pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10;
1064
1065         LM_ReadPhy (pDevice, PHY_ID2_REG, &Value32);
1066         pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
1067             (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
1068
1069         /* Set the EnableTbi flag to false if we have a copper PHY. */
1070         switch (pDevice->PhyId & PHY_ID_MASK) {
1071         case PHY_BCM5400_PHY_ID:
1072                 pDevice->EnableTbi = FALSE;
1073                 break;
1074
1075         case PHY_BCM5401_PHY_ID:
1076                 pDevice->EnableTbi = FALSE;
1077                 break;
1078
1079         case PHY_BCM5411_PHY_ID:
1080                 pDevice->EnableTbi = FALSE;
1081                 break;
1082
1083         case PHY_BCM5701_PHY_ID:
1084                 pDevice->EnableTbi = FALSE;
1085                 break;
1086
1087         case PHY_BCM5703_PHY_ID:
1088                 pDevice->EnableTbi = FALSE;
1089                 break;
1090
1091         case PHY_BCM5704_PHY_ID:
1092                 pDevice->EnableTbi = FALSE;
1093                 break;
1094
1095         case PHY_BCM8002_PHY_ID:
1096                 pDevice->EnableTbi = TRUE;
1097                 break;
1098
1099         default:
1100
1101                 if (pAdapterInfo) {
1102                         pDevice->PhyId = pAdapterInfo->PhyId;
1103                         pDevice->EnableTbi = pAdapterInfo->Serdes;
1104                 } else if (EeSigFound) {
1105                         pDevice->PhyId = EePhyId;
1106                         pDevice->EnableTbi = EePhyTypeSerdes;
1107                 }
1108                 break;
1109         }
1110
1111         /* Bail out if we don't know the copper PHY id. */
1112         if (UNKNOWN_PHY_ID (pDevice->PhyId) && !pDevice->EnableTbi) {
1113                 return LM_STATUS_FAILURE;
1114         }
1115
1116         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5703) {
1117                 if ((pDevice->SavedCacheLineReg & 0xff00) < 0x4000) {
1118                         pDevice->SavedCacheLineReg &= 0xffff00ff;
1119                         pDevice->SavedCacheLineReg |= 0x4000;
1120                 }
1121         }
1122         /* Change driver parameters. */
1123         Status = MM_GetConfig (pDevice);
1124         if (Status != LM_STATUS_SUCCESS) {
1125                 return Status;
1126         }
1127 #if INCLUDE_5701_AX_FIX
1128         if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
1129             pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
1130                 pDevice->ResetPhyOnInit = TRUE;
1131         }
1132 #endif
1133
1134         /* Save the current phy link status. */
1135         if (!pDevice->EnableTbi) {
1136                 LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
1137                 LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
1138
1139                 /* If we don't have link reset the PHY. */
1140                 if (!(Value32 & PHY_STATUS_LINK_PASS)
1141                     || pDevice->ResetPhyOnInit) {
1142
1143                         LM_WritePhy (pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
1144
1145                         for (j = 0; j < 100; j++) {
1146                                 MM_Wait (10);
1147
1148                                 LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
1149                                 if (Value32 && !(Value32 & PHY_CTRL_PHY_RESET)) {
1150                                         MM_Wait (40);
1151                                         break;
1152                                 }
1153                         }
1154
1155 #if INCLUDE_5701_AX_FIX
1156                         /* 5701_AX_BX bug:  only advertises 10mb speed. */
1157                         if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
1158                             pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
1159
1160                                 Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
1161                                     PHY_AN_AD_10BASET_HALF |
1162                                     PHY_AN_AD_10BASET_FULL |
1163                                     PHY_AN_AD_100BASETX_FULL |
1164                                     PHY_AN_AD_100BASETX_HALF;
1165                                 Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
1166                                 LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
1167                                 pDevice->advertising = Value32;
1168
1169                                 Value32 = BCM540X_AN_AD_1000BASET_HALF |
1170                                     BCM540X_AN_AD_1000BASET_FULL |
1171                                     BCM540X_CONFIG_AS_MASTER |
1172                                     BCM540X_ENABLE_CONFIG_AS_MASTER;
1173                                 LM_WritePhy (pDevice,
1174                                              BCM540X_1000BASET_CTRL_REG,
1175                                              Value32);
1176                                 pDevice->advertising1000 = Value32;
1177
1178                                 LM_WritePhy (pDevice, PHY_CTRL_REG,
1179                                              PHY_CTRL_AUTO_NEG_ENABLE |
1180                                              PHY_CTRL_RESTART_AUTO_NEG);
1181                         }
1182 #endif
1183                         if (T3_ASIC_REV (pDevice->ChipRevId) ==
1184                             T3_ASIC_REV_5703) {
1185                                 LM_WritePhy (pDevice, 0x18, 0x0c00);
1186                                 LM_WritePhy (pDevice, 0x17, 0x201f);
1187                                 LM_WritePhy (pDevice, 0x15, 0x2aaa);
1188                         }
1189                         if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
1190                                 LM_WritePhy (pDevice, 0x1c, 0x8d68);
1191                                 LM_WritePhy (pDevice, 0x1c, 0x8d68);
1192                         }
1193                         /* Enable Ethernet@WireSpeed. */
1194                         if (pDevice->EnableWireSpeed) {
1195                                 LM_WritePhy (pDevice, 0x18, 0x7007);
1196                                 LM_ReadPhy (pDevice, 0x18, &Value32);
1197                                 LM_WritePhy (pDevice, 0x18,
1198                                              Value32 | BIT_15 | BIT_4);
1199                         }
1200                 }
1201         }
1202
1203         /* Turn off tap power management. */
1204         if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) {
1205                 LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x0c20);
1206                 LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
1207                 LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1804);
1208                 LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
1209                 LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1204);
1210                 LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
1211                 LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0132);
1212                 LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
1213                 LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0232);
1214                 LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
1215                 LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
1216
1217                 MM_Wait (40);
1218         }
1219 #if INCLUDE_TBI_SUPPORT
1220         pDevice->IgnoreTbiLinkChange = FALSE;
1221
1222         if (pDevice->EnableTbi) {
1223                 pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE;
1224                 pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
1225                 if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) ||
1226                     pDevice->DisableAutoNeg) {
1227                         pDevice->PollTbiLink = FALSE;
1228                 }
1229         } else {
1230                 pDevice->PollTbiLink = FALSE;
1231         }
1232 #endif                          /* INCLUDE_TBI_SUPPORT */
1233
1234         /* UseTaggedStatus is only valid for 5701 and later. */
1235         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
1236                 pDevice->UseTaggedStatus = FALSE;
1237
1238                 pDevice->CoalesceMode = 0;
1239         } else {
1240                 pDevice->CoalesceMode =
1241                     HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT |
1242                     HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT;
1243         }
1244
1245         /* Set the status block size. */
1246         if (T3_CHIP_REV (pDevice->ChipRevId) != T3_CHIP_REV_5700_AX &&
1247             T3_CHIP_REV (pDevice->ChipRevId) != T3_CHIP_REV_5700_BX) {
1248                 pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE;
1249         }
1250
1251         /* Check the DURING_INT coalescing ticks parameters. */
1252         if (pDevice->UseTaggedStatus) {
1253                 if (pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
1254                         pDevice->RxCoalescingTicksDuringInt =
1255                             DEFAULT_RX_COALESCING_TICKS_DURING_INT;
1256                 }
1257
1258                 if (pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
1259                         pDevice->TxCoalescingTicksDuringInt =
1260                             DEFAULT_TX_COALESCING_TICKS_DURING_INT;
1261                 }
1262
1263                 if (pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
1264                         pDevice->RxMaxCoalescedFramesDuringInt =
1265                             DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT;
1266                 }
1267
1268                 if (pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
1269                         pDevice->TxMaxCoalescedFramesDuringInt =
1270                             DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT;
1271                 }
1272         } else {
1273                 if (pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
1274                         pDevice->RxCoalescingTicksDuringInt = 0;
1275                 }
1276
1277                 if (pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
1278                         pDevice->TxCoalescingTicksDuringInt = 0;
1279                 }
1280
1281                 if (pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
1282                         pDevice->RxMaxCoalescedFramesDuringInt = 0;
1283                 }
1284
1285                 if (pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
1286                         pDevice->TxMaxCoalescedFramesDuringInt = 0;
1287                 }
1288         }
1289
1290 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
1291         if (pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */ )) {
1292                 pDevice->RxJumboDescCnt = 0;
1293                 if (pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC) {
1294                         pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
1295                 }
1296         } else {
1297                 pDevice->RxJumboBufferSize =
1298                     (pDevice->RxMtu + 8 /* CRC + VLAN */  +
1299                      COMMON_CACHE_LINE_SIZE - 1) & ~COMMON_CACHE_LINE_MASK;
1300
1301                 if (pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE) {
1302                         pDevice->RxJumboBufferSize =
1303                             DEFAULT_JUMBO_RCV_BUFFER_SIZE;
1304                         pDevice->RxMtu =
1305                             pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */ ;
1306                 }
1307                 pDevice->TxMtu = pDevice->RxMtu;
1308
1309         }
1310 #else
1311         pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
1312 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
1313
1314         pDevice->RxPacketDescCnt =
1315 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
1316             pDevice->RxJumboDescCnt +
1317 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
1318             pDevice->RxStdDescCnt;
1319
1320         if (pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC) {
1321                 pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
1322         }
1323
1324         if (pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE) {
1325                 pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE;
1326         }
1327
1328         /* Configure the proper ways to get link change interrupt. */
1329         if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO) {
1330                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
1331                         pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
1332                 } else {
1333                         pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
1334                 }
1335         } else if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
1336                 /* Auto-polling does not work on 5700_AX and 5700_BX. */
1337                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
1338                         pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
1339                 }
1340         }
1341
1342         /* Determine the method to get link change status. */
1343         if (pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO) {
1344                 /* The link status bit in the status block does not work on 5700_AX */
1345                 /* and 5700_BX chips. */
1346                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
1347                         pDevice->LinkChngMode =
1348                             T3_LINK_CHNG_MODE_USE_STATUS_REG;
1349                 } else {
1350                         pDevice->LinkChngMode =
1351                             T3_LINK_CHNG_MODE_USE_STATUS_BLOCK;
1352                 }
1353         }
1354
1355         if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT ||
1356             T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
1357                 pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
1358         }
1359
1360         /* Configure PHY led mode. */
1361         if (pDevice->LedMode == LED_MODE_AUTO) {
1362                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
1363                     T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
1364                         if (pDevice->SubsystemVendorId == T3_SVID_DELL) {
1365                                 pDevice->LedMode = LED_MODE_LINK10;
1366                         } else {
1367                                 pDevice->LedMode = LED_MODE_THREE_LINK;
1368
1369                                 if (EeSigFound && EePhyLedMode != LED_MODE_AUTO) {
1370                                         pDevice->LedMode = EePhyLedMode;
1371                                 }
1372                         }
1373
1374                         /* bug? 5701 in LINK10 mode does not seem to work when */
1375                         /* PhyIntMode is LINK_READY. */
1376                         if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700
1377                             &&
1378 #if INCLUDE_TBI_SUPPORT
1379                             pDevice->EnableTbi == FALSE &&
1380 #endif
1381                             pDevice->LedMode == LED_MODE_LINK10) {
1382                                 pDevice->PhyIntMode =
1383                                     T3_PHY_INT_MODE_MI_INTERRUPT;
1384                                 pDevice->LinkChngMode =
1385                                     T3_LINK_CHNG_MODE_USE_STATUS_REG;
1386                         }
1387
1388                         if (pDevice->EnableTbi) {
1389                                 pDevice->LedMode = LED_MODE_THREE_LINK;
1390                         }
1391                 } else {
1392                         if (EeSigFound && EePhyLedMode != LED_MODE_AUTO) {
1393                                 pDevice->LedMode = EePhyLedMode;
1394                         } else {
1395                                 pDevice->LedMode = LED_MODE_OPEN_DRAIN;
1396                         }
1397                 }
1398         }
1399
1400         /* Enable OneDmaAtOnce. */
1401         if (pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE) {
1402                 pDevice->OneDmaAtOnce = FALSE;
1403         }
1404
1405         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
1406             pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
1407             pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
1408             pDevice->ChipRevId == T3_CHIP_ID_5701_B2) {
1409                 pDevice->WolSpeed = WOL_SPEED_10MB;
1410         } else {
1411                 pDevice->WolSpeed = WOL_SPEED_100MB;
1412         }
1413
1414         /* Offloadings. */
1415         pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
1416
1417         /* Turn off task offloading on Ax. */
1418         if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) {
1419                 pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
1420                                              LM_TASK_OFFLOAD_TX_UDP_CHECKSUM);
1421         }
1422         pDevice->PciState = REG_RD (pDevice, PciCfg.PciState);
1423         LM_ReadVPD (pDevice);
1424         LM_ReadBootCodeVersion (pDevice);
1425         LM_GetBusSpeed (pDevice);
1426
1427         return LM_STATUS_SUCCESS;
1428 }                               /* LM_GetAdapterInfo */
1429
1430 STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid (LM_UINT16 Svid, LM_UINT16 Ssid)
1431 {
1432         static LM_ADAPTER_INFO AdapterArr[] = {
1433                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6,
1434                  PHY_BCM5401_PHY_ID, 0},
1435                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5,
1436                  PHY_BCM5701_PHY_ID, 0},
1437                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6,
1438                  PHY_BCM8002_PHY_ID, 1},
1439                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1},
1440                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1,
1441                  PHY_BCM5701_PHY_ID, 0},
1442                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8,
1443                  PHY_BCM5701_PHY_ID, 0},
1444                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1},
1445                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10,
1446                  PHY_BCM5701_PHY_ID, 0},
1447                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12,
1448                  PHY_BCM5701_PHY_ID, 0},
1449                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1,
1450                  PHY_BCM5701_PHY_ID, 0},
1451                 {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2,
1452                  PHY_BCM5701_PHY_ID, 0},
1453
1454                 {T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0},
1455                 {T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0},
1456                 {T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1},
1457                 {T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0},
1458                 {T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0},
1459
1460                 {T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0},
1461                 {T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0},
1462                 {T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0},
1463                 {T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0},
1464
1465                 {T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0},
1466                 {T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID,
1467                  0},
1468                 {T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1},
1469                 {T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0},
1470                 {T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID,
1471                  0},
1472
1473         };
1474         LM_UINT32 j;
1475
1476         for (j = 0; j < sizeof (AdapterArr) / sizeof (LM_ADAPTER_INFO); j++) {
1477                 if (AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid) {
1478                         return &AdapterArr[j];
1479                 }
1480         }
1481
1482         return NULL;
1483 }
1484
1485 /******************************************************************************/
1486 /* Description:                                                               */
1487 /*    This routine sets up receive/transmit buffer descriptions queues.       */
1488 /*                                                                            */
1489 /* Return:                                                                    */
1490 /*    LM_STATUS_SUCCESS                                                       */
1491 /******************************************************************************/
1492 LM_STATUS LM_InitializeAdapter (PLM_DEVICE_BLOCK pDevice)
1493 {
1494         LM_PHYSICAL_ADDRESS MemPhy;
1495         PLM_UINT8 pMemVirt;
1496         PLM_PACKET pPacket;
1497         LM_STATUS Status;
1498         LM_UINT32 Size;
1499         LM_UINT32 j;
1500
1501         /* Set power state to D0. */
1502         LM_SetPowerState (pDevice, LM_POWER_STATE_D0);
1503
1504         /* Intialize the queues. */
1505         QQ_InitQueue (&pDevice->RxPacketReceivedQ.Container,
1506                       MAX_RX_PACKET_DESC_COUNT);
1507         QQ_InitQueue (&pDevice->RxPacketFreeQ.Container,
1508                       MAX_RX_PACKET_DESC_COUNT);
1509
1510         QQ_InitQueue (&pDevice->TxPacketFreeQ.Container,
1511                       MAX_TX_PACKET_DESC_COUNT);
1512         QQ_InitQueue (&pDevice->TxPacketActiveQ.Container,
1513                       MAX_TX_PACKET_DESC_COUNT);
1514         QQ_InitQueue (&pDevice->TxPacketXmittedQ.Container,
1515                       MAX_TX_PACKET_DESC_COUNT);
1516
1517         /* Allocate shared memory for: status block, the buffers for receive */
1518         /* rings -- standard, mini, jumbo, and return rings. */
1519         Size = T3_STATUS_BLOCK_SIZE + sizeof (T3_STATS_BLOCK) +
1520             T3_STD_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD) +
1521 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
1522             T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD) +
1523 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
1524             T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
1525
1526         /* Memory for host based Send BD. */
1527         if (pDevice->NicSendBd == FALSE) {
1528                 Size += sizeof (T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
1529         }
1530
1531         /* Allocate the memory block. */
1532         Status =
1533             MM_AllocateSharedMemory (pDevice, Size, (PLM_VOID) & pMemVirt,
1534                                      &MemPhy, FALSE);
1535         if (Status != LM_STATUS_SUCCESS) {
1536                 return Status;
1537         }
1538
1539         /* Program DMA Read/Write */
1540         if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) {
1541                 pDevice->DmaReadWriteCtrl = 0x763f000f;
1542         } else {
1543                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5704) {
1544                         pDevice->DmaReadWriteCtrl = 0x761f0000;
1545                 } else {
1546                         pDevice->DmaReadWriteCtrl = 0x761b000f;
1547                 }
1548                 if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
1549                     pDevice->ChipRevId == T3_CHIP_ID_5703_A2) {
1550                         pDevice->OneDmaAtOnce = TRUE;
1551                 }
1552         }
1553         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5703) {
1554                 pDevice->DmaReadWriteCtrl &= 0xfffffff0;
1555         }
1556
1557         if (pDevice->OneDmaAtOnce) {
1558                 pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
1559         }
1560         REG_WR (pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
1561
1562         if (LM_DmaTest (pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS) {
1563                 return LM_STATUS_FAILURE;
1564         }
1565
1566         /* Status block. */
1567         pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt;
1568         pDevice->StatusBlkPhy = MemPhy;
1569         pMemVirt += T3_STATUS_BLOCK_SIZE;
1570         LM_INC_PHYSICAL_ADDRESS (&MemPhy, T3_STATUS_BLOCK_SIZE);
1571
1572         /* Statistics block. */
1573         pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt;
1574         pDevice->StatsBlkPhy = MemPhy;
1575         pMemVirt += sizeof (T3_STATS_BLOCK);
1576         LM_INC_PHYSICAL_ADDRESS (&MemPhy, sizeof (T3_STATS_BLOCK));
1577
1578         /* Receive standard BD buffer. */
1579         pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt;
1580         pDevice->RxStdBdPhy = MemPhy;
1581
1582         pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
1583         LM_INC_PHYSICAL_ADDRESS (&MemPhy,
1584                                  T3_STD_RCV_RCB_ENTRY_COUNT *
1585                                  sizeof (T3_RCV_BD));
1586
1587 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
1588         /* Receive jumbo BD buffer. */
1589         pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt;
1590         pDevice->RxJumboBdPhy = MemPhy;
1591
1592         pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
1593         LM_INC_PHYSICAL_ADDRESS (&MemPhy,
1594                                  T3_JUMBO_RCV_RCB_ENTRY_COUNT *
1595                                  sizeof (T3_RCV_BD));
1596 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
1597
1598         /* Receive return BD buffer. */
1599         pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt;
1600         pDevice->RcvRetBdPhy = MemPhy;
1601
1602         pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
1603         LM_INC_PHYSICAL_ADDRESS (&MemPhy,
1604                                  T3_RCV_RETURN_RCB_ENTRY_COUNT *
1605                                  sizeof (T3_RCV_BD));
1606
1607         /* Set up Send BD. */
1608         if (pDevice->NicSendBd == FALSE) {
1609                 pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt;
1610                 pDevice->SendBdPhy = MemPhy;
1611
1612                 pMemVirt += sizeof (T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
1613                 LM_INC_PHYSICAL_ADDRESS (&MemPhy,
1614                                          sizeof (T3_SND_BD) *
1615                                          T3_SEND_RCB_ENTRY_COUNT);
1616         } else {
1617                 pDevice->pSendBdVirt = (PT3_SND_BD)
1618                     pDevice->pMemView->uIntMem.First32k.BufferDesc;
1619                 pDevice->SendBdPhy.High = 0;
1620                 pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR;
1621         }
1622
1623         /* Allocate memory for packet descriptors. */
1624         Size = (pDevice->RxPacketDescCnt +
1625                 pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE;
1626         Status = MM_AllocateMemory (pDevice, Size, (PLM_VOID *) & pPacket);
1627         if (Status != LM_STATUS_SUCCESS) {
1628                 return Status;
1629         }
1630         pDevice->pPacketDescBase = (PLM_VOID) pPacket;
1631
1632         /* Create transmit packet descriptors from the memory block and add them */
1633         /* to the TxPacketFreeQ for each send ring. */
1634         for (j = 0; j < pDevice->TxPacketDescCnt; j++) {
1635                 /* Ring index. */
1636                 pPacket->Flags = 0;
1637
1638                 /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */
1639                 QQ_PushTail (&pDevice->TxPacketFreeQ.Container, pPacket);
1640
1641                 /* Get the pointer to the next descriptor.  MM_PACKET_DESC_SIZE */
1642                 /* is the total size of the packet descriptor including the */
1643                 /* os-specific extensions in the UM_PACKET structure. */
1644                 pPacket =
1645                     (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
1646         }                       /* for(j.. */
1647
1648         /* Create receive packet descriptors from the memory block and add them */
1649         /* to the RxPacketFreeQ.  Create the Standard packet descriptors. */
1650         for (j = 0; j < pDevice->RxStdDescCnt; j++) {
1651                 /* Receive producer ring. */
1652                 pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING;
1653
1654                 /* Receive buffer size. */
1655                 pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE;
1656
1657                 /* Add the descriptor to RxPacketFreeQ. */
1658                 QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
1659
1660                 /* Get the pointer to the next descriptor.  MM_PACKET_DESC_SIZE */
1661                 /* is the total size of the packet descriptor including the */
1662                 /* os-specific extensions in the UM_PACKET structure. */
1663                 pPacket =
1664                     (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
1665         }                       /* for */
1666
1667 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
1668         /* Create the Jumbo packet descriptors. */
1669         for (j = 0; j < pDevice->RxJumboDescCnt; j++) {
1670                 /* Receive producer ring. */
1671                 pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING;
1672
1673                 /* Receive buffer size. */
1674                 pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;
1675
1676                 /* Add the descriptor to RxPacketFreeQ. */
1677                 QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
1678
1679                 /* Get the pointer to the next descriptor.  MM_PACKET_DESC_SIZE */
1680                 /* is the total size of the packet descriptor including the */
1681                 /* os-specific extensions in the UM_PACKET structure. */
1682                 pPacket =
1683                     (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
1684         }                       /* for */
1685 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
1686
1687         /* Initialize the rest of the packet descriptors. */
1688         Status = MM_InitializeUmPackets (pDevice);
1689         if (Status != LM_STATUS_SUCCESS) {
1690                 return Status;
1691         }
1692
1693         /* if */
1694         /* Default receive mask. */
1695         pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
1696             LM_ACCEPT_UNICAST;
1697
1698         /* Make sure we are in the first 32k memory window or NicSendBd. */
1699         REG_WR (pDevice, PciCfg.MemWindowBaseAddr, 0);
1700
1701         /* Initialize the hardware. */
1702         Status = LM_ResetAdapter (pDevice);
1703         if (Status != LM_STATUS_SUCCESS) {
1704                 return Status;
1705         }
1706
1707         /* We are done with initialization. */
1708         pDevice->InitDone = TRUE;
1709
1710         return LM_STATUS_SUCCESS;
1711 }                               /* LM_InitializeAdapter */
1712
1713 /******************************************************************************/
1714 /* Description:                                                               */
1715 /*    This function Enables/Disables a given block.                          */
1716 /*                                                                            */
1717 /* Return:                                                                    */
1718 /*    LM_STATUS_SUCCESS                                                       */
1719 /******************************************************************************/
1720 LM_STATUS
1721 LM_CntrlBlock (PLM_DEVICE_BLOCK pDevice, LM_UINT32 mask, LM_UINT32 cntrl)
1722 {
1723         LM_UINT32 j, i, data;
1724         LM_UINT32 MaxWaitCnt;
1725
1726         MaxWaitCnt = 2;
1727         j = 0;
1728
1729         for (i = 0; i < 32; i++) {
1730                 if (!(mask & (1 << i)))
1731                         continue;
1732
1733                 switch (1 << i) {
1734                 case T3_BLOCK_DMA_RD:
1735                         data = REG_RD (pDevice, DmaRead.Mode);
1736                         if (cntrl == LM_DISABLE) {
1737                                 data &= ~DMA_READ_MODE_ENABLE;
1738                                 REG_WR (pDevice, DmaRead.Mode, data);
1739                                 for (j = 0; j < MaxWaitCnt; j++) {
1740                                         if (!
1741                                             (REG_RD (pDevice, DmaRead.Mode) &
1742                                              DMA_READ_MODE_ENABLE))
1743                                                 break;
1744                                         MM_Wait (10);
1745                                 }
1746                         } else
1747                                 REG_WR (pDevice, DmaRead.Mode,
1748                                         data | DMA_READ_MODE_ENABLE);
1749                         break;
1750
1751                 case T3_BLOCK_DMA_COMP:
1752                         data = REG_RD (pDevice, DmaComp.Mode);
1753                         if (cntrl == LM_DISABLE) {
1754                                 data &= ~DMA_COMP_MODE_ENABLE;
1755                                 REG_WR (pDevice, DmaComp.Mode, data);
1756                                 for (j = 0; j < MaxWaitCnt; j++) {
1757                                         if (!
1758                                             (REG_RD (pDevice, DmaComp.Mode) &
1759                                              DMA_COMP_MODE_ENABLE))
1760                                                 break;
1761                                         MM_Wait (10);
1762                                 }
1763                         } else
1764                                 REG_WR (pDevice, DmaComp.Mode,
1765                                         data | DMA_COMP_MODE_ENABLE);
1766                         break;
1767
1768                 case T3_BLOCK_RX_BD_INITIATOR:
1769                         data = REG_RD (pDevice, RcvBdIn.Mode);
1770                         if (cntrl == LM_DISABLE) {
1771                                 data &= ~RCV_BD_IN_MODE_ENABLE;
1772                                 REG_WR (pDevice, RcvBdIn.Mode, data);
1773                                 for (j = 0; j < MaxWaitCnt; j++) {
1774                                         if (!
1775                                             (REG_RD (pDevice, RcvBdIn.Mode) &
1776                                              RCV_BD_IN_MODE_ENABLE))
1777                                                 break;
1778                                         MM_Wait (10);
1779                                 }
1780                         } else
1781                                 REG_WR (pDevice, RcvBdIn.Mode,
1782                                         data | RCV_BD_IN_MODE_ENABLE);
1783                         break;
1784
1785                 case T3_BLOCK_RX_BD_COMP:
1786                         data = REG_RD (pDevice, RcvBdComp.Mode);
1787                         if (cntrl == LM_DISABLE) {
1788                                 data &= ~RCV_BD_COMP_MODE_ENABLE;
1789                                 REG_WR (pDevice, RcvBdComp.Mode, data);
1790                                 for (j = 0; j < MaxWaitCnt; j++) {
1791                                         if (!
1792                                             (REG_RD (pDevice, RcvBdComp.Mode) &
1793                                              RCV_BD_COMP_MODE_ENABLE))
1794                                                 break;
1795                                         MM_Wait (10);
1796                                 }
1797                         } else
1798                                 REG_WR (pDevice, RcvBdComp.Mode,
1799                                         data | RCV_BD_COMP_MODE_ENABLE);
1800                         break;
1801
1802                 case T3_BLOCK_DMA_WR:
1803                         data = REG_RD (pDevice, DmaWrite.Mode);
1804                         if (cntrl == LM_DISABLE) {
1805                                 data &= ~DMA_WRITE_MODE_ENABLE;
1806                                 REG_WR (pDevice, DmaWrite.Mode, data);
1807
1808                                 for (j = 0; j < MaxWaitCnt; j++) {
1809                                         if (!
1810                                             (REG_RD (pDevice, DmaWrite.Mode) &
1811                                              DMA_WRITE_MODE_ENABLE))
1812                                                 break;
1813                                         MM_Wait (10);
1814                                 }
1815                         } else
1816                                 REG_WR (pDevice, DmaWrite.Mode,
1817                                         data | DMA_WRITE_MODE_ENABLE);
1818                         break;
1819
1820                 case T3_BLOCK_MSI_HANDLER:
1821                         data = REG_RD (pDevice, Msi.Mode);
1822                         if (cntrl == LM_DISABLE) {
1823                                 data &= ~MSI_MODE_ENABLE;
1824                                 REG_WR (pDevice, Msi.Mode, data);
1825                                 for (j = 0; j < MaxWaitCnt; j++) {
1826                                         if (!
1827                                             (REG_RD (pDevice, Msi.Mode) &
1828                                              MSI_MODE_ENABLE))
1829                                                 break;
1830                                         MM_Wait (10);
1831                                 }
1832                         } else
1833                                 REG_WR (pDevice, Msi.Mode,
1834                                         data | MSI_MODE_ENABLE);
1835                         break;
1836
1837                 case T3_BLOCK_RX_LIST_PLMT:
1838                         data = REG_RD (pDevice, RcvListPlmt.Mode);
1839                         if (cntrl == LM_DISABLE) {
1840                                 data &= ~RCV_LIST_PLMT_MODE_ENABLE;
1841                                 REG_WR (pDevice, RcvListPlmt.Mode, data);
1842                                 for (j = 0; j < MaxWaitCnt; j++) {
1843                                         if (!
1844                                             (REG_RD (pDevice, RcvListPlmt.Mode)
1845                                              & RCV_LIST_PLMT_MODE_ENABLE))
1846                                                 break;
1847                                         MM_Wait (10);
1848                                 }
1849                         } else
1850                                 REG_WR (pDevice, RcvListPlmt.Mode,
1851                                         data | RCV_LIST_PLMT_MODE_ENABLE);
1852                         break;
1853
1854                 case T3_BLOCK_RX_LIST_SELECTOR:
1855                         data = REG_RD (pDevice, RcvListSel.Mode);
1856                         if (cntrl == LM_DISABLE) {
1857                                 data &= ~RCV_LIST_SEL_MODE_ENABLE;
1858                                 REG_WR (pDevice, RcvListSel.Mode, data);
1859                                 for (j = 0; j < MaxWaitCnt; j++) {
1860                                         if (!
1861                                             (REG_RD (pDevice, RcvListSel.Mode) &
1862                                              RCV_LIST_SEL_MODE_ENABLE))
1863                                                 break;
1864                                         MM_Wait (10);
1865                                 }
1866                         } else
1867                                 REG_WR (pDevice, RcvListSel.Mode,
1868                                         data | RCV_LIST_SEL_MODE_ENABLE);
1869                         break;
1870
1871                 case T3_BLOCK_RX_DATA_INITIATOR:
1872                         data = REG_RD (pDevice, RcvDataBdIn.Mode);
1873                         if (cntrl == LM_DISABLE) {
1874                                 data &= ~RCV_DATA_BD_IN_MODE_ENABLE;
1875                                 REG_WR (pDevice, RcvDataBdIn.Mode, data);
1876                                 for (j = 0; j < MaxWaitCnt; j++) {
1877                                         if (!
1878                                             (REG_RD (pDevice, RcvDataBdIn.Mode)
1879                                              & RCV_DATA_BD_IN_MODE_ENABLE))
1880                                                 break;
1881                                         MM_Wait (10);
1882                                 }
1883                         } else
1884                                 REG_WR (pDevice, RcvDataBdIn.Mode,
1885                                         data | RCV_DATA_BD_IN_MODE_ENABLE);
1886                         break;
1887
1888                 case T3_BLOCK_RX_DATA_COMP:
1889                         data = REG_RD (pDevice, RcvDataComp.Mode);
1890                         if (cntrl == LM_DISABLE) {
1891                                 data &= ~RCV_DATA_COMP_MODE_ENABLE;
1892                                 REG_WR (pDevice, RcvDataComp.Mode, data);
1893                                 for (j = 0; j < MaxWaitCnt; j++) {
1894                                         if (!
1895                                             (REG_RD (pDevice, RcvDataBdIn.Mode)
1896                                              & RCV_DATA_COMP_MODE_ENABLE))
1897                                                 break;
1898                                         MM_Wait (10);
1899                                 }
1900                         } else
1901                                 REG_WR (pDevice, RcvDataComp.Mode,
1902                                         data | RCV_DATA_COMP_MODE_ENABLE);
1903                         break;
1904
1905                 case T3_BLOCK_HOST_COALESING:
1906                         data = REG_RD (pDevice, HostCoalesce.Mode);
1907                         if (cntrl == LM_DISABLE) {
1908                                 data &= ~HOST_COALESCE_ENABLE;
1909                                 REG_WR (pDevice, HostCoalesce.Mode, data);
1910                                 for (j = 0; j < MaxWaitCnt; j++) {
1911                                         if (!
1912                                             (REG_RD (pDevice, SndBdIn.Mode) &
1913                                              HOST_COALESCE_ENABLE))
1914                                                 break;
1915                                         MM_Wait (10);
1916                                 }
1917                         } else
1918                                 REG_WR (pDevice, HostCoalesce.Mode,
1919                                         data | HOST_COALESCE_ENABLE);
1920                         break;
1921
1922                 case T3_BLOCK_MAC_RX_ENGINE:
1923                         if (cntrl == LM_DISABLE) {
1924                                 pDevice->RxMode &= ~RX_MODE_ENABLE;
1925                                 REG_WR (pDevice, MacCtrl.RxMode,
1926                                         pDevice->RxMode);
1927                                 for (j = 0; j < MaxWaitCnt; j++) {
1928                                         if (!
1929                                             (REG_RD (pDevice, MacCtrl.RxMode) &
1930                                              RX_MODE_ENABLE)) {
1931                                                 break;
1932                                         }
1933                                         MM_Wait (10);
1934                                 }
1935                         } else {
1936                                 pDevice->RxMode |= RX_MODE_ENABLE;
1937                                 REG_WR (pDevice, MacCtrl.RxMode,
1938                                         pDevice->RxMode);
1939                         }
1940                         break;
1941
1942                 case T3_BLOCK_MBUF_CLUSTER_FREE:
1943                         data = REG_RD (pDevice, MbufClusterFree.Mode);
1944                         if (cntrl == LM_DISABLE) {
1945                                 data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE;
1946                                 REG_WR (pDevice, MbufClusterFree.Mode, data);
1947                                 for (j = 0; j < MaxWaitCnt; j++) {
1948                                         if (!
1949                                             (REG_RD
1950                                              (pDevice,
1951                                               MbufClusterFree.
1952                                               Mode) &
1953                                              MBUF_CLUSTER_FREE_MODE_ENABLE))
1954                                                 break;
1955                                         MM_Wait (10);
1956                                 }
1957                         } else
1958                                 REG_WR (pDevice, MbufClusterFree.Mode,
1959                                         data | MBUF_CLUSTER_FREE_MODE_ENABLE);
1960                         break;
1961
1962                 case T3_BLOCK_SEND_BD_INITIATOR:
1963                         data = REG_RD (pDevice, SndBdIn.Mode);
1964                         if (cntrl == LM_DISABLE) {
1965                                 data &= ~SND_BD_IN_MODE_ENABLE;
1966                                 REG_WR (pDevice, SndBdIn.Mode, data);
1967                                 for (j = 0; j < MaxWaitCnt; j++) {
1968                                         if (!
1969                                             (REG_RD (pDevice, SndBdIn.Mode) &
1970                                              SND_BD_IN_MODE_ENABLE))
1971                                                 break;
1972                                         MM_Wait (10);
1973                                 }
1974                         } else
1975                                 REG_WR (pDevice, SndBdIn.Mode,
1976                                         data | SND_BD_IN_MODE_ENABLE);
1977                         break;
1978
1979                 case T3_BLOCK_SEND_BD_COMP:
1980                         data = REG_RD (pDevice, SndBdComp.Mode);
1981                         if (cntrl == LM_DISABLE) {
1982                                 data &= ~SND_BD_COMP_MODE_ENABLE;
1983                                 REG_WR (pDevice, SndBdComp.Mode, data);
1984                                 for (j = 0; j < MaxWaitCnt; j++) {
1985                                         if (!
1986                                             (REG_RD (pDevice, SndBdComp.Mode) &
1987                                              SND_BD_COMP_MODE_ENABLE))
1988                                                 break;
1989                                         MM_Wait (10);
1990                                 }
1991                         } else
1992                                 REG_WR (pDevice, SndBdComp.Mode,
1993                                         data | SND_BD_COMP_MODE_ENABLE);
1994                         break;
1995
1996                 case T3_BLOCK_SEND_BD_SELECTOR:
1997                         data = REG_RD (pDevice, SndBdSel.Mode);
1998                         if (cntrl == LM_DISABLE) {
1999                                 data &= ~SND_BD_SEL_MODE_ENABLE;
2000                                 REG_WR (pDevice, SndBdSel.Mode, data);
2001                                 for (j = 0; j < MaxWaitCnt; j++) {
2002                                         if (!
2003                                             (REG_RD (pDevice, SndBdSel.Mode) &
2004                                              SND_BD_SEL_MODE_ENABLE))
2005                                                 break;
2006                                         MM_Wait (10);
2007                                 }
2008                         } else
2009                                 REG_WR (pDevice, SndBdSel.Mode,
2010                                         data | SND_BD_SEL_MODE_ENABLE);
2011                         break;
2012
2013                 case T3_BLOCK_SEND_DATA_INITIATOR:
2014                         data = REG_RD (pDevice, SndDataIn.Mode);
2015                         if (cntrl == LM_DISABLE) {
2016                                 data &= ~T3_SND_DATA_IN_MODE_ENABLE;
2017                                 REG_WR (pDevice, SndDataIn.Mode, data);
2018                                 for (j = 0; j < MaxWaitCnt; j++) {
2019                                         if (!
2020                                             (REG_RD (pDevice, SndDataIn.Mode) &
2021                                              T3_SND_DATA_IN_MODE_ENABLE))
2022                                                 break;
2023                                         MM_Wait (10);
2024                                 }
2025                         } else
2026                                 REG_WR (pDevice, SndDataIn.Mode,
2027                                         data | T3_SND_DATA_IN_MODE_ENABLE);
2028                         break;
2029
2030                 case T3_BLOCK_SEND_DATA_COMP:
2031                         data = REG_RD (pDevice, SndDataComp.Mode);
2032                         if (cntrl == LM_DISABLE) {
2033                                 data &= ~SND_DATA_COMP_MODE_ENABLE;
2034                                 REG_WR (pDevice, SndDataComp.Mode, data);
2035                                 for (j = 0; j < MaxWaitCnt; j++) {
2036                                         if (!
2037                                             (REG_RD (pDevice, SndDataComp.Mode)
2038                                              & SND_DATA_COMP_MODE_ENABLE))
2039                                                 break;
2040                                         MM_Wait (10);
2041                                 }
2042                         } else
2043                                 REG_WR (pDevice, SndDataComp.Mode,
2044                                         data | SND_DATA_COMP_MODE_ENABLE);
2045                         break;
2046
2047                 case T3_BLOCK_MAC_TX_ENGINE:
2048                         if (cntrl == LM_DISABLE) {
2049                                 pDevice->TxMode &= ~TX_MODE_ENABLE;
2050                                 REG_WR (pDevice, MacCtrl.TxMode,
2051                                         pDevice->TxMode);
2052                                 for (j = 0; j < MaxWaitCnt; j++) {
2053                                         if (!
2054                                             (REG_RD (pDevice, MacCtrl.TxMode) &
2055                                              TX_MODE_ENABLE))
2056                                                 break;
2057                                         MM_Wait (10);
2058                                 }
2059                         } else {
2060                                 pDevice->TxMode |= TX_MODE_ENABLE;
2061                                 REG_WR (pDevice, MacCtrl.TxMode,
2062                                         pDevice->TxMode);
2063                         }
2064                         break;
2065
2066                 case T3_BLOCK_MEM_ARBITOR:
2067                         data = REG_RD (pDevice, MemArbiter.Mode);
2068                         if (cntrl == LM_DISABLE) {
2069                                 data &= ~T3_MEM_ARBITER_MODE_ENABLE;
2070                                 REG_WR (pDevice, MemArbiter.Mode, data);
2071                                 for (j = 0; j < MaxWaitCnt; j++) {
2072                                         if (!
2073                                             (REG_RD (pDevice, MemArbiter.Mode) &
2074                                              T3_MEM_ARBITER_MODE_ENABLE))
2075                                                 break;
2076                                         MM_Wait (10);
2077                                 }
2078                         } else
2079                                 REG_WR (pDevice, MemArbiter.Mode,
2080                                         data | T3_MEM_ARBITER_MODE_ENABLE);
2081                         break;
2082
2083                 case T3_BLOCK_MBUF_MANAGER:
2084                         data = REG_RD (pDevice, BufMgr.Mode);
2085                         if (cntrl == LM_DISABLE) {
2086                                 data &= ~BUFMGR_MODE_ENABLE;
2087                                 REG_WR (pDevice, BufMgr.Mode, data);
2088                                 for (j = 0; j < MaxWaitCnt; j++) {
2089                                         if (!
2090                                             (REG_RD (pDevice, BufMgr.Mode) &
2091                                              BUFMGR_MODE_ENABLE))
2092                                                 break;
2093                                         MM_Wait (10);
2094                                 }
2095                         } else
2096                                 REG_WR (pDevice, BufMgr.Mode,
2097                                         data | BUFMGR_MODE_ENABLE);
2098                         break;
2099
2100                 case T3_BLOCK_MAC_GLOBAL:
2101                         if (cntrl == LM_DISABLE) {
2102                                 pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE |
2103                                                       MAC_MODE_ENABLE_RDE |
2104                                                       MAC_MODE_ENABLE_FHDE);
2105                         } else {
2106                                 pDevice->MacMode |= (MAC_MODE_ENABLE_TDE |
2107                                                      MAC_MODE_ENABLE_RDE |
2108                                                      MAC_MODE_ENABLE_FHDE);
2109                         }
2110                         REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
2111                         break;
2112
2113                 default:
2114                         return LM_STATUS_FAILURE;
2115                 }               /* switch */
2116
2117                 if (j >= MaxWaitCnt) {
2118                         return LM_STATUS_FAILURE;
2119                 }
2120         }
2121
2122         return LM_STATUS_SUCCESS;
2123 }
2124
2125 /******************************************************************************/
2126 /* Description:                                                               */
2127 /*    This function reinitializes the adapter.                                */
2128 /*                                                                            */
2129 /* Return:                                                                    */
2130 /*    LM_STATUS_SUCCESS                                                       */
2131 /******************************************************************************/
2132 LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice)
2133 {
2134         LM_UINT32 Value32;
2135         LM_UINT16 Value16;
2136         LM_UINT32 j, k;
2137
2138         /* Disable interrupt. */
2139         LM_DisableInterrupt (pDevice);
2140
2141         /* May get a spurious interrupt */
2142         pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED;
2143
2144         /* Disable transmit and receive DMA engines.  Abort all pending requests. */
2145         if (pDevice->InitDone) {
2146                 LM_Abort (pDevice);
2147         }
2148
2149         pDevice->ShuttingDown = FALSE;
2150
2151         LM_ResetChip (pDevice);
2152
2153         /* Bug: Athlon fix for B3 silicon only.  This bit does not do anything */
2154         /* in other chip revisions. */
2155         if (pDevice->DelayPciGrant) {
2156                 Value32 = REG_RD (pDevice, PciCfg.ClockCtrl);
2157                 REG_WR (pDevice, PciCfg.ClockCtrl, Value32 | BIT_31);
2158         }
2159
2160         if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
2161                 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
2162                         Value32 = REG_RD (pDevice, PciCfg.PciState);
2163                         Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
2164                         REG_WR (pDevice, PciCfg.PciState, Value32);
2165                 }
2166         }
2167
2168         /* Enable TaggedStatus mode. */
2169         if (pDevice->UseTaggedStatus) {
2170                 pDevice->MiscHostCtrl |=
2171                     MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE;
2172         }
2173
2174         /* Restore PCI configuration registers. */
2175         MM_WriteConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG,
2176                           pDevice->SavedCacheLineReg);
2177         MM_WriteConfig32 (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
2178                           (pDevice->SubsystemId << 16) | pDevice->
2179                           SubsystemVendorId);
2180
2181         /* Clear the statistics block. */
2182         for (j = 0x0300; j < 0x0b00; j++) {
2183                 MEM_WR_OFFSET (pDevice, j, 0);
2184         }
2185
2186         /* Initialize the statistis Block */
2187         pDevice->pStatusBlkVirt->Status = 0;
2188         pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
2189         pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
2190         pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
2191
2192         for (j = 0; j < 16; j++) {
2193                 pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0;
2194                 pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0;
2195         }
2196
2197         for (k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT; k++) {
2198                 pDevice->pRxStdBdVirt[k].HostAddr.High = 0;
2199                 pDevice->pRxStdBdVirt[k].HostAddr.Low = 0;
2200         }
2201
2202 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
2203         /* Receive jumbo BD buffer. */
2204         for (k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++) {
2205                 pDevice->pRxJumboBdVirt[k].HostAddr.High = 0;
2206                 pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0;
2207         }
2208 #endif
2209
2210         REG_WR (pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
2211
2212         /* GRC mode control register. */
2213 #ifdef BIG_ENDIAN_PCI           /* Jimmy, this ifdef block deleted in new code! */
2214         Value32 =
2215             GRC_MODE_WORD_SWAP_DATA |
2216             GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
2217             GRC_MODE_INT_ON_MAC_ATTN | GRC_MODE_HOST_STACK_UP;
2218 #else
2219         /* No CPU Swap modes for PCI IO */
2220         Value32 =
2221 #ifdef BIG_ENDIAN_HOST
2222             GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
2223             GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
2224             GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA |
2225 #else
2226             GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
2227             GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA |
2228 #endif
2229             GRC_MODE_INT_ON_MAC_ATTN | GRC_MODE_HOST_STACK_UP;
2230 #endif                          /* !BIG_ENDIAN_PCI */
2231
2232         /* Configure send BD mode. */
2233         if (pDevice->NicSendBd == FALSE) {
2234                 Value32 |= GRC_MODE_HOST_SEND_BDS;
2235         } else {
2236                 Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS;
2237         }
2238
2239         /* Configure pseudo checksum mode. */
2240         if (pDevice->NoTxPseudoHdrChksum) {
2241                 Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM;
2242         }
2243
2244         if (pDevice->NoRxPseudoHdrChksum) {
2245                 Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM;
2246         }
2247
2248         REG_WR (pDevice, Grc.Mode, Value32);
2249
2250         /* Setup the timer prescalar register. */
2251         REG_WR (pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */
2252
2253         /* Set up the MBUF pool base address and size. */
2254         REG_WR (pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
2255         REG_WR (pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
2256
2257         /* Set up the DMA descriptor pool base address and size. */
2258         REG_WR (pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR);
2259         REG_WR (pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE);
2260
2261         /* Configure MBUF and Threshold watermarks */
2262         /* Configure the DMA read MBUF low water mark. */
2263         if (pDevice->DmaMbufLowMark) {
2264                 REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
2265                         pDevice->DmaMbufLowMark);
2266         } else {
2267                 if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
2268                         REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
2269                                 T3_DEF_DMA_MBUF_LOW_WMARK);
2270                 } else {
2271                         REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
2272                                 T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO);
2273                 }
2274         }
2275
2276         /* Configure the MAC Rx MBUF low water mark. */
2277         if (pDevice->RxMacMbufLowMark) {
2278                 REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
2279                         pDevice->RxMacMbufLowMark);
2280         } else {
2281                 if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
2282                         REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
2283                                 T3_DEF_RX_MAC_MBUF_LOW_WMARK);
2284                 } else {
2285                         REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
2286                                 T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO);
2287                 }
2288         }
2289
2290         /* Configure the MBUF high water mark. */
2291         if (pDevice->MbufHighMark) {
2292                 REG_WR (pDevice, BufMgr.MbufHighWaterMark,
2293                         pDevice->MbufHighMark);
2294         } else {
2295                 if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
2296                         REG_WR (pDevice, BufMgr.MbufHighWaterMark,
2297                                 T3_DEF_MBUF_HIGH_WMARK);
2298                 } else {
2299                         REG_WR (pDevice, BufMgr.MbufHighWaterMark,
2300                                 T3_DEF_MBUF_HIGH_WMARK_JUMBO);
2301                 }
2302         }
2303
2304         REG_WR (pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK);
2305         REG_WR (pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK);
2306
2307         /* Enable buffer manager. */
2308         REG_WR (pDevice, BufMgr.Mode,
2309                 BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
2310
2311         for (j = 0; j < 2000; j++) {
2312                 if (REG_RD (pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)
2313                         break;
2314                 MM_Wait (10);
2315         }
2316
2317         if (j >= 2000) {
2318                 return LM_STATUS_FAILURE;
2319         }
2320
2321         /* Enable the FTQs. */
2322         REG_WR (pDevice, Ftq.Reset, 0xffffffff);
2323         REG_WR (pDevice, Ftq.Reset, 0);
2324
2325         /* Wait until FTQ is ready */
2326         for (j = 0; j < 2000; j++) {
2327                 if (REG_RD (pDevice, Ftq.Reset) == 0)
2328                         break;
2329                 MM_Wait (10);
2330         }
2331
2332         if (j >= 2000) {
2333                 return LM_STATUS_FAILURE;
2334         }
2335
2336         /* Initialize the Standard Receive RCB. */
2337         REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High,
2338                 pDevice->RxStdBdPhy.High);
2339         REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low,
2340                 pDevice->RxStdBdPhy.Low);
2341         REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
2342                 MAX_STD_RCV_BUFFER_SIZE << 16);
2343
2344         /* Initialize the Jumbo Receive RCB. */
2345         REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags,
2346                 T3_RCB_FLAG_RING_DISABLED);
2347 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
2348         REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High,
2349                 pDevice->RxJumboBdPhy.High);
2350         REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low,
2351                 pDevice->RxJumboBdPhy.Low);
2352
2353         REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0);
2354
2355 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
2356
2357         /* Initialize the Mini Receive RCB. */
2358         REG_WR (pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags,
2359                 T3_RCB_FLAG_RING_DISABLED);
2360
2361         {
2362                 REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr,
2363                         (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR);
2364                 REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr,
2365                         (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR);
2366         }
2367
2368         /* Receive BD Ring replenish threshold. */
2369         REG_WR (pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt / 8);
2370 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
2371         REG_WR (pDevice, RcvBdIn.JumboRcvThreshold,
2372                 pDevice->RxJumboDescCnt / 8);
2373 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
2374
2375         /* Disable all the unused rings. */
2376         for (j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) {
2377                 MEM_WR (pDevice, SendRcb[j].u.MaxLen_Flags,
2378                         T3_RCB_FLAG_RING_DISABLED);
2379         }                       /* for */
2380
2381         /* Initialize the indices. */
2382         pDevice->SendProdIdx = 0;
2383         pDevice->SendConIdx = 0;
2384
2385         MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, 0);
2386         MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, 0);
2387
2388         /* Set up host or NIC based send RCB. */
2389         if (pDevice->NicSendBd == FALSE) {
2390                 MEM_WR (pDevice, SendRcb[0].HostRingAddr.High,
2391                         pDevice->SendBdPhy.High);
2392                 MEM_WR (pDevice, SendRcb[0].HostRingAddr.Low,
2393                         pDevice->SendBdPhy.Low);
2394
2395                 /* Set up the NIC ring address in the RCB. */
2396                 MEM_WR (pDevice, SendRcb[0].NicRingAddr,
2397                         T3_NIC_SND_BUFFER_DESC_ADDR);
2398
2399                 /* Setup the RCB. */
2400                 MEM_WR (pDevice, SendRcb[0].u.MaxLen_Flags,
2401                         T3_SEND_RCB_ENTRY_COUNT << 16);
2402
2403                 for (k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) {
2404                         pDevice->pSendBdVirt[k].HostAddr.High = 0;
2405                         pDevice->pSendBdVirt[k].HostAddr.Low = 0;
2406                 }
2407         } else {
2408                 MEM_WR (pDevice, SendRcb[0].HostRingAddr.High, 0);
2409                 MEM_WR (pDevice, SendRcb[0].HostRingAddr.Low, 0);
2410                 MEM_WR (pDevice, SendRcb[0].NicRingAddr,
2411                         pDevice->SendBdPhy.Low);
2412
2413                 for (k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) {
2414                         __raw_writel (0,
2415                                       &(pDevice->pSendBdVirt[k].HostAddr.High));
2416                         __raw_writel (0,
2417                                       &(pDevice->pSendBdVirt[k].HostAddr.Low));
2418                         __raw_writel (0,
2419                                       &(pDevice->pSendBdVirt[k].u1.Len_Flags));
2420                         pDevice->ShadowSendBd[k].HostAddr.High = 0;
2421                         pDevice->ShadowSendBd[k].u1.Len_Flags = 0;
2422                 }
2423         }
2424         atomic_set (&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT - 1);
2425
2426         /* Configure the receive return rings. */
2427         for (j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++) {
2428                 MEM_WR (pDevice, RcvRetRcb[j].u.MaxLen_Flags,
2429                         T3_RCB_FLAG_RING_DISABLED);
2430         }
2431
2432         pDevice->RcvRetConIdx = 0;
2433
2434         MEM_WR (pDevice, RcvRetRcb[0].HostRingAddr.High,
2435                 pDevice->RcvRetBdPhy.High);
2436         MEM_WR (pDevice, RcvRetRcb[0].HostRingAddr.Low,
2437                 pDevice->RcvRetBdPhy.Low);
2438
2439         /* Set up the NIC ring address in the RCB. */
2440         /* Not very clear from the spec.  I am guessing that for Receive */
2441         /* Return Ring, NicRingAddr is not used. */
2442         MEM_WR (pDevice, RcvRetRcb[0].NicRingAddr, 0);
2443
2444         /* Setup the RCB. */
2445         MEM_WR (pDevice, RcvRetRcb[0].u.MaxLen_Flags,
2446                 T3_RCV_RETURN_RCB_ENTRY_COUNT << 16);
2447
2448         /* Reinitialize RX ring producer index */
2449         MB_REG_WR (pDevice, Mailbox.RcvStdProdIdx.Low, 0);
2450         MB_REG_WR (pDevice, Mailbox.RcvJumboProdIdx.Low, 0);
2451         MB_REG_WR (pDevice, Mailbox.RcvMiniProdIdx.Low, 0);
2452
2453 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
2454         pDevice->RxJumboProdIdx = 0;
2455         pDevice->RxJumboQueuedCnt = 0;
2456 #endif
2457
2458         /* Reinitialize our copy of the indices. */
2459         pDevice->RxStdProdIdx = 0;
2460         pDevice->RxStdQueuedCnt = 0;
2461
2462 #if T3_JUMBO_RCV_ENTRY_COUNT
2463         pDevice->RxJumboProdIdx = 0;
2464 #endif                          /* T3_JUMBO_RCV_ENTRY_COUNT */
2465
2466         /* Configure the MAC address. */
2467         LM_SetMacAddress (pDevice, pDevice->NodeAddress);
2468
2469         /* Initialize the transmit random backoff seed. */
2470         Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] +
2471                    pDevice->NodeAddress[2] + pDevice->NodeAddress[3] +
2472                    pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) &
2473             MAC_TX_BACKOFF_SEED_MASK;
2474         REG_WR (pDevice, MacCtrl.TxBackoffSeed, Value32);
2475
2476         /* Receive MTU.  Frames larger than the MTU is marked as oversized. */
2477         REG_WR (pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8);  /* CRC + VLAN. */
2478
2479         /* Configure Time slot/IPG per 802.3 */
2480         REG_WR (pDevice, MacCtrl.TxLengths, 0x2620);
2481
2482         /*
2483          * Configure Receive Rules so that packets don't match
2484          * Programmble rule will be queued to Return Ring 1
2485          */
2486         REG_WR (pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS);
2487
2488         /*
2489          * Configure to have 16 Classes of Services (COS) and one
2490          * queue per class.  Bad frames are queued to RRR#1.
2491          * And frames don't match rules are also queued to COS#1.
2492          */
2493         REG_WR (pDevice, RcvListPlmt.Config, 0x181);
2494
2495         /* Enable Receive Placement Statistics */
2496         REG_WR (pDevice, RcvListPlmt.StatsEnableMask, 0xffffff);
2497         REG_WR (pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE);
2498
2499         /* Enable Send Data Initator Statistics */
2500         REG_WR (pDevice, SndDataIn.StatsEnableMask, 0xffffff);
2501         REG_WR (pDevice, SndDataIn.StatsCtrl,
2502                 T3_SND_DATA_IN_STATS_CTRL_ENABLE |
2503                 T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE);
2504
2505         /* Disable the host coalescing state machine before configuring it's */
2506         /* parameters. */
2507         REG_WR (pDevice, HostCoalesce.Mode, 0);
2508         for (j = 0; j < 2000; j++) {
2509                 Value32 = REG_RD (pDevice, HostCoalesce.Mode);
2510                 if (!(Value32 & HOST_COALESCE_ENABLE)) {
2511                         break;
2512                 }
2513                 MM_Wait (10);
2514         }
2515
2516         /* Host coalescing configurations. */
2517         REG_WR (pDevice, HostCoalesce.RxCoalescingTicks,
2518                 pDevice->RxCoalescingTicks);
2519         REG_WR (pDevice, HostCoalesce.TxCoalescingTicks,
2520                 pDevice->TxCoalescingTicks);
2521         REG_WR (pDevice, HostCoalesce.RxMaxCoalescedFrames,
2522                 pDevice->RxMaxCoalescedFrames);
2523         REG_WR (pDevice, HostCoalesce.TxMaxCoalescedFrames,
2524                 pDevice->TxMaxCoalescedFrames);
2525         REG_WR (pDevice, HostCoalesce.RxCoalescedTickDuringInt,
2526                 pDevice->RxCoalescingTicksDuringInt);
2527         REG_WR (pDevice, HostCoalesce.TxCoalescedTickDuringInt,
2528                 pDevice->TxCoalescingTicksDuringInt);
2529         REG_WR (pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt,
2530                 pDevice->RxMaxCoalescedFramesDuringInt);
2531         REG_WR (pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt,
2532                 pDevice->TxMaxCoalescedFramesDuringInt);
2533
2534         /* Initialize the address of the status block.  The NIC will DMA */
2535         /* the status block to this memory which resides on the host. */
2536         REG_WR (pDevice, HostCoalesce.StatusBlkHostAddr.High,
2537                 pDevice->StatusBlkPhy.High);
2538         REG_WR (pDevice, HostCoalesce.StatusBlkHostAddr.Low,
2539                 pDevice->StatusBlkPhy.Low);
2540
2541         /* Initialize the address of the statistics block.  The NIC will DMA */
2542         /* the statistics to this block of memory. */
2543         REG_WR (pDevice, HostCoalesce.StatsBlkHostAddr.High,
2544                 pDevice->StatsBlkPhy.High);
2545         REG_WR (pDevice, HostCoalesce.StatsBlkHostAddr.Low,
2546                 pDevice->StatsBlkPhy.Low);
2547
2548         REG_WR (pDevice, HostCoalesce.StatsCoalescingTicks,
2549                 pDevice->StatsCoalescingTicks);
2550
2551         REG_WR (pDevice, HostCoalesce.StatsBlkNicAddr, 0x300);
2552         REG_WR (pDevice, HostCoalesce.StatusBlkNicAddr, 0xb00);
2553
2554         /* Enable Host Coalesing state machine */
2555         REG_WR (pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE |
2556                 pDevice->CoalesceMode);
2557
2558         /* Enable the Receive BD Completion state machine. */
2559         REG_WR (pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE |
2560                 RCV_BD_COMP_MODE_ATTN_ENABLE);
2561
2562         /* Enable the Receive List Placement state machine. */
2563         REG_WR (pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE);
2564
2565         /* Enable the Receive List Selector state machine. */
2566         REG_WR (pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE |
2567                 RCV_LIST_SEL_MODE_ATTN_ENABLE);
2568
2569         /* Enable transmit DMA, clear statistics. */
2570         pDevice->MacMode = MAC_MODE_ENABLE_TX_STATISTICS |
2571             MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE |
2572             MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE;
2573         REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode |
2574                 MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS);
2575
2576         /* GRC miscellaneous local control register. */
2577         pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN |
2578             GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM;
2579
2580         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
2581                 pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
2582                     GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1;
2583         }
2584
2585         REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
2586         MM_Wait (40);
2587
2588         /* Reset RX counters. */
2589         for (j = 0; j < sizeof (LM_RX_COUNTERS); j++) {
2590                 ((PLM_UINT8) & pDevice->RxCounters)[j] = 0;
2591         }
2592
2593         /* Reset TX counters. */
2594         for (j = 0; j < sizeof (LM_TX_COUNTERS); j++) {
2595                 ((PLM_UINT8) & pDevice->TxCounters)[j] = 0;
2596         }
2597
2598         MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 0);
2599
2600         /* Enable the DMA Completion state machine. */
2601         REG_WR (pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE);
2602
2603         /* Enable the DMA Write state machine. */
2604         Value32 = DMA_WRITE_MODE_ENABLE |
2605             DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
2606             DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
2607             DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
2608             DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
2609             DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
2610             DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
2611             DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
2612             DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
2613         REG_WR (pDevice, DmaWrite.Mode, Value32);
2614
2615         if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
2616                 if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
2617                         Value16 = REG_RD (pDevice, PciCfg.PciXCommand);
2618                         Value16 &=
2619                             ~(PCIX_CMD_MAX_SPLIT_MASK |
2620                               PCIX_CMD_MAX_BURST_MASK);
2621                         Value16 |=
2622                             ((PCIX_CMD_MAX_BURST_CPIOB <<
2623                               PCIX_CMD_MAX_BURST_SHL) &
2624                              PCIX_CMD_MAX_BURST_MASK);
2625                         if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) {
2626                                 Value16 |=
2627                                     (pDevice->
2628                                      SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL)
2629                                     & PCIX_CMD_MAX_SPLIT_MASK;
2630                         }
2631                         REG_WR (pDevice, PciCfg.PciXCommand, Value16);
2632                 }
2633         }
2634
2635         /* Enable the Read DMA state machine. */
2636         Value32 = DMA_READ_MODE_ENABLE |
2637             DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE |
2638             DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE |
2639             DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE |
2640             DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
2641             DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE |
2642             DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
2643             DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE |
2644             DMA_READ_MODE_LONG_READ_ATTN_ENABLE;
2645
2646         if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) {
2647                 Value32 |= DMA_READ_MODE_SPLIT_ENABLE;
2648         }
2649         REG_WR (pDevice, DmaRead.Mode, Value32);
2650
2651         /* Enable the Receive Data Completion state machine. */
2652         REG_WR (pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE |
2653                 RCV_DATA_COMP_MODE_ATTN_ENABLE);
2654
2655         /* Enable the Mbuf Cluster Free state machine. */
2656         REG_WR (pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE);
2657
2658         /* Enable the Send Data Completion state machine. */
2659         REG_WR (pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE);
2660
2661         /* Enable the Send BD Completion state machine. */
2662         REG_WR (pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE |
2663                 SND_BD_COMP_MODE_ATTN_ENABLE);
2664
2665         /* Enable the Receive BD Initiator state machine. */
2666         REG_WR (pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE |
2667                 RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE);
2668
2669         /* Enable the Receive Data and Receive BD Initiator state machine. */
2670         REG_WR (pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE |
2671                 RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE);
2672
2673         /* Enable the Send Data Initiator state machine. */
2674         REG_WR (pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE);
2675
2676         /* Enable the Send BD Initiator state machine. */
2677         REG_WR (pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE |
2678                 SND_BD_IN_MODE_ATTN_ENABLE);
2679
2680         /* Enable the Send BD Selector state machine. */
2681         REG_WR (pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE |
2682                 SND_BD_SEL_MODE_ATTN_ENABLE);
2683
2684 #if INCLUDE_5701_AX_FIX
2685         /* Load the firmware for the 5701_A0 workaround. */
2686         if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0) {
2687                 LM_LoadRlsFirmware (pDevice);
2688         }
2689 #endif
2690
2691         /* Enable the transmitter. */
2692         pDevice->TxMode = TX_MODE_ENABLE;
2693         REG_WR (pDevice, MacCtrl.TxMode, pDevice->TxMode);
2694
2695         /* Enable the receiver. */
2696         pDevice->RxMode = RX_MODE_ENABLE;
2697         REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
2698
2699         if (pDevice->RestoreOnWakeUp) {
2700                 pDevice->RestoreOnWakeUp = FALSE;
2701                 pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg;
2702                 pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType;
2703         }
2704
2705         /* Disable auto polling. */
2706         pDevice->MiMode = 0xc0000;
2707         REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
2708
2709         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
2710             T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
2711                 Value32 = LED_CTRL_PHY_MODE_1;
2712         } else {
2713                 if (pDevice->LedMode == LED_MODE_OUTPUT) {
2714                         Value32 = LED_CTRL_PHY_MODE_2;
2715                 } else {
2716                         Value32 = LED_CTRL_PHY_MODE_1;
2717                 }
2718         }
2719         REG_WR (pDevice, MacCtrl.LedCtrl, Value32);
2720
2721         /* Activate Link to enable MAC state machine */
2722         REG_WR (pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN);
2723
2724         if (pDevice->EnableTbi) {
2725                 REG_WR (pDevice, MacCtrl.RxMode, RX_MODE_RESET);
2726                 MM_Wait (10);
2727                 REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
2728                 if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1) {
2729                         REG_WR (pDevice, MacCtrl.SerdesCfg, 0x616000);
2730                 }
2731         }
2732         /* Setup the phy chip. */
2733         LM_SetupPhy (pDevice);
2734
2735         if (!pDevice->EnableTbi) {
2736                 /* Clear CRC stats */
2737                 LM_ReadPhy (pDevice, 0x1e, &Value32);
2738                 LM_WritePhy (pDevice, 0x1e, Value32 | 0x8000);
2739                 LM_ReadPhy (pDevice, 0x14, &Value32);
2740         }
2741
2742         /* Set up the receive mask. */
2743         LM_SetReceiveMask (pDevice, pDevice->ReceiveMask);
2744
2745         /* Queue Rx packet buffers. */
2746         if (pDevice->QueueRxPackets) {
2747                 LM_QueueRxPackets (pDevice);
2748         }
2749
2750         /* Enable interrupt to the host. */
2751         if (pDevice->InitDone) {
2752                 LM_EnableInterrupt (pDevice);
2753         }
2754
2755         return LM_STATUS_SUCCESS;
2756 }                               /* LM_ResetAdapter */
2757
2758 /******************************************************************************/
2759 /* Description:                                                               */
2760 /*    This routine disables the adapter from generating interrupts.           */
2761 /*                                                                            */
2762 /* Return:                                                                    */
2763 /*    LM_STATUS_SUCCESS                                                       */
2764 /******************************************************************************/
2765 LM_STATUS LM_DisableInterrupt (PLM_DEVICE_BLOCK pDevice)
2766 {
2767         REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl |
2768                 MISC_HOST_CTRL_MASK_PCI_INT);
2769         MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 1);
2770
2771         return LM_STATUS_SUCCESS;
2772 }
2773
2774 /******************************************************************************/
2775 /* Description:                                                               */
2776 /*    This routine enables the adapter to generate interrupts.                */
2777 /*                                                                            */
2778 /* Return:                                                                    */
2779 /*    LM_STATUS_SUCCESS                                                       */
2780 /******************************************************************************/
2781 LM_STATUS LM_EnableInterrupt (PLM_DEVICE_BLOCK pDevice)
2782 {
2783         REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl &
2784                 ~MISC_HOST_CTRL_MASK_PCI_INT);
2785         MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 0);
2786
2787         if (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) {
2788                 REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
2789                         GRC_MISC_LOCAL_CTRL_SET_INT);
2790         }
2791
2792         return LM_STATUS_SUCCESS;
2793 }
2794
2795 /******************************************************************************/
2796 /* Description:                                                               */
2797 /*    This routine puts a packet on the wire if there is a transmit DMA       */
2798 /*    descriptor available; otherwise the packet is queued for later          */
2799 /*    transmission.  If the second argue is NULL, this routine will put       */
2800 /*    the queued packet on the wire if possible.                              */
2801 /*                                                                            */
2802 /* Return:                                                                    */
2803 /*    LM_STATUS_SUCCESS                                                       */
2804 /******************************************************************************/
2805 #if 0
2806 LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
2807 {
2808         LM_UINT32 FragCount;
2809         PT3_SND_BD pSendBd;
2810         PT3_SND_BD pShadowSendBd;
2811         LM_UINT32 Value32, Len;
2812         LM_UINT32 Idx;
2813
2814         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
2815                 return LM_5700SendPacket (pDevice, pPacket);
2816         }
2817
2818         /* Update the SendBdLeft count. */
2819         atomic_sub (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
2820
2821         /* Initalize the send buffer descriptors. */
2822         Idx = pDevice->SendProdIdx;
2823
2824         pSendBd = &pDevice->pSendBdVirt[Idx];
2825
2826         /* Next producer index. */
2827         if (pDevice->NicSendBd == TRUE) {
2828                 T3_64BIT_HOST_ADDR paddr;
2829
2830                 pShadowSendBd = &pDevice->ShadowSendBd[Idx];
2831                 for (FragCount = 0;;) {
2832                         MM_MapTxDma (pDevice, pPacket, &paddr, &Len, FragCount);
2833                         /* Initialize the pointer to the send buffer fragment. */
2834                         if (paddr.High != pShadowSendBd->HostAddr.High) {
2835                                 __raw_writel (paddr.High,
2836                                               &(pSendBd->HostAddr.High));
2837                                 pShadowSendBd->HostAddr.High = paddr.High;
2838                         }
2839                         __raw_writel (paddr.Low, &(pSendBd->HostAddr.Low));
2840
2841                         /* Setup the control flags and send buffer size. */
2842                         Value32 = (Len << 16) | pPacket->Flags;
2843
2844                         Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
2845
2846                         FragCount++;
2847                         if (FragCount >= pPacket->u.Tx.FragCount) {
2848                                 Value32 |= SND_BD_FLAG_END;
2849                                 if (Value32 != pShadowSendBd->u1.Len_Flags) {
2850                                         __raw_writel (Value32,
2851                                                       &(pSendBd->u1.Len_Flags));
2852                                         pShadowSendBd->u1.Len_Flags = Value32;
2853                                 }
2854                                 if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
2855                                         __raw_writel (pPacket->VlanTag,
2856                                                       &(pSendBd->u2.VlanTag));
2857                                 }
2858                                 break;
2859                         } else {
2860                                 if (Value32 != pShadowSendBd->u1.Len_Flags) {
2861                                         __raw_writel (Value32,
2862                                                       &(pSendBd->u1.Len_Flags));
2863                                         pShadowSendBd->u1.Len_Flags = Value32;
2864                                 }
2865                                 if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
2866                                         __raw_writel (pPacket->VlanTag,
2867                                                       &(pSendBd->u2.VlanTag));
2868                                 }
2869                         }
2870
2871                         pSendBd++;
2872                         pShadowSendBd++;
2873                         if (Idx == 0) {
2874                                 pSendBd = &pDevice->pSendBdVirt[0];
2875                                 pShadowSendBd = &pDevice->ShadowSendBd[0];
2876                         }
2877                 }               /* for */
2878
2879                 /* Put the packet descriptor in the ActiveQ. */
2880                 QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);
2881
2882                 wmb ();
2883                 MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
2884
2885         } else {
2886                 for (FragCount = 0;;) {
2887                         /* Initialize the pointer to the send buffer fragment. */
2888                         MM_MapTxDma (pDevice, pPacket, &pSendBd->HostAddr, &Len,
2889                                      FragCount);
2890
2891                         pSendBd->u2.VlanTag = pPacket->VlanTag;
2892
2893                         /* Setup the control flags and send buffer size. */
2894                         Value32 = (Len << 16) | pPacket->Flags;
2895
2896                         Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
2897
2898                         FragCount++;
2899                         if (FragCount >= pPacket->u.Tx.FragCount) {
2900                                 pSendBd->u1.Len_Flags =
2901                                     Value32 | SND_BD_FLAG_END;
2902                                 break;
2903                         } else {
2904                                 pSendBd->u1.Len_Flags = Value32;
2905                         }
2906                         pSendBd++;
2907                         if (Idx == 0) {
2908                                 pSendBd = &pDevice->pSendBdVirt[0];
2909                         }
2910                 }               /* for */
2911
2912                 /* Put the packet descriptor in the ActiveQ. */
2913                 QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);
2914
2915                 wmb ();
2916                 MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
2917
2918         }
2919
2920         /* Update the producer index. */
2921         pDevice->SendProdIdx = Idx;
2922
2923         return LM_STATUS_SUCCESS;
2924 }
2925 #endif
2926
2927 LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
2928 {
2929         LM_UINT32 FragCount;
2930         PT3_SND_BD pSendBd, pTmpSendBd, pShadowSendBd;
2931         T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT];
2932         LM_UINT32 StartIdx, Idx;
2933
2934         while (1) {
2935                 /* Initalize the send buffer descriptors. */
2936                 StartIdx = Idx = pDevice->SendProdIdx;
2937
2938                 if (pDevice->NicSendBd) {
2939                         pTmpSendBd = pSendBd = &NicSendBdArr[0];
2940                 } else {
2941                         pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx];
2942                 }
2943
2944                 /* Next producer index. */
2945                 for (FragCount = 0;;) {
2946                         LM_UINT32 Value32, Len;
2947
2948                         /* Initialize the pointer to the send buffer fragment. */
2949                         MM_MapTxDma (pDevice, pPacket, &pSendBd->HostAddr, &Len,
2950                                      FragCount);
2951
2952                         pSendBd->u2.VlanTag = pPacket->VlanTag;
2953
2954                         /* Setup the control flags and send buffer size. */
2955                         Value32 = (Len << 16) | pPacket->Flags;
2956
2957                         Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
2958
2959                         FragCount++;
2960                         if (FragCount >= pPacket->u.Tx.FragCount) {
2961                                 pSendBd->u1.Len_Flags =
2962                                     Value32 | SND_BD_FLAG_END;
2963                                 break;
2964                         } else {
2965                                 pSendBd->u1.Len_Flags = Value32;
2966                         }
2967                         pSendBd++;
2968                         if ((Idx == 0) && !pDevice->NicSendBd) {
2969                                 pSendBd = &pDevice->pSendBdVirt[0];
2970                         }
2971                 }               /* for */
2972                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
2973                         if (LM_Test4GBoundary (pDevice, pPacket, pTmpSendBd) ==
2974                             LM_STATUS_SUCCESS) {
2975                                 if (MM_CoalesceTxBuffer (pDevice, pPacket) !=
2976                                     LM_STATUS_SUCCESS) {
2977                                         QQ_PushHead (&pDevice->TxPacketFreeQ.
2978                                                      Container, pPacket);
2979                                         return LM_STATUS_FAILURE;
2980                                 }
2981                                 continue;
2982                         }
2983                 }
2984                 break;
2985         }
2986         /* Put the packet descriptor in the ActiveQ. */
2987         QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);
2988
2989         if (pDevice->NicSendBd) {
2990                 pSendBd = &pDevice->pSendBdVirt[StartIdx];
2991                 pShadowSendBd = &pDevice->ShadowSendBd[StartIdx];
2992
2993                 while (StartIdx != Idx) {
2994                         LM_UINT32 Value32;
2995
2996                         if ((Value32 = pTmpSendBd->HostAddr.High) !=
2997                             pShadowSendBd->HostAddr.High) {
2998                                 __raw_writel (Value32,
2999                                               &(pSendBd->HostAddr.High));
3000                                 pShadowSendBd->HostAddr.High = Value32;
3001                         }
3002
3003                         __raw_writel (pTmpSendBd->HostAddr.Low,
3004                                       &(pSendBd->HostAddr.Low));
3005
3006                         if ((Value32 = pTmpSendBd->u1.Len_Flags) !=
3007                             pShadowSendBd->u1.Len_Flags) {
3008                                 __raw_writel (Value32,
3009                                               &(pSendBd->u1.Len_Flags));
3010                                 pShadowSendBd->u1.Len_Flags = Value32;
3011                         }
3012
3013                         if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
3014                                 __raw_writel (pTmpSendBd->u2.VlanTag,
3015                                               &(pSendBd->u2.VlanTag));
3016                         }
3017
3018                         StartIdx =
3019                             (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
3020                         if (StartIdx == 0)
3021                                 pSendBd = &pDevice->pSendBdVirt[0];
3022                         else
3023                                 pSendBd++;
3024                         pTmpSendBd++;
3025                 }
3026                 wmb ();
3027                 MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
3028
3029                 if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
3030                         MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
3031                 }
3032         } else {
3033                 wmb ();
3034                 MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
3035
3036                 if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
3037                         MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low,
3038                                    Idx);
3039                 }
3040         }
3041
3042         /* Update the SendBdLeft count. */
3043         atomic_sub (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
3044
3045         /* Update the producer index. */
3046         pDevice->SendProdIdx = Idx;
3047
3048         return LM_STATUS_SUCCESS;
3049 }
3050
3051 STATIC LM_STATUS
3052 LM_Test4GBoundary (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
3053                    PT3_SND_BD pSendBd)
3054 {
3055         int FragCount;
3056         LM_UINT32 Idx, Base, Len;
3057
3058         Idx = pDevice->SendProdIdx;
3059         for (FragCount = 0;;) {
3060                 Len = pSendBd->u1.Len_Flags >> 16;
3061                 if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) &&
3062                     (pSendBd->HostAddr.High == 0) &&
3063                     ((Base + 8 + Len) < Base)) {
3064                         return LM_STATUS_SUCCESS;
3065                 }
3066                 FragCount++;
3067                 if (FragCount >= pPacket->u.Tx.FragCount) {
3068                         break;
3069                 }
3070                 pSendBd++;
3071                 if (!pDevice->NicSendBd) {
3072                         Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
3073                         if (Idx == 0) {
3074                                 pSendBd = &pDevice->pSendBdVirt[0];
3075                         }
3076                 }
3077         }
3078         return LM_STATUS_FAILURE;
3079 }
3080
3081 /******************************************************************************/
3082 /* Description:                                                               */
3083 /*                                                                            */
3084 /* Return:                                                                    */
3085 /******************************************************************************/
3086 __inline static unsigned long
3087 ComputeCrc32 (unsigned char *pBuffer, unsigned long BufferSize)
3088 {
3089         unsigned long Reg;
3090         unsigned long Tmp;
3091         unsigned long j, k;
3092
3093         Reg = 0xffffffff;
3094
3095         for (j = 0; j < BufferSize; j++) {
3096                 Reg ^= pBuffer[j];
3097
3098                 for (k = 0; k < 8; k++) {
3099                         Tmp = Reg & 0x01;
3100
3101                         Reg >>= 1;
3102
3103                         if (Tmp) {
3104                                 Reg ^= 0xedb88320;
3105                         }
3106                 }
3107         }
3108
3109         return ~Reg;
3110 }                               /* ComputeCrc32 */
3111
3112 /******************************************************************************/
3113 /* Description:                                                               */
3114 /*    This routine sets the receive control register according to ReceiveMask */
3115 /*                                                                            */
3116 /* Return:                                                                    */
3117 /*    LM_STATUS_SUCCESS                                                       */
3118 /******************************************************************************/
3119 LM_STATUS LM_SetReceiveMask (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask)
3120 {
3121         LM_UINT32 ReceiveMask;
3122         LM_UINT32 RxMode;
3123         LM_UINT32 j, k;
3124
3125         ReceiveMask = Mask;
3126
3127         RxMode = pDevice->RxMode;
3128
3129         if (Mask & LM_ACCEPT_UNICAST) {
3130                 Mask &= ~LM_ACCEPT_UNICAST;
3131         }
3132
3133         if (Mask & LM_ACCEPT_MULTICAST) {
3134                 Mask &= ~LM_ACCEPT_MULTICAST;
3135         }
3136
3137         if (Mask & LM_ACCEPT_ALL_MULTICAST) {
3138                 Mask &= ~LM_ACCEPT_ALL_MULTICAST;
3139         }
3140
3141         if (Mask & LM_ACCEPT_BROADCAST) {
3142                 Mask &= ~LM_ACCEPT_BROADCAST;
3143         }
3144
3145         RxMode &= ~RX_MODE_PROMISCUOUS_MODE;
3146         if (Mask & LM_PROMISCUOUS_MODE) {
3147                 RxMode |= RX_MODE_PROMISCUOUS_MODE;
3148                 Mask &= ~LM_PROMISCUOUS_MODE;
3149         }
3150
3151         RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED);
3152         if (Mask & LM_ACCEPT_ERROR_PACKET) {
3153                 RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED;
3154                 Mask &= ~LM_ACCEPT_ERROR_PACKET;
3155         }
3156
3157         /* Make sure all the bits are valid before committing changes. */
3158         if (Mask) {
3159                 return LM_STATUS_FAILURE;
3160         }
3161
3162         /* Commit the new filter. */
3163         pDevice->RxMode = RxMode;
3164         REG_WR (pDevice, MacCtrl.RxMode, RxMode);
3165
3166         pDevice->ReceiveMask = ReceiveMask;
3167
3168         /* Set up the MC hash table. */
3169         if (ReceiveMask & LM_ACCEPT_ALL_MULTICAST) {
3170                 for (k = 0; k < 4; k++) {
3171                         REG_WR (pDevice, MacCtrl.HashReg[k], 0xffffffff);
3172                 }
3173         } else if (ReceiveMask & LM_ACCEPT_MULTICAST) {
3174                 LM_UINT32 HashReg[4];
3175
3176                 HashReg[0] = 0;
3177                 HashReg[1] = 0;
3178                 HashReg[2] = 0;
3179                 HashReg[3] = 0;
3180                 for (j = 0; j < pDevice->McEntryCount; j++) {
3181                         LM_UINT32 RegIndex;
3182                         LM_UINT32 Bitpos;
3183                         LM_UINT32 Crc32;
3184
3185                         Crc32 =
3186                             ComputeCrc32 (pDevice->McTable[j],
3187                                           ETHERNET_ADDRESS_SIZE);
3188
3189                         /* The most significant 7 bits of the CRC32 (no inversion), */
3190                         /* are used to index into one of the possible 128 bit positions. */
3191                         Bitpos = ~Crc32 & 0x7f;
3192
3193                         /* Hash register index. */
3194                         RegIndex = (Bitpos & 0x60) >> 5;
3195
3196                         /* Bit to turn on within a hash register. */
3197                         Bitpos &= 0x1f;
3198
3199                         /* Enable the multicast bit. */
3200                         HashReg[RegIndex] |= (1 << Bitpos);
3201                 }
3202
3203                 /* REV_AX has problem with multicast filtering where it uses both */
3204                 /* DA and SA to perform hashing. */
3205                 for (k = 0; k < 4; k++) {
3206                         REG_WR (pDevice, MacCtrl.HashReg[k], HashReg[k]);
3207                 }
3208         } else {
3209                 /* Reject all multicast frames. */
3210                 for (j = 0; j < 4; j++) {
3211                         REG_WR (pDevice, MacCtrl.HashReg[j], 0);
3212                 }
3213         }
3214
3215         /* By default, Tigon3 will accept broadcast frames.  We need to setup */
3216         if (ReceiveMask & LM_ACCEPT_BROADCAST) {
3217                 REG_WR (pDevice,
3218                         MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
3219                         REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
3220                 REG_WR (pDevice,
3221                         MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
3222                         REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
3223                 REG_WR (pDevice,
3224                         MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
3225                         REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
3226                 REG_WR (pDevice,
3227                         MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
3228                         REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
3229         } else {
3230                 REG_WR (pDevice,
3231                         MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
3232                         REJECT_BROADCAST_RULE1_RULE);
3233                 REG_WR (pDevice,
3234                         MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
3235                         REJECT_BROADCAST_RULE1_VALUE);
3236                 REG_WR (pDevice,
3237                         MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
3238                         REJECT_BROADCAST_RULE2_RULE);
3239                 REG_WR (pDevice,
3240                         MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
3241                         REJECT_BROADCAST_RULE2_VALUE);
3242         }
3243
3244         /* disable the rest of the rules. */
3245         for (j = RCV_LAST_RULE_IDX; j < 16; j++) {
3246                 REG_WR (pDevice, MacCtrl.RcvRules[j].Rule, 0);
3247                 REG_WR (pDevice, MacCtrl.RcvRules[j].Value, 0);
3248         }
3249
3250         return LM_STATUS_SUCCESS;
3251 }                               /* LM_SetReceiveMask */
3252
3253 /******************************************************************************/
3254 /* Description:                                                               */
3255 /*    Disable the interrupt and put the transmitter and receiver engines in   */
3256 /*    an idle state.  Also aborts all pending send requests and receive       */
3257 /*    buffers.                                                                */
3258 /*                                                                            */
3259 /* Return:                                                                    */
3260 /*    LM_STATUS_SUCCESS                                                       */
3261 /******************************************************************************/
3262 LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice)
3263 {
3264         PLM_PACKET pPacket;
3265         LM_UINT Idx;
3266
3267         LM_DisableInterrupt (pDevice);
3268
3269         /* Disable all the state machines. */
3270         LM_CntrlBlock (pDevice, T3_BLOCK_MAC_RX_ENGINE, LM_DISABLE);
3271         LM_CntrlBlock (pDevice, T3_BLOCK_RX_BD_INITIATOR, LM_DISABLE);
3272         LM_CntrlBlock (pDevice, T3_BLOCK_RX_LIST_PLMT, LM_DISABLE);
3273         LM_CntrlBlock (pDevice, T3_BLOCK_RX_LIST_SELECTOR, LM_DISABLE);
3274         LM_CntrlBlock (pDevice, T3_BLOCK_RX_DATA_INITIATOR, LM_DISABLE);
3275         LM_CntrlBlock (pDevice, T3_BLOCK_RX_DATA_COMP, LM_DISABLE);
3276         LM_CntrlBlock (pDevice, T3_BLOCK_RX_BD_COMP, LM_DISABLE);
3277
3278         LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_SELECTOR, LM_DISABLE);
3279         LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_INITIATOR, LM_DISABLE);
3280         LM_CntrlBlock (pDevice, T3_BLOCK_SEND_DATA_INITIATOR, LM_DISABLE);
3281         LM_CntrlBlock (pDevice, T3_BLOCK_DMA_RD, LM_DISABLE);
3282         LM_CntrlBlock (pDevice, T3_BLOCK_SEND_DATA_COMP, LM_DISABLE);
3283         LM_CntrlBlock (pDevice, T3_BLOCK_DMA_COMP, LM_DISABLE);
3284         LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_COMP, LM_DISABLE);
3285
3286         /* Clear TDE bit */
3287         pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE;
3288         REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
3289
3290         LM_CntrlBlock (pDevice, T3_BLOCK_MAC_TX_ENGINE, LM_DISABLE);
3291         LM_CntrlBlock (pDevice, T3_BLOCK_HOST_COALESING, LM_DISABLE);
3292         LM_CntrlBlock (pDevice, T3_BLOCK_DMA_WR, LM_DISABLE);
3293         LM_CntrlBlock (pDevice, T3_BLOCK_MBUF_CLUSTER_FREE, LM_DISABLE);
3294
3295         /* Reset all FTQs */
3296         REG_WR (pDevice, Ftq.Reset, 0xffffffff);
3297         REG_WR (pDevice, Ftq.Reset, 0x0);
3298
3299         LM_CntrlBlock (pDevice, T3_BLOCK_MBUF_MANAGER, LM_DISABLE);
3300         LM_CntrlBlock (pDevice, T3_BLOCK_MEM_ARBITOR, LM_DISABLE);
3301
3302         MM_ACQUIRE_INT_LOCK (pDevice);
3303
3304         /* Abort packets that have already queued to go out. */
3305         pPacket = (PLM_PACKET) QQ_PopHead (&pDevice->TxPacketActiveQ.Container);
3306         while (pPacket) {
3307
3308                 pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED;
3309                 pDevice->TxCounters.TxPacketAbortedCnt++;
3310
3311                 atomic_add (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
3312
3313                 QQ_PushTail (&pDevice->TxPacketXmittedQ.Container, pPacket);
3314
3315                 pPacket = (PLM_PACKET)
3316                     QQ_PopHead (&pDevice->TxPacketActiveQ.Container);
3317         }
3318
3319         /* Cleanup the receive return rings. */
3320         LM_ServiceRxInterrupt (pDevice);
3321
3322         /* Don't want to indicate rx packets in Ndis miniport shutdown context. */
3323         /* Doing so may cause system crash. */
3324         if (!pDevice->ShuttingDown) {
3325                 /* Indicate packets to the protocol. */
3326                 MM_IndicateTxPackets (pDevice);
3327
3328                 /* Indicate received packets to the protocols. */
3329                 MM_IndicateRxPackets (pDevice);
3330         } else {
3331                 /* Move the receive packet descriptors in the ReceivedQ to the */
3332                 /* free queue. */
3333                 for (;;) {
3334                         pPacket =
3335                             (PLM_PACKET) QQ_PopHead (&pDevice->
3336                                                      RxPacketReceivedQ.
3337                                                      Container);
3338                         if (pPacket == NULL) {
3339                                 break;
3340                         }
3341                         QQ_PushTail (&pDevice->RxPacketFreeQ.Container,
3342                                      pPacket);
3343                 }
3344         }
3345
3346         /* Clean up the Std Receive Producer ring. */
3347         Idx = pDevice->pStatusBlkVirt->RcvStdConIdx;
3348
3349         while (Idx != pDevice->RxStdProdIdx) {
3350                 pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) +
3351                                         MM_UINT_PTR (pDevice->pRxStdBdVirt[Idx].
3352                                                      Opaque));
3353
3354                 QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
3355
3356                 Idx = (Idx + 1) & T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
3357         }                       /* while */
3358
3359         /* Reinitialize our copy of the indices. */
3360         pDevice->RxStdProdIdx = 0;
3361
3362 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
3363         /* Clean up the Jumbo Receive Producer ring. */
3364         Idx = pDevice->pStatusBlkVirt->RcvJumboConIdx;
3365
3366         while (Idx != pDevice->RxJumboProdIdx) {
3367                 pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) +
3368                                         MM_UINT_PTR (pDevice->
3369                                                      pRxJumboBdVirt[Idx].
3370                                                      Opaque));
3371
3372                 QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
3373
3374                 Idx = (Idx + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
3375         }                       /* while */
3376
3377         /* Reinitialize our copy of the indices. */
3378         pDevice->RxJumboProdIdx = 0;
3379 #endif                          /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
3380
3381         MM_RELEASE_INT_LOCK (pDevice);
3382
3383         /* Initialize the statistis Block */
3384         pDevice->pStatusBlkVirt->Status = 0;
3385         pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
3386         pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
3387         pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
3388
3389         return LM_STATUS_SUCCESS;
3390 }                               /* LM_Abort */
3391
3392 /******************************************************************************/
3393 /* Description:                                                               */
3394 /*    Disable the interrupt and put the transmitter and receiver engines in   */
3395 /*    an idle state.  Aborts all pending send requests and receive buffers.   */
3396 /*    Also free all the receive buffers.                                      */
3397 /*                                                                            */
3398 /* Return:                                                                    */
3399 /*    LM_STATUS_SUCCESS                                                       */
3400 /******************************************************************************/
3401 LM_STATUS LM_Halt (PLM_DEVICE_BLOCK pDevice)
3402 {
3403         PLM_PACKET pPacket;
3404         LM_UINT32 EntryCnt;
3405
3406         LM_Abort (pDevice);
3407
3408         /* Get the number of entries in the queue. */
3409         EntryCnt = QQ_GetEntryCnt (&pDevice->RxPacketFreeQ.Container);
3410
3411         /* Make sure all the packets have been accounted for. */
3412         for (EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++) {
3413                 pPacket =
3414                     (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
3415                 if (pPacket == 0)
3416                         break;
3417
3418                 MM_FreeRxBuffer (pDevice, pPacket);
3419
3420                 QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
3421         }
3422
3423         LM_ResetChip (pDevice);
3424
3425         /* Restore PCI configuration registers. */
3426         MM_WriteConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG,
3427                           pDevice->SavedCacheLineReg);
3428         LM_RegWrInd (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
3429                      (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
3430
3431         /* Reprogram the MAC address. */
3432         LM_SetMacAddress (pDevice, pDevice->NodeAddress);
3433
3434         return LM_STATUS_SUCCESS;
3435 }                               /* LM_Halt */
3436
3437 STATIC LM_STATUS LM_ResetChip (PLM_DEVICE_BLOCK pDevice)
3438 {
3439         LM_UINT32 Value32;
3440         LM_UINT32 j;
3441
3442         /* Wait for access to the nvram interface before resetting.  This is */
3443         /* a workaround to prevent EEPROM corruption. */
3444         if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
3445             T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
3446                 /* Request access to the flash interface. */
3447                 REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
3448
3449                 for (j = 0; j < 100000; j++) {
3450                         Value32 = REG_RD (pDevice, Nvram.SwArb);
3451                         if (Value32 & SW_ARB_GNT1) {
3452                                 break;
3453                         }
3454                         MM_Wait (10);
3455                 }
3456         }
3457
3458         /* Global reset. */
3459         REG_WR (pDevice, Grc.MiscCfg, GRC_MISC_CFG_CORE_CLOCK_RESET);
3460         MM_Wait (40);
3461         MM_Wait (40);
3462         MM_Wait (40);
3463
3464         /* make sure we re-enable indirect accesses */
3465         MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG,
3466                           pDevice->MiscHostCtrl);
3467
3468         /* Set MAX PCI retry to zero. */
3469         Value32 =
3470             T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE;
3471         if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
3472                 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
3473                         Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
3474                 }
3475         }
3476         MM_WriteConfig32 (pDevice, T3_PCI_STATE_REG, Value32);
3477
3478         /* Restore PCI command register. */
3479         MM_WriteConfig32 (pDevice, PCI_COMMAND_REG,
3480                           pDevice->PciCommandStatusWords);
3481
3482         /* Disable PCI-X relaxed ordering bit. */
3483         MM_ReadConfig32 (pDevice, PCIX_CAP_REG, &Value32);
3484         Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING;
3485         MM_WriteConfig32 (pDevice, PCIX_CAP_REG, Value32);
3486
3487         /* Enable memory arbiter. */
3488         REG_WR (pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
3489
3490 #ifdef BIG_ENDIAN_PCI           /* This from jfd */
3491         Value32 = GRC_MODE_WORD_SWAP_DATA | GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
3492 #else
3493 #ifdef BIG_ENDIAN_HOST
3494         /* Reconfigure the mode register. */
3495         Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
3496             GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
3497             GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA;
3498 #else
3499         /* Reconfigure the mode register. */
3500         Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
3501 #endif
3502 #endif
3503         REG_WR (pDevice, Grc.Mode, Value32);
3504
3505         /* Prevent PXE from restarting. */
3506         MEM_WR_OFFSET (pDevice, 0x0b50, T3_MAGIC_NUM);
3507
3508         if (pDevice->EnableTbi) {
3509                 pDevice->MacMode = MAC_MODE_PORT_MODE_TBI;
3510                 REG_WR (pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI);
3511         } else {
3512                 REG_WR (pDevice, MacCtrl.Mode, 0);
3513         }
3514
3515         /* Wait for the firmware to finish initialization. */
3516         for (j = 0; j < 100000; j++) {
3517                 MM_Wait (10);
3518
3519                 Value32 = MEM_RD_OFFSET (pDevice, 0x0b50);
3520                 if (Value32 == ~T3_MAGIC_NUM) {
3521                         break;
3522                 }
3523         }
3524         return LM_STATUS_SUCCESS;
3525 }
3526
3527 /******************************************************************************/
3528 /* Description:                                                               */
3529 /*                                                                            */
3530 /* Return:                                                                    */
3531 /******************************************************************************/
3532 __inline static void LM_ServiceTxInterrupt (PLM_DEVICE_BLOCK pDevice)
3533 {
3534         PLM_PACKET pPacket;
3535         LM_UINT32 HwConIdx;
3536         LM_UINT32 SwConIdx;
3537
3538         HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
3539
3540         /* Get our copy of the consumer index.  The buffer descriptors */
3541         /* that are in between the consumer indices are freed. */
3542         SwConIdx = pDevice->SendConIdx;
3543
3544         /* Move the packets from the TxPacketActiveQ that are sent out to */
3545         /* the TxPacketXmittedQ.  Packets that are sent use the */
3546         /* descriptors that are between SwConIdx and HwConIdx. */
3547         while (SwConIdx != HwConIdx) {
3548                 /* Get the packet that was sent from the TxPacketActiveQ. */
3549                 pPacket =
3550                     (PLM_PACKET) QQ_PopHead (&pDevice->TxPacketActiveQ.
3551                                              Container);
3552
3553                 /* Set the return status. */
3554                 pPacket->PacketStatus = LM_STATUS_SUCCESS;
3555
3556                 /* Put the packet in the TxPacketXmittedQ for indication later. */
3557                 QQ_PushTail (&pDevice->TxPacketXmittedQ.Container, pPacket);
3558
3559                 /* Move to the next packet's BD. */
3560                 SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) &
3561                     T3_SEND_RCB_ENTRY_COUNT_MASK;
3562
3563                 /* Update the number of unused BDs. */
3564                 atomic_add (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
3565
3566                 /* Get the new updated HwConIdx. */
3567                 HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
3568         }                       /* while */
3569
3570         /* Save the new SwConIdx. */
3571         pDevice->SendConIdx = SwConIdx;
3572
3573 }                               /* LM_ServiceTxInterrupt */
3574
3575 /******************************************************************************/
3576 /* Description:                                                               */
3577 /*                                                                            */
3578 /* Return:                                                                    */
3579 /******************************************************************************/
3580 __inline static void LM_ServiceRxInterrupt (PLM_DEVICE_BLOCK pDevice)
3581 {
3582         PLM_PACKET pPacket;
3583         PT3_RCV_BD pRcvBd;
3584         LM_UINT32 HwRcvRetProdIdx;
3585         LM_UINT32 SwRcvRetConIdx;
3586
3587         /* Loop thru the receive return rings for received packets. */
3588         HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
3589
3590         SwRcvRetConIdx = pDevice->RcvRetConIdx;
3591         while (SwRcvRetConIdx != HwRcvRetProdIdx) {
3592                 pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx];
3593
3594                 /* Get the received packet descriptor. */
3595                 pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) +
3596                                         MM_UINT_PTR (pRcvBd->Opaque));
3597
3598                 /* Check the error flag. */
3599                 if (pRcvBd->ErrorFlag &&
3600                     pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) {
3601                         pPacket->PacketStatus = LM_STATUS_FAILURE;
3602
3603                         pDevice->RxCounters.RxPacketErrCnt++;
3604
3605                         if (pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC) {
3606                                 pDevice->RxCounters.RxErrCrcCnt++;
3607                         }
3608
3609                         if (pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT) {
3610                                 pDevice->RxCounters.RxErrCollCnt++;
3611                         }
3612
3613                         if (pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT) {
3614                                 pDevice->RxCounters.RxErrLinkLostCnt++;
3615                         }
3616
3617                         if (pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR) {
3618                                 pDevice->RxCounters.RxErrPhyDecodeCnt++;
3619                         }
3620
3621                         if (pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) {
3622                                 pDevice->RxCounters.RxErrOddNibbleCnt++;
3623                         }
3624
3625                         if (pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT) {
3626                                 pDevice->RxCounters.RxErrMacAbortCnt++;
3627                         }
3628
3629                         if (pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64) {
3630                                 pDevice->RxCounters.RxErrShortPacketCnt++;
3631                         }
3632
3633                         if (pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES) {
3634                                 pDevice->RxCounters.RxErrNoResourceCnt++;
3635                         }
3636
3637                         if (pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD) {
3638                                 pDevice->RxCounters.RxErrLargePacketCnt++;
3639                         }
3640                 } else {
3641                         pPacket->PacketStatus = LM_STATUS_SUCCESS;
3642                         pPacket->PacketSize = pRcvBd->Len - 4;
3643
3644                         pPacket->Flags = pRcvBd->Flags;
3645                         if (pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG) {
3646                                 pPacket->VlanTag = pRcvBd->VlanTag;
3647                         }
3648
3649                         pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum;
3650                 }
3651
3652                 /* Put the packet descriptor containing the received packet */
3653                 /* buffer in the RxPacketReceivedQ for indication later. */
3654                 QQ_PushTail (&pDevice->RxPacketReceivedQ.Container, pPacket);
3655
3656                 /* Go to the next buffer descriptor. */
3657                 SwRcvRetConIdx = (SwRcvRetConIdx + 1) &
3658                     T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK;
3659
3660                 /* Get the updated HwRcvRetProdIdx. */
3661                 HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
3662         }                       /* while */
3663
3664         pDevice->RcvRetConIdx = SwRcvRetConIdx;
3665
3666         /* Update the receive return ring consumer index. */
3667         MB_REG_WR (pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx);
3668 }                               /* LM_ServiceRxInterrupt */
3669
3670 /******************************************************************************/
3671 /* Description:                                                               */
3672 /*    This is the interrupt event handler routine. It acknowledges all        */
3673 /*    pending interrupts and process all pending events.                      */
3674 /*                                                                            */
3675 /* Return:                                                                    */
3676 /*    LM_STATUS_SUCCESS                                                       */
3677 /******************************************************************************/
3678 LM_STATUS LM_ServiceInterrupts (PLM_DEVICE_BLOCK pDevice)
3679 {
3680         LM_UINT32 Value32;
3681         int ServicePhyInt = FALSE;
3682
3683         /* Setup the phy chip whenever the link status changes. */
3684         if (pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG) {
3685                 Value32 = REG_RD (pDevice, MacCtrl.Status);
3686                 if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) {
3687                         if (Value32 & MAC_STATUS_MI_INTERRUPT) {
3688                                 ServicePhyInt = TRUE;
3689                         }
3690                 } else if (Value32 & MAC_STATUS_LINK_STATE_CHANGED) {
3691                         ServicePhyInt = TRUE;
3692                 }
3693         } else {
3694                 if (pDevice->pStatusBlkVirt->
3695                     Status & STATUS_BLOCK_LINK_CHANGED_STATUS) {
3696                         pDevice->pStatusBlkVirt->Status =
3697                             STATUS_BLOCK_UPDATED | (pDevice->pStatusBlkVirt->
3698                                                     Status &
3699                                                     ~STATUS_BLOCK_LINK_CHANGED_STATUS);
3700                         ServicePhyInt = TRUE;
3701                 }
3702         }
3703 #if INCLUDE_TBI_SUPPORT
3704         if (pDevice->IgnoreTbiLinkChange == TRUE) {
3705                 ServicePhyInt = FALSE;
3706         }
3707 #endif
3708         if (ServicePhyInt == TRUE) {
3709                 LM_SetupPhy (pDevice);
3710         }
3711
3712         /* Service receive and transmit interrupts. */
3713         LM_ServiceRxInterrupt (pDevice);
3714         LM_ServiceTxInterrupt (pDevice);
3715
3716         /* No spinlock for this queue since this routine is serialized. */
3717         if (!QQ_Empty (&pDevice->RxPacketReceivedQ.Container)) {
3718                 /* Indicate receive packets. */
3719                 MM_IndicateRxPackets (pDevice);
3720                 /*       LM_QueueRxPackets(pDevice); */
3721         }
3722
3723         /* No spinlock for this queue since this routine is serialized. */
3724         if (!QQ_Empty (&pDevice->TxPacketXmittedQ.Container)) {
3725                 MM_IndicateTxPackets (pDevice);
3726         }
3727
3728         return LM_STATUS_SUCCESS;
3729 }                               /* LM_ServiceInterrupts */
3730
3731 /******************************************************************************/
3732 /* Description:                                                               */
3733 /*                                                                            */
3734 /* Return:                                                                    */
3735 /******************************************************************************/
3736 LM_STATUS LM_MulticastAdd (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress)
3737 {
3738         PLM_UINT8 pEntry;
3739         LM_UINT32 j;
3740
3741         pEntry = pDevice->McTable[0];
3742         for (j = 0; j < pDevice->McEntryCount; j++) {
3743                 if (IS_ETH_ADDRESS_EQUAL (pEntry, pMcAddress)) {
3744                         /* Found a match, increment the instance count. */
3745                         pEntry[LM_MC_INSTANCE_COUNT_INDEX] += 1;
3746
3747                         return LM_STATUS_SUCCESS;
3748                 }
3749
3750                 pEntry += LM_MC_ENTRY_SIZE;
3751         }
3752
3753         if (pDevice->McEntryCount >= LM_MAX_MC_TABLE_SIZE) {
3754                 return LM_STATUS_FAILURE;
3755         }
3756
3757         pEntry = pDevice->McTable[pDevice->McEntryCount];
3758
3759         COPY_ETH_ADDRESS (pMcAddress, pEntry);
3760         pEntry[LM_MC_INSTANCE_COUNT_INDEX] = 1;
3761
3762         pDevice->McEntryCount++;
3763
3764         LM_SetReceiveMask (pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST);
3765
3766         return LM_STATUS_SUCCESS;
3767 }                               /* LM_MulticastAdd */
3768
3769 /******************************************************************************/
3770 /* Description:                                                               */
3771 /*                                                                            */
3772 /* Return:                                                                    */
3773 /******************************************************************************/
3774 LM_STATUS LM_MulticastDel (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress)
3775 {
3776         PLM_UINT8 pEntry;
3777         LM_UINT32 j;
3778
3779         pEntry = pDevice->McTable[0];
3780         for (j = 0; j < pDevice->McEntryCount; j++) {
3781                 if (IS_ETH_ADDRESS_EQUAL (pEntry, pMcAddress)) {
3782                         /* Found a match, decrement the instance count. */
3783                         pEntry[LM_MC_INSTANCE_COUNT_INDEX] -= 1;
3784
3785                         /* No more instance left, remove the address from the table. */
3786                         /* Move the last entry in the table to the delete slot. */
3787                         if (pEntry[LM_MC_INSTANCE_COUNT_INDEX] == 0 &&
3788                             pDevice->McEntryCount > 1) {
3789
3790                                 COPY_ETH_ADDRESS (pDevice->
3791                                                   McTable[pDevice->
3792                                                           McEntryCount - 1],
3793                                                   pEntry);
3794                                 pEntry[LM_MC_INSTANCE_COUNT_INDEX] =
3795                                     pDevice->McTable[pDevice->McEntryCount - 1]
3796                                     [LM_MC_INSTANCE_COUNT_INDEX];
3797                         }
3798                         pDevice->McEntryCount--;
3799
3800                         /* Update the receive mask if the table is empty. */
3801                         if (pDevice->McEntryCount == 0) {
3802                                 LM_SetReceiveMask (pDevice,
3803                                                    pDevice->
3804                                                    ReceiveMask &
3805                                                    ~LM_ACCEPT_MULTICAST);
3806                         }
3807
3808                         return LM_STATUS_SUCCESS;
3809                 }
3810
3811                 pEntry += LM_MC_ENTRY_SIZE;
3812         }
3813
3814         return LM_STATUS_FAILURE;
3815 }                               /* LM_MulticastDel */
3816
3817 /******************************************************************************/
3818 /* Description:                                                               */
3819 /*                                                                            */
3820 /* Return:                                                                    */
3821 /******************************************************************************/
3822 LM_STATUS LM_MulticastClear (PLM_DEVICE_BLOCK pDevice)
3823 {
3824         pDevice->McEntryCount = 0;
3825
3826         LM_SetReceiveMask (pDevice,
3827                            pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST);
3828
3829         return LM_STATUS_SUCCESS;
3830 }                               /* LM_MulticastClear */
3831
3832 /******************************************************************************/
3833 /* Description:                                                               */
3834 /*                                                                            */
3835 /* Return:                                                                    */
3836 /******************************************************************************/
3837 LM_STATUS LM_SetMacAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress)
3838 {
3839         LM_UINT32 j;
3840
3841         for (j = 0; j < 4; j++) {
3842                 REG_WR (pDevice, MacCtrl.MacAddr[j].High,
3843                         (pMacAddress[0] << 8) | pMacAddress[1]);
3844                 REG_WR (pDevice, MacCtrl.MacAddr[j].Low,
3845                         (pMacAddress[2] << 24) | (pMacAddress[3] << 16) |
3846                         (pMacAddress[4] << 8) | pMacAddress[5]);
3847         }
3848
3849         return LM_STATUS_SUCCESS;
3850 }
3851
3852 /******************************************************************************/
3853 /* Description:                                                               */
3854 /*    Sets up the default line speed, and duplex modes based on the requested */
3855 /*    media type.                                                             */
3856 /*                                                                            */
3857 /* Return:                                                                    */
3858 /*    None.                                                                   */
3859 /******************************************************************************/
3860 static LM_STATUS
3861 LM_TranslateRequestedMediaType (LM_REQUESTED_MEDIA_TYPE RequestedMediaType,
3862                                 PLM_MEDIA_TYPE pMediaType,
3863                                 PLM_LINE_SPEED pLineSpeed,
3864                                 PLM_DUPLEX_MODE pDuplexMode)
3865 {
3866         *pMediaType = LM_MEDIA_TYPE_AUTO;
3867         *pLineSpeed = LM_LINE_SPEED_UNKNOWN;
3868         *pDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
3869
3870         /* determine media type */
3871         switch (RequestedMediaType) {
3872         case LM_REQUESTED_MEDIA_TYPE_BNC:
3873                 *pMediaType = LM_MEDIA_TYPE_BNC;
3874                 *pLineSpeed = LM_LINE_SPEED_10MBPS;
3875                 *pDuplexMode = LM_DUPLEX_MODE_HALF;
3876                 break;
3877
3878         case LM_REQUESTED_MEDIA_TYPE_UTP_AUTO:
3879                 *pMediaType = LM_MEDIA_TYPE_UTP;
3880                 break;
3881
3882         case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS:
3883                 *pMediaType = LM_MEDIA_TYPE_UTP;
3884                 *pLineSpeed = LM_LINE_SPEED_10MBPS;
3885                 *pDuplexMode = LM_DUPLEX_MODE_HALF;
3886                 break;
3887
3888         case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX:
3889                 *pMediaType = LM_MEDIA_TYPE_UTP;
3890                 *pLineSpeed = LM_LINE_SPEED_10MBPS;
3891                 *pDuplexMode = LM_DUPLEX_MODE_FULL;
3892                 break;
3893
3894         case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS:
3895                 *pMediaType = LM_MEDIA_TYPE_UTP;
3896                 *pLineSpeed = LM_LINE_SPEED_100MBPS;
3897                 *pDuplexMode = LM_DUPLEX_MODE_HALF;
3898                 break;
3899
3900         case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX:
3901                 *pMediaType = LM_MEDIA_TYPE_UTP;
3902                 *pLineSpeed = LM_LINE_SPEED_100MBPS;
3903                 *pDuplexMode = LM_DUPLEX_MODE_FULL;
3904                 break;
3905
3906         case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS:
3907                 *pMediaType = LM_MEDIA_TYPE_UTP;
3908                 *pLineSpeed = LM_LINE_SPEED_1000MBPS;
3909                 *pDuplexMode = LM_DUPLEX_MODE_HALF;
3910                 break;
3911
3912         case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX:
3913                 *pMediaType = LM_MEDIA_TYPE_UTP;
3914                 *pLineSpeed = LM_LINE_SPEED_1000MBPS;
3915                 *pDuplexMode = LM_DUPLEX_MODE_FULL;
3916                 break;
3917
3918         case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS:
3919                 *pMediaType = LM_MEDIA_TYPE_FIBER;
3920                 *pLineSpeed = LM_LINE_SPEED_100MBPS;
3921                 *pDuplexMode = LM_DUPLEX_MODE_HALF;
3922                 break;
3923
3924         case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS_FULL_DUPLEX:
3925                 *pMediaType = LM_MEDIA_TYPE_FIBER;
3926                 *pLineSpeed = LM_LINE_SPEED_100MBPS;
3927                 *pDuplexMode = LM_DUPLEX_MODE_FULL;
3928                 break;
3929
3930         case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS:
3931                 *pMediaType = LM_MEDIA_TYPE_FIBER;
3932                 *pLineSpeed = LM_LINE_SPEED_1000MBPS;
3933                 *pDuplexMode = LM_DUPLEX_MODE_HALF;
3934                 break;
3935
3936         case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX:
3937                 *pMediaType = LM_MEDIA_TYPE_FIBER;
3938                 *pLineSpeed = LM_LINE_SPEED_1000MBPS;
3939                 *pDuplexMode = LM_DUPLEX_MODE_FULL;
3940                 break;
3941
3942         default:
3943                 break;
3944         }                       /* switch */
3945
3946         return LM_STATUS_SUCCESS;
3947 }                               /* LM_TranslateRequestedMediaType */
3948
3949 /******************************************************************************/
3950 /* Description:                                                               */
3951 /*                                                                            */
3952 /* Return:                                                                    */
3953 /*    LM_STATUS_LINK_ACTIVE                                                   */
3954 /*    LM_STATUS_LINK_DOWN                                                     */
3955 /******************************************************************************/
3956 static LM_STATUS LM_InitBcm540xPhy (PLM_DEVICE_BLOCK pDevice)
3957 {
3958         LM_LINE_SPEED CurrentLineSpeed;
3959         LM_DUPLEX_MODE CurrentDuplexMode;
3960         LM_STATUS CurrentLinkStatus;
3961         LM_UINT32 Value32;
3962         LM_UINT32 j;
3963
3964 #if 1                           /* jmb: bugfix -- moved here, out of code that sets initial pwr state */
3965         LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x2);
3966 #endif
3967         if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) {
3968                 LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
3969                 LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
3970
3971                 if (!pDevice->InitDone) {
3972                         Value32 = 0;
3973                 }
3974
3975                 if (!(Value32 & PHY_STATUS_LINK_PASS)) {
3976                         LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x0c20);
3977
3978                         LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
3979                         LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1804);
3980
3981                         LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
3982                         LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1204);
3983
3984                         LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
3985                         LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0132);
3986
3987                         LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
3988                         LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0232);
3989
3990                         LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
3991                         LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
3992
3993                         LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
3994                         for (j = 0; j < 1000; j++) {
3995                                 MM_Wait (10);
3996
3997                                 LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
3998                                 if (Value32 & PHY_STATUS_LINK_PASS) {
3999                                         MM_Wait (40);
4000                                         break;
4001                                 }
4002                         }
4003
4004                         if ((pDevice->PhyId & PHY_ID_REV_MASK) ==
4005                             PHY_BCM5401_B0_REV) {
4006                                 if (!(Value32 & PHY_STATUS_LINK_PASS)
4007                                     && (pDevice->OldLineSpeed ==
4008                                         LM_LINE_SPEED_1000MBPS)) {
4009                                         LM_WritePhy (pDevice, PHY_CTRL_REG,
4010                                                      PHY_CTRL_PHY_RESET);
4011                                         for (j = 0; j < 100; j++) {
4012                                                 MM_Wait (10);
4013
4014                                                 LM_ReadPhy (pDevice,
4015                                                             PHY_CTRL_REG,
4016                                                             &Value32);
4017                                                 if (!
4018                                                     (Value32 &
4019                                                      PHY_CTRL_PHY_RESET)) {
4020                                                         MM_Wait (40);
4021                                                         break;
4022                                                 }
4023                                         }
4024
4025                                         LM_WritePhy (pDevice, BCM5401_AUX_CTRL,
4026                                                      0x0c20);
4027
4028                                         LM_WritePhy (pDevice,
4029                                                      BCM540X_DSP_ADDRESS_REG,
4030                                                      0x0012);
4031                                         LM_WritePhy (pDevice,
4032                                                      BCM540X_DSP_RW_PORT,
4033                                                      0x1804);
4034
4035                                         LM_WritePhy (pDevice,
4036                                                      BCM540X_DSP_ADDRESS_REG,
4037                                                      0x0013);
4038                                         LM_WritePhy (pDevice,
4039                                                      BCM540X_DSP_RW_PORT,
4040                                                      0x1204);
4041
4042                                         LM_WritePhy (pDevice,
4043                                                      BCM540X_DSP_ADDRESS_REG,
4044                                                      0x8006);
4045                                         LM_WritePhy (pDevice,
4046                                                      BCM540X_DSP_RW_PORT,
4047                                                      0x0132);
4048
4049                                         LM_WritePhy (pDevice,
4050                                                      BCM540X_DSP_ADDRESS_REG,
4051                                                      0x8006);
4052                                         LM_WritePhy (pDevice,
4053                                                      BCM540X_DSP_RW_PORT,
4054                                                      0x0232);
4055
4056                                         LM_WritePhy (pDevice,
4057                                                      BCM540X_DSP_ADDRESS_REG,
4058                                                      0x201f);
4059                                         LM_WritePhy (pDevice,
4060                                                      BCM540X_DSP_RW_PORT,
4061                                                      0x0a20);
4062                                 }
4063                         }
4064                 }
4065         } else if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
4066                    pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
4067                 /* Bug: 5701 A0, B0 TX CRC workaround. */
4068                 LM_WritePhy (pDevice, 0x15, 0x0a75);
4069                 LM_WritePhy (pDevice, 0x1c, 0x8c68);
4070                 LM_WritePhy (pDevice, 0x1c, 0x8d68);
4071                 LM_WritePhy (pDevice, 0x1c, 0x8c68);
4072         }
4073
4074         /* Acknowledge interrupts. */
4075         LM_ReadPhy (pDevice, BCM540X_INT_STATUS_REG, &Value32);
4076         LM_ReadPhy (pDevice, BCM540X_INT_STATUS_REG, &Value32);
4077
4078         /* Configure the interrupt mask. */
4079         if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) {
4080                 LM_WritePhy (pDevice, BCM540X_INT_MASK_REG,
4081                              ~BCM540X_INT_LINK_CHANGE);
4082         }
4083
4084         /* Configure PHY led mode. */
4085         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
4086             (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700)) {
4087                 if (pDevice->LedMode == LED_MODE_THREE_LINK) {
4088                         LM_WritePhy (pDevice, BCM540X_EXT_CTRL_REG,
4089                                      BCM540X_EXT_CTRL_LINK3_LED_MODE);
4090                 } else {
4091                         LM_WritePhy (pDevice, BCM540X_EXT_CTRL_REG, 0);
4092                 }
4093         }
4094
4095         CurrentLinkStatus = LM_STATUS_LINK_DOWN;
4096
4097         /* Get current link and duplex mode. */
4098         for (j = 0; j < 100; j++) {
4099                 LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
4100                 LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
4101
4102                 if (Value32 & PHY_STATUS_LINK_PASS) {
4103                         break;
4104                 }
4105                 MM_Wait (40);
4106         }
4107
4108         if (Value32 & PHY_STATUS_LINK_PASS) {
4109
4110                 /* Determine the current line and duplex settings. */
4111                 LM_ReadPhy (pDevice, BCM540X_AUX_STATUS_REG, &Value32);
4112                 for (j = 0; j < 2000; j++) {
4113                         MM_Wait (10);
4114
4115                         LM_ReadPhy (pDevice, BCM540X_AUX_STATUS_REG, &Value32);
4116                         if (Value32) {
4117                                 break;
4118                         }
4119                 }
4120
4121                 switch (Value32 & BCM540X_AUX_SPEED_MASK) {
4122                 case BCM540X_AUX_10BASET_HD:
4123                         CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
4124                         CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
4125                         break;
4126
4127                 case BCM540X_AUX_10BASET_FD:
4128                         CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
4129                         CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
4130                         break;
4131
4132                 case BCM540X_AUX_100BASETX_HD:
4133                         CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
4134                         CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
4135                         break;
4136
4137                 case BCM540X_AUX_100BASETX_FD:
4138                         CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
4139                         CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
4140                         break;
4141
4142                 case BCM540X_AUX_100BASET_HD:
4143                         CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
4144                         CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
4145                         break;
4146
4147                 case BCM540X_AUX_100BASET_FD:
4148                         CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
4149                         CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
4150                         break;
4151
4152                 default:
4153
4154                         CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN;
4155                         CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
4156                         break;
4157                 }
4158
4159                 /* Make sure we are in auto-neg mode. */
4160                 for (j = 0; j < 200; j++) {
4161                         LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
4162                         if (Value32 && Value32 != 0x7fff) {
4163                                 break;
4164                         }
4165
4166                         if (Value32 == 0 && pDevice->RequestedMediaType ==
4167                             LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS) {
4168                                 break;
4169                         }
4170
4171                         MM_Wait (10);
4172                 }
4173
4174                 /* Use the current line settings for "auto" mode. */
4175                 if (pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO
4176                     || pDevice->RequestedMediaType ==
4177                     LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) {
4178                         if (Value32 & PHY_CTRL_AUTO_NEG_ENABLE) {
4179                                 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
4180
4181                                 /* We may be exiting low power mode and the link is in */
4182                                 /* 10mb.  In this case, we need to restart autoneg. */
4183                                 LM_ReadPhy (pDevice, BCM540X_1000BASET_CTRL_REG,
4184                                             &Value32);
4185                                 pDevice->advertising1000 = Value32;
4186                                 /* 5702FE supports 10/100Mb only. */
4187                                 if (T3_ASIC_REV (pDevice->ChipRevId) !=
4188                                     T3_ASIC_REV_5703
4189                                     || pDevice->BondId !=
4190                                     GRC_MISC_BD_ID_5702FE) {
4191                                         if (!
4192                                             (Value32 &
4193                                              (BCM540X_AN_AD_1000BASET_HALF |
4194                                               BCM540X_AN_AD_1000BASET_FULL))) {
4195                                                 CurrentLinkStatus =
4196                                                     LM_STATUS_LINK_SETTING_MISMATCH;
4197                                         }
4198                                 }
4199                         } else {
4200                                 CurrentLinkStatus =
4201                                     LM_STATUS_LINK_SETTING_MISMATCH;
4202                         }
4203                 } else {
4204                         /* Force line settings. */
4205                         /* Use the current setting if it matches the user's requested */
4206                         /* setting. */
4207                         LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
4208                         if ((pDevice->LineSpeed == CurrentLineSpeed) &&
4209                             (pDevice->DuplexMode == CurrentDuplexMode)) {
4210                                 if ((pDevice->DisableAutoNeg &&
4211                                      !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) ||
4212                                     (!pDevice->DisableAutoNeg &&
4213                                      (Value32 & PHY_CTRL_AUTO_NEG_ENABLE))) {
4214                                         CurrentLinkStatus =
4215                                             LM_STATUS_LINK_ACTIVE;
4216                                 } else {
4217                                         CurrentLinkStatus =
4218                                             LM_STATUS_LINK_SETTING_MISMATCH;
4219                                 }
4220                         } else {
4221                                 CurrentLinkStatus =
4222                                     LM_STATUS_LINK_SETTING_MISMATCH;
4223                         }
4224                 }
4225
4226                 /* Save line settings. */
4227                 pDevice->LineSpeed = CurrentLineSpeed;
4228                 pDevice->DuplexMode = CurrentDuplexMode;
4229                 pDevice->MediaType = LM_MEDIA_TYPE_UTP;
4230         }
4231
4232         return CurrentLinkStatus;
4233 }                               /* LM_InitBcm540xPhy */
4234
4235 /******************************************************************************/
4236 /* Description:                                                               */
4237 /*                                                                            */
4238 /* Return:                                                                    */
4239 /******************************************************************************/
4240 LM_STATUS
4241 LM_SetFlowControl (PLM_DEVICE_BLOCK pDevice,
4242                    LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd)
4243 {
4244         LM_FLOW_CONTROL FlowCap;
4245
4246         /* Resolve flow control. */
4247         FlowCap = LM_FLOW_CONTROL_NONE;
4248
4249         /* See Table 28B-3 of 802.3ab-1999 spec. */
4250         if (pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE) {
4251                 if (LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE) {
4252                         if (LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) {
4253                                 if (RemotePhyAd &
4254                                     PHY_LINK_PARTNER_PAUSE_CAPABLE) {
4255                                         FlowCap =
4256                                             LM_FLOW_CONTROL_TRANSMIT_PAUSE |
4257                                             LM_FLOW_CONTROL_RECEIVE_PAUSE;
4258                                 } else if (RemotePhyAd &
4259                                            PHY_LINK_PARTNER_ASYM_PAUSE) {
4260                                         FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE;
4261                                 }
4262                         } else {
4263                                 if (RemotePhyAd &
4264                                     PHY_LINK_PARTNER_PAUSE_CAPABLE) {
4265                                         FlowCap =
4266                                             LM_FLOW_CONTROL_TRANSMIT_PAUSE |
4267                                             LM_FLOW_CONTROL_RECEIVE_PAUSE;
4268                                 }
4269                         }
4270                 } else if (LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) {
4271                         if ((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) &&
4272                             (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)) {
4273                                 FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE;
4274                         }
4275                 }
4276         } else {
4277                 FlowCap = pDevice->FlowControlCap;
4278         }
4279
4280         /* Enable/disable rx PAUSE. */
4281         pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL;
4282         if (FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE &&
4283             (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
4284              pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)) {
4285                 pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
4286                 pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL;
4287
4288         }
4289         REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
4290
4291         /* Enable/disable tx PAUSE. */
4292         pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL;
4293         if (FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE &&
4294             (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
4295              pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)) {
4296                 pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
4297                 pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL;
4298
4299         }
4300         REG_WR (pDevice, MacCtrl.TxMode, pDevice->TxMode);
4301
4302         return LM_STATUS_SUCCESS;
4303 }
4304
4305 #if INCLUDE_TBI_SUPPORT
4306 /******************************************************************************/
4307 /* Description:                                                               */
4308 /*                                                                            */
4309 /* Return:                                                                    */
4310 /******************************************************************************/
4311 STATIC LM_STATUS LM_InitBcm800xPhy (PLM_DEVICE_BLOCK pDevice)
4312 {
4313         LM_UINT32 Value32;
4314         LM_UINT32 j;
4315
4316         Value32 = REG_RD (pDevice, MacCtrl.Status);
4317
4318         /* Reset the SERDES during init and when we have link. */
4319         if (!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED) {
4320                 /* Set PLL lock range. */
4321                 LM_WritePhy (pDevice, 0x16, 0x8007);
4322
4323                 /* Software reset. */
4324                 LM_WritePhy (pDevice, 0x00, 0x8000);
4325
4326                 /* Wait for reset to complete. */
4327                 for (j = 0; j < 500; j++) {
4328                         MM_Wait (10);
4329                 }
4330
4331                 /* Config mode; seletct PMA/Ch 1 regs. */
4332                 LM_WritePhy (pDevice, 0x10, 0x8411);
4333
4334                 /* Enable auto-lock and comdet, select txclk for tx. */
4335                 LM_WritePhy (pDevice, 0x11, 0x0a10);
4336
4337                 LM_WritePhy (pDevice, 0x18, 0x00a0);
4338                 LM_WritePhy (pDevice, 0x16, 0x41ff);
4339
4340                 /* Assert and deassert POR. */
4341                 LM_WritePhy (pDevice, 0x13, 0x0400);
4342                 MM_Wait (40);
4343                 LM_WritePhy (pDevice, 0x13, 0x0000);
4344
4345                 LM_WritePhy (pDevice, 0x11, 0x0a50);
4346                 MM_Wait (40);
4347                 LM_WritePhy (pDevice, 0x11, 0x0a10);
4348
4349                 /* Delay for signal to stabilize. */
4350                 for (j = 0; j < 15000; j++) {
4351                         MM_Wait (10);
4352                 }
4353
4354                 /* Deselect the channel register so we can read the PHY id later. */
4355                 LM_WritePhy (pDevice, 0x10, 0x8011);
4356         }
4357
4358         return LM_STATUS_SUCCESS;
4359 }
4360
4361 /******************************************************************************/
4362 /* Description:                                                               */
4363 /*                                                                            */
4364 /* Return:                                                                    */
4365 /******************************************************************************/
4366 STATIC LM_STATUS LM_SetupFiberPhy (PLM_DEVICE_BLOCK pDevice)
4367 {
4368         LM_STATUS CurrentLinkStatus;
4369         AUTONEG_STATUS AnStatus = 0;
4370         LM_UINT32 Value32;
4371         LM_UINT32 Cnt;
4372         LM_UINT32 j, k;
4373
4374         pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK);
4375
4376         /* Initialize the send_config register. */
4377         REG_WR (pDevice, MacCtrl.TxAutoNeg, 0);
4378
4379         /* Enable TBI and full duplex mode. */
4380         pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI;
4381         REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
4382
4383         /* Initialize the BCM8002 SERDES PHY. */
4384         switch (pDevice->PhyId & PHY_ID_MASK) {
4385         case PHY_BCM8002_PHY_ID:
4386                 LM_InitBcm800xPhy (pDevice);
4387                 break;
4388
4389         default:
4390                 break;
4391         }
4392
4393         /* Enable link change interrupt. */
4394         REG_WR (pDevice, MacCtrl.MacEvent,
4395                 MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
4396
4397         /* Default to link down. */
4398         CurrentLinkStatus = LM_STATUS_LINK_DOWN;
4399
4400         /* Get the link status. */
4401         Value32 = REG_RD (pDevice, MacCtrl.Status);
4402         if (Value32 & MAC_STATUS_PCS_SYNCED) {
4403                 if ((pDevice->RequestedMediaType ==
4404                      LM_REQUESTED_MEDIA_TYPE_AUTO)
4405                     || (pDevice->DisableAutoNeg == FALSE)) {
4406                         /* auto-negotiation mode. */
4407                         /* Initialize the autoneg default capaiblities. */
4408                         AutonegInit (&pDevice->AnInfo);
4409
4410                         /* Set the context pointer to point to the main device structure. */
4411                         pDevice->AnInfo.pContext = pDevice;
4412
4413                         /* Setup flow control advertisement register. */
4414                         Value32 = GetPhyAdFlowCntrlSettings (pDevice);
4415                         if (Value32 & PHY_AN_AD_PAUSE_CAPABLE) {
4416                                 pDevice->AnInfo.mr_adv_sym_pause = 1;
4417                         } else {
4418                                 pDevice->AnInfo.mr_adv_sym_pause = 0;
4419                         }
4420
4421                         if (Value32 & PHY_AN_AD_ASYM_PAUSE) {
4422                                 pDevice->AnInfo.mr_adv_asym_pause = 1;
4423                         } else {
4424                                 pDevice->AnInfo.mr_adv_asym_pause = 0;
4425                         }
4426
4427                         /* Try to autoneg up to six times. */
4428                         if (pDevice->IgnoreTbiLinkChange) {
4429                                 Cnt = 1;
4430                         } else {
4431                                 Cnt = 6;
4432                         }
4433                         for (j = 0; j < Cnt; j++) {
4434                                 REG_WR (pDevice, MacCtrl.TxAutoNeg, 0);
4435
4436                                 Value32 =
4437                                     pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK;
4438                                 REG_WR (pDevice, MacCtrl.Mode, Value32);
4439                                 MM_Wait (20);
4440
4441                                 REG_WR (pDevice, MacCtrl.Mode,
4442                                         pDevice->
4443                                         MacMode | MAC_MODE_SEND_CONFIGS);
4444
4445                                 MM_Wait (20);
4446
4447                                 pDevice->AnInfo.State = AN_STATE_UNKNOWN;
4448                                 pDevice->AnInfo.CurrentTime_us = 0;
4449
4450                                 REG_WR (pDevice, Grc.Timer, 0);
4451                                 for (k = 0;
4452                                      (pDevice->AnInfo.CurrentTime_us < 75000)
4453                                      && (k < 75000); k++) {
4454                                         AnStatus =
4455                                             Autoneg8023z (&pDevice->AnInfo);
4456
4457                                         if ((AnStatus == AUTONEG_STATUS_DONE) ||
4458                                             (AnStatus == AUTONEG_STATUS_FAILED))
4459                                         {
4460                                                 break;
4461                                         }
4462
4463                                         pDevice->AnInfo.CurrentTime_us =
4464                                             REG_RD (pDevice, Grc.Timer);
4465
4466                                 }
4467                                 if ((AnStatus == AUTONEG_STATUS_DONE) ||
4468                                     (AnStatus == AUTONEG_STATUS_FAILED)) {
4469                                         break;
4470                                 }
4471                                 if (j >= 1) {
4472                                         if (!(REG_RD (pDevice, MacCtrl.Status) &
4473                                               MAC_STATUS_PCS_SYNCED)) {
4474                                                 break;
4475                                         }
4476                                 }
4477                         }
4478
4479                         /* Stop sending configs. */
4480                         MM_AnTxIdle (&pDevice->AnInfo);
4481
4482                         /* Resolve flow control settings. */
4483                         if ((AnStatus == AUTONEG_STATUS_DONE) &&
4484                             pDevice->AnInfo.mr_an_complete
4485                             && pDevice->AnInfo.mr_link_ok
4486                             && pDevice->AnInfo.mr_lp_adv_full_duplex) {
4487                                 LM_UINT32 RemotePhyAd;
4488                                 LM_UINT32 LocalPhyAd;
4489
4490                                 LocalPhyAd = 0;
4491                                 if (pDevice->AnInfo.mr_adv_sym_pause) {
4492                                         LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE;
4493                                 }
4494
4495                                 if (pDevice->AnInfo.mr_adv_asym_pause) {
4496                                         LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE;
4497                                 }
4498
4499                                 RemotePhyAd = 0;
4500                                 if (pDevice->AnInfo.mr_lp_adv_sym_pause) {
4501                                         RemotePhyAd |=
4502                                             PHY_LINK_PARTNER_PAUSE_CAPABLE;
4503                                 }
4504
4505                                 if (pDevice->AnInfo.mr_lp_adv_asym_pause) {
4506                                         RemotePhyAd |=
4507                                             PHY_LINK_PARTNER_ASYM_PAUSE;
4508                                 }
4509
4510                                 LM_SetFlowControl (pDevice, LocalPhyAd,
4511                                                    RemotePhyAd);
4512
4513                                 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
4514                         }
4515                         for (j = 0; j < 30; j++) {
4516                                 MM_Wait (20);
4517                                 REG_WR (pDevice, MacCtrl.Status,
4518                                         MAC_STATUS_SYNC_CHANGED |
4519                                         MAC_STATUS_CFG_CHANGED);
4520                                 MM_Wait (20);
4521                                 if ((REG_RD (pDevice, MacCtrl.Status) &
4522                                      (MAC_STATUS_SYNC_CHANGED |
4523                                       MAC_STATUS_CFG_CHANGED)) == 0)
4524                                         break;
4525                         }
4526                         if (pDevice->PollTbiLink) {
4527                                 Value32 = REG_RD (pDevice, MacCtrl.Status);
4528                                 if (Value32 & MAC_STATUS_RECEIVING_CFG) {
4529                                         pDevice->IgnoreTbiLinkChange = TRUE;
4530                                 } else {
4531                                         pDevice->IgnoreTbiLinkChange = FALSE;
4532                                 }
4533                         }
4534                         Value32 = REG_RD (pDevice, MacCtrl.Status);
4535                         if (CurrentLinkStatus == LM_STATUS_LINK_DOWN &&
4536                             (Value32 & MAC_STATUS_PCS_SYNCED) &&
4537                             ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0)) {
4538                                 CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
4539                         }
4540                 } else {
4541                         /* We are forcing line speed. */
4542                         pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
4543                         LM_SetFlowControl (pDevice, 0, 0);
4544
4545                         CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
4546                         REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode |
4547                                 MAC_MODE_SEND_CONFIGS);
4548                 }
4549         }
4550         /* Set the link polarity bit. */
4551         pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
4552         REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
4553
4554         pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
4555             (pDevice->pStatusBlkVirt->
4556              Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
4557
4558         for (j = 0; j < 100; j++) {
4559                 REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
4560                         MAC_STATUS_CFG_CHANGED);
4561                 MM_Wait (5);
4562                 if ((REG_RD (pDevice, MacCtrl.Status) &
4563                      (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
4564                         break;
4565         }
4566
4567         Value32 = REG_RD (pDevice, MacCtrl.Status);
4568         if ((Value32 & MAC_STATUS_PCS_SYNCED) == 0) {
4569                 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
4570                 if (pDevice->DisableAutoNeg == FALSE) {
4571                         REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode |
4572                                 MAC_MODE_SEND_CONFIGS);
4573                         MM_Wait (1);
4574                         REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
4575                 }
4576         }
4577
4578         /* Initialize the current link status. */
4579         if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
4580                 pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS;
4581                 pDevice->DuplexMode = LM_DUPLEX_MODE_FULL;
4582                 REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
4583                         LED_CTRL_1000MBPS_LED_ON);
4584         } else {
4585                 pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN;
4586                 pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN;
4587                 REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
4588                         LED_CTRL_OVERRIDE_TRAFFIC_LED);
4589         }
4590
4591         /* Indicate link status. */
4592         if (pDevice->LinkStatus != CurrentLinkStatus) {
4593                 pDevice->LinkStatus = CurrentLinkStatus;
4594                 MM_IndicateStatus (pDevice, CurrentLinkStatus);
4595         }
4596
4597         return LM_STATUS_SUCCESS;
4598 }
4599 #endif                          /* INCLUDE_TBI_SUPPORT */
4600
4601 /******************************************************************************/
4602 /* Description:                                                               */
4603 /*                                                                            */
4604 /* Return:                                                                    */
4605 /******************************************************************************/
4606 LM_STATUS LM_SetupCopperPhy (PLM_DEVICE_BLOCK pDevice)
4607 {
4608         LM_STATUS CurrentLinkStatus;
4609         LM_UINT32 Value32;
4610
4611         /* Assume there is not link first. */
4612         CurrentLinkStatus = LM_STATUS_LINK_DOWN;
4613
4614         /* Disable phy link change attention. */
4615         REG_WR (pDevice, MacCtrl.MacEvent, 0);
4616
4617         /* Clear link change attention. */
4618         REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
4619                 MAC_STATUS_CFG_CHANGED);
4620
4621         /* Disable auto-polling for the moment. */
4622         pDevice->MiMode = 0xc0000;
4623         REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
4624         MM_Wait (40);
4625
4626         /* Determine the requested line speed and duplex. */
4627         pDevice->OldLineSpeed = pDevice->LineSpeed;
4628         LM_TranslateRequestedMediaType (pDevice->RequestedMediaType,
4629                                         &pDevice->MediaType,
4630                                         &pDevice->LineSpeed,
4631                                         &pDevice->DuplexMode);
4632
4633         /* Initialize the phy chip. */
4634         switch (pDevice->PhyId & PHY_ID_MASK) {
4635         case PHY_BCM5400_PHY_ID:
4636         case PHY_BCM5401_PHY_ID:
4637         case PHY_BCM5411_PHY_ID:
4638         case PHY_BCM5701_PHY_ID:
4639         case PHY_BCM5703_PHY_ID:
4640         case PHY_BCM5704_PHY_ID:
4641                 CurrentLinkStatus = LM_InitBcm540xPhy (pDevice);
4642                 break;
4643
4644         default:
4645                 break;
4646         }
4647
4648         if (CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH) {
4649                 CurrentLinkStatus = LM_STATUS_LINK_DOWN;
4650         }
4651
4652         /* Setup flow control. */
4653         pDevice->FlowControl = LM_FLOW_CONTROL_NONE;
4654         if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
4655                 LM_FLOW_CONTROL FlowCap;        /* Flow control capability. */
4656
4657                 FlowCap = LM_FLOW_CONTROL_NONE;
4658
4659                 if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) {
4660                         if (pDevice->DisableAutoNeg == FALSE ||
4661                             pDevice->RequestedMediaType ==
4662                             LM_REQUESTED_MEDIA_TYPE_AUTO
4663                             || pDevice->RequestedMediaType ==
4664                             LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) {
4665                                 LM_UINT32 ExpectedPhyAd;
4666                                 LM_UINT32 LocalPhyAd;
4667                                 LM_UINT32 RemotePhyAd;
4668
4669                                 LM_ReadPhy (pDevice, PHY_AN_AD_REG,
4670                                             &LocalPhyAd);
4671                                 pDevice->advertising = LocalPhyAd;
4672                                 LocalPhyAd &=
4673                                     (PHY_AN_AD_ASYM_PAUSE |
4674                                      PHY_AN_AD_PAUSE_CAPABLE);
4675
4676                                 ExpectedPhyAd =
4677                                     GetPhyAdFlowCntrlSettings (pDevice);
4678
4679                                 if (LocalPhyAd != ExpectedPhyAd) {
4680                                         CurrentLinkStatus = LM_STATUS_LINK_DOWN;
4681                                 } else {
4682                                         LM_ReadPhy (pDevice,
4683                                                     PHY_LINK_PARTNER_ABILITY_REG,
4684                                                     &RemotePhyAd);
4685
4686                                         LM_SetFlowControl (pDevice, LocalPhyAd,
4687                                                            RemotePhyAd);
4688                                 }
4689                         } else {
4690                                 pDevice->FlowControlCap &=
4691                                     ~LM_FLOW_CONTROL_AUTO_PAUSE;
4692                                 LM_SetFlowControl (pDevice, 0, 0);
4693                         }
4694                 }
4695         }
4696
4697         if (CurrentLinkStatus == LM_STATUS_LINK_DOWN) {
4698                 LM_ForceAutoNeg (pDevice, pDevice->RequestedMediaType);
4699
4700                 /* If we force line speed, we make get link right away. */
4701                 LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
4702                 LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
4703                 if (Value32 & PHY_STATUS_LINK_PASS) {
4704                         CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
4705                 }
4706         }
4707
4708         /* GMII interface. */
4709         pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
4710         if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
4711                 if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS ||
4712                     pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) {
4713                         pDevice->MacMode |= MAC_MODE_PORT_MODE_MII;
4714                 } else {
4715                         pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
4716                 }
4717         } else {
4718                 pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
4719         }
4720
4721         /* Set the MAC to operate in the appropriate duplex mode. */
4722         pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX;
4723         if (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF) {
4724                 pDevice->MacMode |= MAC_MODE_HALF_DUPLEX;
4725         }
4726
4727         /* Set the link polarity bit. */
4728         pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
4729         if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
4730                 if ((pDevice->LedMode == LED_MODE_LINK10) ||
4731                     (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE &&
4732                      pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)) {
4733                         pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
4734                 }
4735         } else {
4736                 if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
4737                         pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
4738                 }
4739
4740                 /* Set LED mode. */
4741                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
4742                     T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
4743                         Value32 = LED_CTRL_PHY_MODE_1;
4744                 } else {
4745                         if (pDevice->LedMode == LED_MODE_OUTPUT) {
4746                                 Value32 = LED_CTRL_PHY_MODE_2;
4747                         } else {
4748                                 Value32 = LED_CTRL_PHY_MODE_1;
4749                         }
4750                 }
4751                 REG_WR (pDevice, MacCtrl.LedCtrl, Value32);
4752         }
4753
4754         REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
4755
4756         /* Enable auto polling. */
4757         if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
4758                 pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE;
4759                 REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
4760         }
4761
4762         /* Enable phy link change attention. */
4763         if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) {
4764                 REG_WR (pDevice, MacCtrl.MacEvent,
4765                         MAC_EVENT_ENABLE_MI_INTERRUPT);
4766         } else {
4767                 REG_WR (pDevice, MacCtrl.MacEvent,
4768                         MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
4769         }
4770         if ((T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) &&
4771             (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) &&
4772             (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
4773             (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) &&
4774               (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) ||
4775              !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))) {
4776                 MM_Wait (120);
4777                 REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
4778                         MAC_STATUS_CFG_CHANGED);
4779                 MEM_WR_OFFSET (pDevice, T3_FIRMWARE_MAILBOX,
4780                                T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE);
4781         }
4782
4783         /* Indicate link status. */
4784         if (pDevice->LinkStatus != CurrentLinkStatus) {
4785                 pDevice->LinkStatus = CurrentLinkStatus;
4786                 MM_IndicateStatus (pDevice, CurrentLinkStatus);
4787         }
4788
4789         return LM_STATUS_SUCCESS;
4790 }                               /* LM_SetupCopperPhy */
4791
4792 /******************************************************************************/
4793 /* Description:                                                               */
4794 /*                                                                            */
4795 /* Return:                                                                    */
4796 /******************************************************************************/
4797 LM_STATUS LM_SetupPhy (PLM_DEVICE_BLOCK pDevice)
4798 {
4799         LM_STATUS LmStatus;
4800         LM_UINT32 Value32;
4801
4802 #if INCLUDE_TBI_SUPPORT
4803         if (pDevice->EnableTbi) {
4804                 LmStatus = LM_SetupFiberPhy (pDevice);
4805         } else
4806 #endif                          /* INCLUDE_TBI_SUPPORT */
4807         {
4808                 LmStatus = LM_SetupCopperPhy (pDevice);
4809         }
4810         if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
4811                 if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
4812                         Value32 = REG_RD (pDevice, PciCfg.PciState);
4813                         REG_WR (pDevice, PciCfg.PciState,
4814                                 Value32 | T3_PCI_STATE_RETRY_SAME_DMA);
4815                 }
4816         }
4817         if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
4818             (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)) {
4819                 REG_WR (pDevice, MacCtrl.TxLengths, 0x26ff);
4820         } else {
4821                 REG_WR (pDevice, MacCtrl.TxLengths, 0x2620);
4822         }
4823
4824         return LmStatus;
4825 }
4826
4827 /******************************************************************************/
4828 /* Description:                                                               */
4829 /*                                                                            */
4830 /* Return:                                                                    */
4831 /******************************************************************************/
4832 LM_VOID
4833 LM_ReadPhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, PLM_UINT32 pData32)
4834 {
4835         LM_UINT32 Value32;
4836         LM_UINT32 j;
4837
4838         if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
4839                 REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode &
4840                         ~MI_MODE_AUTO_POLLING_ENABLE);
4841                 MM_Wait (40);
4842         }
4843
4844         Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
4845             ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) <<
4846              MI_COM_FIRST_PHY_REG_ADDR_BIT) | MI_COM_CMD_READ | MI_COM_START;
4847
4848         REG_WR (pDevice, MacCtrl.MiCom, Value32);
4849
4850         for (j = 0; j < 20; j++) {
4851                 MM_Wait (25);
4852
4853                 Value32 = REG_RD (pDevice, MacCtrl.MiCom);
4854
4855                 if (!(Value32 & MI_COM_BUSY)) {
4856                         MM_Wait (5);
4857                         Value32 = REG_RD (pDevice, MacCtrl.MiCom);
4858                         Value32 &= MI_COM_PHY_DATA_MASK;
4859                         break;
4860                 }
4861         }
4862
4863         if (Value32 & MI_COM_BUSY) {
4864                 Value32 = 0;
4865         }
4866
4867         *pData32 = Value32;
4868
4869         if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
4870                 REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
4871                 MM_Wait (40);
4872         }
4873 }                               /* LM_ReadPhy */
4874
4875 /******************************************************************************/
4876 /* Description:                                                               */
4877 /*                                                                            */
4878 /* Return:                                                                    */
4879 /******************************************************************************/
4880 LM_VOID
4881 LM_WritePhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, LM_UINT32 Data32)
4882 {
4883         LM_UINT32 Value32;
4884         LM_UINT32 j;
4885
4886         if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
4887                 REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode &
4888                         ~MI_MODE_AUTO_POLLING_ENABLE);
4889                 MM_Wait (40);
4890         }
4891
4892         Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
4893             ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) <<
4894              MI_COM_FIRST_PHY_REG_ADDR_BIT) | (Data32 & MI_COM_PHY_DATA_MASK) |
4895             MI_COM_CMD_WRITE | MI_COM_START;
4896
4897         REG_WR (pDevice, MacCtrl.MiCom, Value32);
4898
4899         for (j = 0; j < 20; j++) {
4900                 MM_Wait (25);
4901
4902                 Value32 = REG_RD (pDevice, MacCtrl.MiCom);
4903
4904                 if (!(Value32 & MI_COM_BUSY)) {
4905                         MM_Wait (5);
4906                         break;
4907                 }
4908         }
4909
4910         if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
4911                 REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
4912                 MM_Wait (40);
4913         }
4914 }                               /* LM_WritePhy */
4915
4916 /******************************************************************************/
4917 /* Description:                                                               */
4918 /*                                                                            */
4919 /* Return:                                                                    */
4920 /******************************************************************************/
4921 LM_STATUS LM_SetPowerState (PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel)
4922 {
4923         LM_UINT32 PmeSupport;
4924         LM_UINT32 Value32;
4925         LM_UINT32 PmCtrl;
4926
4927         /* make sureindirect accesses are enabled */
4928         MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG,
4929                           pDevice->MiscHostCtrl);
4930
4931         /* Clear the PME_ASSERT bit and the power state bits.  Also enable */
4932         /* the PME bit. */
4933         MM_ReadConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl);
4934
4935         PmCtrl |= T3_PM_PME_ASSERTED;
4936         PmCtrl &= ~T3_PM_POWER_STATE_MASK;
4937
4938         /* Set the appropriate power state. */
4939         if (PowerLevel == LM_POWER_STATE_D0) {
4940
4941                 /* Bring the card out of low power mode. */
4942                 PmCtrl |= T3_PM_POWER_STATE_D0;
4943                 MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
4944
4945                 REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
4946                 MM_Wait (40);
4947 #if 0                           /* Bugfix by jmb...can't call WritePhy here because pDevice not fully initialized */
4948                 LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x02);
4949 #endif
4950
4951                 return LM_STATUS_SUCCESS;
4952         } else if (PowerLevel == LM_POWER_STATE_D1) {
4953                 PmCtrl |= T3_PM_POWER_STATE_D1;
4954         } else if (PowerLevel == LM_POWER_STATE_D2) {
4955                 PmCtrl |= T3_PM_POWER_STATE_D2;
4956         } else if (PowerLevel == LM_POWER_STATE_D3) {
4957                 PmCtrl |= T3_PM_POWER_STATE_D3;
4958         } else {
4959                 return LM_STATUS_FAILURE;
4960         }
4961         PmCtrl |= T3_PM_PME_ENABLE;
4962
4963         /* Mask out all interrupts so LM_SetupPhy won't be called while we are */
4964         /* setting new line speed. */
4965         Value32 = REG_RD (pDevice, PciCfg.MiscHostCtrl);
4966         REG_WR (pDevice, PciCfg.MiscHostCtrl,
4967                 Value32 | MISC_HOST_CTRL_MASK_PCI_INT);
4968
4969         if (!pDevice->RestoreOnWakeUp) {
4970                 pDevice->RestoreOnWakeUp = TRUE;
4971                 pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg;
4972                 pDevice->WakeUpRequestedMediaType = pDevice->RequestedMediaType;
4973         }
4974
4975         /* Force auto-negotiation to 10 line speed. */
4976         pDevice->DisableAutoNeg = FALSE;
4977         pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
4978         LM_SetupPhy (pDevice);
4979
4980         /* Put the driver in the initial state, and go through the power down */
4981         /* sequence. */
4982         LM_Halt (pDevice);
4983
4984         MM_ReadConfig32 (pDevice, T3_PCI_PM_CAP_REG, &PmeSupport);
4985
4986         if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) {
4987
4988                 /* Enable WOL. */
4989                 LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x5a);
4990                 MM_Wait (40);
4991
4992                 /* Set LED mode. */
4993                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
4994                     T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
4995                         Value32 = LED_CTRL_PHY_MODE_1;
4996                 } else {
4997                         if (pDevice->LedMode == LED_MODE_OUTPUT) {
4998                                 Value32 = LED_CTRL_PHY_MODE_2;
4999                         } else {
5000                                 Value32 = LED_CTRL_PHY_MODE_1;
5001                         }
5002                 }
5003
5004                 Value32 = MAC_MODE_PORT_MODE_MII;
5005                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
5006                         if (pDevice->LedMode == LED_MODE_LINK10 ||
5007                             pDevice->WolSpeed == WOL_SPEED_10MB) {
5008                                 Value32 |= MAC_MODE_LINK_POLARITY;
5009                         }
5010                 } else {
5011                         Value32 |= MAC_MODE_LINK_POLARITY;
5012                 }
5013                 REG_WR (pDevice, MacCtrl.Mode, Value32);
5014                 MM_Wait (40);
5015                 MM_Wait (40);
5016                 MM_Wait (40);
5017
5018                 /* Always enable magic packet wake-up if we have vaux. */
5019                 if ((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) &&
5020                     (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET)) {
5021                         Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE;
5022                 }
5023
5024                 REG_WR (pDevice, MacCtrl.Mode, Value32);
5025
5026                 /* Enable the receiver. */
5027                 REG_WR (pDevice, MacCtrl.RxMode, RX_MODE_ENABLE);
5028         }
5029
5030         /* Disable tx/rx clocks, and seletect an alternate clock. */
5031         if (pDevice->WolSpeed == WOL_SPEED_100MB) {
5032                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
5033                     T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
5034                         Value32 =
5035                             T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
5036                             T3_PCI_SELECT_ALTERNATE_CLOCK;
5037                 } else {
5038                         Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK;
5039                 }
5040                 REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
5041
5042                 MM_Wait (40);
5043
5044                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
5045                     T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
5046                         Value32 =
5047                             T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
5048                             T3_PCI_SELECT_ALTERNATE_CLOCK |
5049                             T3_PCI_44MHZ_CORE_CLOCK;
5050                 } else {
5051                         Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK |
5052                             T3_PCI_44MHZ_CORE_CLOCK;
5053                 }
5054
5055                 REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
5056
5057                 MM_Wait (40);
5058
5059                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
5060                     T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
5061                         Value32 =
5062                             T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
5063                             T3_PCI_44MHZ_CORE_CLOCK;
5064                 } else {
5065                         Value32 = T3_PCI_44MHZ_CORE_CLOCK;
5066                 }
5067
5068                 REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
5069         } else {
5070                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
5071                     T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
5072                         Value32 =
5073                             T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
5074                             T3_PCI_SELECT_ALTERNATE_CLOCK |
5075                             T3_PCI_POWER_DOWN_PCI_PLL133;
5076                 } else {
5077                         Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK |
5078                             T3_PCI_POWER_DOWN_PCI_PLL133;
5079                 }
5080
5081                 REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
5082         }
5083
5084         MM_Wait (40);
5085
5086         if (!pDevice->EepromWp
5087             && (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)) {
5088                 /* Switch adapter to auxilliary power. */
5089                 if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
5090                     T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
5091                         /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
5092                         REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
5093                                 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
5094                                 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
5095                                 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
5096                                 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
5097                                 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
5098                         MM_Wait (40);
5099                 } else {
5100                         /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */
5101                         REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
5102                                 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
5103                                 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
5104                                 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
5105                                 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
5106                                 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
5107                         MM_Wait (40);
5108
5109                         /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */
5110                         REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
5111                                 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
5112                                 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
5113                                 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
5114                                 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
5115                                 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
5116                                 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
5117                         MM_Wait (40);
5118
5119                         /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
5120                         REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
5121                                 GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
5122                                 GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
5123                                 GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
5124                                 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
5125                                 GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
5126                         MM_Wait (40);
5127                 }
5128         }
5129
5130         /* Set the phy to low power mode. */
5131         /* Put the the hardware in low power mode. */
5132         MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
5133
5134         return LM_STATUS_SUCCESS;
5135 }                               /* LM_SetPowerState */
5136
5137 /******************************************************************************/
5138 /* Description:                                                               */
5139 /*                                                                            */
5140 /* Return:                                                                    */
5141 /******************************************************************************/
5142 static LM_UINT32 GetPhyAdFlowCntrlSettings (PLM_DEVICE_BLOCK pDevice)
5143 {
5144         LM_UINT32 Value32;
5145
5146         Value32 = 0;
5147
5148         /* Auto negotiation flow control only when autonegotiation is enabled. */
5149         if (pDevice->DisableAutoNeg == FALSE ||
5150             pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO ||
5151             pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) {
5152                 /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */
5153                 if ((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) ||
5154                     ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)
5155                      && (pDevice->
5156                          FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))) {
5157                         Value32 |= PHY_AN_AD_PAUSE_CAPABLE;
5158                 } else if (pDevice->
5159                            FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE) {
5160                         Value32 |= PHY_AN_AD_ASYM_PAUSE;
5161                 } else if (pDevice->
5162                            FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) {
5163                         Value32 |=
5164                             PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE;
5165                 }
5166         }
5167
5168         return Value32;
5169 }
5170
5171 /******************************************************************************/
5172 /* Description:                                                               */
5173 /*                                                                            */
5174 /* Return:                                                                    */
5175 /*    LM_STATUS_FAILURE                                                       */
5176 /*    LM_STATUS_SUCCESS                                                       */
5177 /*                                                                            */
5178 /******************************************************************************/
5179 static LM_STATUS
5180 LM_ForceAutoNegBcm540xPhy (PLM_DEVICE_BLOCK pDevice,
5181                            LM_REQUESTED_MEDIA_TYPE RequestedMediaType)
5182 {
5183         LM_MEDIA_TYPE MediaType;
5184         LM_LINE_SPEED LineSpeed;
5185         LM_DUPLEX_MODE DuplexMode;
5186         LM_UINT32 NewPhyCtrl;
5187         LM_UINT32 Value32;
5188         LM_UINT32 Cnt;
5189
5190         /* Get the interface type, line speed, and duplex mode. */
5191         LM_TranslateRequestedMediaType (RequestedMediaType, &MediaType,
5192                                         &LineSpeed, &DuplexMode);
5193
5194         if (pDevice->RestoreOnWakeUp) {
5195                 LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0);
5196                 pDevice->advertising1000 = 0;
5197                 Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF;
5198                 if (pDevice->WolSpeed == WOL_SPEED_100MB) {
5199                         Value32 |=
5200                             PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
5201                 }
5202                 Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
5203                 Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
5204                 LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
5205                 pDevice->advertising = Value32;
5206         }
5207         /* Setup the auto-negotiation advertisement register. */
5208         else if (LineSpeed == LM_LINE_SPEED_UNKNOWN) {
5209                 /* Setup the 10/100 Mbps auto-negotiation advertisement register. */
5210                 Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
5211                     PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL |
5212                     PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
5213                 Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
5214
5215                 LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
5216                 pDevice->advertising = Value32;
5217
5218                 /* Advertise 1000Mbps */
5219                 Value32 =
5220                     BCM540X_AN_AD_1000BASET_HALF | BCM540X_AN_AD_1000BASET_FULL;
5221
5222 #if INCLUDE_5701_AX_FIX
5223                 /* Bug: workaround for CRC error in gigabit mode when we are in */
5224                 /* slave mode.  This will force the PHY to operate in */
5225                 /* master mode. */
5226                 if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
5227                     pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
5228                         Value32 |= BCM540X_CONFIG_AS_MASTER |
5229                             BCM540X_ENABLE_CONFIG_AS_MASTER;
5230                 }
5231 #endif
5232
5233                 LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
5234                 pDevice->advertising1000 = Value32;
5235         } else {
5236                 if (LineSpeed == LM_LINE_SPEED_1000MBPS) {
5237                         Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
5238                         Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
5239
5240                         LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
5241                         pDevice->advertising = Value32;
5242
5243                         if (DuplexMode != LM_DUPLEX_MODE_FULL) {
5244                                 Value32 = BCM540X_AN_AD_1000BASET_HALF;
5245                         } else {
5246                                 Value32 = BCM540X_AN_AD_1000BASET_FULL;
5247                         }
5248
5249                         LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG,
5250                                      Value32);
5251                         pDevice->advertising1000 = Value32;
5252                 } else if (LineSpeed == LM_LINE_SPEED_100MBPS) {
5253                         LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0);
5254                         pDevice->advertising1000 = 0;
5255
5256                         if (DuplexMode != LM_DUPLEX_MODE_FULL) {
5257                                 Value32 = PHY_AN_AD_100BASETX_HALF;
5258                         } else {
5259                                 Value32 = PHY_AN_AD_100BASETX_FULL;
5260                         }
5261
5262                         Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
5263                         Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
5264
5265                         LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
5266                         pDevice->advertising = Value32;
5267                 } else if (LineSpeed == LM_LINE_SPEED_10MBPS) {
5268                         LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0);
5269                         pDevice->advertising1000 = 0;
5270
5271                         if (DuplexMode != LM_DUPLEX_MODE_FULL) {
5272                                 Value32 = PHY_AN_AD_10BASET_HALF;
5273                         } else {
5274                                 Value32 = PHY_AN_AD_10BASET_FULL;
5275                         }
5276
5277                         Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
5278                         Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
5279
5280                         LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
5281                         pDevice->advertising = Value32;
5282                 }
5283         }
5284
5285         /* Force line speed if auto-negotiation is disabled. */
5286         if (pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN) {
5287                 /* This code path is executed only when there is link. */
5288                 pDevice->MediaType = MediaType;
5289                 pDevice->LineSpeed = LineSpeed;
5290                 pDevice->DuplexMode = DuplexMode;
5291
5292                 /* Force line seepd. */
5293                 NewPhyCtrl = 0;
5294                 switch (LineSpeed) {
5295                 case LM_LINE_SPEED_10MBPS:
5296                         NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS;
5297                         break;
5298                 case LM_LINE_SPEED_100MBPS:
5299                         NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS;
5300                         break;
5301                 case LM_LINE_SPEED_1000MBPS:
5302                         NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
5303                         break;
5304                 default:
5305                         NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
5306                         break;
5307                 }
5308
5309                 if (DuplexMode == LM_DUPLEX_MODE_FULL) {
5310                         NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE;
5311                 }
5312
5313                 /* Don't do anything if the PHY_CTRL is already what we wanted. */
5314                 LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
5315                 if (Value32 != NewPhyCtrl) {
5316                         /* Temporary bring the link down before forcing line speed. */
5317                         LM_WritePhy (pDevice, PHY_CTRL_REG,
5318                                      PHY_CTRL_LOOPBACK_MODE);
5319
5320                         /* Wait for link to go down. */
5321                         for (Cnt = 0; Cnt < 15000; Cnt++) {
5322                                 MM_Wait (10);
5323
5324                                 LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
5325                                 LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
5326
5327                                 if (!(Value32 & PHY_STATUS_LINK_PASS)) {
5328                                         MM_Wait (40);
5329                                         break;
5330                                 }
5331                         }
5332
5333                         LM_WritePhy (pDevice, PHY_CTRL_REG, NewPhyCtrl);
5334                         MM_Wait (40);
5335                 }
5336         } else {
5337                 LM_WritePhy (pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
5338                              PHY_CTRL_RESTART_AUTO_NEG);
5339         }
5340
5341         return LM_STATUS_SUCCESS;
5342 }                               /* LM_ForceAutoNegBcm540xPhy */
5343
5344 /******************************************************************************/
5345 /* Description:                                                               */
5346 /*                                                                            */
5347 /* Return:                                                                    */
5348 /******************************************************************************/
5349 static LM_STATUS
5350 LM_ForceAutoNeg (PLM_DEVICE_BLOCK pDevice,
5351                  LM_REQUESTED_MEDIA_TYPE RequestedMediaType)
5352 {
5353         LM_STATUS LmStatus;
5354
5355         /* Initialize the phy chip. */
5356         switch (pDevice->PhyId & PHY_ID_MASK) {
5357         case PHY_BCM5400_PHY_ID:
5358         case PHY_BCM5401_PHY_ID:
5359         case PHY_BCM5411_PHY_ID:
5360         case PHY_BCM5701_PHY_ID:
5361         case PHY_BCM5703_PHY_ID:
5362         case PHY_BCM5704_PHY_ID:
5363                 LmStatus =
5364                     LM_ForceAutoNegBcm540xPhy (pDevice, RequestedMediaType);
5365                 break;
5366
5367         default:
5368                 LmStatus = LM_STATUS_FAILURE;
5369                 break;
5370         }
5371
5372         return LmStatus;
5373 }                               /* LM_ForceAutoNeg */
5374
5375 /******************************************************************************/
5376 /* Description:                                                               */
5377 /*                                                                            */
5378 /* Return:                                                                    */
5379 /******************************************************************************/
5380 LM_STATUS LM_LoadFirmware (PLM_DEVICE_BLOCK pDevice,
5381                            PT3_FWIMG_INFO pFwImg,
5382                            LM_UINT32 LoadCpu, LM_UINT32 StartCpu)
5383 {
5384         LM_UINT32 i;
5385         LM_UINT32 address;
5386
5387         if (LoadCpu & T3_RX_CPU_ID) {
5388                 if (LM_HaltCpu (pDevice, T3_RX_CPU_ID) != LM_STATUS_SUCCESS) {
5389                         return LM_STATUS_FAILURE;
5390                 }
5391
5392                 /* First of all clear scrach pad memory */
5393                 for (i = 0; i < T3_RX_CPU_SPAD_SIZE; i += 4) {
5394                         LM_RegWrInd (pDevice, T3_RX_CPU_SPAD_ADDR + i, 0);
5395                 }
5396
5397                 /* Copy code first */
5398                 address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
5399                 for (i = 0; i <= pFwImg->Text.Length; i += 4) {
5400                         LM_RegWrInd (pDevice, address + i,
5401                                      ((LM_UINT32 *) pFwImg->Text.Buffer)[i /
5402                                                                          4]);
5403                 }
5404
5405                 address =
5406                     T3_RX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
5407                 for (i = 0; i <= pFwImg->ROnlyData.Length; i += 4) {
5408                         LM_RegWrInd (pDevice, address + i,
5409                                      ((LM_UINT32 *) pFwImg->ROnlyData.
5410                                       Buffer)[i / 4]);
5411                 }
5412
5413                 address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
5414                 for (i = 0; i <= pFwImg->Data.Length; i += 4) {
5415                         LM_RegWrInd (pDevice, address + i,
5416                                      ((LM_UINT32 *) pFwImg->Data.Buffer)[i /
5417                                                                          4]);
5418                 }
5419         }
5420
5421         if (LoadCpu & T3_TX_CPU_ID) {
5422                 if (LM_HaltCpu (pDevice, T3_TX_CPU_ID) != LM_STATUS_SUCCESS) {
5423                         return LM_STATUS_FAILURE;
5424                 }
5425
5426                 /* First of all clear scrach pad memory */
5427                 for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i += 4) {
5428                         LM_RegWrInd (pDevice, T3_TX_CPU_SPAD_ADDR + i, 0);
5429                 }
5430
5431                 /* Copy code first */
5432                 address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
5433                 for (i = 0; i <= pFwImg->Text.Length; i += 4) {
5434                         LM_RegWrInd (pDevice, address + i,
5435                                      ((LM_UINT32 *) pFwImg->Text.Buffer)[i /
5436                                                                          4]);
5437                 }
5438
5439                 address =
5440                     T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
5441                 for (i = 0; i <= pFwImg->ROnlyData.Length; i += 4) {
5442                         LM_RegWrInd (pDevice, address + i,
5443                                      ((LM_UINT32 *) pFwImg->ROnlyData.
5444                                       Buffer)[i / 4]);
5445                 }
5446
5447                 address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
5448                 for (i = 0; i <= pFwImg->Data.Length; i += 4) {
5449                         LM_RegWrInd (pDevice, address + i,
5450                                      ((LM_UINT32 *) pFwImg->Data.Buffer)[i /
5451                                                                          4]);
5452                 }
5453         }
5454
5455         if (StartCpu & T3_RX_CPU_ID) {
5456                 /* Start Rx CPU */
5457                 REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
5458                 REG_WR (pDevice, rxCpu.reg.PC, pFwImg->StartAddress);
5459                 for (i = 0; i < 5; i++) {
5460                         if (pFwImg->StartAddress ==
5461                             REG_RD (pDevice, rxCpu.reg.PC))
5462                                 break;
5463
5464                         REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
5465                         REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT);
5466                         REG_WR (pDevice, rxCpu.reg.PC, pFwImg->StartAddress);
5467                         MM_Wait (1000);
5468                 }
5469
5470                 REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
5471                 REG_WR (pDevice, rxCpu.reg.mode, 0);
5472         }
5473
5474         if (StartCpu & T3_TX_CPU_ID) {
5475                 /* Start Tx CPU */
5476                 REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
5477                 REG_WR (pDevice, txCpu.reg.PC, pFwImg->StartAddress);
5478                 for (i = 0; i < 5; i++) {
5479                         if (pFwImg->StartAddress ==
5480                             REG_RD (pDevice, txCpu.reg.PC))
5481                                 break;
5482
5483                         REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
5484                         REG_WR (pDevice, txCpu.reg.mode, CPU_MODE_HALT);
5485                         REG_WR (pDevice, txCpu.reg.PC, pFwImg->StartAddress);
5486                         MM_Wait (1000);
5487                 }
5488
5489                 REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
5490                 REG_WR (pDevice, txCpu.reg.mode, 0);
5491         }
5492
5493         return LM_STATUS_SUCCESS;
5494 }
5495
5496 STATIC LM_STATUS LM_HaltCpu (PLM_DEVICE_BLOCK pDevice, LM_UINT32 cpu_number)
5497 {
5498         LM_UINT32 i;
5499
5500         if (cpu_number == T3_RX_CPU_ID) {
5501                 for (i = 0; i < 10000; i++) {
5502                         REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
5503                         REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT);
5504
5505                         if (REG_RD (pDevice, rxCpu.reg.mode) & CPU_MODE_HALT)
5506                                 break;
5507                 }
5508
5509                 REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
5510                 REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT);
5511                 MM_Wait (10);
5512         } else {
5513                 for (i = 0; i < 10000; i++) {
5514                         REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
5515                         REG_WR (pDevice, txCpu.reg.mode, CPU_MODE_HALT);
5516
5517                         if (REG_RD (pDevice, txCpu.reg.mode) & CPU_MODE_HALT)
5518                                 break;
5519                 }
5520         }
5521
5522         return ((i == 10000) ? LM_STATUS_FAILURE : LM_STATUS_SUCCESS);
5523 }
5524
5525 int LM_BlinkLED (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec)
5526 {
5527         LM_UINT32 Oldcfg;
5528         int j;
5529         int ret = 0;
5530
5531         if (BlinkDurationSec == 0) {
5532                 return 0;
5533         }
5534         if (BlinkDurationSec > 120) {
5535                 BlinkDurationSec = 120;
5536         }
5537
5538         Oldcfg = REG_RD (pDevice, MacCtrl.LedCtrl);
5539         for (j = 0; j < BlinkDurationSec * 2; j++) {
5540                 if (j % 2) {
5541                         /* Turn on the LEDs. */
5542                         REG_WR (pDevice, MacCtrl.LedCtrl,
5543                                 LED_CTRL_OVERRIDE_LINK_LED |
5544                                 LED_CTRL_1000MBPS_LED_ON |
5545                                 LED_CTRL_100MBPS_LED_ON |
5546                                 LED_CTRL_10MBPS_LED_ON |
5547                                 LED_CTRL_OVERRIDE_TRAFFIC_LED |
5548                                 LED_CTRL_BLINK_TRAFFIC_LED |
5549                                 LED_CTRL_TRAFFIC_LED);
5550                 } else {
5551                         /* Turn off the LEDs. */
5552                         REG_WR (pDevice, MacCtrl.LedCtrl,
5553                                 LED_CTRL_OVERRIDE_LINK_LED |
5554                                 LED_CTRL_OVERRIDE_TRAFFIC_LED);
5555                 }
5556
5557 #ifndef EMBEDDED
5558                 current->state = TASK_INTERRUPTIBLE;
5559                 if (schedule_timeout (HZ / 2) != 0) {
5560                         ret = -EINTR;
5561                         break;
5562                 }
5563 #else
5564                 udelay (100000);        /* 1s sleep */
5565 #endif
5566         }
5567         REG_WR (pDevice, MacCtrl.LedCtrl, Oldcfg);
5568         return ret;
5569 }
5570
5571 int t3_do_dma (PLM_DEVICE_BLOCK pDevice,
5572                LM_PHYSICAL_ADDRESS host_addr_phy, int length, int dma_read)
5573 {
5574         T3_DMA_DESC dma_desc;
5575         int i;
5576         LM_UINT32 dma_desc_addr;
5577         LM_UINT32 value32;
5578
5579         REG_WR (pDevice, BufMgr.Mode, 0);
5580         REG_WR (pDevice, Ftq.Reset, 0);
5581
5582         dma_desc.host_addr.High = host_addr_phy.High;
5583         dma_desc.host_addr.Low = host_addr_phy.Low;
5584         dma_desc.nic_mbuf = 0x2100;
5585         dma_desc.len = length;
5586         dma_desc.flags = 0x00000004;    /* Generate Rx-CPU event */
5587
5588         if (dma_read) {
5589                 dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) |
5590                     T3_QID_DMA_HIGH_PRI_READ;
5591                 REG_WR (pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE);
5592         } else {
5593                 dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) |
5594                     T3_QID_DMA_HIGH_PRI_WRITE;
5595                 REG_WR (pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE);
5596         }
5597
5598         dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR;
5599
5600         /* Writing this DMA descriptor to DMA memory */
5601         for (i = 0; i < sizeof (T3_DMA_DESC); i += 4) {
5602                 value32 = *((PLM_UINT32) (((PLM_UINT8) & dma_desc) + i));
5603                 MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG,
5604                                   dma_desc_addr + i);
5605                 MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG,
5606                                   cpu_to_le32 (value32));
5607         }
5608         MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0);
5609
5610         if (dma_read)
5611                 REG_WR (pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue,
5612                         dma_desc_addr);
5613         else
5614                 REG_WR (pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue,
5615                         dma_desc_addr);
5616
5617         for (i = 0; i < 40; i++) {
5618                 if (dma_read)
5619                         value32 =
5620                             REG_RD (pDevice,
5621                                     Ftq.RcvBdCompFtqFifoEnqueueDequeue);
5622                 else
5623                         value32 =
5624                             REG_RD (pDevice,
5625                                     Ftq.RcvDataCompFtqFifoEnqueueDequeue);
5626
5627                 if ((value32 & 0xffff) == dma_desc_addr)
5628                         break;
5629
5630                 MM_Wait (10);
5631         }
5632
5633         return LM_STATUS_SUCCESS;
5634 }
5635
5636 STATIC LM_STATUS
5637 LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
5638             LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize)
5639 {
5640         int j;
5641         LM_UINT32 *ptr;
5642         int dma_success = 0;
5643
5644         if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
5645             T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
5646                 return LM_STATUS_SUCCESS;
5647         }
5648         while (!dma_success) {
5649                 /* Fill data with incremental patterns */
5650                 ptr = (LM_UINT32 *) pBufferVirt;
5651                 for (j = 0; j < BufferSize / 4; j++)
5652                         *ptr++ = j;
5653
5654                 if (t3_do_dma (pDevice, BufferPhy, BufferSize, 1) ==
5655                     LM_STATUS_FAILURE) {
5656                         return LM_STATUS_FAILURE;
5657                 }
5658
5659                 MM_Wait (40);
5660                 ptr = (LM_UINT32 *) pBufferVirt;
5661                 /* Fill data with zero */
5662                 for (j = 0; j < BufferSize / 4; j++)
5663                         *ptr++ = 0;
5664
5665                 if (t3_do_dma (pDevice, BufferPhy, BufferSize, 0) ==
5666                     LM_STATUS_FAILURE) {
5667                         return LM_STATUS_FAILURE;
5668                 }
5669
5670                 MM_Wait (40);
5671                 /* Check for data */
5672                 ptr = (LM_UINT32 *) pBufferVirt;
5673                 for (j = 0; j < BufferSize / 4; j++) {
5674                         if (*ptr++ != j) {
5675                                 if ((pDevice->
5676                                      DmaReadWriteCtrl &
5677                                      DMA_CTRL_WRITE_BOUNDARY_MASK)
5678                                     == DMA_CTRL_WRITE_BOUNDARY_DISABLE) {
5679                                         pDevice->DmaReadWriteCtrl =
5680                                             (pDevice->
5681                                              DmaReadWriteCtrl &
5682                                              ~DMA_CTRL_WRITE_BOUNDARY_MASK) |
5683                                             DMA_CTRL_WRITE_BOUNDARY_16;
5684                                         REG_WR (pDevice,
5685                                                 PciCfg.DmaReadWriteCtrl,
5686                                                 pDevice->DmaReadWriteCtrl);
5687                                         break;
5688                                 } else {
5689                                         return LM_STATUS_FAILURE;
5690                                 }
5691                         }
5692                 }
5693                 if (j == (BufferSize / 4))
5694                         dma_success = 1;
5695         }
5696         return LM_STATUS_SUCCESS;
5697 }
5698
5699 #endif