1 // SPDX-License-Identifier: GPL-2.0+
3 * CPSW MDIO generic driver for TI AMxx/K2x/EMAC devices.
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
14 #include <linux/bitops.h>
15 #include <linux/delay.h>
17 struct cpsw_mdio_regs {
20 #define CONTROL_IDLE BIT(31)
21 #define CONTROL_ENABLE BIT(30)
22 #define CONTROL_FAULT BIT(19)
23 #define CONTROL_FAULT_ENABLE BIT(18)
24 #define CONTROL_DIV_MASK GENMASK(15, 0)
26 #define MDIO_MAN_MDCLK_O BIT(2)
27 #define MDIO_MAN_OE BIT(1)
28 #define MDIO_MAN_PIN BIT(0)
29 #define MDIO_MANUALMODE BIT(31)
47 #define USERACCESS_GO BIT(31)
48 #define USERACCESS_WRITE BIT(30)
49 #define USERACCESS_ACK BIT(29)
50 #define USERACCESS_READ (0)
51 #define USERACCESS_PHY_REG_SHIFT (21)
52 #define USERACCESS_PHY_ADDR_SHIFT (16)
53 #define USERACCESS_DATA GENMASK(15, 0)
57 #define CPSW_MDIO_DIV_DEF 0xff
58 #define PHY_REG_MASK 0x1f
59 #define PHY_ID_MASK 0x1f
61 #define MDIO_BITRANGE 0x8000
62 #define C22_READ_PATTERN 0x6
63 #define C22_WRITE_PATTERN 0x5
64 #define C22_BITRANGE 0x8
65 #define PHY_BITRANGE 0x10
66 #define PHY_DATA_BITRANGE 0x8000
69 * This timeout definition is a worst-case ultra defensive measure against
70 * unexpected controller lock ups. Ideally, we should never ever hit this
71 * scenario in practice.
73 #define CPSW_MDIO_TIMEOUT 100 /* msecs */
75 enum cpsw_mdio_manual {
82 struct cpsw_mdio_regs *regs;
87 static void cpsw_mdio_disable(struct cpsw_mdio *mdio)
90 /* Disable MDIO state machine */
91 reg = readl(&mdio->regs->control);
92 reg &= ~CONTROL_ENABLE;
94 writel(reg, &mdio->regs->control);
97 static void cpsw_mdio_enable_manual_mode(struct cpsw_mdio *mdio)
101 /* set manual mode */
102 reg = readl(&mdio->regs->poll);
103 reg |= MDIO_MANUALMODE;
105 writel(reg, &mdio->regs->poll);
108 static void cpsw_mdio_sw_set_bit(struct cpsw_mdio *mdio,
109 enum cpsw_mdio_manual bit)
113 reg = readl(&mdio->regs->manualif);
118 writel(reg, &mdio->regs->manualif);
122 writel(reg, &mdio->regs->manualif);
125 reg |= MDIO_MAN_MDCLK_O;
126 writel(reg, &mdio->regs->manualif);
133 static void cpsw_mdio_sw_clr_bit(struct cpsw_mdio *mdio,
134 enum cpsw_mdio_manual bit)
138 reg = readl(&mdio->regs->manualif);
143 writel(reg, &mdio->regs->manualif);
146 reg &= ~MDIO_MAN_PIN;
147 writel(reg, &mdio->regs->manualif);
150 reg = readl(&mdio->regs->manualif);
151 reg &= ~MDIO_MAN_MDCLK_O;
152 writel(reg, &mdio->regs->manualif);
159 static int cpsw_mdio_test_man_bit(struct cpsw_mdio *mdio,
160 enum cpsw_mdio_manual bit)
164 reg = readl(&mdio->regs->manualif);
165 return test_bit(bit, ®);
168 static void cpsw_mdio_toggle_man_bit(struct cpsw_mdio *mdio,
169 enum cpsw_mdio_manual bit)
171 cpsw_mdio_sw_clr_bit(mdio, bit);
172 cpsw_mdio_sw_set_bit(mdio, bit);
175 static void cpsw_mdio_man_send_pattern(struct cpsw_mdio *mdio,
176 u32 bitrange, u32 val)
180 for (i = bitrange; i; i = i >> 1) {
182 cpsw_mdio_sw_set_bit(mdio, MDIO_PIN);
184 cpsw_mdio_sw_clr_bit(mdio, MDIO_PIN);
186 cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
190 static void cpsw_mdio_sw_preamble(struct cpsw_mdio *mdio)
194 cpsw_mdio_sw_clr_bit(mdio, MDIO_OE);
196 cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
197 cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
198 cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
199 cpsw_mdio_sw_set_bit(mdio, MDIO_MDCLK);
201 for (i = 0; i < 32; i++) {
202 cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
203 cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
204 cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
205 cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
209 static int cpsw_mdio_sw_read(struct mii_dev *bus, int phy_id,
210 int dev_addr, int phy_reg)
212 struct cpsw_mdio *mdio = bus->priv;
216 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
219 cpsw_mdio_disable(mdio);
220 cpsw_mdio_enable_manual_mode(mdio);
221 cpsw_mdio_sw_preamble(mdio);
223 cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
224 cpsw_mdio_sw_set_bit(mdio, MDIO_OE);
226 /* Issue clause 22 MII read function {0,1,1,0} */
227 cpsw_mdio_man_send_pattern(mdio, C22_BITRANGE, C22_READ_PATTERN);
229 /* Send the device number MSB first */
230 cpsw_mdio_man_send_pattern(mdio, PHY_BITRANGE, phy_id);
232 /* Send the register number MSB first */
233 cpsw_mdio_man_send_pattern(mdio, PHY_BITRANGE, phy_reg);
235 /* Send turn around cycles */
236 cpsw_mdio_sw_clr_bit(mdio, MDIO_OE);
238 cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
240 ack = cpsw_mdio_test_man_bit(mdio, MDIO_PIN);
241 cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
245 for (i = MDIO_BITRANGE; i; i = i >> 1) {
246 if (cpsw_mdio_test_man_bit(mdio, MDIO_PIN))
249 cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
252 for (i = MDIO_BITRANGE; i; i = i >> 1)
253 cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
258 cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
259 cpsw_mdio_sw_set_bit(mdio, MDIO_MDCLK);
260 cpsw_mdio_sw_set_bit(mdio, MDIO_MDCLK);
261 cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
266 static int cpsw_mdio_sw_write(struct mii_dev *bus, int phy_id,
267 int dev_addr, int phy_reg, u16 phy_data)
269 struct cpsw_mdio *mdio = bus->priv;
271 if ((phy_reg & ~PHY_REG_MASK) || (phy_id & ~PHY_ID_MASK))
274 cpsw_mdio_disable(mdio);
275 cpsw_mdio_enable_manual_mode(mdio);
276 cpsw_mdio_sw_preamble(mdio);
278 cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
279 cpsw_mdio_sw_set_bit(mdio, MDIO_OE);
281 /* Issue clause 22 MII write function {0,1,0,1} */
282 cpsw_mdio_man_send_pattern(mdio, C22_BITRANGE, C22_WRITE_PATTERN);
284 /* Send the device number MSB first */
285 cpsw_mdio_man_send_pattern(mdio, PHY_BITRANGE, phy_id);
287 /* Send the register number MSB first */
288 cpsw_mdio_man_send_pattern(mdio, PHY_BITRANGE, phy_reg);
290 /* set turn-around cycles */
291 cpsw_mdio_sw_set_bit(mdio, MDIO_PIN);
292 cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
293 cpsw_mdio_sw_clr_bit(mdio, MDIO_PIN);
294 cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
296 /* Send Register data MSB first */
297 cpsw_mdio_man_send_pattern(mdio, PHY_DATA_BITRANGE, phy_data);
298 cpsw_mdio_sw_clr_bit(mdio, MDIO_OE);
300 cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
301 cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
302 cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
303 cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
308 /* wait until hardware is ready for another user access */
309 static int cpsw_mdio_wait_for_user_access(struct cpsw_mdio *mdio)
311 return wait_for_bit_le32(&mdio->regs->user[0].access,
312 USERACCESS_GO, false,
313 CPSW_MDIO_TIMEOUT, false);
316 static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
317 int dev_addr, int phy_reg)
319 struct cpsw_mdio *mdio = bus->priv;
323 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
326 ret = cpsw_mdio_wait_for_user_access(mdio);
329 reg = (USERACCESS_GO | USERACCESS_READ |
330 (phy_reg << USERACCESS_PHY_REG_SHIFT) |
331 (phy_id << USERACCESS_PHY_ADDR_SHIFT));
332 writel(reg, &mdio->regs->user[0].access);
333 ret = cpsw_mdio_wait_for_user_access(mdio);
337 reg = readl(&mdio->regs->user[0].access);
338 data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
342 static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
343 int phy_reg, u16 data)
345 struct cpsw_mdio *mdio = bus->priv;
349 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
352 ret = cpsw_mdio_wait_for_user_access(mdio);
355 reg = (USERACCESS_GO | USERACCESS_WRITE |
356 (phy_reg << USERACCESS_PHY_REG_SHIFT) |
357 (phy_id << USERACCESS_PHY_ADDR_SHIFT) |
358 (data & USERACCESS_DATA));
359 writel(reg, &mdio->regs->user[0].access);
361 return cpsw_mdio_wait_for_user_access(mdio);
364 u32 cpsw_mdio_get_alive(struct mii_dev *bus)
366 struct cpsw_mdio *mdio = bus->priv;
369 val = readl(&mdio->regs->alive);
370 return val & GENMASK(7, 0);
373 struct mii_dev *cpsw_mdio_init(const char *name, phys_addr_t mdio_base,
374 u32 bus_freq, int fck_freq, bool manual_mode)
376 struct cpsw_mdio *cpsw_mdio;
379 cpsw_mdio = calloc(1, sizeof(*cpsw_mdio));
381 debug("failed to alloc cpsw_mdio\n");
385 cpsw_mdio->bus = mdio_alloc();
386 if (!cpsw_mdio->bus) {
387 debug("failed to alloc mii bus\n");
392 cpsw_mdio->regs = (struct cpsw_mdio_regs *)(uintptr_t)mdio_base;
394 if (!bus_freq || !fck_freq)
395 cpsw_mdio->div = CPSW_MDIO_DIV_DEF;
397 cpsw_mdio->div = (fck_freq / bus_freq) - 1;
398 cpsw_mdio->div &= CONTROL_DIV_MASK;
400 /* set enable and clock divider */
401 writel(cpsw_mdio->div | CONTROL_ENABLE | CONTROL_FAULT |
402 CONTROL_FAULT_ENABLE, &cpsw_mdio->regs->control);
403 wait_for_bit_le32(&cpsw_mdio->regs->control,
404 CONTROL_IDLE, false, CPSW_MDIO_TIMEOUT, true);
407 * wait for scan logic to settle:
408 * the scan time consists of (a) a large fixed component, and (b) a
409 * small component that varies with the mii bus frequency. These
410 * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
411 * silicon. Since the effect of (b) was found to be largely
412 * negligible, we keep things simple here.
417 cpsw_mdio->bus->read = cpsw_mdio_sw_read;
418 cpsw_mdio->bus->write = cpsw_mdio_sw_write;
420 cpsw_mdio->bus->read = cpsw_mdio_read;
421 cpsw_mdio->bus->write = cpsw_mdio_write;
424 cpsw_mdio->bus->priv = cpsw_mdio;
425 snprintf(cpsw_mdio->bus->name, sizeof(cpsw_mdio->bus->name), name);
427 ret = mdio_register(cpsw_mdio->bus);
429 debug("failed to register mii bus\n");
433 return cpsw_mdio->bus;
436 mdio_free(cpsw_mdio->bus);
441 void cpsw_mdio_free(struct mii_dev *bus)
443 struct cpsw_mdio *mdio = bus->priv;
447 reg = readl(&mdio->regs->control);
448 reg &= ~CONTROL_ENABLE;
449 writel(reg, &mdio->regs->control);
451 mdio_unregister(bus);