1 // SPDX-License-Identifier: GPL-2.0+
3 * CPSW Ethernet Switch Driver
5 * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/
18 #include <dm/device_compat.h>
19 #include <linux/bitops.h>
20 #include <linux/compiler.h>
21 #include <linux/errno.h>
25 #include <asm/arch/cpu.h>
28 #include "cpsw_mdio.h"
30 #define BITMASK(bits) (BIT(bits) - 1)
31 #define NUM_DESCS (PKTBUFSRX * 2)
33 #define PKT_MAX (1500 + 14 + 4 + 4)
35 #define GIGABITEN BIT(7)
36 #define FULLDUPLEXEN BIT(0)
38 #define CTL_EXT_EN BIT(18)
40 #define CPDMA_TXCONTROL 0x004
41 #define CPDMA_RXCONTROL 0x014
42 #define CPDMA_SOFTRESET 0x01c
43 #define CPDMA_RXFREE 0x0e0
44 #define CPDMA_TXHDP_VER1 0x100
45 #define CPDMA_TXHDP_VER2 0x200
46 #define CPDMA_RXHDP_VER1 0x120
47 #define CPDMA_RXHDP_VER2 0x220
48 #define CPDMA_TXCP_VER1 0x140
49 #define CPDMA_TXCP_VER2 0x240
50 #define CPDMA_RXCP_VER1 0x160
51 #define CPDMA_RXCP_VER2 0x260
53 /* Descriptor mode bits */
54 #define CPDMA_DESC_SOP BIT(31)
55 #define CPDMA_DESC_EOP BIT(30)
56 #define CPDMA_DESC_OWNER BIT(29)
57 #define CPDMA_DESC_EOQ BIT(28)
60 * This timeout definition is a worst-case ultra defensive measure against
61 * unexpected controller lock ups. Ideally, we should never ever hit this
62 * scenario in practice.
64 #define CPDMA_TIMEOUT 100 /* msecs */
74 struct cpsw_slave_regs {
82 #elif defined(CONFIG_TI814X)
91 struct cpsw_host_regs {
98 u32 cpdma_rx_chan_map;
101 struct cpsw_sliver_regs {
114 #define ALE_ENTRY_BITS 68
115 #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
118 #define ALE_CONTROL 0x08
119 #define ALE_UNKNOWNVLAN 0x18
120 #define ALE_TABLE_CONTROL 0x20
121 #define ALE_TABLE 0x34
122 #define ALE_PORTCTL 0x40
124 #define ALE_TABLE_WRITE BIT(31)
126 #define ALE_TYPE_FREE 0
127 #define ALE_TYPE_ADDR 1
128 #define ALE_TYPE_VLAN 2
129 #define ALE_TYPE_VLAN_ADDR 3
131 #define ALE_UCAST_PERSISTANT 0
132 #define ALE_UCAST_UNTOUCHED 1
133 #define ALE_UCAST_OUI 2
134 #define ALE_UCAST_TOUCHED 3
136 #define ALE_MCAST_FWD 0
137 #define ALE_MCAST_BLOCK_LEARN_FWD 1
138 #define ALE_MCAST_FWD_LEARN 2
139 #define ALE_MCAST_FWD_2 3
141 enum cpsw_ale_port_state {
142 ALE_PORT_STATE_DISABLE = 0x00,
143 ALE_PORT_STATE_BLOCK = 0x01,
144 ALE_PORT_STATE_LEARN = 0x02,
145 ALE_PORT_STATE_FORWARD = 0x03,
148 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
150 #define ALE_BLOCKED 2
153 struct cpsw_slave_regs *regs;
154 struct cpsw_sliver_regs *sliver;
157 struct cpsw_slave_data *data;
161 /* hardware fields */
166 /* software fields */
172 struct cpdma_desc *head, *tail;
173 void *hdp, *cp, *rxfree;
176 /* AM33xx SoC specific definitions for the CONTROL port */
177 #define AM33XX_GMII_SEL_MODE_MII 0
178 #define AM33XX_GMII_SEL_MODE_RMII 1
179 #define AM33XX_GMII_SEL_MODE_RGMII 2
181 #define AM33XX_GMII_SEL_RGMII1_IDMODE BIT(4)
182 #define AM33XX_GMII_SEL_RGMII2_IDMODE BIT(5)
183 #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
184 #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
186 #define GMII_SEL_MODE_MASK 0x3
188 #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)
189 #define desc_read(desc, fld) __raw_readl(&(desc)->fld)
190 #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld))
192 #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
193 #define chan_read(chan, fld) __raw_readl((chan)->fld)
194 #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
196 #define for_active_slave(slave, priv) \
197 slave = (priv)->slaves + ((priv)->data)->active_slave; if (slave)
198 #define for_each_slave(slave, priv) \
199 for (slave = (priv)->slaves; slave != (priv)->slaves + \
200 ((priv)->data)->slaves; slave++)
206 struct eth_device *dev;
208 struct cpsw_platform_data *data;
211 struct cpsw_regs *regs;
213 struct cpsw_host_regs *host_port_regs;
216 struct cpdma_desc *descs;
217 struct cpdma_desc *desc_free;
218 struct cpdma_chan rx_chan, tx_chan;
220 struct cpsw_slave *slaves;
221 struct phy_device *phydev;
227 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
233 idx = 2 - idx; /* flip */
234 return (ale_entry[idx] >> start) & BITMASK(bits);
237 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
242 value &= BITMASK(bits);
245 idx = 2 - idx; /* flip */
246 ale_entry[idx] &= ~(BITMASK(bits) << start);
247 ale_entry[idx] |= (value << start);
250 #define DEFINE_ALE_FIELD(name, start, bits) \
251 static inline int __maybe_unused cpsw_ale_get_##name(u32 *ale_entry) \
253 return cpsw_ale_get_field(ale_entry, start, bits); \
255 static inline void __maybe_unused cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
257 cpsw_ale_set_field(ale_entry, start, bits, value); \
260 DEFINE_ALE_FIELD(entry_type, 60, 2)
261 DEFINE_ALE_FIELD(mcast_state, 62, 2)
262 DEFINE_ALE_FIELD(port_mask, 66, 3)
263 DEFINE_ALE_FIELD(ucast_type, 62, 2)
264 DEFINE_ALE_FIELD(port_num, 66, 2)
265 DEFINE_ALE_FIELD(blocked, 65, 1)
266 DEFINE_ALE_FIELD(secure, 64, 1)
267 DEFINE_ALE_FIELD(mcast, 40, 1)
269 /* The MAC address field in the ALE entry cannot be macroized as above */
270 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
274 for (i = 0; i < 6; i++)
275 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
278 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
282 for (i = 0; i < 6; i++)
283 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
286 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
290 __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
292 for (i = 0; i < ALE_ENTRY_WORDS; i++)
293 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
298 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
302 for (i = 0; i < ALE_ENTRY_WORDS; i++)
303 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
305 __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
310 static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
312 u32 ale_entry[ALE_ENTRY_WORDS];
315 for (idx = 0; idx < priv->data->ale_entries; idx++) {
318 cpsw_ale_read(priv, idx, ale_entry);
319 type = cpsw_ale_get_entry_type(ale_entry);
320 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
322 cpsw_ale_get_addr(ale_entry, entry_addr);
323 if (memcmp(entry_addr, addr, 6) == 0)
329 static int cpsw_ale_match_free(struct cpsw_priv *priv)
331 u32 ale_entry[ALE_ENTRY_WORDS];
334 for (idx = 0; idx < priv->data->ale_entries; idx++) {
335 cpsw_ale_read(priv, idx, ale_entry);
336 type = cpsw_ale_get_entry_type(ale_entry);
337 if (type == ALE_TYPE_FREE)
343 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
345 u32 ale_entry[ALE_ENTRY_WORDS];
348 for (idx = 0; idx < priv->data->ale_entries; idx++) {
349 cpsw_ale_read(priv, idx, ale_entry);
350 type = cpsw_ale_get_entry_type(ale_entry);
351 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
353 if (cpsw_ale_get_mcast(ale_entry))
355 type = cpsw_ale_get_ucast_type(ale_entry);
356 if (type != ALE_UCAST_PERSISTANT &&
357 type != ALE_UCAST_OUI)
363 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
366 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
369 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
370 cpsw_ale_set_addr(ale_entry, addr);
371 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
372 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
373 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
374 cpsw_ale_set_port_num(ale_entry, port);
376 idx = cpsw_ale_match_addr(priv, addr);
378 idx = cpsw_ale_match_free(priv);
380 idx = cpsw_ale_find_ageable(priv);
384 cpsw_ale_write(priv, idx, ale_entry);
388 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
391 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
394 idx = cpsw_ale_match_addr(priv, addr);
396 cpsw_ale_read(priv, idx, ale_entry);
398 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
399 cpsw_ale_set_addr(ale_entry, addr);
400 cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
402 mask = cpsw_ale_get_port_mask(ale_entry);
404 cpsw_ale_set_port_mask(ale_entry, port_mask);
407 idx = cpsw_ale_match_free(priv);
409 idx = cpsw_ale_find_ageable(priv);
413 cpsw_ale_write(priv, idx, ale_entry);
417 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
419 u32 tmp, mask = BIT(bit);
421 tmp = __raw_readl(priv->ale_regs + ALE_CONTROL);
423 tmp |= val ? mask : 0;
424 __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
427 #define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val)
428 #define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val)
429 #define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val)
431 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
434 int offset = ALE_PORTCTL + 4 * port;
437 tmp = __raw_readl(priv->ale_regs + offset);
440 __raw_writel(tmp, priv->ale_regs + offset);
443 /* Set a self-clearing bit in a register, and wait for it to clear */
444 static inline void setbit_and_wait_for_clear32(void *addr)
446 __raw_writel(CLEAR_BIT, addr);
447 while (__raw_readl(addr) & CLEAR_BIT)
451 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
452 ((mac)[2] << 16) | ((mac)[3] << 24))
453 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
455 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
456 struct cpsw_priv *priv)
459 struct eth_pdata *pdata = dev_get_platdata(priv->dev);
461 writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
462 writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
464 __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
465 __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
469 static int cpsw_slave_update_link(struct cpsw_slave *slave,
470 struct cpsw_priv *priv, int *link)
472 struct phy_device *phy;
480 ret = phy_startup(phy);
487 if (phy->link) { /* link up */
488 mac_control = priv->data->mac_control;
489 if (phy->speed == 1000)
490 mac_control |= GIGABITEN;
491 if (phy->duplex == DUPLEX_FULL)
492 mac_control |= FULLDUPLEXEN;
493 if (phy->speed == 100)
494 mac_control |= MIIEN;
495 if (phy->speed == 10 && phy_interface_is_rgmii(phy))
496 mac_control |= CTL_EXT_EN;
499 if (mac_control == slave->mac_control)
503 printf("link up on port %d, speed %d, %s duplex\n",
504 slave->slave_num, phy->speed,
505 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
507 printf("link down on port %d\n", slave->slave_num);
510 __raw_writel(mac_control, &slave->sliver->mac_control);
511 slave->mac_control = mac_control;
517 static int cpsw_update_link(struct cpsw_priv *priv)
520 struct cpsw_slave *slave;
522 for_active_slave(slave, priv)
523 ret = cpsw_slave_update_link(slave, priv, NULL);
528 static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
530 if (priv->host_port == 0)
531 return slave_num + 1;
536 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
540 setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
542 /* setup priority mapping */
543 __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
544 __raw_writel(0x33221100, &slave->regs->tx_pri_map);
546 /* setup max packet size, and mac address */
547 __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
548 cpsw_set_slave_mac(slave, priv);
550 slave->mac_control = 0; /* no link yet */
552 /* enable forwarding */
553 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
554 cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
556 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
558 priv->phy_mask |= 1 << slave->data->phy_addr;
561 static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
563 struct cpdma_desc *desc = priv->desc_free;
566 priv->desc_free = desc_read_ptr(desc, hw_next);
570 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
573 desc_write(desc, hw_next, priv->desc_free);
574 priv->desc_free = desc;
578 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
579 void *buffer, int len)
581 struct cpdma_desc *desc, *prev;
584 desc = cpdma_desc_alloc(priv);
591 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
593 desc_write(desc, hw_next, 0);
594 desc_write(desc, hw_buffer, buffer);
595 desc_write(desc, hw_len, len);
596 desc_write(desc, hw_mode, mode | len);
597 desc_write(desc, sw_buffer, buffer);
598 desc_write(desc, sw_len, len);
601 /* simple case - first packet enqueued */
604 chan_write(chan, hdp, desc);
608 /* not the first packet - enqueue at the tail */
610 desc_write(prev, hw_next, desc);
613 /* next check if EOQ has been triggered already */
614 if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
615 chan_write(chan, hdp, desc);
619 chan_write(chan, rxfree, 1);
623 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
624 void **buffer, int *len)
626 struct cpdma_desc *desc = chan->head;
632 status = desc_read(desc, hw_mode);
635 *len = status & 0x7ff;
638 *buffer = desc_read_ptr(desc, sw_buffer);
640 if (status & CPDMA_DESC_OWNER) {
641 if (chan_read(chan, hdp) == 0) {
642 if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
643 chan_write(chan, hdp, desc);
649 chan->head = desc_read_ptr(desc, hw_next);
650 chan_write(chan, cp, desc);
652 cpdma_desc_free(priv, desc);
656 static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr)
658 struct cpsw_slave *slave;
661 /* soft reset the controller and initialize priv */
662 setbit_and_wait_for_clear32(&priv->regs->soft_reset);
664 /* initialize and reset the address lookup engine */
665 cpsw_ale_enable(priv, 1);
666 cpsw_ale_clear(priv, 1);
667 cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
669 /* setup host port priority mapping */
670 __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
671 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
673 /* disable priority elevation and enable statistics on all ports */
674 __raw_writel(0, &priv->regs->ptype);
676 /* enable statistics collection only on the host port */
677 __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
678 __raw_writel(0x7, &priv->regs->stat_port_en);
680 cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
682 cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE);
683 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
685 for_active_slave(slave, priv)
686 cpsw_slave_init(slave, priv);
688 ret = cpsw_update_link(priv);
692 /* init descriptor pool */
693 for (i = 0; i < NUM_DESCS; i++) {
694 desc_write(&priv->descs[i], hw_next,
695 (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
697 priv->desc_free = &priv->descs[0];
699 /* initialize channels */
700 if (priv->data->version == CPSW_CTRL_VERSION_2) {
701 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
702 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
703 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
704 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
706 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
707 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
708 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
710 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
711 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
712 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
713 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
715 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
716 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
717 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
720 /* clear dma state */
721 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
723 if (priv->data->version == CPSW_CTRL_VERSION_2) {
724 for (i = 0; i < priv->data->channels; i++) {
725 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
727 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
729 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
731 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
733 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
737 for (i = 0; i < priv->data->channels; i++) {
738 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
740 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
742 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
744 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
746 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
752 __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
753 __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
755 /* submit rx descs */
756 for (i = 0; i < PKTBUFSRX; i++) {
757 ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
760 printf("error %d submitting rx desc\n", ret);
769 static int cpsw_reap_completed_packets(struct cpsw_priv *priv)
771 int timeout = CPDMA_TIMEOUT;
773 /* reap completed packets */
775 (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0))
781 static void _cpsw_halt(struct cpsw_priv *priv)
783 cpsw_reap_completed_packets(priv);
785 writel(0, priv->dma_regs + CPDMA_TXCONTROL);
786 writel(0, priv->dma_regs + CPDMA_RXCONTROL);
788 /* soft reset the controller and initialize priv */
789 setbit_and_wait_for_clear32(&priv->regs->soft_reset);
791 /* clear dma state */
792 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
796 static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
800 flush_dcache_range((unsigned long)packet,
801 (unsigned long)packet + ALIGN(length, PKTALIGN));
803 timeout = cpsw_reap_completed_packets(priv);
805 printf("cpdma_process timeout\n");
809 return cpdma_submit(priv, &priv->tx_chan, packet, length);
812 static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt)
818 ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len);
822 invalidate_dcache_range((unsigned long)buffer,
823 (unsigned long)buffer + PKTSIZE_ALIGN);
829 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
830 struct cpsw_priv *priv)
832 void *regs = priv->regs;
833 struct cpsw_slave_data *data = priv->data->slave_data + slave_num;
834 slave->slave_num = slave_num;
836 slave->regs = regs + data->slave_reg_ofs;
837 slave->sliver = regs + data->sliver_reg_ofs;
840 static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
842 struct phy_device *phydev;
843 u32 supported = PHY_GBIT_FEATURES;
846 phydev = phy_connect(priv->bus,
847 slave->data->phy_addr,
849 slave->data->phy_if);
854 phydev->supported &= supported;
855 if (slave->data->max_speed) {
856 ret = phy_set_supported(phydev, slave->data->max_speed);
859 dev_dbg(priv->dev, "Port %u speed forced to %uMbit\n",
860 slave->slave_num + 1, slave->data->max_speed);
862 phydev->advertising = phydev->supported;
865 if (ofnode_valid(slave->data->phy_of_handle))
866 phydev->node = slave->data->phy_of_handle;
869 priv->phydev = phydev;
875 static void cpsw_phy_addr_update(struct cpsw_priv *priv)
877 struct cpsw_platform_data *data = priv->data;
878 u16 alive = cpsw_mdio_get_alive(priv->bus);
879 int active = data->active_slave;
880 int new_addr = ffs(alive) - 1;
883 * If there is only one phy alive and its address does not match
884 * that of active slave, then phy address can safely be updated.
886 if (hweight16(alive) == 1 &&
887 data->slave_data[active].phy_addr != new_addr) {
888 printf("Updated phy address for CPSW#%d, old: %d, new: %d\n",
889 active, data->slave_data[active].phy_addr, new_addr);
890 data->slave_data[active].phy_addr = new_addr;
894 int _cpsw_register(struct cpsw_priv *priv)
896 struct cpsw_slave *slave;
897 struct cpsw_platform_data *data = priv->data;
898 void *regs = (void *)data->cpsw_base;
900 priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
905 priv->host_port = data->host_port_num;
907 priv->host_port_regs = regs + data->host_port_reg_ofs;
908 priv->dma_regs = regs + data->cpdma_reg_ofs;
909 priv->ale_regs = regs + data->ale_reg_ofs;
910 priv->descs = (void *)regs + data->bd_ram_ofs;
914 for_each_slave(slave, priv) {
915 cpsw_slave_setup(slave, idx, priv);
919 priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0);
923 cpsw_phy_addr_update(priv);
925 for_active_slave(slave, priv)
926 cpsw_phy_init(priv, slave);
931 #ifndef CONFIG_DM_ETH
932 static int cpsw_init(struct eth_device *dev, bd_t *bis)
934 struct cpsw_priv *priv = dev->priv;
936 return _cpsw_init(priv, dev->enetaddr);
939 static void cpsw_halt(struct eth_device *dev)
941 struct cpsw_priv *priv = dev->priv;
943 return _cpsw_halt(priv);
946 static int cpsw_send(struct eth_device *dev, void *packet, int length)
948 struct cpsw_priv *priv = dev->priv;
950 return _cpsw_send(priv, packet, length);
953 static int cpsw_recv(struct eth_device *dev)
955 struct cpsw_priv *priv = dev->priv;
959 len = _cpsw_recv(priv, &pkt);
962 net_process_received_packet(pkt, len);
963 cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE);
969 int cpsw_register(struct cpsw_platform_data *data)
971 struct cpsw_priv *priv;
972 struct eth_device *dev;
975 dev = calloc(sizeof(*dev), 1);
979 priv = calloc(sizeof(*priv), 1);
988 strcpy(dev->name, "cpsw");
990 dev->init = cpsw_init;
991 dev->halt = cpsw_halt;
992 dev->send = cpsw_send;
993 dev->recv = cpsw_recv;
998 ret = _cpsw_register(priv);
1000 eth_unregister(dev);
1009 static int cpsw_eth_start(struct udevice *dev)
1011 struct eth_pdata *pdata = dev_get_platdata(dev);
1012 struct cpsw_priv *priv = dev_get_priv(dev);
1014 return _cpsw_init(priv, pdata->enetaddr);
1017 static int cpsw_eth_send(struct udevice *dev, void *packet, int length)
1019 struct cpsw_priv *priv = dev_get_priv(dev);
1021 return _cpsw_send(priv, packet, length);
1024 static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1026 struct cpsw_priv *priv = dev_get_priv(dev);
1028 return _cpsw_recv(priv, packetp);
1031 static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet,
1034 struct cpsw_priv *priv = dev_get_priv(dev);
1036 return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE);
1039 static void cpsw_eth_stop(struct udevice *dev)
1041 struct cpsw_priv *priv = dev_get_priv(dev);
1043 return _cpsw_halt(priv);
1046 static const struct eth_ops cpsw_eth_ops = {
1047 .start = cpsw_eth_start,
1048 .send = cpsw_eth_send,
1049 .recv = cpsw_eth_recv,
1050 .free_pkt = cpsw_eth_free_pkt,
1051 .stop = cpsw_eth_stop,
1054 static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
1055 phy_interface_t phy_mode)
1060 bool rgmii_id = false;
1061 int slave = priv->data->active_slave;
1063 reg = readl(priv->data->gmii_sel);
1066 case PHY_INTERFACE_MODE_RMII:
1067 mode = AM33XX_GMII_SEL_MODE_RMII;
1070 case PHY_INTERFACE_MODE_RGMII:
1071 case PHY_INTERFACE_MODE_RGMII_RXID:
1072 mode = AM33XX_GMII_SEL_MODE_RGMII;
1074 case PHY_INTERFACE_MODE_RGMII_ID:
1075 case PHY_INTERFACE_MODE_RGMII_TXID:
1076 mode = AM33XX_GMII_SEL_MODE_RGMII;
1080 case PHY_INTERFACE_MODE_MII:
1082 mode = AM33XX_GMII_SEL_MODE_MII;
1086 mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
1089 if (priv->data->rmii_clock_external) {
1091 mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
1093 mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
1098 mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
1100 mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
1106 writel(reg, priv->data->gmii_sel);
1109 static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv,
1110 phy_interface_t phy_mode)
1115 int slave = priv->data->active_slave;
1117 reg = readl(priv->data->gmii_sel);
1120 case PHY_INTERFACE_MODE_RMII:
1121 mode = AM33XX_GMII_SEL_MODE_RMII;
1124 case PHY_INTERFACE_MODE_RGMII:
1125 case PHY_INTERFACE_MODE_RGMII_ID:
1126 case PHY_INTERFACE_MODE_RGMII_RXID:
1127 case PHY_INTERFACE_MODE_RGMII_TXID:
1128 mode = AM33XX_GMII_SEL_MODE_RGMII;
1131 case PHY_INTERFACE_MODE_MII:
1133 mode = AM33XX_GMII_SEL_MODE_MII;
1139 mask = GMII_SEL_MODE_MASK;
1142 mask = GMII_SEL_MODE_MASK << 4;
1146 dev_err(priv->dev, "invalid slave number...\n");
1150 if (priv->data->rmii_clock_external)
1151 dev_err(priv->dev, "RMII External clock is not supported\n");
1156 writel(reg, priv->data->gmii_sel);
1159 static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat,
1160 phy_interface_t phy_mode)
1162 if (!strcmp(compat, "ti,am3352-cpsw-phy-sel"))
1163 cpsw_gmii_sel_am3352(priv, phy_mode);
1164 if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel"))
1165 cpsw_gmii_sel_am3352(priv, phy_mode);
1166 else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel"))
1167 cpsw_gmii_sel_dra7xx(priv, phy_mode);
1170 static int cpsw_eth_probe(struct udevice *dev)
1172 struct cpsw_priv *priv = dev_get_priv(dev);
1173 struct eth_pdata *pdata = dev_get_platdata(dev);
1176 priv->data = pdata->priv_pdata;
1177 ti_cm_get_macid(dev, priv->data, pdata->enetaddr);
1178 /* Select phy interface in control module */
1179 cpsw_phy_sel(priv, priv->data->phy_sel_compat,
1180 pdata->phy_interface);
1182 return _cpsw_register(priv);
1185 #if CONFIG_IS_ENABLED(OF_CONTROL)
1186 static void cpsw_eth_of_parse_slave(struct cpsw_platform_data *data,
1187 int slave_index, ofnode subnode)
1189 struct ofnode_phandle_args out_args;
1190 struct cpsw_slave_data *slave_data;
1191 const char *phy_mode;
1195 slave_data = &data->slave_data[slave_index];
1197 phy_mode = ofnode_read_string(subnode, "phy-mode");
1199 slave_data->phy_if = phy_get_interface_by_name(phy_mode);
1201 ret = ofnode_parse_phandle_with_args(subnode, "phy-handle",
1202 NULL, 0, 0, &out_args);
1204 slave_data->phy_of_handle = out_args.node;
1206 ret = ofnode_read_s32(slave_data->phy_of_handle, "reg",
1207 &slave_data->phy_addr);
1209 printf("error: phy addr not found in dt\n");
1211 ret = ofnode_read_u32_array(subnode, "phy_id", phy_id, 2);
1213 printf("error: phy_id read failed\n");
1216 slave_data->max_speed = ofnode_read_s32_default(subnode,
1220 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
1222 struct eth_pdata *pdata = dev_get_platdata(dev);
1223 struct cpsw_platform_data *data;
1224 struct gpio_desc *mode_gpios;
1225 int slave_index = 0;
1230 data = calloc(1, sizeof(struct cpsw_platform_data));
1234 pdata->priv_pdata = data;
1235 pdata->iobase = dev_read_addr(dev);
1236 data->version = CPSW_CTRL_VERSION_2;
1237 data->bd_ram_ofs = CPSW_BD_OFFSET;
1238 data->ale_reg_ofs = CPSW_ALE_OFFSET;
1239 data->cpdma_reg_ofs = CPSW_CPDMA_OFFSET;
1240 data->mdio_div = CPSW_MDIO_DIV;
1241 data->host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
1243 pdata->phy_interface = -1;
1245 data->cpsw_base = pdata->iobase;
1247 ret = dev_read_s32(dev, "cpdma_channels", &data->channels);
1249 printf("error: cpdma_channels not found in dt\n");
1253 ret = dev_read_s32(dev, "slaves", &data->slaves);
1255 printf("error: slaves not found in dt\n");
1258 data->slave_data = malloc(sizeof(struct cpsw_slave_data) *
1261 ret = dev_read_s32(dev, "ale_entries", &data->ale_entries);
1263 printf("error: ale_entries not found in dt\n");
1267 ret = dev_read_u32(dev, "bd_ram_size", &data->bd_ram_ofs);
1269 printf("error: bd_ram_size not found in dt\n");
1273 ret = dev_read_u32(dev, "mac_control", &data->mac_control);
1275 printf("error: ale_entries not found in dt\n");
1279 num_mode_gpios = gpio_get_list_count(dev, "mode-gpios");
1280 if (num_mode_gpios > 0) {
1281 mode_gpios = malloc(sizeof(struct gpio_desc) *
1283 gpio_request_list_by_name(dev, "mode-gpios", mode_gpios,
1284 num_mode_gpios, GPIOD_IS_OUT);
1288 data->active_slave = dev_read_u32_default(dev, "active_slave", 0);
1290 ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
1293 name = ofnode_get_name(subnode);
1294 if (!strncmp(name, "mdio", 4)) {
1295 data->mdio_base = ofnode_get_addr(subnode);
1296 if (data->mdio_base == FDT_ADDR_T_NONE) {
1297 pr_err("Not able to get MDIO address space\n");
1302 if (!strncmp(name, "slave", 5)) {
1303 if (slave_index >= data->slaves)
1306 cpsw_eth_of_parse_slave(data, slave_index, subnode);
1310 if (!strncmp(name, "cpsw-phy-sel", 12)) {
1311 data->gmii_sel = ofnode_get_addr(subnode);
1313 if (data->gmii_sel == FDT_ADDR_T_NONE) {
1314 pr_err("Not able to get gmii_sel reg address\n");
1318 if (ofnode_read_bool(subnode, "rmii-clock-ext"))
1319 data->rmii_clock_external = true;
1321 data->phy_sel_compat = ofnode_read_string(subnode,
1323 if (!data->phy_sel_compat) {
1324 pr_err("Not able to get gmii_sel compatible\n");
1330 data->slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET;
1331 data->slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET;
1333 if (data->slaves == 2) {
1334 data->slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET;
1335 data->slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
1338 ret = ti_cm_get_macid_addr(dev, data->active_slave, data);
1340 pr_err("cpsw read efuse mac failed\n");
1344 pdata->phy_interface = data->slave_data[data->active_slave].phy_if;
1345 if (pdata->phy_interface == -1) {
1346 debug("%s: Invalid PHY interface '%s'\n", __func__,
1347 phy_string_for_interface(pdata->phy_interface));
1354 static const struct udevice_id cpsw_eth_ids[] = {
1355 { .compatible = "ti,cpsw" },
1356 { .compatible = "ti,am335x-cpsw" },
1361 int cpsw_get_slave_phy_addr(struct udevice *dev, int slave)
1363 struct cpsw_priv *priv = dev_get_priv(dev);
1364 struct cpsw_platform_data *data = priv->data;
1366 return data->slave_data[slave].phy_addr;
1369 U_BOOT_DRIVER(eth_cpsw) = {
1372 #if CONFIG_IS_ENABLED(OF_CONTROL)
1373 .of_match = cpsw_eth_ids,
1374 .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata,
1375 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1377 .probe = cpsw_eth_probe,
1378 .ops = &cpsw_eth_ops,
1379 .priv_auto_alloc_size = sizeof(struct cpsw_priv),
1380 .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_PRE_RELOC,
1382 #endif /* CONFIG_DM_ETH */