drivers/net/ti/cpsw.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * CPSW Ethernet Switch Driver
   4  *
   5  * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <cpu_func.h>
  11 #include <log.h>
  12 #include <net.h>
  13 #include <miiphy.h>
  14 #include <malloc.h>
  15 #include <net.h>
  16 #include <netdev.h>
  17 #include <cpsw.h>
  18 #include <dm/device_compat.h>
  19 #include <linux/bitops.h>
  20 #include <linux/errno.h>
  21 #include <asm/gpio.h>
  22 #include <asm/io.h>
  23 #include <phy.h>
  24 #include <asm/arch/cpu.h>
  25 #include <dm.h>
  26
  27 #include "cpsw_mdio.h"
  28
  29 #define BITMASK(bits)           (BIT(bits) - 1)
  30 #define NUM_DESCS               (PKTBUFSRX * 2)
  31 #define PKT_MIN                 60
  32 #define PKT_MAX                 (1500 + 14 + 4 + 4)
  33 #define CLEAR_BIT               1
  34 #define GIGABITEN               BIT(7)
  35 #define FULLDUPLEXEN            BIT(0)
  36 #define MIIEN                   BIT(15)
  37 #define CTL_EXT_EN              BIT(18)
  38 /* DMA Registers */
  39 #define CPDMA_TXCONTROL         0x004
  40 #define CPDMA_RXCONTROL         0x014
  41 #define CPDMA_SOFTRESET         0x01c
  42 #define CPDMA_RXFREE            0x0e0
  43 #define CPDMA_TXHDP_VER1        0x100
  44 #define CPDMA_TXHDP_VER2        0x200
  45 #define CPDMA_RXHDP_VER1        0x120
  46 #define CPDMA_RXHDP_VER2        0x220
  47 #define CPDMA_TXCP_VER1         0x140
  48 #define CPDMA_TXCP_VER2         0x240
  49 #define CPDMA_RXCP_VER1         0x160
  50 #define CPDMA_RXCP_VER2         0x260
  51
  52 /* Descriptor mode bits */
  53 #define CPDMA_DESC_SOP          BIT(31)
  54 #define CPDMA_DESC_EOP          BIT(30)
  55 #define CPDMA_DESC_OWNER        BIT(29)
  56 #define CPDMA_DESC_EOQ          BIT(28)
  57
  58 /*
  59  * This timeout definition is a worst-case ultra defensive measure against
  60  * unexpected controller lock ups.  Ideally, we should never ever hit this
  61  * scenario in practice.
  62  */
  63 #define CPDMA_TIMEOUT           100 /* msecs */
  64
  65 struct cpsw_regs {
  66         u32     id_ver;
  67         u32     control;
  68         u32     soft_reset;
  69         u32     stat_port_en;
  70         u32     ptype;
  71 };
  72
  73 struct cpsw_slave_regs {
  74         u32     max_blks;
  75         u32     blk_cnt;
  76         u32     flow_thresh;
  77         u32     port_vlan;
  78         u32     tx_pri_map;
  79 #ifdef CONFIG_AM33XX
  80         u32     gap_thresh;
  81 #elif defined(CONFIG_TI814X)
  82         u32     ts_ctl;
  83         u32     ts_seq_ltype;
  84         u32     ts_vlan;
  85 #endif
  86         u32     sa_lo;
  87         u32     sa_hi;
  88 };
  89
  90 struct cpsw_host_regs {
  91         u32     max_blks;
  92         u32     blk_cnt;
  93         u32     flow_thresh;
  94         u32     port_vlan;
  95         u32     tx_pri_map;
  96         u32     cpdma_tx_pri_map;
  97         u32     cpdma_rx_chan_map;
  98 };
  99
 100 struct cpsw_sliver_regs {
 101         u32     id_ver;
 102         u32     mac_control;
 103         u32     mac_status;
 104         u32     soft_reset;
 105         u32     rx_maxlen;
 106         u32     __reserved_0;
 107         u32     rx_pause;
 108         u32     tx_pause;
 109         u32     __reserved_1;
 110         u32     rx_pri_map;
 111 };
 112
 113 #define ALE_ENTRY_BITS          68
 114 #define ALE_ENTRY_WORDS         DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
 115
 116 /* ALE Registers */
 117 #define ALE_CONTROL             0x08
 118 #define ALE_UNKNOWNVLAN         0x18
 119 #define ALE_TABLE_CONTROL       0x20
 120 #define ALE_TABLE               0x34
 121 #define ALE_PORTCTL             0x40
 122
 123 #define ALE_TABLE_WRITE         BIT(31)
 124
 125 #define ALE_TYPE_FREE                   0
 126 #define ALE_TYPE_ADDR                   1
 127 #define ALE_TYPE_VLAN                   2
 128 #define ALE_TYPE_VLAN_ADDR              3
 129
 130 #define ALE_UCAST_PERSISTANT            0
 131 #define ALE_UCAST_UNTOUCHED             1
 132 #define ALE_UCAST_OUI                   2
 133 #define ALE_UCAST_TOUCHED               3
 134
 135 #define ALE_MCAST_FWD                   0
 136 #define ALE_MCAST_BLOCK_LEARN_FWD       1
 137 #define ALE_MCAST_FWD_LEARN             2
 138 #define ALE_MCAST_FWD_2                 3
 139
 140 enum cpsw_ale_port_state {
 141         ALE_PORT_STATE_DISABLE  = 0x00,
 142         ALE_PORT_STATE_BLOCK    = 0x01,
 143         ALE_PORT_STATE_LEARN    = 0x02,
 144         ALE_PORT_STATE_FORWARD  = 0x03,
 145 };
 146
 147 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
 148 #define ALE_SECURE      1
 149 #define ALE_BLOCKED     2
 150
 151 struct cpsw_slave {
 152         struct cpsw_slave_regs          *regs;
 153         struct cpsw_sliver_regs         *sliver;
 154         int                             slave_num;
 155         u32                             mac_control;
 156         struct cpsw_slave_data          *data;
 157 };
 158
 159 struct cpdma_desc {
 160         /* hardware fields */
 161         u32                     hw_next;
 162         u32                     hw_buffer;
 163         u32                     hw_len;
 164         u32                     hw_mode;
 165         /* software fields */
 166         u32                     sw_buffer;
 167         u32                     sw_len;
 168 };
 169
 170 struct cpdma_chan {
 171         struct cpdma_desc       *head, *tail;
 172         void                    *hdp, *cp, *rxfree;
 173 };
 174
 175 /* AM33xx SoC specific definitions for the CONTROL port */
 176 #define AM33XX_GMII_SEL_MODE_MII        0
 177 #define AM33XX_GMII_SEL_MODE_RMII       1
 178 #define AM33XX_GMII_SEL_MODE_RGMII      2
 179
 180 #define AM33XX_GMII_SEL_RGMII1_IDMODE   BIT(4)
 181 #define AM33XX_GMII_SEL_RGMII2_IDMODE   BIT(5)
 182 #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
 183 #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
 184
 185 #define GMII_SEL_MODE_MASK              0x3
 186
 187 #define desc_write(desc, fld, val)      __raw_writel((u32)(val), &(desc)->fld)
 188 #define desc_read(desc, fld)            __raw_readl(&(desc)->fld)
 189 #define desc_read_ptr(desc, fld)        ((void *)__raw_readl(&(desc)->fld))
 190
 191 #define chan_write(chan, fld, val)      __raw_writel((u32)(val), (chan)->fld)
 192 #define chan_read(chan, fld)            __raw_readl((chan)->fld)
 193 #define chan_read_ptr(chan, fld)        ((void *)__raw_readl((chan)->fld))
 194
 195 #define for_active_slave(slave, priv) \
 196         slave = (priv)->slaves + ((priv)->data)->active_slave; if (slave)
 197 #define for_each_slave(slave, priv) \
 198         for (slave = (priv)->slaves; slave != (priv)->slaves + \
 199                                 ((priv)->data)->slaves; slave++)
 200
 201 struct cpsw_priv {
 202 #ifdef CONFIG_DM_ETH
 203         struct udevice                  *dev;
 204 #else
 205         struct eth_device               *dev;
 206 #endif
 207         struct cpsw_platform_data       *data;
 208         int                             host_port;
 209
 210         struct cpsw_regs                *regs;
 211         void                            *dma_regs;
 212         struct cpsw_host_regs           *host_port_regs;
 213         void                            *ale_regs;
 214
 215         struct cpdma_desc               *descs;
 216         struct cpdma_desc               *desc_free;
 217         struct cpdma_chan               rx_chan, tx_chan;
 218
 219         struct cpsw_slave               *slaves;
 220         struct phy_device               *phydev;
 221         struct mii_dev                  *bus;
 222
 223         u32                             phy_mask;
 224 };
 225
 226 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
 227 {
 228         int idx;
 229
 230         idx    = start / 32;
 231         start -= idx * 32;
 232         idx    = 2 - idx; /* flip */
 233         return (ale_entry[idx] >> start) & BITMASK(bits);
 234 }
 235
 236 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
 237                                       u32 value)
 238 {
 239         int idx;
 240
 241         value &= BITMASK(bits);
 242         idx    = start / 32;
 243         start -= idx * 32;
 244         idx    = 2 - idx; /* flip */
 245         ale_entry[idx] &= ~(BITMASK(bits) << start);
 246         ale_entry[idx] |=  (value << start);
 247 }
 248
 249 #define DEFINE_ALE_FIELD(name, start, bits)                             \
 250 static inline int cpsw_ale_get_##name(u32 *ale_entry)                   \
 251 {                                                                       \
 252         return cpsw_ale_get_field(ale_entry, start, bits);              \
 253 }                                                                       \
 254 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value)       \
 255 {                                                                       \
 256         cpsw_ale_set_field(ale_entry, start, bits, value);              \
 257 }
 258
 259 DEFINE_ALE_FIELD(entry_type,            60,     2)
 260 DEFINE_ALE_FIELD(mcast_state,           62,     2)
 261 DEFINE_ALE_FIELD(port_mask,             66,     3)
 262 DEFINE_ALE_FIELD(ucast_type,            62,     2)
 263 DEFINE_ALE_FIELD(port_num,              66,     2)
 264 DEFINE_ALE_FIELD(blocked,               65,     1)
 265 DEFINE_ALE_FIELD(secure,                64,     1)
 266 DEFINE_ALE_FIELD(mcast,                 40,     1)
 267
 268 /* The MAC address field in the ALE entry cannot be macroized as above */
 269 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
 270 {
 271         int i;
 272
 273         for (i = 0; i < 6; i++)
 274                 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
 275 }
 276
 277 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
 278 {
 279         int i;
 280
 281         for (i = 0; i < 6; i++)
 282                 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
 283 }
 284
 285 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 286 {
 287         int i;
 288
 289         __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
 290
 291         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 292                 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
 293
 294         return idx;
 295 }
 296
 297 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 298 {
 299         int i;
 300
 301         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 302                 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
 303
 304         __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
 305
 306         return idx;
 307 }
 308
 309 static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
 310 {
 311         u32 ale_entry[ALE_ENTRY_WORDS];
 312         int type, idx;
 313
 314         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 315                 u8 entry_addr[6];
 316
 317                 cpsw_ale_read(priv, idx, ale_entry);
 318                 type = cpsw_ale_get_entry_type(ale_entry);
 319                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 320                         continue;
 321                 cpsw_ale_get_addr(ale_entry, entry_addr);
 322                 if (memcmp(entry_addr, addr, 6) == 0)
 323                         return idx;
 324         }
 325         return -ENOENT;
 326 }
 327
 328 static int cpsw_ale_match_free(struct cpsw_priv *priv)
 329 {
 330         u32 ale_entry[ALE_ENTRY_WORDS];
 331         int type, idx;
 332
 333         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 334                 cpsw_ale_read(priv, idx, ale_entry);
 335                 type = cpsw_ale_get_entry_type(ale_entry);
 336                 if (type == ALE_TYPE_FREE)
 337                         return idx;
 338         }
 339         return -ENOENT;
 340 }
 341
 342 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
 343 {
 344         u32 ale_entry[ALE_ENTRY_WORDS];
 345         int type, idx;
 346
 347         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 348                 cpsw_ale_read(priv, idx, ale_entry);
 349                 type = cpsw_ale_get_entry_type(ale_entry);
 350                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 351                         continue;
 352                 if (cpsw_ale_get_mcast(ale_entry))
 353                         continue;
 354                 type = cpsw_ale_get_ucast_type(ale_entry);
 355                 if (type != ALE_UCAST_PERSISTANT &&
 356                     type != ALE_UCAST_OUI)
 357                         return idx;
 358         }
 359         return -ENOENT;
 360 }
 361
 362 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
 363                               int port, int flags)
 364 {
 365         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 366         int idx;
 367
 368         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 369         cpsw_ale_set_addr(ale_entry, addr);
 370         cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
 371         cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
 372         cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
 373         cpsw_ale_set_port_num(ale_entry, port);
 374
 375         idx = cpsw_ale_match_addr(priv, addr);
 376         if (idx < 0)
 377                 idx = cpsw_ale_match_free(priv);
 378         if (idx < 0)
 379                 idx = cpsw_ale_find_ageable(priv);
 380         if (idx < 0)
 381                 return -ENOMEM;
 382
 383         cpsw_ale_write(priv, idx, ale_entry);
 384         return 0;
 385 }
 386
 387 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
 388                               int port_mask)
 389 {
 390         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 391         int idx, mask;
 392
 393         idx = cpsw_ale_match_addr(priv, addr);
 394         if (idx >= 0)
 395                 cpsw_ale_read(priv, idx, ale_entry);
 396
 397         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 398         cpsw_ale_set_addr(ale_entry, addr);
 399         cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
 400
 401         mask = cpsw_ale_get_port_mask(ale_entry);
 402         port_mask |= mask;
 403         cpsw_ale_set_port_mask(ale_entry, port_mask);
 404
 405         if (idx < 0)
 406                 idx = cpsw_ale_match_free(priv);
 407         if (idx < 0)
 408                 idx = cpsw_ale_find_ageable(priv);
 409         if (idx < 0)
 410                 return -ENOMEM;
 411
 412         cpsw_ale_write(priv, idx, ale_entry);
 413         return 0;
 414 }
 415
 416 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
 417 {
 418         u32 tmp, mask = BIT(bit);
 419
 420         tmp  = __raw_readl(priv->ale_regs + ALE_CONTROL);
 421         tmp &= ~mask;
 422         tmp |= val ? mask : 0;
 423         __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
 424 }
 425
 426 #define cpsw_ale_enable(priv, val)      cpsw_ale_control(priv, 31, val)
 427 #define cpsw_ale_clear(priv, val)       cpsw_ale_control(priv, 30, val)
 428 #define cpsw_ale_vlan_aware(priv, val)  cpsw_ale_control(priv,  2, val)
 429
 430 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
 431                                        int val)
 432 {
 433         int offset = ALE_PORTCTL + 4 * port;
 434         u32 tmp, mask = 0x3;
 435
 436         tmp  = __raw_readl(priv->ale_regs + offset);
 437         tmp &= ~mask;
 438         tmp |= val & mask;
 439         __raw_writel(tmp, priv->ale_regs + offset);
 440 }
 441
 442 /* Set a self-clearing bit in a register, and wait for it to clear */
 443 static inline void setbit_and_wait_for_clear32(void *addr)
 444 {
 445         __raw_writel(CLEAR_BIT, addr);
 446         while (__raw_readl(addr) & CLEAR_BIT)
 447                 ;
 448 }
 449
 450 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 451                          ((mac)[2] << 16) | ((mac)[3] << 24))
 452 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 453
 454 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 455                                struct cpsw_priv *priv)
 456 {
 457 #ifdef CONFIG_DM_ETH
 458         struct eth_pdata *pdata = dev_get_platdata(priv->dev);
 459
 460         writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
 461         writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
 462 #else
 463         __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
 464         __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
 465 #endif
 466 }
 467
 468 static int cpsw_slave_update_link(struct cpsw_slave *slave,
 469                                    struct cpsw_priv *priv, int *link)
 470 {
 471         struct phy_device *phy;
 472         u32 mac_control = 0;
 473         int ret = -ENODEV;
 474
 475         phy = priv->phydev;
 476         if (!phy)
 477                 goto out;
 478
 479         ret = phy_startup(phy);
 480         if (ret)
 481                 goto out;
 482
 483         if (link)
 484                 *link = phy->link;
 485
 486         if (phy->link) { /* link up */
 487                 mac_control = priv->data->mac_control;
 488                 if (phy->speed == 1000)
 489                         mac_control |= GIGABITEN;
 490                 if (phy->duplex == DUPLEX_FULL)
 491                         mac_control |= FULLDUPLEXEN;
 492                 if (phy->speed == 100)
 493                         mac_control |= MIIEN;
 494                 if (phy->speed == 10 && phy_interface_is_rgmii(phy))
 495                         mac_control |= CTL_EXT_EN;
 496         }
 497
 498         if (mac_control == slave->mac_control)
 499                 goto out;
 500
 501         if (mac_control) {
 502                 printf("link up on port %d, speed %d, %s duplex\n",
 503                                 slave->slave_num, phy->speed,
 504                                 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
 505         } else {
 506                 printf("link down on port %d\n", slave->slave_num);
 507         }
 508
 509         __raw_writel(mac_control, &slave->sliver->mac_control);
 510         slave->mac_control = mac_control;
 511
 512 out:
 513         return ret;
 514 }
 515
 516 static int cpsw_update_link(struct cpsw_priv *priv)
 517 {
 518         int ret = -ENODEV;
 519         struct cpsw_slave *slave;
 520
 521         for_active_slave(slave, priv)
 522                 ret = cpsw_slave_update_link(slave, priv, NULL);
 523
 524         return ret;
 525 }
 526
 527 static inline u32  cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 528 {
 529         if (priv->host_port == 0)
 530                 return slave_num + 1;
 531         else
 532                 return slave_num;
 533 }
 534
 535 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
 536 {
 537         u32     slave_port;
 538
 539         setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
 540
 541         /* setup priority mapping */
 542         __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
 543         __raw_writel(0x33221100, &slave->regs->tx_pri_map);
 544
 545         /* setup max packet size, and mac address */
 546         __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
 547         cpsw_set_slave_mac(slave, priv);
 548
 549         slave->mac_control = 0; /* no link yet */
 550
 551         /* enable forwarding */
 552         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 553         cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
 554
 555         cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
 556
 557         priv->phy_mask |= 1 << slave->data->phy_addr;
 558 }
 559
 560 static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
 561 {
 562         struct cpdma_desc *desc = priv->desc_free;
 563
 564         if (desc)
 565                 priv->desc_free = desc_read_ptr(desc, hw_next);
 566         return desc;
 567 }
 568
 569 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
 570 {
 571         if (desc) {
 572                 desc_write(desc, hw_next, priv->desc_free);
 573                 priv->desc_free = desc;
 574         }
 575 }
 576
 577 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
 578                         void *buffer, int len)
 579 {
 580         struct cpdma_desc *desc, *prev;
 581         u32 mode;
 582
 583         desc = cpdma_desc_alloc(priv);
 584         if (!desc)
 585                 return -ENOMEM;
 586
 587         if (len < PKT_MIN)
 588                 len = PKT_MIN;
 589
 590         mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
 591
 592         desc_write(desc, hw_next,   0);
 593         desc_write(desc, hw_buffer, buffer);
 594         desc_write(desc, hw_len,    len);
 595         desc_write(desc, hw_mode,   mode | len);
 596         desc_write(desc, sw_buffer, buffer);
 597         desc_write(desc, sw_len,    len);
 598
 599         if (!chan->head) {
 600                 /* simple case - first packet enqueued */
 601                 chan->head = desc;
 602                 chan->tail = desc;
 603                 chan_write(chan, hdp, desc);
 604                 goto done;
 605         }
 606
 607         /* not the first packet - enqueue at the tail */
 608         prev = chan->tail;
 609         desc_write(prev, hw_next, desc);
 610         chan->tail = desc;
 611
 612         /* next check if EOQ has been triggered already */
 613         if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
 614                 chan_write(chan, hdp, desc);
 615
 616 done:
 617         if (chan->rxfree)
 618                 chan_write(chan, rxfree, 1);
 619         return 0;
 620 }
 621
 622 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
 623                          void **buffer, int *len)
 624 {
 625         struct cpdma_desc *desc = chan->head;
 626         u32 status;
 627
 628         if (!desc)
 629                 return -ENOENT;
 630
 631         status = desc_read(desc, hw_mode);
 632
 633         if (len)
 634                 *len = status & 0x7ff;
 635
 636         if (buffer)
 637                 *buffer = desc_read_ptr(desc, sw_buffer);
 638
 639         if (status & CPDMA_DESC_OWNER) {
 640                 if (chan_read(chan, hdp) == 0) {
 641                         if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
 642                                 chan_write(chan, hdp, desc);
 643                 }
 644
 645                 return -EBUSY;
 646         }
 647
 648         chan->head = desc_read_ptr(desc, hw_next);
 649         chan_write(chan, cp, desc);
 650
 651         cpdma_desc_free(priv, desc);
 652         return 0;
 653 }
 654
 655 static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr)
 656 {
 657         struct cpsw_slave       *slave;
 658         int i, ret;
 659
 660         /* soft reset the controller and initialize priv */
 661         setbit_and_wait_for_clear32(&priv->regs->soft_reset);
 662
 663         /* initialize and reset the address lookup engine */
 664         cpsw_ale_enable(priv, 1);
 665         cpsw_ale_clear(priv, 1);
 666         cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
 667
 668         /* setup host port priority mapping */
 669         __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
 670         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
 671
 672         /* disable priority elevation and enable statistics on all ports */
 673         __raw_writel(0, &priv->regs->ptype);
 674
 675         /* enable statistics collection only on the host port */
 676         __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
 677         __raw_writel(0x7, &priv->regs->stat_port_en);
 678
 679         cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
 680
 681         cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE);
 682         cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
 683
 684         for_active_slave(slave, priv)
 685                 cpsw_slave_init(slave, priv);
 686
 687         ret = cpsw_update_link(priv);
 688         if (ret)
 689                 goto out;
 690
 691         /* init descriptor pool */
 692         for (i = 0; i < NUM_DESCS; i++) {
 693                 desc_write(&priv->descs[i], hw_next,
 694                            (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
 695         }
 696         priv->desc_free = &priv->descs[0];
 697
 698         /* initialize channels */
 699         if (priv->data->version == CPSW_CTRL_VERSION_2) {
 700                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 701                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER2;
 702                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER2;
 703                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 704
 705                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 706                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER2;
 707                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER2;
 708         } else {
 709                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 710                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER1;
 711                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER1;
 712                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 713
 714                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 715                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER1;
 716                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER1;
 717         }
 718
 719         /* clear dma state */
 720         setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 721
 722         if (priv->data->version == CPSW_CTRL_VERSION_2) {
 723                 for (i = 0; i < priv->data->channels; i++) {
 724                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
 725                                         * i);
 726                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
 727                                         * i);
 728                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
 729                                         * i);
 730                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
 731                                         * i);
 732                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
 733                                         * i);
 734                 }
 735         } else {
 736                 for (i = 0; i < priv->data->channels; i++) {
 737                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
 738                                         * i);
 739                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
 740                                         * i);
 741                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
 742                                         * i);
 743                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
 744                                         * i);
 745                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
 746                                         * i);
 747
 748                 }
 749         }
 750
 751         __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
 752         __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
 753
 754         /* submit rx descs */
 755         for (i = 0; i < PKTBUFSRX; i++) {
 756                 ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
 757                                    PKTSIZE);
 758                 if (ret < 0) {
 759                         printf("error %d submitting rx desc\n", ret);
 760                         break;
 761                 }
 762         }
 763
 764 out:
 765         return ret;
 766 }
 767
 768 static int cpsw_reap_completed_packets(struct cpsw_priv *priv)
 769 {
 770         int timeout = CPDMA_TIMEOUT;
 771
 772         /* reap completed packets */
 773         while (timeout-- &&
 774                (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0))
 775                 ;
 776
 777         return timeout;
 778 }
 779
 780 static void _cpsw_halt(struct cpsw_priv *priv)
 781 {
 782         cpsw_reap_completed_packets(priv);
 783
 784         writel(0, priv->dma_regs + CPDMA_TXCONTROL);
 785         writel(0, priv->dma_regs + CPDMA_RXCONTROL);
 786
 787         /* soft reset the controller and initialize priv */
 788         setbit_and_wait_for_clear32(&priv->regs->soft_reset);
 789
 790         /* clear dma state */
 791         setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 792
 793 }
 794
 795 static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
 796 {
 797         int timeout;
 798
 799         flush_dcache_range((unsigned long)packet,
 800                            (unsigned long)packet + ALIGN(length, PKTALIGN));
 801
 802         timeout = cpsw_reap_completed_packets(priv);
 803         if (timeout == -1) {
 804                 printf("cpdma_process timeout\n");
 805                 return -ETIMEDOUT;
 806         }
 807
 808         return cpdma_submit(priv, &priv->tx_chan, packet, length);
 809 }
 810
 811 static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt)
 812 {
 813         void *buffer;
 814         int len;
 815         int ret;
 816
 817         ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len);
 818         if (ret < 0)
 819                 return ret;
 820
 821         invalidate_dcache_range((unsigned long)buffer,
 822                                 (unsigned long)buffer + PKTSIZE_ALIGN);
 823         *pkt = buffer;
 824
 825         return len;
 826 }
 827
 828 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
 829                             struct cpsw_priv *priv)
 830 {
 831         void                    *regs = priv->regs;
 832         struct cpsw_slave_data  *data = priv->data->slave_data + slave_num;
 833         slave->slave_num = slave_num;
 834         slave->data     = data;
 835         slave->regs     = regs + data->slave_reg_ofs;
 836         slave->sliver   = regs + data->sliver_reg_ofs;
 837 }
 838
 839 static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
 840 {
 841         struct phy_device *phydev;
 842         u32 supported = PHY_GBIT_FEATURES;
 843         int ret;
 844
 845         phydev = phy_connect(priv->bus,
 846                         slave->data->phy_addr,
 847                         priv->dev,
 848                         slave->data->phy_if);
 849
 850         if (!phydev)
 851                 return -1;
 852
 853         phydev->supported &= supported;
 854         if (slave->data->max_speed) {
 855                 ret = phy_set_supported(phydev, slave->data->max_speed);
 856                 if (ret)
 857                         return ret;
 858                 dev_dbg(priv->dev, "Port %u speed forced to %uMbit\n",
 859                         slave->slave_num + 1, slave->data->max_speed);
 860         }
 861         phydev->advertising = phydev->supported;
 862
 863 #ifdef CONFIG_DM_ETH
 864         if (ofnode_valid(slave->data->phy_of_handle))
 865                 phydev->node = slave->data->phy_of_handle;
 866 #endif
 867
 868         priv->phydev = phydev;
 869         phy_config(phydev);
 870
 871         return 1;
 872 }
 873
 874 static void cpsw_phy_addr_update(struct cpsw_priv *priv)
 875 {
 876         struct cpsw_platform_data *data = priv->data;
 877         u16 alive = cpsw_mdio_get_alive(priv->bus);
 878         int active = data->active_slave;
 879         int new_addr = ffs(alive) - 1;
 880
 881         /*
 882          * If there is only one phy alive and its address does not match
 883          * that of active slave, then phy address can safely be updated.
 884          */
 885         if (hweight16(alive) == 1 &&
 886             data->slave_data[active].phy_addr != new_addr) {
 887                 printf("Updated phy address for CPSW#%d, old: %d, new: %d\n",
 888                        active, data->slave_data[active].phy_addr, new_addr);
 889                 data->slave_data[active].phy_addr = new_addr;
 890         }
 891 }
 892
 893 int _cpsw_register(struct cpsw_priv *priv)
 894 {
 895         struct cpsw_slave       *slave;
 896         struct cpsw_platform_data *data = priv->data;
 897         void                    *regs = (void *)data->cpsw_base;
 898
 899         priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
 900         if (!priv->slaves) {
 901                 return -ENOMEM;
 902         }
 903
 904         priv->host_port         = data->host_port_num;
 905         priv->regs              = regs;
 906         priv->host_port_regs    = regs + data->host_port_reg_ofs;
 907         priv->dma_regs          = regs + data->cpdma_reg_ofs;
 908         priv->ale_regs          = regs + data->ale_reg_ofs;
 909         priv->descs             = (void *)regs + data->bd_ram_ofs;
 910
 911         int idx = 0;
 912
 913         for_each_slave(slave, priv) {
 914                 cpsw_slave_setup(slave, idx, priv);
 915                 idx = idx + 1;
 916         }
 917
 918         priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0);
 919         if (!priv->bus)
 920                 return -EFAULT;
 921
 922         cpsw_phy_addr_update(priv);
 923
 924         for_active_slave(slave, priv)
 925                 cpsw_phy_init(priv, slave);
 926
 927         return 0;
 928 }
 929
 930 #ifndef CONFIG_DM_ETH
 931 static int cpsw_init(struct eth_device *dev, bd_t *bis)
 932 {
 933         struct cpsw_priv        *priv = dev->priv;
 934
 935         return _cpsw_init(priv, dev->enetaddr);
 936 }
 937
 938 static void cpsw_halt(struct eth_device *dev)
 939 {
 940         struct cpsw_priv *priv = dev->priv;
 941
 942         return _cpsw_halt(priv);
 943 }
 944
 945 static int cpsw_send(struct eth_device *dev, void *packet, int length)
 946 {
 947         struct cpsw_priv        *priv = dev->priv;
 948
 949         return _cpsw_send(priv, packet, length);
 950 }
 951
 952 static int cpsw_recv(struct eth_device *dev)
 953 {
 954         struct cpsw_priv *priv = dev->priv;
 955         uchar *pkt = NULL;
 956         int len;
 957
 958         len = _cpsw_recv(priv, &pkt);
 959
 960         if (len > 0) {
 961                 net_process_received_packet(pkt, len);
 962                 cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE);
 963         }
 964
 965         return len;
 966 }
 967
 968 int cpsw_register(struct cpsw_platform_data *data)
 969 {
 970         struct cpsw_priv        *priv;
 971         struct eth_device       *dev;
 972         int ret;
 973
 974         dev = calloc(sizeof(*dev), 1);
 975         if (!dev)
 976                 return -ENOMEM;
 977
 978         priv = calloc(sizeof(*priv), 1);
 979         if (!priv) {
 980                 free(dev);
 981                 return -ENOMEM;
 982         }
 983
 984         priv->dev = dev;
 985         priv->data = data;
 986
 987         strcpy(dev->name, "cpsw");
 988         dev->iobase     = 0;
 989         dev->init       = cpsw_init;
 990         dev->halt       = cpsw_halt;
 991         dev->send       = cpsw_send;
 992         dev->recv       = cpsw_recv;
 993         dev->priv       = priv;
 994
 995         eth_register(dev);
 996
 997         ret = _cpsw_register(priv);
 998         if (ret < 0) {
 999                 eth_unregister(dev);
1000                 free(dev);
1001                 free(priv);
1002                 return ret;
1003         }
1004
1005         return 1;
1006 }
1007 #else
1008 static int cpsw_eth_start(struct udevice *dev)
1009 {
1010         struct eth_pdata *pdata = dev_get_platdata(dev);
1011         struct cpsw_priv *priv = dev_get_priv(dev);
1012
1013         return _cpsw_init(priv, pdata->enetaddr);
1014 }
1015
1016 static int cpsw_eth_send(struct udevice *dev, void *packet, int length)
1017 {
1018         struct cpsw_priv *priv = dev_get_priv(dev);
1019
1020         return _cpsw_send(priv, packet, length);
1021 }
1022
1023 static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1024 {
1025         struct cpsw_priv *priv = dev_get_priv(dev);
1026
1027         return _cpsw_recv(priv, packetp);
1028 }
1029
1030 static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet,
1031                                    int length)
1032 {
1033         struct cpsw_priv *priv = dev_get_priv(dev);
1034
1035         return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE);
1036 }
1037
1038 static void cpsw_eth_stop(struct udevice *dev)
1039 {
1040         struct cpsw_priv *priv = dev_get_priv(dev);
1041
1042         return _cpsw_halt(priv);
1043 }
1044
1045 static const struct eth_ops cpsw_eth_ops = {
1046         .start          = cpsw_eth_start,
1047         .send           = cpsw_eth_send,
1048         .recv           = cpsw_eth_recv,
1049         .free_pkt       = cpsw_eth_free_pkt,
1050         .stop           = cpsw_eth_stop,
1051 };
1052
1053 static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
1054                                  phy_interface_t phy_mode)
1055 {
1056         u32 reg;
1057         u32 mask;
1058         u32 mode = 0;
1059         bool rgmii_id = false;
1060         int slave = priv->data->active_slave;
1061
1062         reg = readl(priv->data->gmii_sel);
1063
1064         switch (phy_mode) {
1065         case PHY_INTERFACE_MODE_RMII:
1066                 mode = AM33XX_GMII_SEL_MODE_RMII;
1067                 break;
1068
1069         case PHY_INTERFACE_MODE_RGMII:
1070         case PHY_INTERFACE_MODE_RGMII_RXID:
1071                 mode = AM33XX_GMII_SEL_MODE_RGMII;
1072                 break;
1073         case PHY_INTERFACE_MODE_RGMII_ID:
1074         case PHY_INTERFACE_MODE_RGMII_TXID:
1075                 mode = AM33XX_GMII_SEL_MODE_RGMII;
1076                 rgmii_id = true;
1077                 break;
1078
1079         case PHY_INTERFACE_MODE_MII:
1080         default:
1081                 mode = AM33XX_GMII_SEL_MODE_MII;
1082                 break;
1083         };
1084
1085         mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
1086         mode <<= slave * 2;
1087
1088         if (priv->data->rmii_clock_external) {
1089                 if (slave == 0)
1090                         mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
1091                 else
1092                         mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
1093         }
1094
1095         if (rgmii_id) {
1096                 if (slave == 0)
1097                         mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
1098                 else
1099                         mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
1100         }
1101
1102         reg &= ~mask;
1103         reg |= mode;
1104
1105         writel(reg, priv->data->gmii_sel);
1106 }
1107
1108 static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv,
1109                                  phy_interface_t phy_mode)
1110 {
1111         u32 reg;
1112         u32 mask;
1113         u32 mode = 0;
1114         int slave = priv->data->active_slave;
1115
1116         reg = readl(priv->data->gmii_sel);
1117
1118         switch (phy_mode) {
1119         case PHY_INTERFACE_MODE_RMII:
1120                 mode = AM33XX_GMII_SEL_MODE_RMII;
1121                 break;
1122
1123         case PHY_INTERFACE_MODE_RGMII:
1124         case PHY_INTERFACE_MODE_RGMII_ID:
1125         case PHY_INTERFACE_MODE_RGMII_RXID:
1126         case PHY_INTERFACE_MODE_RGMII_TXID:
1127                 mode = AM33XX_GMII_SEL_MODE_RGMII;
1128                 break;
1129
1130         case PHY_INTERFACE_MODE_MII:
1131         default:
1132                 mode = AM33XX_GMII_SEL_MODE_MII;
1133                 break;
1134         };
1135
1136         switch (slave) {
1137         case 0:
1138                 mask = GMII_SEL_MODE_MASK;
1139                 break;
1140         case 1:
1141                 mask = GMII_SEL_MODE_MASK << 4;
1142                 mode <<= 4;
1143                 break;
1144         default:
1145                 dev_err(priv->dev, "invalid slave number...\n");
1146                 return;
1147         }
1148
1149         if (priv->data->rmii_clock_external)
1150                 dev_err(priv->dev, "RMII External clock is not supported\n");
1151
1152         reg &= ~mask;
1153         reg |= mode;
1154
1155         writel(reg, priv->data->gmii_sel);
1156 }
1157
1158 static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat,
1159                          phy_interface_t phy_mode)
1160 {
1161         if (!strcmp(compat, "ti,am3352-cpsw-phy-sel"))
1162                 cpsw_gmii_sel_am3352(priv, phy_mode);
1163         if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel"))
1164                 cpsw_gmii_sel_am3352(priv, phy_mode);
1165         else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel"))
1166                 cpsw_gmii_sel_dra7xx(priv, phy_mode);
1167 }
1168
1169 static int cpsw_eth_probe(struct udevice *dev)
1170 {
1171         struct cpsw_priv *priv = dev_get_priv(dev);
1172         struct eth_pdata *pdata = dev_get_platdata(dev);
1173
1174         priv->dev = dev;
1175         priv->data = pdata->priv_pdata;
1176         ti_cm_get_macid(dev, priv->data, pdata->enetaddr);
1177         /* Select phy interface in control module */
1178         cpsw_phy_sel(priv, priv->data->phy_sel_compat,
1179                      pdata->phy_interface);
1180
1181         return _cpsw_register(priv);
1182 }
1183
1184 #if CONFIG_IS_ENABLED(OF_CONTROL)
1185 static void cpsw_eth_of_parse_slave(struct cpsw_platform_data *data,
1186                                     int slave_index, ofnode subnode)
1187 {
1188         struct ofnode_phandle_args out_args;
1189         struct cpsw_slave_data *slave_data;
1190         const char *phy_mode;
1191         u32 phy_id[2];
1192         int ret;
1193
1194         slave_data = &data->slave_data[slave_index];
1195
1196         phy_mode = ofnode_read_string(subnode, "phy-mode");
1197         if (phy_mode)
1198                 slave_data->phy_if = phy_get_interface_by_name(phy_mode);
1199
1200         ret = ofnode_parse_phandle_with_args(subnode, "phy-handle",
1201                                              NULL, 0, 0, &out_args);
1202         if (!ret) {
1203                 slave_data->phy_of_handle = out_args.node;
1204
1205                 ret = ofnode_read_s32(slave_data->phy_of_handle, "reg",
1206                                       &slave_data->phy_addr);
1207                 if (ret)
1208                         printf("error: phy addr not found in dt\n");
1209         } else {
1210                 ret = ofnode_read_u32_array(subnode, "phy_id", phy_id, 2);
1211                 if (ret)
1212                         printf("error: phy_id read failed\n");
1213         }
1214
1215         slave_data->max_speed = ofnode_read_s32_default(subnode,
1216                                                         "max-speed", 0);
1217 }
1218
1219 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
1220 {
1221         struct eth_pdata *pdata = dev_get_platdata(dev);
1222         struct cpsw_platform_data *data;
1223         struct gpio_desc *mode_gpios;
1224         int slave_index = 0;
1225         int num_mode_gpios;
1226         ofnode subnode;
1227         int ret;
1228
1229         data = calloc(1, sizeof(struct cpsw_platform_data));
1230         if (!data)
1231                 return -ENOMEM;
1232
1233         pdata->priv_pdata = data;
1234         pdata->iobase = dev_read_addr(dev);
1235         data->version = CPSW_CTRL_VERSION_2;
1236         data->bd_ram_ofs = CPSW_BD_OFFSET;
1237         data->ale_reg_ofs = CPSW_ALE_OFFSET;
1238         data->cpdma_reg_ofs = CPSW_CPDMA_OFFSET;
1239         data->mdio_div = CPSW_MDIO_DIV;
1240         data->host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
1241
1242         pdata->phy_interface = -1;
1243
1244         data->cpsw_base = pdata->iobase;
1245
1246         ret = dev_read_s32(dev, "cpdma_channels", &data->channels);
1247         if (ret) {
1248                 printf("error: cpdma_channels not found in dt\n");
1249                 return ret;
1250         }
1251
1252         ret = dev_read_s32(dev, "slaves", &data->slaves);
1253         if (ret) {
1254                 printf("error: slaves not found in dt\n");
1255                 return ret;
1256         }
1257         data->slave_data = malloc(sizeof(struct cpsw_slave_data) *
1258                                        data->slaves);
1259
1260         ret = dev_read_s32(dev, "ale_entries", &data->ale_entries);
1261         if (ret) {
1262                 printf("error: ale_entries not found in dt\n");
1263                 return ret;
1264         }
1265
1266         ret = dev_read_u32(dev, "bd_ram_size", &data->bd_ram_ofs);
1267         if (ret) {
1268                 printf("error: bd_ram_size not found in dt\n");
1269                 return ret;
1270         }
1271
1272         ret = dev_read_u32(dev, "mac_control", &data->mac_control);
1273         if (ret) {
1274                 printf("error: ale_entries not found in dt\n");
1275                 return ret;
1276         }
1277
1278         num_mode_gpios = gpio_get_list_count(dev, "mode-gpios");
1279         if (num_mode_gpios > 0) {
1280                 mode_gpios = malloc(sizeof(struct gpio_desc) *
1281                                     num_mode_gpios);
1282                 gpio_request_list_by_name(dev, "mode-gpios", mode_gpios,
1283                                           num_mode_gpios, GPIOD_IS_OUT);
1284                 free(mode_gpios);
1285         }
1286
1287         data->active_slave = dev_read_u32_default(dev, "active_slave", 0);
1288
1289         ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
1290                 const char *name;
1291
1292                 name = ofnode_get_name(subnode);
1293                 if (!strncmp(name, "mdio", 4)) {
1294                         data->mdio_base = ofnode_get_addr(subnode);
1295                         if (data->mdio_base == FDT_ADDR_T_NONE) {
1296                                 pr_err("Not able to get MDIO address space\n");
1297                                 return -ENOENT;
1298                         }
1299                 }
1300
1301                 if (!strncmp(name, "slave", 5)) {
1302                         if (slave_index >= data->slaves)
1303                                 continue;
1304
1305                         cpsw_eth_of_parse_slave(data, slave_index, subnode);
1306                         slave_index++;
1307                 }
1308
1309                 if (!strncmp(name, "cpsw-phy-sel", 12)) {
1310                         data->gmii_sel = ofnode_get_addr(subnode);
1311
1312                         if (data->gmii_sel == FDT_ADDR_T_NONE) {
1313                                 pr_err("Not able to get gmii_sel reg address\n");
1314                                 return -ENOENT;
1315                         }
1316
1317                         if (ofnode_read_bool(subnode, "rmii-clock-ext"))
1318                                 data->rmii_clock_external = true;
1319
1320                         data->phy_sel_compat = ofnode_read_string(subnode,
1321                                                                   "compatible");
1322                         if (!data->phy_sel_compat) {
1323                                 pr_err("Not able to get gmii_sel compatible\n");
1324                                 return -ENOENT;
1325                         }
1326                 }
1327         }
1328
1329         data->slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET;
1330         data->slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET;
1331
1332         if (data->slaves == 2) {
1333                 data->slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET;
1334                 data->slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
1335         }
1336
1337         ret = ti_cm_get_macid_addr(dev, data->active_slave, data);
1338         if (ret < 0) {
1339                 pr_err("cpsw read efuse mac failed\n");
1340                 return ret;
1341         }
1342
1343         pdata->phy_interface = data->slave_data[data->active_slave].phy_if;
1344         if (pdata->phy_interface == -1) {
1345                 debug("%s: Invalid PHY interface '%s'\n", __func__,
1346                       phy_string_for_interface(pdata->phy_interface));
1347                 return -EINVAL;
1348         }
1349
1350         return 0;
1351 }
1352
1353 static const struct udevice_id cpsw_eth_ids[] = {
1354         { .compatible = "ti,cpsw" },
1355         { .compatible = "ti,am335x-cpsw" },
1356         { }
1357 };
1358 #endif
1359
1360 int cpsw_get_slave_phy_addr(struct udevice *dev, int slave)
1361 {
1362         struct cpsw_priv *priv = dev_get_priv(dev);
1363         struct cpsw_platform_data *data = priv->data;
1364
1365         return data->slave_data[slave].phy_addr;
1366 }
1367
1368 U_BOOT_DRIVER(eth_cpsw) = {
1369         .name   = "eth_cpsw",
1370         .id     = UCLASS_ETH,
1371 #if CONFIG_IS_ENABLED(OF_CONTROL)
1372         .of_match = cpsw_eth_ids,
1373         .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata,
1374         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1375 #endif
1376         .probe  = cpsw_eth_probe,
1377         .ops    = &cpsw_eth_ops,
1378         .priv_auto_alloc_size = sizeof(struct cpsw_priv),
1379         .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_PRE_RELOC,
1380 };
1381 #endif /* CONFIG_DM_ETH */