drivers/net/ti/cpsw.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * CPSW Ethernet Switch Driver
   4  *
   5  * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <cpu_func.h>
  11 #include <log.h>
  12 #include <net.h>
  13 #include <miiphy.h>
  14 #include <malloc.h>
  15 #include <net.h>
  16 #include <netdev.h>
  17 #include <cpsw.h>
  18 #include <dm/device_compat.h>
  19 #include <linux/bitops.h>
  20 #include <linux/compiler.h>
  21 #include <linux/errno.h>
  22 #include <asm/gpio.h>
  23 #include <asm/io.h>
  24 #include <phy.h>
  25 #include <asm/arch/cpu.h>
  26 #include <dm.h>
  27
  28 #include "cpsw_mdio.h"
  29
  30 #define BITMASK(bits)           (BIT(bits) - 1)
  31 #define NUM_DESCS               (PKTBUFSRX * 2)
  32 #define PKT_MIN                 60
  33 #define PKT_MAX                 (1500 + 14 + 4 + 4)
  34 #define CLEAR_BIT               1
  35 #define GIGABITEN               BIT(7)
  36 #define FULLDUPLEXEN            BIT(0)
  37 #define MIIEN                   BIT(15)
  38 #define CTL_EXT_EN              BIT(18)
  39 /* DMA Registers */
  40 #define CPDMA_TXCONTROL         0x004
  41 #define CPDMA_RXCONTROL         0x014
  42 #define CPDMA_SOFTRESET         0x01c
  43 #define CPDMA_RXFREE            0x0e0
  44 #define CPDMA_TXHDP_VER1        0x100
  45 #define CPDMA_TXHDP_VER2        0x200
  46 #define CPDMA_RXHDP_VER1        0x120
  47 #define CPDMA_RXHDP_VER2        0x220
  48 #define CPDMA_TXCP_VER1         0x140
  49 #define CPDMA_TXCP_VER2         0x240
  50 #define CPDMA_RXCP_VER1         0x160
  51 #define CPDMA_RXCP_VER2         0x260
  52
  53 /* Descriptor mode bits */
  54 #define CPDMA_DESC_SOP          BIT(31)
  55 #define CPDMA_DESC_EOP          BIT(30)
  56 #define CPDMA_DESC_OWNER        BIT(29)
  57 #define CPDMA_DESC_EOQ          BIT(28)
  58
  59 /*
  60  * This timeout definition is a worst-case ultra defensive measure against
  61  * unexpected controller lock ups.  Ideally, we should never ever hit this
  62  * scenario in practice.
  63  */
  64 #define CPDMA_TIMEOUT           100 /* msecs */
  65
  66 struct cpsw_regs {
  67         u32     id_ver;
  68         u32     control;
  69         u32     soft_reset;
  70         u32     stat_port_en;
  71         u32     ptype;
  72 };
  73
  74 struct cpsw_slave_regs {
  75         u32     max_blks;
  76         u32     blk_cnt;
  77         u32     flow_thresh;
  78         u32     port_vlan;
  79         u32     tx_pri_map;
  80 #ifdef CONFIG_AM33XX
  81         u32     gap_thresh;
  82 #endif
  83         u32     sa_lo;
  84         u32     sa_hi;
  85 };
  86
  87 struct cpsw_host_regs {
  88         u32     max_blks;
  89         u32     blk_cnt;
  90         u32     flow_thresh;
  91         u32     port_vlan;
  92         u32     tx_pri_map;
  93         u32     cpdma_tx_pri_map;
  94         u32     cpdma_rx_chan_map;
  95 };
  96
  97 struct cpsw_sliver_regs {
  98         u32     id_ver;
  99         u32     mac_control;
 100         u32     mac_status;
 101         u32     soft_reset;
 102         u32     rx_maxlen;
 103         u32     __reserved_0;
 104         u32     rx_pause;
 105         u32     tx_pause;
 106         u32     __reserved_1;
 107         u32     rx_pri_map;
 108 };
 109
 110 #define ALE_ENTRY_BITS          68
 111 #define ALE_ENTRY_WORDS         DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
 112
 113 /* ALE Registers */
 114 #define ALE_CONTROL             0x08
 115 #define ALE_UNKNOWNVLAN         0x18
 116 #define ALE_TABLE_CONTROL       0x20
 117 #define ALE_TABLE               0x34
 118 #define ALE_PORTCTL             0x40
 119
 120 #define ALE_TABLE_WRITE         BIT(31)
 121
 122 #define ALE_TYPE_FREE                   0
 123 #define ALE_TYPE_ADDR                   1
 124 #define ALE_TYPE_VLAN                   2
 125 #define ALE_TYPE_VLAN_ADDR              3
 126
 127 #define ALE_UCAST_PERSISTANT            0
 128 #define ALE_UCAST_UNTOUCHED             1
 129 #define ALE_UCAST_OUI                   2
 130 #define ALE_UCAST_TOUCHED               3
 131
 132 #define ALE_MCAST_FWD                   0
 133 #define ALE_MCAST_BLOCK_LEARN_FWD       1
 134 #define ALE_MCAST_FWD_LEARN             2
 135 #define ALE_MCAST_FWD_2                 3
 136
 137 enum cpsw_ale_port_state {
 138         ALE_PORT_STATE_DISABLE  = 0x00,
 139         ALE_PORT_STATE_BLOCK    = 0x01,
 140         ALE_PORT_STATE_LEARN    = 0x02,
 141         ALE_PORT_STATE_FORWARD  = 0x03,
 142 };
 143
 144 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
 145 #define ALE_SECURE      1
 146 #define ALE_BLOCKED     2
 147
 148 struct cpsw_slave {
 149         struct cpsw_slave_regs          *regs;
 150         struct cpsw_sliver_regs         *sliver;
 151         int                             slave_num;
 152         u32                             mac_control;
 153         struct cpsw_slave_data          *data;
 154 };
 155
 156 struct cpdma_desc {
 157         /* hardware fields */
 158         u32                     hw_next;
 159         u32                     hw_buffer;
 160         u32                     hw_len;
 161         u32                     hw_mode;
 162         /* software fields */
 163         u32                     sw_buffer;
 164         u32                     sw_len;
 165 };
 166
 167 struct cpdma_chan {
 168         struct cpdma_desc       *head, *tail;
 169         void                    *hdp, *cp, *rxfree;
 170 };
 171
 172 /* AM33xx SoC specific definitions for the CONTROL port */
 173 #define AM33XX_GMII_SEL_MODE_MII        0
 174 #define AM33XX_GMII_SEL_MODE_RMII       1
 175 #define AM33XX_GMII_SEL_MODE_RGMII      2
 176
 177 #define AM33XX_GMII_SEL_RGMII1_IDMODE   BIT(4)
 178 #define AM33XX_GMII_SEL_RGMII2_IDMODE   BIT(5)
 179 #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
 180 #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
 181
 182 #define GMII_SEL_MODE_MASK              0x3
 183
 184 #define desc_write(desc, fld, val)      __raw_writel((u32)(val), &(desc)->fld)
 185 #define desc_read(desc, fld)            __raw_readl(&(desc)->fld)
 186 #define desc_read_ptr(desc, fld)        ((void *)__raw_readl(&(desc)->fld))
 187
 188 #define chan_write(chan, fld, val)      __raw_writel((u32)(val), (chan)->fld)
 189 #define chan_read(chan, fld)            __raw_readl((chan)->fld)
 190 #define chan_read_ptr(chan, fld)        ((void *)__raw_readl((chan)->fld))
 191
 192 #define for_active_slave(slave, priv) \
 193         slave = (priv)->slaves + ((priv)->data)->active_slave; if (slave)
 194 #define for_each_slave(slave, priv) \
 195         for (slave = (priv)->slaves; slave != (priv)->slaves + \
 196                                 ((priv)->data)->slaves; slave++)
 197
 198 struct cpsw_priv {
 199         struct udevice                  *dev;
 200         struct cpsw_platform_data       *data;
 201         int                             host_port;
 202
 203         struct cpsw_regs                *regs;
 204         void                            *dma_regs;
 205         struct cpsw_host_regs           *host_port_regs;
 206         void                            *ale_regs;
 207
 208         struct cpdma_desc               *descs;
 209         struct cpdma_desc               *desc_free;
 210         struct cpdma_chan               rx_chan, tx_chan;
 211
 212         struct cpsw_slave               *slaves;
 213         struct phy_device               *phydev;
 214         struct mii_dev                  *bus;
 215
 216         u32                             phy_mask;
 217 };
 218
 219 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
 220 {
 221         int idx;
 222
 223         idx    = start / 32;
 224         start -= idx * 32;
 225         idx    = 2 - idx; /* flip */
 226         return (ale_entry[idx] >> start) & BITMASK(bits);
 227 }
 228
 229 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
 230                                       u32 value)
 231 {
 232         int idx;
 233
 234         value &= BITMASK(bits);
 235         idx    = start / 32;
 236         start -= idx * 32;
 237         idx    = 2 - idx; /* flip */
 238         ale_entry[idx] &= ~(BITMASK(bits) << start);
 239         ale_entry[idx] |=  (value << start);
 240 }
 241
 242 #define DEFINE_ALE_FIELD(name, start, bits)                             \
 243 static inline int __maybe_unused cpsw_ale_get_##name(u32 *ale_entry)    \
 244 {                                                                       \
 245         return cpsw_ale_get_field(ale_entry, start, bits);              \
 246 }                                                                       \
 247 static inline void __maybe_unused cpsw_ale_set_##name(u32 *ale_entry, u32 value)        \
 248 {                                                                       \
 249         cpsw_ale_set_field(ale_entry, start, bits, value);              \
 250 }
 251
 252 DEFINE_ALE_FIELD(entry_type,            60,     2)
 253 DEFINE_ALE_FIELD(mcast_state,           62,     2)
 254 DEFINE_ALE_FIELD(port_mask,             66,     3)
 255 DEFINE_ALE_FIELD(ucast_type,            62,     2)
 256 DEFINE_ALE_FIELD(port_num,              66,     2)
 257 DEFINE_ALE_FIELD(blocked,               65,     1)
 258 DEFINE_ALE_FIELD(secure,                64,     1)
 259 DEFINE_ALE_FIELD(mcast,                 40,     1)
 260
 261 /* The MAC address field in the ALE entry cannot be macroized as above */
 262 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
 263 {
 264         int i;
 265
 266         for (i = 0; i < 6; i++)
 267                 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
 268 }
 269
 270 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
 271 {
 272         int i;
 273
 274         for (i = 0; i < 6; i++)
 275                 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
 276 }
 277
 278 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 279 {
 280         int i;
 281
 282         __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
 283
 284         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 285                 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
 286
 287         return idx;
 288 }
 289
 290 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 291 {
 292         int i;
 293
 294         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 295                 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
 296
 297         __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
 298
 299         return idx;
 300 }
 301
 302 static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
 303 {
 304         u32 ale_entry[ALE_ENTRY_WORDS];
 305         int type, idx;
 306
 307         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 308                 u8 entry_addr[6];
 309
 310                 cpsw_ale_read(priv, idx, ale_entry);
 311                 type = cpsw_ale_get_entry_type(ale_entry);
 312                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 313                         continue;
 314                 cpsw_ale_get_addr(ale_entry, entry_addr);
 315                 if (memcmp(entry_addr, addr, 6) == 0)
 316                         return idx;
 317         }
 318         return -ENOENT;
 319 }
 320
 321 static int cpsw_ale_match_free(struct cpsw_priv *priv)
 322 {
 323         u32 ale_entry[ALE_ENTRY_WORDS];
 324         int type, idx;
 325
 326         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 327                 cpsw_ale_read(priv, idx, ale_entry);
 328                 type = cpsw_ale_get_entry_type(ale_entry);
 329                 if (type == ALE_TYPE_FREE)
 330                         return idx;
 331         }
 332         return -ENOENT;
 333 }
 334
 335 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
 336 {
 337         u32 ale_entry[ALE_ENTRY_WORDS];
 338         int type, idx;
 339
 340         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 341                 cpsw_ale_read(priv, idx, ale_entry);
 342                 type = cpsw_ale_get_entry_type(ale_entry);
 343                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 344                         continue;
 345                 if (cpsw_ale_get_mcast(ale_entry))
 346                         continue;
 347                 type = cpsw_ale_get_ucast_type(ale_entry);
 348                 if (type != ALE_UCAST_PERSISTANT &&
 349                     type != ALE_UCAST_OUI)
 350                         return idx;
 351         }
 352         return -ENOENT;
 353 }
 354
 355 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
 356                               int port, int flags)
 357 {
 358         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 359         int idx;
 360
 361         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 362         cpsw_ale_set_addr(ale_entry, addr);
 363         cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
 364         cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
 365         cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
 366         cpsw_ale_set_port_num(ale_entry, port);
 367
 368         idx = cpsw_ale_match_addr(priv, addr);
 369         if (idx < 0)
 370                 idx = cpsw_ale_match_free(priv);
 371         if (idx < 0)
 372                 idx = cpsw_ale_find_ageable(priv);
 373         if (idx < 0)
 374                 return -ENOMEM;
 375
 376         cpsw_ale_write(priv, idx, ale_entry);
 377         return 0;
 378 }
 379
 380 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
 381                               int port_mask)
 382 {
 383         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 384         int idx, mask;
 385
 386         idx = cpsw_ale_match_addr(priv, addr);
 387         if (idx >= 0)
 388                 cpsw_ale_read(priv, idx, ale_entry);
 389
 390         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 391         cpsw_ale_set_addr(ale_entry, addr);
 392         cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
 393
 394         mask = cpsw_ale_get_port_mask(ale_entry);
 395         port_mask |= mask;
 396         cpsw_ale_set_port_mask(ale_entry, port_mask);
 397
 398         if (idx < 0)
 399                 idx = cpsw_ale_match_free(priv);
 400         if (idx < 0)
 401                 idx = cpsw_ale_find_ageable(priv);
 402         if (idx < 0)
 403                 return -ENOMEM;
 404
 405         cpsw_ale_write(priv, idx, ale_entry);
 406         return 0;
 407 }
 408
 409 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
 410 {
 411         u32 tmp, mask = BIT(bit);
 412
 413         tmp  = __raw_readl(priv->ale_regs + ALE_CONTROL);
 414         tmp &= ~mask;
 415         tmp |= val ? mask : 0;
 416         __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
 417 }
 418
 419 #define cpsw_ale_enable(priv, val)      cpsw_ale_control(priv, 31, val)
 420 #define cpsw_ale_clear(priv, val)       cpsw_ale_control(priv, 30, val)
 421 #define cpsw_ale_vlan_aware(priv, val)  cpsw_ale_control(priv,  2, val)
 422
 423 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
 424                                        int val)
 425 {
 426         int offset = ALE_PORTCTL + 4 * port;
 427         u32 tmp, mask = 0x3;
 428
 429         tmp  = __raw_readl(priv->ale_regs + offset);
 430         tmp &= ~mask;
 431         tmp |= val & mask;
 432         __raw_writel(tmp, priv->ale_regs + offset);
 433 }
 434
 435 /* Set a self-clearing bit in a register, and wait for it to clear */
 436 static inline void setbit_and_wait_for_clear32(void *addr)
 437 {
 438         __raw_writel(CLEAR_BIT, addr);
 439         while (__raw_readl(addr) & CLEAR_BIT)
 440                 ;
 441 }
 442
 443 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 444                          ((mac)[2] << 16) | ((mac)[3] << 24))
 445 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 446
 447 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 448                                struct cpsw_priv *priv)
 449 {
 450         struct eth_pdata *pdata = dev_get_plat(priv->dev);
 451
 452         writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
 453         writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
 454 }
 455
 456 static int cpsw_slave_update_link(struct cpsw_slave *slave,
 457                                    struct cpsw_priv *priv, int *link)
 458 {
 459         struct phy_device *phy;
 460         u32 mac_control = 0;
 461         int ret = -ENODEV;
 462
 463         phy = priv->phydev;
 464         if (!phy)
 465                 goto out;
 466
 467         ret = phy_startup(phy);
 468         if (ret)
 469                 goto out;
 470
 471         if (link)
 472                 *link = phy->link;
 473
 474         if (phy->link) { /* link up */
 475                 mac_control = priv->data->mac_control;
 476                 if (phy->speed == 1000)
 477                         mac_control |= GIGABITEN;
 478                 if (phy->duplex == DUPLEX_FULL)
 479                         mac_control |= FULLDUPLEXEN;
 480                 if (phy->speed == 100)
 481                         mac_control |= MIIEN;
 482                 if (phy->speed == 10 && phy_interface_is_rgmii(phy))
 483                         mac_control |= CTL_EXT_EN;
 484         }
 485
 486         if (mac_control == slave->mac_control)
 487                 goto out;
 488
 489         if (mac_control) {
 490                 printf("link up on port %d, speed %d, %s duplex\n",
 491                                 slave->slave_num, phy->speed,
 492                                 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
 493         } else {
 494                 printf("link down on port %d\n", slave->slave_num);
 495         }
 496
 497         __raw_writel(mac_control, &slave->sliver->mac_control);
 498         slave->mac_control = mac_control;
 499
 500 out:
 501         return ret;
 502 }
 503
 504 static int cpsw_update_link(struct cpsw_priv *priv)
 505 {
 506         int ret = -ENODEV;
 507         struct cpsw_slave *slave;
 508
 509         for_active_slave(slave, priv)
 510                 ret = cpsw_slave_update_link(slave, priv, NULL);
 511
 512         return ret;
 513 }
 514
 515 static inline u32  cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 516 {
 517         if (priv->host_port == 0)
 518                 return slave_num + 1;
 519         else
 520                 return slave_num;
 521 }
 522
 523 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
 524 {
 525         u32     slave_port;
 526
 527         setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
 528
 529         /* setup priority mapping */
 530         __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
 531         __raw_writel(0x33221100, &slave->regs->tx_pri_map);
 532
 533         /* setup max packet size, and mac address */
 534         __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
 535         cpsw_set_slave_mac(slave, priv);
 536
 537         slave->mac_control = 0; /* no link yet */
 538
 539         /* enable forwarding */
 540         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 541         cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
 542
 543         cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
 544
 545         priv->phy_mask |= 1 << slave->data->phy_addr;
 546 }
 547
 548 static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
 549 {
 550         struct cpdma_desc *desc = priv->desc_free;
 551
 552         if (desc)
 553                 priv->desc_free = desc_read_ptr(desc, hw_next);
 554         return desc;
 555 }
 556
 557 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
 558 {
 559         if (desc) {
 560                 desc_write(desc, hw_next, priv->desc_free);
 561                 priv->desc_free = desc;
 562         }
 563 }
 564
 565 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
 566                         void *buffer, int len)
 567 {
 568         struct cpdma_desc *desc, *prev;
 569         u32 mode;
 570
 571         desc = cpdma_desc_alloc(priv);
 572         if (!desc)
 573                 return -ENOMEM;
 574
 575         if (len < PKT_MIN)
 576                 len = PKT_MIN;
 577
 578         mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
 579
 580         desc_write(desc, hw_next,   0);
 581         desc_write(desc, hw_buffer, buffer);
 582         desc_write(desc, hw_len,    len);
 583         desc_write(desc, hw_mode,   mode | len);
 584         desc_write(desc, sw_buffer, buffer);
 585         desc_write(desc, sw_len,    len);
 586
 587         if (!chan->head) {
 588                 /* simple case - first packet enqueued */
 589                 chan->head = desc;
 590                 chan->tail = desc;
 591                 chan_write(chan, hdp, desc);
 592                 goto done;
 593         }
 594
 595         /* not the first packet - enqueue at the tail */
 596         prev = chan->tail;
 597         desc_write(prev, hw_next, desc);
 598         chan->tail = desc;
 599
 600         /* next check if EOQ has been triggered already */
 601         if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
 602                 chan_write(chan, hdp, desc);
 603
 604 done:
 605         if (chan->rxfree)
 606                 chan_write(chan, rxfree, 1);
 607         return 0;
 608 }
 609
 610 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
 611                          void **buffer, int *len)
 612 {
 613         struct cpdma_desc *desc = chan->head;
 614         u32 status;
 615
 616         if (!desc)
 617                 return -ENOENT;
 618
 619         status = desc_read(desc, hw_mode);
 620
 621         if (len)
 622                 *len = status & 0x7ff;
 623
 624         if (buffer)
 625                 *buffer = desc_read_ptr(desc, sw_buffer);
 626
 627         if (status & CPDMA_DESC_OWNER) {
 628                 if (chan_read(chan, hdp) == 0) {
 629                         if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
 630                                 chan_write(chan, hdp, desc);
 631                 }
 632
 633                 return -EBUSY;
 634         }
 635
 636         chan->head = desc_read_ptr(desc, hw_next);
 637         chan_write(chan, cp, desc);
 638
 639         cpdma_desc_free(priv, desc);
 640         return 0;
 641 }
 642
 643 static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr)
 644 {
 645         struct cpsw_slave       *slave;
 646         int i, ret;
 647
 648         /* soft reset the controller and initialize priv */
 649         setbit_and_wait_for_clear32(&priv->regs->soft_reset);
 650
 651         /* initialize and reset the address lookup engine */
 652         cpsw_ale_enable(priv, 1);
 653         cpsw_ale_clear(priv, 1);
 654         cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
 655
 656         /* setup host port priority mapping */
 657         __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
 658         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
 659
 660         /* disable priority elevation and enable statistics on all ports */
 661         __raw_writel(0, &priv->regs->ptype);
 662
 663         /* enable statistics collection only on the host port */
 664         __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
 665         __raw_writel(0x7, &priv->regs->stat_port_en);
 666
 667         cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
 668
 669         cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE);
 670         cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
 671
 672         for_active_slave(slave, priv)
 673                 cpsw_slave_init(slave, priv);
 674
 675         ret = cpsw_update_link(priv);
 676         if (ret)
 677                 goto out;
 678
 679         /* init descriptor pool */
 680         for (i = 0; i < NUM_DESCS; i++) {
 681                 desc_write(&priv->descs[i], hw_next,
 682                            (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
 683         }
 684         priv->desc_free = &priv->descs[0];
 685
 686         /* initialize channels */
 687         if (priv->data->version == CPSW_CTRL_VERSION_2) {
 688                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 689                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER2;
 690                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER2;
 691                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 692
 693                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 694                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER2;
 695                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER2;
 696         } else {
 697                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 698                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER1;
 699                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER1;
 700                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 701
 702                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 703                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER1;
 704                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER1;
 705         }
 706
 707         /* clear dma state */
 708         setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 709
 710         if (priv->data->version == CPSW_CTRL_VERSION_2) {
 711                 for (i = 0; i < priv->data->channels; i++) {
 712                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
 713                                         * i);
 714                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
 715                                         * i);
 716                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
 717                                         * i);
 718                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
 719                                         * i);
 720                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
 721                                         * i);
 722                 }
 723         } else {
 724                 for (i = 0; i < priv->data->channels; i++) {
 725                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
 726                                         * i);
 727                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
 728                                         * i);
 729                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
 730                                         * i);
 731                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
 732                                         * i);
 733                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
 734                                         * i);
 735
 736                 }
 737         }
 738
 739         __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
 740         __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
 741
 742         /* submit rx descs */
 743         for (i = 0; i < PKTBUFSRX; i++) {
 744                 ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
 745                                    PKTSIZE);
 746                 if (ret < 0) {
 747                         printf("error %d submitting rx desc\n", ret);
 748                         break;
 749                 }
 750         }
 751
 752 out:
 753         return ret;
 754 }
 755
 756 static int cpsw_reap_completed_packets(struct cpsw_priv *priv)
 757 {
 758         int timeout = CPDMA_TIMEOUT;
 759
 760         /* reap completed packets */
 761         while (timeout-- &&
 762                (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0))
 763                 ;
 764
 765         return timeout;
 766 }
 767
 768 static void _cpsw_halt(struct cpsw_priv *priv)
 769 {
 770         cpsw_reap_completed_packets(priv);
 771
 772         writel(0, priv->dma_regs + CPDMA_TXCONTROL);
 773         writel(0, priv->dma_regs + CPDMA_RXCONTROL);
 774
 775         /* soft reset the controller and initialize priv */
 776         setbit_and_wait_for_clear32(&priv->regs->soft_reset);
 777
 778         /* clear dma state */
 779         setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 780
 781 }
 782
 783 static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
 784 {
 785         int timeout;
 786
 787         flush_dcache_range((unsigned long)packet,
 788                            (unsigned long)packet + ALIGN(length, PKTALIGN));
 789
 790         timeout = cpsw_reap_completed_packets(priv);
 791         if (timeout == -1) {
 792                 printf("cpdma_process timeout\n");
 793                 return -ETIMEDOUT;
 794         }
 795
 796         return cpdma_submit(priv, &priv->tx_chan, packet, length);
 797 }
 798
 799 static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt)
 800 {
 801         void *buffer;
 802         int len;
 803         int ret;
 804
 805         ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len);
 806         if (ret < 0)
 807                 return ret;
 808
 809         invalidate_dcache_range((unsigned long)buffer,
 810                                 (unsigned long)buffer + PKTSIZE_ALIGN);
 811         *pkt = buffer;
 812
 813         return len;
 814 }
 815
 816 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
 817                             struct cpsw_priv *priv)
 818 {
 819         void                    *regs = priv->regs;
 820         struct cpsw_slave_data  *data = priv->data->slave_data + slave_num;
 821         slave->slave_num = slave_num;
 822         slave->data     = data;
 823         slave->regs     = regs + data->slave_reg_ofs;
 824         slave->sliver   = regs + data->sliver_reg_ofs;
 825 }
 826
 827 static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
 828 {
 829         struct phy_device *phydev;
 830         u32 supported = PHY_GBIT_FEATURES;
 831         int ret;
 832
 833         phydev = phy_connect(priv->bus,
 834                         slave->data->phy_addr,
 835                         priv->dev,
 836                         slave->data->phy_if);
 837
 838         if (!phydev)
 839                 return -1;
 840
 841         phydev->supported &= supported;
 842         if (slave->data->max_speed) {
 843                 ret = phy_set_supported(phydev, slave->data->max_speed);
 844                 if (ret)
 845                         return ret;
 846                 dev_dbg(priv->dev, "Port %u speed forced to %uMbit\n",
 847                         slave->slave_num + 1, slave->data->max_speed);
 848         }
 849         phydev->advertising = phydev->supported;
 850
 851         if (ofnode_valid(slave->data->phy_of_handle))
 852                 phydev->node = slave->data->phy_of_handle;
 853
 854         priv->phydev = phydev;
 855         phy_config(phydev);
 856
 857         return 1;
 858 }
 859
 860 static void cpsw_phy_addr_update(struct cpsw_priv *priv)
 861 {
 862         struct cpsw_platform_data *data = priv->data;
 863         u16 alive = cpsw_mdio_get_alive(priv->bus);
 864         int active = data->active_slave;
 865         int new_addr = ffs(alive) - 1;
 866
 867         /*
 868          * If there is only one phy alive and its address does not match
 869          * that of active slave, then phy address can safely be updated.
 870          */
 871         if (hweight16(alive) == 1 &&
 872             data->slave_data[active].phy_addr != new_addr) {
 873                 printf("Updated phy address for CPSW#%d, old: %d, new: %d\n",
 874                        active, data->slave_data[active].phy_addr, new_addr);
 875                 data->slave_data[active].phy_addr = new_addr;
 876         }
 877 }
 878
 879 int _cpsw_register(struct cpsw_priv *priv)
 880 {
 881         struct cpsw_slave       *slave;
 882         struct cpsw_platform_data *data = priv->data;
 883         void                    *regs = (void *)data->cpsw_base;
 884
 885         priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
 886         if (!priv->slaves) {
 887                 return -ENOMEM;
 888         }
 889
 890         priv->host_port         = data->host_port_num;
 891         priv->regs              = regs;
 892         priv->host_port_regs    = regs + data->host_port_reg_ofs;
 893         priv->dma_regs          = regs + data->cpdma_reg_ofs;
 894         priv->ale_regs          = regs + data->ale_reg_ofs;
 895         priv->descs             = (void *)regs + data->bd_ram_ofs;
 896
 897         int idx = 0;
 898
 899         for_each_slave(slave, priv) {
 900                 cpsw_slave_setup(slave, idx, priv);
 901                 idx = idx + 1;
 902         }
 903
 904         priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0,
 905                                    false);
 906         if (!priv->bus)
 907                 return -EFAULT;
 908
 909         cpsw_phy_addr_update(priv);
 910
 911         for_active_slave(slave, priv)
 912                 cpsw_phy_init(priv, slave);
 913
 914         return 0;
 915 }
 916
 917 static int cpsw_eth_start(struct udevice *dev)
 918 {
 919         struct eth_pdata *pdata = dev_get_plat(dev);
 920         struct cpsw_priv *priv = dev_get_priv(dev);
 921
 922         return _cpsw_init(priv, pdata->enetaddr);
 923 }
 924
 925 static int cpsw_eth_send(struct udevice *dev, void *packet, int length)
 926 {
 927         struct cpsw_priv *priv = dev_get_priv(dev);
 928
 929         return _cpsw_send(priv, packet, length);
 930 }
 931
 932 static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 933 {
 934         struct cpsw_priv *priv = dev_get_priv(dev);
 935
 936         return _cpsw_recv(priv, packetp);
 937 }
 938
 939 static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet,
 940                                    int length)
 941 {
 942         struct cpsw_priv *priv = dev_get_priv(dev);
 943
 944         return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE);
 945 }
 946
 947 static void cpsw_eth_stop(struct udevice *dev)
 948 {
 949         struct cpsw_priv *priv = dev_get_priv(dev);
 950
 951         return _cpsw_halt(priv);
 952 }
 953
 954 static const struct eth_ops cpsw_eth_ops = {
 955         .start          = cpsw_eth_start,
 956         .send           = cpsw_eth_send,
 957         .recv           = cpsw_eth_recv,
 958         .free_pkt       = cpsw_eth_free_pkt,
 959         .stop           = cpsw_eth_stop,
 960 };
 961
 962 static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
 963                                  phy_interface_t phy_mode)
 964 {
 965         u32 reg;
 966         u32 mask;
 967         u32 mode = 0;
 968         bool rgmii_id = false;
 969         int slave = priv->data->active_slave;
 970
 971         reg = readl(priv->data->gmii_sel);
 972
 973         switch (phy_mode) {
 974         case PHY_INTERFACE_MODE_RMII:
 975                 mode = AM33XX_GMII_SEL_MODE_RMII;
 976                 break;
 977
 978         case PHY_INTERFACE_MODE_RGMII:
 979         case PHY_INTERFACE_MODE_RGMII_RXID:
 980                 mode = AM33XX_GMII_SEL_MODE_RGMII;
 981                 break;
 982         case PHY_INTERFACE_MODE_RGMII_ID:
 983         case PHY_INTERFACE_MODE_RGMII_TXID:
 984                 mode = AM33XX_GMII_SEL_MODE_RGMII;
 985                 rgmii_id = true;
 986                 break;
 987
 988         case PHY_INTERFACE_MODE_MII:
 989         default:
 990                 mode = AM33XX_GMII_SEL_MODE_MII;
 991                 break;
 992         };
 993
 994         mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
 995         mode <<= slave * 2;
 996
 997         if (priv->data->rmii_clock_external) {
 998                 if (slave == 0)
 999                         mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
1000                 else
1001                         mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
1002         }
1003
1004         if (rgmii_id) {
1005                 if (slave == 0)
1006                         mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
1007                 else
1008                         mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
1009         }
1010
1011         reg &= ~mask;
1012         reg |= mode;
1013
1014         writel(reg, priv->data->gmii_sel);
1015 }
1016
1017 static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv,
1018                                  phy_interface_t phy_mode)
1019 {
1020         u32 reg;
1021         u32 mask;
1022         u32 mode = 0;
1023         int slave = priv->data->active_slave;
1024
1025         reg = readl(priv->data->gmii_sel);
1026
1027         switch (phy_mode) {
1028         case PHY_INTERFACE_MODE_RMII:
1029                 mode = AM33XX_GMII_SEL_MODE_RMII;
1030                 break;
1031
1032         case PHY_INTERFACE_MODE_RGMII:
1033         case PHY_INTERFACE_MODE_RGMII_ID:
1034         case PHY_INTERFACE_MODE_RGMII_RXID:
1035         case PHY_INTERFACE_MODE_RGMII_TXID:
1036                 mode = AM33XX_GMII_SEL_MODE_RGMII;
1037                 break;
1038
1039         case PHY_INTERFACE_MODE_MII:
1040         default:
1041                 mode = AM33XX_GMII_SEL_MODE_MII;
1042                 break;
1043         };
1044
1045         switch (slave) {
1046         case 0:
1047                 mask = GMII_SEL_MODE_MASK;
1048                 break;
1049         case 1:
1050                 mask = GMII_SEL_MODE_MASK << 4;
1051                 mode <<= 4;
1052                 break;
1053         default:
1054                 dev_err(priv->dev, "invalid slave number...\n");
1055                 return;
1056         }
1057
1058         if (priv->data->rmii_clock_external)
1059                 dev_err(priv->dev, "RMII External clock is not supported\n");
1060
1061         reg &= ~mask;
1062         reg |= mode;
1063
1064         writel(reg, priv->data->gmii_sel);
1065 }
1066
1067 static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat,
1068                          phy_interface_t phy_mode)
1069 {
1070         if (!strcmp(compat, "ti,am3352-cpsw-phy-sel"))
1071                 cpsw_gmii_sel_am3352(priv, phy_mode);
1072         if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel"))
1073                 cpsw_gmii_sel_am3352(priv, phy_mode);
1074         else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel"))
1075                 cpsw_gmii_sel_dra7xx(priv, phy_mode);
1076 }
1077
1078 static int cpsw_eth_probe(struct udevice *dev)
1079 {
1080         struct cpsw_priv *priv = dev_get_priv(dev);
1081         struct eth_pdata *pdata = dev_get_plat(dev);
1082
1083         priv->dev = dev;
1084         priv->data = pdata->priv_pdata;
1085         ti_cm_get_macid(dev, priv->data, pdata->enetaddr);
1086         /* Select phy interface in control module */
1087         cpsw_phy_sel(priv, priv->data->phy_sel_compat,
1088                      pdata->phy_interface);
1089
1090         return _cpsw_register(priv);
1091 }
1092
1093 #if CONFIG_IS_ENABLED(OF_CONTROL)
1094 static void cpsw_eth_of_parse_slave(struct cpsw_platform_data *data,
1095                                     int slave_index, ofnode subnode)
1096 {
1097         struct ofnode_phandle_args out_args;
1098         struct cpsw_slave_data *slave_data;
1099         u32 phy_id[2];
1100         int ret;
1101
1102         slave_data = &data->slave_data[slave_index];
1103
1104         slave_data->phy_if = ofnode_read_phy_mode(subnode);
1105
1106         ret = ofnode_parse_phandle_with_args(subnode, "phy-handle",
1107                                              NULL, 0, 0, &out_args);
1108         if (!ret) {
1109                 slave_data->phy_of_handle = out_args.node;
1110
1111                 ret = ofnode_read_s32(slave_data->phy_of_handle, "reg",
1112                                       &slave_data->phy_addr);
1113                 if (ret)
1114                         printf("error: phy addr not found in dt\n");
1115         } else {
1116                 ret = ofnode_read_u32_array(subnode, "phy_id", phy_id, 2);
1117                 if (ret)
1118                         printf("error: phy_id read failed\n");
1119         }
1120
1121         slave_data->max_speed = ofnode_read_s32_default(subnode,
1122                                                         "max-speed", 0);
1123 }
1124
1125 static int cpsw_eth_of_to_plat(struct udevice *dev)
1126 {
1127         struct eth_pdata *pdata = dev_get_plat(dev);
1128         struct cpsw_platform_data *data;
1129         struct gpio_desc *mode_gpios;
1130         int slave_index = 0;
1131         int num_mode_gpios;
1132         ofnode subnode;
1133         int ret;
1134
1135         data = calloc(1, sizeof(struct cpsw_platform_data));
1136         if (!data)
1137                 return -ENOMEM;
1138
1139         pdata->priv_pdata = data;
1140         pdata->iobase = dev_read_addr(dev);
1141         data->version = CPSW_CTRL_VERSION_2;
1142         data->bd_ram_ofs = CPSW_BD_OFFSET;
1143         data->ale_reg_ofs = CPSW_ALE_OFFSET;
1144         data->cpdma_reg_ofs = CPSW_CPDMA_OFFSET;
1145         data->mdio_div = CPSW_MDIO_DIV;
1146         data->host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
1147
1148         pdata->phy_interface = -1;
1149
1150         data->cpsw_base = pdata->iobase;
1151
1152         ret = dev_read_s32(dev, "cpdma_channels", &data->channels);
1153         if (ret) {
1154                 printf("error: cpdma_channels not found in dt\n");
1155                 return ret;
1156         }
1157
1158         ret = dev_read_s32(dev, "slaves", &data->slaves);
1159         if (ret) {
1160                 printf("error: slaves not found in dt\n");
1161                 return ret;
1162         }
1163         data->slave_data = malloc(sizeof(struct cpsw_slave_data) *
1164                                        data->slaves);
1165
1166         ret = dev_read_s32(dev, "ale_entries", &data->ale_entries);
1167         if (ret) {
1168                 printf("error: ale_entries not found in dt\n");
1169                 return ret;
1170         }
1171
1172         ret = dev_read_u32(dev, "bd_ram_size", &data->bd_ram_ofs);
1173         if (ret) {
1174                 printf("error: bd_ram_size not found in dt\n");
1175                 return ret;
1176         }
1177
1178         ret = dev_read_u32(dev, "mac_control", &data->mac_control);
1179         if (ret) {
1180                 printf("error: ale_entries not found in dt\n");
1181                 return ret;
1182         }
1183
1184         num_mode_gpios = gpio_get_list_count(dev, "mode-gpios");
1185         if (num_mode_gpios > 0) {
1186                 mode_gpios = malloc(sizeof(struct gpio_desc) *
1187                                     num_mode_gpios);
1188                 gpio_request_list_by_name(dev, "mode-gpios", mode_gpios,
1189                                           num_mode_gpios, GPIOD_IS_OUT);
1190                 free(mode_gpios);
1191         }
1192
1193         data->active_slave = dev_read_u32_default(dev, "active_slave", 0);
1194
1195         ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
1196                 const char *name;
1197
1198                 name = ofnode_get_name(subnode);
1199                 if (!strncmp(name, "mdio", 4)) {
1200                         data->mdio_base = ofnode_get_addr(subnode);
1201                         if (data->mdio_base == FDT_ADDR_T_NONE) {
1202                                 pr_err("Not able to get MDIO address space\n");
1203                                 return -ENOENT;
1204                         }
1205                 }
1206
1207                 if (!strncmp(name, "slave", 5)) {
1208                         if (slave_index >= data->slaves)
1209                                 continue;
1210
1211                         cpsw_eth_of_parse_slave(data, slave_index, subnode);
1212                         slave_index++;
1213                 }
1214
1215                 if (!strncmp(name, "cpsw-phy-sel", 12)) {
1216                         data->gmii_sel = ofnode_get_addr(subnode);
1217
1218                         if (data->gmii_sel == FDT_ADDR_T_NONE) {
1219                                 pr_err("Not able to get gmii_sel reg address\n");
1220                                 return -ENOENT;
1221                         }
1222
1223                         if (ofnode_read_bool(subnode, "rmii-clock-ext"))
1224                                 data->rmii_clock_external = true;
1225
1226                         data->phy_sel_compat = ofnode_read_string(subnode,
1227                                                                   "compatible");
1228                         if (!data->phy_sel_compat) {
1229                                 pr_err("Not able to get gmii_sel compatible\n");
1230                                 return -ENOENT;
1231                         }
1232                 }
1233         }
1234
1235         data->slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET;
1236         data->slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET;
1237
1238         if (data->slaves == 2) {
1239                 data->slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET;
1240                 data->slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
1241         }
1242
1243         ret = ti_cm_get_macid_addr(dev, data->active_slave, data);
1244         if (ret < 0) {
1245                 pr_err("cpsw read efuse mac failed\n");
1246                 return ret;
1247         }
1248
1249         pdata->phy_interface = data->slave_data[data->active_slave].phy_if;
1250         if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
1251                 return -EINVAL;
1252
1253         return 0;
1254 }
1255
1256 static const struct udevice_id cpsw_eth_ids[] = {
1257         { .compatible = "ti,cpsw" },
1258         { .compatible = "ti,am335x-cpsw" },
1259         { }
1260 };
1261 #endif
1262
1263 int cpsw_get_slave_phy_addr(struct udevice *dev, int slave)
1264 {
1265         struct cpsw_priv *priv = dev_get_priv(dev);
1266         struct cpsw_platform_data *data = priv->data;
1267
1268         return data->slave_data[slave].phy_addr;
1269 }
1270
1271 U_BOOT_DRIVER(eth_cpsw) = {
1272         .name   = "eth_cpsw",
1273         .id     = UCLASS_ETH,
1274 #if CONFIG_IS_ENABLED(OF_CONTROL)
1275         .of_match = cpsw_eth_ids,
1276         .of_to_plat = cpsw_eth_of_to_plat,
1277         .plat_auto      = sizeof(struct eth_pdata),
1278 #endif
1279         .probe  = cpsw_eth_probe,
1280         .ops    = &cpsw_eth_ops,
1281         .priv_auto      = sizeof(struct cpsw_priv),
1282         .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_PRE_RELOC,
1283 };