drivers/net/ti/am65-cpsw-nuss.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver
   4  *
   5  * Copyright (C) 2019, Texas Instruments, Incorporated
   6  *
   7  */
   8
   9 #include <common.h>
  10 #include <malloc.h>
  11 #include <asm/cache.h>
  12 #include <asm/io.h>
  13 #include <asm/processor.h>
  14 #include <clk.h>
  15 #include <dm.h>
  16 #include <dm/device_compat.h>
  17 #include <dm/lists.h>
  18 #include <dm/pinctrl.h>
  19 #include <dma-uclass.h>
  20 #include <dm/of_access.h>
  21 #include <miiphy.h>
  22 #include <net.h>
  23 #include <phy.h>
  24 #include <power-domain.h>
  25 #include <regmap.h>
  26 #include <soc.h>
  27 #include <syscon.h>
  28 #include <linux/bitops.h>
  29 #include <linux/soc/ti/ti-udma.h>
  30
  31 #include "cpsw_mdio.h"
  32
  33 #define AM65_CPSW_CPSWNU_MAX_PORTS 9
  34
  35 #define AM65_CPSW_SS_BASE               0x0
  36 #define AM65_CPSW_SGMII_BASE    0x100
  37 #define AM65_CPSW_MDIO_BASE     0xf00
  38 #define AM65_CPSW_XGMII_BASE    0x2100
  39 #define AM65_CPSW_CPSW_NU_BASE  0x20000
  40 #define AM65_CPSW_CPSW_NU_ALE_BASE 0x1e000
  41
  42 #define AM65_CPSW_CPSW_NU_PORTS_OFFSET  0x1000
  43 #define AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET     0x330
  44
  45 #define AM65_CPSW_MDIO_BUS_FREQ_DEF 1000000
  46
  47 #define AM65_CPSW_CTL_REG                       0x4
  48 #define AM65_CPSW_STAT_PORT_EN_REG      0x14
  49 #define AM65_CPSW_PTYPE_REG             0x18
  50
  51 #define AM65_CPSW_CTL_REG_P0_ENABLE                     BIT(2)
  52 #define AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE              BIT(13)
  53 #define AM65_CPSW_CTL_REG_P0_RX_PAD                     BIT(14)
  54
  55 #define AM65_CPSW_P0_FLOW_ID_REG                        0x8
  56 #define AM65_CPSW_PN_RX_MAXLEN_REG              0x24
  57 #define AM65_CPSW_PN_REG_SA_L                   0x308
  58 #define AM65_CPSW_PN_REG_SA_H                   0x30c
  59
  60 #define AM65_CPSW_ALE_CTL_REG                   0x8
  61 #define AM65_CPSW_ALE_CTL_REG_ENABLE            BIT(31)
  62 #define AM65_CPSW_ALE_CTL_REG_RESET_TBL         BIT(30)
  63 #define AM65_CPSW_ALE_CTL_REG_BYPASS            BIT(4)
  64 #define AM65_CPSW_ALE_PN_CTL_REG(x)             (0x40 + (x) * 4)
  65 #define AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD   0x3
  66 #define AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY       BIT(11)
  67
  68 #define AM65_CPSW_ALE_THREADMAPDEF_REG          0x134
  69 #define AM65_CPSW_ALE_DEFTHREAD_EN              BIT(15)
  70
  71 #define AM65_CPSW_MACSL_CTL_REG                 0x0
  72 #define AM65_CPSW_MACSL_CTL_REG_IFCTL_A         BIT(15)
  73 #define AM65_CPSW_MACSL_CTL_EXT_EN              BIT(18)
  74 #define AM65_CPSW_MACSL_CTL_REG_GIG             BIT(7)
  75 #define AM65_CPSW_MACSL_CTL_REG_GMII_EN         BIT(5)
  76 #define AM65_CPSW_MACSL_CTL_REG_LOOPBACK        BIT(1)
  77 #define AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX     BIT(0)
  78 #define AM65_CPSW_MACSL_RESET_REG               0x8
  79 #define AM65_CPSW_MACSL_RESET_REG_RESET         BIT(0)
  80 #define AM65_CPSW_MACSL_STATUS_REG              0x4
  81 #define AM65_CPSW_MACSL_RESET_REG_PN_IDLE       BIT(31)
  82 #define AM65_CPSW_MACSL_RESET_REG_PN_E_IDLE     BIT(30)
  83 #define AM65_CPSW_MACSL_RESET_REG_PN_P_IDLE     BIT(29)
  84 #define AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE    BIT(28)
  85 #define AM65_CPSW_MACSL_RESET_REG_IDLE_MASK \
  86         (AM65_CPSW_MACSL_RESET_REG_PN_IDLE | \
  87          AM65_CPSW_MACSL_RESET_REG_PN_E_IDLE | \
  88          AM65_CPSW_MACSL_RESET_REG_PN_P_IDLE | \
  89          AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE)
  90
  91 #define AM65_CPSW_CPPI_PKT_TYPE                 0x7
  92
  93 struct am65_cpsw_port {
  94         fdt_addr_t      port_base;
  95         fdt_addr_t      macsl_base;
  96         bool            disabled;
  97         u32             mac_control;
  98 };
  99
 100 struct am65_cpsw_common {
 101         struct udevice          *dev;
 102         fdt_addr_t              ss_base;
 103         fdt_addr_t              cpsw_base;
 104         fdt_addr_t              mdio_base;
 105         fdt_addr_t              ale_base;
 106
 107         struct clk              fclk;
 108         struct power_domain     pwrdmn;
 109
 110         u32                     port_num;
 111         struct am65_cpsw_port   ports[AM65_CPSW_CPSWNU_MAX_PORTS];
 112
 113         struct mii_dev          *bus;
 114         u32                     bus_freq;
 115
 116         struct dma              dma_tx;
 117         struct dma              dma_rx;
 118         u32                     rx_next;
 119         u32                     rx_pend;
 120         bool                    started;
 121 };
 122
 123 struct am65_cpsw_priv {
 124         struct udevice          *dev;
 125         struct am65_cpsw_common *cpsw_common;
 126         u32                     port_id;
 127
 128         struct phy_device       *phydev;
 129         bool                    has_phy;
 130         ofnode                  phy_node;
 131         u32                     phy_addr;
 132
 133         bool                    mdio_manual_mode;
 134 };
 135
 136 #ifdef PKTSIZE_ALIGN
 137 #define UDMA_RX_BUF_SIZE PKTSIZE_ALIGN
 138 #else
 139 #define UDMA_RX_BUF_SIZE ALIGN(1522, ARCH_DMA_MINALIGN)
 140 #endif
 141
 142 #ifdef PKTBUFSRX
 143 #define UDMA_RX_DESC_NUM PKTBUFSRX
 144 #else
 145 #define UDMA_RX_DESC_NUM 4
 146 #endif
 147
 148 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 149                          ((mac)[2] << 16) | ((mac)[3] << 24))
 150 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 151
 152 static void am65_cpsw_set_sl_mac(struct am65_cpsw_port *slave,
 153                                  unsigned char *addr)
 154 {
 155         writel(mac_hi(addr),
 156                slave->port_base + AM65_CPSW_PN_REG_SA_H);
 157         writel(mac_lo(addr),
 158                slave->port_base + AM65_CPSW_PN_REG_SA_L);
 159 }
 160
 161 int am65_cpsw_macsl_reset(struct am65_cpsw_port *slave)
 162 {
 163         u32 i = 100;
 164
 165         /* Set the soft reset bit */
 166         writel(AM65_CPSW_MACSL_RESET_REG_RESET,
 167                slave->macsl_base + AM65_CPSW_MACSL_RESET_REG);
 168
 169         while ((readl(slave->macsl_base + AM65_CPSW_MACSL_RESET_REG) &
 170                 AM65_CPSW_MACSL_RESET_REG_RESET) && i--)
 171                 cpu_relax();
 172
 173         /* Timeout on the reset */
 174         return i;
 175 }
 176
 177 static int am65_cpsw_macsl_wait_for_idle(struct am65_cpsw_port *slave)
 178 {
 179         u32 i = 100;
 180
 181         while ((readl(slave->macsl_base + AM65_CPSW_MACSL_STATUS_REG) &
 182                 AM65_CPSW_MACSL_RESET_REG_IDLE_MASK) && i--)
 183                 cpu_relax();
 184
 185         return i;
 186 }
 187
 188 static int am65_cpsw_update_link(struct am65_cpsw_priv *priv)
 189 {
 190         struct am65_cpsw_common *common = priv->cpsw_common;
 191         struct am65_cpsw_port *port = &common->ports[priv->port_id];
 192         struct phy_device *phy = priv->phydev;
 193         u32 mac_control = 0;
 194
 195         if (phy->link) { /* link up */
 196                 mac_control = /*AM65_CPSW_MACSL_CTL_REG_LOOPBACK |*/
 197                               AM65_CPSW_MACSL_CTL_REG_GMII_EN;
 198                 if (phy->speed == 1000)
 199                         mac_control |= AM65_CPSW_MACSL_CTL_REG_GIG;
 200                 if (phy->speed == 10 && phy_interface_is_rgmii(phy))
 201                         /* Can be used with in band mode only */
 202                         mac_control |= AM65_CPSW_MACSL_CTL_EXT_EN;
 203                 if (phy->duplex == DUPLEX_FULL)
 204                         mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX;
 205                 if (phy->speed == 100)
 206                         mac_control |= AM65_CPSW_MACSL_CTL_REG_IFCTL_A;
 207         }
 208
 209         if (mac_control == port->mac_control)
 210                 goto out;
 211
 212         if (mac_control) {
 213                 printf("link up on port %d, speed %d, %s duplex\n",
 214                        priv->port_id, phy->speed,
 215                        (phy->duplex == DUPLEX_FULL) ? "full" : "half");
 216         } else {
 217                 printf("link down on port %d\n", priv->port_id);
 218         }
 219
 220         writel(mac_control, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
 221         port->mac_control = mac_control;
 222
 223 out:
 224         return phy->link;
 225 }
 226
 227 #define AM65_GMII_SEL_PORT_OFFS(x)      (0x4 * ((x) - 1))
 228
 229 #define AM65_GMII_SEL_MODE_MII          0
 230 #define AM65_GMII_SEL_MODE_RMII         1
 231 #define AM65_GMII_SEL_MODE_RGMII        2
 232
 233 #define AM65_GMII_SEL_RGMII_IDMODE      BIT(4)
 234
 235 static int am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv,
 236                                  phy_interface_t phy_mode)
 237 {
 238         struct udevice *dev = priv->dev;
 239         u32 offset, reg, phandle;
 240         bool rgmii_id = false;
 241         fdt_addr_t gmii_sel;
 242         u32 mode = 0;
 243         ofnode node;
 244         int ret;
 245
 246         ret = ofnode_read_u32(dev_ofnode(dev), "phys", &phandle);
 247         if (ret)
 248                 return ret;
 249
 250         ret = ofnode_read_u32_index(dev_ofnode(dev), "phys", 1, &offset);
 251         if (ret)
 252                 return ret;
 253
 254         node = ofnode_get_by_phandle(phandle);
 255         if (!ofnode_valid(node))
 256                 return -ENODEV;
 257
 258         gmii_sel = ofnode_get_addr(node);
 259         if (gmii_sel == FDT_ADDR_T_NONE)
 260                 return -ENODEV;
 261
 262         gmii_sel += AM65_GMII_SEL_PORT_OFFS(offset);
 263         reg = readl(gmii_sel);
 264
 265         dev_dbg(dev, "old gmii_sel: %08x\n", reg);
 266
 267         switch (phy_mode) {
 268         case PHY_INTERFACE_MODE_RMII:
 269                 mode = AM65_GMII_SEL_MODE_RMII;
 270                 break;
 271
 272         case PHY_INTERFACE_MODE_RGMII:
 273         case PHY_INTERFACE_MODE_RGMII_RXID:
 274                 mode = AM65_GMII_SEL_MODE_RGMII;
 275                 break;
 276
 277         case PHY_INTERFACE_MODE_RGMII_ID:
 278         case PHY_INTERFACE_MODE_RGMII_TXID:
 279                 mode = AM65_GMII_SEL_MODE_RGMII;
 280                 rgmii_id = true;
 281                 break;
 282
 283         default:
 284                 dev_warn(dev,
 285                          "Unsupported PHY mode: %u. Defaulting to MII.\n",
 286                          phy_mode);
 287                 /* fallthrough */
 288         case PHY_INTERFACE_MODE_MII:
 289                 mode = AM65_GMII_SEL_MODE_MII;
 290                 break;
 291         };
 292
 293         if (rgmii_id)
 294                 mode |= AM65_GMII_SEL_RGMII_IDMODE;
 295
 296         reg = mode;
 297         dev_dbg(dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n",
 298                 phy_mode, reg);
 299         writel(reg, gmii_sel);
 300
 301         reg = readl(gmii_sel);
 302         if (reg != mode) {
 303                 dev_err(dev,
 304                         "gmii_sel PHY mode NOT SET!: requested: %08x, gmii_sel: %08x\n",
 305                         mode, reg);
 306                 return 0;
 307         }
 308
 309         return 0;
 310 }
 311
 312 static int am65_cpsw_start(struct udevice *dev)
 313 {
 314         struct eth_pdata *pdata = dev_get_plat(dev);
 315         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 316         struct am65_cpsw_common *common = priv->cpsw_common;
 317         struct am65_cpsw_port *port = &common->ports[priv->port_id];
 318         struct am65_cpsw_port *port0 = &common->ports[0];
 319         struct ti_udma_drv_chan_cfg_data *dma_rx_cfg_data;
 320         int ret, i;
 321
 322         ret = power_domain_on(&common->pwrdmn);
 323         if (ret) {
 324                 dev_err(dev, "power_domain_on() failed %d\n", ret);
 325                 goto out;
 326         }
 327
 328         ret = clk_enable(&common->fclk);
 329         if (ret) {
 330                 dev_err(dev, "clk enabled failed %d\n", ret);
 331                 goto err_off_pwrdm;
 332         }
 333
 334         common->rx_next = 0;
 335         common->rx_pend = 0;
 336         ret = dma_get_by_name(common->dev, "tx0", &common->dma_tx);
 337         if (ret) {
 338                 dev_err(dev, "TX dma get failed %d\n", ret);
 339                 goto err_off_clk;
 340         }
 341         ret = dma_get_by_name(common->dev, "rx", &common->dma_rx);
 342         if (ret) {
 343                 dev_err(dev, "RX dma get failed %d\n", ret);
 344                 goto err_free_tx;
 345         }
 346
 347         for (i = 0; i < UDMA_RX_DESC_NUM; i++) {
 348                 ret = dma_prepare_rcv_buf(&common->dma_rx,
 349                                           net_rx_packets[i],
 350                                           UDMA_RX_BUF_SIZE);
 351                 if (ret) {
 352                         dev_err(dev, "RX dma add buf failed %d\n", ret);
 353                         goto err_free_tx;
 354                 }
 355         }
 356
 357         ret = dma_enable(&common->dma_tx);
 358         if (ret) {
 359                 dev_err(dev, "TX dma_enable failed %d\n", ret);
 360                 goto err_free_rx;
 361         }
 362         ret = dma_enable(&common->dma_rx);
 363         if (ret) {
 364                 dev_err(dev, "RX dma_enable failed %d\n", ret);
 365                 goto err_dis_tx;
 366         }
 367
 368         /* Control register */
 369         writel(AM65_CPSW_CTL_REG_P0_ENABLE |
 370                AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE |
 371                AM65_CPSW_CTL_REG_P0_RX_PAD,
 372                common->cpsw_base + AM65_CPSW_CTL_REG);
 373
 374         /* disable priority elevation */
 375         writel(0, common->cpsw_base + AM65_CPSW_PTYPE_REG);
 376
 377         /* enable statistics */
 378         writel(BIT(0) | BIT(priv->port_id),
 379                common->cpsw_base + AM65_CPSW_STAT_PORT_EN_REG);
 380
 381         /* Port 0  length register */
 382         writel(PKTSIZE_ALIGN, port0->port_base + AM65_CPSW_PN_RX_MAXLEN_REG);
 383
 384         /* set base flow_id */
 385         dma_get_cfg(&common->dma_rx, 0, (void **)&dma_rx_cfg_data);
 386         writel(dma_rx_cfg_data->flow_id_base,
 387                port0->port_base + AM65_CPSW_P0_FLOW_ID_REG);
 388         dev_info(dev, "K3 CPSW: rflow_id_base: %u\n",
 389                  dma_rx_cfg_data->flow_id_base);
 390
 391         /* Reset and enable the ALE */
 392         writel(AM65_CPSW_ALE_CTL_REG_ENABLE | AM65_CPSW_ALE_CTL_REG_RESET_TBL |
 393                AM65_CPSW_ALE_CTL_REG_BYPASS,
 394                common->ale_base + AM65_CPSW_ALE_CTL_REG);
 395
 396         /* port 0 put into forward mode */
 397         writel(AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD,
 398                common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
 399
 400         writel(AM65_CPSW_ALE_DEFTHREAD_EN,
 401                common->ale_base + AM65_CPSW_ALE_THREADMAPDEF_REG);
 402
 403         /* PORT x configuration */
 404
 405         /* Port x Max length register */
 406         writel(PKTSIZE_ALIGN, port->port_base + AM65_CPSW_PN_RX_MAXLEN_REG);
 407
 408         /* Port x set mac */
 409         am65_cpsw_set_sl_mac(port, pdata->enetaddr);
 410
 411         /* Port x ALE: mac_only, Forwarding */
 412         writel(AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY |
 413                AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD,
 414                common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
 415
 416         port->mac_control = 0;
 417         if (!am65_cpsw_macsl_reset(port)) {
 418                 dev_err(dev, "mac_sl reset failed\n");
 419                 ret = -EFAULT;
 420                 goto err_dis_rx;
 421         }
 422
 423         ret = phy_startup(priv->phydev);
 424         if (ret) {
 425                 dev_err(dev, "phy_startup failed\n");
 426                 goto err_dis_rx;
 427         }
 428
 429         ret = am65_cpsw_update_link(priv);
 430         if (!ret) {
 431                 ret = -ENODEV;
 432                 goto err_phy_shutdown;
 433         }
 434
 435         common->started = true;
 436
 437         return 0;
 438
 439 err_phy_shutdown:
 440         phy_shutdown(priv->phydev);
 441 err_dis_rx:
 442         /* disable ports */
 443         writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
 444         writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
 445         if (!am65_cpsw_macsl_wait_for_idle(port))
 446                 dev_err(dev, "mac_sl idle timeout\n");
 447         writel(0, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
 448         writel(0, common->ale_base + AM65_CPSW_ALE_CTL_REG);
 449         writel(0, common->cpsw_base + AM65_CPSW_CTL_REG);
 450
 451         dma_disable(&common->dma_rx);
 452 err_dis_tx:
 453         dma_disable(&common->dma_tx);
 454 err_free_rx:
 455         dma_free(&common->dma_rx);
 456 err_free_tx:
 457         dma_free(&common->dma_tx);
 458 err_off_clk:
 459         clk_disable(&common->fclk);
 460 err_off_pwrdm:
 461         power_domain_off(&common->pwrdmn);
 462 out:
 463         dev_err(dev, "%s end error\n", __func__);
 464
 465         return ret;
 466 }
 467
 468 static int am65_cpsw_send(struct udevice *dev, void *packet, int length)
 469 {
 470         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 471         struct am65_cpsw_common *common = priv->cpsw_common;
 472         struct ti_udma_drv_packet_data packet_data;
 473         int ret;
 474
 475         packet_data.pkt_type = AM65_CPSW_CPPI_PKT_TYPE;
 476         packet_data.dest_tag = priv->port_id;
 477         ret = dma_send(&common->dma_tx, packet, length, &packet_data);
 478         if (ret) {
 479                 dev_err(dev, "TX dma_send failed %d\n", ret);
 480                 return ret;
 481         }
 482
 483         return 0;
 484 }
 485
 486 static int am65_cpsw_recv(struct udevice *dev, int flags, uchar **packetp)
 487 {
 488         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 489         struct am65_cpsw_common *common = priv->cpsw_common;
 490
 491         /* try to receive a new packet */
 492         return dma_receive(&common->dma_rx, (void **)packetp, NULL);
 493 }
 494
 495 static int am65_cpsw_free_pkt(struct udevice *dev, uchar *packet, int length)
 496 {
 497         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 498         struct am65_cpsw_common *common = priv->cpsw_common;
 499         int ret;
 500
 501         if (length > 0) {
 502                 u32 pkt = common->rx_next % UDMA_RX_DESC_NUM;
 503
 504                 ret = dma_prepare_rcv_buf(&common->dma_rx,
 505                                           net_rx_packets[pkt],
 506                                           UDMA_RX_BUF_SIZE);
 507                 if (ret)
 508                         dev_err(dev, "RX dma free_pkt failed %d\n", ret);
 509                 common->rx_next++;
 510         }
 511
 512         return 0;
 513 }
 514
 515 static void am65_cpsw_stop(struct udevice *dev)
 516 {
 517         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 518         struct am65_cpsw_common *common = priv->cpsw_common;
 519         struct am65_cpsw_port *port = &common->ports[priv->port_id];
 520
 521         if (!common->started)
 522                 return;
 523
 524         phy_shutdown(priv->phydev);
 525
 526         writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
 527         writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
 528         if (!am65_cpsw_macsl_wait_for_idle(port))
 529                 dev_err(dev, "mac_sl idle timeout\n");
 530         writel(0, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
 531         writel(0, common->ale_base + AM65_CPSW_ALE_CTL_REG);
 532         writel(0, common->cpsw_base + AM65_CPSW_CTL_REG);
 533
 534         dma_disable(&common->dma_tx);
 535         dma_free(&common->dma_tx);
 536
 537         dma_disable(&common->dma_rx);
 538         dma_free(&common->dma_rx);
 539
 540         common->started = false;
 541 }
 542
 543 static int am65_cpsw_am654_get_efuse_macid(struct udevice *dev,
 544                                            int slave, u8 *mac_addr)
 545 {
 546         u32 mac_lo, mac_hi, offset;
 547         struct regmap *syscon;
 548         int ret;
 549
 550         syscon = syscon_regmap_lookup_by_phandle(dev, "ti,syscon-efuse");
 551         if (IS_ERR(syscon)) {
 552                 if (PTR_ERR(syscon) == -ENODEV)
 553                         return 0;
 554                 return PTR_ERR(syscon);
 555         }
 556
 557         ret = dev_read_u32_index(dev, "ti,syscon-efuse", 1, &offset);
 558         if (ret)
 559                 return ret;
 560
 561         regmap_read(syscon, offset, &mac_lo);
 562         regmap_read(syscon, offset + 4, &mac_hi);
 563
 564         mac_addr[0] = (mac_hi >> 8) & 0xff;
 565         mac_addr[1] = mac_hi & 0xff;
 566         mac_addr[2] = (mac_lo >> 24) & 0xff;
 567         mac_addr[3] = (mac_lo >> 16) & 0xff;
 568         mac_addr[4] = (mac_lo >> 8) & 0xff;
 569         mac_addr[5] = mac_lo & 0xff;
 570
 571         return 0;
 572 }
 573
 574 static int am65_cpsw_read_rom_hwaddr(struct udevice *dev)
 575 {
 576         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 577         struct eth_pdata *pdata = dev_get_plat(dev);
 578
 579         am65_cpsw_am654_get_efuse_macid(dev,
 580                                         priv->port_id,
 581                                         pdata->enetaddr);
 582
 583         return 0;
 584 }
 585
 586 static const struct eth_ops am65_cpsw_ops = {
 587         .start          = am65_cpsw_start,
 588         .send           = am65_cpsw_send,
 589         .recv           = am65_cpsw_recv,
 590         .free_pkt       = am65_cpsw_free_pkt,
 591         .stop           = am65_cpsw_stop,
 592         .read_rom_hwaddr = am65_cpsw_read_rom_hwaddr,
 593 };
 594
 595 static const struct soc_attr k3_mdio_soc_data[] = {
 596         { .family = "AM62X", .revision = "SR1.0" },
 597         { .family = "AM64X", .revision = "SR1.0" },
 598         { .family = "AM64X", .revision = "SR2.0" },
 599         { .family = "AM65X", .revision = "SR1.0" },
 600         { .family = "AM65X", .revision = "SR2.0" },
 601         { .family = "J7200", .revision = "SR1.0" },
 602         { .family = "J7200", .revision = "SR2.0" },
 603         { .family = "J721E", .revision = "SR1.0" },
 604         { .family = "J721E", .revision = "SR1.1" },
 605         { .family = "J721S2", .revision = "SR1.0" },
 606         { /* sentinel */ },
 607 };
 608
 609 static ofnode am65_cpsw_find_mdio(ofnode parent)
 610 {
 611         ofnode node;
 612
 613         ofnode_for_each_subnode(node, parent)
 614                 if (ofnode_device_is_compatible(node, "ti,cpsw-mdio"))
 615                         return node;
 616
 617         return ofnode_null();
 618 }
 619
 620 static int am65_cpsw_mdio_setup(struct udevice *dev)
 621 {
 622         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 623         struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
 624         struct udevice *mdio_dev;
 625         ofnode mdio;
 626         int ret;
 627
 628         mdio = am65_cpsw_find_mdio(dev_ofnode(cpsw_common->dev));
 629         if (!ofnode_valid(mdio))
 630                 return 0;
 631
 632         /*
 633          * The MDIO controller is represented in the DT binding by a
 634          * subnode of the MAC controller.
 635          *
 636          * We don't have a DM driver for the MDIO device yet, and thus any
 637          * pinctrl setting on its node will be ignored.
 638          *
 639          * However, we do need to make sure the pins states tied to the
 640          * MDIO node are configured properly. Fortunately, the core DM
 641          * does that for use when we get a device, so we can work around
 642          * that whole issue by just requesting a dummy MDIO driver to
 643          * probe, and our pins will get muxed.
 644          */
 645         ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdio_dev);
 646         if (ret)
 647                 return ret;
 648
 649         return 0;
 650 }
 651
 652 static int am65_cpsw_mdio_init(struct udevice *dev)
 653 {
 654         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 655         struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
 656         int ret;
 657
 658         if (!priv->has_phy || cpsw_common->bus)
 659                 return 0;
 660
 661         ret = am65_cpsw_mdio_setup(dev);
 662         if (ret)
 663                 return ret;
 664
 665         cpsw_common->bus = cpsw_mdio_init(dev->name,
 666                                           cpsw_common->mdio_base,
 667                                           cpsw_common->bus_freq,
 668                                           clk_get_rate(&cpsw_common->fclk),
 669                                           priv->mdio_manual_mode);
 670         if (!cpsw_common->bus)
 671                 return -EFAULT;
 672
 673         return 0;
 674 }
 675
 676 static int am65_cpsw_phy_init(struct udevice *dev)
 677 {
 678         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 679         struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
 680         struct eth_pdata *pdata = dev_get_plat(dev);
 681         struct phy_device *phydev;
 682         u32 supported = PHY_GBIT_FEATURES;
 683         int ret;
 684
 685         phydev = phy_connect(cpsw_common->bus,
 686                              priv->phy_addr,
 687                              priv->dev,
 688                              pdata->phy_interface);
 689
 690         if (!phydev) {
 691                 dev_err(dev, "phy_connect() failed\n");
 692                 return -ENODEV;
 693         }
 694
 695         phydev->supported &= supported;
 696         if (pdata->max_speed) {
 697                 ret = phy_set_supported(phydev, pdata->max_speed);
 698                 if (ret)
 699                         return ret;
 700         }
 701         phydev->advertising = phydev->supported;
 702
 703         if (ofnode_valid(priv->phy_node))
 704                 phydev->node = priv->phy_node;
 705
 706         priv->phydev = phydev;
 707         ret = phy_config(phydev);
 708         if (ret < 0)
 709                 pr_err("phy_config() failed: %d", ret);
 710
 711         return ret;
 712 }
 713
 714 static int am65_cpsw_ofdata_parse_phy(struct udevice *dev)
 715 {
 716         struct eth_pdata *pdata = dev_get_plat(dev);
 717         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 718         struct ofnode_phandle_args out_args;
 719         int ret = 0;
 720
 721         dev_read_u32(dev, "reg", &priv->port_id);
 722
 723         pdata->phy_interface = dev_read_phy_mode(dev);
 724         if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
 725                 dev_err(dev, "Invalid PHY mode, port %u\n", priv->port_id);
 726                 return -EINVAL;
 727         }
 728
 729         dev_read_u32(dev, "max-speed", (u32 *)&pdata->max_speed);
 730         if (pdata->max_speed)
 731                 dev_err(dev, "Port %u speed froced to %uMbit\n",
 732                         priv->port_id, pdata->max_speed);
 733
 734         priv->has_phy  = true;
 735         ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle",
 736                                              NULL, 0, 0, &out_args);
 737         if (ret) {
 738                 dev_err(dev, "can't parse phy-handle port %u (%d)\n",
 739                         priv->port_id, ret);
 740                 priv->has_phy  = false;
 741                 ret = 0;
 742         }
 743
 744         priv->phy_node = out_args.node;
 745         if (priv->has_phy) {
 746                 ret = ofnode_read_u32(priv->phy_node, "reg", &priv->phy_addr);
 747                 if (ret) {
 748                         dev_err(dev, "failed to get phy_addr port %u (%d)\n",
 749                                 priv->port_id, ret);
 750                         goto out;
 751                 }
 752         }
 753
 754 out:
 755         return ret;
 756 }
 757
 758 static int am65_cpsw_port_probe(struct udevice *dev)
 759 {
 760         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 761         struct eth_pdata *pdata = dev_get_plat(dev);
 762         struct am65_cpsw_common *cpsw_common;
 763         char portname[15];
 764         int ret;
 765
 766         priv->dev = dev;
 767
 768         cpsw_common = dev_get_priv(dev->parent);
 769         priv->cpsw_common = cpsw_common;
 770
 771         sprintf(portname, "%s%s", dev->parent->name, dev->name);
 772         device_set_name(dev, portname);
 773
 774         priv->mdio_manual_mode = false;
 775         if (soc_device_match(k3_mdio_soc_data))
 776                 priv->mdio_manual_mode = true;
 777
 778         ret = am65_cpsw_ofdata_parse_phy(dev);
 779         if (ret)
 780                 goto out;
 781
 782         ret = am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface);
 783         if (ret)
 784                 goto out;
 785
 786         ret = am65_cpsw_mdio_init(dev);
 787         if (ret)
 788                 goto out;
 789
 790         ret = am65_cpsw_phy_init(dev);
 791         if (ret)
 792                 goto out;
 793 out:
 794         return ret;
 795 }
 796
 797 static int am65_cpsw_probe_nuss(struct udevice *dev)
 798 {
 799         struct am65_cpsw_common *cpsw_common = dev_get_priv(dev);
 800         ofnode ports_np, node;
 801         int ret, i;
 802         struct udevice *port_dev;
 803
 804         cpsw_common->dev = dev;
 805         cpsw_common->ss_base = dev_read_addr(dev);
 806         if (cpsw_common->ss_base == FDT_ADDR_T_NONE)
 807                 return -EINVAL;
 808
 809         ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0);
 810         if (ret) {
 811                 dev_err(dev, "failed to get pwrdmn: %d\n", ret);
 812                 return ret;
 813         }
 814
 815         ret = clk_get_by_name(dev, "fck", &cpsw_common->fclk);
 816         if (ret) {
 817                 power_domain_free(&cpsw_common->pwrdmn);
 818                 dev_err(dev, "failed to get clock %d\n", ret);
 819                 return ret;
 820         }
 821
 822         cpsw_common->cpsw_base = cpsw_common->ss_base + AM65_CPSW_CPSW_NU_BASE;
 823         cpsw_common->ale_base = cpsw_common->cpsw_base +
 824                                 AM65_CPSW_CPSW_NU_ALE_BASE;
 825         cpsw_common->mdio_base = cpsw_common->ss_base + AM65_CPSW_MDIO_BASE;
 826
 827         ports_np = dev_read_subnode(dev, "ethernet-ports");
 828         if (!ofnode_valid(ports_np)) {
 829                 ret = -ENOENT;
 830                 goto out;
 831         }
 832
 833         ofnode_for_each_subnode(node, ports_np) {
 834                 const char *node_name;
 835                 u32 port_id;
 836                 bool disabled;
 837
 838                 node_name = ofnode_get_name(node);
 839
 840                 disabled = !ofnode_is_enabled(node);
 841
 842                 ret = ofnode_read_u32(node, "reg", &port_id);
 843                 if (ret) {
 844                         dev_err(dev, "%s: failed to get port_id (%d)\n",
 845                                 node_name, ret);
 846                         goto out;
 847                 }
 848
 849                 if (port_id >= AM65_CPSW_CPSWNU_MAX_PORTS) {
 850                         dev_err(dev, "%s: invalid port_id (%d)\n",
 851                                 node_name, port_id);
 852                         ret = -EINVAL;
 853                         goto out;
 854                 }
 855                 cpsw_common->port_num++;
 856
 857                 if (!port_id)
 858                         continue;
 859
 860                 cpsw_common->ports[port_id].disabled = disabled;
 861                 if (disabled)
 862                         continue;
 863
 864                 ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", ofnode_get_name(node), node, &port_dev);
 865                 if (ret)
 866                         dev_err(dev, "Failed to bind to %s node\n", ofnode_get_name(node));
 867         }
 868
 869         for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) {
 870                 struct am65_cpsw_port *port = &cpsw_common->ports[i];
 871
 872                 port->port_base = cpsw_common->cpsw_base +
 873                                   AM65_CPSW_CPSW_NU_PORTS_OFFSET +
 874                                   (i * AM65_CPSW_CPSW_NU_PORTS_OFFSET);
 875                 port->macsl_base = port->port_base +
 876                                    AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET;
 877         }
 878
 879         cpsw_common->bus_freq =
 880                         dev_read_u32_default(dev, "bus_freq",
 881                                              AM65_CPSW_MDIO_BUS_FREQ_DEF);
 882
 883         dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u mdio_freq:%u\n",
 884                  readl(cpsw_common->ss_base),
 885                  readl(cpsw_common->cpsw_base),
 886                  readl(cpsw_common->ale_base),
 887                  cpsw_common->port_num,
 888                  cpsw_common->bus_freq);
 889
 890 out:
 891         clk_free(&cpsw_common->fclk);
 892         power_domain_free(&cpsw_common->pwrdmn);
 893         return ret;
 894 }
 895
 896 static const struct udevice_id am65_cpsw_nuss_ids[] = {
 897         { .compatible = "ti,am654-cpsw-nuss" },
 898         { .compatible = "ti,j721e-cpsw-nuss" },
 899         { .compatible = "ti,am642-cpsw-nuss" },
 900         { }
 901 };
 902
 903 U_BOOT_DRIVER(am65_cpsw_nuss) = {
 904         .name   = "am65_cpsw_nuss",
 905         .id     = UCLASS_MISC,
 906         .of_match = am65_cpsw_nuss_ids,
 907         .probe  = am65_cpsw_probe_nuss,
 908         .priv_auto = sizeof(struct am65_cpsw_common),
 909 };
 910
 911 U_BOOT_DRIVER(am65_cpsw_nuss_port) = {
 912         .name   = "am65_cpsw_nuss_port",
 913         .id     = UCLASS_ETH,
 914         .probe  = am65_cpsw_port_probe,
 915         .ops    = &am65_cpsw_ops,
 916         .priv_auto      = sizeof(struct am65_cpsw_priv),
 917         .plat_auto      = sizeof(struct eth_pdata),
 918         .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_OS_PREPARE,
 919 };
 920
 921 static const struct udevice_id am65_cpsw_mdio_ids[] = {
 922         { .compatible = "ti,cpsw-mdio" },
 923         { }
 924 };
 925
 926 U_BOOT_DRIVER(am65_cpsw_mdio) = {
 927         .name           = "am65_cpsw_mdio",
 928         .id             = UCLASS_MDIO,
 929         .of_match       = am65_cpsw_mdio_ids,
 930 };