1 // SPDX-License-Identifier: GPL-2.0+
3 * Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver
5 * Copyright (C) 2019, Texas Instruments, Incorporated
11 #include <asm/cache.h>
13 #include <asm/processor.h>
16 #include <dm/device_compat.h>
18 #include <dma-uclass.h>
19 #include <dm/of_access.h>
23 #include <power-domain.h>
24 #include <linux/bitops.h>
25 #include <linux/soc/ti/ti-udma.h>
27 #include "cpsw_mdio.h"
29 #define AM65_CPSW_CPSWNU_MAX_PORTS 2
31 #define AM65_CPSW_SS_BASE 0x0
32 #define AM65_CPSW_SGMII_BASE 0x100
33 #define AM65_CPSW_MDIO_BASE 0xf00
34 #define AM65_CPSW_XGMII_BASE 0x2100
35 #define AM65_CPSW_CPSW_NU_BASE 0x20000
36 #define AM65_CPSW_CPSW_NU_ALE_BASE 0x1e000
38 #define AM65_CPSW_CPSW_NU_PORTS_OFFSET 0x1000
39 #define AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET 0x330
41 #define AM65_CPSW_MDIO_BUS_FREQ_DEF 1000000
43 #define AM65_CPSW_CTL_REG 0x4
44 #define AM65_CPSW_STAT_PORT_EN_REG 0x14
45 #define AM65_CPSW_PTYPE_REG 0x18
47 #define AM65_CPSW_CTL_REG_P0_ENABLE BIT(2)
48 #define AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE BIT(13)
49 #define AM65_CPSW_CTL_REG_P0_RX_PAD BIT(14)
51 #define AM65_CPSW_P0_FLOW_ID_REG 0x8
52 #define AM65_CPSW_PN_RX_MAXLEN_REG 0x24
53 #define AM65_CPSW_PN_REG_SA_L 0x308
54 #define AM65_CPSW_PN_REG_SA_H 0x30c
56 #define AM65_CPSW_ALE_CTL_REG 0x8
57 #define AM65_CPSW_ALE_CTL_REG_ENABLE BIT(31)
58 #define AM65_CPSW_ALE_CTL_REG_RESET_TBL BIT(30)
59 #define AM65_CPSW_ALE_CTL_REG_BYPASS BIT(4)
60 #define AM65_CPSW_ALE_PN_CTL_REG(x) (0x40 + (x) * 4)
61 #define AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD 0x3
62 #define AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY BIT(11)
64 #define AM65_CPSW_ALE_THREADMAPDEF_REG 0x134
65 #define AM65_CPSW_ALE_DEFTHREAD_EN BIT(15)
67 #define AM65_CPSW_MACSL_CTL_REG 0x0
68 #define AM65_CPSW_MACSL_CTL_REG_IFCTL_A BIT(15)
69 #define AM65_CPSW_MACSL_CTL_EXT_EN BIT(18)
70 #define AM65_CPSW_MACSL_CTL_REG_GIG BIT(7)
71 #define AM65_CPSW_MACSL_CTL_REG_GMII_EN BIT(5)
72 #define AM65_CPSW_MACSL_CTL_REG_LOOPBACK BIT(1)
73 #define AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX BIT(0)
74 #define AM65_CPSW_MACSL_RESET_REG 0x8
75 #define AM65_CPSW_MACSL_RESET_REG_RESET BIT(0)
76 #define AM65_CPSW_MACSL_STATUS_REG 0x4
77 #define AM65_CPSW_MACSL_RESET_REG_PN_IDLE BIT(31)
78 #define AM65_CPSW_MACSL_RESET_REG_PN_E_IDLE BIT(30)
79 #define AM65_CPSW_MACSL_RESET_REG_PN_P_IDLE BIT(29)
80 #define AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE BIT(28)
81 #define AM65_CPSW_MACSL_RESET_REG_IDLE_MASK \
82 (AM65_CPSW_MACSL_RESET_REG_PN_IDLE | \
83 AM65_CPSW_MACSL_RESET_REG_PN_E_IDLE | \
84 AM65_CPSW_MACSL_RESET_REG_PN_P_IDLE | \
85 AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE)
87 #define AM65_CPSW_CPPI_PKT_TYPE 0x7
89 struct am65_cpsw_port {
91 fdt_addr_t macsl_base;
96 struct am65_cpsw_common {
100 fdt_addr_t mdio_base;
103 fdt_addr_t mac_efuse;
106 struct power_domain pwrdmn;
109 struct am65_cpsw_port ports[AM65_CPSW_CPSWNU_MAX_PORTS];
121 struct am65_cpsw_priv {
123 struct am65_cpsw_common *cpsw_common;
126 struct phy_device *phydev;
133 #define UDMA_RX_BUF_SIZE PKTSIZE_ALIGN
135 #define UDMA_RX_BUF_SIZE ALIGN(1522, ARCH_DMA_MINALIGN)
139 #define UDMA_RX_DESC_NUM PKTBUFSRX
141 #define UDMA_RX_DESC_NUM 4
144 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
145 ((mac)[2] << 16) | ((mac)[3] << 24))
146 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
148 static void am65_cpsw_set_sl_mac(struct am65_cpsw_port *slave,
152 slave->port_base + AM65_CPSW_PN_REG_SA_H);
154 slave->port_base + AM65_CPSW_PN_REG_SA_L);
157 int am65_cpsw_macsl_reset(struct am65_cpsw_port *slave)
161 /* Set the soft reset bit */
162 writel(AM65_CPSW_MACSL_RESET_REG_RESET,
163 slave->macsl_base + AM65_CPSW_MACSL_RESET_REG);
165 while ((readl(slave->macsl_base + AM65_CPSW_MACSL_RESET_REG) &
166 AM65_CPSW_MACSL_RESET_REG_RESET) && i--)
169 /* Timeout on the reset */
173 static int am65_cpsw_macsl_wait_for_idle(struct am65_cpsw_port *slave)
177 while ((readl(slave->macsl_base + AM65_CPSW_MACSL_STATUS_REG) &
178 AM65_CPSW_MACSL_RESET_REG_IDLE_MASK) && i--)
184 static int am65_cpsw_update_link(struct am65_cpsw_priv *priv)
186 struct am65_cpsw_common *common = priv->cpsw_common;
187 struct am65_cpsw_port *port = &common->ports[priv->port_id];
188 struct phy_device *phy = priv->phydev;
191 if (phy->link) { /* link up */
192 mac_control = /*AM65_CPSW_MACSL_CTL_REG_LOOPBACK |*/
193 AM65_CPSW_MACSL_CTL_REG_GMII_EN;
194 if (phy->speed == 1000)
195 mac_control |= AM65_CPSW_MACSL_CTL_REG_GIG;
196 if (phy->speed == 10 && phy_interface_is_rgmii(phy))
197 /* Can be used with in band mode only */
198 mac_control |= AM65_CPSW_MACSL_CTL_EXT_EN;
199 if (phy->duplex == DUPLEX_FULL)
200 mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX;
201 if (phy->speed == 100)
202 mac_control |= AM65_CPSW_MACSL_CTL_REG_IFCTL_A;
205 if (mac_control == port->mac_control)
209 printf("link up on port %d, speed %d, %s duplex\n",
210 priv->port_id, phy->speed,
211 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
213 printf("link down on port %d\n", priv->port_id);
216 writel(mac_control, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
217 port->mac_control = mac_control;
223 #define AM65_GMII_SEL_MODE_MII 0
224 #define AM65_GMII_SEL_MODE_RMII 1
225 #define AM65_GMII_SEL_MODE_RGMII 2
227 #define AM65_GMII_SEL_RGMII_IDMODE BIT(4)
229 static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv,
230 phy_interface_t phy_mode, int slave)
232 struct am65_cpsw_common *common = priv->cpsw_common;
235 bool rgmii_id = false;
237 reg = readl(common->gmii_sel);
239 dev_dbg(common->dev, "old gmii_sel: %08x\n", reg);
242 case PHY_INTERFACE_MODE_RMII:
243 mode = AM65_GMII_SEL_MODE_RMII;
246 case PHY_INTERFACE_MODE_RGMII:
247 case PHY_INTERFACE_MODE_RGMII_RXID:
248 mode = AM65_GMII_SEL_MODE_RGMII;
251 case PHY_INTERFACE_MODE_RGMII_ID:
252 case PHY_INTERFACE_MODE_RGMII_TXID:
253 mode = AM65_GMII_SEL_MODE_RGMII;
258 dev_warn(common->dev,
259 "Unsupported PHY mode: %u. Defaulting to MII.\n",
262 case PHY_INTERFACE_MODE_MII:
263 mode = AM65_GMII_SEL_MODE_MII;
268 mode |= AM65_GMII_SEL_RGMII_IDMODE;
271 dev_dbg(common->dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n",
273 writel(reg, common->gmii_sel);
275 reg = readl(common->gmii_sel);
278 "gmii_sel PHY mode NOT SET!: requested: %08x, gmii_sel: %08x\n",
282 static int am65_cpsw_start(struct udevice *dev)
284 struct eth_pdata *pdata = dev_get_platdata(dev);
285 struct am65_cpsw_priv *priv = dev_get_priv(dev);
286 struct am65_cpsw_common *common = priv->cpsw_common;
287 struct am65_cpsw_port *port = &common->ports[priv->port_id];
288 struct am65_cpsw_port *port0 = &common->ports[0];
289 struct ti_udma_drv_chan_cfg_data *dma_rx_cfg_data;
292 ret = power_domain_on(&common->pwrdmn);
294 dev_err(dev, "power_domain_on() failed %d\n", ret);
298 ret = clk_enable(&common->fclk);
300 dev_err(dev, "clk enabled failed %d\n", ret);
306 ret = dma_get_by_name(common->dev, "tx0", &common->dma_tx);
308 dev_err(dev, "TX dma get failed %d\n", ret);
311 ret = dma_get_by_name(common->dev, "rx", &common->dma_rx);
313 dev_err(dev, "RX dma get failed %d\n", ret);
317 for (i = 0; i < UDMA_RX_DESC_NUM; i++) {
318 ret = dma_prepare_rcv_buf(&common->dma_rx,
322 dev_err(dev, "RX dma add buf failed %d\n", ret);
327 ret = dma_enable(&common->dma_tx);
329 dev_err(dev, "TX dma_enable failed %d\n", ret);
332 ret = dma_enable(&common->dma_rx);
334 dev_err(dev, "RX dma_enable failed %d\n", ret);
338 /* Control register */
339 writel(AM65_CPSW_CTL_REG_P0_ENABLE |
340 AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE |
341 AM65_CPSW_CTL_REG_P0_RX_PAD,
342 common->cpsw_base + AM65_CPSW_CTL_REG);
344 /* disable priority elevation */
345 writel(0, common->cpsw_base + AM65_CPSW_PTYPE_REG);
347 /* enable statistics */
348 writel(BIT(0) | BIT(priv->port_id),
349 common->cpsw_base + AM65_CPSW_STAT_PORT_EN_REG);
351 /* Port 0 length register */
352 writel(PKTSIZE_ALIGN, port0->port_base + AM65_CPSW_PN_RX_MAXLEN_REG);
354 /* set base flow_id */
355 dma_get_cfg(&common->dma_rx, 0, (void **)&dma_rx_cfg_data);
356 writel(dma_rx_cfg_data->flow_id_base,
357 port0->port_base + AM65_CPSW_P0_FLOW_ID_REG);
358 dev_info(dev, "K3 CPSW: rflow_id_base: %u\n",
359 dma_rx_cfg_data->flow_id_base);
361 /* Reset and enable the ALE */
362 writel(AM65_CPSW_ALE_CTL_REG_ENABLE | AM65_CPSW_ALE_CTL_REG_RESET_TBL |
363 AM65_CPSW_ALE_CTL_REG_BYPASS,
364 common->ale_base + AM65_CPSW_ALE_CTL_REG);
366 /* port 0 put into forward mode */
367 writel(AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD,
368 common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
370 writel(AM65_CPSW_ALE_DEFTHREAD_EN,
371 common->ale_base + AM65_CPSW_ALE_THREADMAPDEF_REG);
373 /* PORT x configuration */
375 /* Port x Max length register */
376 writel(PKTSIZE_ALIGN, port->port_base + AM65_CPSW_PN_RX_MAXLEN_REG);
379 am65_cpsw_set_sl_mac(port, pdata->enetaddr);
381 /* Port x ALE: mac_only, Forwarding */
382 writel(AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY |
383 AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD,
384 common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
386 port->mac_control = 0;
387 if (!am65_cpsw_macsl_reset(port)) {
388 dev_err(dev, "mac_sl reset failed\n");
393 ret = phy_startup(priv->phydev);
395 dev_err(dev, "phy_startup failed\n");
399 ret = am65_cpsw_update_link(priv);
402 goto err_phy_shutdown;
405 common->started = true;
410 phy_shutdown(priv->phydev);
413 writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
414 writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
415 if (!am65_cpsw_macsl_wait_for_idle(port))
416 dev_err(dev, "mac_sl idle timeout\n");
417 writel(0, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
418 writel(0, common->ale_base + AM65_CPSW_ALE_CTL_REG);
419 writel(0, common->cpsw_base + AM65_CPSW_CTL_REG);
421 dma_disable(&common->dma_rx);
423 dma_disable(&common->dma_tx);
425 dma_free(&common->dma_rx);
427 dma_free(&common->dma_tx);
429 clk_disable(&common->fclk);
431 power_domain_off(&common->pwrdmn);
433 dev_err(dev, "%s end error\n", __func__);
438 static int am65_cpsw_send(struct udevice *dev, void *packet, int length)
440 struct am65_cpsw_priv *priv = dev_get_priv(dev);
441 struct am65_cpsw_common *common = priv->cpsw_common;
442 struct ti_udma_drv_packet_data packet_data;
445 packet_data.pkt_type = AM65_CPSW_CPPI_PKT_TYPE;
446 packet_data.dest_tag = priv->port_id;
447 ret = dma_send(&common->dma_tx, packet, length, &packet_data);
449 dev_err(dev, "TX dma_send failed %d\n", ret);
456 static int am65_cpsw_recv(struct udevice *dev, int flags, uchar **packetp)
458 struct am65_cpsw_priv *priv = dev_get_priv(dev);
459 struct am65_cpsw_common *common = priv->cpsw_common;
461 /* try to receive a new packet */
462 return dma_receive(&common->dma_rx, (void **)packetp, NULL);
465 static int am65_cpsw_free_pkt(struct udevice *dev, uchar *packet, int length)
467 struct am65_cpsw_priv *priv = dev_get_priv(dev);
468 struct am65_cpsw_common *common = priv->cpsw_common;
472 u32 pkt = common->rx_next % UDMA_RX_DESC_NUM;
474 ret = dma_prepare_rcv_buf(&common->dma_rx,
478 dev_err(dev, "RX dma free_pkt failed %d\n", ret);
485 static void am65_cpsw_stop(struct udevice *dev)
487 struct am65_cpsw_priv *priv = dev_get_priv(dev);
488 struct am65_cpsw_common *common = priv->cpsw_common;
489 struct am65_cpsw_port *port = &common->ports[priv->port_id];
491 if (!common->started)
494 phy_shutdown(priv->phydev);
496 writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
497 writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
498 if (!am65_cpsw_macsl_wait_for_idle(port))
499 dev_err(dev, "mac_sl idle timeout\n");
500 writel(0, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
501 writel(0, common->ale_base + AM65_CPSW_ALE_CTL_REG);
502 writel(0, common->cpsw_base + AM65_CPSW_CTL_REG);
504 dma_disable(&common->dma_tx);
505 dma_free(&common->dma_tx);
507 dma_disable(&common->dma_rx);
508 dma_free(&common->dma_rx);
510 common->started = false;
513 static int am65_cpsw_read_rom_hwaddr(struct udevice *dev)
515 struct am65_cpsw_priv *priv = dev_get_priv(dev);
516 struct am65_cpsw_common *common = priv->cpsw_common;
517 struct eth_pdata *pdata = dev_get_platdata(dev);
520 if (common->mac_efuse == FDT_ADDR_T_NONE)
523 mac_lo = readl(common->mac_efuse);
524 mac_hi = readl(common->mac_efuse + 4);
525 pdata->enetaddr[0] = (mac_hi >> 8) & 0xff;
526 pdata->enetaddr[1] = mac_hi & 0xff;
527 pdata->enetaddr[2] = (mac_lo >> 24) & 0xff;
528 pdata->enetaddr[3] = (mac_lo >> 16) & 0xff;
529 pdata->enetaddr[4] = (mac_lo >> 8) & 0xff;
530 pdata->enetaddr[5] = mac_lo & 0xff;
535 static const struct eth_ops am65_cpsw_ops = {
536 .start = am65_cpsw_start,
537 .send = am65_cpsw_send,
538 .recv = am65_cpsw_recv,
539 .free_pkt = am65_cpsw_free_pkt,
540 .stop = am65_cpsw_stop,
541 .read_rom_hwaddr = am65_cpsw_read_rom_hwaddr,
544 static int am65_cpsw_mdio_init(struct udevice *dev)
546 struct am65_cpsw_priv *priv = dev_get_priv(dev);
547 struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
549 if (!priv->has_phy || cpsw_common->bus)
552 cpsw_common->bus = cpsw_mdio_init(dev->name,
553 cpsw_common->mdio_base,
554 cpsw_common->bus_freq,
555 clk_get_rate(&cpsw_common->fclk));
556 if (!cpsw_common->bus)
562 static int am65_cpsw_phy_init(struct udevice *dev)
564 struct am65_cpsw_priv *priv = dev_get_priv(dev);
565 struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
566 struct eth_pdata *pdata = dev_get_platdata(dev);
567 struct phy_device *phydev;
568 u32 supported = PHY_GBIT_FEATURES;
571 phydev = phy_connect(cpsw_common->bus,
574 pdata->phy_interface);
577 dev_err(dev, "phy_connect() failed\n");
581 phydev->supported &= supported;
582 if (pdata->max_speed) {
583 ret = phy_set_supported(phydev, pdata->max_speed);
587 phydev->advertising = phydev->supported;
589 if (ofnode_valid(priv->phy_node))
590 phydev->node = priv->phy_node;
592 priv->phydev = phydev;
593 ret = phy_config(phydev);
595 pr_err("phy_config() failed: %d", ret);
600 static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np)
602 struct eth_pdata *pdata = dev_get_platdata(dev);
603 struct am65_cpsw_priv *priv = dev_get_priv(dev);
604 struct ofnode_phandle_args out_args;
605 const char *phy_mode;
608 phy_mode = ofnode_read_string(port_np, "phy-mode");
610 pdata->phy_interface =
611 phy_get_interface_by_name(phy_mode);
612 if (pdata->phy_interface == -1) {
613 dev_err(dev, "Invalid PHY mode '%s', port %u\n",
614 phy_mode, priv->port_id);
620 ofnode_read_u32(port_np, "max-speed", (u32 *)&pdata->max_speed);
621 if (pdata->max_speed)
622 dev_err(dev, "Port %u speed froced to %uMbit\n",
623 priv->port_id, pdata->max_speed);
625 priv->has_phy = true;
626 ret = ofnode_parse_phandle_with_args(port_np, "phy-handle",
627 NULL, 0, 0, &out_args);
629 dev_err(dev, "can't parse phy-handle port %u (%d)\n",
631 priv->has_phy = false;
635 priv->phy_node = out_args.node;
637 ret = ofnode_read_u32(priv->phy_node, "reg", &priv->phy_addr);
639 dev_err(dev, "failed to get phy_addr port %u (%d)\n",
649 static int am65_cpsw_probe_cpsw(struct udevice *dev)
651 struct am65_cpsw_priv *priv = dev_get_priv(dev);
652 struct eth_pdata *pdata = dev_get_platdata(dev);
653 struct am65_cpsw_common *cpsw_common;
654 ofnode ports_np, node;
659 cpsw_common = calloc(1, sizeof(*priv->cpsw_common));
662 priv->cpsw_common = cpsw_common;
664 cpsw_common->dev = dev;
665 cpsw_common->ss_base = dev_read_addr(dev);
666 if (cpsw_common->ss_base == FDT_ADDR_T_NONE)
668 cpsw_common->mac_efuse = devfdt_get_addr_name(dev, "mac_efuse");
669 /* no err check - optional */
671 ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0);
673 dev_err(dev, "failed to get pwrdmn: %d\n", ret);
677 ret = clk_get_by_name(dev, "fck", &cpsw_common->fclk);
679 power_domain_free(&cpsw_common->pwrdmn);
680 dev_err(dev, "failed to get clock %d\n", ret);
684 cpsw_common->cpsw_base = cpsw_common->ss_base + AM65_CPSW_CPSW_NU_BASE;
685 cpsw_common->ale_base = cpsw_common->cpsw_base +
686 AM65_CPSW_CPSW_NU_ALE_BASE;
687 cpsw_common->mdio_base = cpsw_common->ss_base + AM65_CPSW_MDIO_BASE;
689 ports_np = dev_read_subnode(dev, "ethernet-ports");
690 if (!ofnode_valid(ports_np)) {
695 ofnode_for_each_subnode(node, ports_np) {
696 const char *node_name;
700 node_name = ofnode_get_name(node);
702 disabled = !ofnode_is_available(node);
704 ret = ofnode_read_u32(node, "reg", &port_id);
706 dev_err(dev, "%s: failed to get port_id (%d)\n",
711 if (port_id >= AM65_CPSW_CPSWNU_MAX_PORTS) {
712 dev_err(dev, "%s: invalid port_id (%d)\n",
717 cpsw_common->port_num++;
722 priv->port_id = port_id;
723 cpsw_common->ports[port_id].disabled = disabled;
727 ret = am65_cpsw_ofdata_parse_phy(dev, node);
732 for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) {
733 struct am65_cpsw_port *port = &cpsw_common->ports[i];
735 port->port_base = cpsw_common->cpsw_base +
736 AM65_CPSW_CPSW_NU_PORTS_OFFSET +
737 (i * AM65_CPSW_CPSW_NU_PORTS_OFFSET);
738 port->macsl_base = port->port_base +
739 AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET;
742 node = dev_read_subnode(dev, "cpsw-phy-sel");
743 if (!ofnode_valid(node)) {
744 dev_err(dev, "can't find cpsw-phy-sel\n");
749 cpsw_common->gmii_sel = ofnode_get_addr(node);
750 if (cpsw_common->gmii_sel == FDT_ADDR_T_NONE) {
751 dev_err(dev, "failed to get gmii_sel base\n");
755 cpsw_common->bus_freq =
756 dev_read_u32_default(dev, "bus_freq",
757 AM65_CPSW_MDIO_BUS_FREQ_DEF);
759 am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id);
761 ret = am65_cpsw_mdio_init(dev);
765 ret = am65_cpsw_phy_init(dev);
769 dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u mdio_freq:%u\n",
770 readl(cpsw_common->ss_base),
771 readl(cpsw_common->cpsw_base),
772 readl(cpsw_common->ale_base),
773 cpsw_common->port_num,
774 cpsw_common->bus_freq);
777 clk_free(&cpsw_common->fclk);
778 power_domain_free(&cpsw_common->pwrdmn);
782 static const struct udevice_id am65_cpsw_nuss_ids[] = {
783 { .compatible = "ti,am654-cpsw-nuss" },
784 { .compatible = "ti,j721e-cpsw-nuss" },
788 U_BOOT_DRIVER(am65_cpsw_nuss_slave) = {
789 .name = "am65_cpsw_nuss_slave",
791 .of_match = am65_cpsw_nuss_ids,
792 .probe = am65_cpsw_probe_cpsw,
793 .ops = &am65_cpsw_ops,
794 .priv_auto_alloc_size = sizeof(struct am65_cpsw_priv),
795 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
796 .flags = DM_FLAG_ALLOC_PRIV_DMA,