drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2011 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mdio.h>
  36 #include <linux/mii.h>
  37 #include <linux/phy.h>
  38 #include <linux/brcmphy.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/ip.h>
  41 #include <linux/tcp.h>
  42 #include <linux/workqueue.h>
  43 #include <linux/prefetch.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/firmware.h>
  46
  47 #include <net/checksum.h>
  48 #include <net/ip.h>
  49
  50 #include <asm/system.h>
  51 #include <linux/io.h>
  52 #include <asm/byteorder.h>
  53 #include <linux/uaccess.h>
  54
  55 #ifdef CONFIG_SPARC
  56 #include <asm/idprom.h>
  57 #include <asm/prom.h>
  58 #endif
  59
  60 #define BAR_0   0
  61 #define BAR_2   2
  62
  63 #include "tg3.h"
  64
  65 #define DRV_MODULE_NAME         "tg3"
  66 #define TG3_MAJ_NUM                     3
  67 #define TG3_MIN_NUM                     117
  68 #define DRV_MODULE_VERSION      \
  69         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  70 #define DRV_MODULE_RELDATE      "January 25, 2011"
  71
  72 #define TG3_DEF_MAC_MODE        0
  73 #define TG3_DEF_RX_MODE         0
  74 #define TG3_DEF_TX_MODE         0
  75 #define TG3_DEF_MSG_ENABLE        \
  76         (NETIF_MSG_DRV          | \
  77          NETIF_MSG_PROBE        | \
  78          NETIF_MSG_LINK         | \
  79          NETIF_MSG_TIMER        | \
  80          NETIF_MSG_IFDOWN       | \
  81          NETIF_MSG_IFUP         | \
  82          NETIF_MSG_RX_ERR       | \
  83          NETIF_MSG_TX_ERR)
  84
  85 /* length of time before we decide the hardware is borked,
  86  * and dev->tx_timeout() should be called to fix the problem
  87  */
  88 #define TG3_TX_TIMEOUT                  (5 * HZ)
  89
  90 /* hardware minimum and maximum for a single frame's data payload */
  91 #define TG3_MIN_MTU                     60
  92 #define TG3_MAX_MTU(tp) \
  93         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  94
  95 /* These numbers seem to be hard coded in the NIC firmware somehow.
  96  * You can't change the ring sizes, but you can change where you place
  97  * them in the NIC onboard memory.
  98  */
  99 #define TG3_RX_STD_RING_SIZE(tp) \
 100         ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
 101          TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JMB_RING_SIZE(tp) \
 104         ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
 105          TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
 106 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 107 #define TG3_RSS_INDIR_TBL_SIZE          128
 108
 109 /* Do not place this n-ring entries value into the tp struct itself,
 110  * we really want to expose these constants to GCC so that modulo et
 111  * al.  operations are done with shifts and masks instead of with
 112  * hw multiply/modulo instructions.  Another solution would be to
 113  * replace things like '% foo' with '& (foo - 1)'.
 114  */
 115
 116 #define TG3_TX_RING_SIZE                512
 117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 118
 119 #define TG3_RX_STD_RING_BYTES(tp) \
 120         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
 121 #define TG3_RX_JMB_RING_BYTES(tp) \
 122         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
 123 #define TG3_RX_RCB_RING_BYTES(tp) \
 124         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
 125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 126                                  TG3_TX_RING_SIZE)
 127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 128
 129 #define TG3_DMA_BYTE_ENAB               64
 130
 131 #define TG3_RX_STD_DMA_SZ               1536
 132 #define TG3_RX_JMB_DMA_SZ               9046
 133
 134 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 135
 136 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 137 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 138
 139 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
 140         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
 141
 142 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
 143         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
 144
 145 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 146  * that are at least dword aligned when used in PCIX mode.  The driver
 147  * works around this bug by double copying the packet.  This workaround
 148  * is built into the normal double copy length check for efficiency.
 149  *
 150  * However, the double copy is only necessary on those architectures
 151  * where unaligned memory accesses are inefficient.  For those architectures
 152  * where unaligned memory accesses incur little penalty, we can reintegrate
 153  * the 5701 in the normal rx path.  Doing so saves a device structure
 154  * dereference by hardcoding the double copy threshold in place.
 155  */
 156 #define TG3_RX_COPY_THRESHOLD           256
 157 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 158         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 159 #else
 160         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 161 #endif
 162
 163 /* minimum number of free TX descriptors required to wake up TX process */
 164 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 165
 166 #define TG3_RAW_IP_ALIGN 2
 167
 168 /* number of ETHTOOL_GSTATS u64's */
 169 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 170
 171 #define TG3_NUM_TEST            6
 172
 173 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 174
 175 #define FIRMWARE_TG3            "tigon/tg3.bin"
 176 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 177 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 178
 179 static char version[] __devinitdata =
 180         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 181
 182 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 183 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 184 MODULE_LICENSE("GPL");
 185 MODULE_VERSION(DRV_MODULE_VERSION);
 186 MODULE_FIRMWARE(FIRMWARE_TG3);
 187 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 188 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 189
 190 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 191 module_param(tg3_debug, int, 0);
 192 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 193
 194 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 275         {}
 276 };
 277
 278 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 279
 280 static const struct {
 281         const char string[ETH_GSTRING_LEN];
 282 } ethtool_stats_keys[TG3_NUM_STATS] = {
 283         { "rx_octets" },
 284         { "rx_fragments" },
 285         { "rx_ucast_packets" },
 286         { "rx_mcast_packets" },
 287         { "rx_bcast_packets" },
 288         { "rx_fcs_errors" },
 289         { "rx_align_errors" },
 290         { "rx_xon_pause_rcvd" },
 291         { "rx_xoff_pause_rcvd" },
 292         { "rx_mac_ctrl_rcvd" },
 293         { "rx_xoff_entered" },
 294         { "rx_frame_too_long_errors" },
 295         { "rx_jabbers" },
 296         { "rx_undersize_packets" },
 297         { "rx_in_length_errors" },
 298         { "rx_out_length_errors" },
 299         { "rx_64_or_less_octet_packets" },
 300         { "rx_65_to_127_octet_packets" },
 301         { "rx_128_to_255_octet_packets" },
 302         { "rx_256_to_511_octet_packets" },
 303         { "rx_512_to_1023_octet_packets" },
 304         { "rx_1024_to_1522_octet_packets" },
 305         { "rx_1523_to_2047_octet_packets" },
 306         { "rx_2048_to_4095_octet_packets" },
 307         { "rx_4096_to_8191_octet_packets" },
 308         { "rx_8192_to_9022_octet_packets" },
 309
 310         { "tx_octets" },
 311         { "tx_collisions" },
 312
 313         { "tx_xon_sent" },
 314         { "tx_xoff_sent" },
 315         { "tx_flow_control" },
 316         { "tx_mac_errors" },
 317         { "tx_single_collisions" },
 318         { "tx_mult_collisions" },
 319         { "tx_deferred" },
 320         { "tx_excessive_collisions" },
 321         { "tx_late_collisions" },
 322         { "tx_collide_2times" },
 323         { "tx_collide_3times" },
 324         { "tx_collide_4times" },
 325         { "tx_collide_5times" },
 326         { "tx_collide_6times" },
 327         { "tx_collide_7times" },
 328         { "tx_collide_8times" },
 329         { "tx_collide_9times" },
 330         { "tx_collide_10times" },
 331         { "tx_collide_11times" },
 332         { "tx_collide_12times" },
 333         { "tx_collide_13times" },
 334         { "tx_collide_14times" },
 335         { "tx_collide_15times" },
 336         { "tx_ucast_packets" },
 337         { "tx_mcast_packets" },
 338         { "tx_bcast_packets" },
 339         { "tx_carrier_sense_errors" },
 340         { "tx_discards" },
 341         { "tx_errors" },
 342
 343         { "dma_writeq_full" },
 344         { "dma_write_prioq_full" },
 345         { "rxbds_empty" },
 346         { "rx_discards" },
 347         { "rx_errors" },
 348         { "rx_threshold_hit" },
 349
 350         { "dma_readq_full" },
 351         { "dma_read_prioq_full" },
 352         { "tx_comp_queue_full" },
 353
 354         { "ring_set_send_prod_index" },
 355         { "ring_status_update" },
 356         { "nic_irqs" },
 357         { "nic_avoided_irqs" },
 358         { "nic_tx_threshold_hit" }
 359 };
 360
 361 static const struct {
 362         const char string[ETH_GSTRING_LEN];
 363 } ethtool_test_keys[TG3_NUM_TEST] = {
 364         { "nvram test     (online) " },
 365         { "link test      (online) " },
 366         { "register test  (offline)" },
 367         { "memory test    (offline)" },
 368         { "loopback test  (offline)" },
 369         { "interrupt test (offline)" },
 370 };
 371
 372 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 373 {
 374         writel(val, tp->regs + off);
 375 }
 376
 377 static u32 tg3_read32(struct tg3 *tp, u32 off)
 378 {
 379         return readl(tp->regs + off);
 380 }
 381
 382 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 383 {
 384         writel(val, tp->aperegs + off);
 385 }
 386
 387 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 388 {
 389         return readl(tp->aperegs + off);
 390 }
 391
 392 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 393 {
 394         unsigned long flags;
 395
 396         spin_lock_irqsave(&tp->indirect_lock, flags);
 397         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 398         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 399         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 400 }
 401
 402 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 403 {
 404         writel(val, tp->regs + off);
 405         readl(tp->regs + off);
 406 }
 407
 408 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 409 {
 410         unsigned long flags;
 411         u32 val;
 412
 413         spin_lock_irqsave(&tp->indirect_lock, flags);
 414         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 415         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 416         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 417         return val;
 418 }
 419
 420 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 421 {
 422         unsigned long flags;
 423
 424         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 425                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 426                                        TG3_64BIT_REG_LOW, val);
 427                 return;
 428         }
 429         if (off == TG3_RX_STD_PROD_IDX_REG) {
 430                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 431                                        TG3_64BIT_REG_LOW, val);
 432                 return;
 433         }
 434
 435         spin_lock_irqsave(&tp->indirect_lock, flags);
 436         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 437         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 438         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 439
 440         /* In indirect mode when disabling interrupts, we also need
 441          * to clear the interrupt bit in the GRC local ctrl register.
 442          */
 443         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 444             (val == 0x1)) {
 445                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 446                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 447         }
 448 }
 449
 450 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 451 {
 452         unsigned long flags;
 453         u32 val;
 454
 455         spin_lock_irqsave(&tp->indirect_lock, flags);
 456         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 457         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 458         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 459         return val;
 460 }
 461
 462 /* usec_wait specifies the wait time in usec when writing to certain registers
 463  * where it is unsafe to read back the register without some delay.
 464  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 465  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 466  */
 467 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 468 {
 469         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 470             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 471                 /* Non-posted methods */
 472                 tp->write32(tp, off, val);
 473         else {
 474                 /* Posted method */
 475                 tg3_write32(tp, off, val);
 476                 if (usec_wait)
 477                         udelay(usec_wait);
 478                 tp->read32(tp, off);
 479         }
 480         /* Wait again after the read for the posted method to guarantee that
 481          * the wait time is met.
 482          */
 483         if (usec_wait)
 484                 udelay(usec_wait);
 485 }
 486
 487 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 488 {
 489         tp->write32_mbox(tp, off, val);
 490         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 491             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 492                 tp->read32_mbox(tp, off);
 493 }
 494
 495 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 496 {
 497         void __iomem *mbox = tp->regs + off;
 498         writel(val, mbox);
 499         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 500                 writel(val, mbox);
 501         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 502                 readl(mbox);
 503 }
 504
 505 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 506 {
 507         return readl(tp->regs + off + GRCMBOX_BASE);
 508 }
 509
 510 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 511 {
 512         writel(val, tp->regs + off + GRCMBOX_BASE);
 513 }
 514
 515 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 516 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 517 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 518 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 519 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 520
 521 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 522 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 523 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 524 #define tr32(reg)                       tp->read32(tp, reg)
 525
 526 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 527 {
 528         unsigned long flags;
 529
 530         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 531             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 532                 return;
 533
 534         spin_lock_irqsave(&tp->indirect_lock, flags);
 535         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 536                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 538
 539                 /* Always leave this as zero. */
 540                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 541         } else {
 542                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 543                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 544
 545                 /* Always leave this as zero. */
 546                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 547         }
 548         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 549 }
 550
 551 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 552 {
 553         unsigned long flags;
 554
 555         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 556             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 557                 *val = 0;
 558                 return;
 559         }
 560
 561         spin_lock_irqsave(&tp->indirect_lock, flags);
 562         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 563                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 564                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 565
 566                 /* Always leave this as zero. */
 567                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 568         } else {
 569                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 570                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 571
 572                 /* Always leave this as zero. */
 573                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 574         }
 575         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 576 }
 577
 578 static void tg3_ape_lock_init(struct tg3 *tp)
 579 {
 580         int i;
 581         u32 regbase;
 582
 583         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 584                 regbase = TG3_APE_LOCK_GRANT;
 585         else
 586                 regbase = TG3_APE_PER_LOCK_GRANT;
 587
 588         /* Make sure the driver hasn't any stale locks. */
 589         for (i = 0; i < 8; i++)
 590                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 591 }
 592
 593 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 594 {
 595         int i, off;
 596         int ret = 0;
 597         u32 status, req, gnt;
 598
 599         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 600                 return 0;
 601
 602         switch (locknum) {
 603         case TG3_APE_LOCK_GRC:
 604         case TG3_APE_LOCK_MEM:
 605                 break;
 606         default:
 607                 return -EINVAL;
 608         }
 609
 610         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 611                 req = TG3_APE_LOCK_REQ;
 612                 gnt = TG3_APE_LOCK_GRANT;
 613         } else {
 614                 req = TG3_APE_PER_LOCK_REQ;
 615                 gnt = TG3_APE_PER_LOCK_GRANT;
 616         }
 617
 618         off = 4 * locknum;
 619
 620         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 621
 622         /* Wait for up to 1 millisecond to acquire lock. */
 623         for (i = 0; i < 100; i++) {
 624                 status = tg3_ape_read32(tp, gnt + off);
 625                 if (status == APE_LOCK_GRANT_DRIVER)
 626                         break;
 627                 udelay(10);
 628         }
 629
 630         if (status != APE_LOCK_GRANT_DRIVER) {
 631                 /* Revoke the lock request. */
 632                 tg3_ape_write32(tp, gnt + off,
 633                                 APE_LOCK_GRANT_DRIVER);
 634
 635                 ret = -EBUSY;
 636         }
 637
 638         return ret;
 639 }
 640
 641 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 642 {
 643         u32 gnt;
 644
 645         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 646                 return;
 647
 648         switch (locknum) {
 649         case TG3_APE_LOCK_GRC:
 650         case TG3_APE_LOCK_MEM:
 651                 break;
 652         default:
 653                 return;
 654         }
 655
 656         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 657                 gnt = TG3_APE_LOCK_GRANT;
 658         else
 659                 gnt = TG3_APE_PER_LOCK_GRANT;
 660
 661         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 662 }
 663
 664 static void tg3_disable_ints(struct tg3 *tp)
 665 {
 666         int i;
 667
 668         tw32(TG3PCI_MISC_HOST_CTRL,
 669              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 670         for (i = 0; i < tp->irq_max; i++)
 671                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 672 }
 673
 674 static void tg3_enable_ints(struct tg3 *tp)
 675 {
 676         int i;
 677
 678         tp->irq_sync = 0;
 679         wmb();
 680
 681         tw32(TG3PCI_MISC_HOST_CTRL,
 682              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 683
 684         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 685         for (i = 0; i < tp->irq_cnt; i++) {
 686                 struct tg3_napi *tnapi = &tp->napi[i];
 687
 688                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 689                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 690                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 691
 692                 tp->coal_now |= tnapi->coal_now;
 693         }
 694
 695         /* Force an initial interrupt */
 696         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 697             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 698                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 699         else
 700                 tw32(HOSTCC_MODE, tp->coal_now);
 701
 702         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 703 }
 704
 705 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 706 {
 707         struct tg3 *tp = tnapi->tp;
 708         struct tg3_hw_status *sblk = tnapi->hw_status;
 709         unsigned int work_exists = 0;
 710
 711         /* check for phy events */
 712         if (!(tp->tg3_flags &
 713               (TG3_FLAG_USE_LINKCHG_REG |
 714                TG3_FLAG_POLL_SERDES))) {
 715                 if (sblk->status & SD_STATUS_LINK_CHG)
 716                         work_exists = 1;
 717         }
 718         /* check for RX/TX work to do */
 719         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 720             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 721                 work_exists = 1;
 722
 723         return work_exists;
 724 }
 725
 726 /* tg3_int_reenable
 727  *  similar to tg3_enable_ints, but it accurately determines whether there
 728  *  is new work pending and can return without flushing the PIO write
 729  *  which reenables interrupts
 730  */
 731 static void tg3_int_reenable(struct tg3_napi *tnapi)
 732 {
 733         struct tg3 *tp = tnapi->tp;
 734
 735         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 736         mmiowb();
 737
 738         /* When doing tagged status, this work check is unnecessary.
 739          * The last_tag we write above tells the chip which piece of
 740          * work we've completed.
 741          */
 742         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 743             tg3_has_work(tnapi))
 744                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 745                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 746 }
 747
 748 static void tg3_switch_clocks(struct tg3 *tp)
 749 {
 750         u32 clock_ctrl;
 751         u32 orig_clock_ctrl;
 752
 753         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 754             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 755                 return;
 756
 757         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 758
 759         orig_clock_ctrl = clock_ctrl;
 760         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 761                        CLOCK_CTRL_CLKRUN_OENABLE |
 762                        0x1f);
 763         tp->pci_clock_ctrl = clock_ctrl;
 764
 765         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 766                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 767                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 768                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 769                 }
 770         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 771                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 772                             clock_ctrl |
 773                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 774                             40);
 775                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 776                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 777                             40);
 778         }
 779         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 780 }
 781
 782 #define PHY_BUSY_LOOPS  5000
 783
 784 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 785 {
 786         u32 frame_val;
 787         unsigned int loops;
 788         int ret;
 789
 790         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 791                 tw32_f(MAC_MI_MODE,
 792                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 793                 udelay(80);
 794         }
 795
 796         *val = 0x0;
 797
 798         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 799                       MI_COM_PHY_ADDR_MASK);
 800         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 801                       MI_COM_REG_ADDR_MASK);
 802         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 803
 804         tw32_f(MAC_MI_COM, frame_val);
 805
 806         loops = PHY_BUSY_LOOPS;
 807         while (loops != 0) {
 808                 udelay(10);
 809                 frame_val = tr32(MAC_MI_COM);
 810
 811                 if ((frame_val & MI_COM_BUSY) == 0) {
 812                         udelay(5);
 813                         frame_val = tr32(MAC_MI_COM);
 814                         break;
 815                 }
 816                 loops -= 1;
 817         }
 818
 819         ret = -EBUSY;
 820         if (loops != 0) {
 821                 *val = frame_val & MI_COM_DATA_MASK;
 822                 ret = 0;
 823         }
 824
 825         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 826                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 827                 udelay(80);
 828         }
 829
 830         return ret;
 831 }
 832
 833 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 834 {
 835         u32 frame_val;
 836         unsigned int loops;
 837         int ret;
 838
 839         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 840             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 841                 return 0;
 842
 843         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 844                 tw32_f(MAC_MI_MODE,
 845                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 846                 udelay(80);
 847         }
 848
 849         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 850                       MI_COM_PHY_ADDR_MASK);
 851         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 852                       MI_COM_REG_ADDR_MASK);
 853         frame_val |= (val & MI_COM_DATA_MASK);
 854         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 855
 856         tw32_f(MAC_MI_COM, frame_val);
 857
 858         loops = PHY_BUSY_LOOPS;
 859         while (loops != 0) {
 860                 udelay(10);
 861                 frame_val = tr32(MAC_MI_COM);
 862                 if ((frame_val & MI_COM_BUSY) == 0) {
 863                         udelay(5);
 864                         frame_val = tr32(MAC_MI_COM);
 865                         break;
 866                 }
 867                 loops -= 1;
 868         }
 869
 870         ret = -EBUSY;
 871         if (loops != 0)
 872                 ret = 0;
 873
 874         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 875                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 876                 udelay(80);
 877         }
 878
 879         return ret;
 880 }
 881
 882 static int tg3_bmcr_reset(struct tg3 *tp)
 883 {
 884         u32 phy_control;
 885         int limit, err;
 886
 887         /* OK, reset it, and poll the BMCR_RESET bit until it
 888          * clears or we time out.
 889          */
 890         phy_control = BMCR_RESET;
 891         err = tg3_writephy(tp, MII_BMCR, phy_control);
 892         if (err != 0)
 893                 return -EBUSY;
 894
 895         limit = 5000;
 896         while (limit--) {
 897                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 898                 if (err != 0)
 899                         return -EBUSY;
 900
 901                 if ((phy_control & BMCR_RESET) == 0) {
 902                         udelay(40);
 903                         break;
 904                 }
 905                 udelay(10);
 906         }
 907         if (limit < 0)
 908                 return -EBUSY;
 909
 910         return 0;
 911 }
 912
 913 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 914 {
 915         struct tg3 *tp = bp->priv;
 916         u32 val;
 917
 918         spin_lock_bh(&tp->lock);
 919
 920         if (tg3_readphy(tp, reg, &val))
 921                 val = -EIO;
 922
 923         spin_unlock_bh(&tp->lock);
 924
 925         return val;
 926 }
 927
 928 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 929 {
 930         struct tg3 *tp = bp->priv;
 931         u32 ret = 0;
 932
 933         spin_lock_bh(&tp->lock);
 934
 935         if (tg3_writephy(tp, reg, val))
 936                 ret = -EIO;
 937
 938         spin_unlock_bh(&tp->lock);
 939
 940         return ret;
 941 }
 942
 943 static int tg3_mdio_reset(struct mii_bus *bp)
 944 {
 945         return 0;
 946 }
 947
 948 static void tg3_mdio_config_5785(struct tg3 *tp)
 949 {
 950         u32 val;
 951         struct phy_device *phydev;
 952
 953         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 954         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 955         case PHY_ID_BCM50610:
 956         case PHY_ID_BCM50610M:
 957                 val = MAC_PHYCFG2_50610_LED_MODES;
 958                 break;
 959         case PHY_ID_BCMAC131:
 960                 val = MAC_PHYCFG2_AC131_LED_MODES;
 961                 break;
 962         case PHY_ID_RTL8211C:
 963                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 964                 break;
 965         case PHY_ID_RTL8201E:
 966                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 967                 break;
 968         default:
 969                 return;
 970         }
 971
 972         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 973                 tw32(MAC_PHYCFG2, val);
 974
 975                 val = tr32(MAC_PHYCFG1);
 976                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 977                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 978                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 979                 tw32(MAC_PHYCFG1, val);
 980
 981                 return;
 982         }
 983
 984         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
 985                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 986                        MAC_PHYCFG2_FMODE_MASK_MASK |
 987                        MAC_PHYCFG2_GMODE_MASK_MASK |
 988                        MAC_PHYCFG2_ACT_MASK_MASK   |
 989                        MAC_PHYCFG2_QUAL_MASK_MASK |
 990                        MAC_PHYCFG2_INBAND_ENABLE;
 991
 992         tw32(MAC_PHYCFG2, val);
 993
 994         val = tr32(MAC_PHYCFG1);
 995         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 996                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 997         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
 998                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 999                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1000                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1001                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1002         }
1003         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1004                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1005         tw32(MAC_PHYCFG1, val);
1006
1007         val = tr32(MAC_EXT_RGMII_MODE);
1008         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1009                  MAC_RGMII_MODE_RX_QUALITY |
1010                  MAC_RGMII_MODE_RX_ACTIVITY |
1011                  MAC_RGMII_MODE_RX_ENG_DET |
1012                  MAC_RGMII_MODE_TX_ENABLE |
1013                  MAC_RGMII_MODE_TX_LOWPWR |
1014                  MAC_RGMII_MODE_TX_RESET);
1015         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1016                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1017                         val |= MAC_RGMII_MODE_RX_INT_B |
1018                                MAC_RGMII_MODE_RX_QUALITY |
1019                                MAC_RGMII_MODE_RX_ACTIVITY |
1020                                MAC_RGMII_MODE_RX_ENG_DET;
1021                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1022                         val |= MAC_RGMII_MODE_TX_ENABLE |
1023                                MAC_RGMII_MODE_TX_LOWPWR |
1024                                MAC_RGMII_MODE_TX_RESET;
1025         }
1026         tw32(MAC_EXT_RGMII_MODE, val);
1027 }
1028
1029 static void tg3_mdio_start(struct tg3 *tp)
1030 {
1031         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1032         tw32_f(MAC_MI_MODE, tp->mi_mode);
1033         udelay(80);
1034
1035         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1036             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1037                 tg3_mdio_config_5785(tp);
1038 }
1039
1040 static int tg3_mdio_init(struct tg3 *tp)
1041 {
1042         int i;
1043         u32 reg;
1044         struct phy_device *phydev;
1045
1046         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
1047                 u32 is_serdes;
1048
1049                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1050
1051                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1052                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1053                 else
1054                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1055                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1056                 if (is_serdes)
1057                         tp->phy_addr += 7;
1058         } else
1059                 tp->phy_addr = TG3_PHY_MII_ADDR;
1060
1061         tg3_mdio_start(tp);
1062
1063         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1064             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1065                 return 0;
1066
1067         tp->mdio_bus = mdiobus_alloc();
1068         if (tp->mdio_bus == NULL)
1069                 return -ENOMEM;
1070
1071         tp->mdio_bus->name     = "tg3 mdio bus";
1072         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1073                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1074         tp->mdio_bus->priv     = tp;
1075         tp->mdio_bus->parent   = &tp->pdev->dev;
1076         tp->mdio_bus->read     = &tg3_mdio_read;
1077         tp->mdio_bus->write    = &tg3_mdio_write;
1078         tp->mdio_bus->reset    = &tg3_mdio_reset;
1079         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1080         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1081
1082         for (i = 0; i < PHY_MAX_ADDR; i++)
1083                 tp->mdio_bus->irq[i] = PHY_POLL;
1084
1085         /* The bus registration will look for all the PHYs on the mdio bus.
1086          * Unfortunately, it does not ensure the PHY is powered up before
1087          * accessing the PHY ID registers.  A chip reset is the
1088          * quickest way to bring the device back to an operational state..
1089          */
1090         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1091                 tg3_bmcr_reset(tp);
1092
1093         i = mdiobus_register(tp->mdio_bus);
1094         if (i) {
1095                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1096                 mdiobus_free(tp->mdio_bus);
1097                 return i;
1098         }
1099
1100         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1101
1102         if (!phydev || !phydev->drv) {
1103                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1104                 mdiobus_unregister(tp->mdio_bus);
1105                 mdiobus_free(tp->mdio_bus);
1106                 return -ENODEV;
1107         }
1108
1109         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1110         case PHY_ID_BCM57780:
1111                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1112                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1113                 break;
1114         case PHY_ID_BCM50610:
1115         case PHY_ID_BCM50610M:
1116                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1117                                      PHY_BRCM_RX_REFCLK_UNUSED |
1118                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1119                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1120                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1121                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1122                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1123                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1124                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1125                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1126                 /* fallthru */
1127         case PHY_ID_RTL8211C:
1128                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1129                 break;
1130         case PHY_ID_RTL8201E:
1131         case PHY_ID_BCMAC131:
1132                 phydev->interface = PHY_INTERFACE_MODE_MII;
1133                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1134                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1135                 break;
1136         }
1137
1138         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1139
1140         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1141                 tg3_mdio_config_5785(tp);
1142
1143         return 0;
1144 }
1145
1146 static void tg3_mdio_fini(struct tg3 *tp)
1147 {
1148         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1149                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1150                 mdiobus_unregister(tp->mdio_bus);
1151                 mdiobus_free(tp->mdio_bus);
1152         }
1153 }
1154
1155 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1156 {
1157         int err;
1158
1159         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1160         if (err)
1161                 goto done;
1162
1163         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1164         if (err)
1165                 goto done;
1166
1167         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1168                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1169         if (err)
1170                 goto done;
1171
1172         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1173
1174 done:
1175         return err;
1176 }
1177
1178 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1179 {
1180         int err;
1181
1182         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1183         if (err)
1184                 goto done;
1185
1186         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1187         if (err)
1188                 goto done;
1189
1190         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1191                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1192         if (err)
1193                 goto done;
1194
1195         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1196
1197 done:
1198         return err;
1199 }
1200
1201 /* tp->lock is held. */
1202 static inline void tg3_generate_fw_event(struct tg3 *tp)
1203 {
1204         u32 val;
1205
1206         val = tr32(GRC_RX_CPU_EVENT);
1207         val |= GRC_RX_CPU_DRIVER_EVENT;
1208         tw32_f(GRC_RX_CPU_EVENT, val);
1209
1210         tp->last_event_jiffies = jiffies;
1211 }
1212
1213 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1214
1215 /* tp->lock is held. */
1216 static void tg3_wait_for_event_ack(struct tg3 *tp)
1217 {
1218         int i;
1219         unsigned int delay_cnt;
1220         long time_remain;
1221
1222         /* If enough time has passed, no wait is necessary. */
1223         time_remain = (long)(tp->last_event_jiffies + 1 +
1224                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1225                       (long)jiffies;
1226         if (time_remain < 0)
1227                 return;
1228
1229         /* Check if we can shorten the wait time. */
1230         delay_cnt = jiffies_to_usecs(time_remain);
1231         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1232                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1233         delay_cnt = (delay_cnt >> 3) + 1;
1234
1235         for (i = 0; i < delay_cnt; i++) {
1236                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1237                         break;
1238                 udelay(8);
1239         }
1240 }
1241
1242 /* tp->lock is held. */
1243 static void tg3_ump_link_report(struct tg3 *tp)
1244 {
1245         u32 reg;
1246         u32 val;
1247
1248         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1249             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1250                 return;
1251
1252         tg3_wait_for_event_ack(tp);
1253
1254         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1255
1256         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1257
1258         val = 0;
1259         if (!tg3_readphy(tp, MII_BMCR, &reg))
1260                 val = reg << 16;
1261         if (!tg3_readphy(tp, MII_BMSR, &reg))
1262                 val |= (reg & 0xffff);
1263         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1264
1265         val = 0;
1266         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1267                 val = reg << 16;
1268         if (!tg3_readphy(tp, MII_LPA, &reg))
1269                 val |= (reg & 0xffff);
1270         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1271
1272         val = 0;
1273         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1274                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1275                         val = reg << 16;
1276                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1277                         val |= (reg & 0xffff);
1278         }
1279         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1280
1281         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1282                 val = reg << 16;
1283         else
1284                 val = 0;
1285         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1286
1287         tg3_generate_fw_event(tp);
1288 }
1289
1290 static void tg3_link_report(struct tg3 *tp)
1291 {
1292         if (!netif_carrier_ok(tp->dev)) {
1293                 netif_info(tp, link, tp->dev, "Link is down\n");
1294                 tg3_ump_link_report(tp);
1295         } else if (netif_msg_link(tp)) {
1296                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1297                             (tp->link_config.active_speed == SPEED_1000 ?
1298                              1000 :
1299                              (tp->link_config.active_speed == SPEED_100 ?
1300                               100 : 10)),
1301                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1302                              "full" : "half"));
1303
1304                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1305                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1306                             "on" : "off",
1307                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1308                             "on" : "off");
1309                 tg3_ump_link_report(tp);
1310         }
1311 }
1312
1313 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1314 {
1315         u16 miireg;
1316
1317         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1318                 miireg = ADVERTISE_PAUSE_CAP;
1319         else if (flow_ctrl & FLOW_CTRL_TX)
1320                 miireg = ADVERTISE_PAUSE_ASYM;
1321         else if (flow_ctrl & FLOW_CTRL_RX)
1322                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1323         else
1324                 miireg = 0;
1325
1326         return miireg;
1327 }
1328
1329 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1330 {
1331         u16 miireg;
1332
1333         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1334                 miireg = ADVERTISE_1000XPAUSE;
1335         else if (flow_ctrl & FLOW_CTRL_TX)
1336                 miireg = ADVERTISE_1000XPSE_ASYM;
1337         else if (flow_ctrl & FLOW_CTRL_RX)
1338                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1339         else
1340                 miireg = 0;
1341
1342         return miireg;
1343 }
1344
1345 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1346 {
1347         u8 cap = 0;
1348
1349         if (lcladv & ADVERTISE_1000XPAUSE) {
1350                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1351                         if (rmtadv & LPA_1000XPAUSE)
1352                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1353                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1354                                 cap = FLOW_CTRL_RX;
1355                 } else {
1356                         if (rmtadv & LPA_1000XPAUSE)
1357                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1358                 }
1359         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1360                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1361                         cap = FLOW_CTRL_TX;
1362         }
1363
1364         return cap;
1365 }
1366
1367 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1368 {
1369         u8 autoneg;
1370         u8 flowctrl = 0;
1371         u32 old_rx_mode = tp->rx_mode;
1372         u32 old_tx_mode = tp->tx_mode;
1373
1374         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1375                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1376         else
1377                 autoneg = tp->link_config.autoneg;
1378
1379         if (autoneg == AUTONEG_ENABLE &&
1380             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1381                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1382                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1383                 else
1384                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1385         } else
1386                 flowctrl = tp->link_config.flowctrl;
1387
1388         tp->link_config.active_flowctrl = flowctrl;
1389
1390         if (flowctrl & FLOW_CTRL_RX)
1391                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1392         else
1393                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1394
1395         if (old_rx_mode != tp->rx_mode)
1396                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1397
1398         if (flowctrl & FLOW_CTRL_TX)
1399                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1400         else
1401                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1402
1403         if (old_tx_mode != tp->tx_mode)
1404                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1405 }
1406
1407 static void tg3_adjust_link(struct net_device *dev)
1408 {
1409         u8 oldflowctrl, linkmesg = 0;
1410         u32 mac_mode, lcl_adv, rmt_adv;
1411         struct tg3 *tp = netdev_priv(dev);
1412         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1413
1414         spin_lock_bh(&tp->lock);
1415
1416         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1417                                     MAC_MODE_HALF_DUPLEX);
1418
1419         oldflowctrl = tp->link_config.active_flowctrl;
1420
1421         if (phydev->link) {
1422                 lcl_adv = 0;
1423                 rmt_adv = 0;
1424
1425                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1426                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1427                 else if (phydev->speed == SPEED_1000 ||
1428                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1429                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1430                 else
1431                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1432
1433                 if (phydev->duplex == DUPLEX_HALF)
1434                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1435                 else {
1436                         lcl_adv = tg3_advert_flowctrl_1000T(
1437                                   tp->link_config.flowctrl);
1438
1439                         if (phydev->pause)
1440                                 rmt_adv = LPA_PAUSE_CAP;
1441                         if (phydev->asym_pause)
1442                                 rmt_adv |= LPA_PAUSE_ASYM;
1443                 }
1444
1445                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1446         } else
1447                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1448
1449         if (mac_mode != tp->mac_mode) {
1450                 tp->mac_mode = mac_mode;
1451                 tw32_f(MAC_MODE, tp->mac_mode);
1452                 udelay(40);
1453         }
1454
1455         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1456                 if (phydev->speed == SPEED_10)
1457                         tw32(MAC_MI_STAT,
1458                              MAC_MI_STAT_10MBPS_MODE |
1459                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1460                 else
1461                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1462         }
1463
1464         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1465                 tw32(MAC_TX_LENGTHS,
1466                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1467                       (6 << TX_LENGTHS_IPG_SHIFT) |
1468                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1469         else
1470                 tw32(MAC_TX_LENGTHS,
1471                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1472                       (6 << TX_LENGTHS_IPG_SHIFT) |
1473                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1474
1475         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1476             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1477             phydev->speed != tp->link_config.active_speed ||
1478             phydev->duplex != tp->link_config.active_duplex ||
1479             oldflowctrl != tp->link_config.active_flowctrl)
1480                 linkmesg = 1;
1481
1482         tp->link_config.active_speed = phydev->speed;
1483         tp->link_config.active_duplex = phydev->duplex;
1484
1485         spin_unlock_bh(&tp->lock);
1486
1487         if (linkmesg)
1488                 tg3_link_report(tp);
1489 }
1490
1491 static int tg3_phy_init(struct tg3 *tp)
1492 {
1493         struct phy_device *phydev;
1494
1495         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1496                 return 0;
1497
1498         /* Bring the PHY back to a known state. */
1499         tg3_bmcr_reset(tp);
1500
1501         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1502
1503         /* Attach the MAC to the PHY. */
1504         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1505                              phydev->dev_flags, phydev->interface);
1506         if (IS_ERR(phydev)) {
1507                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1508                 return PTR_ERR(phydev);
1509         }
1510
1511         /* Mask with MAC supported features. */
1512         switch (phydev->interface) {
1513         case PHY_INTERFACE_MODE_GMII:
1514         case PHY_INTERFACE_MODE_RGMII:
1515                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1516                         phydev->supported &= (PHY_GBIT_FEATURES |
1517                                               SUPPORTED_Pause |
1518                                               SUPPORTED_Asym_Pause);
1519                         break;
1520                 }
1521                 /* fallthru */
1522         case PHY_INTERFACE_MODE_MII:
1523                 phydev->supported &= (PHY_BASIC_FEATURES |
1524                                       SUPPORTED_Pause |
1525                                       SUPPORTED_Asym_Pause);
1526                 break;
1527         default:
1528                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1529                 return -EINVAL;
1530         }
1531
1532         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1533
1534         phydev->advertising = phydev->supported;
1535
1536         return 0;
1537 }
1538
1539 static void tg3_phy_start(struct tg3 *tp)
1540 {
1541         struct phy_device *phydev;
1542
1543         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1544                 return;
1545
1546         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1547
1548         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1549                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1550                 phydev->speed = tp->link_config.orig_speed;
1551                 phydev->duplex = tp->link_config.orig_duplex;
1552                 phydev->autoneg = tp->link_config.orig_autoneg;
1553                 phydev->advertising = tp->link_config.orig_advertising;
1554         }
1555
1556         phy_start(phydev);
1557
1558         phy_start_aneg(phydev);
1559 }
1560
1561 static void tg3_phy_stop(struct tg3 *tp)
1562 {
1563         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1564                 return;
1565
1566         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1567 }
1568
1569 static void tg3_phy_fini(struct tg3 *tp)
1570 {
1571         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1572                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1573                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1574         }
1575 }
1576
1577 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1578 {
1579         int err;
1580
1581         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1582         if (!err)
1583                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1584
1585         return err;
1586 }
1587
1588 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1589 {
1590         int err;
1591
1592         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1593         if (!err)
1594                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1595
1596         return err;
1597 }
1598
1599 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1600 {
1601         u32 phytest;
1602
1603         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1604                 u32 phy;
1605
1606                 tg3_writephy(tp, MII_TG3_FET_TEST,
1607                              phytest | MII_TG3_FET_SHADOW_EN);
1608                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1609                         if (enable)
1610                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1611                         else
1612                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1613                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1614                 }
1615                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1616         }
1617 }
1618
1619 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1620 {
1621         u32 reg;
1622
1623         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1624             ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
1625              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1626                 return;
1627
1628         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1629                 tg3_phy_fet_toggle_apd(tp, enable);
1630                 return;
1631         }
1632
1633         reg = MII_TG3_MISC_SHDW_WREN |
1634               MII_TG3_MISC_SHDW_SCR5_SEL |
1635               MII_TG3_MISC_SHDW_SCR5_LPED |
1636               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1637               MII_TG3_MISC_SHDW_SCR5_SDTL |
1638               MII_TG3_MISC_SHDW_SCR5_C125OE;
1639         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1640                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1641
1642         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1643
1644
1645         reg = MII_TG3_MISC_SHDW_WREN |
1646               MII_TG3_MISC_SHDW_APD_SEL |
1647               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1648         if (enable)
1649                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1650
1651         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1652 }
1653
1654 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1655 {
1656         u32 phy;
1657
1658         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1659             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1660                 return;
1661
1662         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1663                 u32 ephy;
1664
1665                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1666                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1667
1668                         tg3_writephy(tp, MII_TG3_FET_TEST,
1669                                      ephy | MII_TG3_FET_SHADOW_EN);
1670                         if (!tg3_readphy(tp, reg, &phy)) {
1671                                 if (enable)
1672                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1673                                 else
1674                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1675                                 tg3_writephy(tp, reg, phy);
1676                         }
1677                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1678                 }
1679         } else {
1680                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1681                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1682                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1683                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1684                         if (enable)
1685                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1686                         else
1687                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1688                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1689                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1690                 }
1691         }
1692 }
1693
1694 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1695 {
1696         u32 val;
1697
1698         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1699                 return;
1700
1701         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1702             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1703                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1704                              (val | (1 << 15) | (1 << 4)));
1705 }
1706
1707 static void tg3_phy_apply_otp(struct tg3 *tp)
1708 {
1709         u32 otp, phy;
1710
1711         if (!tp->phy_otp)
1712                 return;
1713
1714         otp = tp->phy_otp;
1715
1716         /* Enable SM_DSP clock and tx 6dB coding. */
1717         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1718               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1719               MII_TG3_AUXCTL_ACTL_TX_6DB;
1720         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1721
1722         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1723         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1724         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1725
1726         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1727               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1728         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1729
1730         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1731         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1732         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1733
1734         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1735         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1736
1737         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1738         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1739
1740         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1741               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1742         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1743
1744         /* Turn off SM_DSP clock. */
1745         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1746               MII_TG3_AUXCTL_ACTL_TX_6DB;
1747         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1748 }
1749
1750 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1751 {
1752         u32 val;
1753
1754         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1755                 return;
1756
1757         tp->setlpicnt = 0;
1758
1759         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1760             current_link_up == 1 &&
1761             tp->link_config.active_duplex == DUPLEX_FULL &&
1762             (tp->link_config.active_speed == SPEED_100 ||
1763              tp->link_config.active_speed == SPEED_1000)) {
1764                 u32 eeectl;
1765
1766                 if (tp->link_config.active_speed == SPEED_1000)
1767                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1768                 else
1769                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1770
1771                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1772
1773                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1774                                   TG3_CL45_D7_EEERES_STAT, &val);
1775
1776                 switch (val) {
1777                 case TG3_CL45_D7_EEERES_STAT_LP_1000T:
1778                         switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
1779                         case ASIC_REV_5717:
1780                         case ASIC_REV_5719:
1781                         case ASIC_REV_57765:
1782                                 /* Enable SM_DSP clock and tx 6dB coding. */
1783                                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1784                                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1785                                       MII_TG3_AUXCTL_ACTL_TX_6DB;
1786                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1787
1788                                 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
1789
1790                                 /* Turn off SM_DSP clock. */
1791                                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1792                                       MII_TG3_AUXCTL_ACTL_TX_6DB;
1793                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1794                         }
1795                         /* Fallthrough */
1796                 case TG3_CL45_D7_EEERES_STAT_LP_100TX:
1797                         tp->setlpicnt = 2;
1798                 }
1799         }
1800
1801         if (!tp->setlpicnt) {
1802                 val = tr32(TG3_CPMU_EEE_MODE);
1803                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1804         }
1805 }
1806
1807 static int tg3_wait_macro_done(struct tg3 *tp)
1808 {
1809         int limit = 100;
1810
1811         while (limit--) {
1812                 u32 tmp32;
1813
1814                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1815                         if ((tmp32 & 0x1000) == 0)
1816                                 break;
1817                 }
1818         }
1819         if (limit < 0)
1820                 return -EBUSY;
1821
1822         return 0;
1823 }
1824
1825 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1826 {
1827         static const u32 test_pat[4][6] = {
1828         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1829         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1830         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1831         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1832         };
1833         int chan;
1834
1835         for (chan = 0; chan < 4; chan++) {
1836                 int i;
1837
1838                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1839                              (chan * 0x2000) | 0x0200);
1840                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1841
1842                 for (i = 0; i < 6; i++)
1843                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1844                                      test_pat[chan][i]);
1845
1846                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1847                 if (tg3_wait_macro_done(tp)) {
1848                         *resetp = 1;
1849                         return -EBUSY;
1850                 }
1851
1852                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1853                              (chan * 0x2000) | 0x0200);
1854                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1855                 if (tg3_wait_macro_done(tp)) {
1856                         *resetp = 1;
1857                         return -EBUSY;
1858                 }
1859
1860                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1861                 if (tg3_wait_macro_done(tp)) {
1862                         *resetp = 1;
1863                         return -EBUSY;
1864                 }
1865
1866                 for (i = 0; i < 6; i += 2) {
1867                         u32 low, high;
1868
1869                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1870                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1871                             tg3_wait_macro_done(tp)) {
1872                                 *resetp = 1;
1873                                 return -EBUSY;
1874                         }
1875                         low &= 0x7fff;
1876                         high &= 0x000f;
1877                         if (low != test_pat[chan][i] ||
1878                             high != test_pat[chan][i+1]) {
1879                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1880                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1881                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1882
1883                                 return -EBUSY;
1884                         }
1885                 }
1886         }
1887
1888         return 0;
1889 }
1890
1891 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1892 {
1893         int chan;
1894
1895         for (chan = 0; chan < 4; chan++) {
1896                 int i;
1897
1898                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1899                              (chan * 0x2000) | 0x0200);
1900                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1901                 for (i = 0; i < 6; i++)
1902                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1903                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1904                 if (tg3_wait_macro_done(tp))
1905                         return -EBUSY;
1906         }
1907
1908         return 0;
1909 }
1910
1911 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1912 {
1913         u32 reg32, phy9_orig;
1914         int retries, do_phy_reset, err;
1915
1916         retries = 10;
1917         do_phy_reset = 1;
1918         do {
1919                 if (do_phy_reset) {
1920                         err = tg3_bmcr_reset(tp);
1921                         if (err)
1922                                 return err;
1923                         do_phy_reset = 0;
1924                 }
1925
1926                 /* Disable transmitter and interrupt.  */
1927                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1928                         continue;
1929
1930                 reg32 |= 0x3000;
1931                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1932
1933                 /* Set full-duplex, 1000 mbps.  */
1934                 tg3_writephy(tp, MII_BMCR,
1935                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1936
1937                 /* Set to master mode.  */
1938                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1939                         continue;
1940
1941                 tg3_writephy(tp, MII_TG3_CTRL,
1942                              (MII_TG3_CTRL_AS_MASTER |
1943                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1944
1945                 /* Enable SM_DSP_CLOCK and 6dB.  */
1946                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1947
1948                 /* Block the PHY control access.  */
1949                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1950
1951                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1952                 if (!err)
1953                         break;
1954         } while (--retries);
1955
1956         err = tg3_phy_reset_chanpat(tp);
1957         if (err)
1958                 return err;
1959
1960         tg3_phydsp_write(tp, 0x8005, 0x0000);
1961
1962         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1963         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1964
1965         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1966             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1967                 /* Set Extended packet length bit for jumbo frames */
1968                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1969         } else {
1970                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1971         }
1972
1973         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1974
1975         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1976                 reg32 &= ~0x3000;
1977                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1978         } else if (!err)
1979                 err = -EBUSY;
1980
1981         return err;
1982 }
1983
1984 /* This will reset the tigon3 PHY if there is no valid
1985  * link unless the FORCE argument is non-zero.
1986  */
1987 static int tg3_phy_reset(struct tg3 *tp)
1988 {
1989         u32 val, cpmuctrl;
1990         int err;
1991
1992         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1993                 val = tr32(GRC_MISC_CFG);
1994                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1995                 udelay(40);
1996         }
1997         err  = tg3_readphy(tp, MII_BMSR, &val);
1998         err |= tg3_readphy(tp, MII_BMSR, &val);
1999         if (err != 0)
2000                 return -EBUSY;
2001
2002         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2003                 netif_carrier_off(tp->dev);
2004                 tg3_link_report(tp);
2005         }
2006
2007         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2008             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2009             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2010                 err = tg3_phy_reset_5703_4_5(tp);
2011                 if (err)
2012                         return err;
2013                 goto out;
2014         }
2015
2016         cpmuctrl = 0;
2017         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2018             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2019                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2020                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2021                         tw32(TG3_CPMU_CTRL,
2022                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2023         }
2024
2025         err = tg3_bmcr_reset(tp);
2026         if (err)
2027                 return err;
2028
2029         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2030                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2031                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2032
2033                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2034         }
2035
2036         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2037             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2038                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2039                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2040                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2041                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2042                         udelay(40);
2043                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2044                 }
2045         }
2046
2047         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
2048             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2049                 return 0;
2050
2051         tg3_phy_apply_otp(tp);
2052
2053         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2054                 tg3_phy_toggle_apd(tp, true);
2055         else
2056                 tg3_phy_toggle_apd(tp, false);
2057
2058 out:
2059         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2060                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2061                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2062                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2063                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2064         }
2065         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2066                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2067                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2068         }
2069         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2070                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2071                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2072                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2073                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2074                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2075         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2076                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2077                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2078                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2079                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2080                         tg3_writephy(tp, MII_TG3_TEST1,
2081                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2082                 } else
2083                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2084                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2085         }
2086         /* Set Extended packet length bit (bit 14) on all chips that */
2087         /* support jumbo frames */
2088         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2089                 /* Cannot do read-modify-write on 5401 */
2090                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2091         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2092                 /* Set bit 14 with read-modify-write to preserve other bits */
2093                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2094                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2095                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2096         }
2097
2098         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2099          * jumbo frames transmission.
2100          */
2101         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2102                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2103                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2104                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2105         }
2106
2107         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2108                 /* adjust output voltage */
2109                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2110         }
2111
2112         tg3_phy_toggle_automdix(tp, 1);
2113         tg3_phy_set_wirespeed(tp);
2114         return 0;
2115 }
2116
2117 static void tg3_frob_aux_power(struct tg3 *tp)
2118 {
2119         bool need_vaux = false;
2120
2121         /* The GPIOs do something completely different on 57765. */
2122         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2123             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2124             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2125                 return;
2126
2127         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2128              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2129              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2130              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
2131             tp->pdev_peer != tp->pdev) {
2132                 struct net_device *dev_peer;
2133
2134                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2135
2136                 /* remove_one() may have been run on the peer. */
2137                 if (dev_peer) {
2138                         struct tg3 *tp_peer = netdev_priv(dev_peer);
2139
2140                         if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE)
2141                                 return;
2142
2143                         if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2144                             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF))
2145                                 need_vaux = true;
2146                 }
2147         }
2148
2149         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2150             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2151                 need_vaux = true;
2152
2153         if (need_vaux) {
2154                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2155                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2156                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2157                                     (GRC_LCLCTRL_GPIO_OE0 |
2158                                      GRC_LCLCTRL_GPIO_OE1 |
2159                                      GRC_LCLCTRL_GPIO_OE2 |
2160                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2161                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2162                                     100);
2163                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2164                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2165                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2166                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2167                                              GRC_LCLCTRL_GPIO_OE1 |
2168                                              GRC_LCLCTRL_GPIO_OE2 |
2169                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2170                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2171                                              tp->grc_local_ctrl;
2172                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2173
2174                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2175                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2176
2177                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2178                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2179                 } else {
2180                         u32 no_gpio2;
2181                         u32 grc_local_ctrl = 0;
2182
2183                         /* Workaround to prevent overdrawing Amps. */
2184                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2185                             ASIC_REV_5714) {
2186                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2187                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2188                                             grc_local_ctrl, 100);
2189                         }
2190
2191                         /* On 5753 and variants, GPIO2 cannot be used. */
2192                         no_gpio2 = tp->nic_sram_data_cfg &
2193                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2194
2195                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2196                                          GRC_LCLCTRL_GPIO_OE1 |
2197                                          GRC_LCLCTRL_GPIO_OE2 |
2198                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2199                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2200                         if (no_gpio2) {
2201                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2202                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2203                         }
2204                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2205                                                     grc_local_ctrl, 100);
2206
2207                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2208
2209                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2210                                                     grc_local_ctrl, 100);
2211
2212                         if (!no_gpio2) {
2213                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2214                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2215                                             grc_local_ctrl, 100);
2216                         }
2217                 }
2218         } else {
2219                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2220                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2221                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2222                                     (GRC_LCLCTRL_GPIO_OE1 |
2223                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2224
2225                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2226                                     GRC_LCLCTRL_GPIO_OE1, 100);
2227
2228                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2229                                     (GRC_LCLCTRL_GPIO_OE1 |
2230                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2231                 }
2232         }
2233 }
2234
2235 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2236 {
2237         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2238                 return 1;
2239         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2240                 if (speed != SPEED_10)
2241                         return 1;
2242         } else if (speed == SPEED_10)
2243                 return 1;
2244
2245         return 0;
2246 }
2247
2248 static int tg3_setup_phy(struct tg3 *, int);
2249
2250 #define RESET_KIND_SHUTDOWN     0
2251 #define RESET_KIND_INIT         1
2252 #define RESET_KIND_SUSPEND      2
2253
2254 static void tg3_write_sig_post_reset(struct tg3 *, int);
2255 static int tg3_halt_cpu(struct tg3 *, u32);
2256
2257 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2258 {
2259         u32 val;
2260
2261         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2262                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2263                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2264                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2265
2266                         sg_dig_ctrl |=
2267                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2268                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2269                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2270                 }
2271                 return;
2272         }
2273
2274         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2275                 tg3_bmcr_reset(tp);
2276                 val = tr32(GRC_MISC_CFG);
2277                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2278                 udelay(40);
2279                 return;
2280         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2281                 u32 phytest;
2282                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2283                         u32 phy;
2284
2285                         tg3_writephy(tp, MII_ADVERTISE, 0);
2286                         tg3_writephy(tp, MII_BMCR,
2287                                      BMCR_ANENABLE | BMCR_ANRESTART);
2288
2289                         tg3_writephy(tp, MII_TG3_FET_TEST,
2290                                      phytest | MII_TG3_FET_SHADOW_EN);
2291                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2292                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2293                                 tg3_writephy(tp,
2294                                              MII_TG3_FET_SHDW_AUXMODE4,
2295                                              phy);
2296                         }
2297                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2298                 }
2299                 return;
2300         } else if (do_low_power) {
2301                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2302                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2303
2304                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2305                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2306                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2307                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2308                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2309         }
2310
2311         /* The PHY should not be powered down on some chips because
2312          * of bugs.
2313          */
2314         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2315             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2316             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2317              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2318                 return;
2319
2320         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2321             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2322                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2323                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2324                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2325                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2326         }
2327
2328         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2329 }
2330
2331 /* tp->lock is held. */
2332 static int tg3_nvram_lock(struct tg3 *tp)
2333 {
2334         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2335                 int i;
2336
2337                 if (tp->nvram_lock_cnt == 0) {
2338                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2339                         for (i = 0; i < 8000; i++) {
2340                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2341                                         break;
2342                                 udelay(20);
2343                         }
2344                         if (i == 8000) {
2345                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2346                                 return -ENODEV;
2347                         }
2348                 }
2349                 tp->nvram_lock_cnt++;
2350         }
2351         return 0;
2352 }
2353
2354 /* tp->lock is held. */
2355 static void tg3_nvram_unlock(struct tg3 *tp)
2356 {
2357         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2358                 if (tp->nvram_lock_cnt > 0)
2359                         tp->nvram_lock_cnt--;
2360                 if (tp->nvram_lock_cnt == 0)
2361                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2362         }
2363 }
2364
2365 /* tp->lock is held. */
2366 static void tg3_enable_nvram_access(struct tg3 *tp)
2367 {
2368         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2369             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2370                 u32 nvaccess = tr32(NVRAM_ACCESS);
2371
2372                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2373         }
2374 }
2375
2376 /* tp->lock is held. */
2377 static void tg3_disable_nvram_access(struct tg3 *tp)
2378 {
2379         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2380             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2381                 u32 nvaccess = tr32(NVRAM_ACCESS);
2382
2383                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2384         }
2385 }
2386
2387 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2388                                         u32 offset, u32 *val)
2389 {
2390         u32 tmp;
2391         int i;
2392
2393         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2394                 return -EINVAL;
2395
2396         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2397                                         EEPROM_ADDR_DEVID_MASK |
2398                                         EEPROM_ADDR_READ);
2399         tw32(GRC_EEPROM_ADDR,
2400              tmp |
2401              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2402              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2403               EEPROM_ADDR_ADDR_MASK) |
2404              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2405
2406         for (i = 0; i < 1000; i++) {
2407                 tmp = tr32(GRC_EEPROM_ADDR);
2408
2409                 if (tmp & EEPROM_ADDR_COMPLETE)
2410                         break;
2411                 msleep(1);
2412         }
2413         if (!(tmp & EEPROM_ADDR_COMPLETE))
2414                 return -EBUSY;
2415
2416         tmp = tr32(GRC_EEPROM_DATA);
2417
2418         /*
2419          * The data will always be opposite the native endian
2420          * format.  Perform a blind byteswap to compensate.
2421          */
2422         *val = swab32(tmp);
2423
2424         return 0;
2425 }
2426
2427 #define NVRAM_CMD_TIMEOUT 10000
2428
2429 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2430 {
2431         int i;
2432
2433         tw32(NVRAM_CMD, nvram_cmd);
2434         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2435                 udelay(10);
2436                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2437                         udelay(10);
2438                         break;
2439                 }
2440         }
2441
2442         if (i == NVRAM_CMD_TIMEOUT)
2443                 return -EBUSY;
2444
2445         return 0;
2446 }
2447
2448 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2449 {
2450         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2451             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2452             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2453            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2454             (tp->nvram_jedecnum == JEDEC_ATMEL))
2455
2456                 addr = ((addr / tp->nvram_pagesize) <<
2457                         ATMEL_AT45DB0X1B_PAGE_POS) +
2458                        (addr % tp->nvram_pagesize);
2459
2460         return addr;
2461 }
2462
2463 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2464 {
2465         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2466             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2467             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2468            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2469             (tp->nvram_jedecnum == JEDEC_ATMEL))
2470
2471                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2472                         tp->nvram_pagesize) +
2473                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2474
2475         return addr;
2476 }
2477
2478 /* NOTE: Data read in from NVRAM is byteswapped according to
2479  * the byteswapping settings for all other register accesses.
2480  * tg3 devices are BE devices, so on a BE machine, the data
2481  * returned will be exactly as it is seen in NVRAM.  On a LE
2482  * machine, the 32-bit value will be byteswapped.
2483  */
2484 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2485 {
2486         int ret;
2487
2488         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2489                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2490
2491         offset = tg3_nvram_phys_addr(tp, offset);
2492
2493         if (offset > NVRAM_ADDR_MSK)
2494                 return -EINVAL;
2495
2496         ret = tg3_nvram_lock(tp);
2497         if (ret)
2498                 return ret;
2499
2500         tg3_enable_nvram_access(tp);
2501
2502         tw32(NVRAM_ADDR, offset);
2503         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2504                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2505
2506         if (ret == 0)
2507                 *val = tr32(NVRAM_RDDATA);
2508
2509         tg3_disable_nvram_access(tp);
2510
2511         tg3_nvram_unlock(tp);
2512
2513         return ret;
2514 }
2515
2516 /* Ensures NVRAM data is in bytestream format. */
2517 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2518 {
2519         u32 v;
2520         int res = tg3_nvram_read(tp, offset, &v);
2521         if (!res)
2522                 *val = cpu_to_be32(v);
2523         return res;
2524 }
2525
2526 /* tp->lock is held. */
2527 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2528 {
2529         u32 addr_high, addr_low;
2530         int i;
2531
2532         addr_high = ((tp->dev->dev_addr[0] << 8) |
2533                      tp->dev->dev_addr[1]);
2534         addr_low = ((tp->dev->dev_addr[2] << 24) |
2535                     (tp->dev->dev_addr[3] << 16) |
2536                     (tp->dev->dev_addr[4] <<  8) |
2537                     (tp->dev->dev_addr[5] <<  0));
2538         for (i = 0; i < 4; i++) {
2539                 if (i == 1 && skip_mac_1)
2540                         continue;
2541                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2542                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2543         }
2544
2545         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2546             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2547                 for (i = 0; i < 12; i++) {
2548                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2549                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2550                 }
2551         }
2552
2553         addr_high = (tp->dev->dev_addr[0] +
2554                      tp->dev->dev_addr[1] +
2555                      tp->dev->dev_addr[2] +
2556                      tp->dev->dev_addr[3] +
2557                      tp->dev->dev_addr[4] +
2558                      tp->dev->dev_addr[5]) &
2559                 TX_BACKOFF_SEED_MASK;
2560         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2561 }
2562
2563 static void tg3_enable_register_access(struct tg3 *tp)
2564 {
2565         /*
2566          * Make sure register accesses (indirect or otherwise) will function
2567          * correctly.
2568          */
2569         pci_write_config_dword(tp->pdev,
2570                                TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2571 }
2572
2573 static int tg3_power_up(struct tg3 *tp)
2574 {
2575         tg3_enable_register_access(tp);
2576
2577         pci_set_power_state(tp->pdev, PCI_D0);
2578
2579         /* Switch out of Vaux if it is a NIC */
2580         if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2581                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2582
2583         return 0;
2584 }
2585
2586 static int tg3_power_down_prepare(struct tg3 *tp)
2587 {
2588         u32 misc_host_ctrl;
2589         bool device_should_wake, do_low_power;
2590
2591         tg3_enable_register_access(tp);
2592
2593         /* Restore the CLKREQ setting. */
2594         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2595                 u16 lnkctl;
2596
2597                 pci_read_config_word(tp->pdev,
2598                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2599                                      &lnkctl);
2600                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2601                 pci_write_config_word(tp->pdev,
2602                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2603                                       lnkctl);
2604         }
2605
2606         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2607         tw32(TG3PCI_MISC_HOST_CTRL,
2608              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2609
2610         device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2611                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2612
2613         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2614                 do_low_power = false;
2615                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2616                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2617                         struct phy_device *phydev;
2618                         u32 phyid, advertising;
2619
2620                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2621
2622                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2623
2624                         tp->link_config.orig_speed = phydev->speed;
2625                         tp->link_config.orig_duplex = phydev->duplex;
2626                         tp->link_config.orig_autoneg = phydev->autoneg;
2627                         tp->link_config.orig_advertising = phydev->advertising;
2628
2629                         advertising = ADVERTISED_TP |
2630                                       ADVERTISED_Pause |
2631                                       ADVERTISED_Autoneg |
2632                                       ADVERTISED_10baseT_Half;
2633
2634                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2635                             device_should_wake) {
2636                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2637                                         advertising |=
2638                                                 ADVERTISED_100baseT_Half |
2639                                                 ADVERTISED_100baseT_Full |
2640                                                 ADVERTISED_10baseT_Full;
2641                                 else
2642                                         advertising |= ADVERTISED_10baseT_Full;
2643                         }
2644
2645                         phydev->advertising = advertising;
2646
2647                         phy_start_aneg(phydev);
2648
2649                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2650                         if (phyid != PHY_ID_BCMAC131) {
2651                                 phyid &= PHY_BCM_OUI_MASK;
2652                                 if (phyid == PHY_BCM_OUI_1 ||
2653                                     phyid == PHY_BCM_OUI_2 ||
2654                                     phyid == PHY_BCM_OUI_3)
2655                                         do_low_power = true;
2656                         }
2657                 }
2658         } else {
2659                 do_low_power = true;
2660
2661                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2662                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2663                         tp->link_config.orig_speed = tp->link_config.speed;
2664                         tp->link_config.orig_duplex = tp->link_config.duplex;
2665                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2666                 }
2667
2668                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2669                         tp->link_config.speed = SPEED_10;
2670                         tp->link_config.duplex = DUPLEX_HALF;
2671                         tp->link_config.autoneg = AUTONEG_ENABLE;
2672                         tg3_setup_phy(tp, 0);
2673                 }
2674         }
2675
2676         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2677                 u32 val;
2678
2679                 val = tr32(GRC_VCPU_EXT_CTRL);
2680                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2681         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2682                 int i;
2683                 u32 val;
2684
2685                 for (i = 0; i < 200; i++) {
2686                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2687                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2688                                 break;
2689                         msleep(1);
2690                 }
2691         }
2692         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2693                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2694                                                      WOL_DRV_STATE_SHUTDOWN |
2695                                                      WOL_DRV_WOL |
2696                                                      WOL_SET_MAGIC_PKT);
2697
2698         if (device_should_wake) {
2699                 u32 mac_mode;
2700
2701                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2702                         if (do_low_power) {
2703                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2704                                 udelay(40);
2705                         }
2706
2707                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2708                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2709                         else
2710                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2711
2712                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2713                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2714                             ASIC_REV_5700) {
2715                                 u32 speed = (tp->tg3_flags &
2716                                              TG3_FLAG_WOL_SPEED_100MB) ?
2717                                              SPEED_100 : SPEED_10;
2718                                 if (tg3_5700_link_polarity(tp, speed))
2719                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2720                                 else
2721                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2722                         }
2723                 } else {
2724                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2725                 }
2726
2727                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2728                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2729
2730                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2731                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2732                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2733                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2734                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2735                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2736
2737                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2738                         mac_mode |= MAC_MODE_APE_TX_EN |
2739                                     MAC_MODE_APE_RX_EN |
2740                                     MAC_MODE_TDE_ENABLE;
2741
2742                 tw32_f(MAC_MODE, mac_mode);
2743                 udelay(100);
2744
2745                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2746                 udelay(10);
2747         }
2748
2749         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2750             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2751              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2752                 u32 base_val;
2753
2754                 base_val = tp->pci_clock_ctrl;
2755                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2756                              CLOCK_CTRL_TXCLK_DISABLE);
2757
2758                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2759                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2760         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2761                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2762                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2763                 /* do nothing */
2764         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2765                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2766                 u32 newbits1, newbits2;
2767
2768                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2769                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2770                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2771                                     CLOCK_CTRL_TXCLK_DISABLE |
2772                                     CLOCK_CTRL_ALTCLK);
2773                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2774                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2775                         newbits1 = CLOCK_CTRL_625_CORE;
2776                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2777                 } else {
2778                         newbits1 = CLOCK_CTRL_ALTCLK;
2779                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2780                 }
2781
2782                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2783                             40);
2784
2785                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2786                             40);
2787
2788                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2789                         u32 newbits3;
2790
2791                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2792                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2793                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2794                                             CLOCK_CTRL_TXCLK_DISABLE |
2795                                             CLOCK_CTRL_44MHZ_CORE);
2796                         } else {
2797                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2798                         }
2799
2800                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2801                                     tp->pci_clock_ctrl | newbits3, 40);
2802                 }
2803         }
2804
2805         if (!(device_should_wake) &&
2806             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2807                 tg3_power_down_phy(tp, do_low_power);
2808
2809         tg3_frob_aux_power(tp);
2810
2811         /* Workaround for unstable PLL clock */
2812         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2813             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2814                 u32 val = tr32(0x7d00);
2815
2816                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2817                 tw32(0x7d00, val);
2818                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2819                         int err;
2820
2821                         err = tg3_nvram_lock(tp);
2822                         tg3_halt_cpu(tp, RX_CPU_BASE);
2823                         if (!err)
2824                                 tg3_nvram_unlock(tp);
2825                 }
2826         }
2827
2828         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2829
2830         return 0;
2831 }
2832
2833 static void tg3_power_down(struct tg3 *tp)
2834 {
2835         tg3_power_down_prepare(tp);
2836
2837         pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2838         pci_set_power_state(tp->pdev, PCI_D3hot);
2839 }
2840
2841 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2842 {
2843         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2844         case MII_TG3_AUX_STAT_10HALF:
2845                 *speed = SPEED_10;
2846                 *duplex = DUPLEX_HALF;
2847                 break;
2848
2849         case MII_TG3_AUX_STAT_10FULL:
2850                 *speed = SPEED_10;
2851                 *duplex = DUPLEX_FULL;
2852                 break;
2853
2854         case MII_TG3_AUX_STAT_100HALF:
2855                 *speed = SPEED_100;
2856                 *duplex = DUPLEX_HALF;
2857                 break;
2858
2859         case MII_TG3_AUX_STAT_100FULL:
2860                 *speed = SPEED_100;
2861                 *duplex = DUPLEX_FULL;
2862                 break;
2863
2864         case MII_TG3_AUX_STAT_1000HALF:
2865                 *speed = SPEED_1000;
2866                 *duplex = DUPLEX_HALF;
2867                 break;
2868
2869         case MII_TG3_AUX_STAT_1000FULL:
2870                 *speed = SPEED_1000;
2871                 *duplex = DUPLEX_FULL;
2872                 break;
2873
2874         default:
2875                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2876                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2877                                  SPEED_10;
2878                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2879                                   DUPLEX_HALF;
2880                         break;
2881                 }
2882                 *speed = SPEED_INVALID;
2883                 *duplex = DUPLEX_INVALID;
2884                 break;
2885         }
2886 }
2887
2888 static void tg3_phy_copper_begin(struct tg3 *tp)
2889 {
2890         u32 new_adv;
2891         int i;
2892
2893         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2894                 /* Entering low power mode.  Disable gigabit and
2895                  * 100baseT advertisements.
2896                  */
2897                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2898
2899                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2900                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2901                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2902                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2903
2904                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2905         } else if (tp->link_config.speed == SPEED_INVALID) {
2906                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2907                         tp->link_config.advertising &=
2908                                 ~(ADVERTISED_1000baseT_Half |
2909                                   ADVERTISED_1000baseT_Full);
2910
2911                 new_adv = ADVERTISE_CSMA;
2912                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2913                         new_adv |= ADVERTISE_10HALF;
2914                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2915                         new_adv |= ADVERTISE_10FULL;
2916                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2917                         new_adv |= ADVERTISE_100HALF;
2918                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2919                         new_adv |= ADVERTISE_100FULL;
2920
2921                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2922
2923                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2924
2925                 if (tp->link_config.advertising &
2926                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2927                         new_adv = 0;
2928                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2929                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2930                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2931                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2932                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2933                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2934                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2935                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2936                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2937                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2938                 } else {
2939                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2940                 }
2941         } else {
2942                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2943                 new_adv |= ADVERTISE_CSMA;
2944
2945                 /* Asking for a specific link mode. */
2946                 if (tp->link_config.speed == SPEED_1000) {
2947                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2948
2949                         if (tp->link_config.duplex == DUPLEX_FULL)
2950                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2951                         else
2952                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2953                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2954                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2955                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2956                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2957                 } else {
2958                         if (tp->link_config.speed == SPEED_100) {
2959                                 if (tp->link_config.duplex == DUPLEX_FULL)
2960                                         new_adv |= ADVERTISE_100FULL;
2961                                 else
2962                                         new_adv |= ADVERTISE_100HALF;
2963                         } else {
2964                                 if (tp->link_config.duplex == DUPLEX_FULL)
2965                                         new_adv |= ADVERTISE_10FULL;
2966                                 else
2967                                         new_adv |= ADVERTISE_10HALF;
2968                         }
2969                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2970
2971                         new_adv = 0;
2972                 }
2973
2974                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2975         }
2976
2977         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2978                 u32 val;
2979
2980                 tw32(TG3_CPMU_EEE_MODE,
2981                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2982
2983                 /* Enable SM_DSP clock and tx 6dB coding. */
2984                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2985                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2986                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2987                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2988
2989                 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
2990                 case ASIC_REV_5717:
2991                 case ASIC_REV_57765:
2992                         if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2993                                 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
2994                                                  MII_TG3_DSP_CH34TP2_HIBW01);
2995                         /* Fall through */
2996                 case ASIC_REV_5719:
2997                         val = MII_TG3_DSP_TAP26_ALNOKO |
2998                               MII_TG3_DSP_TAP26_RMRXSTO |
2999                               MII_TG3_DSP_TAP26_OPCSINPT;
3000                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3001                 }
3002
3003                 val = 0;
3004                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3005                         /* Advertise 100-BaseTX EEE ability */
3006                         if (tp->link_config.advertising &
3007                             ADVERTISED_100baseT_Full)
3008                                 val |= MDIO_AN_EEE_ADV_100TX;
3009                         /* Advertise 1000-BaseT EEE ability */
3010                         if (tp->link_config.advertising &
3011                             ADVERTISED_1000baseT_Full)
3012                                 val |= MDIO_AN_EEE_ADV_1000T;
3013                 }
3014                 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3015
3016                 /* Turn off SM_DSP clock. */
3017                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3018                       MII_TG3_AUXCTL_ACTL_TX_6DB;
3019                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3020         }
3021
3022         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3023             tp->link_config.speed != SPEED_INVALID) {
3024                 u32 bmcr, orig_bmcr;
3025
3026                 tp->link_config.active_speed = tp->link_config.speed;
3027                 tp->link_config.active_duplex = tp->link_config.duplex;
3028
3029                 bmcr = 0;
3030                 switch (tp->link_config.speed) {
3031                 default:
3032                 case SPEED_10:
3033                         break;
3034
3035                 case SPEED_100:
3036                         bmcr |= BMCR_SPEED100;
3037                         break;
3038
3039                 case SPEED_1000:
3040                         bmcr |= TG3_BMCR_SPEED1000;
3041                         break;
3042                 }
3043
3044                 if (tp->link_config.duplex == DUPLEX_FULL)
3045                         bmcr |= BMCR_FULLDPLX;
3046
3047                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3048                     (bmcr != orig_bmcr)) {
3049                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3050                         for (i = 0; i < 1500; i++) {
3051                                 u32 tmp;
3052
3053                                 udelay(10);
3054                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3055                                     tg3_readphy(tp, MII_BMSR, &tmp))
3056                                         continue;
3057                                 if (!(tmp & BMSR_LSTATUS)) {
3058                                         udelay(40);
3059                                         break;
3060                                 }
3061                         }
3062                         tg3_writephy(tp, MII_BMCR, bmcr);
3063                         udelay(40);
3064                 }
3065         } else {
3066                 tg3_writephy(tp, MII_BMCR,
3067                              BMCR_ANENABLE | BMCR_ANRESTART);
3068         }
3069 }
3070
3071 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3072 {
3073         int err;
3074
3075         /* Turn off tap power management. */
3076         /* Set Extended packet length bit */
3077         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3078
3079         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3080         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3081         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3082         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3083         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3084
3085         udelay(40);
3086
3087         return err;
3088 }
3089
3090 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3091 {
3092         u32 adv_reg, all_mask = 0;
3093
3094         if (mask & ADVERTISED_10baseT_Half)
3095                 all_mask |= ADVERTISE_10HALF;
3096         if (mask & ADVERTISED_10baseT_Full)
3097                 all_mask |= ADVERTISE_10FULL;
3098         if (mask & ADVERTISED_100baseT_Half)
3099                 all_mask |= ADVERTISE_100HALF;
3100         if (mask & ADVERTISED_100baseT_Full)
3101                 all_mask |= ADVERTISE_100FULL;
3102
3103         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3104                 return 0;
3105
3106         if ((adv_reg & all_mask) != all_mask)
3107                 return 0;
3108         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3109                 u32 tg3_ctrl;
3110
3111                 all_mask = 0;
3112                 if (mask & ADVERTISED_1000baseT_Half)
3113                         all_mask |= ADVERTISE_1000HALF;
3114                 if (mask & ADVERTISED_1000baseT_Full)
3115                         all_mask |= ADVERTISE_1000FULL;
3116
3117                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3118                         return 0;
3119
3120                 if ((tg3_ctrl & all_mask) != all_mask)
3121                         return 0;
3122         }
3123         return 1;
3124 }
3125
3126 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3127 {
3128         u32 curadv, reqadv;
3129
3130         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3131                 return 1;
3132
3133         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3134         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3135
3136         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3137                 if (curadv != reqadv)
3138                         return 0;
3139
3140                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3141                         tg3_readphy(tp, MII_LPA, rmtadv);
3142         } else {
3143                 /* Reprogram the advertisement register, even if it
3144                  * does not affect the current link.  If the link
3145                  * gets renegotiated in the future, we can save an
3146                  * additional renegotiation cycle by advertising
3147                  * it correctly in the first place.
3148                  */
3149                 if (curadv != reqadv) {
3150                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3151                                      ADVERTISE_PAUSE_ASYM);
3152                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3153                 }
3154         }
3155
3156         return 1;
3157 }
3158
3159 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3160 {
3161         int current_link_up;
3162         u32 bmsr, val;
3163         u32 lcl_adv, rmt_adv;
3164         u16 current_speed;
3165         u8 current_duplex;
3166         int i, err;
3167
3168         tw32(MAC_EVENT, 0);
3169
3170         tw32_f(MAC_STATUS,
3171              (MAC_STATUS_SYNC_CHANGED |
3172               MAC_STATUS_CFG_CHANGED |
3173               MAC_STATUS_MI_COMPLETION |
3174               MAC_STATUS_LNKSTATE_CHANGED));
3175         udelay(40);
3176
3177         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3178                 tw32_f(MAC_MI_MODE,
3179                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3180                 udelay(80);
3181         }
3182
3183         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3184
3185         /* Some third-party PHYs need to be reset on link going
3186          * down.
3187          */
3188         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3189              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3190              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3191             netif_carrier_ok(tp->dev)) {
3192                 tg3_readphy(tp, MII_BMSR, &bmsr);
3193                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3194                     !(bmsr & BMSR_LSTATUS))
3195                         force_reset = 1;
3196         }
3197         if (force_reset)
3198                 tg3_phy_reset(tp);
3199
3200         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3201                 tg3_readphy(tp, MII_BMSR, &bmsr);
3202                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3203                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3204                         bmsr = 0;
3205
3206                 if (!(bmsr & BMSR_LSTATUS)) {
3207                         err = tg3_init_5401phy_dsp(tp);
3208                         if (err)
3209                                 return err;
3210
3211                         tg3_readphy(tp, MII_BMSR, &bmsr);
3212                         for (i = 0; i < 1000; i++) {
3213                                 udelay(10);
3214                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3215                                     (bmsr & BMSR_LSTATUS)) {
3216                                         udelay(40);
3217                                         break;
3218                                 }
3219                         }
3220
3221                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3222                             TG3_PHY_REV_BCM5401_B0 &&
3223                             !(bmsr & BMSR_LSTATUS) &&
3224                             tp->link_config.active_speed == SPEED_1000) {
3225                                 err = tg3_phy_reset(tp);
3226                                 if (!err)
3227                                         err = tg3_init_5401phy_dsp(tp);
3228                                 if (err)
3229                                         return err;
3230                         }
3231                 }
3232         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3233                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3234                 /* 5701 {A0,B0} CRC bug workaround */
3235                 tg3_writephy(tp, 0x15, 0x0a75);
3236                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3237                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3238                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3239         }
3240
3241         /* Clear pending interrupts... */
3242         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3243         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3244
3245         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3246                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3247         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3248                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3249
3250         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3251             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3252                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3253                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3254                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3255                 else
3256                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3257         }
3258
3259         current_link_up = 0;
3260         current_speed = SPEED_INVALID;
3261         current_duplex = DUPLEX_INVALID;
3262
3263         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3264                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3265                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3266                 if (!(val & (1 << 10))) {
3267                         val |= (1 << 10);
3268                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3269                         goto relink;
3270                 }
3271         }
3272
3273         bmsr = 0;
3274         for (i = 0; i < 100; i++) {
3275                 tg3_readphy(tp, MII_BMSR, &bmsr);
3276                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3277                     (bmsr & BMSR_LSTATUS))
3278                         break;
3279                 udelay(40);
3280         }
3281
3282         if (bmsr & BMSR_LSTATUS) {
3283                 u32 aux_stat, bmcr;
3284
3285                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3286                 for (i = 0; i < 2000; i++) {
3287                         udelay(10);
3288                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3289                             aux_stat)
3290                                 break;
3291                 }
3292
3293                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3294                                              &current_speed,
3295                                              &current_duplex);
3296
3297                 bmcr = 0;
3298                 for (i = 0; i < 200; i++) {
3299                         tg3_readphy(tp, MII_BMCR, &bmcr);
3300                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3301                                 continue;
3302                         if (bmcr && bmcr != 0x7fff)
3303                                 break;
3304                         udelay(10);
3305                 }
3306
3307                 lcl_adv = 0;
3308                 rmt_adv = 0;
3309
3310                 tp->link_config.active_speed = current_speed;
3311                 tp->link_config.active_duplex = current_duplex;
3312
3313                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3314                         if ((bmcr & BMCR_ANENABLE) &&
3315                             tg3_copper_is_advertising_all(tp,
3316                                                 tp->link_config.advertising)) {
3317                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3318                                                                   &rmt_adv))
3319                                         current_link_up = 1;
3320                         }
3321                 } else {
3322                         if (!(bmcr & BMCR_ANENABLE) &&
3323                             tp->link_config.speed == current_speed &&
3324                             tp->link_config.duplex == current_duplex &&
3325                             tp->link_config.flowctrl ==
3326                             tp->link_config.active_flowctrl) {
3327                                 current_link_up = 1;
3328                         }
3329                 }
3330
3331                 if (current_link_up == 1 &&
3332                     tp->link_config.active_duplex == DUPLEX_FULL)
3333                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3334         }
3335
3336 relink:
3337         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3338                 tg3_phy_copper_begin(tp);
3339
3340                 tg3_readphy(tp, MII_BMSR, &bmsr);
3341                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3342                     (bmsr & BMSR_LSTATUS))
3343                         current_link_up = 1;
3344         }
3345
3346         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3347         if (current_link_up == 1) {
3348                 if (tp->link_config.active_speed == SPEED_100 ||
3349                     tp->link_config.active_speed == SPEED_10)
3350                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3351                 else
3352                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3353         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3354                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3355         else
3356                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3357
3358         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3359         if (tp->link_config.active_duplex == DUPLEX_HALF)
3360                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3361
3362         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3363                 if (current_link_up == 1 &&
3364                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3365                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3366                 else
3367                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3368         }
3369
3370         /* ??? Without this setting Netgear GA302T PHY does not
3371          * ??? send/receive packets...
3372          */
3373         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3374             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3375                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3376                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3377                 udelay(80);
3378         }
3379
3380         tw32_f(MAC_MODE, tp->mac_mode);
3381         udelay(40);
3382
3383         tg3_phy_eee_adjust(tp, current_link_up);
3384
3385         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3386                 /* Polled via timer. */
3387                 tw32_f(MAC_EVENT, 0);
3388         } else {
3389                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3390         }
3391         udelay(40);
3392
3393         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3394             current_link_up == 1 &&
3395             tp->link_config.active_speed == SPEED_1000 &&
3396             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3397              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3398                 udelay(120);
3399                 tw32_f(MAC_STATUS,
3400                      (MAC_STATUS_SYNC_CHANGED |
3401                       MAC_STATUS_CFG_CHANGED));
3402                 udelay(40);
3403                 tg3_write_mem(tp,
3404                               NIC_SRAM_FIRMWARE_MBOX,
3405                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3406         }
3407
3408         /* Prevent send BD corruption. */
3409         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3410                 u16 oldlnkctl, newlnkctl;
3411
3412                 pci_read_config_word(tp->pdev,
3413                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3414                                      &oldlnkctl);
3415                 if (tp->link_config.active_speed == SPEED_100 ||
3416                     tp->link_config.active_speed == SPEED_10)
3417                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3418                 else
3419                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3420                 if (newlnkctl != oldlnkctl)
3421                         pci_write_config_word(tp->pdev,
3422                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3423                                               newlnkctl);
3424         }
3425
3426         if (current_link_up != netif_carrier_ok(tp->dev)) {
3427                 if (current_link_up)
3428                         netif_carrier_on(tp->dev);
3429                 else
3430                         netif_carrier_off(tp->dev);
3431                 tg3_link_report(tp);
3432         }
3433
3434         return 0;
3435 }
3436
3437 struct tg3_fiber_aneginfo {
3438         int state;
3439 #define ANEG_STATE_UNKNOWN              0
3440 #define ANEG_STATE_AN_ENABLE            1
3441 #define ANEG_STATE_RESTART_INIT         2
3442 #define ANEG_STATE_RESTART              3
3443 #define ANEG_STATE_DISABLE_LINK_OK      4
3444 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3445 #define ANEG_STATE_ABILITY_DETECT       6
3446 #define ANEG_STATE_ACK_DETECT_INIT      7
3447 #define ANEG_STATE_ACK_DETECT           8
3448 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3449 #define ANEG_STATE_COMPLETE_ACK         10
3450 #define ANEG_STATE_IDLE_DETECT_INIT     11
3451 #define ANEG_STATE_IDLE_DETECT          12
3452 #define ANEG_STATE_LINK_OK              13
3453 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3454 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3455
3456         u32 flags;
3457 #define MR_AN_ENABLE            0x00000001
3458 #define MR_RESTART_AN           0x00000002
3459 #define MR_AN_COMPLETE          0x00000004
3460 #define MR_PAGE_RX              0x00000008
3461 #define MR_NP_LOADED            0x00000010
3462 #define MR_TOGGLE_TX            0x00000020
3463 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3464 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3465 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3466 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3467 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3468 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3469 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3470 #define MR_TOGGLE_RX            0x00002000
3471 #define MR_NP_RX                0x00004000
3472
3473 #define MR_LINK_OK              0x80000000
3474
3475         unsigned long link_time, cur_time;
3476
3477         u32 ability_match_cfg;
3478         int ability_match_count;
3479
3480         char ability_match, idle_match, ack_match;
3481
3482         u32 txconfig, rxconfig;
3483 #define ANEG_CFG_NP             0x00000080
3484 #define ANEG_CFG_ACK            0x00000040
3485 #define ANEG_CFG_RF2            0x00000020
3486 #define ANEG_CFG_RF1            0x00000010
3487 #define ANEG_CFG_PS2            0x00000001
3488 #define ANEG_CFG_PS1            0x00008000
3489 #define ANEG_CFG_HD             0x00004000
3490 #define ANEG_CFG_FD             0x00002000
3491 #define ANEG_CFG_INVAL          0x00001f06
3492
3493 };
3494 #define ANEG_OK         0
3495 #define ANEG_DONE       1
3496 #define ANEG_TIMER_ENAB 2
3497 #define ANEG_FAILED     -1
3498
3499 #define ANEG_STATE_SETTLE_TIME  10000
3500
3501 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3502                                    struct tg3_fiber_aneginfo *ap)
3503 {
3504         u16 flowctrl;
3505         unsigned long delta;
3506         u32 rx_cfg_reg;
3507         int ret;
3508
3509         if (ap->state == ANEG_STATE_UNKNOWN) {
3510                 ap->rxconfig = 0;
3511                 ap->link_time = 0;
3512                 ap->cur_time = 0;
3513                 ap->ability_match_cfg = 0;
3514                 ap->ability_match_count = 0;
3515                 ap->ability_match = 0;
3516                 ap->idle_match = 0;
3517                 ap->ack_match = 0;
3518         }
3519         ap->cur_time++;
3520
3521         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3522                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3523
3524                 if (rx_cfg_reg != ap->ability_match_cfg) {
3525                         ap->ability_match_cfg = rx_cfg_reg;
3526                         ap->ability_match = 0;
3527                         ap->ability_match_count = 0;
3528                 } else {
3529                         if (++ap->ability_match_count > 1) {
3530                                 ap->ability_match = 1;
3531                                 ap->ability_match_cfg = rx_cfg_reg;
3532                         }
3533                 }
3534                 if (rx_cfg_reg & ANEG_CFG_ACK)
3535                         ap->ack_match = 1;
3536                 else
3537                         ap->ack_match = 0;
3538
3539                 ap->idle_match = 0;
3540         } else {
3541                 ap->idle_match = 1;
3542                 ap->ability_match_cfg = 0;
3543                 ap->ability_match_count = 0;
3544                 ap->ability_match = 0;
3545                 ap->ack_match = 0;
3546
3547                 rx_cfg_reg = 0;
3548         }
3549
3550         ap->rxconfig = rx_cfg_reg;
3551         ret = ANEG_OK;
3552
3553         switch (ap->state) {
3554         case ANEG_STATE_UNKNOWN:
3555                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3556                         ap->state = ANEG_STATE_AN_ENABLE;
3557
3558                 /* fallthru */
3559         case ANEG_STATE_AN_ENABLE:
3560                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3561                 if (ap->flags & MR_AN_ENABLE) {
3562                         ap->link_time = 0;
3563                         ap->cur_time = 0;
3564                         ap->ability_match_cfg = 0;
3565                         ap->ability_match_count = 0;
3566                         ap->ability_match = 0;
3567                         ap->idle_match = 0;
3568                         ap->ack_match = 0;
3569
3570                         ap->state = ANEG_STATE_RESTART_INIT;
3571                 } else {
3572                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3573                 }
3574                 break;
3575
3576         case ANEG_STATE_RESTART_INIT:
3577                 ap->link_time = ap->cur_time;
3578                 ap->flags &= ~(MR_NP_LOADED);
3579                 ap->txconfig = 0;
3580                 tw32(MAC_TX_AUTO_NEG, 0);
3581                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3582                 tw32_f(MAC_MODE, tp->mac_mode);
3583                 udelay(40);
3584
3585                 ret = ANEG_TIMER_ENAB;
3586                 ap->state = ANEG_STATE_RESTART;
3587
3588                 /* fallthru */
3589         case ANEG_STATE_RESTART:
3590                 delta = ap->cur_time - ap->link_time;
3591                 if (delta > ANEG_STATE_SETTLE_TIME)
3592                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3593                 else
3594                         ret = ANEG_TIMER_ENAB;
3595                 break;
3596
3597         case ANEG_STATE_DISABLE_LINK_OK:
3598                 ret = ANEG_DONE;
3599                 break;
3600
3601         case ANEG_STATE_ABILITY_DETECT_INIT:
3602                 ap->flags &= ~(MR_TOGGLE_TX);
3603                 ap->txconfig = ANEG_CFG_FD;
3604                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3605                 if (flowctrl & ADVERTISE_1000XPAUSE)
3606                         ap->txconfig |= ANEG_CFG_PS1;
3607                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3608                         ap->txconfig |= ANEG_CFG_PS2;
3609                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3610                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3611                 tw32_f(MAC_MODE, tp->mac_mode);
3612                 udelay(40);
3613
3614                 ap->state = ANEG_STATE_ABILITY_DETECT;
3615                 break;
3616
3617         case ANEG_STATE_ABILITY_DETECT:
3618                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3619                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3620                 break;
3621
3622         case ANEG_STATE_ACK_DETECT_INIT:
3623                 ap->txconfig |= ANEG_CFG_ACK;
3624                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3625                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3626                 tw32_f(MAC_MODE, tp->mac_mode);
3627                 udelay(40);
3628
3629                 ap->state = ANEG_STATE_ACK_DETECT;
3630
3631                 /* fallthru */
3632         case ANEG_STATE_ACK_DETECT:
3633                 if (ap->ack_match != 0) {
3634                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3635                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3636                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3637                         } else {
3638                                 ap->state = ANEG_STATE_AN_ENABLE;
3639                         }
3640                 } else if (ap->ability_match != 0 &&
3641                            ap->rxconfig == 0) {
3642                         ap->state = ANEG_STATE_AN_ENABLE;
3643                 }
3644                 break;
3645
3646         case ANEG_STATE_COMPLETE_ACK_INIT:
3647                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3648                         ret = ANEG_FAILED;
3649                         break;
3650                 }
3651                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3652                                MR_LP_ADV_HALF_DUPLEX |
3653                                MR_LP_ADV_SYM_PAUSE |
3654                                MR_LP_ADV_ASYM_PAUSE |
3655                                MR_LP_ADV_REMOTE_FAULT1 |
3656                                MR_LP_ADV_REMOTE_FAULT2 |
3657                                MR_LP_ADV_NEXT_PAGE |
3658                                MR_TOGGLE_RX |
3659                                MR_NP_RX);
3660                 if (ap->rxconfig & ANEG_CFG_FD)
3661                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3662                 if (ap->rxconfig & ANEG_CFG_HD)
3663                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3664                 if (ap->rxconfig & ANEG_CFG_PS1)
3665                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3666                 if (ap->rxconfig & ANEG_CFG_PS2)
3667                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3668                 if (ap->rxconfig & ANEG_CFG_RF1)
3669                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3670                 if (ap->rxconfig & ANEG_CFG_RF2)
3671                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3672                 if (ap->rxconfig & ANEG_CFG_NP)
3673                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3674
3675                 ap->link_time = ap->cur_time;
3676
3677                 ap->flags ^= (MR_TOGGLE_TX);
3678                 if (ap->rxconfig & 0x0008)
3679                         ap->flags |= MR_TOGGLE_RX;
3680                 if (ap->rxconfig & ANEG_CFG_NP)
3681                         ap->flags |= MR_NP_RX;
3682                 ap->flags |= MR_PAGE_RX;
3683
3684                 ap->state = ANEG_STATE_COMPLETE_ACK;
3685                 ret = ANEG_TIMER_ENAB;
3686                 break;
3687
3688         case ANEG_STATE_COMPLETE_ACK:
3689                 if (ap->ability_match != 0 &&
3690                     ap->rxconfig == 0) {
3691                         ap->state = ANEG_STATE_AN_ENABLE;
3692                         break;
3693                 }
3694                 delta = ap->cur_time - ap->link_time;
3695                 if (delta > ANEG_STATE_SETTLE_TIME) {
3696                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3697                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3698                         } else {
3699                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3700                                     !(ap->flags & MR_NP_RX)) {
3701                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3702                                 } else {
3703                                         ret = ANEG_FAILED;
3704                                 }
3705                         }
3706                 }
3707                 break;
3708
3709         case ANEG_STATE_IDLE_DETECT_INIT:
3710                 ap->link_time = ap->cur_time;
3711                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3712                 tw32_f(MAC_MODE, tp->mac_mode);
3713                 udelay(40);
3714
3715                 ap->state = ANEG_STATE_IDLE_DETECT;
3716                 ret = ANEG_TIMER_ENAB;
3717                 break;
3718
3719         case ANEG_STATE_IDLE_DETECT:
3720                 if (ap->ability_match != 0 &&
3721                     ap->rxconfig == 0) {
3722                         ap->state = ANEG_STATE_AN_ENABLE;
3723                         break;
3724                 }
3725                 delta = ap->cur_time - ap->link_time;
3726                 if (delta > ANEG_STATE_SETTLE_TIME) {
3727                         /* XXX another gem from the Broadcom driver :( */
3728                         ap->state = ANEG_STATE_LINK_OK;
3729                 }
3730                 break;
3731
3732         case ANEG_STATE_LINK_OK:
3733                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3734                 ret = ANEG_DONE;
3735                 break;
3736
3737         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3738                 /* ??? unimplemented */
3739                 break;
3740
3741         case ANEG_STATE_NEXT_PAGE_WAIT:
3742                 /* ??? unimplemented */
3743                 break;
3744
3745         default:
3746                 ret = ANEG_FAILED;
3747                 break;
3748         }
3749
3750         return ret;
3751 }
3752
3753 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3754 {
3755         int res = 0;
3756         struct tg3_fiber_aneginfo aninfo;
3757         int status = ANEG_FAILED;
3758         unsigned int tick;
3759         u32 tmp;
3760
3761         tw32_f(MAC_TX_AUTO_NEG, 0);
3762
3763         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3764         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3765         udelay(40);
3766
3767         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3768         udelay(40);
3769
3770         memset(&aninfo, 0, sizeof(aninfo));
3771         aninfo.flags |= MR_AN_ENABLE;
3772         aninfo.state = ANEG_STATE_UNKNOWN;
3773         aninfo.cur_time = 0;
3774         tick = 0;
3775         while (++tick < 195000) {
3776                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3777                 if (status == ANEG_DONE || status == ANEG_FAILED)
3778                         break;
3779
3780                 udelay(1);
3781         }
3782
3783         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3784         tw32_f(MAC_MODE, tp->mac_mode);
3785         udelay(40);
3786
3787         *txflags = aninfo.txconfig;
3788         *rxflags = aninfo.flags;
3789
3790         if (status == ANEG_DONE &&
3791             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3792                              MR_LP_ADV_FULL_DUPLEX)))
3793                 res = 1;
3794
3795         return res;
3796 }
3797
3798 static void tg3_init_bcm8002(struct tg3 *tp)
3799 {
3800         u32 mac_status = tr32(MAC_STATUS);
3801         int i;
3802
3803         /* Reset when initting first time or we have a link. */
3804         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3805             !(mac_status & MAC_STATUS_PCS_SYNCED))
3806                 return;
3807
3808         /* Set PLL lock range. */
3809         tg3_writephy(tp, 0x16, 0x8007);
3810
3811         /* SW reset */
3812         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3813
3814         /* Wait for reset to complete. */
3815         /* XXX schedule_timeout() ... */
3816         for (i = 0; i < 500; i++)
3817                 udelay(10);
3818
3819         /* Config mode; select PMA/Ch 1 regs. */
3820         tg3_writephy(tp, 0x10, 0x8411);
3821
3822         /* Enable auto-lock and comdet, select txclk for tx. */
3823         tg3_writephy(tp, 0x11, 0x0a10);
3824
3825         tg3_writephy(tp, 0x18, 0x00a0);
3826         tg3_writephy(tp, 0x16, 0x41ff);
3827
3828         /* Assert and deassert POR. */
3829         tg3_writephy(tp, 0x13, 0x0400);
3830         udelay(40);
3831         tg3_writephy(tp, 0x13, 0x0000);
3832
3833         tg3_writephy(tp, 0x11, 0x0a50);
3834         udelay(40);
3835         tg3_writephy(tp, 0x11, 0x0a10);
3836
3837         /* Wait for signal to stabilize */
3838         /* XXX schedule_timeout() ... */
3839         for (i = 0; i < 15000; i++)
3840                 udelay(10);
3841
3842         /* Deselect the channel register so we can read the PHYID
3843          * later.
3844          */
3845         tg3_writephy(tp, 0x10, 0x8011);
3846 }
3847
3848 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3849 {
3850         u16 flowctrl;
3851         u32 sg_dig_ctrl, sg_dig_status;
3852         u32 serdes_cfg, expected_sg_dig_ctrl;
3853         int workaround, port_a;
3854         int current_link_up;
3855
3856         serdes_cfg = 0;
3857         expected_sg_dig_ctrl = 0;
3858         workaround = 0;
3859         port_a = 1;
3860         current_link_up = 0;
3861
3862         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3863             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3864                 workaround = 1;
3865                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3866                         port_a = 0;
3867
3868                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3869                 /* preserve bits 20-23 for voltage regulator */
3870                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3871         }
3872
3873         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3874
3875         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3876                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3877                         if (workaround) {
3878                                 u32 val = serdes_cfg;
3879
3880                                 if (port_a)
3881                                         val |= 0xc010000;
3882                                 else
3883                                         val |= 0x4010000;
3884                                 tw32_f(MAC_SERDES_CFG, val);
3885                         }
3886
3887                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3888                 }
3889                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3890                         tg3_setup_flow_control(tp, 0, 0);
3891                         current_link_up = 1;
3892                 }
3893                 goto out;
3894         }
3895
3896         /* Want auto-negotiation.  */
3897         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3898
3899         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3900         if (flowctrl & ADVERTISE_1000XPAUSE)
3901                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3902         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3903                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3904
3905         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3906                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3907                     tp->serdes_counter &&
3908                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3909                                     MAC_STATUS_RCVD_CFG)) ==
3910                      MAC_STATUS_PCS_SYNCED)) {
3911                         tp->serdes_counter--;
3912                         current_link_up = 1;
3913                         goto out;
3914                 }
3915 restart_autoneg:
3916                 if (workaround)
3917                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3918                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3919                 udelay(5);
3920                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3921
3922                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3923                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3924         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3925                                  MAC_STATUS_SIGNAL_DET)) {
3926                 sg_dig_status = tr32(SG_DIG_STATUS);
3927                 mac_status = tr32(MAC_STATUS);
3928
3929                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3930                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3931                         u32 local_adv = 0, remote_adv = 0;
3932
3933                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3934                                 local_adv |= ADVERTISE_1000XPAUSE;
3935                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3936                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3937
3938                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3939                                 remote_adv |= LPA_1000XPAUSE;
3940                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3941                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3942
3943                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3944                         current_link_up = 1;
3945                         tp->serdes_counter = 0;
3946                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3947                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3948                         if (tp->serdes_counter)
3949                                 tp->serdes_counter--;
3950                         else {
3951                                 if (workaround) {
3952                                         u32 val = serdes_cfg;
3953
3954                                         if (port_a)
3955                                                 val |= 0xc010000;
3956                                         else
3957                                                 val |= 0x4010000;
3958
3959                                         tw32_f(MAC_SERDES_CFG, val);
3960                                 }
3961
3962                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3963                                 udelay(40);
3964
3965                                 /* Link parallel detection - link is up */
3966                                 /* only if we have PCS_SYNC and not */
3967                                 /* receiving config code words */
3968                                 mac_status = tr32(MAC_STATUS);
3969                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3970                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3971                                         tg3_setup_flow_control(tp, 0, 0);
3972                                         current_link_up = 1;
3973                                         tp->phy_flags |=
3974                                                 TG3_PHYFLG_PARALLEL_DETECT;
3975                                         tp->serdes_counter =
3976                                                 SERDES_PARALLEL_DET_TIMEOUT;
3977                                 } else
3978                                         goto restart_autoneg;
3979                         }
3980                 }
3981         } else {
3982                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3983                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3984         }
3985
3986 out:
3987         return current_link_up;
3988 }
3989
3990 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3991 {
3992         int current_link_up = 0;
3993
3994         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3995                 goto out;
3996
3997         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3998                 u32 txflags, rxflags;
3999                 int i;
4000
4001                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4002                         u32 local_adv = 0, remote_adv = 0;
4003
4004                         if (txflags & ANEG_CFG_PS1)
4005                                 local_adv |= ADVERTISE_1000XPAUSE;
4006                         if (txflags & ANEG_CFG_PS2)
4007                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
4008
4009                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
4010                                 remote_adv |= LPA_1000XPAUSE;
4011                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4012                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4013
4014                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4015
4016                         current_link_up = 1;
4017                 }
4018                 for (i = 0; i < 30; i++) {
4019                         udelay(20);
4020                         tw32_f(MAC_STATUS,
4021                                (MAC_STATUS_SYNC_CHANGED |
4022                                 MAC_STATUS_CFG_CHANGED));
4023                         udelay(40);
4024                         if ((tr32(MAC_STATUS) &
4025                              (MAC_STATUS_SYNC_CHANGED |
4026                               MAC_STATUS_CFG_CHANGED)) == 0)
4027                                 break;
4028                 }
4029
4030                 mac_status = tr32(MAC_STATUS);
4031                 if (current_link_up == 0 &&
4032                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4033                     !(mac_status & MAC_STATUS_RCVD_CFG))
4034                         current_link_up = 1;
4035         } else {
4036                 tg3_setup_flow_control(tp, 0, 0);
4037
4038                 /* Forcing 1000FD link up. */
4039                 current_link_up = 1;
4040
4041                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4042                 udelay(40);
4043
4044                 tw32_f(MAC_MODE, tp->mac_mode);
4045                 udelay(40);
4046         }
4047
4048 out:
4049         return current_link_up;
4050 }
4051
4052 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4053 {
4054         u32 orig_pause_cfg;
4055         u16 orig_active_speed;
4056         u8 orig_active_duplex;
4057         u32 mac_status;
4058         int current_link_up;
4059         int i;
4060
4061         orig_pause_cfg = tp->link_config.active_flowctrl;
4062         orig_active_speed = tp->link_config.active_speed;
4063         orig_active_duplex = tp->link_config.active_duplex;
4064
4065         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4066             netif_carrier_ok(tp->dev) &&
4067             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4068                 mac_status = tr32(MAC_STATUS);
4069                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4070                                MAC_STATUS_SIGNAL_DET |
4071                                MAC_STATUS_CFG_CHANGED |
4072                                MAC_STATUS_RCVD_CFG);
4073                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4074                                    MAC_STATUS_SIGNAL_DET)) {
4075                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4076                                             MAC_STATUS_CFG_CHANGED));
4077                         return 0;
4078                 }
4079         }
4080
4081         tw32_f(MAC_TX_AUTO_NEG, 0);
4082
4083         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4084         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4085         tw32_f(MAC_MODE, tp->mac_mode);
4086         udelay(40);
4087
4088         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4089                 tg3_init_bcm8002(tp);
4090
4091         /* Enable link change event even when serdes polling.  */
4092         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4093         udelay(40);
4094
4095         current_link_up = 0;
4096         mac_status = tr32(MAC_STATUS);
4097
4098         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4099                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4100         else
4101                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4102
4103         tp->napi[0].hw_status->status =
4104                 (SD_STATUS_UPDATED |
4105                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4106
4107         for (i = 0; i < 100; i++) {
4108                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4109                                     MAC_STATUS_CFG_CHANGED));
4110                 udelay(5);
4111                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4112                                          MAC_STATUS_CFG_CHANGED |
4113                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4114                         break;
4115         }
4116
4117         mac_status = tr32(MAC_STATUS);
4118         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4119                 current_link_up = 0;
4120                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4121                     tp->serdes_counter == 0) {
4122                         tw32_f(MAC_MODE, (tp->mac_mode |
4123                                           MAC_MODE_SEND_CONFIGS));
4124                         udelay(1);
4125                         tw32_f(MAC_MODE, tp->mac_mode);
4126                 }
4127         }
4128
4129         if (current_link_up == 1) {
4130                 tp->link_config.active_speed = SPEED_1000;
4131                 tp->link_config.active_duplex = DUPLEX_FULL;
4132                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4133                                     LED_CTRL_LNKLED_OVERRIDE |
4134                                     LED_CTRL_1000MBPS_ON));
4135         } else {
4136                 tp->link_config.active_speed = SPEED_INVALID;
4137                 tp->link_config.active_duplex = DUPLEX_INVALID;
4138                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4139                                     LED_CTRL_LNKLED_OVERRIDE |
4140                                     LED_CTRL_TRAFFIC_OVERRIDE));
4141         }
4142
4143         if (current_link_up != netif_carrier_ok(tp->dev)) {
4144                 if (current_link_up)
4145                         netif_carrier_on(tp->dev);
4146                 else
4147                         netif_carrier_off(tp->dev);
4148                 tg3_link_report(tp);
4149         } else {
4150                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4151                 if (orig_pause_cfg != now_pause_cfg ||
4152                     orig_active_speed != tp->link_config.active_speed ||
4153                     orig_active_duplex != tp->link_config.active_duplex)
4154                         tg3_link_report(tp);
4155         }
4156
4157         return 0;
4158 }
4159
4160 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4161 {
4162         int current_link_up, err = 0;
4163         u32 bmsr, bmcr;
4164         u16 current_speed;
4165         u8 current_duplex;
4166         u32 local_adv, remote_adv;
4167
4168         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4169         tw32_f(MAC_MODE, tp->mac_mode);
4170         udelay(40);
4171
4172         tw32(MAC_EVENT, 0);
4173
4174         tw32_f(MAC_STATUS,
4175              (MAC_STATUS_SYNC_CHANGED |
4176               MAC_STATUS_CFG_CHANGED |
4177               MAC_STATUS_MI_COMPLETION |
4178               MAC_STATUS_LNKSTATE_CHANGED));
4179         udelay(40);
4180
4181         if (force_reset)
4182                 tg3_phy_reset(tp);
4183
4184         current_link_up = 0;
4185         current_speed = SPEED_INVALID;
4186         current_duplex = DUPLEX_INVALID;
4187
4188         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4189         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4190         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4191                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4192                         bmsr |= BMSR_LSTATUS;
4193                 else
4194                         bmsr &= ~BMSR_LSTATUS;
4195         }
4196
4197         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4198
4199         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4200             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4201                 /* do nothing, just check for link up at the end */
4202         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4203                 u32 adv, new_adv;
4204
4205                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4206                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4207                                   ADVERTISE_1000XPAUSE |
4208                                   ADVERTISE_1000XPSE_ASYM |
4209                                   ADVERTISE_SLCT);
4210
4211                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4212
4213                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4214                         new_adv |= ADVERTISE_1000XHALF;
4215                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4216                         new_adv |= ADVERTISE_1000XFULL;
4217
4218                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4219                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4220                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4221                         tg3_writephy(tp, MII_BMCR, bmcr);
4222
4223                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4224                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4225                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4226
4227                         return err;
4228                 }
4229         } else {
4230                 u32 new_bmcr;
4231
4232                 bmcr &= ~BMCR_SPEED1000;
4233                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4234
4235                 if (tp->link_config.duplex == DUPLEX_FULL)
4236                         new_bmcr |= BMCR_FULLDPLX;
4237
4238                 if (new_bmcr != bmcr) {
4239                         /* BMCR_SPEED1000 is a reserved bit that needs
4240                          * to be set on write.
4241                          */
4242                         new_bmcr |= BMCR_SPEED1000;
4243
4244                         /* Force a linkdown */
4245                         if (netif_carrier_ok(tp->dev)) {
4246                                 u32 adv;
4247
4248                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4249                                 adv &= ~(ADVERTISE_1000XFULL |
4250                                          ADVERTISE_1000XHALF |
4251                                          ADVERTISE_SLCT);
4252                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4253                                 tg3_writephy(tp, MII_BMCR, bmcr |
4254                                                            BMCR_ANRESTART |
4255                                                            BMCR_ANENABLE);
4256                                 udelay(10);
4257                                 netif_carrier_off(tp->dev);
4258                         }
4259                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4260                         bmcr = new_bmcr;
4261                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4262                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4263                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4264                             ASIC_REV_5714) {
4265                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4266                                         bmsr |= BMSR_LSTATUS;
4267                                 else
4268                                         bmsr &= ~BMSR_LSTATUS;
4269                         }
4270                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4271                 }
4272         }
4273
4274         if (bmsr & BMSR_LSTATUS) {
4275                 current_speed = SPEED_1000;
4276                 current_link_up = 1;
4277                 if (bmcr & BMCR_FULLDPLX)
4278                         current_duplex = DUPLEX_FULL;
4279                 else
4280                         current_duplex = DUPLEX_HALF;
4281
4282                 local_adv = 0;
4283                 remote_adv = 0;
4284
4285                 if (bmcr & BMCR_ANENABLE) {
4286                         u32 common;
4287
4288                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4289                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4290                         common = local_adv & remote_adv;
4291                         if (common & (ADVERTISE_1000XHALF |
4292                                       ADVERTISE_1000XFULL)) {
4293                                 if (common & ADVERTISE_1000XFULL)
4294                                         current_duplex = DUPLEX_FULL;
4295                                 else
4296                                         current_duplex = DUPLEX_HALF;
4297                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4298                                 /* Link is up via parallel detect */
4299                         } else {
4300                                 current_link_up = 0;
4301                         }
4302                 }
4303         }
4304
4305         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4306                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4307
4308         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4309         if (tp->link_config.active_duplex == DUPLEX_HALF)
4310                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4311
4312         tw32_f(MAC_MODE, tp->mac_mode);
4313         udelay(40);
4314
4315         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4316
4317         tp->link_config.active_speed = current_speed;
4318         tp->link_config.active_duplex = current_duplex;
4319
4320         if (current_link_up != netif_carrier_ok(tp->dev)) {
4321                 if (current_link_up)
4322                         netif_carrier_on(tp->dev);
4323                 else {
4324                         netif_carrier_off(tp->dev);
4325                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4326                 }
4327                 tg3_link_report(tp);
4328         }
4329         return err;
4330 }
4331
4332 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4333 {
4334         if (tp->serdes_counter) {
4335                 /* Give autoneg time to complete. */
4336                 tp->serdes_counter--;
4337                 return;
4338         }
4339
4340         if (!netif_carrier_ok(tp->dev) &&
4341             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4342                 u32 bmcr;
4343
4344                 tg3_readphy(tp, MII_BMCR, &bmcr);
4345                 if (bmcr & BMCR_ANENABLE) {
4346                         u32 phy1, phy2;
4347
4348                         /* Select shadow register 0x1f */
4349                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4350                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4351
4352                         /* Select expansion interrupt status register */
4353                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4354                                          MII_TG3_DSP_EXP1_INT_STAT);
4355                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4356                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4357
4358                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4359                                 /* We have signal detect and not receiving
4360                                  * config code words, link is up by parallel
4361                                  * detection.
4362                                  */
4363
4364                                 bmcr &= ~BMCR_ANENABLE;
4365                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4366                                 tg3_writephy(tp, MII_BMCR, bmcr);
4367                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4368                         }
4369                 }
4370         } else if (netif_carrier_ok(tp->dev) &&
4371                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4372                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4373                 u32 phy2;
4374
4375                 /* Select expansion interrupt status register */
4376                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4377                                  MII_TG3_DSP_EXP1_INT_STAT);
4378                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4379                 if (phy2 & 0x20) {
4380                         u32 bmcr;
4381
4382                         /* Config code words received, turn on autoneg. */
4383                         tg3_readphy(tp, MII_BMCR, &bmcr);
4384                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4385
4386                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4387
4388                 }
4389         }
4390 }
4391
4392 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4393 {
4394         u32 val;
4395         int err;
4396
4397         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4398                 err = tg3_setup_fiber_phy(tp, force_reset);
4399         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4400                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4401         else
4402                 err = tg3_setup_copper_phy(tp, force_reset);
4403
4404         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4405                 u32 scale;
4406
4407                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4408                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4409                         scale = 65;
4410                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4411                         scale = 6;
4412                 else
4413                         scale = 12;
4414
4415                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4416                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4417                 tw32(GRC_MISC_CFG, val);
4418         }
4419
4420         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4421               (6 << TX_LENGTHS_IPG_SHIFT);
4422         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
4423                 val |= tr32(MAC_TX_LENGTHS) &
4424                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
4425                         TX_LENGTHS_CNT_DWN_VAL_MSK);
4426
4427         if (tp->link_config.active_speed == SPEED_1000 &&
4428             tp->link_config.active_duplex == DUPLEX_HALF)
4429                 tw32(MAC_TX_LENGTHS, val |
4430                      (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
4431         else
4432                 tw32(MAC_TX_LENGTHS, val |
4433                      (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
4434
4435         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4436                 if (netif_carrier_ok(tp->dev)) {
4437                         tw32(HOSTCC_STAT_COAL_TICKS,
4438                              tp->coal.stats_block_coalesce_usecs);
4439                 } else {
4440                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4441                 }
4442         }
4443
4444         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4445                 val = tr32(PCIE_PWR_MGMT_THRESH);
4446                 if (!netif_carrier_ok(tp->dev))
4447                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4448                               tp->pwrmgmt_thresh;
4449                 else
4450                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4451                 tw32(PCIE_PWR_MGMT_THRESH, val);
4452         }
4453
4454         return err;
4455 }
4456
4457 static inline int tg3_irq_sync(struct tg3 *tp)
4458 {
4459         return tp->irq_sync;
4460 }
4461
4462 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
4463 {
4464         int i;
4465
4466         dst = (u32 *)((u8 *)dst + off);
4467         for (i = 0; i < len; i += sizeof(u32))
4468                 *dst++ = tr32(off + i);
4469 }
4470
4471 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
4472 {
4473         tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
4474         tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
4475         tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
4476         tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
4477         tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
4478         tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
4479         tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
4480         tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
4481         tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
4482         tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
4483         tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
4484         tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
4485         tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
4486         tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
4487         tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
4488         tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
4489         tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
4490         tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
4491         tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
4492
4493         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX)
4494                 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
4495
4496         tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
4497         tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
4498         tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
4499         tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
4500         tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
4501         tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
4502         tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
4503         tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
4504
4505         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4506                 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
4507                 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
4508                 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
4509         }
4510
4511         tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
4512         tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
4513         tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
4514         tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
4515         tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
4516
4517         if (tp->tg3_flags & TG3_FLAG_NVRAM)
4518                 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
4519 }
4520
4521 static void tg3_dump_state(struct tg3 *tp)
4522 {
4523         int i;
4524         u32 *regs;
4525
4526         regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
4527         if (!regs) {
4528                 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
4529                 return;
4530         }
4531
4532         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4533                 /* Read up to but not including private PCI registers */
4534                 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
4535                         regs[i / sizeof(u32)] = tr32(i);
4536         } else
4537                 tg3_dump_legacy_regs(tp, regs);
4538
4539         for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
4540                 if (!regs[i + 0] && !regs[i + 1] &&
4541                     !regs[i + 2] && !regs[i + 3])
4542                         continue;
4543
4544                 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
4545                            i * 4,
4546                            regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
4547         }
4548
4549         kfree(regs);
4550
4551         for (i = 0; i < tp->irq_cnt; i++) {
4552                 struct tg3_napi *tnapi = &tp->napi[i];
4553
4554                 /* SW status block */
4555                 netdev_err(tp->dev,
4556                          "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
4557                            i,
4558                            tnapi->hw_status->status,
4559                            tnapi->hw_status->status_tag,
4560                            tnapi->hw_status->rx_jumbo_consumer,
4561                            tnapi->hw_status->rx_consumer,
4562                            tnapi->hw_status->rx_mini_consumer,
4563                            tnapi->hw_status->idx[0].rx_producer,
4564                            tnapi->hw_status->idx[0].tx_consumer);
4565
4566                 netdev_err(tp->dev,
4567                 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
4568                            i,
4569                            tnapi->last_tag, tnapi->last_irq_tag,
4570                            tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
4571                            tnapi->rx_rcb_ptr,
4572                            tnapi->prodring.rx_std_prod_idx,
4573                            tnapi->prodring.rx_std_cons_idx,
4574                            tnapi->prodring.rx_jmb_prod_idx,
4575                            tnapi->prodring.rx_jmb_cons_idx);
4576         }
4577 }
4578
4579 /* This is called whenever we suspect that the system chipset is re-
4580  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4581  * is bogus tx completions. We try to recover by setting the
4582  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4583  * in the workqueue.
4584  */
4585 static void tg3_tx_recover(struct tg3 *tp)
4586 {
4587         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4588                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4589
4590         netdev_warn(tp->dev,
4591                     "The system may be re-ordering memory-mapped I/O "
4592                     "cycles to the network device, attempting to recover. "
4593                     "Please report the problem to the driver maintainer "
4594                     "and include system chipset information.\n");
4595
4596         spin_lock(&tp->lock);
4597         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4598         spin_unlock(&tp->lock);
4599 }
4600
4601 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4602 {
4603         /* Tell compiler to fetch tx indices from memory. */
4604         barrier();
4605         return tnapi->tx_pending -
4606                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4607 }
4608
4609 /* Tigon3 never reports partial packet sends.  So we do not
4610  * need special logic to handle SKBs that have not had all
4611  * of their frags sent yet, like SunGEM does.
4612  */
4613 static void tg3_tx(struct tg3_napi *tnapi)
4614 {
4615         struct tg3 *tp = tnapi->tp;
4616         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4617         u32 sw_idx = tnapi->tx_cons;
4618         struct netdev_queue *txq;
4619         int index = tnapi - tp->napi;
4620
4621         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4622                 index--;
4623
4624         txq = netdev_get_tx_queue(tp->dev, index);
4625
4626         while (sw_idx != hw_idx) {
4627                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4628                 struct sk_buff *skb = ri->skb;
4629                 int i, tx_bug = 0;
4630
4631                 if (unlikely(skb == NULL)) {
4632                         tg3_tx_recover(tp);
4633                         return;
4634                 }
4635
4636                 pci_unmap_single(tp->pdev,
4637                                  dma_unmap_addr(ri, mapping),
4638                                  skb_headlen(skb),
4639                                  PCI_DMA_TODEVICE);
4640
4641                 ri->skb = NULL;
4642
4643                 sw_idx = NEXT_TX(sw_idx);
4644
4645                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4646                         ri = &tnapi->tx_buffers[sw_idx];
4647                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4648                                 tx_bug = 1;
4649
4650                         pci_unmap_page(tp->pdev,
4651                                        dma_unmap_addr(ri, mapping),
4652                                        skb_shinfo(skb)->frags[i].size,
4653                                        PCI_DMA_TODEVICE);
4654                         sw_idx = NEXT_TX(sw_idx);
4655                 }
4656
4657                 dev_kfree_skb(skb);
4658
4659                 if (unlikely(tx_bug)) {
4660                         tg3_tx_recover(tp);
4661                         return;
4662                 }
4663         }
4664
4665         tnapi->tx_cons = sw_idx;
4666
4667         /* Need to make the tx_cons update visible to tg3_start_xmit()
4668          * before checking for netif_queue_stopped().  Without the
4669          * memory barrier, there is a small possibility that tg3_start_xmit()
4670          * will miss it and cause the queue to be stopped forever.
4671          */
4672         smp_mb();
4673
4674         if (unlikely(netif_tx_queue_stopped(txq) &&
4675                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4676                 __netif_tx_lock(txq, smp_processor_id());
4677                 if (netif_tx_queue_stopped(txq) &&
4678                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4679                         netif_tx_wake_queue(txq);
4680                 __netif_tx_unlock(txq);
4681         }
4682 }
4683
4684 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4685 {
4686         if (!ri->skb)
4687                 return;
4688
4689         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4690                          map_sz, PCI_DMA_FROMDEVICE);
4691         dev_kfree_skb_any(ri->skb);
4692         ri->skb = NULL;
4693 }
4694
4695 /* Returns size of skb allocated or < 0 on error.
4696  *
4697  * We only need to fill in the address because the other members
4698  * of the RX descriptor are invariant, see tg3_init_rings.
4699  *
4700  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4701  * posting buffers we only dirty the first cache line of the RX
4702  * descriptor (containing the address).  Whereas for the RX status
4703  * buffers the cpu only reads the last cacheline of the RX descriptor
4704  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4705  */
4706 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4707                             u32 opaque_key, u32 dest_idx_unmasked)
4708 {
4709         struct tg3_rx_buffer_desc *desc;
4710         struct ring_info *map;
4711         struct sk_buff *skb;
4712         dma_addr_t mapping;
4713         int skb_size, dest_idx;
4714
4715         switch (opaque_key) {
4716         case RXD_OPAQUE_RING_STD:
4717                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4718                 desc = &tpr->rx_std[dest_idx];
4719                 map = &tpr->rx_std_buffers[dest_idx];
4720                 skb_size = tp->rx_pkt_map_sz;
4721                 break;
4722
4723         case RXD_OPAQUE_RING_JUMBO:
4724                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4725                 desc = &tpr->rx_jmb[dest_idx].std;
4726                 map = &tpr->rx_jmb_buffers[dest_idx];
4727                 skb_size = TG3_RX_JMB_MAP_SZ;
4728                 break;
4729
4730         default:
4731                 return -EINVAL;
4732         }
4733
4734         /* Do not overwrite any of the map or rp information
4735          * until we are sure we can commit to a new buffer.
4736          *
4737          * Callers depend upon this behavior and assume that
4738          * we leave everything unchanged if we fail.
4739          */
4740         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4741         if (skb == NULL)
4742                 return -ENOMEM;
4743
4744         skb_reserve(skb, tp->rx_offset);
4745
4746         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4747                                  PCI_DMA_FROMDEVICE);
4748         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4749                 dev_kfree_skb(skb);
4750                 return -EIO;
4751         }
4752
4753         map->skb = skb;
4754         dma_unmap_addr_set(map, mapping, mapping);
4755
4756         desc->addr_hi = ((u64)mapping >> 32);
4757         desc->addr_lo = ((u64)mapping & 0xffffffff);
4758
4759         return skb_size;
4760 }
4761
4762 /* We only need to move over in the address because the other
4763  * members of the RX descriptor are invariant.  See notes above
4764  * tg3_alloc_rx_skb for full details.
4765  */
4766 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4767                            struct tg3_rx_prodring_set *dpr,
4768                            u32 opaque_key, int src_idx,
4769                            u32 dest_idx_unmasked)
4770 {
4771         struct tg3 *tp = tnapi->tp;
4772         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4773         struct ring_info *src_map, *dest_map;
4774         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4775         int dest_idx;
4776
4777         switch (opaque_key) {
4778         case RXD_OPAQUE_RING_STD:
4779                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4780                 dest_desc = &dpr->rx_std[dest_idx];
4781                 dest_map = &dpr->rx_std_buffers[dest_idx];
4782                 src_desc = &spr->rx_std[src_idx];
4783                 src_map = &spr->rx_std_buffers[src_idx];
4784                 break;
4785
4786         case RXD_OPAQUE_RING_JUMBO:
4787                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4788                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4789                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4790                 src_desc = &spr->rx_jmb[src_idx].std;
4791                 src_map = &spr->rx_jmb_buffers[src_idx];
4792                 break;
4793
4794         default:
4795                 return;
4796         }
4797
4798         dest_map->skb = src_map->skb;
4799         dma_unmap_addr_set(dest_map, mapping,
4800                            dma_unmap_addr(src_map, mapping));
4801         dest_desc->addr_hi = src_desc->addr_hi;
4802         dest_desc->addr_lo = src_desc->addr_lo;
4803
4804         /* Ensure that the update to the skb happens after the physical
4805          * addresses have been transferred to the new BD location.
4806          */
4807         smp_wmb();
4808
4809         src_map->skb = NULL;
4810 }
4811
4812 /* The RX ring scheme is composed of multiple rings which post fresh
4813  * buffers to the chip, and one special ring the chip uses to report
4814  * status back to the host.
4815  *
4816  * The special ring reports the status of received packets to the
4817  * host.  The chip does not write into the original descriptor the
4818  * RX buffer was obtained from.  The chip simply takes the original
4819  * descriptor as provided by the host, updates the status and length
4820  * field, then writes this into the next status ring entry.
4821  *
4822  * Each ring the host uses to post buffers to the chip is described
4823  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4824  * it is first placed into the on-chip ram.  When the packet's length
4825  * is known, it walks down the TG3_BDINFO entries to select the ring.
4826  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4827  * which is within the range of the new packet's length is chosen.
4828  *
4829  * The "separate ring for rx status" scheme may sound queer, but it makes
4830  * sense from a cache coherency perspective.  If only the host writes
4831  * to the buffer post rings, and only the chip writes to the rx status
4832  * rings, then cache lines never move beyond shared-modified state.
4833  * If both the host and chip were to write into the same ring, cache line
4834  * eviction could occur since both entities want it in an exclusive state.
4835  */
4836 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4837 {
4838         struct tg3 *tp = tnapi->tp;
4839         u32 work_mask, rx_std_posted = 0;
4840         u32 std_prod_idx, jmb_prod_idx;
4841         u32 sw_idx = tnapi->rx_rcb_ptr;
4842         u16 hw_idx;
4843         int received;
4844         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4845
4846         hw_idx = *(tnapi->rx_rcb_prod_idx);
4847         /*
4848          * We need to order the read of hw_idx and the read of
4849          * the opaque cookie.
4850          */
4851         rmb();
4852         work_mask = 0;
4853         received = 0;
4854         std_prod_idx = tpr->rx_std_prod_idx;
4855         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4856         while (sw_idx != hw_idx && budget > 0) {
4857                 struct ring_info *ri;
4858                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4859                 unsigned int len;
4860                 struct sk_buff *skb;
4861                 dma_addr_t dma_addr;
4862                 u32 opaque_key, desc_idx, *post_ptr;
4863
4864                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4865                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4866                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4867                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4868                         dma_addr = dma_unmap_addr(ri, mapping);
4869                         skb = ri->skb;
4870                         post_ptr = &std_prod_idx;
4871                         rx_std_posted++;
4872                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4873                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4874                         dma_addr = dma_unmap_addr(ri, mapping);
4875                         skb = ri->skb;
4876                         post_ptr = &jmb_prod_idx;
4877                 } else
4878                         goto next_pkt_nopost;
4879
4880                 work_mask |= opaque_key;
4881
4882                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4883                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4884                 drop_it:
4885                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4886                                        desc_idx, *post_ptr);
4887                 drop_it_no_recycle:
4888                         /* Other statistics kept track of by card. */
4889                         tp->rx_dropped++;
4890                         goto next_pkt;
4891                 }
4892
4893                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4894                       ETH_FCS_LEN;
4895
4896                 if (len > TG3_RX_COPY_THRESH(tp)) {
4897                         int skb_size;
4898
4899                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4900                                                     *post_ptr);
4901                         if (skb_size < 0)
4902                                 goto drop_it;
4903
4904                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4905                                          PCI_DMA_FROMDEVICE);
4906
4907                         /* Ensure that the update to the skb happens
4908                          * after the usage of the old DMA mapping.
4909                          */
4910                         smp_wmb();
4911
4912                         ri->skb = NULL;
4913
4914                         skb_put(skb, len);
4915                 } else {
4916                         struct sk_buff *copy_skb;
4917
4918                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4919                                        desc_idx, *post_ptr);
4920
4921                         copy_skb = netdev_alloc_skb(tp->dev, len +
4922                                                     TG3_RAW_IP_ALIGN);
4923                         if (copy_skb == NULL)
4924                                 goto drop_it_no_recycle;
4925
4926                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4927                         skb_put(copy_skb, len);
4928                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4929                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4930                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4931
4932                         /* We'll reuse the original ring buffer. */
4933                         skb = copy_skb;
4934                 }
4935
4936                 if ((tp->dev->features & NETIF_F_RXCSUM) &&
4937                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4938                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4939                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4940                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4941                 else
4942                         skb_checksum_none_assert(skb);
4943
4944                 skb->protocol = eth_type_trans(skb, tp->dev);
4945
4946                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4947                     skb->protocol != htons(ETH_P_8021Q)) {
4948                         dev_kfree_skb(skb);
4949                         goto drop_it_no_recycle;
4950                 }
4951
4952                 if (desc->type_flags & RXD_FLAG_VLAN &&
4953                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4954                         __vlan_hwaccel_put_tag(skb,
4955                                                desc->err_vlan & RXD_VLAN_MASK);
4956
4957                 napi_gro_receive(&tnapi->napi, skb);
4958
4959                 received++;
4960                 budget--;
4961
4962 next_pkt:
4963                 (*post_ptr)++;
4964
4965                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4966                         tpr->rx_std_prod_idx = std_prod_idx &
4967                                                tp->rx_std_ring_mask;
4968                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4969                                      tpr->rx_std_prod_idx);
4970                         work_mask &= ~RXD_OPAQUE_RING_STD;
4971                         rx_std_posted = 0;
4972                 }
4973 next_pkt_nopost:
4974                 sw_idx++;
4975                 sw_idx &= tp->rx_ret_ring_mask;
4976
4977                 /* Refresh hw_idx to see if there is new work */
4978                 if (sw_idx == hw_idx) {
4979                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4980                         rmb();
4981                 }
4982         }
4983
4984         /* ACK the status ring. */
4985         tnapi->rx_rcb_ptr = sw_idx;
4986         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4987
4988         /* Refill RX ring(s). */
4989         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4990                 if (work_mask & RXD_OPAQUE_RING_STD) {
4991                         tpr->rx_std_prod_idx = std_prod_idx &
4992                                                tp->rx_std_ring_mask;
4993                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4994                                      tpr->rx_std_prod_idx);
4995                 }
4996                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4997                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4998                                                tp->rx_jmb_ring_mask;
4999                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5000                                      tpr->rx_jmb_prod_idx);
5001                 }
5002                 mmiowb();
5003         } else if (work_mask) {
5004                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5005                  * updated before the producer indices can be updated.
5006                  */
5007                 smp_wmb();
5008
5009                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5010                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5011
5012                 if (tnapi != &tp->napi[1])
5013                         napi_schedule(&tp->napi[1].napi);
5014         }
5015
5016         return received;
5017 }
5018
5019 static void tg3_poll_link(struct tg3 *tp)
5020 {
5021         /* handle link change and other phy events */
5022         if (!(tp->tg3_flags &
5023               (TG3_FLAG_USE_LINKCHG_REG |
5024                TG3_FLAG_POLL_SERDES))) {
5025                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5026
5027                 if (sblk->status & SD_STATUS_LINK_CHG) {
5028                         sblk->status = SD_STATUS_UPDATED |
5029                                        (sblk->status & ~SD_STATUS_LINK_CHG);
5030                         spin_lock(&tp->lock);
5031                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
5032                                 tw32_f(MAC_STATUS,
5033                                      (MAC_STATUS_SYNC_CHANGED |
5034                                       MAC_STATUS_CFG_CHANGED |
5035                                       MAC_STATUS_MI_COMPLETION |
5036                                       MAC_STATUS_LNKSTATE_CHANGED));
5037                                 udelay(40);
5038                         } else
5039                                 tg3_setup_phy(tp, 0);
5040                         spin_unlock(&tp->lock);
5041                 }
5042         }
5043 }
5044
5045 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5046                                 struct tg3_rx_prodring_set *dpr,
5047                                 struct tg3_rx_prodring_set *spr)
5048 {
5049         u32 si, di, cpycnt, src_prod_idx;
5050         int i, err = 0;
5051
5052         while (1) {
5053                 src_prod_idx = spr->rx_std_prod_idx;
5054
5055                 /* Make sure updates to the rx_std_buffers[] entries and the
5056                  * standard producer index are seen in the correct order.
5057                  */
5058                 smp_rmb();
5059
5060                 if (spr->rx_std_cons_idx == src_prod_idx)
5061                         break;
5062
5063                 if (spr->rx_std_cons_idx < src_prod_idx)
5064                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5065                 else
5066                         cpycnt = tp->rx_std_ring_mask + 1 -
5067                                  spr->rx_std_cons_idx;
5068
5069                 cpycnt = min(cpycnt,
5070                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
5071
5072                 si = spr->rx_std_cons_idx;
5073                 di = dpr->rx_std_prod_idx;
5074
5075                 for (i = di; i < di + cpycnt; i++) {
5076                         if (dpr->rx_std_buffers[i].skb) {
5077                                 cpycnt = i - di;
5078                                 err = -ENOSPC;
5079                                 break;
5080                         }
5081                 }
5082
5083                 if (!cpycnt)
5084                         break;
5085
5086                 /* Ensure that updates to the rx_std_buffers ring and the
5087                  * shadowed hardware producer ring from tg3_recycle_skb() are
5088                  * ordered correctly WRT the skb check above.
5089                  */
5090                 smp_rmb();
5091
5092                 memcpy(&dpr->rx_std_buffers[di],
5093                        &spr->rx_std_buffers[si],
5094                        cpycnt * sizeof(struct ring_info));
5095
5096                 for (i = 0; i < cpycnt; i++, di++, si++) {
5097                         struct tg3_rx_buffer_desc *sbd, *dbd;
5098                         sbd = &spr->rx_std[si];
5099                         dbd = &dpr->rx_std[di];
5100                         dbd->addr_hi = sbd->addr_hi;
5101                         dbd->addr_lo = sbd->addr_lo;
5102                 }
5103
5104                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5105                                        tp->rx_std_ring_mask;
5106                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5107                                        tp->rx_std_ring_mask;
5108         }
5109
5110         while (1) {
5111                 src_prod_idx = spr->rx_jmb_prod_idx;
5112
5113                 /* Make sure updates to the rx_jmb_buffers[] entries and
5114                  * the jumbo producer index are seen in the correct order.
5115                  */
5116                 smp_rmb();
5117
5118                 if (spr->rx_jmb_cons_idx == src_prod_idx)
5119                         break;
5120
5121                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5122                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5123                 else
5124                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5125                                  spr->rx_jmb_cons_idx;
5126
5127                 cpycnt = min(cpycnt,
5128                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5129
5130                 si = spr->rx_jmb_cons_idx;
5131                 di = dpr->rx_jmb_prod_idx;
5132
5133                 for (i = di; i < di + cpycnt; i++) {
5134                         if (dpr->rx_jmb_buffers[i].skb) {
5135                                 cpycnt = i - di;
5136                                 err = -ENOSPC;
5137                                 break;
5138                         }
5139                 }
5140
5141                 if (!cpycnt)
5142                         break;
5143
5144                 /* Ensure that updates to the rx_jmb_buffers ring and the
5145                  * shadowed hardware producer ring from tg3_recycle_skb() are
5146                  * ordered correctly WRT the skb check above.
5147                  */
5148                 smp_rmb();
5149
5150                 memcpy(&dpr->rx_jmb_buffers[di],
5151                        &spr->rx_jmb_buffers[si],
5152                        cpycnt * sizeof(struct ring_info));
5153
5154                 for (i = 0; i < cpycnt; i++, di++, si++) {
5155                         struct tg3_rx_buffer_desc *sbd, *dbd;
5156                         sbd = &spr->rx_jmb[si].std;
5157                         dbd = &dpr->rx_jmb[di].std;
5158                         dbd->addr_hi = sbd->addr_hi;
5159                         dbd->addr_lo = sbd->addr_lo;
5160                 }
5161
5162                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5163                                        tp->rx_jmb_ring_mask;
5164                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5165                                        tp->rx_jmb_ring_mask;
5166         }
5167
5168         return err;
5169 }
5170
5171 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5172 {
5173         struct tg3 *tp = tnapi->tp;
5174
5175         /* run TX completion thread */
5176         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5177                 tg3_tx(tnapi);
5178                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5179                         return work_done;
5180         }
5181
5182         /* run RX thread, within the bounds set by NAPI.
5183          * All RX "locking" is done by ensuring outside
5184          * code synchronizes with tg3->napi.poll()
5185          */
5186         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5187                 work_done += tg3_rx(tnapi, budget - work_done);
5188
5189         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5190                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5191                 int i, err = 0;
5192                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5193                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5194
5195                 for (i = 1; i < tp->irq_cnt; i++)
5196                         err |= tg3_rx_prodring_xfer(tp, dpr,
5197                                                     &tp->napi[i].prodring);
5198
5199                 wmb();
5200
5201                 if (std_prod_idx != dpr->rx_std_prod_idx)
5202                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5203                                      dpr->rx_std_prod_idx);
5204
5205                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5206                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5207                                      dpr->rx_jmb_prod_idx);
5208
5209                 mmiowb();
5210
5211                 if (err)
5212                         tw32_f(HOSTCC_MODE, tp->coal_now);
5213         }
5214
5215         return work_done;
5216 }
5217
5218 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5219 {
5220         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5221         struct tg3 *tp = tnapi->tp;
5222         int work_done = 0;
5223         struct tg3_hw_status *sblk = tnapi->hw_status;
5224
5225         while (1) {
5226                 work_done = tg3_poll_work(tnapi, work_done, budget);
5227
5228                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5229                         goto tx_recovery;
5230
5231                 if (unlikely(work_done >= budget))
5232                         break;
5233
5234                 /* tp->last_tag is used in tg3_int_reenable() below
5235                  * to tell the hw how much work has been processed,
5236                  * so we must read it before checking for more work.
5237                  */
5238                 tnapi->last_tag = sblk->status_tag;
5239                 tnapi->last_irq_tag = tnapi->last_tag;
5240                 rmb();
5241
5242                 /* check for RX/TX work to do */
5243                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5244                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5245                         napi_complete(napi);
5246                         /* Reenable interrupts. */
5247                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5248                         mmiowb();
5249                         break;
5250                 }
5251         }
5252
5253         return work_done;
5254
5255 tx_recovery:
5256         /* work_done is guaranteed to be less than budget. */
5257         napi_complete(napi);
5258         schedule_work(&tp->reset_task);
5259         return work_done;
5260 }
5261
5262 static int tg3_poll(struct napi_struct *napi, int budget)
5263 {
5264         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5265         struct tg3 *tp = tnapi->tp;
5266         int work_done = 0;
5267         struct tg3_hw_status *sblk = tnapi->hw_status;
5268
5269         while (1) {
5270                 tg3_poll_link(tp);
5271
5272                 work_done = tg3_poll_work(tnapi, work_done, budget);
5273
5274                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5275                         goto tx_recovery;
5276
5277                 if (unlikely(work_done >= budget))
5278                         break;
5279
5280                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5281                         /* tp->last_tag is used in tg3_int_reenable() below
5282                          * to tell the hw how much work has been processed,
5283                          * so we must read it before checking for more work.
5284                          */
5285                         tnapi->last_tag = sblk->status_tag;
5286                         tnapi->last_irq_tag = tnapi->last_tag;
5287                         rmb();
5288                 } else
5289                         sblk->status &= ~SD_STATUS_UPDATED;
5290
5291                 if (likely(!tg3_has_work(tnapi))) {
5292                         napi_complete(napi);
5293                         tg3_int_reenable(tnapi);
5294                         break;
5295                 }
5296         }
5297
5298         return work_done;
5299
5300 tx_recovery:
5301         /* work_done is guaranteed to be less than budget. */
5302         napi_complete(napi);
5303         schedule_work(&tp->reset_task);
5304         return work_done;
5305 }
5306
5307 static void tg3_napi_disable(struct tg3 *tp)
5308 {
5309         int i;
5310
5311         for (i = tp->irq_cnt - 1; i >= 0; i--)
5312                 napi_disable(&tp->napi[i].napi);
5313 }
5314
5315 static void tg3_napi_enable(struct tg3 *tp)
5316 {
5317         int i;
5318
5319         for (i = 0; i < tp->irq_cnt; i++)
5320                 napi_enable(&tp->napi[i].napi);
5321 }
5322
5323 static void tg3_napi_init(struct tg3 *tp)
5324 {
5325         int i;
5326
5327         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5328         for (i = 1; i < tp->irq_cnt; i++)
5329                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5330 }
5331
5332 static void tg3_napi_fini(struct tg3 *tp)
5333 {
5334         int i;
5335
5336         for (i = 0; i < tp->irq_cnt; i++)
5337                 netif_napi_del(&tp->napi[i].napi);
5338 }
5339
5340 static inline void tg3_netif_stop(struct tg3 *tp)
5341 {
5342         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5343         tg3_napi_disable(tp);
5344         netif_tx_disable(tp->dev);
5345 }
5346
5347 static inline void tg3_netif_start(struct tg3 *tp)
5348 {
5349         /* NOTE: unconditional netif_tx_wake_all_queues is only
5350          * appropriate so long as all callers are assured to
5351          * have free tx slots (such as after tg3_init_hw)
5352          */
5353         netif_tx_wake_all_queues(tp->dev);
5354
5355         tg3_napi_enable(tp);
5356         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5357         tg3_enable_ints(tp);
5358 }
5359
5360 static void tg3_irq_quiesce(struct tg3 *tp)
5361 {
5362         int i;
5363
5364         BUG_ON(tp->irq_sync);
5365
5366         tp->irq_sync = 1;
5367         smp_mb();
5368
5369         for (i = 0; i < tp->irq_cnt; i++)
5370                 synchronize_irq(tp->napi[i].irq_vec);
5371 }
5372
5373 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5374  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5375  * with as well.  Most of the time, this is not necessary except when
5376  * shutting down the device.
5377  */
5378 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5379 {
5380         spin_lock_bh(&tp->lock);
5381         if (irq_sync)
5382                 tg3_irq_quiesce(tp);
5383 }
5384
5385 static inline void tg3_full_unlock(struct tg3 *tp)
5386 {
5387         spin_unlock_bh(&tp->lock);
5388 }
5389
5390 /* One-shot MSI handler - Chip automatically disables interrupt
5391  * after sending MSI so driver doesn't have to do it.
5392  */
5393 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5394 {
5395         struct tg3_napi *tnapi = dev_id;
5396         struct tg3 *tp = tnapi->tp;
5397
5398         prefetch(tnapi->hw_status);
5399         if (tnapi->rx_rcb)
5400                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5401
5402         if (likely(!tg3_irq_sync(tp)))
5403                 napi_schedule(&tnapi->napi);
5404
5405         return IRQ_HANDLED;
5406 }
5407
5408 /* MSI ISR - No need to check for interrupt sharing and no need to
5409  * flush status block and interrupt mailbox. PCI ordering rules
5410  * guarantee that MSI will arrive after the status block.
5411  */
5412 static irqreturn_t tg3_msi(int irq, void *dev_id)
5413 {
5414         struct tg3_napi *tnapi = dev_id;
5415         struct tg3 *tp = tnapi->tp;
5416
5417         prefetch(tnapi->hw_status);
5418         if (tnapi->rx_rcb)
5419                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5420         /*
5421          * Writing any value to intr-mbox-0 clears PCI INTA# and
5422          * chip-internal interrupt pending events.
5423          * Writing non-zero to intr-mbox-0 additional tells the
5424          * NIC to stop sending us irqs, engaging "in-intr-handler"
5425          * event coalescing.
5426          */
5427         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5428         if (likely(!tg3_irq_sync(tp)))
5429                 napi_schedule(&tnapi->napi);
5430
5431         return IRQ_RETVAL(1);
5432 }
5433
5434 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5435 {
5436         struct tg3_napi *tnapi = dev_id;
5437         struct tg3 *tp = tnapi->tp;
5438         struct tg3_hw_status *sblk = tnapi->hw_status;
5439         unsigned int handled = 1;
5440
5441         /* In INTx mode, it is possible for the interrupt to arrive at
5442          * the CPU before the status block posted prior to the interrupt.
5443          * Reading the PCI State register will confirm whether the
5444          * interrupt is ours and will flush the status block.
5445          */
5446         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5447                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5448                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5449                         handled = 0;
5450                         goto out;
5451                 }
5452         }
5453
5454         /*
5455          * Writing any value to intr-mbox-0 clears PCI INTA# and
5456          * chip-internal interrupt pending events.
5457          * Writing non-zero to intr-mbox-0 additional tells the
5458          * NIC to stop sending us irqs, engaging "in-intr-handler"
5459          * event coalescing.
5460          *
5461          * Flush the mailbox to de-assert the IRQ immediately to prevent
5462          * spurious interrupts.  The flush impacts performance but
5463          * excessive spurious interrupts can be worse in some cases.
5464          */
5465         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5466         if (tg3_irq_sync(tp))
5467                 goto out;
5468         sblk->status &= ~SD_STATUS_UPDATED;
5469         if (likely(tg3_has_work(tnapi))) {
5470                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5471                 napi_schedule(&tnapi->napi);
5472         } else {
5473                 /* No work, shared interrupt perhaps?  re-enable
5474                  * interrupts, and flush that PCI write
5475                  */
5476                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5477                                0x00000000);
5478         }
5479 out:
5480         return IRQ_RETVAL(handled);
5481 }
5482
5483 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5484 {
5485         struct tg3_napi *tnapi = dev_id;
5486         struct tg3 *tp = tnapi->tp;
5487         struct tg3_hw_status *sblk = tnapi->hw_status;
5488         unsigned int handled = 1;
5489
5490         /* In INTx mode, it is possible for the interrupt to arrive at
5491          * the CPU before the status block posted prior to the interrupt.
5492          * Reading the PCI State register will confirm whether the
5493          * interrupt is ours and will flush the status block.
5494          */
5495         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5496                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5497                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5498                         handled = 0;
5499                         goto out;
5500                 }
5501         }
5502
5503         /*
5504          * writing any value to intr-mbox-0 clears PCI INTA# and
5505          * chip-internal interrupt pending events.
5506          * writing non-zero to intr-mbox-0 additional tells the
5507          * NIC to stop sending us irqs, engaging "in-intr-handler"
5508          * event coalescing.
5509          *
5510          * Flush the mailbox to de-assert the IRQ immediately to prevent
5511          * spurious interrupts.  The flush impacts performance but
5512          * excessive spurious interrupts can be worse in some cases.
5513          */
5514         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5515
5516         /*
5517          * In a shared interrupt configuration, sometimes other devices'
5518          * interrupts will scream.  We record the current status tag here
5519          * so that the above check can report that the screaming interrupts
5520          * are unhandled.  Eventually they will be silenced.
5521          */
5522         tnapi->last_irq_tag = sblk->status_tag;
5523
5524         if (tg3_irq_sync(tp))
5525                 goto out;
5526
5527         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5528
5529         napi_schedule(&tnapi->napi);
5530
5531 out:
5532         return IRQ_RETVAL(handled);
5533 }
5534
5535 /* ISR for interrupt test */
5536 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5537 {
5538         struct tg3_napi *tnapi = dev_id;
5539         struct tg3 *tp = tnapi->tp;
5540         struct tg3_hw_status *sblk = tnapi->hw_status;
5541
5542         if ((sblk->status & SD_STATUS_UPDATED) ||
5543             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5544                 tg3_disable_ints(tp);
5545                 return IRQ_RETVAL(1);
5546         }
5547         return IRQ_RETVAL(0);
5548 }
5549
5550 static int tg3_init_hw(struct tg3 *, int);
5551 static int tg3_halt(struct tg3 *, int, int);
5552
5553 /* Restart hardware after configuration changes, self-test, etc.
5554  * Invoked with tp->lock held.
5555  */
5556 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5557         __releases(tp->lock)
5558         __acquires(tp->lock)
5559 {
5560         int err;
5561
5562         err = tg3_init_hw(tp, reset_phy);
5563         if (err) {
5564                 netdev_err(tp->dev,
5565                            "Failed to re-initialize device, aborting\n");
5566                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5567                 tg3_full_unlock(tp);
5568                 del_timer_sync(&tp->timer);
5569                 tp->irq_sync = 0;
5570                 tg3_napi_enable(tp);
5571                 dev_close(tp->dev);
5572                 tg3_full_lock(tp, 0);
5573         }
5574         return err;
5575 }
5576
5577 #ifdef CONFIG_NET_POLL_CONTROLLER
5578 static void tg3_poll_controller(struct net_device *dev)
5579 {
5580         int i;
5581         struct tg3 *tp = netdev_priv(dev);
5582
5583         for (i = 0; i < tp->irq_cnt; i++)
5584                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5585 }
5586 #endif
5587
5588 static void tg3_reset_task(struct work_struct *work)
5589 {
5590         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5591         int err;
5592         unsigned int restart_timer;
5593
5594         tg3_full_lock(tp, 0);
5595
5596         if (!netif_running(tp->dev)) {
5597                 tg3_full_unlock(tp);
5598                 return;
5599         }
5600
5601         tg3_full_unlock(tp);
5602
5603         tg3_phy_stop(tp);
5604
5605         tg3_netif_stop(tp);
5606
5607         tg3_full_lock(tp, 1);
5608
5609         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5610         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5611
5612         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5613                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5614                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5615                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5616                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5617         }
5618
5619         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5620         err = tg3_init_hw(tp, 1);
5621         if (err)
5622                 goto out;
5623
5624         tg3_netif_start(tp);
5625
5626         if (restart_timer)
5627                 mod_timer(&tp->timer, jiffies + 1);
5628
5629 out:
5630         tg3_full_unlock(tp);
5631
5632         if (!err)
5633                 tg3_phy_start(tp);
5634 }
5635
5636 static void tg3_tx_timeout(struct net_device *dev)
5637 {
5638         struct tg3 *tp = netdev_priv(dev);
5639
5640         if (netif_msg_tx_err(tp)) {
5641                 netdev_err(dev, "transmit timed out, resetting\n");
5642                 tg3_dump_state(tp);
5643         }
5644
5645         schedule_work(&tp->reset_task);
5646 }
5647
5648 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5649 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5650 {
5651         u32 base = (u32) mapping & 0xffffffff;
5652
5653         return (base > 0xffffdcc0) && (base + len + 8 < base);
5654 }
5655
5656 /* Test for DMA addresses > 40-bit */
5657 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5658                                           int len)
5659 {
5660 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5661         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5662                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5663         return 0;
5664 #else
5665         return 0;
5666 #endif
5667 }
5668
5669 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5670
5671 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5672 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5673                                        struct sk_buff *skb, u32 last_plus_one,
5674                                        u32 *start, u32 base_flags, u32 mss)
5675 {
5676         struct tg3 *tp = tnapi->tp;
5677         struct sk_buff *new_skb;
5678         dma_addr_t new_addr = 0;
5679         u32 entry = *start;
5680         int i, ret = 0;
5681
5682         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5683                 new_skb = skb_copy(skb, GFP_ATOMIC);
5684         else {
5685                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5686
5687                 new_skb = skb_copy_expand(skb,
5688                                           skb_headroom(skb) + more_headroom,
5689                                           skb_tailroom(skb), GFP_ATOMIC);
5690         }
5691
5692         if (!new_skb) {
5693                 ret = -1;
5694         } else {
5695                 /* New SKB is guaranteed to be linear. */
5696                 entry = *start;
5697                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5698                                           PCI_DMA_TODEVICE);
5699                 /* Make sure the mapping succeeded */
5700                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5701                         ret = -1;
5702                         dev_kfree_skb(new_skb);
5703                         new_skb = NULL;
5704
5705                 /* Make sure new skb does not cross any 4G boundaries.
5706                  * Drop the packet if it does.
5707                  */
5708                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5709                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5710                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5711                                          PCI_DMA_TODEVICE);
5712                         ret = -1;
5713                         dev_kfree_skb(new_skb);
5714                         new_skb = NULL;
5715                 } else {
5716                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5717                                     base_flags, 1 | (mss << 1));
5718                         *start = NEXT_TX(entry);
5719                 }
5720         }
5721
5722         /* Now clean up the sw ring entries. */
5723         i = 0;
5724         while (entry != last_plus_one) {
5725                 int len;
5726
5727                 if (i == 0)
5728                         len = skb_headlen(skb);
5729                 else
5730                         len = skb_shinfo(skb)->frags[i-1].size;
5731
5732                 pci_unmap_single(tp->pdev,
5733                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5734                                                 mapping),
5735                                  len, PCI_DMA_TODEVICE);
5736                 if (i == 0) {
5737                         tnapi->tx_buffers[entry].skb = new_skb;
5738                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5739                                            new_addr);
5740                 } else {
5741                         tnapi->tx_buffers[entry].skb = NULL;
5742                 }
5743                 entry = NEXT_TX(entry);
5744                 i++;
5745         }
5746
5747         dev_kfree_skb(skb);
5748
5749         return ret;
5750 }
5751
5752 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5753                         dma_addr_t mapping, int len, u32 flags,
5754                         u32 mss_and_is_end)
5755 {
5756         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5757         int is_end = (mss_and_is_end & 0x1);
5758         u32 mss = (mss_and_is_end >> 1);
5759         u32 vlan_tag = 0;
5760
5761         if (is_end)
5762                 flags |= TXD_FLAG_END;
5763         if (flags & TXD_FLAG_VLAN) {
5764                 vlan_tag = flags >> 16;
5765                 flags &= 0xffff;
5766         }
5767         vlan_tag |= (mss << TXD_MSS_SHIFT);
5768
5769         txd->addr_hi = ((u64) mapping >> 32);
5770         txd->addr_lo = ((u64) mapping & 0xffffffff);
5771         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5772         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5773 }
5774
5775 /* hard_start_xmit for devices that don't have any bugs and
5776  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5777  */
5778 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5779                                   struct net_device *dev)
5780 {
5781         struct tg3 *tp = netdev_priv(dev);
5782         u32 len, entry, base_flags, mss;
5783         dma_addr_t mapping;
5784         struct tg3_napi *tnapi;
5785         struct netdev_queue *txq;
5786         unsigned int i, last;
5787
5788         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5789         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5790         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5791                 tnapi++;
5792
5793         /* We are running in BH disabled context with netif_tx_lock
5794          * and TX reclaim runs via tp->napi.poll inside of a software
5795          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5796          * no IRQ context deadlocks to worry about either.  Rejoice!
5797          */
5798         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5799                 if (!netif_tx_queue_stopped(txq)) {
5800                         netif_tx_stop_queue(txq);
5801
5802                         /* This is a hard error, log it. */
5803                         netdev_err(dev,
5804                                    "BUG! Tx Ring full when queue awake!\n");
5805                 }
5806                 return NETDEV_TX_BUSY;
5807         }
5808
5809         entry = tnapi->tx_prod;
5810         base_flags = 0;
5811         mss = skb_shinfo(skb)->gso_size;
5812         if (mss) {
5813                 int tcp_opt_len, ip_tcp_len;
5814                 u32 hdrlen;
5815
5816                 if (skb_header_cloned(skb) &&
5817                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5818                         dev_kfree_skb(skb);
5819                         goto out_unlock;
5820                 }
5821
5822                 if (skb_is_gso_v6(skb)) {
5823                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5824                 } else {
5825                         struct iphdr *iph = ip_hdr(skb);
5826
5827                         tcp_opt_len = tcp_optlen(skb);
5828                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5829
5830                         iph->check = 0;
5831                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5832                         hdrlen = ip_tcp_len + tcp_opt_len;
5833                 }
5834
5835                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5836                         mss |= (hdrlen & 0xc) << 12;
5837                         if (hdrlen & 0x10)
5838                                 base_flags |= 0x00000010;
5839                         base_flags |= (hdrlen & 0x3e0) << 5;
5840                 } else
5841                         mss |= hdrlen << 9;
5842
5843                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5844                                TXD_FLAG_CPU_POST_DMA);
5845
5846                 tcp_hdr(skb)->check = 0;
5847
5848         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5849                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5850         }
5851
5852         if (vlan_tx_tag_present(skb))
5853                 base_flags |= (TXD_FLAG_VLAN |
5854                                (vlan_tx_tag_get(skb) << 16));
5855
5856         len = skb_headlen(skb);
5857
5858         /* Queue skb data, a.k.a. the main skb fragment. */
5859         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5860         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5861                 dev_kfree_skb(skb);
5862                 goto out_unlock;
5863         }
5864
5865         tnapi->tx_buffers[entry].skb = skb;
5866         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5867
5868         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5869             !mss && skb->len > VLAN_ETH_FRAME_LEN)
5870                 base_flags |= TXD_FLAG_JMB_PKT;
5871
5872         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5873                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5874
5875         entry = NEXT_TX(entry);
5876
5877         /* Now loop through additional data fragments, and queue them. */
5878         if (skb_shinfo(skb)->nr_frags > 0) {
5879                 last = skb_shinfo(skb)->nr_frags - 1;
5880                 for (i = 0; i <= last; i++) {
5881                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5882
5883                         len = frag->size;
5884                         mapping = pci_map_page(tp->pdev,
5885                                                frag->page,
5886                                                frag->page_offset,
5887                                                len, PCI_DMA_TODEVICE);
5888                         if (pci_dma_mapping_error(tp->pdev, mapping))
5889                                 goto dma_error;
5890
5891                         tnapi->tx_buffers[entry].skb = NULL;
5892                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5893                                            mapping);
5894
5895                         tg3_set_txd(tnapi, entry, mapping, len,
5896                                     base_flags, (i == last) | (mss << 1));
5897
5898                         entry = NEXT_TX(entry);
5899                 }
5900         }
5901
5902         /* Packets are ready, update Tx producer idx local and on card. */
5903         tw32_tx_mbox(tnapi->prodmbox, entry);
5904
5905         tnapi->tx_prod = entry;
5906         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5907                 netif_tx_stop_queue(txq);
5908
5909                 /* netif_tx_stop_queue() must be done before checking
5910                  * checking tx index in tg3_tx_avail() below, because in
5911                  * tg3_tx(), we update tx index before checking for
5912                  * netif_tx_queue_stopped().
5913                  */
5914                 smp_mb();
5915                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5916                         netif_tx_wake_queue(txq);
5917         }
5918
5919 out_unlock:
5920         mmiowb();
5921
5922         return NETDEV_TX_OK;
5923
5924 dma_error:
5925         last = i;
5926         entry = tnapi->tx_prod;
5927         tnapi->tx_buffers[entry].skb = NULL;
5928         pci_unmap_single(tp->pdev,
5929                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5930                          skb_headlen(skb),
5931                          PCI_DMA_TODEVICE);
5932         for (i = 0; i <= last; i++) {
5933                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5934                 entry = NEXT_TX(entry);
5935
5936                 pci_unmap_page(tp->pdev,
5937                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5938                                               mapping),
5939                                frag->size, PCI_DMA_TODEVICE);
5940         }
5941
5942         dev_kfree_skb(skb);
5943         return NETDEV_TX_OK;
5944 }
5945
5946 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5947                                           struct net_device *);
5948
5949 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5950  * TSO header is greater than 80 bytes.
5951  */
5952 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5953 {
5954         struct sk_buff *segs, *nskb;
5955         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5956
5957         /* Estimate the number of fragments in the worst case */
5958         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5959                 netif_stop_queue(tp->dev);
5960
5961                 /* netif_tx_stop_queue() must be done before checking
5962                  * checking tx index in tg3_tx_avail() below, because in
5963                  * tg3_tx(), we update tx index before checking for
5964                  * netif_tx_queue_stopped().
5965                  */
5966                 smp_mb();
5967                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5968                         return NETDEV_TX_BUSY;
5969
5970                 netif_wake_queue(tp->dev);
5971         }
5972
5973         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5974         if (IS_ERR(segs))
5975                 goto tg3_tso_bug_end;
5976
5977         do {
5978                 nskb = segs;
5979                 segs = segs->next;
5980                 nskb->next = NULL;
5981                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5982         } while (segs);
5983
5984 tg3_tso_bug_end:
5985         dev_kfree_skb(skb);
5986
5987         return NETDEV_TX_OK;
5988 }
5989
5990 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5991  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5992  */
5993 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5994                                           struct net_device *dev)
5995 {
5996         struct tg3 *tp = netdev_priv(dev);
5997         u32 len, entry, base_flags, mss;
5998         int would_hit_hwbug;
5999         dma_addr_t mapping;
6000         struct tg3_napi *tnapi;
6001         struct netdev_queue *txq;
6002         unsigned int i, last;
6003
6004         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6005         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
6006         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
6007                 tnapi++;
6008
6009         /* We are running in BH disabled context with netif_tx_lock
6010          * and TX reclaim runs via tp->napi.poll inside of a software
6011          * interrupt.  Furthermore, IRQ processing runs lockless so we have
6012          * no IRQ context deadlocks to worry about either.  Rejoice!
6013          */
6014         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
6015                 if (!netif_tx_queue_stopped(txq)) {
6016                         netif_tx_stop_queue(txq);
6017
6018                         /* This is a hard error, log it. */
6019                         netdev_err(dev,
6020                                    "BUG! Tx Ring full when queue awake!\n");
6021                 }
6022                 return NETDEV_TX_BUSY;
6023         }
6024
6025         entry = tnapi->tx_prod;
6026         base_flags = 0;
6027         if (skb->ip_summed == CHECKSUM_PARTIAL)
6028                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
6029
6030         mss = skb_shinfo(skb)->gso_size;
6031         if (mss) {
6032                 struct iphdr *iph;
6033                 u32 tcp_opt_len, hdr_len;
6034
6035                 if (skb_header_cloned(skb) &&
6036                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
6037                         dev_kfree_skb(skb);
6038                         goto out_unlock;
6039                 }
6040
6041                 iph = ip_hdr(skb);
6042                 tcp_opt_len = tcp_optlen(skb);
6043
6044                 if (skb_is_gso_v6(skb)) {
6045                         hdr_len = skb_headlen(skb) - ETH_HLEN;
6046                 } else {
6047                         u32 ip_tcp_len;
6048
6049                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
6050                         hdr_len = ip_tcp_len + tcp_opt_len;
6051
6052                         iph->check = 0;
6053                         iph->tot_len = htons(mss + hdr_len);
6054                 }
6055
6056                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
6057                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
6058                         return tg3_tso_bug(tp, skb);
6059
6060                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
6061                                TXD_FLAG_CPU_POST_DMA);
6062
6063                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
6064                         tcp_hdr(skb)->check = 0;
6065                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
6066                 } else
6067                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6068                                                                  iph->daddr, 0,
6069                                                                  IPPROTO_TCP,
6070                                                                  0);
6071
6072                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
6073                         mss |= (hdr_len & 0xc) << 12;
6074                         if (hdr_len & 0x10)
6075                                 base_flags |= 0x00000010;
6076                         base_flags |= (hdr_len & 0x3e0) << 5;
6077                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
6078                         mss |= hdr_len << 9;
6079                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
6080                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6081                         if (tcp_opt_len || iph->ihl > 5) {
6082                                 int tsflags;
6083
6084                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6085                                 mss |= (tsflags << 11);
6086                         }
6087                 } else {
6088                         if (tcp_opt_len || iph->ihl > 5) {
6089                                 int tsflags;
6090
6091                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6092                                 base_flags |= tsflags << 12;
6093                         }
6094                 }
6095         }
6096
6097         if (vlan_tx_tag_present(skb))
6098                 base_flags |= (TXD_FLAG_VLAN |
6099                                (vlan_tx_tag_get(skb) << 16));
6100
6101         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
6102             !mss && skb->len > VLAN_ETH_FRAME_LEN)
6103                 base_flags |= TXD_FLAG_JMB_PKT;
6104
6105         len = skb_headlen(skb);
6106
6107         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6108         if (pci_dma_mapping_error(tp->pdev, mapping)) {
6109                 dev_kfree_skb(skb);
6110                 goto out_unlock;
6111         }
6112
6113         tnapi->tx_buffers[entry].skb = skb;
6114         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6115
6116         would_hit_hwbug = 0;
6117
6118         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
6119                 would_hit_hwbug = 1;
6120
6121         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6122             tg3_4g_overflow_test(mapping, len))
6123                 would_hit_hwbug = 1;
6124
6125         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6126             tg3_40bit_overflow_test(tp, mapping, len))
6127                 would_hit_hwbug = 1;
6128
6129         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
6130                 would_hit_hwbug = 1;
6131
6132         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6133                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6134
6135         entry = NEXT_TX(entry);
6136
6137         /* Now loop through additional data fragments, and queue them. */
6138         if (skb_shinfo(skb)->nr_frags > 0) {
6139                 last = skb_shinfo(skb)->nr_frags - 1;
6140                 for (i = 0; i <= last; i++) {
6141                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6142
6143                         len = frag->size;
6144                         mapping = pci_map_page(tp->pdev,
6145                                                frag->page,
6146                                                frag->page_offset,
6147                                                len, PCI_DMA_TODEVICE);
6148
6149                         tnapi->tx_buffers[entry].skb = NULL;
6150                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6151                                            mapping);
6152                         if (pci_dma_mapping_error(tp->pdev, mapping))
6153                                 goto dma_error;
6154
6155                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6156                             len <= 8)
6157                                 would_hit_hwbug = 1;
6158
6159                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6160                             tg3_4g_overflow_test(mapping, len))
6161                                 would_hit_hwbug = 1;
6162
6163                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6164                             tg3_40bit_overflow_test(tp, mapping, len))
6165                                 would_hit_hwbug = 1;
6166
6167                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6168                                 tg3_set_txd(tnapi, entry, mapping, len,
6169                                             base_flags, (i == last)|(mss << 1));
6170                         else
6171                                 tg3_set_txd(tnapi, entry, mapping, len,
6172                                             base_flags, (i == last));
6173
6174                         entry = NEXT_TX(entry);
6175                 }
6176         }
6177
6178         if (would_hit_hwbug) {
6179                 u32 last_plus_one = entry;
6180                 u32 start;
6181
6182                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6183                 start &= (TG3_TX_RING_SIZE - 1);
6184
6185                 /* If the workaround fails due to memory/mapping
6186                  * failure, silently drop this packet.
6187                  */
6188                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6189                                                 &start, base_flags, mss))
6190                         goto out_unlock;
6191
6192                 entry = start;
6193         }
6194
6195         /* Packets are ready, update Tx producer idx local and on card. */
6196         tw32_tx_mbox(tnapi->prodmbox, entry);
6197
6198         tnapi->tx_prod = entry;
6199         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6200                 netif_tx_stop_queue(txq);
6201
6202                 /* netif_tx_stop_queue() must be done before checking
6203                  * checking tx index in tg3_tx_avail() below, because in
6204                  * tg3_tx(), we update tx index before checking for
6205                  * netif_tx_queue_stopped().
6206                  */
6207                 smp_mb();
6208                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6209                         netif_tx_wake_queue(txq);
6210         }
6211
6212 out_unlock:
6213         mmiowb();
6214
6215         return NETDEV_TX_OK;
6216
6217 dma_error:
6218         last = i;
6219         entry = tnapi->tx_prod;
6220         tnapi->tx_buffers[entry].skb = NULL;
6221         pci_unmap_single(tp->pdev,
6222                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6223                          skb_headlen(skb),
6224                          PCI_DMA_TODEVICE);
6225         for (i = 0; i <= last; i++) {
6226                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6227                 entry = NEXT_TX(entry);
6228
6229                 pci_unmap_page(tp->pdev,
6230                                dma_unmap_addr(&tnapi->tx_buffers[entry],
6231                                               mapping),
6232                                frag->size, PCI_DMA_TODEVICE);
6233         }
6234
6235         dev_kfree_skb(skb);
6236         return NETDEV_TX_OK;
6237 }
6238
6239 static u32 tg3_fix_features(struct net_device *dev, u32 features)
6240 {
6241         struct tg3 *tp = netdev_priv(dev);
6242
6243         if (dev->mtu > ETH_DATA_LEN && (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6244                 features &= ~NETIF_F_ALL_TSO;
6245
6246         return features;
6247 }
6248
6249 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6250                                int new_mtu)
6251 {
6252         dev->mtu = new_mtu;
6253
6254         if (new_mtu > ETH_DATA_LEN) {
6255                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6256                         netdev_update_features(dev);
6257                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6258                 } else {
6259                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6260                 }
6261         } else {
6262                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6263                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6264                         netdev_update_features(dev);
6265                 }
6266                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6267         }
6268 }
6269
6270 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6271 {
6272         struct tg3 *tp = netdev_priv(dev);
6273         int err;
6274
6275         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6276                 return -EINVAL;
6277
6278         if (!netif_running(dev)) {
6279                 /* We'll just catch it later when the
6280                  * device is up'd.
6281                  */
6282                 tg3_set_mtu(dev, tp, new_mtu);
6283                 return 0;
6284         }
6285
6286         tg3_phy_stop(tp);
6287
6288         tg3_netif_stop(tp);
6289
6290         tg3_full_lock(tp, 1);
6291
6292         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6293
6294         tg3_set_mtu(dev, tp, new_mtu);
6295
6296         err = tg3_restart_hw(tp, 0);
6297
6298         if (!err)
6299                 tg3_netif_start(tp);
6300
6301         tg3_full_unlock(tp);
6302
6303         if (!err)
6304                 tg3_phy_start(tp);
6305
6306         return err;
6307 }
6308
6309 static void tg3_rx_prodring_free(struct tg3 *tp,
6310                                  struct tg3_rx_prodring_set *tpr)
6311 {
6312         int i;
6313
6314         if (tpr != &tp->napi[0].prodring) {
6315                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6316                      i = (i + 1) & tp->rx_std_ring_mask)
6317                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6318                                         tp->rx_pkt_map_sz);
6319
6320                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6321                         for (i = tpr->rx_jmb_cons_idx;
6322                              i != tpr->rx_jmb_prod_idx;
6323                              i = (i + 1) & tp->rx_jmb_ring_mask) {
6324                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6325                                                 TG3_RX_JMB_MAP_SZ);
6326                         }
6327                 }
6328
6329                 return;
6330         }
6331
6332         for (i = 0; i <= tp->rx_std_ring_mask; i++)
6333                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6334                                 tp->rx_pkt_map_sz);
6335
6336         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6337             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6338                 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6339                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6340                                         TG3_RX_JMB_MAP_SZ);
6341         }
6342 }
6343
6344 /* Initialize rx rings for packet processing.
6345  *
6346  * The chip has been shut down and the driver detached from
6347  * the networking, so no interrupts or new tx packets will
6348  * end up in the driver.  tp->{tx,}lock are held and thus
6349  * we may not sleep.
6350  */
6351 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6352                                  struct tg3_rx_prodring_set *tpr)
6353 {
6354         u32 i, rx_pkt_dma_sz;
6355
6356         tpr->rx_std_cons_idx = 0;
6357         tpr->rx_std_prod_idx = 0;
6358         tpr->rx_jmb_cons_idx = 0;
6359         tpr->rx_jmb_prod_idx = 0;
6360
6361         if (tpr != &tp->napi[0].prodring) {
6362                 memset(&tpr->rx_std_buffers[0], 0,
6363                        TG3_RX_STD_BUFF_RING_SIZE(tp));
6364                 if (tpr->rx_jmb_buffers)
6365                         memset(&tpr->rx_jmb_buffers[0], 0,
6366                                TG3_RX_JMB_BUFF_RING_SIZE(tp));
6367                 goto done;
6368         }
6369
6370         /* Zero out all descriptors. */
6371         memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6372
6373         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6374         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6375             tp->dev->mtu > ETH_DATA_LEN)
6376                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6377         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6378
6379         /* Initialize invariants of the rings, we only set this
6380          * stuff once.  This works because the card does not
6381          * write into the rx buffer posting rings.
6382          */
6383         for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6384                 struct tg3_rx_buffer_desc *rxd;
6385
6386                 rxd = &tpr->rx_std[i];
6387                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6388                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6389                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6390                                (i << RXD_OPAQUE_INDEX_SHIFT));
6391         }
6392
6393         /* Now allocate fresh SKBs for each rx ring. */
6394         for (i = 0; i < tp->rx_pending; i++) {
6395                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6396                         netdev_warn(tp->dev,
6397                                     "Using a smaller RX standard ring. Only "
6398                                     "%d out of %d buffers were allocated "
6399                                     "successfully\n", i, tp->rx_pending);
6400                         if (i == 0)
6401                                 goto initfail;
6402                         tp->rx_pending = i;
6403                         break;
6404                 }
6405         }
6406
6407         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
6408             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6409                 goto done;
6410
6411         memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6412
6413         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6414                 goto done;
6415
6416         for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6417                 struct tg3_rx_buffer_desc *rxd;
6418
6419                 rxd = &tpr->rx_jmb[i].std;
6420                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6421                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6422                                   RXD_FLAG_JUMBO;
6423                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6424                        (i << RXD_OPAQUE_INDEX_SHIFT));
6425         }
6426
6427         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6428                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6429                         netdev_warn(tp->dev,
6430                                     "Using a smaller RX jumbo ring. Only %d "
6431                                     "out of %d buffers were allocated "
6432                                     "successfully\n", i, tp->rx_jumbo_pending);
6433                         if (i == 0)
6434                                 goto initfail;
6435                         tp->rx_jumbo_pending = i;
6436                         break;
6437                 }
6438         }
6439
6440 done:
6441         return 0;
6442
6443 initfail:
6444         tg3_rx_prodring_free(tp, tpr);
6445         return -ENOMEM;
6446 }
6447
6448 static void tg3_rx_prodring_fini(struct tg3 *tp,
6449                                  struct tg3_rx_prodring_set *tpr)
6450 {
6451         kfree(tpr->rx_std_buffers);
6452         tpr->rx_std_buffers = NULL;
6453         kfree(tpr->rx_jmb_buffers);
6454         tpr->rx_jmb_buffers = NULL;
6455         if (tpr->rx_std) {
6456                 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
6457                                   tpr->rx_std, tpr->rx_std_mapping);
6458                 tpr->rx_std = NULL;
6459         }
6460         if (tpr->rx_jmb) {
6461                 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
6462                                   tpr->rx_jmb, tpr->rx_jmb_mapping);
6463                 tpr->rx_jmb = NULL;
6464         }
6465 }
6466
6467 static int tg3_rx_prodring_init(struct tg3 *tp,
6468                                 struct tg3_rx_prodring_set *tpr)
6469 {
6470         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6471                                       GFP_KERNEL);
6472         if (!tpr->rx_std_buffers)
6473                 return -ENOMEM;
6474
6475         tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
6476                                          TG3_RX_STD_RING_BYTES(tp),
6477                                          &tpr->rx_std_mapping,
6478                                          GFP_KERNEL);
6479         if (!tpr->rx_std)
6480                 goto err_out;
6481
6482         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6483             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6484                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6485                                               GFP_KERNEL);
6486                 if (!tpr->rx_jmb_buffers)
6487                         goto err_out;
6488
6489                 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
6490                                                  TG3_RX_JMB_RING_BYTES(tp),
6491                                                  &tpr->rx_jmb_mapping,
6492                                                  GFP_KERNEL);
6493                 if (!tpr->rx_jmb)
6494                         goto err_out;
6495         }
6496
6497         return 0;
6498
6499 err_out:
6500         tg3_rx_prodring_fini(tp, tpr);
6501         return -ENOMEM;
6502 }
6503
6504 /* Free up pending packets in all rx/tx rings.
6505  *
6506  * The chip has been shut down and the driver detached from
6507  * the networking, so no interrupts or new tx packets will
6508  * end up in the driver.  tp->{tx,}lock is not held and we are not
6509  * in an interrupt context and thus may sleep.
6510  */
6511 static void tg3_free_rings(struct tg3 *tp)
6512 {
6513         int i, j;
6514
6515         for (j = 0; j < tp->irq_cnt; j++) {
6516                 struct tg3_napi *tnapi = &tp->napi[j];
6517
6518                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6519
6520                 if (!tnapi->tx_buffers)
6521                         continue;
6522
6523                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6524                         struct ring_info *txp;
6525                         struct sk_buff *skb;
6526                         unsigned int k;
6527
6528                         txp = &tnapi->tx_buffers[i];
6529                         skb = txp->skb;
6530
6531                         if (skb == NULL) {
6532                                 i++;
6533                                 continue;
6534                         }
6535
6536                         pci_unmap_single(tp->pdev,
6537                                          dma_unmap_addr(txp, mapping),
6538                                          skb_headlen(skb),
6539                                          PCI_DMA_TODEVICE);
6540                         txp->skb = NULL;
6541
6542                         i++;
6543
6544                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6545                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6546                                 pci_unmap_page(tp->pdev,
6547                                                dma_unmap_addr(txp, mapping),
6548                                                skb_shinfo(skb)->frags[k].size,
6549                                                PCI_DMA_TODEVICE);
6550                                 i++;
6551                         }
6552
6553                         dev_kfree_skb_any(skb);
6554                 }
6555         }
6556 }
6557
6558 /* Initialize tx/rx rings for packet processing.
6559  *
6560  * The chip has been shut down and the driver detached from
6561  * the networking, so no interrupts or new tx packets will
6562  * end up in the driver.  tp->{tx,}lock are held and thus
6563  * we may not sleep.
6564  */
6565 static int tg3_init_rings(struct tg3 *tp)
6566 {
6567         int i;
6568
6569         /* Free up all the SKBs. */
6570         tg3_free_rings(tp);
6571
6572         for (i = 0; i < tp->irq_cnt; i++) {
6573                 struct tg3_napi *tnapi = &tp->napi[i];
6574
6575                 tnapi->last_tag = 0;
6576                 tnapi->last_irq_tag = 0;
6577                 tnapi->hw_status->status = 0;
6578                 tnapi->hw_status->status_tag = 0;
6579                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6580
6581                 tnapi->tx_prod = 0;
6582                 tnapi->tx_cons = 0;
6583                 if (tnapi->tx_ring)
6584                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6585
6586                 tnapi->rx_rcb_ptr = 0;
6587                 if (tnapi->rx_rcb)
6588                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6589
6590                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6591                         tg3_free_rings(tp);
6592                         return -ENOMEM;
6593                 }
6594         }
6595
6596         return 0;
6597 }
6598
6599 /*
6600  * Must not be invoked with interrupt sources disabled and
6601  * the hardware shutdown down.
6602  */
6603 static void tg3_free_consistent(struct tg3 *tp)
6604 {
6605         int i;
6606
6607         for (i = 0; i < tp->irq_cnt; i++) {
6608                 struct tg3_napi *tnapi = &tp->napi[i];
6609
6610                 if (tnapi->tx_ring) {
6611                         dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
6612                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6613                         tnapi->tx_ring = NULL;
6614                 }
6615
6616                 kfree(tnapi->tx_buffers);
6617                 tnapi->tx_buffers = NULL;
6618
6619                 if (tnapi->rx_rcb) {
6620                         dma_free_coherent(&tp->pdev->dev,
6621                                           TG3_RX_RCB_RING_BYTES(tp),
6622                                           tnapi->rx_rcb,
6623                                           tnapi->rx_rcb_mapping);
6624                         tnapi->rx_rcb = NULL;
6625                 }
6626
6627                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6628
6629                 if (tnapi->hw_status) {
6630                         dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
6631                                           tnapi->hw_status,
6632                                           tnapi->status_mapping);
6633                         tnapi->hw_status = NULL;
6634                 }
6635         }
6636
6637         if (tp->hw_stats) {
6638                 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
6639                                   tp->hw_stats, tp->stats_mapping);
6640                 tp->hw_stats = NULL;
6641         }
6642 }
6643
6644 /*
6645  * Must not be invoked with interrupt sources disabled and
6646  * the hardware shutdown down.  Can sleep.
6647  */
6648 static int tg3_alloc_consistent(struct tg3 *tp)
6649 {
6650         int i;
6651
6652         tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
6653                                           sizeof(struct tg3_hw_stats),
6654                                           &tp->stats_mapping,
6655                                           GFP_KERNEL);
6656         if (!tp->hw_stats)
6657                 goto err_out;
6658
6659         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6660
6661         for (i = 0; i < tp->irq_cnt; i++) {
6662                 struct tg3_napi *tnapi = &tp->napi[i];
6663                 struct tg3_hw_status *sblk;
6664
6665                 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
6666                                                       TG3_HW_STATUS_SIZE,
6667                                                       &tnapi->status_mapping,
6668                                                       GFP_KERNEL);
6669                 if (!tnapi->hw_status)
6670                         goto err_out;
6671
6672                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6673                 sblk = tnapi->hw_status;
6674
6675                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6676                         goto err_out;
6677
6678                 /* If multivector TSS is enabled, vector 0 does not handle
6679                  * tx interrupts.  Don't allocate any resources for it.
6680                  */
6681                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6682                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6683                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6684                                                     TG3_TX_RING_SIZE,
6685                                                     GFP_KERNEL);
6686                         if (!tnapi->tx_buffers)
6687                                 goto err_out;
6688
6689                         tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
6690                                                             TG3_TX_RING_BYTES,
6691                                                         &tnapi->tx_desc_mapping,
6692                                                             GFP_KERNEL);
6693                         if (!tnapi->tx_ring)
6694                                 goto err_out;
6695                 }
6696
6697                 /*
6698                  * When RSS is enabled, the status block format changes
6699                  * slightly.  The "rx_jumbo_consumer", "reserved",
6700                  * and "rx_mini_consumer" members get mapped to the
6701                  * other three rx return ring producer indexes.
6702                  */
6703                 switch (i) {
6704                 default:
6705                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6706                         break;
6707                 case 2:
6708                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6709                         break;
6710                 case 3:
6711                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6712                         break;
6713                 case 4:
6714                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6715                         break;
6716                 }
6717
6718                 /*
6719                  * If multivector RSS is enabled, vector 0 does not handle
6720                  * rx or tx interrupts.  Don't allocate any resources for it.
6721                  */
6722                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6723                         continue;
6724
6725                 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
6726                                                    TG3_RX_RCB_RING_BYTES(tp),
6727                                                    &tnapi->rx_rcb_mapping,
6728                                                    GFP_KERNEL);
6729                 if (!tnapi->rx_rcb)
6730                         goto err_out;
6731
6732                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6733         }
6734
6735         return 0;
6736
6737 err_out:
6738         tg3_free_consistent(tp);
6739         return -ENOMEM;
6740 }
6741
6742 #define MAX_WAIT_CNT 1000
6743
6744 /* To stop a block, clear the enable bit and poll till it
6745  * clears.  tp->lock is held.
6746  */
6747 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6748 {
6749         unsigned int i;
6750         u32 val;
6751
6752         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6753                 switch (ofs) {
6754                 case RCVLSC_MODE:
6755                 case DMAC_MODE:
6756                 case MBFREE_MODE:
6757                 case BUFMGR_MODE:
6758                 case MEMARB_MODE:
6759                         /* We can't enable/disable these bits of the
6760                          * 5705/5750, just say success.
6761                          */
6762                         return 0;
6763
6764                 default:
6765                         break;
6766                 }
6767         }
6768
6769         val = tr32(ofs);
6770         val &= ~enable_bit;
6771         tw32_f(ofs, val);
6772
6773         for (i = 0; i < MAX_WAIT_CNT; i++) {
6774                 udelay(100);
6775                 val = tr32(ofs);
6776                 if ((val & enable_bit) == 0)
6777                         break;
6778         }
6779
6780         if (i == MAX_WAIT_CNT && !silent) {
6781                 dev_err(&tp->pdev->dev,
6782                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6783                         ofs, enable_bit);
6784                 return -ENODEV;
6785         }
6786
6787         return 0;
6788 }
6789
6790 /* tp->lock is held. */
6791 static int tg3_abort_hw(struct tg3 *tp, int silent)
6792 {
6793         int i, err;
6794
6795         tg3_disable_ints(tp);
6796
6797         tp->rx_mode &= ~RX_MODE_ENABLE;
6798         tw32_f(MAC_RX_MODE, tp->rx_mode);
6799         udelay(10);
6800
6801         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6802         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6803         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6804         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6805         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6806         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6807
6808         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6809         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6810         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6811         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6812         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6813         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6814         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6815
6816         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6817         tw32_f(MAC_MODE, tp->mac_mode);
6818         udelay(40);
6819
6820         tp->tx_mode &= ~TX_MODE_ENABLE;
6821         tw32_f(MAC_TX_MODE, tp->tx_mode);
6822
6823         for (i = 0; i < MAX_WAIT_CNT; i++) {
6824                 udelay(100);
6825                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6826                         break;
6827         }
6828         if (i >= MAX_WAIT_CNT) {
6829                 dev_err(&tp->pdev->dev,
6830                         "%s timed out, TX_MODE_ENABLE will not clear "
6831                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6832                 err |= -ENODEV;
6833         }
6834
6835         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6836         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6837         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6838
6839         tw32(FTQ_RESET, 0xffffffff);
6840         tw32(FTQ_RESET, 0x00000000);
6841
6842         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6843         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6844
6845         for (i = 0; i < tp->irq_cnt; i++) {
6846                 struct tg3_napi *tnapi = &tp->napi[i];
6847                 if (tnapi->hw_status)
6848                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6849         }
6850         if (tp->hw_stats)
6851                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6852
6853         return err;
6854 }
6855
6856 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6857 {
6858         int i;
6859         u32 apedata;
6860
6861         /* NCSI does not support APE events */
6862         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6863                 return;
6864
6865         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6866         if (apedata != APE_SEG_SIG_MAGIC)
6867                 return;
6868
6869         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6870         if (!(apedata & APE_FW_STATUS_READY))
6871                 return;
6872
6873         /* Wait for up to 1 millisecond for APE to service previous event. */
6874         for (i = 0; i < 10; i++) {
6875                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6876                         return;
6877
6878                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6879
6880                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6881                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6882                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6883
6884                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6885
6886                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6887                         break;
6888
6889                 udelay(100);
6890         }
6891
6892         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6893                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6894 }
6895
6896 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6897 {
6898         u32 event;
6899         u32 apedata;
6900
6901         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6902                 return;
6903
6904         switch (kind) {
6905         case RESET_KIND_INIT:
6906                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6907                                 APE_HOST_SEG_SIG_MAGIC);
6908                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6909                                 APE_HOST_SEG_LEN_MAGIC);
6910                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6911                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6912                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6913                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6914                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6915                                 APE_HOST_BEHAV_NO_PHYLOCK);
6916                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6917                                     TG3_APE_HOST_DRVR_STATE_START);
6918
6919                 event = APE_EVENT_STATUS_STATE_START;
6920                 break;
6921         case RESET_KIND_SHUTDOWN:
6922                 /* With the interface we are currently using,
6923                  * APE does not track driver state.  Wiping
6924                  * out the HOST SEGMENT SIGNATURE forces
6925                  * the APE to assume OS absent status.
6926                  */
6927                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6928
6929                 if (device_may_wakeup(&tp->pdev->dev) &&
6930                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6931                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6932                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6933                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6934                 } else
6935                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6936
6937                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6938
6939                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6940                 break;
6941         case RESET_KIND_SUSPEND:
6942                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6943                 break;
6944         default:
6945                 return;
6946         }
6947
6948         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6949
6950         tg3_ape_send_event(tp, event);
6951 }
6952
6953 /* tp->lock is held. */
6954 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6955 {
6956         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6957                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6958
6959         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6960                 switch (kind) {
6961                 case RESET_KIND_INIT:
6962                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6963                                       DRV_STATE_START);
6964                         break;
6965
6966                 case RESET_KIND_SHUTDOWN:
6967                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6968                                       DRV_STATE_UNLOAD);
6969                         break;
6970
6971                 case RESET_KIND_SUSPEND:
6972                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6973                                       DRV_STATE_SUSPEND);
6974                         break;
6975
6976                 default:
6977                         break;
6978                 }
6979         }
6980
6981         if (kind == RESET_KIND_INIT ||
6982             kind == RESET_KIND_SUSPEND)
6983                 tg3_ape_driver_state_change(tp, kind);
6984 }
6985
6986 /* tp->lock is held. */
6987 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6988 {
6989         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6990                 switch (kind) {
6991                 case RESET_KIND_INIT:
6992                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6993                                       DRV_STATE_START_DONE);
6994                         break;
6995
6996                 case RESET_KIND_SHUTDOWN:
6997                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6998                                       DRV_STATE_UNLOAD_DONE);
6999                         break;
7000
7001                 default:
7002                         break;
7003                 }
7004         }
7005
7006         if (kind == RESET_KIND_SHUTDOWN)
7007                 tg3_ape_driver_state_change(tp, kind);
7008 }
7009
7010 /* tp->lock is held. */
7011 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
7012 {
7013         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7014                 switch (kind) {
7015                 case RESET_KIND_INIT:
7016                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7017                                       DRV_STATE_START);
7018                         break;
7019
7020                 case RESET_KIND_SHUTDOWN:
7021                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7022                                       DRV_STATE_UNLOAD);
7023                         break;
7024
7025                 case RESET_KIND_SUSPEND:
7026                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7027                                       DRV_STATE_SUSPEND);
7028                         break;
7029
7030                 default:
7031                         break;
7032                 }
7033         }
7034 }
7035
7036 static int tg3_poll_fw(struct tg3 *tp)
7037 {
7038         int i;
7039         u32 val;
7040
7041         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7042                 /* Wait up to 20ms for init done. */
7043                 for (i = 0; i < 200; i++) {
7044                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
7045                                 return 0;
7046                         udelay(100);
7047                 }
7048                 return -ENODEV;
7049         }
7050
7051         /* Wait for firmware initialization to complete. */
7052         for (i = 0; i < 100000; i++) {
7053                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
7054                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
7055                         break;
7056                 udelay(10);
7057         }
7058
7059         /* Chip might not be fitted with firmware.  Some Sun onboard
7060          * parts are configured like that.  So don't signal the timeout
7061          * of the above loop as an error, but do report the lack of
7062          * running firmware once.
7063          */
7064         if (i >= 100000 &&
7065             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
7066                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
7067
7068                 netdev_info(tp->dev, "No firmware running\n");
7069         }
7070
7071         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7072                 /* The 57765 A0 needs a little more
7073                  * time to do some important work.
7074                  */
7075                 mdelay(10);
7076         }
7077
7078         return 0;
7079 }
7080
7081 /* Save PCI command register before chip reset */
7082 static void tg3_save_pci_state(struct tg3 *tp)
7083 {
7084         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
7085 }
7086
7087 /* Restore PCI state after chip reset */
7088 static void tg3_restore_pci_state(struct tg3 *tp)
7089 {
7090         u32 val;
7091
7092         /* Re-enable indirect register accesses. */
7093         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7094                                tp->misc_host_ctrl);
7095
7096         /* Set MAX PCI retry to zero. */
7097         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7098         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7099             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
7100                 val |= PCISTATE_RETRY_SAME_DMA;
7101         /* Allow reads and writes to the APE register and memory space. */
7102         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7103                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7104                        PCISTATE_ALLOW_APE_SHMEM_WR |
7105                        PCISTATE_ALLOW_APE_PSPACE_WR;
7106         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7107
7108         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7109
7110         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7111                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7112                         pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7113                 else {
7114                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7115                                               tp->pci_cacheline_sz);
7116                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7117                                               tp->pci_lat_timer);
7118                 }
7119         }
7120
7121         /* Make sure PCI-X relaxed ordering bit is clear. */
7122         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7123                 u16 pcix_cmd;
7124
7125                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7126                                      &pcix_cmd);
7127                 pcix_cmd &= ~PCI_X_CMD_ERO;
7128                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7129                                       pcix_cmd);
7130         }
7131
7132         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
7133
7134                 /* Chip reset on 5780 will reset MSI enable bit,
7135                  * so need to restore it.
7136                  */
7137                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7138                         u16 ctrl;
7139
7140                         pci_read_config_word(tp->pdev,
7141                                              tp->msi_cap + PCI_MSI_FLAGS,
7142                                              &ctrl);
7143                         pci_write_config_word(tp->pdev,
7144                                               tp->msi_cap + PCI_MSI_FLAGS,
7145                                               ctrl | PCI_MSI_FLAGS_ENABLE);
7146                         val = tr32(MSGINT_MODE);
7147                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7148                 }
7149         }
7150 }
7151
7152 static void tg3_stop_fw(struct tg3 *);
7153
7154 /* tp->lock is held. */
7155 static int tg3_chip_reset(struct tg3 *tp)
7156 {
7157         u32 val;
7158         void (*write_op)(struct tg3 *, u32, u32);
7159         int i, err;
7160
7161         tg3_nvram_lock(tp);
7162
7163         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7164
7165         /* No matching tg3_nvram_unlock() after this because
7166          * chip reset below will undo the nvram lock.
7167          */
7168         tp->nvram_lock_cnt = 0;
7169
7170         /* GRC_MISC_CFG core clock reset will clear the memory
7171          * enable bit in PCI register 4 and the MSI enable bit
7172          * on some chips, so we save relevant registers here.
7173          */
7174         tg3_save_pci_state(tp);
7175
7176         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7177             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7178                 tw32(GRC_FASTBOOT_PC, 0);
7179
7180         /*
7181          * We must avoid the readl() that normally takes place.
7182          * It locks machines, causes machine checks, and other
7183          * fun things.  So, temporarily disable the 5701
7184          * hardware workaround, while we do the reset.
7185          */
7186         write_op = tp->write32;
7187         if (write_op == tg3_write_flush_reg32)
7188                 tp->write32 = tg3_write32;
7189
7190         /* Prevent the irq handler from reading or writing PCI registers
7191          * during chip reset when the memory enable bit in the PCI command
7192          * register may be cleared.  The chip does not generate interrupt
7193          * at this time, but the irq handler may still be called due to irq
7194          * sharing or irqpoll.
7195          */
7196         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
7197         for (i = 0; i < tp->irq_cnt; i++) {
7198                 struct tg3_napi *tnapi = &tp->napi[i];
7199                 if (tnapi->hw_status) {
7200                         tnapi->hw_status->status = 0;
7201                         tnapi->hw_status->status_tag = 0;
7202                 }
7203                 tnapi->last_tag = 0;
7204                 tnapi->last_irq_tag = 0;
7205         }
7206         smp_mb();
7207
7208         for (i = 0; i < tp->irq_cnt; i++)
7209                 synchronize_irq(tp->napi[i].irq_vec);
7210
7211         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7212                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7213                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7214         }
7215
7216         /* do the reset */
7217         val = GRC_MISC_CFG_CORECLK_RESET;
7218
7219         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7220                 /* Force PCIe 1.0a mode */
7221                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7222                     !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
7223                     tr32(TG3_PCIE_PHY_TSTCTL) ==
7224                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7225                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7226
7227                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7228                         tw32(GRC_MISC_CFG, (1 << 29));
7229                         val |= (1 << 29);
7230                 }
7231         }
7232
7233         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7234                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7235                 tw32(GRC_VCPU_EXT_CTRL,
7236                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7237         }
7238
7239         /* Manage gphy power for all CPMU absent PCIe devices. */
7240         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7241             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7242                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7243
7244         tw32(GRC_MISC_CFG, val);
7245
7246         /* restore 5701 hardware bug workaround write method */
7247         tp->write32 = write_op;
7248
7249         /* Unfortunately, we have to delay before the PCI read back.
7250          * Some 575X chips even will not respond to a PCI cfg access
7251          * when the reset command is given to the chip.
7252          *
7253          * How do these hardware designers expect things to work
7254          * properly if the PCI write is posted for a long period
7255          * of time?  It is always necessary to have some method by
7256          * which a register read back can occur to push the write
7257          * out which does the reset.
7258          *
7259          * For most tg3 variants the trick below was working.
7260          * Ho hum...
7261          */
7262         udelay(120);
7263
7264         /* Flush PCI posted writes.  The normal MMIO registers
7265          * are inaccessible at this time so this is the only
7266          * way to make this reliably (actually, this is no longer
7267          * the case, see above).  I tried to use indirect
7268          * register read/write but this upset some 5701 variants.
7269          */
7270         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7271
7272         udelay(120);
7273
7274         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7275                 u16 val16;
7276
7277                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7278                         int i;
7279                         u32 cfg_val;
7280
7281                         /* Wait for link training to complete.  */
7282                         for (i = 0; i < 5000; i++)
7283                                 udelay(100);
7284
7285                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7286                         pci_write_config_dword(tp->pdev, 0xc4,
7287                                                cfg_val | (1 << 15));
7288                 }
7289
7290                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7291                 pci_read_config_word(tp->pdev,
7292                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7293                                      &val16);
7294                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7295                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7296                 /*
7297                  * Older PCIe devices only support the 128 byte
7298                  * MPS setting.  Enforce the restriction.
7299                  */
7300                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7301                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7302                 pci_write_config_word(tp->pdev,
7303                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7304                                       val16);
7305
7306                 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7307
7308                 /* Clear error status */
7309                 pci_write_config_word(tp->pdev,
7310                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7311                                       PCI_EXP_DEVSTA_CED |
7312                                       PCI_EXP_DEVSTA_NFED |
7313                                       PCI_EXP_DEVSTA_FED |
7314                                       PCI_EXP_DEVSTA_URD);
7315         }
7316
7317         tg3_restore_pci_state(tp);
7318
7319         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7320
7321         val = 0;
7322         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7323                 val = tr32(MEMARB_MODE);
7324         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7325
7326         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7327                 tg3_stop_fw(tp);
7328                 tw32(0x5000, 0x400);
7329         }
7330
7331         tw32(GRC_MODE, tp->grc_mode);
7332
7333         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7334                 val = tr32(0xc4);
7335
7336                 tw32(0xc4, val | (1 << 15));
7337         }
7338
7339         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7340             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7341                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7342                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7343                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7344                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7345         }
7346
7347         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7348                 tp->mac_mode = MAC_MODE_APE_TX_EN |
7349                                MAC_MODE_APE_RX_EN |
7350                                MAC_MODE_TDE_ENABLE;
7351
7352         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7353                 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
7354                 val = tp->mac_mode;
7355         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7356                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7357                 val = tp->mac_mode;
7358         } else
7359                 val = 0;
7360
7361         tw32_f(MAC_MODE, val);
7362         udelay(40);
7363
7364         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7365
7366         err = tg3_poll_fw(tp);
7367         if (err)
7368                 return err;
7369
7370         tg3_mdio_start(tp);
7371
7372         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7373             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7374             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7375             !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
7376                 val = tr32(0x7c00);
7377
7378                 tw32(0x7c00, val | (1 << 25));
7379         }
7380
7381         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
7382                 val = tr32(TG3_CPMU_CLCK_ORIDE);
7383                 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
7384         }
7385
7386         /* Reprobe ASF enable state.  */
7387         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7388         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7389         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7390         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7391                 u32 nic_cfg;
7392
7393                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7394                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7395                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7396                         tp->last_event_jiffies = jiffies;
7397                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7398                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7399                 }
7400         }
7401
7402         return 0;
7403 }
7404
7405 /* tp->lock is held. */
7406 static void tg3_stop_fw(struct tg3 *tp)
7407 {
7408         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7409            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7410                 /* Wait for RX cpu to ACK the previous event. */
7411                 tg3_wait_for_event_ack(tp);
7412
7413                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7414
7415                 tg3_generate_fw_event(tp);
7416
7417                 /* Wait for RX cpu to ACK this event. */
7418                 tg3_wait_for_event_ack(tp);
7419         }
7420 }
7421
7422 /* tp->lock is held. */
7423 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7424 {
7425         int err;
7426
7427         tg3_stop_fw(tp);
7428
7429         tg3_write_sig_pre_reset(tp, kind);
7430
7431         tg3_abort_hw(tp, silent);
7432         err = tg3_chip_reset(tp);
7433
7434         __tg3_set_mac_addr(tp, 0);
7435
7436         tg3_write_sig_legacy(tp, kind);
7437         tg3_write_sig_post_reset(tp, kind);
7438
7439         if (err)
7440                 return err;
7441
7442         return 0;
7443 }
7444
7445 #define RX_CPU_SCRATCH_BASE     0x30000
7446 #define RX_CPU_SCRATCH_SIZE     0x04000
7447 #define TX_CPU_SCRATCH_BASE     0x34000
7448 #define TX_CPU_SCRATCH_SIZE     0x04000
7449
7450 /* tp->lock is held. */
7451 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7452 {
7453         int i;
7454
7455         BUG_ON(offset == TX_CPU_BASE &&
7456             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7457
7458         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7459                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7460
7461                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7462                 return 0;
7463         }
7464         if (offset == RX_CPU_BASE) {
7465                 for (i = 0; i < 10000; i++) {
7466                         tw32(offset + CPU_STATE, 0xffffffff);
7467                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7468                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7469                                 break;
7470                 }
7471
7472                 tw32(offset + CPU_STATE, 0xffffffff);
7473                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7474                 udelay(10);
7475         } else {
7476                 for (i = 0; i < 10000; i++) {
7477                         tw32(offset + CPU_STATE, 0xffffffff);
7478                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7479                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7480                                 break;
7481                 }
7482         }
7483
7484         if (i >= 10000) {
7485                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7486                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7487                 return -ENODEV;
7488         }
7489
7490         /* Clear firmware's nvram arbitration. */
7491         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7492                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7493         return 0;
7494 }
7495
7496 struct fw_info {
7497         unsigned int fw_base;
7498         unsigned int fw_len;
7499         const __be32 *fw_data;
7500 };
7501
7502 /* tp->lock is held. */
7503 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7504                                  int cpu_scratch_size, struct fw_info *info)
7505 {
7506         int err, lock_err, i;
7507         void (*write_op)(struct tg3 *, u32, u32);
7508
7509         if (cpu_base == TX_CPU_BASE &&
7510             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7511                 netdev_err(tp->dev,
7512                            "%s: Trying to load TX cpu firmware which is 5705\n",
7513                            __func__);
7514                 return -EINVAL;
7515         }
7516
7517         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7518                 write_op = tg3_write_mem;
7519         else
7520                 write_op = tg3_write_indirect_reg32;
7521
7522         /* It is possible that bootcode is still loading at this point.
7523          * Get the nvram lock first before halting the cpu.
7524          */
7525         lock_err = tg3_nvram_lock(tp);
7526         err = tg3_halt_cpu(tp, cpu_base);
7527         if (!lock_err)
7528                 tg3_nvram_unlock(tp);
7529         if (err)
7530                 goto out;
7531
7532         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7533                 write_op(tp, cpu_scratch_base + i, 0);
7534         tw32(cpu_base + CPU_STATE, 0xffffffff);
7535         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7536         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7537                 write_op(tp, (cpu_scratch_base +
7538                               (info->fw_base & 0xffff) +
7539                               (i * sizeof(u32))),
7540                               be32_to_cpu(info->fw_data[i]));
7541
7542         err = 0;
7543
7544 out:
7545         return err;
7546 }
7547
7548 /* tp->lock is held. */
7549 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7550 {
7551         struct fw_info info;
7552         const __be32 *fw_data;
7553         int err, i;
7554
7555         fw_data = (void *)tp->fw->data;
7556
7557         /* Firmware blob starts with version numbers, followed by
7558            start address and length. We are setting complete length.
7559            length = end_address_of_bss - start_address_of_text.
7560            Remainder is the blob to be loaded contiguously
7561            from start address. */
7562
7563         info.fw_base = be32_to_cpu(fw_data[1]);
7564         info.fw_len = tp->fw->size - 12;
7565         info.fw_data = &fw_data[3];
7566
7567         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7568                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7569                                     &info);
7570         if (err)
7571                 return err;
7572
7573         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7574                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7575                                     &info);
7576         if (err)
7577                 return err;
7578
7579         /* Now startup only the RX cpu. */
7580         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7581         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7582
7583         for (i = 0; i < 5; i++) {
7584                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7585                         break;
7586                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7587                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7588                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7589                 udelay(1000);
7590         }
7591         if (i >= 5) {
7592                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7593                            "should be %08x\n", __func__,
7594                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7595                 return -ENODEV;
7596         }
7597         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7598         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7599
7600         return 0;
7601 }
7602
7603 /* 5705 needs a special version of the TSO firmware.  */
7604
7605 /* tp->lock is held. */
7606 static int tg3_load_tso_firmware(struct tg3 *tp)
7607 {
7608         struct fw_info info;
7609         const __be32 *fw_data;
7610         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7611         int err, i;
7612
7613         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7614                 return 0;
7615
7616         fw_data = (void *)tp->fw->data;
7617
7618         /* Firmware blob starts with version numbers, followed by
7619            start address and length. We are setting complete length.
7620            length = end_address_of_bss - start_address_of_text.
7621            Remainder is the blob to be loaded contiguously
7622            from start address. */
7623
7624         info.fw_base = be32_to_cpu(fw_data[1]);
7625         cpu_scratch_size = tp->fw_len;
7626         info.fw_len = tp->fw->size - 12;
7627         info.fw_data = &fw_data[3];
7628
7629         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7630                 cpu_base = RX_CPU_BASE;
7631                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7632         } else {
7633                 cpu_base = TX_CPU_BASE;
7634                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7635                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7636         }
7637
7638         err = tg3_load_firmware_cpu(tp, cpu_base,
7639                                     cpu_scratch_base, cpu_scratch_size,
7640                                     &info);
7641         if (err)
7642                 return err;
7643
7644         /* Now startup the cpu. */
7645         tw32(cpu_base + CPU_STATE, 0xffffffff);
7646         tw32_f(cpu_base + CPU_PC, info.fw_base);
7647
7648         for (i = 0; i < 5; i++) {
7649                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7650                         break;
7651                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7652                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7653                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7654                 udelay(1000);
7655         }
7656         if (i >= 5) {
7657                 netdev_err(tp->dev,
7658                            "%s fails to set CPU PC, is %08x should be %08x\n",
7659                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7660                 return -ENODEV;
7661         }
7662         tw32(cpu_base + CPU_STATE, 0xffffffff);
7663         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7664         return 0;
7665 }
7666
7667
7668 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7669 {
7670         struct tg3 *tp = netdev_priv(dev);
7671         struct sockaddr *addr = p;
7672         int err = 0, skip_mac_1 = 0;
7673
7674         if (!is_valid_ether_addr(addr->sa_data))
7675                 return -EINVAL;
7676
7677         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7678
7679         if (!netif_running(dev))
7680                 return 0;
7681
7682         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7683                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7684
7685                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7686                 addr0_low = tr32(MAC_ADDR_0_LOW);
7687                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7688                 addr1_low = tr32(MAC_ADDR_1_LOW);
7689
7690                 /* Skip MAC addr 1 if ASF is using it. */
7691                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7692                     !(addr1_high == 0 && addr1_low == 0))
7693                         skip_mac_1 = 1;
7694         }
7695         spin_lock_bh(&tp->lock);
7696         __tg3_set_mac_addr(tp, skip_mac_1);
7697         spin_unlock_bh(&tp->lock);
7698
7699         return err;
7700 }
7701
7702 /* tp->lock is held. */
7703 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7704                            dma_addr_t mapping, u32 maxlen_flags,
7705                            u32 nic_addr)
7706 {
7707         tg3_write_mem(tp,
7708                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7709                       ((u64) mapping >> 32));
7710         tg3_write_mem(tp,
7711                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7712                       ((u64) mapping & 0xffffffff));
7713         tg3_write_mem(tp,
7714                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7715                        maxlen_flags);
7716
7717         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7718                 tg3_write_mem(tp,
7719                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7720                               nic_addr);
7721 }
7722
7723 static void __tg3_set_rx_mode(struct net_device *);
7724 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7725 {
7726         int i;
7727
7728         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7729                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7730                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7731                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7732         } else {
7733                 tw32(HOSTCC_TXCOL_TICKS, 0);
7734                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7735                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7736         }
7737
7738         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7739                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7740                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7741                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7742         } else {
7743                 tw32(HOSTCC_RXCOL_TICKS, 0);
7744                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7745                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7746         }
7747
7748         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7749                 u32 val = ec->stats_block_coalesce_usecs;
7750
7751                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7752                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7753
7754                 if (!netif_carrier_ok(tp->dev))
7755                         val = 0;
7756
7757                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7758         }
7759
7760         for (i = 0; i < tp->irq_cnt - 1; i++) {
7761                 u32 reg;
7762
7763                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7764                 tw32(reg, ec->rx_coalesce_usecs);
7765                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7766                 tw32(reg, ec->rx_max_coalesced_frames);
7767                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7768                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7769
7770                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7771                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7772                         tw32(reg, ec->tx_coalesce_usecs);
7773                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7774                         tw32(reg, ec->tx_max_coalesced_frames);
7775                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7776                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7777                 }
7778         }
7779
7780         for (; i < tp->irq_max - 1; i++) {
7781                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7782                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7783                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7784
7785                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7786                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7787                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7788                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7789                 }
7790         }
7791 }
7792
7793 /* tp->lock is held. */
7794 static void tg3_rings_reset(struct tg3 *tp)
7795 {
7796         int i;
7797         u32 stblk, txrcb, rxrcb, limit;
7798         struct tg3_napi *tnapi = &tp->napi[0];
7799
7800         /* Disable all transmit rings but the first. */
7801         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7802                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7803         else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7804                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7805         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7806                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7807         else
7808                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7809
7810         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7811              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7812                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7813                               BDINFO_FLAGS_DISABLED);
7814
7815
7816         /* Disable all receive return rings but the first. */
7817         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7818                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7819         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7820                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7821         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7822                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7823                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7824         else
7825                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7826
7827         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7828              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7829                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7830                               BDINFO_FLAGS_DISABLED);
7831
7832         /* Disable interrupts */
7833         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7834
7835         /* Zero mailbox registers. */
7836         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7837                 for (i = 1; i < tp->irq_max; i++) {
7838                         tp->napi[i].tx_prod = 0;
7839                         tp->napi[i].tx_cons = 0;
7840                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7841                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7842                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7843                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7844                 }
7845                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7846                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7847         } else {
7848                 tp->napi[0].tx_prod = 0;
7849                 tp->napi[0].tx_cons = 0;
7850                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7851                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7852         }
7853
7854         /* Make sure the NIC-based send BD rings are disabled. */
7855         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7856                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7857                 for (i = 0; i < 16; i++)
7858                         tw32_tx_mbox(mbox + i * 8, 0);
7859         }
7860
7861         txrcb = NIC_SRAM_SEND_RCB;
7862         rxrcb = NIC_SRAM_RCV_RET_RCB;
7863
7864         /* Clear status block in ram. */
7865         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7866
7867         /* Set status block DMA address */
7868         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7869              ((u64) tnapi->status_mapping >> 32));
7870         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7871              ((u64) tnapi->status_mapping & 0xffffffff));
7872
7873         if (tnapi->tx_ring) {
7874                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7875                                (TG3_TX_RING_SIZE <<
7876                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7877                                NIC_SRAM_TX_BUFFER_DESC);
7878                 txrcb += TG3_BDINFO_SIZE;
7879         }
7880
7881         if (tnapi->rx_rcb) {
7882                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7883                                (tp->rx_ret_ring_mask + 1) <<
7884                                 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7885                 rxrcb += TG3_BDINFO_SIZE;
7886         }
7887
7888         stblk = HOSTCC_STATBLCK_RING1;
7889
7890         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7891                 u64 mapping = (u64)tnapi->status_mapping;
7892                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7893                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7894
7895                 /* Clear status block in ram. */
7896                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7897
7898                 if (tnapi->tx_ring) {
7899                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7900                                        (TG3_TX_RING_SIZE <<
7901                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7902                                        NIC_SRAM_TX_BUFFER_DESC);
7903                         txrcb += TG3_BDINFO_SIZE;
7904                 }
7905
7906                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7907                                ((tp->rx_ret_ring_mask + 1) <<
7908                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7909
7910                 stblk += 8;
7911                 rxrcb += TG3_BDINFO_SIZE;
7912         }
7913 }
7914
7915 /* tp->lock is held. */
7916 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7917 {
7918         u32 val, rdmac_mode;
7919         int i, err, limit;
7920         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7921
7922         tg3_disable_ints(tp);
7923
7924         tg3_stop_fw(tp);
7925
7926         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7927
7928         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7929                 tg3_abort_hw(tp, 1);
7930
7931         /* Enable MAC control of LPI */
7932         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7933                 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7934                        TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7935                        TG3_CPMU_EEE_LNKIDL_UART_IDL);
7936
7937                 tw32_f(TG3_CPMU_EEE_CTRL,
7938                        TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7939
7940                 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7941                       TG3_CPMU_EEEMD_LPI_IN_TX |
7942                       TG3_CPMU_EEEMD_LPI_IN_RX |
7943                       TG3_CPMU_EEEMD_EEE_ENABLE;
7944
7945                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7946                         val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
7947
7948                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7949                         val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
7950
7951                 tw32_f(TG3_CPMU_EEE_MODE, val);
7952
7953                 tw32_f(TG3_CPMU_EEE_DBTMR1,
7954                        TG3_CPMU_DBTMR1_PCIEXIT_2047US |
7955                        TG3_CPMU_DBTMR1_LNKIDLE_2047US);
7956
7957                 tw32_f(TG3_CPMU_EEE_DBTMR2,
7958                        TG3_CPMU_DBTMR2_APE_TX_2047US |
7959                        TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
7960         }
7961
7962         if (reset_phy)
7963                 tg3_phy_reset(tp);
7964
7965         err = tg3_chip_reset(tp);
7966         if (err)
7967                 return err;
7968
7969         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7970
7971         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7972                 val = tr32(TG3_CPMU_CTRL);
7973                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7974                 tw32(TG3_CPMU_CTRL, val);
7975
7976                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7977                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7978                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7979                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7980
7981                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7982                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7983                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7984                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7985
7986                 val = tr32(TG3_CPMU_HST_ACC);
7987                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7988                 val |= CPMU_HST_ACC_MACCLK_6_25;
7989                 tw32(TG3_CPMU_HST_ACC, val);
7990         }
7991
7992         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7993                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7994                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7995                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7996                 tw32(PCIE_PWR_MGMT_THRESH, val);
7997
7998                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7999                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8000
8001                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
8002
8003                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8004                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8005         }
8006
8007         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
8008                 u32 grc_mode = tr32(GRC_MODE);
8009
8010                 /* Access the lower 1K of PL PCIE block registers. */
8011                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8012                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8013
8014                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8015                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8016                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8017
8018                 tw32(GRC_MODE, grc_mode);
8019         }
8020
8021         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
8022                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8023                         u32 grc_mode = tr32(GRC_MODE);
8024
8025                         /* Access the lower 1K of PL PCIE block registers. */
8026                         val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8027                         tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8028
8029                         val = tr32(TG3_PCIE_TLDLPL_PORT +
8030                                    TG3_PCIE_PL_LO_PHYCTL5);
8031                         tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8032                              val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
8033
8034                         tw32(GRC_MODE, grc_mode);
8035                 }
8036
8037                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8038                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8039                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8040                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8041         }
8042
8043         /* This works around an issue with Athlon chipsets on
8044          * B3 tigon3 silicon.  This bit has no effect on any
8045          * other revision.  But do not set this on PCI Express
8046          * chips and don't even touch the clocks if the CPMU is present.
8047          */
8048         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
8049                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
8050                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8051                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8052         }
8053
8054         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8055             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
8056                 val = tr32(TG3PCI_PCISTATE);
8057                 val |= PCISTATE_RETRY_SAME_DMA;
8058                 tw32(TG3PCI_PCISTATE, val);
8059         }
8060
8061         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
8062                 /* Allow reads and writes to the
8063                  * APE register and memory space.
8064                  */
8065                 val = tr32(TG3PCI_PCISTATE);
8066                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8067                        PCISTATE_ALLOW_APE_SHMEM_WR |
8068                        PCISTATE_ALLOW_APE_PSPACE_WR;
8069                 tw32(TG3PCI_PCISTATE, val);
8070         }
8071
8072         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8073                 /* Enable some hw fixes.  */
8074                 val = tr32(TG3PCI_MSI_DATA);
8075                 val |= (1 << 26) | (1 << 28) | (1 << 29);
8076                 tw32(TG3PCI_MSI_DATA, val);
8077         }
8078
8079         /* Descriptor ring init may make accesses to the
8080          * NIC SRAM area to setup the TX descriptors, so we
8081          * can only do this after the hardware has been
8082          * successfully reset.
8083          */
8084         err = tg3_init_rings(tp);
8085         if (err)
8086                 return err;
8087
8088         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
8089                 val = tr32(TG3PCI_DMA_RW_CTRL) &
8090                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8091                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8092                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8093                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8094         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8095                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
8096                 /* This value is determined during the probe time DMA
8097                  * engine test, tg3_test_dma.
8098                  */
8099                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8100         }
8101
8102         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8103                           GRC_MODE_4X_NIC_SEND_RINGS |
8104                           GRC_MODE_NO_TX_PHDR_CSUM |
8105                           GRC_MODE_NO_RX_PHDR_CSUM);
8106         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
8107
8108         /* Pseudo-header checksum is done by hardware logic and not
8109          * the offload processers, so make the chip do the pseudo-
8110          * header checksums on receive.  For transmit it is more
8111          * convenient to do the pseudo-header checksum in software
8112          * as Linux does that on transmit for us in all cases.
8113          */
8114         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8115
8116         tw32(GRC_MODE,
8117              tp->grc_mode |
8118              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8119
8120         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
8121         val = tr32(GRC_MISC_CFG);
8122         val &= ~0xff;
8123         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8124         tw32(GRC_MISC_CFG, val);
8125
8126         /* Initialize MBUF/DESC pool. */
8127         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8128                 /* Do nothing.  */
8129         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8130                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8131                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8132                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8133                 else
8134                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8135                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8136                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8137         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8138                 int fw_len;
8139
8140                 fw_len = tp->fw_len;
8141                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8142                 tw32(BUFMGR_MB_POOL_ADDR,
8143                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8144                 tw32(BUFMGR_MB_POOL_SIZE,
8145                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8146         }
8147
8148         if (tp->dev->mtu <= ETH_DATA_LEN) {
8149                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8150                      tp->bufmgr_config.mbuf_read_dma_low_water);
8151                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8152                      tp->bufmgr_config.mbuf_mac_rx_low_water);
8153                 tw32(BUFMGR_MB_HIGH_WATER,
8154                      tp->bufmgr_config.mbuf_high_water);
8155         } else {
8156                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8157                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8158                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8159                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8160                 tw32(BUFMGR_MB_HIGH_WATER,
8161                      tp->bufmgr_config.mbuf_high_water_jumbo);
8162         }
8163         tw32(BUFMGR_DMA_LOW_WATER,
8164              tp->bufmgr_config.dma_low_water);
8165         tw32(BUFMGR_DMA_HIGH_WATER,
8166              tp->bufmgr_config.dma_high_water);
8167
8168         val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8169         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8170                 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8171         tw32(BUFMGR_MODE, val);
8172         for (i = 0; i < 2000; i++) {
8173                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8174                         break;
8175                 udelay(10);
8176         }
8177         if (i >= 2000) {
8178                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8179                 return -ENODEV;
8180         }
8181
8182         /* Setup replenish threshold. */
8183         val = tp->rx_pending / 8;
8184         if (val == 0)
8185                 val = 1;
8186         else if (val > tp->rx_std_max_post)
8187                 val = tp->rx_std_max_post;
8188         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8189                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8190                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8191
8192                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
8193                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
8194         }
8195
8196         tw32(RCVBDI_STD_THRESH, val);
8197
8198         /* Initialize TG3_BDINFO's at:
8199          *  RCVDBDI_STD_BD:     standard eth size rx ring
8200          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
8201          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
8202          *
8203          * like so:
8204          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
8205          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
8206          *                              ring attribute flags
8207          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
8208          *
8209          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8210          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8211          *
8212          * The size of each ring is fixed in the firmware, but the location is
8213          * configurable.
8214          */
8215         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8216              ((u64) tpr->rx_std_mapping >> 32));
8217         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8218              ((u64) tpr->rx_std_mapping & 0xffffffff));
8219         if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
8220                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8221                      NIC_SRAM_RX_BUFFER_DESC);
8222
8223         /* Disable the mini ring */
8224         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8225                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8226                      BDINFO_FLAGS_DISABLED);
8227
8228         /* Program the jumbo buffer descriptor ring control
8229          * blocks on those devices that have them.
8230          */
8231         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8232             ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8233             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) {
8234                 /* Setup replenish threshold. */
8235                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
8236
8237                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
8238                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8239                              ((u64) tpr->rx_jmb_mapping >> 32));
8240                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8241                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8242                         val = TG3_RX_JMB_RING_SIZE(tp) <<
8243                               BDINFO_FLAGS_MAXLEN_SHIFT;
8244                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8245                              val | BDINFO_FLAGS_USE_EXT_RECV);
8246                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8247                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8248                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8249                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8250                 } else {
8251                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8252                              BDINFO_FLAGS_DISABLED);
8253                 }
8254
8255                 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
8256                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8257                                 val = TG3_RX_STD_MAX_SIZE_5700;
8258                         else
8259                                 val = TG3_RX_STD_MAX_SIZE_5717;
8260                         val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8261                         val |= (TG3_RX_STD_DMA_SZ << 2);
8262                 } else
8263                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8264         } else
8265                 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8266
8267         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8268
8269         tpr->rx_std_prod_idx = tp->rx_pending;
8270         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8271
8272         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8273                           tp->rx_jumbo_pending : 0;
8274         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8275
8276         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
8277                 tw32(STD_REPLENISH_LWM, 32);
8278                 tw32(JMB_REPLENISH_LWM, 16);
8279         }
8280
8281         tg3_rings_reset(tp);
8282
8283         /* Initialize MAC address and backoff seed. */
8284         __tg3_set_mac_addr(tp, 0);
8285
8286         /* MTU + ethernet header + FCS + optional VLAN tag */
8287         tw32(MAC_RX_MTU_SIZE,
8288              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8289
8290         /* The slot time is changed by tg3_setup_phy if we
8291          * run at gigabit with half duplex.
8292          */
8293         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8294               (6 << TX_LENGTHS_IPG_SHIFT) |
8295               (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8296
8297         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8298                 val |= tr32(MAC_TX_LENGTHS) &
8299                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
8300                         TX_LENGTHS_CNT_DWN_VAL_MSK);
8301
8302         tw32(MAC_TX_LENGTHS, val);
8303
8304         /* Receive rules. */
8305         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8306         tw32(RCVLPC_CONFIG, 0x0181);
8307
8308         /* Calculate RDMAC_MODE setting early, we need it to determine
8309          * the RCVLPC_STATE_ENABLE mask.
8310          */
8311         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8312                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8313                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8314                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8315                       RDMAC_MODE_LNGREAD_ENAB);
8316
8317         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8318                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8319
8320         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8321             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8322             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8323                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8324                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8325                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8326
8327         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8328             tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8329                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8330                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8331                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8332                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8333                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8334                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8335                 }
8336         }
8337
8338         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8339                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8340
8341         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8342                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8343
8344         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8345             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8346             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8347                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8348
8349         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8350                 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8351
8352         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8353             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8354             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8355             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8356             (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
8357                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8358                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8359                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8360                         val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8361                                  TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8362                                  TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8363                         val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8364                                TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8365                                TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8366                 }
8367                 tw32(TG3_RDMA_RSRVCTRL_REG,
8368                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8369         }
8370
8371         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8372             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8373                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8374                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8375                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8376                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8377         }
8378
8379         /* Receive/send statistics. */
8380         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8381                 val = tr32(RCVLPC_STATS_ENABLE);
8382                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8383                 tw32(RCVLPC_STATS_ENABLE, val);
8384         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8385                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8386                 val = tr32(RCVLPC_STATS_ENABLE);
8387                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8388                 tw32(RCVLPC_STATS_ENABLE, val);
8389         } else {
8390                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8391         }
8392         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8393         tw32(SNDDATAI_STATSENAB, 0xffffff);
8394         tw32(SNDDATAI_STATSCTRL,
8395              (SNDDATAI_SCTRL_ENABLE |
8396               SNDDATAI_SCTRL_FASTUPD));
8397
8398         /* Setup host coalescing engine. */
8399         tw32(HOSTCC_MODE, 0);
8400         for (i = 0; i < 2000; i++) {
8401                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8402                         break;
8403                 udelay(10);
8404         }
8405
8406         __tg3_set_coalesce(tp, &tp->coal);
8407
8408         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8409                 /* Status/statistics block address.  See tg3_timer,
8410                  * the tg3_periodic_fetch_stats call there, and
8411                  * tg3_get_stats to see how this works for 5705/5750 chips.
8412                  */
8413                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8414                      ((u64) tp->stats_mapping >> 32));
8415                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8416                      ((u64) tp->stats_mapping & 0xffffffff));
8417                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8418
8419                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8420
8421                 /* Clear statistics and status block memory areas */
8422                 for (i = NIC_SRAM_STATS_BLK;
8423                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8424                      i += sizeof(u32)) {
8425                         tg3_write_mem(tp, i, 0);
8426                         udelay(40);
8427                 }
8428         }
8429
8430         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8431
8432         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8433         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8434         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8435                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8436
8437         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8438                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8439                 /* reset to prevent losing 1st rx packet intermittently */
8440                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8441                 udelay(10);
8442         }
8443
8444         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8445                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8446         else
8447                 tp->mac_mode = 0;
8448         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8449                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8450         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8451             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8452             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8453                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8454         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8455         udelay(40);
8456
8457         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8458          * If TG3_FLG2_IS_NIC is zero, we should read the
8459          * register to preserve the GPIO settings for LOMs. The GPIOs,
8460          * whether used as inputs or outputs, are set by boot code after
8461          * reset.
8462          */
8463         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8464                 u32 gpio_mask;
8465
8466                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8467                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8468                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8469
8470                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8471                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8472                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8473
8474                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8475                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8476
8477                 tp->grc_local_ctrl &= ~gpio_mask;
8478                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8479
8480                 /* GPIO1 must be driven high for eeprom write protect */
8481                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8482                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8483                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8484         }
8485         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8486         udelay(100);
8487
8488         if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
8489                 tp->irq_cnt > 1) {
8490                 val = tr32(MSGINT_MODE);
8491                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8492                 tw32(MSGINT_MODE, val);
8493         }
8494
8495         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8496                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8497                 udelay(40);
8498         }
8499
8500         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8501                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8502                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8503                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8504                WDMAC_MODE_LNGREAD_ENAB);
8505
8506         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8507             tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8508                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8509                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8510                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8511                         /* nothing */
8512                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8513                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8514                         val |= WDMAC_MODE_RX_ACCEL;
8515                 }
8516         }
8517
8518         /* Enable host coalescing bug fix */
8519         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8520                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8521
8522         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8523                 val |= WDMAC_MODE_BURST_ALL_DATA;
8524
8525         tw32_f(WDMAC_MODE, val);
8526         udelay(40);
8527
8528         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8529                 u16 pcix_cmd;
8530
8531                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8532                                      &pcix_cmd);
8533                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8534                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8535                         pcix_cmd |= PCI_X_CMD_READ_2K;
8536                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8537                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8538                         pcix_cmd |= PCI_X_CMD_READ_2K;
8539                 }
8540                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8541                                       pcix_cmd);
8542         }
8543
8544         tw32_f(RDMAC_MODE, rdmac_mode);
8545         udelay(40);
8546
8547         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8548         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8549                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8550
8551         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8552                 tw32(SNDDATAC_MODE,
8553                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8554         else
8555                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8556
8557         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8558         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8559         val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8560         if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
8561                 val |= RCVDBDI_MODE_LRG_RING_SZ;
8562         tw32(RCVDBDI_MODE, val);
8563         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8564         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8565                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8566         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8567         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8568                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8569         tw32(SNDBDI_MODE, val);
8570         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8571
8572         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8573                 err = tg3_load_5701_a0_firmware_fix(tp);
8574                 if (err)
8575                         return err;
8576         }
8577
8578         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8579                 err = tg3_load_tso_firmware(tp);
8580                 if (err)
8581                         return err;
8582         }
8583
8584         tp->tx_mode = TX_MODE_ENABLE;
8585
8586         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8587             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8588                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8589
8590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8591                 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
8592                 tp->tx_mode &= ~val;
8593                 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
8594         }
8595
8596         tw32_f(MAC_TX_MODE, tp->tx_mode);
8597         udelay(100);
8598
8599         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8600                 u32 reg = MAC_RSS_INDIR_TBL_0;
8601                 u8 *ent = (u8 *)&val;
8602
8603                 /* Setup the indirection table */
8604                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8605                         int idx = i % sizeof(val);
8606
8607                         ent[idx] = i % (tp->irq_cnt - 1);
8608                         if (idx == sizeof(val) - 1) {
8609                                 tw32(reg, val);
8610                                 reg += 4;
8611                         }
8612                 }
8613
8614                 /* Setup the "secret" hash key. */
8615                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8616                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8617                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8618                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8619                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8620                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8621                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8622                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8623                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8624                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8625         }
8626
8627         tp->rx_mode = RX_MODE_ENABLE;
8628         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8629                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8630
8631         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8632                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8633                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8634                                RX_MODE_RSS_IPV6_HASH_EN |
8635                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8636                                RX_MODE_RSS_IPV4_HASH_EN |
8637                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8638
8639         tw32_f(MAC_RX_MODE, tp->rx_mode);
8640         udelay(10);
8641
8642         tw32(MAC_LED_CTRL, tp->led_ctrl);
8643
8644         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8645         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8646                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8647                 udelay(10);
8648         }
8649         tw32_f(MAC_RX_MODE, tp->rx_mode);
8650         udelay(10);
8651
8652         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8653                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8654                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8655                         /* Set drive transmission level to 1.2V  */
8656                         /* only if the signal pre-emphasis bit is not set  */
8657                         val = tr32(MAC_SERDES_CFG);
8658                         val &= 0xfffff000;
8659                         val |= 0x880;
8660                         tw32(MAC_SERDES_CFG, val);
8661                 }
8662                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8663                         tw32(MAC_SERDES_CFG, 0x616000);
8664         }
8665
8666         /* Prevent chip from dropping frames when flow control
8667          * is enabled.
8668          */
8669         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8670                 val = 1;
8671         else
8672                 val = 2;
8673         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8674
8675         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8676             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8677                 /* Use hardware link auto-negotiation */
8678                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8679         }
8680
8681         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8682             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8683                 u32 tmp;
8684
8685                 tmp = tr32(SERDES_RX_CTRL);
8686                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8687                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8688                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8689                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8690         }
8691
8692         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8693                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8694                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8695                         tp->link_config.speed = tp->link_config.orig_speed;
8696                         tp->link_config.duplex = tp->link_config.orig_duplex;
8697                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8698                 }
8699
8700                 err = tg3_setup_phy(tp, 0);
8701                 if (err)
8702                         return err;
8703
8704                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8705                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8706                         u32 tmp;
8707
8708                         /* Clear CRC stats. */
8709                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8710                                 tg3_writephy(tp, MII_TG3_TEST1,
8711                                              tmp | MII_TG3_TEST1_CRC_EN);
8712                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8713                         }
8714                 }
8715         }
8716
8717         __tg3_set_rx_mode(tp->dev);
8718
8719         /* Initialize receive rules. */
8720         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8721         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8722         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8723         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8724
8725         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8726             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8727                 limit = 8;
8728         else
8729                 limit = 16;
8730         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8731                 limit -= 4;
8732         switch (limit) {
8733         case 16:
8734                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8735         case 15:
8736                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8737         case 14:
8738                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8739         case 13:
8740                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8741         case 12:
8742                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8743         case 11:
8744                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8745         case 10:
8746                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8747         case 9:
8748                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8749         case 8:
8750                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8751         case 7:
8752                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8753         case 6:
8754                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8755         case 5:
8756                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8757         case 4:
8758                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8759         case 3:
8760                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8761         case 2:
8762         case 1:
8763
8764         default:
8765                 break;
8766         }
8767
8768         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8769                 /* Write our heartbeat update interval to APE. */
8770                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8771                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8772
8773         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8774
8775         return 0;
8776 }
8777
8778 /* Called at device open time to get the chip ready for
8779  * packet processing.  Invoked with tp->lock held.
8780  */
8781 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8782 {
8783         tg3_switch_clocks(tp);
8784
8785         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8786
8787         return tg3_reset_hw(tp, reset_phy);
8788 }
8789
8790 #define TG3_STAT_ADD32(PSTAT, REG) \
8791 do {    u32 __val = tr32(REG); \
8792         (PSTAT)->low += __val; \
8793         if ((PSTAT)->low < __val) \
8794                 (PSTAT)->high += 1; \
8795 } while (0)
8796
8797 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8798 {
8799         struct tg3_hw_stats *sp = tp->hw_stats;
8800
8801         if (!netif_carrier_ok(tp->dev))
8802                 return;
8803
8804         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8805         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8806         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8807         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8808         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8809         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8810         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8811         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8812         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8813         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8814         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8815         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8816         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8817
8818         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8819         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8820         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8821         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8822         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8823         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8824         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8825         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8826         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8827         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8828         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8829         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8830         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8831         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8832
8833         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8834         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8835         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8836 }
8837
8838 static void tg3_timer(unsigned long __opaque)
8839 {
8840         struct tg3 *tp = (struct tg3 *) __opaque;
8841
8842         if (tp->irq_sync)
8843                 goto restart_timer;
8844
8845         spin_lock(&tp->lock);
8846
8847         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8848                 /* All of this garbage is because when using non-tagged
8849                  * IRQ status the mailbox/status_block protocol the chip
8850                  * uses with the cpu is race prone.
8851                  */
8852                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8853                         tw32(GRC_LOCAL_CTRL,
8854                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8855                 } else {
8856                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8857                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8858                 }
8859
8860                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8861                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8862                         spin_unlock(&tp->lock);
8863                         schedule_work(&tp->reset_task);
8864                         return;
8865                 }
8866         }
8867
8868         /* This part only runs once per second. */
8869         if (!--tp->timer_counter) {
8870                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8871                         tg3_periodic_fetch_stats(tp);
8872
8873                 if (tp->setlpicnt && !--tp->setlpicnt) {
8874                         u32 val = tr32(TG3_CPMU_EEE_MODE);
8875                         tw32(TG3_CPMU_EEE_MODE,
8876                              val | TG3_CPMU_EEEMD_LPI_ENABLE);
8877                 }
8878
8879                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8880                         u32 mac_stat;
8881                         int phy_event;
8882
8883                         mac_stat = tr32(MAC_STATUS);
8884
8885                         phy_event = 0;
8886                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8887                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8888                                         phy_event = 1;
8889                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8890                                 phy_event = 1;
8891
8892                         if (phy_event)
8893                                 tg3_setup_phy(tp, 0);
8894                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8895                         u32 mac_stat = tr32(MAC_STATUS);
8896                         int need_setup = 0;
8897
8898                         if (netif_carrier_ok(tp->dev) &&
8899                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8900                                 need_setup = 1;
8901                         }
8902                         if (!netif_carrier_ok(tp->dev) &&
8903                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8904                                          MAC_STATUS_SIGNAL_DET))) {
8905                                 need_setup = 1;
8906                         }
8907                         if (need_setup) {
8908                                 if (!tp->serdes_counter) {
8909                                         tw32_f(MAC_MODE,
8910                                              (tp->mac_mode &
8911                                               ~MAC_MODE_PORT_MODE_MASK));
8912                                         udelay(40);
8913                                         tw32_f(MAC_MODE, tp->mac_mode);
8914                                         udelay(40);
8915                                 }
8916                                 tg3_setup_phy(tp, 0);
8917                         }
8918                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8919                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8920                         tg3_serdes_parallel_detect(tp);
8921                 }
8922
8923                 tp->timer_counter = tp->timer_multiplier;
8924         }
8925
8926         /* Heartbeat is only sent once every 2 seconds.
8927          *
8928          * The heartbeat is to tell the ASF firmware that the host
8929          * driver is still alive.  In the event that the OS crashes,
8930          * ASF needs to reset the hardware to free up the FIFO space
8931          * that may be filled with rx packets destined for the host.
8932          * If the FIFO is full, ASF will no longer function properly.
8933          *
8934          * Unintended resets have been reported on real time kernels
8935          * where the timer doesn't run on time.  Netpoll will also have
8936          * same problem.
8937          *
8938          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8939          * to check the ring condition when the heartbeat is expiring
8940          * before doing the reset.  This will prevent most unintended
8941          * resets.
8942          */
8943         if (!--tp->asf_counter) {
8944                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8945                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8946                         tg3_wait_for_event_ack(tp);
8947
8948                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8949                                       FWCMD_NICDRV_ALIVE3);
8950                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8951                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8952                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8953
8954                         tg3_generate_fw_event(tp);
8955                 }
8956                 tp->asf_counter = tp->asf_multiplier;
8957         }
8958
8959         spin_unlock(&tp->lock);
8960
8961 restart_timer:
8962         tp->timer.expires = jiffies + tp->timer_offset;
8963         add_timer(&tp->timer);
8964 }
8965
8966 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8967 {
8968         irq_handler_t fn;
8969         unsigned long flags;
8970         char *name;
8971         struct tg3_napi *tnapi = &tp->napi[irq_num];
8972
8973         if (tp->irq_cnt == 1)
8974                 name = tp->dev->name;
8975         else {
8976                 name = &tnapi->irq_lbl[0];
8977                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8978                 name[IFNAMSIZ-1] = 0;
8979         }
8980
8981         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8982                 fn = tg3_msi;
8983                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8984                         fn = tg3_msi_1shot;
8985                 flags = 0;
8986         } else {
8987                 fn = tg3_interrupt;
8988                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8989                         fn = tg3_interrupt_tagged;
8990                 flags = IRQF_SHARED;
8991         }
8992
8993         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8994 }
8995
8996 static int tg3_test_interrupt(struct tg3 *tp)
8997 {
8998         struct tg3_napi *tnapi = &tp->napi[0];
8999         struct net_device *dev = tp->dev;
9000         int err, i, intr_ok = 0;
9001         u32 val;
9002
9003         if (!netif_running(dev))
9004                 return -ENODEV;
9005
9006         tg3_disable_ints(tp);
9007
9008         free_irq(tnapi->irq_vec, tnapi);
9009
9010         /*
9011          * Turn off MSI one shot mode.  Otherwise this test has no
9012          * observable way to know whether the interrupt was delivered.
9013          */
9014         if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
9015             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9016                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
9017                 tw32(MSGINT_MODE, val);
9018         }
9019
9020         err = request_irq(tnapi->irq_vec, tg3_test_isr,
9021                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
9022         if (err)
9023                 return err;
9024
9025         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
9026         tg3_enable_ints(tp);
9027
9028         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9029                tnapi->coal_now);
9030
9031         for (i = 0; i < 5; i++) {
9032                 u32 int_mbox, misc_host_ctrl;
9033
9034                 int_mbox = tr32_mailbox(tnapi->int_mbox);
9035                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9036
9037                 if ((int_mbox != 0) ||
9038                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
9039                         intr_ok = 1;
9040                         break;
9041                 }
9042
9043                 msleep(10);
9044         }
9045
9046         tg3_disable_ints(tp);
9047
9048         free_irq(tnapi->irq_vec, tnapi);
9049
9050         err = tg3_request_irq(tp, 0);
9051
9052         if (err)
9053                 return err;
9054
9055         if (intr_ok) {
9056                 /* Reenable MSI one shot mode. */
9057                 if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
9058                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9059                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9060                         tw32(MSGINT_MODE, val);
9061                 }
9062                 return 0;
9063         }
9064
9065         return -EIO;
9066 }
9067
9068 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9069  * successfully restored
9070  */
9071 static int tg3_test_msi(struct tg3 *tp)
9072 {
9073         int err;
9074         u16 pci_cmd;
9075
9076         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
9077                 return 0;
9078
9079         /* Turn off SERR reporting in case MSI terminates with Master
9080          * Abort.
9081          */
9082         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9083         pci_write_config_word(tp->pdev, PCI_COMMAND,
9084                               pci_cmd & ~PCI_COMMAND_SERR);
9085
9086         err = tg3_test_interrupt(tp);
9087
9088         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9089
9090         if (!err)
9091                 return 0;
9092
9093         /* other failures */
9094         if (err != -EIO)
9095                 return err;
9096
9097         /* MSI test failed, go back to INTx mode */
9098         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
9099                     "to INTx mode. Please report this failure to the PCI "
9100                     "maintainer and include system chipset information\n");
9101
9102         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9103
9104         pci_disable_msi(tp->pdev);
9105
9106         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
9107         tp->napi[0].irq_vec = tp->pdev->irq;
9108
9109         err = tg3_request_irq(tp, 0);
9110         if (err)
9111                 return err;
9112
9113         /* Need to reset the chip because the MSI cycle may have terminated
9114          * with Master Abort.
9115          */
9116         tg3_full_lock(tp, 1);
9117
9118         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9119         err = tg3_init_hw(tp, 1);
9120
9121         tg3_full_unlock(tp);
9122
9123         if (err)
9124                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9125
9126         return err;
9127 }
9128
9129 static int tg3_request_firmware(struct tg3 *tp)
9130 {
9131         const __be32 *fw_data;
9132
9133         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
9134                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9135                            tp->fw_needed);
9136                 return -ENOENT;
9137         }
9138
9139         fw_data = (void *)tp->fw->data;
9140
9141         /* Firmware blob starts with version numbers, followed by
9142          * start address and _full_ length including BSS sections
9143          * (which must be longer than the actual data, of course
9144          */
9145
9146         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
9147         if (tp->fw_len < (tp->fw->size - 12)) {
9148                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9149                            tp->fw_len, tp->fw_needed);
9150                 release_firmware(tp->fw);
9151                 tp->fw = NULL;
9152                 return -EINVAL;
9153         }
9154
9155         /* We no longer need firmware; we have it. */
9156         tp->fw_needed = NULL;
9157         return 0;
9158 }
9159
9160 static bool tg3_enable_msix(struct tg3 *tp)
9161 {
9162         int i, rc, cpus = num_online_cpus();
9163         struct msix_entry msix_ent[tp->irq_max];
9164
9165         if (cpus == 1)
9166                 /* Just fallback to the simpler MSI mode. */
9167                 return false;
9168
9169         /*
9170          * We want as many rx rings enabled as there are cpus.
9171          * The first MSIX vector only deals with link interrupts, etc,
9172          * so we add one to the number of vectors we are requesting.
9173          */
9174         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9175
9176         for (i = 0; i < tp->irq_max; i++) {
9177                 msix_ent[i].entry  = i;
9178                 msix_ent[i].vector = 0;
9179         }
9180
9181         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9182         if (rc < 0) {
9183                 return false;
9184         } else if (rc != 0) {
9185                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9186                         return false;
9187                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9188                               tp->irq_cnt, rc);
9189                 tp->irq_cnt = rc;
9190         }
9191
9192         for (i = 0; i < tp->irq_max; i++)
9193                 tp->napi[i].irq_vec = msix_ent[i].vector;
9194
9195         netif_set_real_num_tx_queues(tp->dev, 1);
9196         rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9197         if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9198                 pci_disable_msix(tp->pdev);
9199                 return false;
9200         }
9201
9202         if (tp->irq_cnt > 1) {
9203                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
9204
9205                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9206                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9207                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
9208                         netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9209                 }
9210         }
9211
9212         return true;
9213 }
9214
9215 static void tg3_ints_init(struct tg3 *tp)
9216 {
9217         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9218             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
9219                 /* All MSI supporting chips should support tagged
9220                  * status.  Assert that this is the case.
9221                  */
9222                 netdev_warn(tp->dev,
9223                             "MSI without TAGGED_STATUS? Not using MSI\n");
9224                 goto defcfg;
9225         }
9226
9227         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9228                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9229         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9230                  pci_enable_msi(tp->pdev) == 0)
9231                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9232
9233         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9234                 u32 msi_mode = tr32(MSGINT_MODE);
9235                 if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
9236                     tp->irq_cnt > 1)
9237                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9238                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9239         }
9240 defcfg:
9241         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9242                 tp->irq_cnt = 1;
9243                 tp->napi[0].irq_vec = tp->pdev->irq;
9244                 netif_set_real_num_tx_queues(tp->dev, 1);
9245                 netif_set_real_num_rx_queues(tp->dev, 1);
9246         }
9247 }
9248
9249 static void tg3_ints_fini(struct tg3 *tp)
9250 {
9251         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9252                 pci_disable_msix(tp->pdev);
9253         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9254                 pci_disable_msi(tp->pdev);
9255         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
9256         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
9257 }
9258
9259 static int tg3_open(struct net_device *dev)
9260 {
9261         struct tg3 *tp = netdev_priv(dev);
9262         int i, err;
9263
9264         if (tp->fw_needed) {
9265                 err = tg3_request_firmware(tp);
9266                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9267                         if (err)
9268                                 return err;
9269                 } else if (err) {
9270                         netdev_warn(tp->dev, "TSO capability disabled\n");
9271                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9272                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9273                         netdev_notice(tp->dev, "TSO capability restored\n");
9274                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9275                 }
9276         }
9277
9278         netif_carrier_off(tp->dev);
9279
9280         err = tg3_power_up(tp);
9281         if (err)
9282                 return err;
9283
9284         tg3_full_lock(tp, 0);
9285
9286         tg3_disable_ints(tp);
9287         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9288
9289         tg3_full_unlock(tp);
9290
9291         /*
9292          * Setup interrupts first so we know how
9293          * many NAPI resources to allocate
9294          */
9295         tg3_ints_init(tp);
9296
9297         /* The placement of this call is tied
9298          * to the setup and use of Host TX descriptors.
9299          */
9300         err = tg3_alloc_consistent(tp);
9301         if (err)
9302                 goto err_out1;
9303
9304         tg3_napi_init(tp);
9305
9306         tg3_napi_enable(tp);
9307
9308         for (i = 0; i < tp->irq_cnt; i++) {
9309                 struct tg3_napi *tnapi = &tp->napi[i];
9310                 err = tg3_request_irq(tp, i);
9311                 if (err) {
9312                         for (i--; i >= 0; i--)
9313                                 free_irq(tnapi->irq_vec, tnapi);
9314                         break;
9315                 }
9316         }
9317
9318         if (err)
9319                 goto err_out2;
9320
9321         tg3_full_lock(tp, 0);
9322
9323         err = tg3_init_hw(tp, 1);
9324         if (err) {
9325                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9326                 tg3_free_rings(tp);
9327         } else {
9328                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9329                         tp->timer_offset = HZ;
9330                 else
9331                         tp->timer_offset = HZ / 10;
9332
9333                 BUG_ON(tp->timer_offset > HZ);
9334                 tp->timer_counter = tp->timer_multiplier =
9335                         (HZ / tp->timer_offset);
9336                 tp->asf_counter = tp->asf_multiplier =
9337                         ((HZ / tp->timer_offset) * 2);
9338
9339                 init_timer(&tp->timer);
9340                 tp->timer.expires = jiffies + tp->timer_offset;
9341                 tp->timer.data = (unsigned long) tp;
9342                 tp->timer.function = tg3_timer;
9343         }
9344
9345         tg3_full_unlock(tp);
9346
9347         if (err)
9348                 goto err_out3;
9349
9350         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9351                 err = tg3_test_msi(tp);
9352
9353                 if (err) {
9354                         tg3_full_lock(tp, 0);
9355                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9356                         tg3_free_rings(tp);
9357                         tg3_full_unlock(tp);
9358
9359                         goto err_out2;
9360                 }
9361
9362                 if (!(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
9363                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9364                         u32 val = tr32(PCIE_TRANSACTION_CFG);
9365
9366                         tw32(PCIE_TRANSACTION_CFG,
9367                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9368                 }
9369         }
9370
9371         tg3_phy_start(tp);
9372
9373         tg3_full_lock(tp, 0);
9374
9375         add_timer(&tp->timer);
9376         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9377         tg3_enable_ints(tp);
9378
9379         tg3_full_unlock(tp);
9380
9381         netif_tx_start_all_queues(dev);
9382
9383         return 0;
9384
9385 err_out3:
9386         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9387                 struct tg3_napi *tnapi = &tp->napi[i];
9388                 free_irq(tnapi->irq_vec, tnapi);
9389         }
9390
9391 err_out2:
9392         tg3_napi_disable(tp);
9393         tg3_napi_fini(tp);
9394         tg3_free_consistent(tp);
9395
9396 err_out1:
9397         tg3_ints_fini(tp);
9398         return err;
9399 }
9400
9401 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9402                                                  struct rtnl_link_stats64 *);
9403 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9404
9405 static int tg3_close(struct net_device *dev)
9406 {
9407         int i;
9408         struct tg3 *tp = netdev_priv(dev);
9409
9410         tg3_napi_disable(tp);
9411         cancel_work_sync(&tp->reset_task);
9412
9413         netif_tx_stop_all_queues(dev);
9414
9415         del_timer_sync(&tp->timer);
9416
9417         tg3_phy_stop(tp);
9418
9419         tg3_full_lock(tp, 1);
9420
9421         tg3_disable_ints(tp);
9422
9423         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9424         tg3_free_rings(tp);
9425         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9426
9427         tg3_full_unlock(tp);
9428
9429         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9430                 struct tg3_napi *tnapi = &tp->napi[i];
9431                 free_irq(tnapi->irq_vec, tnapi);
9432         }
9433
9434         tg3_ints_fini(tp);
9435
9436         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9437
9438         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9439                sizeof(tp->estats_prev));
9440
9441         tg3_napi_fini(tp);
9442
9443         tg3_free_consistent(tp);
9444
9445         tg3_power_down(tp);
9446
9447         netif_carrier_off(tp->dev);
9448
9449         return 0;
9450 }
9451
9452 static inline u64 get_stat64(tg3_stat64_t *val)
9453 {
9454        return ((u64)val->high << 32) | ((u64)val->low);
9455 }
9456
9457 static u64 calc_crc_errors(struct tg3 *tp)
9458 {
9459         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9460
9461         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9462             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9463              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9464                 u32 val;
9465
9466                 spin_lock_bh(&tp->lock);
9467                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9468                         tg3_writephy(tp, MII_TG3_TEST1,
9469                                      val | MII_TG3_TEST1_CRC_EN);
9470                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9471                 } else
9472                         val = 0;
9473                 spin_unlock_bh(&tp->lock);
9474
9475                 tp->phy_crc_errors += val;
9476
9477                 return tp->phy_crc_errors;
9478         }
9479
9480         return get_stat64(&hw_stats->rx_fcs_errors);
9481 }
9482
9483 #define ESTAT_ADD(member) \
9484         estats->member =        old_estats->member + \
9485                                 get_stat64(&hw_stats->member)
9486
9487 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9488 {
9489         struct tg3_ethtool_stats *estats = &tp->estats;
9490         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9491         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9492
9493         if (!hw_stats)
9494                 return old_estats;
9495
9496         ESTAT_ADD(rx_octets);
9497         ESTAT_ADD(rx_fragments);
9498         ESTAT_ADD(rx_ucast_packets);
9499         ESTAT_ADD(rx_mcast_packets);
9500         ESTAT_ADD(rx_bcast_packets);
9501         ESTAT_ADD(rx_fcs_errors);
9502         ESTAT_ADD(rx_align_errors);
9503         ESTAT_ADD(rx_xon_pause_rcvd);
9504         ESTAT_ADD(rx_xoff_pause_rcvd);
9505         ESTAT_ADD(rx_mac_ctrl_rcvd);
9506         ESTAT_ADD(rx_xoff_entered);
9507         ESTAT_ADD(rx_frame_too_long_errors);
9508         ESTAT_ADD(rx_jabbers);
9509         ESTAT_ADD(rx_undersize_packets);
9510         ESTAT_ADD(rx_in_length_errors);
9511         ESTAT_ADD(rx_out_length_errors);
9512         ESTAT_ADD(rx_64_or_less_octet_packets);
9513         ESTAT_ADD(rx_65_to_127_octet_packets);
9514         ESTAT_ADD(rx_128_to_255_octet_packets);
9515         ESTAT_ADD(rx_256_to_511_octet_packets);
9516         ESTAT_ADD(rx_512_to_1023_octet_packets);
9517         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9518         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9519         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9520         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9521         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9522
9523         ESTAT_ADD(tx_octets);
9524         ESTAT_ADD(tx_collisions);
9525         ESTAT_ADD(tx_xon_sent);
9526         ESTAT_ADD(tx_xoff_sent);
9527         ESTAT_ADD(tx_flow_control);
9528         ESTAT_ADD(tx_mac_errors);
9529         ESTAT_ADD(tx_single_collisions);
9530         ESTAT_ADD(tx_mult_collisions);
9531         ESTAT_ADD(tx_deferred);
9532         ESTAT_ADD(tx_excessive_collisions);
9533         ESTAT_ADD(tx_late_collisions);
9534         ESTAT_ADD(tx_collide_2times);
9535         ESTAT_ADD(tx_collide_3times);
9536         ESTAT_ADD(tx_collide_4times);
9537         ESTAT_ADD(tx_collide_5times);
9538         ESTAT_ADD(tx_collide_6times);
9539         ESTAT_ADD(tx_collide_7times);
9540         ESTAT_ADD(tx_collide_8times);
9541         ESTAT_ADD(tx_collide_9times);
9542         ESTAT_ADD(tx_collide_10times);
9543         ESTAT_ADD(tx_collide_11times);
9544         ESTAT_ADD(tx_collide_12times);
9545         ESTAT_ADD(tx_collide_13times);
9546         ESTAT_ADD(tx_collide_14times);
9547         ESTAT_ADD(tx_collide_15times);
9548         ESTAT_ADD(tx_ucast_packets);
9549         ESTAT_ADD(tx_mcast_packets);
9550         ESTAT_ADD(tx_bcast_packets);
9551         ESTAT_ADD(tx_carrier_sense_errors);
9552         ESTAT_ADD(tx_discards);
9553         ESTAT_ADD(tx_errors);
9554
9555         ESTAT_ADD(dma_writeq_full);
9556         ESTAT_ADD(dma_write_prioq_full);
9557         ESTAT_ADD(rxbds_empty);
9558         ESTAT_ADD(rx_discards);
9559         ESTAT_ADD(rx_errors);
9560         ESTAT_ADD(rx_threshold_hit);
9561
9562         ESTAT_ADD(dma_readq_full);
9563         ESTAT_ADD(dma_read_prioq_full);
9564         ESTAT_ADD(tx_comp_queue_full);
9565
9566         ESTAT_ADD(ring_set_send_prod_index);
9567         ESTAT_ADD(ring_status_update);
9568         ESTAT_ADD(nic_irqs);
9569         ESTAT_ADD(nic_avoided_irqs);
9570         ESTAT_ADD(nic_tx_threshold_hit);
9571
9572         return estats;
9573 }
9574
9575 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9576                                                  struct rtnl_link_stats64 *stats)
9577 {
9578         struct tg3 *tp = netdev_priv(dev);
9579         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9580         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9581
9582         if (!hw_stats)
9583                 return old_stats;
9584
9585         stats->rx_packets = old_stats->rx_packets +
9586                 get_stat64(&hw_stats->rx_ucast_packets) +
9587                 get_stat64(&hw_stats->rx_mcast_packets) +
9588                 get_stat64(&hw_stats->rx_bcast_packets);
9589
9590         stats->tx_packets = old_stats->tx_packets +
9591                 get_stat64(&hw_stats->tx_ucast_packets) +
9592                 get_stat64(&hw_stats->tx_mcast_packets) +
9593                 get_stat64(&hw_stats->tx_bcast_packets);
9594
9595         stats->rx_bytes = old_stats->rx_bytes +
9596                 get_stat64(&hw_stats->rx_octets);
9597         stats->tx_bytes = old_stats->tx_bytes +
9598                 get_stat64(&hw_stats->tx_octets);
9599
9600         stats->rx_errors = old_stats->rx_errors +
9601                 get_stat64(&hw_stats->rx_errors);
9602         stats->tx_errors = old_stats->tx_errors +
9603                 get_stat64(&hw_stats->tx_errors) +
9604                 get_stat64(&hw_stats->tx_mac_errors) +
9605                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9606                 get_stat64(&hw_stats->tx_discards);
9607
9608         stats->multicast = old_stats->multicast +
9609                 get_stat64(&hw_stats->rx_mcast_packets);
9610         stats->collisions = old_stats->collisions +
9611                 get_stat64(&hw_stats->tx_collisions);
9612
9613         stats->rx_length_errors = old_stats->rx_length_errors +
9614                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9615                 get_stat64(&hw_stats->rx_undersize_packets);
9616
9617         stats->rx_over_errors = old_stats->rx_over_errors +
9618                 get_stat64(&hw_stats->rxbds_empty);
9619         stats->rx_frame_errors = old_stats->rx_frame_errors +
9620                 get_stat64(&hw_stats->rx_align_errors);
9621         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9622                 get_stat64(&hw_stats->tx_discards);
9623         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9624                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9625
9626         stats->rx_crc_errors = old_stats->rx_crc_errors +
9627                 calc_crc_errors(tp);
9628
9629         stats->rx_missed_errors = old_stats->rx_missed_errors +
9630                 get_stat64(&hw_stats->rx_discards);
9631
9632         stats->rx_dropped = tp->rx_dropped;
9633
9634         return stats;
9635 }
9636
9637 static inline u32 calc_crc(unsigned char *buf, int len)
9638 {
9639         u32 reg;
9640         u32 tmp;
9641         int j, k;
9642
9643         reg = 0xffffffff;
9644
9645         for (j = 0; j < len; j++) {
9646                 reg ^= buf[j];
9647
9648                 for (k = 0; k < 8; k++) {
9649                         tmp = reg & 0x01;
9650
9651                         reg >>= 1;
9652
9653                         if (tmp)
9654                                 reg ^= 0xedb88320;
9655                 }
9656         }
9657
9658         return ~reg;
9659 }
9660
9661 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9662 {
9663         /* accept or reject all multicast frames */
9664         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9665         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9666         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9667         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9668 }
9669
9670 static void __tg3_set_rx_mode(struct net_device *dev)
9671 {
9672         struct tg3 *tp = netdev_priv(dev);
9673         u32 rx_mode;
9674
9675         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9676                                   RX_MODE_KEEP_VLAN_TAG);
9677
9678 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9679         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9680          * flag clear.
9681          */
9682         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9683                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9684 #endif
9685
9686         if (dev->flags & IFF_PROMISC) {
9687                 /* Promiscuous mode. */
9688                 rx_mode |= RX_MODE_PROMISC;
9689         } else if (dev->flags & IFF_ALLMULTI) {
9690                 /* Accept all multicast. */
9691                 tg3_set_multi(tp, 1);
9692         } else if (netdev_mc_empty(dev)) {
9693                 /* Reject all multicast. */
9694                 tg3_set_multi(tp, 0);
9695         } else {
9696                 /* Accept one or more multicast(s). */
9697                 struct netdev_hw_addr *ha;
9698                 u32 mc_filter[4] = { 0, };
9699                 u32 regidx;
9700                 u32 bit;
9701                 u32 crc;
9702
9703                 netdev_for_each_mc_addr(ha, dev) {
9704                         crc = calc_crc(ha->addr, ETH_ALEN);
9705                         bit = ~crc & 0x7f;
9706                         regidx = (bit & 0x60) >> 5;
9707                         bit &= 0x1f;
9708                         mc_filter[regidx] |= (1 << bit);
9709                 }
9710
9711                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9712                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9713                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9714                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9715         }
9716
9717         if (rx_mode != tp->rx_mode) {
9718                 tp->rx_mode = rx_mode;
9719                 tw32_f(MAC_RX_MODE, rx_mode);
9720                 udelay(10);
9721         }
9722 }
9723
9724 static void tg3_set_rx_mode(struct net_device *dev)
9725 {
9726         struct tg3 *tp = netdev_priv(dev);
9727
9728         if (!netif_running(dev))
9729                 return;
9730
9731         tg3_full_lock(tp, 0);
9732         __tg3_set_rx_mode(dev);
9733         tg3_full_unlock(tp);
9734 }
9735
9736 static int tg3_get_regs_len(struct net_device *dev)
9737 {
9738         return TG3_REG_BLK_SIZE;
9739 }
9740
9741 static void tg3_get_regs(struct net_device *dev,
9742                 struct ethtool_regs *regs, void *_p)
9743 {
9744         struct tg3 *tp = netdev_priv(dev);
9745
9746         regs->version = 0;
9747
9748         memset(_p, 0, TG3_REG_BLK_SIZE);
9749
9750         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9751                 return;
9752
9753         tg3_full_lock(tp, 0);
9754
9755         tg3_dump_legacy_regs(tp, (u32 *)_p);
9756
9757         tg3_full_unlock(tp);
9758 }
9759
9760 static int tg3_get_eeprom_len(struct net_device *dev)
9761 {
9762         struct tg3 *tp = netdev_priv(dev);
9763
9764         return tp->nvram_size;
9765 }
9766
9767 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9768 {
9769         struct tg3 *tp = netdev_priv(dev);
9770         int ret;
9771         u8  *pd;
9772         u32 i, offset, len, b_offset, b_count;
9773         __be32 val;
9774
9775         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9776                 return -EINVAL;
9777
9778         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9779                 return -EAGAIN;
9780
9781         offset = eeprom->offset;
9782         len = eeprom->len;
9783         eeprom->len = 0;
9784
9785         eeprom->magic = TG3_EEPROM_MAGIC;
9786
9787         if (offset & 3) {
9788                 /* adjustments to start on required 4 byte boundary */
9789                 b_offset = offset & 3;
9790                 b_count = 4 - b_offset;
9791                 if (b_count > len) {
9792                         /* i.e. offset=1 len=2 */
9793                         b_count = len;
9794                 }
9795                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9796                 if (ret)
9797                         return ret;
9798                 memcpy(data, ((char *)&val) + b_offset, b_count);
9799                 len -= b_count;
9800                 offset += b_count;
9801                 eeprom->len += b_count;
9802         }
9803
9804         /* read bytes up to the last 4 byte boundary */
9805         pd = &data[eeprom->len];
9806         for (i = 0; i < (len - (len & 3)); i += 4) {
9807                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9808                 if (ret) {
9809                         eeprom->len += i;
9810                         return ret;
9811                 }
9812                 memcpy(pd + i, &val, 4);
9813         }
9814         eeprom->len += i;
9815
9816         if (len & 3) {
9817                 /* read last bytes not ending on 4 byte boundary */
9818                 pd = &data[eeprom->len];
9819                 b_count = len & 3;
9820                 b_offset = offset + len - b_count;
9821                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9822                 if (ret)
9823                         return ret;
9824                 memcpy(pd, &val, b_count);
9825                 eeprom->len += b_count;
9826         }
9827         return 0;
9828 }
9829
9830 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9831
9832 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9833 {
9834         struct tg3 *tp = netdev_priv(dev);
9835         int ret;
9836         u32 offset, len, b_offset, odd_len;
9837         u8 *buf;
9838         __be32 start, end;
9839
9840         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9841                 return -EAGAIN;
9842
9843         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9844             eeprom->magic != TG3_EEPROM_MAGIC)
9845                 return -EINVAL;
9846
9847         offset = eeprom->offset;
9848         len = eeprom->len;
9849
9850         if ((b_offset = (offset & 3))) {
9851                 /* adjustments to start on required 4 byte boundary */
9852                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9853                 if (ret)
9854                         return ret;
9855                 len += b_offset;
9856                 offset &= ~3;
9857                 if (len < 4)
9858                         len = 4;
9859         }
9860
9861         odd_len = 0;
9862         if (len & 3) {
9863                 /* adjustments to end on required 4 byte boundary */
9864                 odd_len = 1;
9865                 len = (len + 3) & ~3;
9866                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9867                 if (ret)
9868                         return ret;
9869         }
9870
9871         buf = data;
9872         if (b_offset || odd_len) {
9873                 buf = kmalloc(len, GFP_KERNEL);
9874                 if (!buf)
9875                         return -ENOMEM;
9876                 if (b_offset)
9877                         memcpy(buf, &start, 4);
9878                 if (odd_len)
9879                         memcpy(buf+len-4, &end, 4);
9880                 memcpy(buf + b_offset, data, eeprom->len);
9881         }
9882
9883         ret = tg3_nvram_write_block(tp, offset, len, buf);
9884
9885         if (buf != data)
9886                 kfree(buf);
9887
9888         return ret;
9889 }
9890
9891 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9892 {
9893         struct tg3 *tp = netdev_priv(dev);
9894
9895         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9896                 struct phy_device *phydev;
9897                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9898                         return -EAGAIN;
9899                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9900                 return phy_ethtool_gset(phydev, cmd);
9901         }
9902
9903         cmd->supported = (SUPPORTED_Autoneg);
9904
9905         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9906                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9907                                    SUPPORTED_1000baseT_Full);
9908
9909         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9910                 cmd->supported |= (SUPPORTED_100baseT_Half |
9911                                   SUPPORTED_100baseT_Full |
9912                                   SUPPORTED_10baseT_Half |
9913                                   SUPPORTED_10baseT_Full |
9914                                   SUPPORTED_TP);
9915                 cmd->port = PORT_TP;
9916         } else {
9917                 cmd->supported |= SUPPORTED_FIBRE;
9918                 cmd->port = PORT_FIBRE;
9919         }
9920
9921         cmd->advertising = tp->link_config.advertising;
9922         if (netif_running(dev)) {
9923                 cmd->speed = tp->link_config.active_speed;
9924                 cmd->duplex = tp->link_config.active_duplex;
9925         } else {
9926                 cmd->speed = SPEED_INVALID;
9927                 cmd->duplex = DUPLEX_INVALID;
9928         }
9929         cmd->phy_address = tp->phy_addr;
9930         cmd->transceiver = XCVR_INTERNAL;
9931         cmd->autoneg = tp->link_config.autoneg;
9932         cmd->maxtxpkt = 0;
9933         cmd->maxrxpkt = 0;
9934         return 0;
9935 }
9936
9937 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9938 {
9939         struct tg3 *tp = netdev_priv(dev);
9940
9941         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9942                 struct phy_device *phydev;
9943                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9944                         return -EAGAIN;
9945                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9946                 return phy_ethtool_sset(phydev, cmd);
9947         }
9948
9949         if (cmd->autoneg != AUTONEG_ENABLE &&
9950             cmd->autoneg != AUTONEG_DISABLE)
9951                 return -EINVAL;
9952
9953         if (cmd->autoneg == AUTONEG_DISABLE &&
9954             cmd->duplex != DUPLEX_FULL &&
9955             cmd->duplex != DUPLEX_HALF)
9956                 return -EINVAL;
9957
9958         if (cmd->autoneg == AUTONEG_ENABLE) {
9959                 u32 mask = ADVERTISED_Autoneg |
9960                            ADVERTISED_Pause |
9961                            ADVERTISED_Asym_Pause;
9962
9963                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9964                         mask |= ADVERTISED_1000baseT_Half |
9965                                 ADVERTISED_1000baseT_Full;
9966
9967                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9968                         mask |= ADVERTISED_100baseT_Half |
9969                                 ADVERTISED_100baseT_Full |
9970                                 ADVERTISED_10baseT_Half |
9971                                 ADVERTISED_10baseT_Full |
9972                                 ADVERTISED_TP;
9973                 else
9974                         mask |= ADVERTISED_FIBRE;
9975
9976                 if (cmd->advertising & ~mask)
9977                         return -EINVAL;
9978
9979                 mask &= (ADVERTISED_1000baseT_Half |
9980                          ADVERTISED_1000baseT_Full |
9981                          ADVERTISED_100baseT_Half |
9982                          ADVERTISED_100baseT_Full |
9983                          ADVERTISED_10baseT_Half |
9984                          ADVERTISED_10baseT_Full);
9985
9986                 cmd->advertising &= mask;
9987         } else {
9988                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9989                         if (cmd->speed != SPEED_1000)
9990                                 return -EINVAL;
9991
9992                         if (cmd->duplex != DUPLEX_FULL)
9993                                 return -EINVAL;
9994                 } else {
9995                         if (cmd->speed != SPEED_100 &&
9996                             cmd->speed != SPEED_10)
9997                                 return -EINVAL;
9998                 }
9999         }
10000
10001         tg3_full_lock(tp, 0);
10002
10003         tp->link_config.autoneg = cmd->autoneg;
10004         if (cmd->autoneg == AUTONEG_ENABLE) {
10005                 tp->link_config.advertising = (cmd->advertising |
10006                                               ADVERTISED_Autoneg);
10007                 tp->link_config.speed = SPEED_INVALID;
10008                 tp->link_config.duplex = DUPLEX_INVALID;
10009         } else {
10010                 tp->link_config.advertising = 0;
10011                 tp->link_config.speed = cmd->speed;
10012                 tp->link_config.duplex = cmd->duplex;
10013         }
10014
10015         tp->link_config.orig_speed = tp->link_config.speed;
10016         tp->link_config.orig_duplex = tp->link_config.duplex;
10017         tp->link_config.orig_autoneg = tp->link_config.autoneg;
10018
10019         if (netif_running(dev))
10020                 tg3_setup_phy(tp, 1);
10021
10022         tg3_full_unlock(tp);
10023
10024         return 0;
10025 }
10026
10027 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10028 {
10029         struct tg3 *tp = netdev_priv(dev);
10030
10031         strcpy(info->driver, DRV_MODULE_NAME);
10032         strcpy(info->version, DRV_MODULE_VERSION);
10033         strcpy(info->fw_version, tp->fw_ver);
10034         strcpy(info->bus_info, pci_name(tp->pdev));
10035 }
10036
10037 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10038 {
10039         struct tg3 *tp = netdev_priv(dev);
10040
10041         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
10042             device_can_wakeup(&tp->pdev->dev))
10043                 wol->supported = WAKE_MAGIC;
10044         else
10045                 wol->supported = 0;
10046         wol->wolopts = 0;
10047         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
10048             device_can_wakeup(&tp->pdev->dev))
10049                 wol->wolopts = WAKE_MAGIC;
10050         memset(&wol->sopass, 0, sizeof(wol->sopass));
10051 }
10052
10053 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10054 {
10055         struct tg3 *tp = netdev_priv(dev);
10056         struct device *dp = &tp->pdev->dev;
10057
10058         if (wol->wolopts & ~WAKE_MAGIC)
10059                 return -EINVAL;
10060         if ((wol->wolopts & WAKE_MAGIC) &&
10061             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
10062                 return -EINVAL;
10063
10064         device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10065
10066         spin_lock_bh(&tp->lock);
10067         if (device_may_wakeup(dp))
10068                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
10069         else
10070                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10071         spin_unlock_bh(&tp->lock);
10072
10073
10074         return 0;
10075 }
10076
10077 static u32 tg3_get_msglevel(struct net_device *dev)
10078 {
10079         struct tg3 *tp = netdev_priv(dev);
10080         return tp->msg_enable;
10081 }
10082
10083 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10084 {
10085         struct tg3 *tp = netdev_priv(dev);
10086         tp->msg_enable = value;
10087 }
10088
10089 static int tg3_nway_reset(struct net_device *dev)
10090 {
10091         struct tg3 *tp = netdev_priv(dev);
10092         int r;
10093
10094         if (!netif_running(dev))
10095                 return -EAGAIN;
10096
10097         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10098                 return -EINVAL;
10099
10100         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10101                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10102                         return -EAGAIN;
10103                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10104         } else {
10105                 u32 bmcr;
10106
10107                 spin_lock_bh(&tp->lock);
10108                 r = -EINVAL;
10109                 tg3_readphy(tp, MII_BMCR, &bmcr);
10110                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10111                     ((bmcr & BMCR_ANENABLE) ||
10112                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10113                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10114                                                    BMCR_ANENABLE);
10115                         r = 0;
10116                 }
10117                 spin_unlock_bh(&tp->lock);
10118         }
10119
10120         return r;
10121 }
10122
10123 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10124 {
10125         struct tg3 *tp = netdev_priv(dev);
10126
10127         ering->rx_max_pending = tp->rx_std_ring_mask;
10128         ering->rx_mini_max_pending = 0;
10129         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10130                 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10131         else
10132                 ering->rx_jumbo_max_pending = 0;
10133
10134         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10135
10136         ering->rx_pending = tp->rx_pending;
10137         ering->rx_mini_pending = 0;
10138         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10139                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10140         else
10141                 ering->rx_jumbo_pending = 0;
10142
10143         ering->tx_pending = tp->napi[0].tx_pending;
10144 }
10145
10146 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10147 {
10148         struct tg3 *tp = netdev_priv(dev);
10149         int i, irq_sync = 0, err = 0;
10150
10151         if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10152             (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10153             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10154             (ering->tx_pending <= MAX_SKB_FRAGS) ||
10155             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10156              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10157                 return -EINVAL;
10158
10159         if (netif_running(dev)) {
10160                 tg3_phy_stop(tp);
10161                 tg3_netif_stop(tp);
10162                 irq_sync = 1;
10163         }
10164
10165         tg3_full_lock(tp, irq_sync);
10166
10167         tp->rx_pending = ering->rx_pending;
10168
10169         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10170             tp->rx_pending > 63)
10171                 tp->rx_pending = 63;
10172         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10173
10174         for (i = 0; i < tp->irq_max; i++)
10175                 tp->napi[i].tx_pending = ering->tx_pending;
10176
10177         if (netif_running(dev)) {
10178                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10179                 err = tg3_restart_hw(tp, 1);
10180                 if (!err)
10181                         tg3_netif_start(tp);
10182         }
10183
10184         tg3_full_unlock(tp);
10185
10186         if (irq_sync && !err)
10187                 tg3_phy_start(tp);
10188
10189         return err;
10190 }
10191
10192 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10193 {
10194         struct tg3 *tp = netdev_priv(dev);
10195
10196         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10197
10198         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10199                 epause->rx_pause = 1;
10200         else
10201                 epause->rx_pause = 0;
10202
10203         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10204                 epause->tx_pause = 1;
10205         else
10206                 epause->tx_pause = 0;
10207 }
10208
10209 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10210 {
10211         struct tg3 *tp = netdev_priv(dev);
10212         int err = 0;
10213
10214         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10215                 u32 newadv;
10216                 struct phy_device *phydev;
10217
10218                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10219
10220                 if (!(phydev->supported & SUPPORTED_Pause) ||
10221                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10222                      (epause->rx_pause != epause->tx_pause)))
10223                         return -EINVAL;
10224
10225                 tp->link_config.flowctrl = 0;
10226                 if (epause->rx_pause) {
10227                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10228
10229                         if (epause->tx_pause) {
10230                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10231                                 newadv = ADVERTISED_Pause;
10232                         } else
10233                                 newadv = ADVERTISED_Pause |
10234                                          ADVERTISED_Asym_Pause;
10235                 } else if (epause->tx_pause) {
10236                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10237                         newadv = ADVERTISED_Asym_Pause;
10238                 } else
10239                         newadv = 0;
10240
10241                 if (epause->autoneg)
10242                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10243                 else
10244                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10245
10246                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10247                         u32 oldadv = phydev->advertising &
10248                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10249                         if (oldadv != newadv) {
10250                                 phydev->advertising &=
10251                                         ~(ADVERTISED_Pause |
10252                                           ADVERTISED_Asym_Pause);
10253                                 phydev->advertising |= newadv;
10254                                 if (phydev->autoneg) {
10255                                         /*
10256                                          * Always renegotiate the link to
10257                                          * inform our link partner of our
10258                                          * flow control settings, even if the
10259                                          * flow control is forced.  Let
10260                                          * tg3_adjust_link() do the final
10261                                          * flow control setup.
10262                                          */
10263                                         return phy_start_aneg(phydev);
10264                                 }
10265                         }
10266
10267                         if (!epause->autoneg)
10268                                 tg3_setup_flow_control(tp, 0, 0);
10269                 } else {
10270                         tp->link_config.orig_advertising &=
10271                                         ~(ADVERTISED_Pause |
10272                                           ADVERTISED_Asym_Pause);
10273                         tp->link_config.orig_advertising |= newadv;
10274                 }
10275         } else {
10276                 int irq_sync = 0;
10277
10278                 if (netif_running(dev)) {
10279                         tg3_netif_stop(tp);
10280                         irq_sync = 1;
10281                 }
10282
10283                 tg3_full_lock(tp, irq_sync);
10284
10285                 if (epause->autoneg)
10286                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10287                 else
10288                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10289                 if (epause->rx_pause)
10290                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10291                 else
10292                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10293                 if (epause->tx_pause)
10294                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10295                 else
10296                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10297
10298                 if (netif_running(dev)) {
10299                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10300                         err = tg3_restart_hw(tp, 1);
10301                         if (!err)
10302                                 tg3_netif_start(tp);
10303                 }
10304
10305                 tg3_full_unlock(tp);
10306         }
10307
10308         return err;
10309 }
10310
10311 static int tg3_get_sset_count(struct net_device *dev, int sset)
10312 {
10313         switch (sset) {
10314         case ETH_SS_TEST:
10315                 return TG3_NUM_TEST;
10316         case ETH_SS_STATS:
10317                 return TG3_NUM_STATS;
10318         default:
10319                 return -EOPNOTSUPP;
10320         }
10321 }
10322
10323 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10324 {
10325         switch (stringset) {
10326         case ETH_SS_STATS:
10327                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10328                 break;
10329         case ETH_SS_TEST:
10330                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10331                 break;
10332         default:
10333                 WARN_ON(1);     /* we need a WARN() */
10334                 break;
10335         }
10336 }
10337
10338 static int tg3_set_phys_id(struct net_device *dev,
10339                             enum ethtool_phys_id_state state)
10340 {
10341         struct tg3 *tp = netdev_priv(dev);
10342
10343         if (!netif_running(tp->dev))
10344                 return -EAGAIN;
10345
10346         switch (state) {
10347         case ETHTOOL_ID_ACTIVE:
10348                 return -EINVAL;
10349
10350         case ETHTOOL_ID_ON:
10351                 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10352                      LED_CTRL_1000MBPS_ON |
10353                      LED_CTRL_100MBPS_ON |
10354                      LED_CTRL_10MBPS_ON |
10355                      LED_CTRL_TRAFFIC_OVERRIDE |
10356                      LED_CTRL_TRAFFIC_BLINK |
10357                      LED_CTRL_TRAFFIC_LED);
10358                 break;
10359
10360         case ETHTOOL_ID_OFF:
10361                 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10362                      LED_CTRL_TRAFFIC_OVERRIDE);
10363                 break;
10364
10365         case ETHTOOL_ID_INACTIVE:
10366                 tw32(MAC_LED_CTRL, tp->led_ctrl);
10367                 break;
10368         }
10369
10370         return 0;
10371 }
10372
10373 static void tg3_get_ethtool_stats(struct net_device *dev,
10374                                    struct ethtool_stats *estats, u64 *tmp_stats)
10375 {
10376         struct tg3 *tp = netdev_priv(dev);
10377         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10378 }
10379
10380 #define NVRAM_TEST_SIZE 0x100
10381 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10382 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10383 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10384 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10385 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10386
10387 static int tg3_test_nvram(struct tg3 *tp)
10388 {
10389         u32 csum, magic;
10390         __be32 *buf;
10391         int i, j, k, err = 0, size;
10392
10393         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10394                 return 0;
10395
10396         if (tg3_nvram_read(tp, 0, &magic) != 0)
10397                 return -EIO;
10398
10399         if (magic == TG3_EEPROM_MAGIC)
10400                 size = NVRAM_TEST_SIZE;
10401         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10402                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10403                     TG3_EEPROM_SB_FORMAT_1) {
10404                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10405                         case TG3_EEPROM_SB_REVISION_0:
10406                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10407                                 break;
10408                         case TG3_EEPROM_SB_REVISION_2:
10409                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10410                                 break;
10411                         case TG3_EEPROM_SB_REVISION_3:
10412                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10413                                 break;
10414                         default:
10415                                 return 0;
10416                         }
10417                 } else
10418                         return 0;
10419         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10420                 size = NVRAM_SELFBOOT_HW_SIZE;
10421         else
10422                 return -EIO;
10423
10424         buf = kmalloc(size, GFP_KERNEL);
10425         if (buf == NULL)
10426                 return -ENOMEM;
10427
10428         err = -EIO;
10429         for (i = 0, j = 0; i < size; i += 4, j++) {
10430                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10431                 if (err)
10432                         break;
10433         }
10434         if (i < size)
10435                 goto out;
10436
10437         /* Selfboot format */
10438         magic = be32_to_cpu(buf[0]);
10439         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10440             TG3_EEPROM_MAGIC_FW) {
10441                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10442
10443                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10444                     TG3_EEPROM_SB_REVISION_2) {
10445                         /* For rev 2, the csum doesn't include the MBA. */
10446                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10447                                 csum8 += buf8[i];
10448                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10449                                 csum8 += buf8[i];
10450                 } else {
10451                         for (i = 0; i < size; i++)
10452                                 csum8 += buf8[i];
10453                 }
10454
10455                 if (csum8 == 0) {
10456                         err = 0;
10457                         goto out;
10458                 }
10459
10460                 err = -EIO;
10461                 goto out;
10462         }
10463
10464         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10465             TG3_EEPROM_MAGIC_HW) {
10466                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10467                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10468                 u8 *buf8 = (u8 *) buf;
10469
10470                 /* Separate the parity bits and the data bytes.  */
10471                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10472                         if ((i == 0) || (i == 8)) {
10473                                 int l;
10474                                 u8 msk;
10475
10476                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10477                                         parity[k++] = buf8[i] & msk;
10478                                 i++;
10479                         } else if (i == 16) {
10480                                 int l;
10481                                 u8 msk;
10482
10483                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10484                                         parity[k++] = buf8[i] & msk;
10485                                 i++;
10486
10487                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10488                                         parity[k++] = buf8[i] & msk;
10489                                 i++;
10490                         }
10491                         data[j++] = buf8[i];
10492                 }
10493
10494                 err = -EIO;
10495                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10496                         u8 hw8 = hweight8(data[i]);
10497
10498                         if ((hw8 & 0x1) && parity[i])
10499                                 goto out;
10500                         else if (!(hw8 & 0x1) && !parity[i])
10501                                 goto out;
10502                 }
10503                 err = 0;
10504                 goto out;
10505         }
10506
10507         err = -EIO;
10508
10509         /* Bootstrap checksum at offset 0x10 */
10510         csum = calc_crc((unsigned char *) buf, 0x10);
10511         if (csum != le32_to_cpu(buf[0x10/4]))
10512                 goto out;
10513
10514         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10515         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10516         if (csum != le32_to_cpu(buf[0xfc/4]))
10517                 goto out;
10518
10519         for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
10520                 /* The data is in little-endian format in NVRAM.
10521                  * Use the big-endian read routines to preserve
10522                  * the byte order as it exists in NVRAM.
10523                  */
10524                 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &buf[i/4]))
10525                         goto out;
10526         }
10527
10528         i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN,
10529                              PCI_VPD_LRDT_RO_DATA);
10530         if (i > 0) {
10531                 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
10532                 if (j < 0)
10533                         goto out;
10534
10535                 if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN)
10536                         goto out;
10537
10538                 i += PCI_VPD_LRDT_TAG_SIZE;
10539                 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
10540                                               PCI_VPD_RO_KEYWORD_CHKSUM);
10541                 if (j > 0) {
10542                         u8 csum8 = 0;
10543
10544                         j += PCI_VPD_INFO_FLD_HDR_SIZE;
10545
10546                         for (i = 0; i <= j; i++)
10547                                 csum8 += ((u8 *)buf)[i];
10548
10549                         if (csum8)
10550                                 goto out;
10551                 }
10552         }
10553
10554         err = 0;
10555
10556 out:
10557         kfree(buf);
10558         return err;
10559 }
10560
10561 #define TG3_SERDES_TIMEOUT_SEC  2
10562 #define TG3_COPPER_TIMEOUT_SEC  6
10563
10564 static int tg3_test_link(struct tg3 *tp)
10565 {
10566         int i, max;
10567
10568         if (!netif_running(tp->dev))
10569                 return -ENODEV;
10570
10571         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10572                 max = TG3_SERDES_TIMEOUT_SEC;
10573         else
10574                 max = TG3_COPPER_TIMEOUT_SEC;
10575
10576         for (i = 0; i < max; i++) {
10577                 if (netif_carrier_ok(tp->dev))
10578                         return 0;
10579
10580                 if (msleep_interruptible(1000))
10581                         break;
10582         }
10583
10584         return -EIO;
10585 }
10586
10587 /* Only test the commonly used registers */
10588 static int tg3_test_registers(struct tg3 *tp)
10589 {
10590         int i, is_5705, is_5750;
10591         u32 offset, read_mask, write_mask, val, save_val, read_val;
10592         static struct {
10593                 u16 offset;
10594                 u16 flags;
10595 #define TG3_FL_5705     0x1
10596 #define TG3_FL_NOT_5705 0x2
10597 #define TG3_FL_NOT_5788 0x4
10598 #define TG3_FL_NOT_5750 0x8
10599                 u32 read_mask;
10600                 u32 write_mask;
10601         } reg_tbl[] = {
10602                 /* MAC Control Registers */
10603                 { MAC_MODE, TG3_FL_NOT_5705,
10604                         0x00000000, 0x00ef6f8c },
10605                 { MAC_MODE, TG3_FL_5705,
10606                         0x00000000, 0x01ef6b8c },
10607                 { MAC_STATUS, TG3_FL_NOT_5705,
10608                         0x03800107, 0x00000000 },
10609                 { MAC_STATUS, TG3_FL_5705,
10610                         0x03800100, 0x00000000 },
10611                 { MAC_ADDR_0_HIGH, 0x0000,
10612                         0x00000000, 0x0000ffff },
10613                 { MAC_ADDR_0_LOW, 0x0000,
10614                         0x00000000, 0xffffffff },
10615                 { MAC_RX_MTU_SIZE, 0x0000,
10616                         0x00000000, 0x0000ffff },
10617                 { MAC_TX_MODE, 0x0000,
10618                         0x00000000, 0x00000070 },
10619                 { MAC_TX_LENGTHS, 0x0000,
10620                         0x00000000, 0x00003fff },
10621                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10622                         0x00000000, 0x000007fc },
10623                 { MAC_RX_MODE, TG3_FL_5705,
10624                         0x00000000, 0x000007dc },
10625                 { MAC_HASH_REG_0, 0x0000,
10626                         0x00000000, 0xffffffff },
10627                 { MAC_HASH_REG_1, 0x0000,
10628                         0x00000000, 0xffffffff },
10629                 { MAC_HASH_REG_2, 0x0000,
10630                         0x00000000, 0xffffffff },
10631                 { MAC_HASH_REG_3, 0x0000,
10632                         0x00000000, 0xffffffff },
10633
10634                 /* Receive Data and Receive BD Initiator Control Registers. */
10635                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10636                         0x00000000, 0xffffffff },
10637                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10638                         0x00000000, 0xffffffff },
10639                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10640                         0x00000000, 0x00000003 },
10641                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10642                         0x00000000, 0xffffffff },
10643                 { RCVDBDI_STD_BD+0, 0x0000,
10644                         0x00000000, 0xffffffff },
10645                 { RCVDBDI_STD_BD+4, 0x0000,
10646                         0x00000000, 0xffffffff },
10647                 { RCVDBDI_STD_BD+8, 0x0000,
10648                         0x00000000, 0xffff0002 },
10649                 { RCVDBDI_STD_BD+0xc, 0x0000,
10650                         0x00000000, 0xffffffff },
10651
10652                 /* Receive BD Initiator Control Registers. */
10653                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10654                         0x00000000, 0xffffffff },
10655                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10656                         0x00000000, 0x000003ff },
10657                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10658                         0x00000000, 0xffffffff },
10659
10660                 /* Host Coalescing Control Registers. */
10661                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10662                         0x00000000, 0x00000004 },
10663                 { HOSTCC_MODE, TG3_FL_5705,
10664                         0x00000000, 0x000000f6 },
10665                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10666                         0x00000000, 0xffffffff },
10667                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10668                         0x00000000, 0x000003ff },
10669                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10670                         0x00000000, 0xffffffff },
10671                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10672                         0x00000000, 0x000003ff },
10673                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10674                         0x00000000, 0xffffffff },
10675                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10676                         0x00000000, 0x000000ff },
10677                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10678                         0x00000000, 0xffffffff },
10679                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10680                         0x00000000, 0x000000ff },
10681                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10682                         0x00000000, 0xffffffff },
10683                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10684                         0x00000000, 0xffffffff },
10685                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10686                         0x00000000, 0xffffffff },
10687                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10688                         0x00000000, 0x000000ff },
10689                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10690                         0x00000000, 0xffffffff },
10691                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10692                         0x00000000, 0x000000ff },
10693                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10694                         0x00000000, 0xffffffff },
10695                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10696                         0x00000000, 0xffffffff },
10697                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10698                         0x00000000, 0xffffffff },
10699                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10700                         0x00000000, 0xffffffff },
10701                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10702                         0x00000000, 0xffffffff },
10703                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10704                         0xffffffff, 0x00000000 },
10705                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10706                         0xffffffff, 0x00000000 },
10707
10708                 /* Buffer Manager Control Registers. */
10709                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10710                         0x00000000, 0x007fff80 },
10711                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10712                         0x00000000, 0x007fffff },
10713                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10714                         0x00000000, 0x0000003f },
10715                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10716                         0x00000000, 0x000001ff },
10717                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10718                         0x00000000, 0x000001ff },
10719                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10720                         0xffffffff, 0x00000000 },
10721                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10722                         0xffffffff, 0x00000000 },
10723
10724                 /* Mailbox Registers */
10725                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10726                         0x00000000, 0x000001ff },
10727                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10728                         0x00000000, 0x000001ff },
10729                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10730                         0x00000000, 0x000007ff },
10731                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10732                         0x00000000, 0x000001ff },
10733
10734                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10735         };
10736
10737         is_5705 = is_5750 = 0;
10738         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10739                 is_5705 = 1;
10740                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10741                         is_5750 = 1;
10742         }
10743
10744         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10745                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10746                         continue;
10747
10748                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10749                         continue;
10750
10751                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10752                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10753                         continue;
10754
10755                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10756                         continue;
10757
10758                 offset = (u32) reg_tbl[i].offset;
10759                 read_mask = reg_tbl[i].read_mask;
10760                 write_mask = reg_tbl[i].write_mask;
10761
10762                 /* Save the original register content */
10763                 save_val = tr32(offset);
10764
10765                 /* Determine the read-only value. */
10766                 read_val = save_val & read_mask;
10767
10768                 /* Write zero to the register, then make sure the read-only bits
10769                  * are not changed and the read/write bits are all zeros.
10770                  */
10771                 tw32(offset, 0);
10772
10773                 val = tr32(offset);
10774
10775                 /* Test the read-only and read/write bits. */
10776                 if (((val & read_mask) != read_val) || (val & write_mask))
10777                         goto out;
10778
10779                 /* Write ones to all the bits defined by RdMask and WrMask, then
10780                  * make sure the read-only bits are not changed and the
10781                  * read/write bits are all ones.
10782                  */
10783                 tw32(offset, read_mask | write_mask);
10784
10785                 val = tr32(offset);
10786
10787                 /* Test the read-only bits. */
10788                 if ((val & read_mask) != read_val)
10789                         goto out;
10790
10791                 /* Test the read/write bits. */
10792                 if ((val & write_mask) != write_mask)
10793                         goto out;
10794
10795                 tw32(offset, save_val);
10796         }
10797
10798         return 0;
10799
10800 out:
10801         if (netif_msg_hw(tp))
10802                 netdev_err(tp->dev,
10803                            "Register test failed at offset %x\n", offset);
10804         tw32(offset, save_val);
10805         return -EIO;
10806 }
10807
10808 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10809 {
10810         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10811         int i;
10812         u32 j;
10813
10814         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10815                 for (j = 0; j < len; j += 4) {
10816                         u32 val;
10817
10818                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10819                         tg3_read_mem(tp, offset + j, &val);
10820                         if (val != test_pattern[i])
10821                                 return -EIO;
10822                 }
10823         }
10824         return 0;
10825 }
10826
10827 static int tg3_test_memory(struct tg3 *tp)
10828 {
10829         static struct mem_entry {
10830                 u32 offset;
10831                 u32 len;
10832         } mem_tbl_570x[] = {
10833                 { 0x00000000, 0x00b50},
10834                 { 0x00002000, 0x1c000},
10835                 { 0xffffffff, 0x00000}
10836         }, mem_tbl_5705[] = {
10837                 { 0x00000100, 0x0000c},
10838                 { 0x00000200, 0x00008},
10839                 { 0x00004000, 0x00800},
10840                 { 0x00006000, 0x01000},
10841                 { 0x00008000, 0x02000},
10842                 { 0x00010000, 0x0e000},
10843                 { 0xffffffff, 0x00000}
10844         }, mem_tbl_5755[] = {
10845                 { 0x00000200, 0x00008},
10846                 { 0x00004000, 0x00800},
10847                 { 0x00006000, 0x00800},
10848                 { 0x00008000, 0x02000},
10849                 { 0x00010000, 0x0c000},
10850                 { 0xffffffff, 0x00000}
10851         }, mem_tbl_5906[] = {
10852                 { 0x00000200, 0x00008},
10853                 { 0x00004000, 0x00400},
10854                 { 0x00006000, 0x00400},
10855                 { 0x00008000, 0x01000},
10856                 { 0x00010000, 0x01000},
10857                 { 0xffffffff, 0x00000}
10858         }, mem_tbl_5717[] = {
10859                 { 0x00000200, 0x00008},
10860                 { 0x00010000, 0x0a000},
10861                 { 0x00020000, 0x13c00},
10862                 { 0xffffffff, 0x00000}
10863         }, mem_tbl_57765[] = {
10864                 { 0x00000200, 0x00008},
10865                 { 0x00004000, 0x00800},
10866                 { 0x00006000, 0x09800},
10867                 { 0x00010000, 0x0a000},
10868                 { 0xffffffff, 0x00000}
10869         };
10870         struct mem_entry *mem_tbl;
10871         int err = 0;
10872         int i;
10873
10874         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
10875                 mem_tbl = mem_tbl_5717;
10876         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10877                 mem_tbl = mem_tbl_57765;
10878         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10879                 mem_tbl = mem_tbl_5755;
10880         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10881                 mem_tbl = mem_tbl_5906;
10882         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10883                 mem_tbl = mem_tbl_5705;
10884         else
10885                 mem_tbl = mem_tbl_570x;
10886
10887         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10888                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10889                 if (err)
10890                         break;
10891         }
10892
10893         return err;
10894 }
10895
10896 #define TG3_MAC_LOOPBACK        0
10897 #define TG3_PHY_LOOPBACK        1
10898
10899 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10900 {
10901         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10902         u32 desc_idx, coal_now;
10903         struct sk_buff *skb, *rx_skb;
10904         u8 *tx_data;
10905         dma_addr_t map;
10906         int num_pkts, tx_len, rx_len, i, err;
10907         struct tg3_rx_buffer_desc *desc;
10908         struct tg3_napi *tnapi, *rnapi;
10909         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10910
10911         tnapi = &tp->napi[0];
10912         rnapi = &tp->napi[0];
10913         if (tp->irq_cnt > 1) {
10914                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10915                         rnapi = &tp->napi[1];
10916                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10917                         tnapi = &tp->napi[1];
10918         }
10919         coal_now = tnapi->coal_now | rnapi->coal_now;
10920
10921         if (loopback_mode == TG3_MAC_LOOPBACK) {
10922                 /* HW errata - mac loopback fails in some cases on 5780.
10923                  * Normal traffic and PHY loopback are not affected by
10924                  * errata.  Also, the MAC loopback test is deprecated for
10925                  * all newer ASIC revisions.
10926                  */
10927                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10928                     (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
10929                         return 0;
10930
10931                 mac_mode = tp->mac_mode &
10932                            ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
10933                 mac_mode |= MAC_MODE_PORT_INT_LPBACK;
10934                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10935                         mac_mode |= MAC_MODE_LINK_POLARITY;
10936                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10937                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10938                 else
10939                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10940                 tw32(MAC_MODE, mac_mode);
10941         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10942                 u32 val;
10943
10944                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10945                         tg3_phy_fet_toggle_apd(tp, false);
10946                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10947                 } else
10948                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10949
10950                 tg3_phy_toggle_automdix(tp, 0);
10951
10952                 tg3_writephy(tp, MII_BMCR, val);
10953                 udelay(40);
10954
10955                 mac_mode = tp->mac_mode &
10956                            ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
10957                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10958                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10959                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10960                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10961                         /* The write needs to be flushed for the AC131 */
10962                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10963                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10964                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10965                 } else
10966                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10967
10968                 /* reset to prevent losing 1st rx packet intermittently */
10969                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10970                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10971                         udelay(10);
10972                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10973                 }
10974                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10975                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10976                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10977                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10978                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10979                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10980                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10981                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10982                 }
10983                 tw32(MAC_MODE, mac_mode);
10984
10985                 /* Wait for link */
10986                 for (i = 0; i < 100; i++) {
10987                         if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
10988                                 break;
10989                         mdelay(1);
10990                 }
10991         } else {
10992                 return -EINVAL;
10993         }
10994
10995         err = -EIO;
10996
10997         tx_len = 1514;
10998         skb = netdev_alloc_skb(tp->dev, tx_len);
10999         if (!skb)
11000                 return -ENOMEM;
11001
11002         tx_data = skb_put(skb, tx_len);
11003         memcpy(tx_data, tp->dev->dev_addr, 6);
11004         memset(tx_data + 6, 0x0, 8);
11005
11006         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
11007
11008         for (i = 14; i < tx_len; i++)
11009                 tx_data[i] = (u8) (i & 0xff);
11010
11011         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11012         if (pci_dma_mapping_error(tp->pdev, map)) {
11013                 dev_kfree_skb(skb);
11014                 return -EIO;
11015         }
11016
11017         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11018                rnapi->coal_now);
11019
11020         udelay(10);
11021
11022         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11023
11024         num_pkts = 0;
11025
11026         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
11027
11028         tnapi->tx_prod++;
11029         num_pkts++;
11030
11031         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11032         tr32_mailbox(tnapi->prodmbox);
11033
11034         udelay(10);
11035
11036         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
11037         for (i = 0; i < 35; i++) {
11038                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11039                        coal_now);
11040
11041                 udelay(10);
11042
11043                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11044                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11045                 if ((tx_idx == tnapi->tx_prod) &&
11046                     (rx_idx == (rx_start_idx + num_pkts)))
11047                         break;
11048         }
11049
11050         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
11051         dev_kfree_skb(skb);
11052
11053         if (tx_idx != tnapi->tx_prod)
11054                 goto out;
11055
11056         if (rx_idx != rx_start_idx + num_pkts)
11057                 goto out;
11058
11059         desc = &rnapi->rx_rcb[rx_start_idx];
11060         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11061         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11062         if (opaque_key != RXD_OPAQUE_RING_STD)
11063                 goto out;
11064
11065         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11066             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11067                 goto out;
11068
11069         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
11070         if (rx_len != tx_len)
11071                 goto out;
11072
11073         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11074
11075         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
11076         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
11077
11078         for (i = 14; i < tx_len; i++) {
11079                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
11080                         goto out;
11081         }
11082         err = 0;
11083
11084         /* tg3_free_rings will unmap and free the rx_skb */
11085 out:
11086         return err;
11087 }
11088
11089 #define TG3_MAC_LOOPBACK_FAILED         1
11090 #define TG3_PHY_LOOPBACK_FAILED         2
11091 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
11092                                          TG3_PHY_LOOPBACK_FAILED)
11093
11094 static int tg3_test_loopback(struct tg3 *tp)
11095 {
11096         int err = 0;
11097         u32 eee_cap, cpmuctrl = 0;
11098
11099         if (!netif_running(tp->dev))
11100                 return TG3_LOOPBACK_FAILED;
11101
11102         eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11103         tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11104
11105         err = tg3_reset_hw(tp, 1);
11106         if (err) {
11107                 err = TG3_LOOPBACK_FAILED;
11108                 goto done;
11109         }
11110
11111         /* Turn off gphy autopowerdown. */
11112         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11113                 tg3_phy_toggle_apd(tp, false);
11114
11115         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11116                 int i;
11117                 u32 status;
11118
11119                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11120
11121                 /* Wait for up to 40 microseconds to acquire lock. */
11122                 for (i = 0; i < 4; i++) {
11123                         status = tr32(TG3_CPMU_MUTEX_GNT);
11124                         if (status == CPMU_MUTEX_GNT_DRIVER)
11125                                 break;
11126                         udelay(10);
11127                 }
11128
11129                 if (status != CPMU_MUTEX_GNT_DRIVER) {
11130                         err = TG3_LOOPBACK_FAILED;
11131                         goto done;
11132                 }
11133
11134                 /* Turn off link-based power management. */
11135                 cpmuctrl = tr32(TG3_CPMU_CTRL);
11136                 tw32(TG3_CPMU_CTRL,
11137                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11138                                   CPMU_CTRL_LINK_AWARE_MODE));
11139         }
11140
11141         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11142                 err |= TG3_MAC_LOOPBACK_FAILED;
11143
11144         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11145                 tw32(TG3_CPMU_CTRL, cpmuctrl);
11146
11147                 /* Release the mutex */
11148                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11149         }
11150
11151         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11152             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11153                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11154                         err |= TG3_PHY_LOOPBACK_FAILED;
11155         }
11156
11157         /* Re-enable gphy autopowerdown. */
11158         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11159                 tg3_phy_toggle_apd(tp, true);
11160
11161 done:
11162         tp->phy_flags |= eee_cap;
11163
11164         return err;
11165 }
11166
11167 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11168                           u64 *data)
11169 {
11170         struct tg3 *tp = netdev_priv(dev);
11171
11172         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11173                 tg3_power_up(tp);
11174
11175         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11176
11177         if (tg3_test_nvram(tp) != 0) {
11178                 etest->flags |= ETH_TEST_FL_FAILED;
11179                 data[0] = 1;
11180         }
11181         if (tg3_test_link(tp) != 0) {
11182                 etest->flags |= ETH_TEST_FL_FAILED;
11183                 data[1] = 1;
11184         }
11185         if (etest->flags & ETH_TEST_FL_OFFLINE) {
11186                 int err, err2 = 0, irq_sync = 0;
11187
11188                 if (netif_running(dev)) {
11189                         tg3_phy_stop(tp);
11190                         tg3_netif_stop(tp);
11191                         irq_sync = 1;
11192                 }
11193
11194                 tg3_full_lock(tp, irq_sync);
11195
11196                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11197                 err = tg3_nvram_lock(tp);
11198                 tg3_halt_cpu(tp, RX_CPU_BASE);
11199                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11200                         tg3_halt_cpu(tp, TX_CPU_BASE);
11201                 if (!err)
11202                         tg3_nvram_unlock(tp);
11203
11204                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11205                         tg3_phy_reset(tp);
11206
11207                 if (tg3_test_registers(tp) != 0) {
11208                         etest->flags |= ETH_TEST_FL_FAILED;
11209                         data[2] = 1;
11210                 }
11211                 if (tg3_test_memory(tp) != 0) {
11212                         etest->flags |= ETH_TEST_FL_FAILED;
11213                         data[3] = 1;
11214                 }
11215                 if ((data[4] = tg3_test_loopback(tp)) != 0)
11216                         etest->flags |= ETH_TEST_FL_FAILED;
11217
11218                 tg3_full_unlock(tp);
11219
11220                 if (tg3_test_interrupt(tp) != 0) {
11221                         etest->flags |= ETH_TEST_FL_FAILED;
11222                         data[5] = 1;
11223                 }
11224
11225                 tg3_full_lock(tp, 0);
11226
11227                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11228                 if (netif_running(dev)) {
11229                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11230                         err2 = tg3_restart_hw(tp, 1);
11231                         if (!err2)
11232                                 tg3_netif_start(tp);
11233                 }
11234
11235                 tg3_full_unlock(tp);
11236
11237                 if (irq_sync && !err2)
11238                         tg3_phy_start(tp);
11239         }
11240         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11241                 tg3_power_down(tp);
11242
11243 }
11244
11245 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11246 {
11247         struct mii_ioctl_data *data = if_mii(ifr);
11248         struct tg3 *tp = netdev_priv(dev);
11249         int err;
11250
11251         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11252                 struct phy_device *phydev;
11253                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11254                         return -EAGAIN;
11255                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11256                 return phy_mii_ioctl(phydev, ifr, cmd);
11257         }
11258
11259         switch (cmd) {
11260         case SIOCGMIIPHY:
11261                 data->phy_id = tp->phy_addr;
11262
11263                 /* fallthru */
11264         case SIOCGMIIREG: {
11265                 u32 mii_regval;
11266
11267                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11268                         break;                  /* We have no PHY */
11269
11270                 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
11271                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
11272                      !netif_running(dev)))
11273                         return -EAGAIN;
11274
11275                 spin_lock_bh(&tp->lock);
11276                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11277                 spin_unlock_bh(&tp->lock);
11278
11279                 data->val_out = mii_regval;
11280
11281                 return err;
11282         }
11283
11284         case SIOCSMIIREG:
11285                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11286                         break;                  /* We have no PHY */
11287
11288                 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
11289                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
11290                      !netif_running(dev)))
11291                         return -EAGAIN;
11292
11293                 spin_lock_bh(&tp->lock);
11294                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11295                 spin_unlock_bh(&tp->lock);
11296
11297                 return err;
11298
11299         default:
11300                 /* do nothing */
11301                 break;
11302         }
11303         return -EOPNOTSUPP;
11304 }
11305
11306 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11307 {
11308         struct tg3 *tp = netdev_priv(dev);
11309
11310         memcpy(ec, &tp->coal, sizeof(*ec));
11311         return 0;
11312 }
11313
11314 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11315 {
11316         struct tg3 *tp = netdev_priv(dev);
11317         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11318         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11319
11320         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11321                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11322                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11323                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11324                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11325         }
11326
11327         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11328             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11329             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11330             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11331             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11332             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11333             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11334             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11335             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11336             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11337                 return -EINVAL;
11338
11339         /* No rx interrupts will be generated if both are zero */
11340         if ((ec->rx_coalesce_usecs == 0) &&
11341             (ec->rx_max_coalesced_frames == 0))
11342                 return -EINVAL;
11343
11344         /* No tx interrupts will be generated if both are zero */
11345         if ((ec->tx_coalesce_usecs == 0) &&
11346             (ec->tx_max_coalesced_frames == 0))
11347                 return -EINVAL;
11348
11349         /* Only copy relevant parameters, ignore all others. */
11350         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11351         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11352         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11353         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11354         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11355         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11356         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11357         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11358         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11359
11360         if (netif_running(dev)) {
11361                 tg3_full_lock(tp, 0);
11362                 __tg3_set_coalesce(tp, &tp->coal);
11363                 tg3_full_unlock(tp);
11364         }
11365         return 0;
11366 }
11367
11368 static const struct ethtool_ops tg3_ethtool_ops = {
11369         .get_settings           = tg3_get_settings,
11370         .set_settings           = tg3_set_settings,
11371         .get_drvinfo            = tg3_get_drvinfo,
11372         .get_regs_len           = tg3_get_regs_len,
11373         .get_regs               = tg3_get_regs,
11374         .get_wol                = tg3_get_wol,
11375         .set_wol                = tg3_set_wol,
11376         .get_msglevel           = tg3_get_msglevel,
11377         .set_msglevel           = tg3_set_msglevel,
11378         .nway_reset             = tg3_nway_reset,
11379         .get_link               = ethtool_op_get_link,
11380         .get_eeprom_len         = tg3_get_eeprom_len,
11381         .get_eeprom             = tg3_get_eeprom,
11382         .set_eeprom             = tg3_set_eeprom,
11383         .get_ringparam          = tg3_get_ringparam,
11384         .set_ringparam          = tg3_set_ringparam,
11385         .get_pauseparam         = tg3_get_pauseparam,
11386         .set_pauseparam         = tg3_set_pauseparam,
11387         .self_test              = tg3_self_test,
11388         .get_strings            = tg3_get_strings,
11389         .set_phys_id            = tg3_set_phys_id,
11390         .get_ethtool_stats      = tg3_get_ethtool_stats,
11391         .get_coalesce           = tg3_get_coalesce,
11392         .set_coalesce           = tg3_set_coalesce,
11393         .get_sset_count         = tg3_get_sset_count,
11394 };
11395
11396 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11397 {
11398         u32 cursize, val, magic;
11399
11400         tp->nvram_size = EEPROM_CHIP_SIZE;
11401
11402         if (tg3_nvram_read(tp, 0, &magic) != 0)
11403                 return;
11404
11405         if ((magic != TG3_EEPROM_MAGIC) &&
11406             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11407             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11408                 return;
11409
11410         /*
11411          * Size the chip by reading offsets at increasing powers of two.
11412          * When we encounter our validation signature, we know the addressing
11413          * has wrapped around, and thus have our chip size.
11414          */
11415         cursize = 0x10;
11416
11417         while (cursize < tp->nvram_size) {
11418                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11419                         return;
11420
11421                 if (val == magic)
11422                         break;
11423
11424                 cursize <<= 1;
11425         }
11426
11427         tp->nvram_size = cursize;
11428 }
11429
11430 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11431 {
11432         u32 val;
11433
11434         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11435             tg3_nvram_read(tp, 0, &val) != 0)
11436                 return;
11437
11438         /* Selfboot format */
11439         if (val != TG3_EEPROM_MAGIC) {
11440                 tg3_get_eeprom_size(tp);
11441                 return;
11442         }
11443
11444         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11445                 if (val != 0) {
11446                         /* This is confusing.  We want to operate on the
11447                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11448                          * call will read from NVRAM and byteswap the data
11449                          * according to the byteswapping settings for all
11450                          * other register accesses.  This ensures the data we
11451                          * want will always reside in the lower 16-bits.
11452                          * However, the data in NVRAM is in LE format, which
11453                          * means the data from the NVRAM read will always be
11454                          * opposite the endianness of the CPU.  The 16-bit
11455                          * byteswap then brings the data to CPU endianness.
11456                          */
11457                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11458                         return;
11459                 }
11460         }
11461         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11462 }
11463
11464 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11465 {
11466         u32 nvcfg1;
11467
11468         nvcfg1 = tr32(NVRAM_CFG1);
11469         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11470                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11471         } else {
11472                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11473                 tw32(NVRAM_CFG1, nvcfg1);
11474         }
11475
11476         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11477             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11478                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11479                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11480                         tp->nvram_jedecnum = JEDEC_ATMEL;
11481                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11482                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11483                         break;
11484                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11485                         tp->nvram_jedecnum = JEDEC_ATMEL;
11486                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11487                         break;
11488                 case FLASH_VENDOR_ATMEL_EEPROM:
11489                         tp->nvram_jedecnum = JEDEC_ATMEL;
11490                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11491                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11492                         break;
11493                 case FLASH_VENDOR_ST:
11494                         tp->nvram_jedecnum = JEDEC_ST;
11495                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11496                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11497                         break;
11498                 case FLASH_VENDOR_SAIFUN:
11499                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11500                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11501                         break;
11502                 case FLASH_VENDOR_SST_SMALL:
11503                 case FLASH_VENDOR_SST_LARGE:
11504                         tp->nvram_jedecnum = JEDEC_SST;
11505                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11506                         break;
11507                 }
11508         } else {
11509                 tp->nvram_jedecnum = JEDEC_ATMEL;
11510                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11511                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11512         }
11513 }
11514
11515 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11516 {
11517         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11518         case FLASH_5752PAGE_SIZE_256:
11519                 tp->nvram_pagesize = 256;
11520                 break;
11521         case FLASH_5752PAGE_SIZE_512:
11522                 tp->nvram_pagesize = 512;
11523                 break;
11524         case FLASH_5752PAGE_SIZE_1K:
11525                 tp->nvram_pagesize = 1024;
11526                 break;
11527         case FLASH_5752PAGE_SIZE_2K:
11528                 tp->nvram_pagesize = 2048;
11529                 break;
11530         case FLASH_5752PAGE_SIZE_4K:
11531                 tp->nvram_pagesize = 4096;
11532                 break;
11533         case FLASH_5752PAGE_SIZE_264:
11534                 tp->nvram_pagesize = 264;
11535                 break;
11536         case FLASH_5752PAGE_SIZE_528:
11537                 tp->nvram_pagesize = 528;
11538                 break;
11539         }
11540 }
11541
11542 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11543 {
11544         u32 nvcfg1;
11545
11546         nvcfg1 = tr32(NVRAM_CFG1);
11547
11548         /* NVRAM protection for TPM */
11549         if (nvcfg1 & (1 << 27))
11550                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11551
11552         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11553         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11554         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11555                 tp->nvram_jedecnum = JEDEC_ATMEL;
11556                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11557                 break;
11558         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11559                 tp->nvram_jedecnum = JEDEC_ATMEL;
11560                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11561                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11562                 break;
11563         case FLASH_5752VENDOR_ST_M45PE10:
11564         case FLASH_5752VENDOR_ST_M45PE20:
11565         case FLASH_5752VENDOR_ST_M45PE40:
11566                 tp->nvram_jedecnum = JEDEC_ST;
11567                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11568                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11569                 break;
11570         }
11571
11572         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11573                 tg3_nvram_get_pagesize(tp, nvcfg1);
11574         } else {
11575                 /* For eeprom, set pagesize to maximum eeprom size */
11576                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11577
11578                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11579                 tw32(NVRAM_CFG1, nvcfg1);
11580         }
11581 }
11582
11583 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11584 {
11585         u32 nvcfg1, protect = 0;
11586
11587         nvcfg1 = tr32(NVRAM_CFG1);
11588
11589         /* NVRAM protection for TPM */
11590         if (nvcfg1 & (1 << 27)) {
11591                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11592                 protect = 1;
11593         }
11594
11595         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11596         switch (nvcfg1) {
11597         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11598         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11599         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11600         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11601                 tp->nvram_jedecnum = JEDEC_ATMEL;
11602                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11603                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11604                 tp->nvram_pagesize = 264;
11605                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11606                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11607                         tp->nvram_size = (protect ? 0x3e200 :
11608                                           TG3_NVRAM_SIZE_512KB);
11609                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11610                         tp->nvram_size = (protect ? 0x1f200 :
11611                                           TG3_NVRAM_SIZE_256KB);
11612                 else
11613                         tp->nvram_size = (protect ? 0x1f200 :
11614                                           TG3_NVRAM_SIZE_128KB);
11615                 break;
11616         case FLASH_5752VENDOR_ST_M45PE10:
11617         case FLASH_5752VENDOR_ST_M45PE20:
11618         case FLASH_5752VENDOR_ST_M45PE40:
11619                 tp->nvram_jedecnum = JEDEC_ST;
11620                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11621                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11622                 tp->nvram_pagesize = 256;
11623                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11624                         tp->nvram_size = (protect ?
11625                                           TG3_NVRAM_SIZE_64KB :
11626                                           TG3_NVRAM_SIZE_128KB);
11627                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11628                         tp->nvram_size = (protect ?
11629                                           TG3_NVRAM_SIZE_64KB :
11630                                           TG3_NVRAM_SIZE_256KB);
11631                 else
11632                         tp->nvram_size = (protect ?
11633                                           TG3_NVRAM_SIZE_128KB :
11634                                           TG3_NVRAM_SIZE_512KB);
11635                 break;
11636         }
11637 }
11638
11639 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11640 {
11641         u32 nvcfg1;
11642
11643         nvcfg1 = tr32(NVRAM_CFG1);
11644
11645         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11646         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11647         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11648         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11649         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11650                 tp->nvram_jedecnum = JEDEC_ATMEL;
11651                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11652                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11653
11654                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11655                 tw32(NVRAM_CFG1, nvcfg1);
11656                 break;
11657         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11658         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11659         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11660         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11661                 tp->nvram_jedecnum = JEDEC_ATMEL;
11662                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11663                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11664                 tp->nvram_pagesize = 264;
11665                 break;
11666         case FLASH_5752VENDOR_ST_M45PE10:
11667         case FLASH_5752VENDOR_ST_M45PE20:
11668         case FLASH_5752VENDOR_ST_M45PE40:
11669                 tp->nvram_jedecnum = JEDEC_ST;
11670                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11671                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11672                 tp->nvram_pagesize = 256;
11673                 break;
11674         }
11675 }
11676
11677 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11678 {
11679         u32 nvcfg1, protect = 0;
11680
11681         nvcfg1 = tr32(NVRAM_CFG1);
11682
11683         /* NVRAM protection for TPM */
11684         if (nvcfg1 & (1 << 27)) {
11685                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11686                 protect = 1;
11687         }
11688
11689         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11690         switch (nvcfg1) {
11691         case FLASH_5761VENDOR_ATMEL_ADB021D:
11692         case FLASH_5761VENDOR_ATMEL_ADB041D:
11693         case FLASH_5761VENDOR_ATMEL_ADB081D:
11694         case FLASH_5761VENDOR_ATMEL_ADB161D:
11695         case FLASH_5761VENDOR_ATMEL_MDB021D:
11696         case FLASH_5761VENDOR_ATMEL_MDB041D:
11697         case FLASH_5761VENDOR_ATMEL_MDB081D:
11698         case FLASH_5761VENDOR_ATMEL_MDB161D:
11699                 tp->nvram_jedecnum = JEDEC_ATMEL;
11700                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11701                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11702                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11703                 tp->nvram_pagesize = 256;
11704                 break;
11705         case FLASH_5761VENDOR_ST_A_M45PE20:
11706         case FLASH_5761VENDOR_ST_A_M45PE40:
11707         case FLASH_5761VENDOR_ST_A_M45PE80:
11708         case FLASH_5761VENDOR_ST_A_M45PE16:
11709         case FLASH_5761VENDOR_ST_M_M45PE20:
11710         case FLASH_5761VENDOR_ST_M_M45PE40:
11711         case FLASH_5761VENDOR_ST_M_M45PE80:
11712         case FLASH_5761VENDOR_ST_M_M45PE16:
11713                 tp->nvram_jedecnum = JEDEC_ST;
11714                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11715                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11716                 tp->nvram_pagesize = 256;
11717                 break;
11718         }
11719
11720         if (protect) {
11721                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11722         } else {
11723                 switch (nvcfg1) {
11724                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11725                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11726                 case FLASH_5761VENDOR_ST_A_M45PE16:
11727                 case FLASH_5761VENDOR_ST_M_M45PE16:
11728                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11729                         break;
11730                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11731                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11732                 case FLASH_5761VENDOR_ST_A_M45PE80:
11733                 case FLASH_5761VENDOR_ST_M_M45PE80:
11734                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11735                         break;
11736                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11737                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11738                 case FLASH_5761VENDOR_ST_A_M45PE40:
11739                 case FLASH_5761VENDOR_ST_M_M45PE40:
11740                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11741                         break;
11742                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11743                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11744                 case FLASH_5761VENDOR_ST_A_M45PE20:
11745                 case FLASH_5761VENDOR_ST_M_M45PE20:
11746                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11747                         break;
11748                 }
11749         }
11750 }
11751
11752 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11753 {
11754         tp->nvram_jedecnum = JEDEC_ATMEL;
11755         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11756         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11757 }
11758
11759 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11760 {
11761         u32 nvcfg1;
11762
11763         nvcfg1 = tr32(NVRAM_CFG1);
11764
11765         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11766         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11767         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11768                 tp->nvram_jedecnum = JEDEC_ATMEL;
11769                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11770                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11771
11772                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11773                 tw32(NVRAM_CFG1, nvcfg1);
11774                 return;
11775         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11776         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11777         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11778         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11779         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11780         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11781         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11782                 tp->nvram_jedecnum = JEDEC_ATMEL;
11783                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11784                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11785
11786                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11787                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11788                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11789                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11790                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11791                         break;
11792                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11793                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11794                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11795                         break;
11796                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11797                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11798                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11799                         break;
11800                 }
11801                 break;
11802         case FLASH_5752VENDOR_ST_M45PE10:
11803         case FLASH_5752VENDOR_ST_M45PE20:
11804         case FLASH_5752VENDOR_ST_M45PE40:
11805                 tp->nvram_jedecnum = JEDEC_ST;
11806                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11807                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11808
11809                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11810                 case FLASH_5752VENDOR_ST_M45PE10:
11811                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11812                         break;
11813                 case FLASH_5752VENDOR_ST_M45PE20:
11814                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11815                         break;
11816                 case FLASH_5752VENDOR_ST_M45PE40:
11817                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11818                         break;
11819                 }
11820                 break;
11821         default:
11822                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11823                 return;
11824         }
11825
11826         tg3_nvram_get_pagesize(tp, nvcfg1);
11827         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11828                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11829 }
11830
11831
11832 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11833 {
11834         u32 nvcfg1;
11835
11836         nvcfg1 = tr32(NVRAM_CFG1);
11837
11838         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11839         case FLASH_5717VENDOR_ATMEL_EEPROM:
11840         case FLASH_5717VENDOR_MICRO_EEPROM:
11841                 tp->nvram_jedecnum = JEDEC_ATMEL;
11842                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11843                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11844
11845                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11846                 tw32(NVRAM_CFG1, nvcfg1);
11847                 return;
11848         case FLASH_5717VENDOR_ATMEL_MDB011D:
11849         case FLASH_5717VENDOR_ATMEL_ADB011B:
11850         case FLASH_5717VENDOR_ATMEL_ADB011D:
11851         case FLASH_5717VENDOR_ATMEL_MDB021D:
11852         case FLASH_5717VENDOR_ATMEL_ADB021B:
11853         case FLASH_5717VENDOR_ATMEL_ADB021D:
11854         case FLASH_5717VENDOR_ATMEL_45USPT:
11855                 tp->nvram_jedecnum = JEDEC_ATMEL;
11856                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11857                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11858
11859                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11860                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11861                         /* Detect size with tg3_nvram_get_size() */
11862                         break;
11863                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11864                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11865                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11866                         break;
11867                 default:
11868                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11869                         break;
11870                 }
11871                 break;
11872         case FLASH_5717VENDOR_ST_M_M25PE10:
11873         case FLASH_5717VENDOR_ST_A_M25PE10:
11874         case FLASH_5717VENDOR_ST_M_M45PE10:
11875         case FLASH_5717VENDOR_ST_A_M45PE10:
11876         case FLASH_5717VENDOR_ST_M_M25PE20:
11877         case FLASH_5717VENDOR_ST_A_M25PE20:
11878         case FLASH_5717VENDOR_ST_M_M45PE20:
11879         case FLASH_5717VENDOR_ST_A_M45PE20:
11880         case FLASH_5717VENDOR_ST_25USPT:
11881         case FLASH_5717VENDOR_ST_45USPT:
11882                 tp->nvram_jedecnum = JEDEC_ST;
11883                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11884                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11885
11886                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11887                 case FLASH_5717VENDOR_ST_M_M25PE20:
11888                 case FLASH_5717VENDOR_ST_M_M45PE20:
11889                         /* Detect size with tg3_nvram_get_size() */
11890                         break;
11891                 case FLASH_5717VENDOR_ST_A_M25PE20:
11892                 case FLASH_5717VENDOR_ST_A_M45PE20:
11893                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11894                         break;
11895                 default:
11896                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11897                         break;
11898                 }
11899                 break;
11900         default:
11901                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11902                 return;
11903         }
11904
11905         tg3_nvram_get_pagesize(tp, nvcfg1);
11906         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11907                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11908 }
11909
11910 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
11911 {
11912         u32 nvcfg1, nvmpinstrp;
11913
11914         nvcfg1 = tr32(NVRAM_CFG1);
11915         nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
11916
11917         switch (nvmpinstrp) {
11918         case FLASH_5720_EEPROM_HD:
11919         case FLASH_5720_EEPROM_LD:
11920                 tp->nvram_jedecnum = JEDEC_ATMEL;
11921                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11922
11923                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11924                 tw32(NVRAM_CFG1, nvcfg1);
11925                 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
11926                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11927                 else
11928                         tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
11929                 return;
11930         case FLASH_5720VENDOR_M_ATMEL_DB011D:
11931         case FLASH_5720VENDOR_A_ATMEL_DB011B:
11932         case FLASH_5720VENDOR_A_ATMEL_DB011D:
11933         case FLASH_5720VENDOR_M_ATMEL_DB021D:
11934         case FLASH_5720VENDOR_A_ATMEL_DB021B:
11935         case FLASH_5720VENDOR_A_ATMEL_DB021D:
11936         case FLASH_5720VENDOR_M_ATMEL_DB041D:
11937         case FLASH_5720VENDOR_A_ATMEL_DB041B:
11938         case FLASH_5720VENDOR_A_ATMEL_DB041D:
11939         case FLASH_5720VENDOR_M_ATMEL_DB081D:
11940         case FLASH_5720VENDOR_A_ATMEL_DB081D:
11941         case FLASH_5720VENDOR_ATMEL_45USPT:
11942                 tp->nvram_jedecnum = JEDEC_ATMEL;
11943                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11944                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11945
11946                 switch (nvmpinstrp) {
11947                 case FLASH_5720VENDOR_M_ATMEL_DB021D:
11948                 case FLASH_5720VENDOR_A_ATMEL_DB021B:
11949                 case FLASH_5720VENDOR_A_ATMEL_DB021D:
11950                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11951                         break;
11952                 case FLASH_5720VENDOR_M_ATMEL_DB041D:
11953                 case FLASH_5720VENDOR_A_ATMEL_DB041B:
11954                 case FLASH_5720VENDOR_A_ATMEL_DB041D:
11955                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11956                         break;
11957                 case FLASH_5720VENDOR_M_ATMEL_DB081D:
11958                 case FLASH_5720VENDOR_A_ATMEL_DB081D:
11959                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11960                         break;
11961                 default:
11962                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11963                         break;
11964                 }
11965                 break;
11966         case FLASH_5720VENDOR_M_ST_M25PE10:
11967         case FLASH_5720VENDOR_M_ST_M45PE10:
11968         case FLASH_5720VENDOR_A_ST_M25PE10:
11969         case FLASH_5720VENDOR_A_ST_M45PE10:
11970         case FLASH_5720VENDOR_M_ST_M25PE20:
11971         case FLASH_5720VENDOR_M_ST_M45PE20:
11972         case FLASH_5720VENDOR_A_ST_M25PE20:
11973         case FLASH_5720VENDOR_A_ST_M45PE20:
11974         case FLASH_5720VENDOR_M_ST_M25PE40:
11975         case FLASH_5720VENDOR_M_ST_M45PE40:
11976         case FLASH_5720VENDOR_A_ST_M25PE40:
11977         case FLASH_5720VENDOR_A_ST_M45PE40:
11978         case FLASH_5720VENDOR_M_ST_M25PE80:
11979         case FLASH_5720VENDOR_M_ST_M45PE80:
11980         case FLASH_5720VENDOR_A_ST_M25PE80:
11981         case FLASH_5720VENDOR_A_ST_M45PE80:
11982         case FLASH_5720VENDOR_ST_25USPT:
11983         case FLASH_5720VENDOR_ST_45USPT:
11984                 tp->nvram_jedecnum = JEDEC_ST;
11985                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11986                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11987
11988                 switch (nvmpinstrp) {
11989                 case FLASH_5720VENDOR_M_ST_M25PE20:
11990                 case FLASH_5720VENDOR_M_ST_M45PE20:
11991                 case FLASH_5720VENDOR_A_ST_M25PE20:
11992                 case FLASH_5720VENDOR_A_ST_M45PE20:
11993                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11994                         break;
11995                 case FLASH_5720VENDOR_M_ST_M25PE40:
11996                 case FLASH_5720VENDOR_M_ST_M45PE40:
11997                 case FLASH_5720VENDOR_A_ST_M25PE40:
11998                 case FLASH_5720VENDOR_A_ST_M45PE40:
11999                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12000                         break;
12001                 case FLASH_5720VENDOR_M_ST_M25PE80:
12002                 case FLASH_5720VENDOR_M_ST_M45PE80:
12003                 case FLASH_5720VENDOR_A_ST_M25PE80:
12004                 case FLASH_5720VENDOR_A_ST_M45PE80:
12005                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12006                         break;
12007                 default:
12008                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12009                         break;
12010                 }
12011                 break;
12012         default:
12013                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
12014                 return;
12015         }
12016
12017         tg3_nvram_get_pagesize(tp, nvcfg1);
12018         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12019                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
12020 }
12021
12022 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12023 static void __devinit tg3_nvram_init(struct tg3 *tp)
12024 {
12025         tw32_f(GRC_EEPROM_ADDR,
12026              (EEPROM_ADDR_FSM_RESET |
12027               (EEPROM_DEFAULT_CLOCK_PERIOD <<
12028                EEPROM_ADDR_CLKPERD_SHIFT)));
12029
12030         msleep(1);
12031
12032         /* Enable seeprom accesses. */
12033         tw32_f(GRC_LOCAL_CTRL,
12034              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12035         udelay(100);
12036
12037         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12038             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12039                 tp->tg3_flags |= TG3_FLAG_NVRAM;
12040
12041                 if (tg3_nvram_lock(tp)) {
12042                         netdev_warn(tp->dev,
12043                                     "Cannot get nvram lock, %s failed\n",
12044                                     __func__);
12045                         return;
12046                 }
12047                 tg3_enable_nvram_access(tp);
12048
12049                 tp->nvram_size = 0;
12050
12051                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12052                         tg3_get_5752_nvram_info(tp);
12053                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12054                         tg3_get_5755_nvram_info(tp);
12055                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12056                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12057                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12058                         tg3_get_5787_nvram_info(tp);
12059                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12060                         tg3_get_5761_nvram_info(tp);
12061                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12062                         tg3_get_5906_nvram_info(tp);
12063                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12064                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12065                         tg3_get_57780_nvram_info(tp);
12066                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12067                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
12068                         tg3_get_5717_nvram_info(tp);
12069                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12070                         tg3_get_5720_nvram_info(tp);
12071                 else
12072                         tg3_get_nvram_info(tp);
12073
12074                 if (tp->nvram_size == 0)
12075                         tg3_get_nvram_size(tp);
12076
12077                 tg3_disable_nvram_access(tp);
12078                 tg3_nvram_unlock(tp);
12079
12080         } else {
12081                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
12082
12083                 tg3_get_eeprom_size(tp);
12084         }
12085 }
12086
12087 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
12088                                     u32 offset, u32 len, u8 *buf)
12089 {
12090         int i, j, rc = 0;
12091         u32 val;
12092
12093         for (i = 0; i < len; i += 4) {
12094                 u32 addr;
12095                 __be32 data;
12096
12097                 addr = offset + i;
12098
12099                 memcpy(&data, buf + i, 4);
12100
12101                 /*
12102                  * The SEEPROM interface expects the data to always be opposite
12103                  * the native endian format.  We accomplish this by reversing
12104                  * all the operations that would have been performed on the
12105                  * data from a call to tg3_nvram_read_be32().
12106                  */
12107                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
12108
12109                 val = tr32(GRC_EEPROM_ADDR);
12110                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
12111
12112                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
12113                         EEPROM_ADDR_READ);
12114                 tw32(GRC_EEPROM_ADDR, val |
12115                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
12116                         (addr & EEPROM_ADDR_ADDR_MASK) |
12117                         EEPROM_ADDR_START |
12118                         EEPROM_ADDR_WRITE);
12119
12120                 for (j = 0; j < 1000; j++) {
12121                         val = tr32(GRC_EEPROM_ADDR);
12122
12123                         if (val & EEPROM_ADDR_COMPLETE)
12124                                 break;
12125                         msleep(1);
12126                 }
12127                 if (!(val & EEPROM_ADDR_COMPLETE)) {
12128                         rc = -EBUSY;
12129                         break;
12130                 }
12131         }
12132
12133         return rc;
12134 }
12135
12136 /* offset and length are dword aligned */
12137 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12138                 u8 *buf)
12139 {
12140         int ret = 0;
12141         u32 pagesize = tp->nvram_pagesize;
12142         u32 pagemask = pagesize - 1;
12143         u32 nvram_cmd;
12144         u8 *tmp;
12145
12146         tmp = kmalloc(pagesize, GFP_KERNEL);
12147         if (tmp == NULL)
12148                 return -ENOMEM;
12149
12150         while (len) {
12151                 int j;
12152                 u32 phy_addr, page_off, size;
12153
12154                 phy_addr = offset & ~pagemask;
12155
12156                 for (j = 0; j < pagesize; j += 4) {
12157                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
12158                                                   (__be32 *) (tmp + j));
12159                         if (ret)
12160                                 break;
12161                 }
12162                 if (ret)
12163                         break;
12164
12165                 page_off = offset & pagemask;
12166                 size = pagesize;
12167                 if (len < size)
12168                         size = len;
12169
12170                 len -= size;
12171
12172                 memcpy(tmp + page_off, buf, size);
12173
12174                 offset = offset + (pagesize - page_off);
12175
12176                 tg3_enable_nvram_access(tp);
12177
12178                 /*
12179                  * Before we can erase the flash page, we need
12180                  * to issue a special "write enable" command.
12181                  */
12182                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12183
12184                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12185                         break;
12186
12187                 /* Erase the target page */
12188                 tw32(NVRAM_ADDR, phy_addr);
12189
12190                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12191                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12192
12193                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12194                         break;
12195
12196                 /* Issue another write enable to start the write. */
12197                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12198
12199                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12200                         break;
12201
12202                 for (j = 0; j < pagesize; j += 4) {
12203                         __be32 data;
12204
12205                         data = *((__be32 *) (tmp + j));
12206
12207                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
12208
12209                         tw32(NVRAM_ADDR, phy_addr + j);
12210
12211                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12212                                 NVRAM_CMD_WR;
12213
12214                         if (j == 0)
12215                                 nvram_cmd |= NVRAM_CMD_FIRST;
12216                         else if (j == (pagesize - 4))
12217                                 nvram_cmd |= NVRAM_CMD_LAST;
12218
12219                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12220                                 break;
12221                 }
12222                 if (ret)
12223                         break;
12224         }
12225
12226         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12227         tg3_nvram_exec_cmd(tp, nvram_cmd);
12228
12229         kfree(tmp);
12230
12231         return ret;
12232 }
12233
12234 /* offset and length are dword aligned */
12235 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12236                 u8 *buf)
12237 {
12238         int i, ret = 0;
12239
12240         for (i = 0; i < len; i += 4, offset += 4) {
12241                 u32 page_off, phy_addr, nvram_cmd;
12242                 __be32 data;
12243
12244                 memcpy(&data, buf + i, 4);
12245                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12246
12247                 page_off = offset % tp->nvram_pagesize;
12248
12249                 phy_addr = tg3_nvram_phys_addr(tp, offset);
12250
12251                 tw32(NVRAM_ADDR, phy_addr);
12252
12253                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12254
12255                 if (page_off == 0 || i == 0)
12256                         nvram_cmd |= NVRAM_CMD_FIRST;
12257                 if (page_off == (tp->nvram_pagesize - 4))
12258                         nvram_cmd |= NVRAM_CMD_LAST;
12259
12260                 if (i == (len - 4))
12261                         nvram_cmd |= NVRAM_CMD_LAST;
12262
12263                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12264                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12265                     (tp->nvram_jedecnum == JEDEC_ST) &&
12266                     (nvram_cmd & NVRAM_CMD_FIRST)) {
12267
12268                         if ((ret = tg3_nvram_exec_cmd(tp,
12269                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12270                                 NVRAM_CMD_DONE)))
12271
12272                                 break;
12273                 }
12274                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12275                         /* We always do complete word writes to eeprom. */
12276                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12277                 }
12278
12279                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12280                         break;
12281         }
12282         return ret;
12283 }
12284
12285 /* offset and length are dword aligned */
12286 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12287 {
12288         int ret;
12289
12290         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12291                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12292                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
12293                 udelay(40);
12294         }
12295
12296         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12297                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12298         } else {
12299                 u32 grc_mode;
12300
12301                 ret = tg3_nvram_lock(tp);
12302                 if (ret)
12303                         return ret;
12304
12305                 tg3_enable_nvram_access(tp);
12306                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12307                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12308                         tw32(NVRAM_WRITE1, 0x406);
12309
12310                 grc_mode = tr32(GRC_MODE);
12311                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12312
12313                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12314                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12315
12316                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12317                                 buf);
12318                 } else {
12319                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12320                                 buf);
12321                 }
12322
12323                 grc_mode = tr32(GRC_MODE);
12324                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12325
12326                 tg3_disable_nvram_access(tp);
12327                 tg3_nvram_unlock(tp);
12328         }
12329
12330         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12331                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12332                 udelay(40);
12333         }
12334
12335         return ret;
12336 }
12337
12338 struct subsys_tbl_ent {
12339         u16 subsys_vendor, subsys_devid;
12340         u32 phy_id;
12341 };
12342
12343 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12344         /* Broadcom boards. */
12345         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12346           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12347         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12348           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12349         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12350           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12351         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12352           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12353         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12354           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12355         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12356           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12357         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12358           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12359         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12360           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12361         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12362           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12363         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12364           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12365         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12366           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12367
12368         /* 3com boards. */
12369         { TG3PCI_SUBVENDOR_ID_3COM,
12370           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12371         { TG3PCI_SUBVENDOR_ID_3COM,
12372           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12373         { TG3PCI_SUBVENDOR_ID_3COM,
12374           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12375         { TG3PCI_SUBVENDOR_ID_3COM,
12376           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12377         { TG3PCI_SUBVENDOR_ID_3COM,
12378           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12379
12380         /* DELL boards. */
12381         { TG3PCI_SUBVENDOR_ID_DELL,
12382           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12383         { TG3PCI_SUBVENDOR_ID_DELL,
12384           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12385         { TG3PCI_SUBVENDOR_ID_DELL,
12386           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12387         { TG3PCI_SUBVENDOR_ID_DELL,
12388           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12389
12390         /* Compaq boards. */
12391         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12392           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12393         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12394           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12395         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12396           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12397         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12398           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12399         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12400           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12401
12402         /* IBM boards. */
12403         { TG3PCI_SUBVENDOR_ID_IBM,
12404           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12405 };
12406
12407 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12408 {
12409         int i;
12410
12411         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12412                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12413                      tp->pdev->subsystem_vendor) &&
12414                     (subsys_id_to_phy_id[i].subsys_devid ==
12415                      tp->pdev->subsystem_device))
12416                         return &subsys_id_to_phy_id[i];
12417         }
12418         return NULL;
12419 }
12420
12421 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12422 {
12423         u32 val;
12424         u16 pmcsr;
12425
12426         /* On some early chips the SRAM cannot be accessed in D3hot state,
12427          * so need make sure we're in D0.
12428          */
12429         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12430         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12431         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12432         msleep(1);
12433
12434         /* Make sure register accesses (indirect or otherwise)
12435          * will function correctly.
12436          */
12437         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12438                                tp->misc_host_ctrl);
12439
12440         /* The memory arbiter has to be enabled in order for SRAM accesses
12441          * to succeed.  Normally on powerup the tg3 chip firmware will make
12442          * sure it is enabled, but other entities such as system netboot
12443          * code might disable it.
12444          */
12445         val = tr32(MEMARB_MODE);
12446         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12447
12448         tp->phy_id = TG3_PHY_ID_INVALID;
12449         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12450
12451         /* Assume an onboard device and WOL capable by default.  */
12452         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12453
12454         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12455                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12456                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12457                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12458                 }
12459                 val = tr32(VCPU_CFGSHDW);
12460                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12461                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12462                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12463                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12464                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12465                 goto done;
12466         }
12467
12468         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12469         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12470                 u32 nic_cfg, led_cfg;
12471                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12472                 int eeprom_phy_serdes = 0;
12473
12474                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12475                 tp->nic_sram_data_cfg = nic_cfg;
12476
12477                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12478                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12479                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12480                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12481                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12482                     (ver > 0) && (ver < 0x100))
12483                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12484
12485                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12486                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12487
12488                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12489                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12490                         eeprom_phy_serdes = 1;
12491
12492                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12493                 if (nic_phy_id != 0) {
12494                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12495                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12496
12497                         eeprom_phy_id  = (id1 >> 16) << 10;
12498                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12499                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12500                 } else
12501                         eeprom_phy_id = 0;
12502
12503                 tp->phy_id = eeprom_phy_id;
12504                 if (eeprom_phy_serdes) {
12505                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12506                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12507                         else
12508                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12509                 }
12510
12511                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12512                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12513                                     SHASTA_EXT_LED_MODE_MASK);
12514                 else
12515                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12516
12517                 switch (led_cfg) {
12518                 default:
12519                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12520                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12521                         break;
12522
12523                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12524                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12525                         break;
12526
12527                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12528                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12529
12530                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12531                          * read on some older 5700/5701 bootcode.
12532                          */
12533                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12534                             ASIC_REV_5700 ||
12535                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12536                             ASIC_REV_5701)
12537                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12538
12539                         break;
12540
12541                 case SHASTA_EXT_LED_SHARED:
12542                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12543                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12544                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12545                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12546                                                  LED_CTRL_MODE_PHY_2);
12547                         break;
12548
12549                 case SHASTA_EXT_LED_MAC:
12550                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12551                         break;
12552
12553                 case SHASTA_EXT_LED_COMBO:
12554                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12555                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12556                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12557                                                  LED_CTRL_MODE_PHY_2);
12558                         break;
12559
12560                 }
12561
12562                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12563                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12564                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12565                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12566
12567                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12568                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12569
12570                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12571                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12572                         if ((tp->pdev->subsystem_vendor ==
12573                              PCI_VENDOR_ID_ARIMA) &&
12574                             (tp->pdev->subsystem_device == 0x205a ||
12575                              tp->pdev->subsystem_device == 0x2063))
12576                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12577                 } else {
12578                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12579                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12580                 }
12581
12582                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12583                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12584                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12585                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12586                 }
12587
12588                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12589                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12590                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12591
12592                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12593                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12594                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12595
12596                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12597                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12598                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12599
12600                 if (cfg2 & (1 << 17))
12601                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12602
12603                 /* serdes signal pre-emphasis in register 0x590 set by */
12604                 /* bootcode if bit 18 is set */
12605                 if (cfg2 & (1 << 18))
12606                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12607
12608                 if (((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) ||
12609                     ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12610                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) &&
12611                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12612                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12613
12614                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12615                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12616                     !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
12617                         u32 cfg3;
12618
12619                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12620                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12621                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12622                 }
12623
12624                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12625                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12626                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12627                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12628                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12629                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12630         }
12631 done:
12632         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
12633                 device_set_wakeup_enable(&tp->pdev->dev,
12634                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12635         else
12636                 device_set_wakeup_capable(&tp->pdev->dev, false);
12637 }
12638
12639 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12640 {
12641         int i;
12642         u32 val;
12643
12644         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12645         tw32(OTP_CTRL, cmd);
12646
12647         /* Wait for up to 1 ms for command to execute. */
12648         for (i = 0; i < 100; i++) {
12649                 val = tr32(OTP_STATUS);
12650                 if (val & OTP_STATUS_CMD_DONE)
12651                         break;
12652                 udelay(10);
12653         }
12654
12655         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12656 }
12657
12658 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12659  * configuration is a 32-bit value that straddles the alignment boundary.
12660  * We do two 32-bit reads and then shift and merge the results.
12661  */
12662 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12663 {
12664         u32 bhalf_otp, thalf_otp;
12665
12666         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12667
12668         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12669                 return 0;
12670
12671         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12672
12673         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12674                 return 0;
12675
12676         thalf_otp = tr32(OTP_READ_DATA);
12677
12678         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12679
12680         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12681                 return 0;
12682
12683         bhalf_otp = tr32(OTP_READ_DATA);
12684
12685         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12686 }
12687
12688 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
12689 {
12690         u32 adv = ADVERTISED_Autoneg |
12691                   ADVERTISED_Pause;
12692
12693         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12694                 adv |= ADVERTISED_1000baseT_Half |
12695                        ADVERTISED_1000baseT_Full;
12696
12697         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12698                 adv |= ADVERTISED_100baseT_Half |
12699                        ADVERTISED_100baseT_Full |
12700                        ADVERTISED_10baseT_Half |
12701                        ADVERTISED_10baseT_Full |
12702                        ADVERTISED_TP;
12703         else
12704                 adv |= ADVERTISED_FIBRE;
12705
12706         tp->link_config.advertising = adv;
12707         tp->link_config.speed = SPEED_INVALID;
12708         tp->link_config.duplex = DUPLEX_INVALID;
12709         tp->link_config.autoneg = AUTONEG_ENABLE;
12710         tp->link_config.active_speed = SPEED_INVALID;
12711         tp->link_config.active_duplex = DUPLEX_INVALID;
12712         tp->link_config.orig_speed = SPEED_INVALID;
12713         tp->link_config.orig_duplex = DUPLEX_INVALID;
12714         tp->link_config.orig_autoneg = AUTONEG_INVALID;
12715 }
12716
12717 static int __devinit tg3_phy_probe(struct tg3 *tp)
12718 {
12719         u32 hw_phy_id_1, hw_phy_id_2;
12720         u32 hw_phy_id, hw_phy_id_masked;
12721         int err;
12722
12723         /* flow control autonegotiation is default behavior */
12724         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12725         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
12726
12727         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12728                 return tg3_phy_init(tp);
12729
12730         /* Reading the PHY ID register can conflict with ASF
12731          * firmware access to the PHY hardware.
12732          */
12733         err = 0;
12734         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12735             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12736                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12737         } else {
12738                 /* Now read the physical PHY_ID from the chip and verify
12739                  * that it is sane.  If it doesn't look good, we fall back
12740                  * to either the hard-coded table based PHY_ID and failing
12741                  * that the value found in the eeprom area.
12742                  */
12743                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12744                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12745
12746                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12747                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12748                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12749
12750                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12751         }
12752
12753         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12754                 tp->phy_id = hw_phy_id;
12755                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12756                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12757                 else
12758                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12759         } else {
12760                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12761                         /* Do nothing, phy ID already set up in
12762                          * tg3_get_eeprom_hw_cfg().
12763                          */
12764                 } else {
12765                         struct subsys_tbl_ent *p;
12766
12767                         /* No eeprom signature?  Try the hardcoded
12768                          * subsys device table.
12769                          */
12770                         p = tg3_lookup_by_subsys(tp);
12771                         if (!p)
12772                                 return -ENODEV;
12773
12774                         tp->phy_id = p->phy_id;
12775                         if (!tp->phy_id ||
12776                             tp->phy_id == TG3_PHY_ID_BCM8002)
12777                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12778                 }
12779         }
12780
12781         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12782             ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
12783               tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
12784              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12785               tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
12786                 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12787
12788         tg3_phy_init_link_config(tp);
12789
12790         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12791             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12792             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12793                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12794
12795                 tg3_readphy(tp, MII_BMSR, &bmsr);
12796                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12797                     (bmsr & BMSR_LSTATUS))
12798                         goto skip_phy_reset;
12799
12800                 err = tg3_phy_reset(tp);
12801                 if (err)
12802                         return err;
12803
12804                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12805                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12806                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12807                 tg3_ctrl = 0;
12808                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12809                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12810                                     MII_TG3_CTRL_ADV_1000_FULL);
12811                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12812                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12813                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12814                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12815                 }
12816
12817                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12818                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12819                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12820                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12821                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12822
12823                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12824                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12825
12826                         tg3_writephy(tp, MII_BMCR,
12827                                      BMCR_ANENABLE | BMCR_ANRESTART);
12828                 }
12829                 tg3_phy_set_wirespeed(tp);
12830
12831                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12832                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12833                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12834         }
12835
12836 skip_phy_reset:
12837         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12838                 err = tg3_init_5401phy_dsp(tp);
12839                 if (err)
12840                         return err;
12841
12842                 err = tg3_init_5401phy_dsp(tp);
12843         }
12844
12845         return err;
12846 }
12847
12848 static void __devinit tg3_read_vpd(struct tg3 *tp)
12849 {
12850         u8 *vpd_data;
12851         unsigned int block_end, rosize, len;
12852         int j, i = 0;
12853         u32 magic;
12854
12855         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12856             tg3_nvram_read(tp, 0x0, &magic))
12857                 goto out_no_vpd;
12858
12859         vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12860         if (!vpd_data)
12861                 goto out_no_vpd;
12862
12863         if (magic == TG3_EEPROM_MAGIC) {
12864                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12865                         u32 tmp;
12866
12867                         /* The data is in little-endian format in NVRAM.
12868                          * Use the big-endian read routines to preserve
12869                          * the byte order as it exists in NVRAM.
12870                          */
12871                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12872                                 goto out_not_found;
12873
12874                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12875                 }
12876         } else {
12877                 ssize_t cnt;
12878                 unsigned int pos = 0;
12879
12880                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12881                         cnt = pci_read_vpd(tp->pdev, pos,
12882                                            TG3_NVM_VPD_LEN - pos,
12883                                            &vpd_data[pos]);
12884                         if (cnt == -ETIMEDOUT || cnt == -EINTR)
12885                                 cnt = 0;
12886                         else if (cnt < 0)
12887                                 goto out_not_found;
12888                 }
12889                 if (pos != TG3_NVM_VPD_LEN)
12890                         goto out_not_found;
12891         }
12892
12893         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12894                              PCI_VPD_LRDT_RO_DATA);
12895         if (i < 0)
12896                 goto out_not_found;
12897
12898         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12899         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12900         i += PCI_VPD_LRDT_TAG_SIZE;
12901
12902         if (block_end > TG3_NVM_VPD_LEN)
12903                 goto out_not_found;
12904
12905         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12906                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12907         if (j > 0) {
12908                 len = pci_vpd_info_field_size(&vpd_data[j]);
12909
12910                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12911                 if (j + len > block_end || len != 4 ||
12912                     memcmp(&vpd_data[j], "1028", 4))
12913                         goto partno;
12914
12915                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12916                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12917                 if (j < 0)
12918                         goto partno;
12919
12920                 len = pci_vpd_info_field_size(&vpd_data[j]);
12921
12922                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12923                 if (j + len > block_end)
12924                         goto partno;
12925
12926                 memcpy(tp->fw_ver, &vpd_data[j], len);
12927                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12928         }
12929
12930 partno:
12931         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12932                                       PCI_VPD_RO_KEYWORD_PARTNO);
12933         if (i < 0)
12934                 goto out_not_found;
12935
12936         len = pci_vpd_info_field_size(&vpd_data[i]);
12937
12938         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12939         if (len > TG3_BPN_SIZE ||
12940             (len + i) > TG3_NVM_VPD_LEN)
12941                 goto out_not_found;
12942
12943         memcpy(tp->board_part_number, &vpd_data[i], len);
12944
12945 out_not_found:
12946         kfree(vpd_data);
12947         if (tp->board_part_number[0])
12948                 return;
12949
12950 out_no_vpd:
12951         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12952                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12953                         strcpy(tp->board_part_number, "BCM5717");
12954                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12955                         strcpy(tp->board_part_number, "BCM5718");
12956                 else
12957                         goto nomatch;
12958         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12959                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12960                         strcpy(tp->board_part_number, "BCM57780");
12961                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12962                         strcpy(tp->board_part_number, "BCM57760");
12963                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12964                         strcpy(tp->board_part_number, "BCM57790");
12965                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12966                         strcpy(tp->board_part_number, "BCM57788");
12967                 else
12968                         goto nomatch;
12969         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12970                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12971                         strcpy(tp->board_part_number, "BCM57761");
12972                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12973                         strcpy(tp->board_part_number, "BCM57765");
12974                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12975                         strcpy(tp->board_part_number, "BCM57781");
12976                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12977                         strcpy(tp->board_part_number, "BCM57785");
12978                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12979                         strcpy(tp->board_part_number, "BCM57791");
12980                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12981                         strcpy(tp->board_part_number, "BCM57795");
12982                 else
12983                         goto nomatch;
12984         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12985                 strcpy(tp->board_part_number, "BCM95906");
12986         } else {
12987 nomatch:
12988                 strcpy(tp->board_part_number, "none");
12989         }
12990 }
12991
12992 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12993 {
12994         u32 val;
12995
12996         if (tg3_nvram_read(tp, offset, &val) ||
12997             (val & 0xfc000000) != 0x0c000000 ||
12998             tg3_nvram_read(tp, offset + 4, &val) ||
12999             val != 0)
13000                 return 0;
13001
13002         return 1;
13003 }
13004
13005 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13006 {
13007         u32 val, offset, start, ver_offset;
13008         int i, dst_off;
13009         bool newver = false;
13010
13011         if (tg3_nvram_read(tp, 0xc, &offset) ||
13012             tg3_nvram_read(tp, 0x4, &start))
13013                 return;
13014
13015         offset = tg3_nvram_logical_addr(tp, offset);
13016
13017         if (tg3_nvram_read(tp, offset, &val))
13018                 return;
13019
13020         if ((val & 0xfc000000) == 0x0c000000) {
13021                 if (tg3_nvram_read(tp, offset + 4, &val))
13022                         return;
13023
13024                 if (val == 0)
13025                         newver = true;
13026         }
13027
13028         dst_off = strlen(tp->fw_ver);
13029
13030         if (newver) {
13031                 if (TG3_VER_SIZE - dst_off < 16 ||
13032                     tg3_nvram_read(tp, offset + 8, &ver_offset))
13033                         return;
13034
13035                 offset = offset + ver_offset - start;
13036                 for (i = 0; i < 16; i += 4) {
13037                         __be32 v;
13038                         if (tg3_nvram_read_be32(tp, offset + i, &v))
13039                                 return;
13040
13041                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
13042                 }
13043         } else {
13044                 u32 major, minor;
13045
13046                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13047                         return;
13048
13049                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13050                         TG3_NVM_BCVER_MAJSFT;
13051                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
13052                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13053                          "v%d.%02d", major, minor);
13054         }
13055 }
13056
13057 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13058 {
13059         u32 val, major, minor;
13060
13061         /* Use native endian representation */
13062         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13063                 return;
13064
13065         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13066                 TG3_NVM_HWSB_CFG1_MAJSFT;
13067         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13068                 TG3_NVM_HWSB_CFG1_MINSFT;
13069
13070         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13071 }
13072
13073 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13074 {
13075         u32 offset, major, minor, build;
13076
13077         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13078
13079         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13080                 return;
13081
13082         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13083         case TG3_EEPROM_SB_REVISION_0:
13084                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13085                 break;
13086         case TG3_EEPROM_SB_REVISION_2:
13087                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13088                 break;
13089         case TG3_EEPROM_SB_REVISION_3:
13090                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13091                 break;
13092         case TG3_EEPROM_SB_REVISION_4:
13093                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13094                 break;
13095         case TG3_EEPROM_SB_REVISION_5:
13096                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13097                 break;
13098         case TG3_EEPROM_SB_REVISION_6:
13099                 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13100                 break;
13101         default:
13102                 return;
13103         }
13104
13105         if (tg3_nvram_read(tp, offset, &val))
13106                 return;
13107
13108         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13109                 TG3_EEPROM_SB_EDH_BLD_SHFT;
13110         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13111                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13112         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
13113
13114         if (minor > 99 || build > 26)
13115                 return;
13116
13117         offset = strlen(tp->fw_ver);
13118         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13119                  " v%d.%02d", major, minor);
13120
13121         if (build > 0) {
13122                 offset = strlen(tp->fw_ver);
13123                 if (offset < TG3_VER_SIZE - 1)
13124                         tp->fw_ver[offset] = 'a' + build - 1;
13125         }
13126 }
13127
13128 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13129 {
13130         u32 val, offset, start;
13131         int i, vlen;
13132
13133         for (offset = TG3_NVM_DIR_START;
13134              offset < TG3_NVM_DIR_END;
13135              offset += TG3_NVM_DIRENT_SIZE) {
13136                 if (tg3_nvram_read(tp, offset, &val))
13137                         return;
13138
13139                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13140                         break;
13141         }
13142
13143         if (offset == TG3_NVM_DIR_END)
13144                 return;
13145
13146         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
13147                 start = 0x08000000;
13148         else if (tg3_nvram_read(tp, offset - 4, &start))
13149                 return;
13150
13151         if (tg3_nvram_read(tp, offset + 4, &offset) ||
13152             !tg3_fw_img_is_valid(tp, offset) ||
13153             tg3_nvram_read(tp, offset + 8, &val))
13154                 return;
13155
13156         offset += val - start;
13157
13158         vlen = strlen(tp->fw_ver);
13159
13160         tp->fw_ver[vlen++] = ',';
13161         tp->fw_ver[vlen++] = ' ';
13162
13163         for (i = 0; i < 4; i++) {
13164                 __be32 v;
13165                 if (tg3_nvram_read_be32(tp, offset, &v))
13166                         return;
13167
13168                 offset += sizeof(v);
13169
13170                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13171                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13172                         break;
13173                 }
13174
13175                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13176                 vlen += sizeof(v);
13177         }
13178 }
13179
13180 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13181 {
13182         int vlen;
13183         u32 apedata;
13184         char *fwtype;
13185
13186         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
13187             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
13188                 return;
13189
13190         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13191         if (apedata != APE_SEG_SIG_MAGIC)
13192                 return;
13193
13194         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13195         if (!(apedata & APE_FW_STATUS_READY))
13196                 return;
13197
13198         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13199
13200         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13201                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
13202                 fwtype = "NCSI";
13203         } else {
13204                 fwtype = "DASH";
13205         }
13206
13207         vlen = strlen(tp->fw_ver);
13208
13209         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13210                  fwtype,
13211                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13212                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13213                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13214                  (apedata & APE_FW_VERSION_BLDMSK));
13215 }
13216
13217 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13218 {
13219         u32 val;
13220         bool vpd_vers = false;
13221
13222         if (tp->fw_ver[0] != 0)
13223                 vpd_vers = true;
13224
13225         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
13226                 strcat(tp->fw_ver, "sb");
13227                 return;
13228         }
13229
13230         if (tg3_nvram_read(tp, 0, &val))
13231                 return;
13232
13233         if (val == TG3_EEPROM_MAGIC)
13234                 tg3_read_bc_ver(tp);
13235         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13236                 tg3_read_sb_ver(tp, val);
13237         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13238                 tg3_read_hwsb_ver(tp);
13239         else
13240                 return;
13241
13242         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
13243              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13244                 goto done;
13245
13246         tg3_read_mgmtfw_ver(tp);
13247
13248 done:
13249         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13250 }
13251
13252 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13253
13254 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13255 {
13256         if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
13257                 return TG3_RX_RET_MAX_SIZE_5717;
13258         else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13259                  !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13260                 return TG3_RX_RET_MAX_SIZE_5700;
13261         else
13262                 return TG3_RX_RET_MAX_SIZE_5705;
13263 }
13264
13265 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13266         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13267         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13268         { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13269         { },
13270 };
13271
13272 static int __devinit tg3_get_invariants(struct tg3 *tp)
13273 {
13274         u32 misc_ctrl_reg;
13275         u32 pci_state_reg, grc_misc_cfg;
13276         u32 val;
13277         u16 pci_cmd;
13278         int err;
13279
13280         /* Force memory write invalidate off.  If we leave it on,
13281          * then on 5700_BX chips we have to enable a workaround.
13282          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13283          * to match the cacheline size.  The Broadcom driver have this
13284          * workaround but turns MWI off all the times so never uses
13285          * it.  This seems to suggest that the workaround is insufficient.
13286          */
13287         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13288         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13289         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13290
13291         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13292          * has the register indirect write enable bit set before
13293          * we try to access any of the MMIO registers.  It is also
13294          * critical that the PCI-X hw workaround situation is decided
13295          * before that as well.
13296          */
13297         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13298                               &misc_ctrl_reg);
13299
13300         tp->pci_chip_rev_id = (misc_ctrl_reg >>
13301                                MISC_HOST_CTRL_CHIPREV_SHIFT);
13302         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13303                 u32 prod_id_asic_rev;
13304
13305                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13306                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13307                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13308                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
13309                         pci_read_config_dword(tp->pdev,
13310                                               TG3PCI_GEN2_PRODID_ASICREV,
13311                                               &prod_id_asic_rev);
13312                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13313                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13314                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13315                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13316                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13317                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13318                         pci_read_config_dword(tp->pdev,
13319                                               TG3PCI_GEN15_PRODID_ASICREV,
13320                                               &prod_id_asic_rev);
13321                 else
13322                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13323                                               &prod_id_asic_rev);
13324
13325                 tp->pci_chip_rev_id = prod_id_asic_rev;
13326         }
13327
13328         /* Wrong chip ID in 5752 A0. This code can be removed later
13329          * as A0 is not in production.
13330          */
13331         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13332                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13333
13334         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13335          * we need to disable memory and use config. cycles
13336          * only to access all registers. The 5702/03 chips
13337          * can mistakenly decode the special cycles from the
13338          * ICH chipsets as memory write cycles, causing corruption
13339          * of register and memory space. Only certain ICH bridges
13340          * will drive special cycles with non-zero data during the
13341          * address phase which can fall within the 5703's address
13342          * range. This is not an ICH bug as the PCI spec allows
13343          * non-zero address during special cycles. However, only
13344          * these ICH bridges are known to drive non-zero addresses
13345          * during special cycles.
13346          *
13347          * Since special cycles do not cross PCI bridges, we only
13348          * enable this workaround if the 5703 is on the secondary
13349          * bus of these ICH bridges.
13350          */
13351         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13352             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13353                 static struct tg3_dev_id {
13354                         u32     vendor;
13355                         u32     device;
13356                         u32     rev;
13357                 } ich_chipsets[] = {
13358                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13359                           PCI_ANY_ID },
13360                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13361                           PCI_ANY_ID },
13362                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13363                           0xa },
13364                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13365                           PCI_ANY_ID },
13366                         { },
13367                 };
13368                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13369                 struct pci_dev *bridge = NULL;
13370
13371                 while (pci_id->vendor != 0) {
13372                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
13373                                                 bridge);
13374                         if (!bridge) {
13375                                 pci_id++;
13376                                 continue;
13377                         }
13378                         if (pci_id->rev != PCI_ANY_ID) {
13379                                 if (bridge->revision > pci_id->rev)
13380                                         continue;
13381                         }
13382                         if (bridge->subordinate &&
13383                             (bridge->subordinate->number ==
13384                              tp->pdev->bus->number)) {
13385
13386                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13387                                 pci_dev_put(bridge);
13388                                 break;
13389                         }
13390                 }
13391         }
13392
13393         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13394                 static struct tg3_dev_id {
13395                         u32     vendor;
13396                         u32     device;
13397                 } bridge_chipsets[] = {
13398                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13399                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13400                         { },
13401                 };
13402                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13403                 struct pci_dev *bridge = NULL;
13404
13405                 while (pci_id->vendor != 0) {
13406                         bridge = pci_get_device(pci_id->vendor,
13407                                                 pci_id->device,
13408                                                 bridge);
13409                         if (!bridge) {
13410                                 pci_id++;
13411                                 continue;
13412                         }
13413                         if (bridge->subordinate &&
13414                             (bridge->subordinate->number <=
13415                              tp->pdev->bus->number) &&
13416                             (bridge->subordinate->subordinate >=
13417                              tp->pdev->bus->number)) {
13418                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13419                                 pci_dev_put(bridge);
13420                                 break;
13421                         }
13422                 }
13423         }
13424
13425         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13426          * DMA addresses > 40-bit. This bridge may have other additional
13427          * 57xx devices behind it in some 4-port NIC designs for example.
13428          * Any tg3 device found behind the bridge will also need the 40-bit
13429          * DMA workaround.
13430          */
13431         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13432             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13433                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13434                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13435                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13436         } else {
13437                 struct pci_dev *bridge = NULL;
13438
13439                 do {
13440                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13441                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13442                                                 bridge);
13443                         if (bridge && bridge->subordinate &&
13444                             (bridge->subordinate->number <=
13445                              tp->pdev->bus->number) &&
13446                             (bridge->subordinate->subordinate >=
13447                              tp->pdev->bus->number)) {
13448                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13449                                 pci_dev_put(bridge);
13450                                 break;
13451                         }
13452                 } while (bridge);
13453         }
13454
13455         /* Initialize misc host control in PCI block. */
13456         tp->misc_host_ctrl |= (misc_ctrl_reg &
13457                                MISC_HOST_CTRL_CHIPREV);
13458         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13459                                tp->misc_host_ctrl);
13460
13461         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13462             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13463             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13464             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13465                 tp->pdev_peer = tg3_find_peer(tp);
13466
13467         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13468             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13469             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13470                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13471
13472         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
13473             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13474                 tp->tg3_flags3 |= TG3_FLG3_57765_PLUS;
13475
13476         /* Intentionally exclude ASIC_REV_5906 */
13477         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13478             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13479             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13480             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13481             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13482             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13483             (tp->tg3_flags3 & TG3_FLG3_57765_PLUS))
13484                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13485
13486         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13487             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13488             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13489             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13490             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13491                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13492
13493         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13494             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13495                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13496
13497         /* 5700 B0 chips do not support checksumming correctly due
13498          * to hardware bugs.
13499          */
13500         if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
13501                 u32 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
13502
13503                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13504                         features |= NETIF_F_IPV6_CSUM;
13505                 tp->dev->features |= features;
13506                 tp->dev->hw_features |= features;
13507                 tp->dev->vlan_features |= features;
13508         }
13509
13510         /* Determine TSO capabilities */
13511         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13512                 ; /* Do nothing. HW bug. */
13513         else if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
13514                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13515         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13516                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13517                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13518         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13519                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13520                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13521                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13522                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13523         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13524                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13525                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13526                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13527                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13528                         tp->fw_needed = FIRMWARE_TG3TSO5;
13529                 else
13530                         tp->fw_needed = FIRMWARE_TG3TSO;
13531         }
13532
13533         tp->irq_max = 1;
13534
13535         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13536                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13537                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13538                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13539                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13540                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13541                      tp->pdev_peer == tp->pdev))
13542                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13543
13544                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13545                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13546                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13547                 }
13548
13549                 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
13550                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13551                         tp->irq_max = TG3_IRQ_MAX_VECS;
13552                 }
13553         }
13554
13555         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13556             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13557             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13558                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13559         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13560                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13561                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13562         }
13563
13564         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13565                 tp->tg3_flags3 |= TG3_FLG3_LRG_PROD_RING_CAP;
13566
13567         if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
13568             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
13569                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13570
13571         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13572             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13573             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13574                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13575
13576         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13577                               &pci_state_reg);
13578
13579         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13580         if (tp->pcie_cap != 0) {
13581                 u16 lnkctl;
13582
13583                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13584
13585                 tp->pcie_readrq = 4096;
13586                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13587                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13588                         tp->pcie_readrq = 2048;
13589
13590                 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
13591
13592                 pci_read_config_word(tp->pdev,
13593                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13594                                      &lnkctl);
13595                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13596                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13597                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13598                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13599                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13600                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13601                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13602                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13603                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13604                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13605                 }
13606         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13607                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13608         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13609                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13610                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13611                 if (!tp->pcix_cap) {
13612                         dev_err(&tp->pdev->dev,
13613                                 "Cannot find PCI-X capability, aborting\n");
13614                         return -EIO;
13615                 }
13616
13617                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13618                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13619         }
13620
13621         /* If we have an AMD 762 or VIA K8T800 chipset, write
13622          * reordering to the mailbox registers done by the host
13623          * controller can cause major troubles.  We read back from
13624          * every mailbox register write to force the writes to be
13625          * posted to the chip in order.
13626          */
13627         if (pci_dev_present(tg3_write_reorder_chipsets) &&
13628             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13629                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13630
13631         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13632                              &tp->pci_cacheline_sz);
13633         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13634                              &tp->pci_lat_timer);
13635         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13636             tp->pci_lat_timer < 64) {
13637                 tp->pci_lat_timer = 64;
13638                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13639                                       tp->pci_lat_timer);
13640         }
13641
13642         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13643                 /* 5700 BX chips need to have their TX producer index
13644                  * mailboxes written twice to workaround a bug.
13645                  */
13646                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13647
13648                 /* If we are in PCI-X mode, enable register write workaround.
13649                  *
13650                  * The workaround is to use indirect register accesses
13651                  * for all chip writes not to mailbox registers.
13652                  */
13653                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13654                         u32 pm_reg;
13655
13656                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13657
13658                         /* The chip can have it's power management PCI config
13659                          * space registers clobbered due to this bug.
13660                          * So explicitly force the chip into D0 here.
13661                          */
13662                         pci_read_config_dword(tp->pdev,
13663                                               tp->pm_cap + PCI_PM_CTRL,
13664                                               &pm_reg);
13665                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13666                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13667                         pci_write_config_dword(tp->pdev,
13668                                                tp->pm_cap + PCI_PM_CTRL,
13669                                                pm_reg);
13670
13671                         /* Also, force SERR#/PERR# in PCI command. */
13672                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13673                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13674                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13675                 }
13676         }
13677
13678         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13679                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13680         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13681                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13682
13683         /* Chip-specific fixup from Broadcom driver */
13684         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13685             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13686                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13687                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13688         }
13689
13690         /* Default fast path register access methods */
13691         tp->read32 = tg3_read32;
13692         tp->write32 = tg3_write32;
13693         tp->read32_mbox = tg3_read32;
13694         tp->write32_mbox = tg3_write32;
13695         tp->write32_tx_mbox = tg3_write32;
13696         tp->write32_rx_mbox = tg3_write32;
13697
13698         /* Various workaround register access methods */
13699         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13700                 tp->write32 = tg3_write_indirect_reg32;
13701         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13702                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13703                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13704                 /*
13705                  * Back to back register writes can cause problems on these
13706                  * chips, the workaround is to read back all reg writes
13707                  * except those to mailbox regs.
13708                  *
13709                  * See tg3_write_indirect_reg32().
13710                  */
13711                 tp->write32 = tg3_write_flush_reg32;
13712         }
13713
13714         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13715             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13716                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13717                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13718                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13719         }
13720
13721         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13722                 tp->read32 = tg3_read_indirect_reg32;
13723                 tp->write32 = tg3_write_indirect_reg32;
13724                 tp->read32_mbox = tg3_read_indirect_mbox;
13725                 tp->write32_mbox = tg3_write_indirect_mbox;
13726                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13727                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13728
13729                 iounmap(tp->regs);
13730                 tp->regs = NULL;
13731
13732                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13733                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13734                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13735         }
13736         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13737                 tp->read32_mbox = tg3_read32_mbox_5906;
13738                 tp->write32_mbox = tg3_write32_mbox_5906;
13739                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13740                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13741         }
13742
13743         if (tp->write32 == tg3_write_indirect_reg32 ||
13744             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13745              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13746               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13747                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13748
13749         /* Get eeprom hw config before calling tg3_set_power_state().
13750          * In particular, the TG3_FLG2_IS_NIC flag must be
13751          * determined before calling tg3_set_power_state() so that
13752          * we know whether or not to switch out of Vaux power.
13753          * When the flag is set, it means that GPIO1 is used for eeprom
13754          * write protect and also implies that it is a LOM where GPIOs
13755          * are not used to switch power.
13756          */
13757         tg3_get_eeprom_hw_cfg(tp);
13758
13759         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13760                 /* Allow reads and writes to the
13761                  * APE register and memory space.
13762                  */
13763                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13764                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13765                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13766                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13767                                        pci_state_reg);
13768         }
13769
13770         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13771             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13772             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13773             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13774             (tp->tg3_flags3 & TG3_FLG3_57765_PLUS))
13775                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13776
13777         /* Set up tp->grc_local_ctrl before calling tg_power_up().
13778          * GPIO1 driven high will bring 5700's external PHY out of reset.
13779          * It is also used as eeprom write protect on LOMs.
13780          */
13781         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13782         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13783             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13784                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13785                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13786         /* Unused GPIO3 must be driven as output on 5752 because there
13787          * are no pull-up resistors on unused GPIO pins.
13788          */
13789         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13790                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13791
13792         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13793             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13794             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13795                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13796
13797         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13798             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13799                 /* Turn off the debug UART. */
13800                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13801                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13802                         /* Keep VMain power. */
13803                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13804                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13805         }
13806
13807         /* Force the chip into D0. */
13808         err = tg3_power_up(tp);
13809         if (err) {
13810                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13811                 return err;
13812         }
13813
13814         /* Derive initial jumbo mode from MTU assigned in
13815          * ether_setup() via the alloc_etherdev() call
13816          */
13817         if (tp->dev->mtu > ETH_DATA_LEN &&
13818             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13819                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13820
13821         /* Determine WakeOnLan speed to use. */
13822         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13823             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13824             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13825             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13826                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13827         } else {
13828                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13829         }
13830
13831         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13832                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13833
13834         /* A few boards don't want Ethernet@WireSpeed phy feature */
13835         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13836             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13837              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13838              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13839             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13840             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13841                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13842
13843         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13844             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13845                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13846         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13847                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13848
13849         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13850             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13851             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13852             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13853             !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
13854                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13855                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13856                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13857                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13858                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13859                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13860                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13861                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13862                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13863                 } else
13864                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13865         }
13866
13867         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13868             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13869                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13870                 if (tp->phy_otp == 0)
13871                         tp->phy_otp = TG3_OTP_DEFAULT;
13872         }
13873
13874         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13875                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13876         else
13877                 tp->mi_mode = MAC_MI_MODE_BASE;
13878
13879         tp->coalesce_mode = 0;
13880         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13881             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13882                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13883
13884         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13885             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13886                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13887
13888         err = tg3_mdio_init(tp);
13889         if (err)
13890                 return err;
13891
13892         /* Initialize data/descriptor byte/word swapping. */
13893         val = tr32(GRC_MODE);
13894         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13895                 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
13896                         GRC_MODE_WORD_SWAP_B2HRX_DATA |
13897                         GRC_MODE_B2HRX_ENABLE |
13898                         GRC_MODE_HTX2B_ENABLE |
13899                         GRC_MODE_HOST_STACKUP);
13900         else
13901                 val &= GRC_MODE_HOST_STACKUP;
13902
13903         tw32(GRC_MODE, val | tp->grc_mode);
13904
13905         tg3_switch_clocks(tp);
13906
13907         /* Clear this out for sanity. */
13908         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13909
13910         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13911                               &pci_state_reg);
13912         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13913             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13914                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13915
13916                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13917                     chiprevid == CHIPREV_ID_5701_B0 ||
13918                     chiprevid == CHIPREV_ID_5701_B2 ||
13919                     chiprevid == CHIPREV_ID_5701_B5) {
13920                         void __iomem *sram_base;
13921
13922                         /* Write some dummy words into the SRAM status block
13923                          * area, see if it reads back correctly.  If the return
13924                          * value is bad, force enable the PCIX workaround.
13925                          */
13926                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13927
13928                         writel(0x00000000, sram_base);
13929                         writel(0x00000000, sram_base + 4);
13930                         writel(0xffffffff, sram_base + 4);
13931                         if (readl(sram_base) != 0x00000000)
13932                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13933                 }
13934         }
13935
13936         udelay(50);
13937         tg3_nvram_init(tp);
13938
13939         grc_misc_cfg = tr32(GRC_MISC_CFG);
13940         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13941
13942         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13943             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13944              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13945                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13946
13947         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13948             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13949                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13950         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13951                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13952                                       HOSTCC_MODE_CLRTICK_TXBD);
13953
13954                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13955                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13956                                        tp->misc_host_ctrl);
13957         }
13958
13959         /* Preserve the APE MAC_MODE bits */
13960         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13961                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13962         else
13963                 tp->mac_mode = TG3_DEF_MAC_MODE;
13964
13965         /* these are limited to 10/100 only */
13966         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13967              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13968             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13969              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13970              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13971               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13972               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13973             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13974              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13975               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13976               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13977             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13978             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13979             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13980             (tp->phy_flags & TG3_PHYFLG_IS_FET))
13981                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13982
13983         err = tg3_phy_probe(tp);
13984         if (err) {
13985                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13986                 /* ... but do not return immediately ... */
13987                 tg3_mdio_fini(tp);
13988         }
13989
13990         tg3_read_vpd(tp);
13991         tg3_read_fw_ver(tp);
13992
13993         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13994                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13995         } else {
13996                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13997                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13998                 else
13999                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14000         }
14001
14002         /* 5700 {AX,BX} chips have a broken status block link
14003          * change bit implementation, so we must use the
14004          * status register in those cases.
14005          */
14006         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14007                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
14008         else
14009                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
14010
14011         /* The led_ctrl is set during tg3_phy_probe, here we might
14012          * have to force the link status polling mechanism based
14013          * upon subsystem IDs.
14014          */
14015         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
14016             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14017             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14018                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14019                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
14020         }
14021
14022         /* For all SERDES we poll the MAC status register. */
14023         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14024                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
14025         else
14026                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
14027
14028         tp->rx_offset = NET_IP_ALIGN;
14029         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
14030         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14031             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
14032                 tp->rx_offset = 0;
14033 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14034                 tp->rx_copy_thresh = ~(u16)0;
14035 #endif
14036         }
14037
14038         tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14039         tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
14040         tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14041
14042         tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
14043
14044         /* Increment the rx prod index on the rx std ring by at most
14045          * 8 for these chips to workaround hw errata.
14046          */
14047         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14048             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14049             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14050                 tp->rx_std_max_post = 8;
14051
14052         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
14053                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14054                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
14055
14056         return err;
14057 }
14058
14059 #ifdef CONFIG_SPARC
14060 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14061 {
14062         struct net_device *dev = tp->dev;
14063         struct pci_dev *pdev = tp->pdev;
14064         struct device_node *dp = pci_device_to_OF_node(pdev);
14065         const unsigned char *addr;
14066         int len;
14067
14068         addr = of_get_property(dp, "local-mac-address", &len);
14069         if (addr && len == 6) {
14070                 memcpy(dev->dev_addr, addr, 6);
14071                 memcpy(dev->perm_addr, dev->dev_addr, 6);
14072                 return 0;
14073         }
14074         return -ENODEV;
14075 }
14076
14077 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14078 {
14079         struct net_device *dev = tp->dev;
14080
14081         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
14082         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
14083         return 0;
14084 }
14085 #endif
14086
14087 static int __devinit tg3_get_device_address(struct tg3 *tp)
14088 {
14089         struct net_device *dev = tp->dev;
14090         u32 hi, lo, mac_offset;
14091         int addr_ok = 0;
14092
14093 #ifdef CONFIG_SPARC
14094         if (!tg3_get_macaddr_sparc(tp))
14095                 return 0;
14096 #endif
14097
14098         mac_offset = 0x7c;
14099         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
14100             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
14101                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14102                         mac_offset = 0xcc;
14103                 if (tg3_nvram_lock(tp))
14104                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14105                 else
14106                         tg3_nvram_unlock(tp);
14107         } else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14108                 if (PCI_FUNC(tp->pdev->devfn) & 1)
14109                         mac_offset = 0xcc;
14110                 if (PCI_FUNC(tp->pdev->devfn) > 1)
14111                         mac_offset += 0x18c;
14112         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14113                 mac_offset = 0x10;
14114
14115         /* First try to get it from MAC address mailbox. */
14116         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14117         if ((hi >> 16) == 0x484b) {
14118                 dev->dev_addr[0] = (hi >>  8) & 0xff;
14119                 dev->dev_addr[1] = (hi >>  0) & 0xff;
14120
14121                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14122                 dev->dev_addr[2] = (lo >> 24) & 0xff;
14123                 dev->dev_addr[3] = (lo >> 16) & 0xff;
14124                 dev->dev_addr[4] = (lo >>  8) & 0xff;
14125                 dev->dev_addr[5] = (lo >>  0) & 0xff;
14126
14127                 /* Some old bootcode may report a 0 MAC address in SRAM */
14128                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14129         }
14130         if (!addr_ok) {
14131                 /* Next, try NVRAM. */
14132                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
14133                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14134                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14135                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14136                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
14137                 }
14138                 /* Finally just fetch it out of the MAC control regs. */
14139                 else {
14140                         hi = tr32(MAC_ADDR_0_HIGH);
14141                         lo = tr32(MAC_ADDR_0_LOW);
14142
14143                         dev->dev_addr[5] = lo & 0xff;
14144                         dev->dev_addr[4] = (lo >> 8) & 0xff;
14145                         dev->dev_addr[3] = (lo >> 16) & 0xff;
14146                         dev->dev_addr[2] = (lo >> 24) & 0xff;
14147                         dev->dev_addr[1] = hi & 0xff;
14148                         dev->dev_addr[0] = (hi >> 8) & 0xff;
14149                 }
14150         }
14151
14152         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14153 #ifdef CONFIG_SPARC
14154                 if (!tg3_get_default_macaddr_sparc(tp))
14155                         return 0;
14156 #endif
14157                 return -EINVAL;
14158         }
14159         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14160         return 0;
14161 }
14162
14163 #define BOUNDARY_SINGLE_CACHELINE       1
14164 #define BOUNDARY_MULTI_CACHELINE        2
14165
14166 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14167 {
14168         int cacheline_size;
14169         u8 byte;
14170         int goal;
14171
14172         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14173         if (byte == 0)
14174                 cacheline_size = 1024;
14175         else
14176                 cacheline_size = (int) byte * 4;
14177
14178         /* On 5703 and later chips, the boundary bits have no
14179          * effect.
14180          */
14181         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14182             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14183             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
14184                 goto out;
14185
14186 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14187         goal = BOUNDARY_MULTI_CACHELINE;
14188 #else
14189 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14190         goal = BOUNDARY_SINGLE_CACHELINE;
14191 #else
14192         goal = 0;
14193 #endif
14194 #endif
14195
14196         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
14197                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14198                 goto out;
14199         }
14200
14201         if (!goal)
14202                 goto out;
14203
14204         /* PCI controllers on most RISC systems tend to disconnect
14205          * when a device tries to burst across a cache-line boundary.
14206          * Therefore, letting tg3 do so just wastes PCI bandwidth.
14207          *
14208          * Unfortunately, for PCI-E there are only limited
14209          * write-side controls for this, and thus for reads
14210          * we will still get the disconnects.  We'll also waste
14211          * these PCI cycles for both read and write for chips
14212          * other than 5700 and 5701 which do not implement the
14213          * boundary bits.
14214          */
14215         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
14216             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
14217                 switch (cacheline_size) {
14218                 case 16:
14219                 case 32:
14220                 case 64:
14221                 case 128:
14222                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14223                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14224                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14225                         } else {
14226                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14227                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14228                         }
14229                         break;
14230
14231                 case 256:
14232                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14233                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14234                         break;
14235
14236                 default:
14237                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14238                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14239                         break;
14240                 }
14241         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14242                 switch (cacheline_size) {
14243                 case 16:
14244                 case 32:
14245                 case 64:
14246                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14247                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14248                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14249                                 break;
14250                         }
14251                         /* fallthrough */
14252                 case 128:
14253                 default:
14254                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14255                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14256                         break;
14257                 }
14258         } else {
14259                 switch (cacheline_size) {
14260                 case 16:
14261                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14262                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14263                                         DMA_RWCTRL_WRITE_BNDRY_16);
14264                                 break;
14265                         }
14266                         /* fallthrough */
14267                 case 32:
14268                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14269                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14270                                         DMA_RWCTRL_WRITE_BNDRY_32);
14271                                 break;
14272                         }
14273                         /* fallthrough */
14274                 case 64:
14275                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14276                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14277                                         DMA_RWCTRL_WRITE_BNDRY_64);
14278                                 break;
14279                         }
14280                         /* fallthrough */
14281                 case 128:
14282                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14283                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14284                                         DMA_RWCTRL_WRITE_BNDRY_128);
14285                                 break;
14286                         }
14287                         /* fallthrough */
14288                 case 256:
14289                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
14290                                 DMA_RWCTRL_WRITE_BNDRY_256);
14291                         break;
14292                 case 512:
14293                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
14294                                 DMA_RWCTRL_WRITE_BNDRY_512);
14295                         break;
14296                 case 1024:
14297                 default:
14298                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14299                                 DMA_RWCTRL_WRITE_BNDRY_1024);
14300                         break;
14301                 }
14302         }
14303
14304 out:
14305         return val;
14306 }
14307
14308 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14309 {
14310         struct tg3_internal_buffer_desc test_desc;
14311         u32 sram_dma_descs;
14312         int i, ret;
14313
14314         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14315
14316         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14317         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14318         tw32(RDMAC_STATUS, 0);
14319         tw32(WDMAC_STATUS, 0);
14320
14321         tw32(BUFMGR_MODE, 0);
14322         tw32(FTQ_RESET, 0);
14323
14324         test_desc.addr_hi = ((u64) buf_dma) >> 32;
14325         test_desc.addr_lo = buf_dma & 0xffffffff;
14326         test_desc.nic_mbuf = 0x00002100;
14327         test_desc.len = size;
14328
14329         /*
14330          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14331          * the *second* time the tg3 driver was getting loaded after an
14332          * initial scan.
14333          *
14334          * Broadcom tells me:
14335          *   ...the DMA engine is connected to the GRC block and a DMA
14336          *   reset may affect the GRC block in some unpredictable way...
14337          *   The behavior of resets to individual blocks has not been tested.
14338          *
14339          * Broadcom noted the GRC reset will also reset all sub-components.
14340          */
14341         if (to_device) {
14342                 test_desc.cqid_sqid = (13 << 8) | 2;
14343
14344                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14345                 udelay(40);
14346         } else {
14347                 test_desc.cqid_sqid = (16 << 8) | 7;
14348
14349                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14350                 udelay(40);
14351         }
14352         test_desc.flags = 0x00000005;
14353
14354         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14355                 u32 val;
14356
14357                 val = *(((u32 *)&test_desc) + i);
14358                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14359                                        sram_dma_descs + (i * sizeof(u32)));
14360                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14361         }
14362         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14363
14364         if (to_device)
14365                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14366         else
14367                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14368
14369         ret = -ENODEV;
14370         for (i = 0; i < 40; i++) {
14371                 u32 val;
14372
14373                 if (to_device)
14374                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14375                 else
14376                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14377                 if ((val & 0xffff) == sram_dma_descs) {
14378                         ret = 0;
14379                         break;
14380                 }
14381
14382                 udelay(100);
14383         }
14384
14385         return ret;
14386 }
14387
14388 #define TEST_BUFFER_SIZE        0x2000
14389
14390 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
14391         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14392         { },
14393 };
14394
14395 static int __devinit tg3_test_dma(struct tg3 *tp)
14396 {
14397         dma_addr_t buf_dma;
14398         u32 *buf, saved_dma_rwctrl;
14399         int ret = 0;
14400
14401         buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14402                                  &buf_dma, GFP_KERNEL);
14403         if (!buf) {
14404                 ret = -ENOMEM;
14405                 goto out_nofree;
14406         }
14407
14408         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14409                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14410
14411         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14412
14413         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
14414                 goto out;
14415
14416         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14417                 /* DMA read watermark not used on PCIE */
14418                 tp->dma_rwctrl |= 0x00180000;
14419         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14420                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14421                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14422                         tp->dma_rwctrl |= 0x003f0000;
14423                 else
14424                         tp->dma_rwctrl |= 0x003f000f;
14425         } else {
14426                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14427                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14428                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14429                         u32 read_water = 0x7;
14430
14431                         /* If the 5704 is behind the EPB bridge, we can
14432                          * do the less restrictive ONE_DMA workaround for
14433                          * better performance.
14434                          */
14435                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14436                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14437                                 tp->dma_rwctrl |= 0x8000;
14438                         else if (ccval == 0x6 || ccval == 0x7)
14439                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14440
14441                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14442                                 read_water = 4;
14443                         /* Set bit 23 to enable PCIX hw bug fix */
14444                         tp->dma_rwctrl |=
14445                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14446                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14447                                 (1 << 23);
14448                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14449                         /* 5780 always in PCIX mode */
14450                         tp->dma_rwctrl |= 0x00144000;
14451                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14452                         /* 5714 always in PCIX mode */
14453                         tp->dma_rwctrl |= 0x00148000;
14454                 } else {
14455                         tp->dma_rwctrl |= 0x001b000f;
14456                 }
14457         }
14458
14459         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14460             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14461                 tp->dma_rwctrl &= 0xfffffff0;
14462
14463         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14464             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14465                 /* Remove this if it causes problems for some boards. */
14466                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14467
14468                 /* On 5700/5701 chips, we need to set this bit.
14469                  * Otherwise the chip will issue cacheline transactions
14470                  * to streamable DMA memory with not all the byte
14471                  * enables turned on.  This is an error on several
14472                  * RISC PCI controllers, in particular sparc64.
14473                  *
14474                  * On 5703/5704 chips, this bit has been reassigned
14475                  * a different meaning.  In particular, it is used
14476                  * on those chips to enable a PCI-X workaround.
14477                  */
14478                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14479         }
14480
14481         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14482
14483 #if 0
14484         /* Unneeded, already done by tg3_get_invariants.  */
14485         tg3_switch_clocks(tp);
14486 #endif
14487
14488         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14489             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14490                 goto out;
14491
14492         /* It is best to perform DMA test with maximum write burst size
14493          * to expose the 5700/5701 write DMA bug.
14494          */
14495         saved_dma_rwctrl = tp->dma_rwctrl;
14496         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14497         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14498
14499         while (1) {
14500                 u32 *p = buf, i;
14501
14502                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14503                         p[i] = i;
14504
14505                 /* Send the buffer to the chip. */
14506                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14507                 if (ret) {
14508                         dev_err(&tp->pdev->dev,
14509                                 "%s: Buffer write failed. err = %d\n",
14510                                 __func__, ret);
14511                         break;
14512                 }
14513
14514 #if 0
14515                 /* validate data reached card RAM correctly. */
14516                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14517                         u32 val;
14518                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14519                         if (le32_to_cpu(val) != p[i]) {
14520                                 dev_err(&tp->pdev->dev,
14521                                         "%s: Buffer corrupted on device! "
14522                                         "(%d != %d)\n", __func__, val, i);
14523                                 /* ret = -ENODEV here? */
14524                         }
14525                         p[i] = 0;
14526                 }
14527 #endif
14528                 /* Now read it back. */
14529                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14530                 if (ret) {
14531                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14532                                 "err = %d\n", __func__, ret);
14533                         break;
14534                 }
14535
14536                 /* Verify it. */
14537                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14538                         if (p[i] == i)
14539                                 continue;
14540
14541                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14542                             DMA_RWCTRL_WRITE_BNDRY_16) {
14543                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14544                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14545                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14546                                 break;
14547                         } else {
14548                                 dev_err(&tp->pdev->dev,
14549                                         "%s: Buffer corrupted on read back! "
14550                                         "(%d != %d)\n", __func__, p[i], i);
14551                                 ret = -ENODEV;
14552                                 goto out;
14553                         }
14554                 }
14555
14556                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14557                         /* Success. */
14558                         ret = 0;
14559                         break;
14560                 }
14561         }
14562         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14563             DMA_RWCTRL_WRITE_BNDRY_16) {
14564
14565                 /* DMA test passed without adjusting DMA boundary,
14566                  * now look for chipsets that are known to expose the
14567                  * DMA bug without failing the test.
14568                  */
14569                 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
14570                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14571                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14572                 } else {
14573                         /* Safe to use the calculated DMA boundary. */
14574                         tp->dma_rwctrl = saved_dma_rwctrl;
14575                 }
14576
14577                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14578         }
14579
14580 out:
14581         dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
14582 out_nofree:
14583         return ret;
14584 }
14585
14586 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14587 {
14588         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
14589                 tp->bufmgr_config.mbuf_read_dma_low_water =
14590                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14591                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14592                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14593                 tp->bufmgr_config.mbuf_high_water =
14594                         DEFAULT_MB_HIGH_WATER_57765;
14595
14596                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14597                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14598                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14599                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14600                 tp->bufmgr_config.mbuf_high_water_jumbo =
14601                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14602         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14603                 tp->bufmgr_config.mbuf_read_dma_low_water =
14604                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14605                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14606                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14607                 tp->bufmgr_config.mbuf_high_water =
14608                         DEFAULT_MB_HIGH_WATER_5705;
14609                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14610                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14611                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14612                         tp->bufmgr_config.mbuf_high_water =
14613                                 DEFAULT_MB_HIGH_WATER_5906;
14614                 }
14615
14616                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14617                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14618                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14619                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14620                 tp->bufmgr_config.mbuf_high_water_jumbo =
14621                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14622         } else {
14623                 tp->bufmgr_config.mbuf_read_dma_low_water =
14624                         DEFAULT_MB_RDMA_LOW_WATER;
14625                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14626                         DEFAULT_MB_MACRX_LOW_WATER;
14627                 tp->bufmgr_config.mbuf_high_water =
14628                         DEFAULT_MB_HIGH_WATER;
14629
14630                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14631                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14632                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14633                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14634                 tp->bufmgr_config.mbuf_high_water_jumbo =
14635                         DEFAULT_MB_HIGH_WATER_JUMBO;
14636         }
14637
14638         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14639         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14640 }
14641
14642 static char * __devinit tg3_phy_string(struct tg3 *tp)
14643 {
14644         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14645         case TG3_PHY_ID_BCM5400:        return "5400";
14646         case TG3_PHY_ID_BCM5401:        return "5401";
14647         case TG3_PHY_ID_BCM5411:        return "5411";
14648         case TG3_PHY_ID_BCM5701:        return "5701";
14649         case TG3_PHY_ID_BCM5703:        return "5703";
14650         case TG3_PHY_ID_BCM5704:        return "5704";
14651         case TG3_PHY_ID_BCM5705:        return "5705";
14652         case TG3_PHY_ID_BCM5750:        return "5750";
14653         case TG3_PHY_ID_BCM5752:        return "5752";
14654         case TG3_PHY_ID_BCM5714:        return "5714";
14655         case TG3_PHY_ID_BCM5780:        return "5780";
14656         case TG3_PHY_ID_BCM5755:        return "5755";
14657         case TG3_PHY_ID_BCM5787:        return "5787";
14658         case TG3_PHY_ID_BCM5784:        return "5784";
14659         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14660         case TG3_PHY_ID_BCM5906:        return "5906";
14661         case TG3_PHY_ID_BCM5761:        return "5761";
14662         case TG3_PHY_ID_BCM5718C:       return "5718C";
14663         case TG3_PHY_ID_BCM5718S:       return "5718S";
14664         case TG3_PHY_ID_BCM57765:       return "57765";
14665         case TG3_PHY_ID_BCM5719C:       return "5719C";
14666         case TG3_PHY_ID_BCM5720C:       return "5720C";
14667         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14668         case 0:                 return "serdes";
14669         default:                return "unknown";
14670         }
14671 }
14672
14673 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14674 {
14675         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14676                 strcpy(str, "PCI Express");
14677                 return str;
14678         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14679                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14680
14681                 strcpy(str, "PCIX:");
14682
14683                 if ((clock_ctrl == 7) ||
14684                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14685                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14686                         strcat(str, "133MHz");
14687                 else if (clock_ctrl == 0)
14688                         strcat(str, "33MHz");
14689                 else if (clock_ctrl == 2)
14690                         strcat(str, "50MHz");
14691                 else if (clock_ctrl == 4)
14692                         strcat(str, "66MHz");
14693                 else if (clock_ctrl == 6)
14694                         strcat(str, "100MHz");
14695         } else {
14696                 strcpy(str, "PCI:");
14697                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14698                         strcat(str, "66MHz");
14699                 else
14700                         strcat(str, "33MHz");
14701         }
14702         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14703                 strcat(str, ":32-bit");
14704         else
14705                 strcat(str, ":64-bit");
14706         return str;
14707 }
14708
14709 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14710 {
14711         struct pci_dev *peer;
14712         unsigned int func, devnr = tp->pdev->devfn & ~7;
14713
14714         for (func = 0; func < 8; func++) {
14715                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14716                 if (peer && peer != tp->pdev)
14717                         break;
14718                 pci_dev_put(peer);
14719         }
14720         /* 5704 can be configured in single-port mode, set peer to
14721          * tp->pdev in that case.
14722          */
14723         if (!peer) {
14724                 peer = tp->pdev;
14725                 return peer;
14726         }
14727
14728         /*
14729          * We don't need to keep the refcount elevated; there's no way
14730          * to remove one half of this device without removing the other
14731          */
14732         pci_dev_put(peer);
14733
14734         return peer;
14735 }
14736
14737 static void __devinit tg3_init_coal(struct tg3 *tp)
14738 {
14739         struct ethtool_coalesce *ec = &tp->coal;
14740
14741         memset(ec, 0, sizeof(*ec));
14742         ec->cmd = ETHTOOL_GCOALESCE;
14743         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14744         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14745         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14746         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14747         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14748         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14749         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14750         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14751         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14752
14753         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14754                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14755                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14756                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14757                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14758                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14759         }
14760
14761         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14762                 ec->rx_coalesce_usecs_irq = 0;
14763                 ec->tx_coalesce_usecs_irq = 0;
14764                 ec->stats_block_coalesce_usecs = 0;
14765         }
14766 }
14767
14768 static const struct net_device_ops tg3_netdev_ops = {
14769         .ndo_open               = tg3_open,
14770         .ndo_stop               = tg3_close,
14771         .ndo_start_xmit         = tg3_start_xmit,
14772         .ndo_get_stats64        = tg3_get_stats64,
14773         .ndo_validate_addr      = eth_validate_addr,
14774         .ndo_set_multicast_list = tg3_set_rx_mode,
14775         .ndo_set_mac_address    = tg3_set_mac_addr,
14776         .ndo_do_ioctl           = tg3_ioctl,
14777         .ndo_tx_timeout         = tg3_tx_timeout,
14778         .ndo_change_mtu         = tg3_change_mtu,
14779         .ndo_fix_features       = tg3_fix_features,
14780 #ifdef CONFIG_NET_POLL_CONTROLLER
14781         .ndo_poll_controller    = tg3_poll_controller,
14782 #endif
14783 };
14784
14785 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14786         .ndo_open               = tg3_open,
14787         .ndo_stop               = tg3_close,
14788         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14789         .ndo_get_stats64        = tg3_get_stats64,
14790         .ndo_validate_addr      = eth_validate_addr,
14791         .ndo_set_multicast_list = tg3_set_rx_mode,
14792         .ndo_set_mac_address    = tg3_set_mac_addr,
14793         .ndo_do_ioctl           = tg3_ioctl,
14794         .ndo_tx_timeout         = tg3_tx_timeout,
14795         .ndo_change_mtu         = tg3_change_mtu,
14796 #ifdef CONFIG_NET_POLL_CONTROLLER
14797         .ndo_poll_controller    = tg3_poll_controller,
14798 #endif
14799 };
14800
14801 static int __devinit tg3_init_one(struct pci_dev *pdev,
14802                                   const struct pci_device_id *ent)
14803 {
14804         struct net_device *dev;
14805         struct tg3 *tp;
14806         int i, err, pm_cap;
14807         u32 sndmbx, rcvmbx, intmbx;
14808         char str[40];
14809         u64 dma_mask, persist_dma_mask;
14810         u32 hw_features = 0;
14811
14812         printk_once(KERN_INFO "%s\n", version);
14813
14814         err = pci_enable_device(pdev);
14815         if (err) {
14816                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14817                 return err;
14818         }
14819
14820         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14821         if (err) {
14822                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14823                 goto err_out_disable_pdev;
14824         }
14825
14826         pci_set_master(pdev);
14827
14828         /* Find power-management capability. */
14829         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14830         if (pm_cap == 0) {
14831                 dev_err(&pdev->dev,
14832                         "Cannot find Power Management capability, aborting\n");
14833                 err = -EIO;
14834                 goto err_out_free_res;
14835         }
14836
14837         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14838         if (!dev) {
14839                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14840                 err = -ENOMEM;
14841                 goto err_out_free_res;
14842         }
14843
14844         SET_NETDEV_DEV(dev, &pdev->dev);
14845
14846         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14847
14848         tp = netdev_priv(dev);
14849         tp->pdev = pdev;
14850         tp->dev = dev;
14851         tp->pm_cap = pm_cap;
14852         tp->rx_mode = TG3_DEF_RX_MODE;
14853         tp->tx_mode = TG3_DEF_TX_MODE;
14854
14855         if (tg3_debug > 0)
14856                 tp->msg_enable = tg3_debug;
14857         else
14858                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14859
14860         /* The word/byte swap controls here control register access byte
14861          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14862          * setting below.
14863          */
14864         tp->misc_host_ctrl =
14865                 MISC_HOST_CTRL_MASK_PCI_INT |
14866                 MISC_HOST_CTRL_WORD_SWAP |
14867                 MISC_HOST_CTRL_INDIR_ACCESS |
14868                 MISC_HOST_CTRL_PCISTATE_RW;
14869
14870         /* The NONFRM (non-frame) byte/word swap controls take effect
14871          * on descriptor entries, anything which isn't packet data.
14872          *
14873          * The StrongARM chips on the board (one for tx, one for rx)
14874          * are running in big-endian mode.
14875          */
14876         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14877                         GRC_MODE_WSWAP_NONFRM_DATA);
14878 #ifdef __BIG_ENDIAN
14879         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14880 #endif
14881         spin_lock_init(&tp->lock);
14882         spin_lock_init(&tp->indirect_lock);
14883         INIT_WORK(&tp->reset_task, tg3_reset_task);
14884
14885         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14886         if (!tp->regs) {
14887                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14888                 err = -ENOMEM;
14889                 goto err_out_free_dev;
14890         }
14891
14892         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14893         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14894
14895         dev->ethtool_ops = &tg3_ethtool_ops;
14896         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14897         dev->irq = pdev->irq;
14898
14899         err = tg3_get_invariants(tp);
14900         if (err) {
14901                 dev_err(&pdev->dev,
14902                         "Problem fetching invariants of chip, aborting\n");
14903                 goto err_out_iounmap;
14904         }
14905
14906         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14907             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
14908                 dev->netdev_ops = &tg3_netdev_ops;
14909         else
14910                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14911
14912
14913         /* The EPB bridge inside 5714, 5715, and 5780 and any
14914          * device behind the EPB cannot support DMA addresses > 40-bit.
14915          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14916          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14917          * do DMA address check in tg3_start_xmit().
14918          */
14919         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14920                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14921         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14922                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14923 #ifdef CONFIG_HIGHMEM
14924                 dma_mask = DMA_BIT_MASK(64);
14925 #endif
14926         } else
14927                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14928
14929         /* Configure DMA attributes. */
14930         if (dma_mask > DMA_BIT_MASK(32)) {
14931                 err = pci_set_dma_mask(pdev, dma_mask);
14932                 if (!err) {
14933                         dev->features |= NETIF_F_HIGHDMA;
14934                         err = pci_set_consistent_dma_mask(pdev,
14935                                                           persist_dma_mask);
14936                         if (err < 0) {
14937                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14938                                         "DMA for consistent allocations\n");
14939                                 goto err_out_iounmap;
14940                         }
14941                 }
14942         }
14943         if (err || dma_mask == DMA_BIT_MASK(32)) {
14944                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14945                 if (err) {
14946                         dev_err(&pdev->dev,
14947                                 "No usable DMA configuration, aborting\n");
14948                         goto err_out_iounmap;
14949                 }
14950         }
14951
14952         tg3_init_bufmgr_config(tp);
14953
14954         /* Selectively allow TSO based on operating conditions */
14955         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14956             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14957                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14958         else {
14959                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14960                 tp->fw_needed = NULL;
14961         }
14962
14963         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14964                 tp->fw_needed = FIRMWARE_TG3;
14965
14966         /* TSO is on by default on chips that support hardware TSO.
14967          * Firmware TSO on older chips gives lower performance, so it
14968          * is off by default, but can be enabled using ethtool.
14969          */
14970         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14971             (dev->features & NETIF_F_IP_CSUM))
14972                 hw_features |= NETIF_F_TSO;
14973         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14974             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14975                 if (dev->features & NETIF_F_IPV6_CSUM)
14976                         hw_features |= NETIF_F_TSO6;
14977                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14978                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14979                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14980                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14981                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14982                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14983                         hw_features |= NETIF_F_TSO_ECN;
14984         }
14985
14986         dev->hw_features |= hw_features;
14987         dev->features |= hw_features;
14988         dev->vlan_features |= hw_features;
14989
14990         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14991             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14992             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14993                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14994                 tp->rx_pending = 63;
14995         }
14996
14997         err = tg3_get_device_address(tp);
14998         if (err) {
14999                 dev_err(&pdev->dev,
15000                         "Could not obtain valid ethernet address, aborting\n");
15001                 goto err_out_iounmap;
15002         }
15003
15004         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
15005                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15006                 if (!tp->aperegs) {
15007                         dev_err(&pdev->dev,
15008                                 "Cannot map APE registers, aborting\n");
15009                         err = -ENOMEM;
15010                         goto err_out_iounmap;
15011                 }
15012
15013                 tg3_ape_lock_init(tp);
15014
15015                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
15016                         tg3_read_dash_ver(tp);
15017         }
15018
15019         /*
15020          * Reset chip in case UNDI or EFI driver did not shutdown
15021          * DMA self test will enable WDMAC and we'll see (spurious)
15022          * pending DMA on the PCI bus at that point.
15023          */
15024         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15025             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15026                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15027                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15028         }
15029
15030         err = tg3_test_dma(tp);
15031         if (err) {
15032                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
15033                 goto err_out_apeunmap;
15034         }
15035
15036         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15037         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15038         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
15039         for (i = 0; i < tp->irq_max; i++) {
15040                 struct tg3_napi *tnapi = &tp->napi[i];
15041
15042                 tnapi->tp = tp;
15043                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15044
15045                 tnapi->int_mbox = intmbx;
15046                 if (i < 4)
15047                         intmbx += 0x8;
15048                 else
15049                         intmbx += 0x4;
15050
15051                 tnapi->consmbox = rcvmbx;
15052                 tnapi->prodmbox = sndmbx;
15053
15054                 if (i)
15055                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
15056                 else
15057                         tnapi->coal_now = HOSTCC_MODE_NOW;
15058
15059                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
15060                         break;
15061
15062                 /*
15063                  * If we support MSIX, we'll be using RSS.  If we're using
15064                  * RSS, the first vector only handles link interrupts and the
15065                  * remaining vectors handle rx and tx interrupts.  Reuse the
15066                  * mailbox values for the next iteration.  The values we setup
15067                  * above are still useful for the single vectored mode.
15068                  */
15069                 if (!i)
15070                         continue;
15071
15072                 rcvmbx += 0x8;
15073
15074                 if (sndmbx & 0x4)
15075                         sndmbx -= 0x4;
15076                 else
15077                         sndmbx += 0xc;
15078         }
15079
15080         tg3_init_coal(tp);
15081
15082         pci_set_drvdata(pdev, dev);
15083
15084         err = register_netdev(dev);
15085         if (err) {
15086                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
15087                 goto err_out_apeunmap;
15088         }
15089
15090         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15091                     tp->board_part_number,
15092                     tp->pci_chip_rev_id,
15093                     tg3_bus_string(tp, str),
15094                     dev->dev_addr);
15095
15096         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
15097                 struct phy_device *phydev;
15098                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
15099                 netdev_info(dev,
15100                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15101                             phydev->drv->name, dev_name(&phydev->dev));
15102         } else {
15103                 char *ethtype;
15104
15105                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15106                         ethtype = "10/100Base-TX";
15107                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15108                         ethtype = "1000Base-SX";
15109                 else
15110                         ethtype = "10/100/1000Base-T";
15111
15112                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
15113                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
15114                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
15115         }
15116
15117         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15118                     (dev->features & NETIF_F_RXCSUM) != 0,
15119                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
15120                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15121                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
15122                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
15123         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15124                     tp->dma_rwctrl,
15125                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15126                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15127
15128         return 0;
15129
15130 err_out_apeunmap:
15131         if (tp->aperegs) {
15132                 iounmap(tp->aperegs);
15133                 tp->aperegs = NULL;
15134         }
15135
15136 err_out_iounmap:
15137         if (tp->regs) {
15138                 iounmap(tp->regs);
15139                 tp->regs = NULL;
15140         }
15141
15142 err_out_free_dev:
15143         free_netdev(dev);
15144
15145 err_out_free_res:
15146         pci_release_regions(pdev);
15147
15148 err_out_disable_pdev:
15149         pci_disable_device(pdev);
15150         pci_set_drvdata(pdev, NULL);
15151         return err;
15152 }
15153
15154 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15155 {
15156         struct net_device *dev = pci_get_drvdata(pdev);
15157
15158         if (dev) {
15159                 struct tg3 *tp = netdev_priv(dev);
15160
15161                 if (tp->fw)
15162                         release_firmware(tp->fw);
15163
15164                 cancel_work_sync(&tp->reset_task);
15165
15166                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
15167                         tg3_phy_fini(tp);
15168                         tg3_mdio_fini(tp);
15169                 }
15170
15171                 unregister_netdev(dev);
15172                 if (tp->aperegs) {
15173                         iounmap(tp->aperegs);
15174                         tp->aperegs = NULL;
15175                 }
15176                 if (tp->regs) {
15177                         iounmap(tp->regs);
15178                         tp->regs = NULL;
15179                 }
15180                 free_netdev(dev);
15181                 pci_release_regions(pdev);
15182                 pci_disable_device(pdev);
15183                 pci_set_drvdata(pdev, NULL);
15184         }
15185 }
15186
15187 #ifdef CONFIG_PM_SLEEP
15188 static int tg3_suspend(struct device *device)
15189 {
15190         struct pci_dev *pdev = to_pci_dev(device);
15191         struct net_device *dev = pci_get_drvdata(pdev);
15192         struct tg3 *tp = netdev_priv(dev);
15193         int err;
15194
15195         if (!netif_running(dev))
15196                 return 0;
15197
15198         flush_work_sync(&tp->reset_task);
15199         tg3_phy_stop(tp);
15200         tg3_netif_stop(tp);
15201
15202         del_timer_sync(&tp->timer);
15203
15204         tg3_full_lock(tp, 1);
15205         tg3_disable_ints(tp);
15206         tg3_full_unlock(tp);
15207
15208         netif_device_detach(dev);
15209
15210         tg3_full_lock(tp, 0);
15211         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15212         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
15213         tg3_full_unlock(tp);
15214
15215         err = tg3_power_down_prepare(tp);
15216         if (err) {
15217                 int err2;
15218
15219                 tg3_full_lock(tp, 0);
15220
15221                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15222                 err2 = tg3_restart_hw(tp, 1);
15223                 if (err2)
15224                         goto out;
15225
15226                 tp->timer.expires = jiffies + tp->timer_offset;
15227                 add_timer(&tp->timer);
15228
15229                 netif_device_attach(dev);
15230                 tg3_netif_start(tp);
15231
15232 out:
15233                 tg3_full_unlock(tp);
15234
15235                 if (!err2)
15236                         tg3_phy_start(tp);
15237         }
15238
15239         return err;
15240 }
15241
15242 static int tg3_resume(struct device *device)
15243 {
15244         struct pci_dev *pdev = to_pci_dev(device);
15245         struct net_device *dev = pci_get_drvdata(pdev);
15246         struct tg3 *tp = netdev_priv(dev);
15247         int err;
15248
15249         if (!netif_running(dev))
15250                 return 0;
15251
15252         netif_device_attach(dev);
15253
15254         tg3_full_lock(tp, 0);
15255
15256         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15257         err = tg3_restart_hw(tp, 1);
15258         if (err)
15259                 goto out;
15260
15261         tp->timer.expires = jiffies + tp->timer_offset;
15262         add_timer(&tp->timer);
15263
15264         tg3_netif_start(tp);
15265
15266 out:
15267         tg3_full_unlock(tp);
15268
15269         if (!err)
15270                 tg3_phy_start(tp);
15271
15272         return err;
15273 }
15274
15275 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15276 #define TG3_PM_OPS (&tg3_pm_ops)
15277
15278 #else
15279
15280 #define TG3_PM_OPS NULL
15281
15282 #endif /* CONFIG_PM_SLEEP */
15283
15284 static struct pci_driver tg3_driver = {
15285         .name           = DRV_MODULE_NAME,
15286         .id_table       = tg3_pci_tbl,
15287         .probe          = tg3_init_one,
15288         .remove         = __devexit_p(tg3_remove_one),
15289         .driver.pm      = TG3_PM_OPS,
15290 };
15291
15292 static int __init tg3_init(void)
15293 {
15294         return pci_register_driver(&tg3_driver);
15295 }
15296
15297 static void __exit tg3_cleanup(void)
15298 {
15299         pci_unregister_driver(&tg3_driver);
15300 }
15301
15302 module_init(tg3_init);
15303 module_exit(tg3_cleanup);