2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
45 #include <net/checksum.h>
48 #include <asm/system.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
54 #include <asm/idprom.h>
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
64 #define TG3_VLAN_TAG_USED 0
69 #define DRV_MODULE_NAME "tg3"
70 #define DRV_MODULE_VERSION "3.108"
71 #define DRV_MODULE_RELDATE "February 17, 2010"
73 #define TG3_DEF_MAC_MODE 0
74 #define TG3_DEF_RX_MODE 0
75 #define TG3_DEF_TX_MODE 0
76 #define TG3_DEF_MSG_ENABLE \
86 /* length of time before we decide the hardware is borked,
87 * and dev->tx_timeout() should be called to fix the problem
89 #define TG3_TX_TIMEOUT (5 * HZ)
91 /* hardware minimum and maximum for a single frame's data payload */
92 #define TG3_MIN_MTU 60
93 #define TG3_MAX_MTU(tp) \
94 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
96 /* These numbers seem to be hard coded in the NIC firmware somehow.
97 * You can't change the ring sizes, but you can change where you place
98 * them in the NIC onboard memory.
100 #define TG3_RX_RING_SIZE 512
101 #define TG3_DEF_RX_RING_PENDING 200
102 #define TG3_RX_JUMBO_RING_SIZE 256
103 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
104 #define TG3_RSS_INDIR_TBL_SIZE 128
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
114 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
116 #define TG3_TX_RING_SIZE 512
117 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
122 TG3_RX_JUMBO_RING_SIZE)
123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
124 TG3_RX_RCB_RING_SIZE(tp))
125 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129 #define TG3_DMA_BYTE_ENAB 64
131 #define TG3_RX_STD_DMA_SZ 1536
132 #define TG3_RX_JMB_DMA_SZ 9046
134 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
137 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
139 #define TG3_RX_STD_BUFF_RING_SIZE \
140 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
142 #define TG3_RX_JMB_BUFF_RING_SIZE \
143 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
145 #define TG3_RSS_MIN_NUM_MSIX_VECS 2
147 /* minimum number of free TX descriptors required to wake up TX process */
148 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
150 #define TG3_RAW_IP_ALIGN 2
152 /* number of ETHTOOL_GSTATS u64's */
153 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
155 #define TG3_NUM_TEST 6
157 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
159 #define FIRMWARE_TG3 "tigon/tg3.bin"
160 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
161 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
163 static char version[] __devinitdata =
164 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
166 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
167 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
168 MODULE_LICENSE("GPL");
169 MODULE_VERSION(DRV_MODULE_VERSION);
170 MODULE_FIRMWARE(FIRMWARE_TG3);
171 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
172 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
174 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
175 module_param(tg3_debug, int, 0);
176 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
178 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
254 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
255 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
256 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
257 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
258 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
259 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
260 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
264 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
266 static const struct {
267 const char string[ETH_GSTRING_LEN];
268 } ethtool_stats_keys[TG3_NUM_STATS] = {
271 { "rx_ucast_packets" },
272 { "rx_mcast_packets" },
273 { "rx_bcast_packets" },
275 { "rx_align_errors" },
276 { "rx_xon_pause_rcvd" },
277 { "rx_xoff_pause_rcvd" },
278 { "rx_mac_ctrl_rcvd" },
279 { "rx_xoff_entered" },
280 { "rx_frame_too_long_errors" },
282 { "rx_undersize_packets" },
283 { "rx_in_length_errors" },
284 { "rx_out_length_errors" },
285 { "rx_64_or_less_octet_packets" },
286 { "rx_65_to_127_octet_packets" },
287 { "rx_128_to_255_octet_packets" },
288 { "rx_256_to_511_octet_packets" },
289 { "rx_512_to_1023_octet_packets" },
290 { "rx_1024_to_1522_octet_packets" },
291 { "rx_1523_to_2047_octet_packets" },
292 { "rx_2048_to_4095_octet_packets" },
293 { "rx_4096_to_8191_octet_packets" },
294 { "rx_8192_to_9022_octet_packets" },
301 { "tx_flow_control" },
303 { "tx_single_collisions" },
304 { "tx_mult_collisions" },
306 { "tx_excessive_collisions" },
307 { "tx_late_collisions" },
308 { "tx_collide_2times" },
309 { "tx_collide_3times" },
310 { "tx_collide_4times" },
311 { "tx_collide_5times" },
312 { "tx_collide_6times" },
313 { "tx_collide_7times" },
314 { "tx_collide_8times" },
315 { "tx_collide_9times" },
316 { "tx_collide_10times" },
317 { "tx_collide_11times" },
318 { "tx_collide_12times" },
319 { "tx_collide_13times" },
320 { "tx_collide_14times" },
321 { "tx_collide_15times" },
322 { "tx_ucast_packets" },
323 { "tx_mcast_packets" },
324 { "tx_bcast_packets" },
325 { "tx_carrier_sense_errors" },
329 { "dma_writeq_full" },
330 { "dma_write_prioq_full" },
334 { "rx_threshold_hit" },
336 { "dma_readq_full" },
337 { "dma_read_prioq_full" },
338 { "tx_comp_queue_full" },
340 { "ring_set_send_prod_index" },
341 { "ring_status_update" },
343 { "nic_avoided_irqs" },
344 { "nic_tx_threshold_hit" }
347 static const struct {
348 const char string[ETH_GSTRING_LEN];
349 } ethtool_test_keys[TG3_NUM_TEST] = {
350 { "nvram test (online) " },
351 { "link test (online) " },
352 { "register test (offline)" },
353 { "memory test (offline)" },
354 { "loopback test (offline)" },
355 { "interrupt test (offline)" },
358 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
360 writel(val, tp->regs + off);
363 static u32 tg3_read32(struct tg3 *tp, u32 off)
365 return (readl(tp->regs + off));
368 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
370 writel(val, tp->aperegs + off);
373 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
375 return (readl(tp->aperegs + off));
378 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
382 spin_lock_irqsave(&tp->indirect_lock, flags);
383 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
384 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
385 spin_unlock_irqrestore(&tp->indirect_lock, flags);
388 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
390 writel(val, tp->regs + off);
391 readl(tp->regs + off);
394 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
399 spin_lock_irqsave(&tp->indirect_lock, flags);
400 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
401 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
402 spin_unlock_irqrestore(&tp->indirect_lock, flags);
406 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
410 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
411 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
412 TG3_64BIT_REG_LOW, val);
415 if (off == TG3_RX_STD_PROD_IDX_REG) {
416 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
417 TG3_64BIT_REG_LOW, val);
421 spin_lock_irqsave(&tp->indirect_lock, flags);
422 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
423 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
424 spin_unlock_irqrestore(&tp->indirect_lock, flags);
426 /* In indirect mode when disabling interrupts, we also need
427 * to clear the interrupt bit in the GRC local ctrl register.
429 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
431 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
432 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
436 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
441 spin_lock_irqsave(&tp->indirect_lock, flags);
442 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
443 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
444 spin_unlock_irqrestore(&tp->indirect_lock, flags);
448 /* usec_wait specifies the wait time in usec when writing to certain registers
449 * where it is unsafe to read back the register without some delay.
450 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
451 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
453 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
455 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
456 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
457 /* Non-posted methods */
458 tp->write32(tp, off, val);
461 tg3_write32(tp, off, val);
466 /* Wait again after the read for the posted method to guarantee that
467 * the wait time is met.
473 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
475 tp->write32_mbox(tp, off, val);
476 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
477 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
478 tp->read32_mbox(tp, off);
481 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
483 void __iomem *mbox = tp->regs + off;
485 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
487 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
491 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
493 return (readl(tp->regs + off + GRCMBOX_BASE));
496 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
498 writel(val, tp->regs + off + GRCMBOX_BASE);
501 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
502 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
503 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
504 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
505 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
507 #define tw32(reg, val) tp->write32(tp, reg, val)
508 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
509 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
510 #define tr32(reg) tp->read32(tp, reg)
512 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
516 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
517 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
520 spin_lock_irqsave(&tp->indirect_lock, flags);
521 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
525 /* Always leave this as zero. */
526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529 tw32_f(TG3PCI_MEM_WIN_DATA, val);
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
537 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
541 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
542 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
547 spin_lock_irqsave(&tp->indirect_lock, flags);
548 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
549 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
550 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
552 /* Always leave this as zero. */
553 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
555 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
556 *val = tr32(TG3PCI_MEM_WIN_DATA);
558 /* Always leave this as zero. */
559 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
561 spin_unlock_irqrestore(&tp->indirect_lock, flags);
564 static void tg3_ape_lock_init(struct tg3 *tp)
568 /* Make sure the driver hasn't any stale locks. */
569 for (i = 0; i < 8; i++)
570 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
571 APE_LOCK_GRANT_DRIVER);
574 static int tg3_ape_lock(struct tg3 *tp, int locknum)
580 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
584 case TG3_APE_LOCK_GRC:
585 case TG3_APE_LOCK_MEM:
593 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
595 /* Wait for up to 1 millisecond to acquire lock. */
596 for (i = 0; i < 100; i++) {
597 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
598 if (status == APE_LOCK_GRANT_DRIVER)
603 if (status != APE_LOCK_GRANT_DRIVER) {
604 /* Revoke the lock request. */
605 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
606 APE_LOCK_GRANT_DRIVER);
614 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
618 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
622 case TG3_APE_LOCK_GRC:
623 case TG3_APE_LOCK_MEM:
630 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
633 static void tg3_disable_ints(struct tg3 *tp)
637 tw32(TG3PCI_MISC_HOST_CTRL,
638 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
639 for (i = 0; i < tp->irq_max; i++)
640 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
643 static void tg3_enable_ints(struct tg3 *tp)
650 tw32(TG3PCI_MISC_HOST_CTRL,
651 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
653 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
654 for (i = 0; i < tp->irq_cnt; i++) {
655 struct tg3_napi *tnapi = &tp->napi[i];
657 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
658 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
659 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
661 tp->coal_now |= tnapi->coal_now;
664 /* Force an initial interrupt */
665 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
666 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
667 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
669 tw32(HOSTCC_MODE, tp->coal_now);
671 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
674 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
676 struct tg3 *tp = tnapi->tp;
677 struct tg3_hw_status *sblk = tnapi->hw_status;
678 unsigned int work_exists = 0;
680 /* check for phy events */
681 if (!(tp->tg3_flags &
682 (TG3_FLAG_USE_LINKCHG_REG |
683 TG3_FLAG_POLL_SERDES))) {
684 if (sblk->status & SD_STATUS_LINK_CHG)
687 /* check for RX/TX work to do */
688 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
689 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
696 * similar to tg3_enable_ints, but it accurately determines whether there
697 * is new work pending and can return without flushing the PIO write
698 * which reenables interrupts
700 static void tg3_int_reenable(struct tg3_napi *tnapi)
702 struct tg3 *tp = tnapi->tp;
704 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
707 /* When doing tagged status, this work check is unnecessary.
708 * The last_tag we write above tells the chip which piece of
709 * work we've completed.
711 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
713 tw32(HOSTCC_MODE, tp->coalesce_mode |
714 HOSTCC_MODE_ENABLE | tnapi->coal_now);
717 static void tg3_napi_disable(struct tg3 *tp)
721 for (i = tp->irq_cnt - 1; i >= 0; i--)
722 napi_disable(&tp->napi[i].napi);
725 static void tg3_napi_enable(struct tg3 *tp)
729 for (i = 0; i < tp->irq_cnt; i++)
730 napi_enable(&tp->napi[i].napi);
733 static inline void tg3_netif_stop(struct tg3 *tp)
735 tp->dev->trans_start = jiffies; /* prevent tx timeout */
736 tg3_napi_disable(tp);
737 netif_tx_disable(tp->dev);
740 static inline void tg3_netif_start(struct tg3 *tp)
742 /* NOTE: unconditional netif_tx_wake_all_queues is only
743 * appropriate so long as all callers are assured to
744 * have free tx slots (such as after tg3_init_hw)
746 netif_tx_wake_all_queues(tp->dev);
749 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
753 static void tg3_switch_clocks(struct tg3 *tp)
758 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
759 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
762 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
764 orig_clock_ctrl = clock_ctrl;
765 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
766 CLOCK_CTRL_CLKRUN_OENABLE |
768 tp->pci_clock_ctrl = clock_ctrl;
770 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
771 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
772 tw32_wait_f(TG3PCI_CLOCK_CTRL,
773 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
775 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
776 tw32_wait_f(TG3PCI_CLOCK_CTRL,
778 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
780 tw32_wait_f(TG3PCI_CLOCK_CTRL,
781 clock_ctrl | (CLOCK_CTRL_ALTCLK),
784 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
787 #define PHY_BUSY_LOOPS 5000
789 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
795 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
797 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
803 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
804 MI_COM_PHY_ADDR_MASK);
805 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
806 MI_COM_REG_ADDR_MASK);
807 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
809 tw32_f(MAC_MI_COM, frame_val);
811 loops = PHY_BUSY_LOOPS;
814 frame_val = tr32(MAC_MI_COM);
816 if ((frame_val & MI_COM_BUSY) == 0) {
818 frame_val = tr32(MAC_MI_COM);
826 *val = frame_val & MI_COM_DATA_MASK;
830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE, tp->mi_mode);
838 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
844 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
845 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
848 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
850 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
854 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
855 MI_COM_PHY_ADDR_MASK);
856 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
857 MI_COM_REG_ADDR_MASK);
858 frame_val |= (val & MI_COM_DATA_MASK);
859 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
861 tw32_f(MAC_MI_COM, frame_val);
863 loops = PHY_BUSY_LOOPS;
866 frame_val = tr32(MAC_MI_COM);
867 if ((frame_val & MI_COM_BUSY) == 0) {
869 frame_val = tr32(MAC_MI_COM);
879 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
880 tw32_f(MAC_MI_MODE, tp->mi_mode);
887 static int tg3_bmcr_reset(struct tg3 *tp)
892 /* OK, reset it, and poll the BMCR_RESET bit until it
893 * clears or we time out.
895 phy_control = BMCR_RESET;
896 err = tg3_writephy(tp, MII_BMCR, phy_control);
902 err = tg3_readphy(tp, MII_BMCR, &phy_control);
906 if ((phy_control & BMCR_RESET) == 0) {
918 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
920 struct tg3 *tp = bp->priv;
923 spin_lock_bh(&tp->lock);
925 if (tg3_readphy(tp, reg, &val))
928 spin_unlock_bh(&tp->lock);
933 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
935 struct tg3 *tp = bp->priv;
938 spin_lock_bh(&tp->lock);
940 if (tg3_writephy(tp, reg, val))
943 spin_unlock_bh(&tp->lock);
948 static int tg3_mdio_reset(struct mii_bus *bp)
953 static void tg3_mdio_config_5785(struct tg3 *tp)
956 struct phy_device *phydev;
958 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
959 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
960 case PHY_ID_BCM50610:
961 case PHY_ID_BCM50610M:
962 val = MAC_PHYCFG2_50610_LED_MODES;
964 case PHY_ID_BCMAC131:
965 val = MAC_PHYCFG2_AC131_LED_MODES;
967 case PHY_ID_RTL8211C:
968 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
970 case PHY_ID_RTL8201E:
971 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
977 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
978 tw32(MAC_PHYCFG2, val);
980 val = tr32(MAC_PHYCFG1);
981 val &= ~(MAC_PHYCFG1_RGMII_INT |
982 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
983 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
984 tw32(MAC_PHYCFG1, val);
989 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
990 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
991 MAC_PHYCFG2_FMODE_MASK_MASK |
992 MAC_PHYCFG2_GMODE_MASK_MASK |
993 MAC_PHYCFG2_ACT_MASK_MASK |
994 MAC_PHYCFG2_QUAL_MASK_MASK |
995 MAC_PHYCFG2_INBAND_ENABLE;
997 tw32(MAC_PHYCFG2, val);
999 val = tr32(MAC_PHYCFG1);
1000 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1001 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1002 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1003 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1005 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1006 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1008 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1009 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1010 tw32(MAC_PHYCFG1, val);
1012 val = tr32(MAC_EXT_RGMII_MODE);
1013 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1014 MAC_RGMII_MODE_RX_QUALITY |
1015 MAC_RGMII_MODE_RX_ACTIVITY |
1016 MAC_RGMII_MODE_RX_ENG_DET |
1017 MAC_RGMII_MODE_TX_ENABLE |
1018 MAC_RGMII_MODE_TX_LOWPWR |
1019 MAC_RGMII_MODE_TX_RESET);
1020 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1021 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1022 val |= MAC_RGMII_MODE_RX_INT_B |
1023 MAC_RGMII_MODE_RX_QUALITY |
1024 MAC_RGMII_MODE_RX_ACTIVITY |
1025 MAC_RGMII_MODE_RX_ENG_DET;
1026 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1027 val |= MAC_RGMII_MODE_TX_ENABLE |
1028 MAC_RGMII_MODE_TX_LOWPWR |
1029 MAC_RGMII_MODE_TX_RESET;
1031 tw32(MAC_EXT_RGMII_MODE, val);
1034 static void tg3_mdio_start(struct tg3 *tp)
1036 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1037 tw32_f(MAC_MI_MODE, tp->mi_mode);
1040 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1042 tg3_mdio_config_5785(tp);
1045 static int tg3_mdio_init(struct tg3 *tp)
1049 struct phy_device *phydev;
1051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1052 u32 funcnum, is_serdes;
1054 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1060 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1061 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1063 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1064 TG3_CPMU_PHY_STRAP_IS_SERDES;
1068 tp->phy_addr = TG3_PHY_MII_ADDR;
1072 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1073 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1076 tp->mdio_bus = mdiobus_alloc();
1077 if (tp->mdio_bus == NULL)
1080 tp->mdio_bus->name = "tg3 mdio bus";
1081 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1082 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1083 tp->mdio_bus->priv = tp;
1084 tp->mdio_bus->parent = &tp->pdev->dev;
1085 tp->mdio_bus->read = &tg3_mdio_read;
1086 tp->mdio_bus->write = &tg3_mdio_write;
1087 tp->mdio_bus->reset = &tg3_mdio_reset;
1088 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1089 tp->mdio_bus->irq = &tp->mdio_irq[0];
1091 for (i = 0; i < PHY_MAX_ADDR; i++)
1092 tp->mdio_bus->irq[i] = PHY_POLL;
1094 /* The bus registration will look for all the PHYs on the mdio bus.
1095 * Unfortunately, it does not ensure the PHY is powered up before
1096 * accessing the PHY ID registers. A chip reset is the
1097 * quickest way to bring the device back to an operational state..
1099 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1102 i = mdiobus_register(tp->mdio_bus);
1104 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1105 mdiobus_free(tp->mdio_bus);
1109 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1111 if (!phydev || !phydev->drv) {
1112 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1113 mdiobus_unregister(tp->mdio_bus);
1114 mdiobus_free(tp->mdio_bus);
1118 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1119 case PHY_ID_BCM57780:
1120 phydev->interface = PHY_INTERFACE_MODE_GMII;
1121 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1123 case PHY_ID_BCM50610:
1124 case PHY_ID_BCM50610M:
1125 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1126 PHY_BRCM_RX_REFCLK_UNUSED |
1127 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1128 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1129 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1130 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1131 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1132 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1133 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1134 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1136 case PHY_ID_RTL8211C:
1137 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1139 case PHY_ID_RTL8201E:
1140 case PHY_ID_BCMAC131:
1141 phydev->interface = PHY_INTERFACE_MODE_MII;
1142 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1143 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1147 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1149 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1150 tg3_mdio_config_5785(tp);
1155 static void tg3_mdio_fini(struct tg3 *tp)
1157 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1158 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1159 mdiobus_unregister(tp->mdio_bus);
1160 mdiobus_free(tp->mdio_bus);
1164 /* tp->lock is held. */
1165 static inline void tg3_generate_fw_event(struct tg3 *tp)
1169 val = tr32(GRC_RX_CPU_EVENT);
1170 val |= GRC_RX_CPU_DRIVER_EVENT;
1171 tw32_f(GRC_RX_CPU_EVENT, val);
1173 tp->last_event_jiffies = jiffies;
1176 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1178 /* tp->lock is held. */
1179 static void tg3_wait_for_event_ack(struct tg3 *tp)
1182 unsigned int delay_cnt;
1185 /* If enough time has passed, no wait is necessary. */
1186 time_remain = (long)(tp->last_event_jiffies + 1 +
1187 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1189 if (time_remain < 0)
1192 /* Check if we can shorten the wait time. */
1193 delay_cnt = jiffies_to_usecs(time_remain);
1194 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1195 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1196 delay_cnt = (delay_cnt >> 3) + 1;
1198 for (i = 0; i < delay_cnt; i++) {
1199 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1205 /* tp->lock is held. */
1206 static void tg3_ump_link_report(struct tg3 *tp)
1211 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1212 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1215 tg3_wait_for_event_ack(tp);
1217 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1219 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1222 if (!tg3_readphy(tp, MII_BMCR, ®))
1224 if (!tg3_readphy(tp, MII_BMSR, ®))
1225 val |= (reg & 0xffff);
1226 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1229 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1231 if (!tg3_readphy(tp, MII_LPA, ®))
1232 val |= (reg & 0xffff);
1233 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1236 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1237 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1239 if (!tg3_readphy(tp, MII_STAT1000, ®))
1240 val |= (reg & 0xffff);
1242 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1244 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1248 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1250 tg3_generate_fw_event(tp);
1253 static void tg3_link_report(struct tg3 *tp)
1255 if (!netif_carrier_ok(tp->dev)) {
1256 netif_info(tp, link, tp->dev, "Link is down\n");
1257 tg3_ump_link_report(tp);
1258 } else if (netif_msg_link(tp)) {
1259 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1260 (tp->link_config.active_speed == SPEED_1000 ?
1262 (tp->link_config.active_speed == SPEED_100 ?
1264 (tp->link_config.active_duplex == DUPLEX_FULL ?
1267 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1268 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1270 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1272 tg3_ump_link_report(tp);
1276 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1280 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1281 miireg = ADVERTISE_PAUSE_CAP;
1282 else if (flow_ctrl & FLOW_CTRL_TX)
1283 miireg = ADVERTISE_PAUSE_ASYM;
1284 else if (flow_ctrl & FLOW_CTRL_RX)
1285 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1292 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1296 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1297 miireg = ADVERTISE_1000XPAUSE;
1298 else if (flow_ctrl & FLOW_CTRL_TX)
1299 miireg = ADVERTISE_1000XPSE_ASYM;
1300 else if (flow_ctrl & FLOW_CTRL_RX)
1301 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1308 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1312 if (lcladv & ADVERTISE_1000XPAUSE) {
1313 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1314 if (rmtadv & LPA_1000XPAUSE)
1315 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1316 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1319 if (rmtadv & LPA_1000XPAUSE)
1320 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1322 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1323 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1330 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1334 u32 old_rx_mode = tp->rx_mode;
1335 u32 old_tx_mode = tp->tx_mode;
1337 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1338 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1340 autoneg = tp->link_config.autoneg;
1342 if (autoneg == AUTONEG_ENABLE &&
1343 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1344 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1345 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1347 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1349 flowctrl = tp->link_config.flowctrl;
1351 tp->link_config.active_flowctrl = flowctrl;
1353 if (flowctrl & FLOW_CTRL_RX)
1354 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1356 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1358 if (old_rx_mode != tp->rx_mode)
1359 tw32_f(MAC_RX_MODE, tp->rx_mode);
1361 if (flowctrl & FLOW_CTRL_TX)
1362 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1364 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1366 if (old_tx_mode != tp->tx_mode)
1367 tw32_f(MAC_TX_MODE, tp->tx_mode);
1370 static void tg3_adjust_link(struct net_device *dev)
1372 u8 oldflowctrl, linkmesg = 0;
1373 u32 mac_mode, lcl_adv, rmt_adv;
1374 struct tg3 *tp = netdev_priv(dev);
1375 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1377 spin_lock_bh(&tp->lock);
1379 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1380 MAC_MODE_HALF_DUPLEX);
1382 oldflowctrl = tp->link_config.active_flowctrl;
1388 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1389 mac_mode |= MAC_MODE_PORT_MODE_MII;
1390 else if (phydev->speed == SPEED_1000 ||
1391 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1392 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1394 mac_mode |= MAC_MODE_PORT_MODE_MII;
1396 if (phydev->duplex == DUPLEX_HALF)
1397 mac_mode |= MAC_MODE_HALF_DUPLEX;
1399 lcl_adv = tg3_advert_flowctrl_1000T(
1400 tp->link_config.flowctrl);
1403 rmt_adv = LPA_PAUSE_CAP;
1404 if (phydev->asym_pause)
1405 rmt_adv |= LPA_PAUSE_ASYM;
1408 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1410 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1412 if (mac_mode != tp->mac_mode) {
1413 tp->mac_mode = mac_mode;
1414 tw32_f(MAC_MODE, tp->mac_mode);
1418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1419 if (phydev->speed == SPEED_10)
1421 MAC_MI_STAT_10MBPS_MODE |
1422 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1424 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1427 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1428 tw32(MAC_TX_LENGTHS,
1429 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1430 (6 << TX_LENGTHS_IPG_SHIFT) |
1431 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1433 tw32(MAC_TX_LENGTHS,
1434 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1435 (6 << TX_LENGTHS_IPG_SHIFT) |
1436 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1438 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1439 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1440 phydev->speed != tp->link_config.active_speed ||
1441 phydev->duplex != tp->link_config.active_duplex ||
1442 oldflowctrl != tp->link_config.active_flowctrl)
1445 tp->link_config.active_speed = phydev->speed;
1446 tp->link_config.active_duplex = phydev->duplex;
1448 spin_unlock_bh(&tp->lock);
1451 tg3_link_report(tp);
1454 static int tg3_phy_init(struct tg3 *tp)
1456 struct phy_device *phydev;
1458 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1461 /* Bring the PHY back to a known state. */
1464 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1466 /* Attach the MAC to the PHY. */
1467 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1468 phydev->dev_flags, phydev->interface);
1469 if (IS_ERR(phydev)) {
1470 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1471 return PTR_ERR(phydev);
1474 /* Mask with MAC supported features. */
1475 switch (phydev->interface) {
1476 case PHY_INTERFACE_MODE_GMII:
1477 case PHY_INTERFACE_MODE_RGMII:
1478 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1479 phydev->supported &= (PHY_GBIT_FEATURES |
1481 SUPPORTED_Asym_Pause);
1485 case PHY_INTERFACE_MODE_MII:
1486 phydev->supported &= (PHY_BASIC_FEATURES |
1488 SUPPORTED_Asym_Pause);
1491 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1495 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1497 phydev->advertising = phydev->supported;
1502 static void tg3_phy_start(struct tg3 *tp)
1504 struct phy_device *phydev;
1506 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1509 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1511 if (tp->link_config.phy_is_low_power) {
1512 tp->link_config.phy_is_low_power = 0;
1513 phydev->speed = tp->link_config.orig_speed;
1514 phydev->duplex = tp->link_config.orig_duplex;
1515 phydev->autoneg = tp->link_config.orig_autoneg;
1516 phydev->advertising = tp->link_config.orig_advertising;
1521 phy_start_aneg(phydev);
1524 static void tg3_phy_stop(struct tg3 *tp)
1526 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1529 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1532 static void tg3_phy_fini(struct tg3 *tp)
1534 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1535 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1536 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1540 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1542 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1543 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1546 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1550 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1553 tg3_writephy(tp, MII_TG3_FET_TEST,
1554 phytest | MII_TG3_FET_SHADOW_EN);
1555 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1557 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1559 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1560 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1562 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1566 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1570 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1571 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1572 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1575 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1576 tg3_phy_fet_toggle_apd(tp, enable);
1580 reg = MII_TG3_MISC_SHDW_WREN |
1581 MII_TG3_MISC_SHDW_SCR5_SEL |
1582 MII_TG3_MISC_SHDW_SCR5_LPED |
1583 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1584 MII_TG3_MISC_SHDW_SCR5_SDTL |
1585 MII_TG3_MISC_SHDW_SCR5_C125OE;
1586 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1587 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1589 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1592 reg = MII_TG3_MISC_SHDW_WREN |
1593 MII_TG3_MISC_SHDW_APD_SEL |
1594 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1596 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1598 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1601 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1605 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1606 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1609 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1612 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1613 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1615 tg3_writephy(tp, MII_TG3_FET_TEST,
1616 ephy | MII_TG3_FET_SHADOW_EN);
1617 if (!tg3_readphy(tp, reg, &phy)) {
1619 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1621 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1622 tg3_writephy(tp, reg, phy);
1624 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1627 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1628 MII_TG3_AUXCTL_SHDWSEL_MISC;
1629 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1630 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1632 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1634 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1635 phy |= MII_TG3_AUXCTL_MISC_WREN;
1636 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1641 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1645 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1648 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1649 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1650 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1651 (val | (1 << 15) | (1 << 4)));
1654 static void tg3_phy_apply_otp(struct tg3 *tp)
1663 /* Enable SM_DSP clock and tx 6dB coding. */
1664 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1665 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1666 MII_TG3_AUXCTL_ACTL_TX_6DB;
1667 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1669 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1670 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1671 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1673 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1674 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1675 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1677 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1678 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1679 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1681 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1682 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1684 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1685 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1687 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1688 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1689 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1691 /* Turn off SM_DSP clock. */
1692 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1693 MII_TG3_AUXCTL_ACTL_TX_6DB;
1694 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1697 static int tg3_wait_macro_done(struct tg3 *tp)
1704 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1705 if ((tmp32 & 0x1000) == 0)
1715 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1717 static const u32 test_pat[4][6] = {
1718 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1719 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1720 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1721 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1725 for (chan = 0; chan < 4; chan++) {
1728 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1729 (chan * 0x2000) | 0x0200);
1730 tg3_writephy(tp, 0x16, 0x0002);
1732 for (i = 0; i < 6; i++)
1733 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1736 tg3_writephy(tp, 0x16, 0x0202);
1737 if (tg3_wait_macro_done(tp)) {
1742 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1743 (chan * 0x2000) | 0x0200);
1744 tg3_writephy(tp, 0x16, 0x0082);
1745 if (tg3_wait_macro_done(tp)) {
1750 tg3_writephy(tp, 0x16, 0x0802);
1751 if (tg3_wait_macro_done(tp)) {
1756 for (i = 0; i < 6; i += 2) {
1759 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1760 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1761 tg3_wait_macro_done(tp)) {
1767 if (low != test_pat[chan][i] ||
1768 high != test_pat[chan][i+1]) {
1769 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1770 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1771 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1781 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1785 for (chan = 0; chan < 4; chan++) {
1788 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1789 (chan * 0x2000) | 0x0200);
1790 tg3_writephy(tp, 0x16, 0x0002);
1791 for (i = 0; i < 6; i++)
1792 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1793 tg3_writephy(tp, 0x16, 0x0202);
1794 if (tg3_wait_macro_done(tp))
1801 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1803 u32 reg32, phy9_orig;
1804 int retries, do_phy_reset, err;
1810 err = tg3_bmcr_reset(tp);
1816 /* Disable transmitter and interrupt. */
1817 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1821 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1823 /* Set full-duplex, 1000 mbps. */
1824 tg3_writephy(tp, MII_BMCR,
1825 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1827 /* Set to master mode. */
1828 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1831 tg3_writephy(tp, MII_TG3_CTRL,
1832 (MII_TG3_CTRL_AS_MASTER |
1833 MII_TG3_CTRL_ENABLE_AS_MASTER));
1835 /* Enable SM_DSP_CLOCK and 6dB. */
1836 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1838 /* Block the PHY control access. */
1839 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1840 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1842 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1845 } while (--retries);
1847 err = tg3_phy_reset_chanpat(tp);
1851 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1852 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1854 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1855 tg3_writephy(tp, 0x16, 0x0000);
1857 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1858 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1859 /* Set Extended packet length bit for jumbo frames */
1860 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1862 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1865 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1867 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
1869 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1876 /* This will reset the tigon3 PHY if there is no valid
1877 * link unless the FORCE argument is non-zero.
1879 static int tg3_phy_reset(struct tg3 *tp)
1885 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1888 val = tr32(GRC_MISC_CFG);
1889 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1892 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1893 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1897 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1898 netif_carrier_off(tp->dev);
1899 tg3_link_report(tp);
1902 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1903 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1904 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1905 err = tg3_phy_reset_5703_4_5(tp);
1912 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1913 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1914 cpmuctrl = tr32(TG3_CPMU_CTRL);
1915 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1917 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1920 err = tg3_bmcr_reset(tp);
1924 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1927 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1928 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1930 tw32(TG3_CPMU_CTRL, cpmuctrl);
1933 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1934 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1937 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1938 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1939 CPMU_LSPD_1000MB_MACCLK_12_5) {
1940 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1942 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1946 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1947 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1950 tg3_phy_apply_otp(tp);
1952 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1953 tg3_phy_toggle_apd(tp, true);
1955 tg3_phy_toggle_apd(tp, false);
1958 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1959 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1960 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1961 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1962 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1963 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1964 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1966 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1967 tg3_writephy(tp, 0x1c, 0x8d68);
1968 tg3_writephy(tp, 0x1c, 0x8d68);
1970 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1971 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1972 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1973 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1974 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1975 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1976 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1977 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1978 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1979 } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1980 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1981 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1982 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1983 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1984 tg3_writephy(tp, MII_TG3_TEST1,
1985 MII_TG3_TEST1_TRIM_EN | 0x4);
1987 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1988 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1990 /* Set Extended packet length bit (bit 14) on all chips that */
1991 /* support jumbo frames */
1992 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1993 /* Cannot do read-modify-write on 5401 */
1994 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1995 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1998 /* Set bit 14 with read-modify-write to preserve other bits */
1999 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2000 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2001 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2004 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2005 * jumbo frames transmission.
2007 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2010 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2011 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2012 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2015 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2016 /* adjust output voltage */
2017 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2020 tg3_phy_toggle_automdix(tp, 1);
2021 tg3_phy_set_wirespeed(tp);
2025 static void tg3_frob_aux_power(struct tg3 *tp)
2027 struct tg3 *tp_peer = tp;
2029 /* The GPIOs do something completely different on 57765. */
2030 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2031 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2034 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2036 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2037 struct net_device *dev_peer;
2039 dev_peer = pci_get_drvdata(tp->pdev_peer);
2040 /* remove_one() may have been run on the peer. */
2044 tp_peer = netdev_priv(dev_peer);
2047 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2048 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2049 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2050 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2052 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2053 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2054 (GRC_LCLCTRL_GPIO_OE0 |
2055 GRC_LCLCTRL_GPIO_OE1 |
2056 GRC_LCLCTRL_GPIO_OE2 |
2057 GRC_LCLCTRL_GPIO_OUTPUT0 |
2058 GRC_LCLCTRL_GPIO_OUTPUT1),
2060 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2061 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2062 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2063 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2064 GRC_LCLCTRL_GPIO_OE1 |
2065 GRC_LCLCTRL_GPIO_OE2 |
2066 GRC_LCLCTRL_GPIO_OUTPUT0 |
2067 GRC_LCLCTRL_GPIO_OUTPUT1 |
2069 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2071 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2072 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2074 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2075 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2078 u32 grc_local_ctrl = 0;
2080 if (tp_peer != tp &&
2081 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2084 /* Workaround to prevent overdrawing Amps. */
2085 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2087 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2088 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2089 grc_local_ctrl, 100);
2092 /* On 5753 and variants, GPIO2 cannot be used. */
2093 no_gpio2 = tp->nic_sram_data_cfg &
2094 NIC_SRAM_DATA_CFG_NO_GPIO2;
2096 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2097 GRC_LCLCTRL_GPIO_OE1 |
2098 GRC_LCLCTRL_GPIO_OE2 |
2099 GRC_LCLCTRL_GPIO_OUTPUT1 |
2100 GRC_LCLCTRL_GPIO_OUTPUT2;
2102 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2103 GRC_LCLCTRL_GPIO_OUTPUT2);
2105 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2106 grc_local_ctrl, 100);
2108 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2110 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2111 grc_local_ctrl, 100);
2114 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2115 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2116 grc_local_ctrl, 100);
2120 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2121 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2122 if (tp_peer != tp &&
2123 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2126 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2127 (GRC_LCLCTRL_GPIO_OE1 |
2128 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2130 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2131 GRC_LCLCTRL_GPIO_OE1, 100);
2133 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2134 (GRC_LCLCTRL_GPIO_OE1 |
2135 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2140 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2142 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2144 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2145 if (speed != SPEED_10)
2147 } else if (speed == SPEED_10)
2153 static int tg3_setup_phy(struct tg3 *, int);
2155 #define RESET_KIND_SHUTDOWN 0
2156 #define RESET_KIND_INIT 1
2157 #define RESET_KIND_SUSPEND 2
2159 static void tg3_write_sig_post_reset(struct tg3 *, int);
2160 static int tg3_halt_cpu(struct tg3 *, u32);
2162 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2166 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2167 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2168 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2169 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2172 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2173 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2174 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2179 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2181 val = tr32(GRC_MISC_CFG);
2182 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2185 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2187 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2190 tg3_writephy(tp, MII_ADVERTISE, 0);
2191 tg3_writephy(tp, MII_BMCR,
2192 BMCR_ANENABLE | BMCR_ANRESTART);
2194 tg3_writephy(tp, MII_TG3_FET_TEST,
2195 phytest | MII_TG3_FET_SHADOW_EN);
2196 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2197 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2199 MII_TG3_FET_SHDW_AUXMODE4,
2202 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2205 } else if (do_low_power) {
2206 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2207 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2209 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2210 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2211 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2212 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2213 MII_TG3_AUXCTL_PCTL_VREG_11V);
2216 /* The PHY should not be powered down on some chips because
2219 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2220 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2221 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2222 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2225 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2226 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2227 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2228 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2229 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2230 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2233 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2236 /* tp->lock is held. */
2237 static int tg3_nvram_lock(struct tg3 *tp)
2239 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2242 if (tp->nvram_lock_cnt == 0) {
2243 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2244 for (i = 0; i < 8000; i++) {
2245 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2250 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2254 tp->nvram_lock_cnt++;
2259 /* tp->lock is held. */
2260 static void tg3_nvram_unlock(struct tg3 *tp)
2262 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2263 if (tp->nvram_lock_cnt > 0)
2264 tp->nvram_lock_cnt--;
2265 if (tp->nvram_lock_cnt == 0)
2266 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2270 /* tp->lock is held. */
2271 static void tg3_enable_nvram_access(struct tg3 *tp)
2273 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2274 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2275 u32 nvaccess = tr32(NVRAM_ACCESS);
2277 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2281 /* tp->lock is held. */
2282 static void tg3_disable_nvram_access(struct tg3 *tp)
2284 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2285 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2286 u32 nvaccess = tr32(NVRAM_ACCESS);
2288 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2292 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2293 u32 offset, u32 *val)
2298 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2301 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2302 EEPROM_ADDR_DEVID_MASK |
2304 tw32(GRC_EEPROM_ADDR,
2306 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2307 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2308 EEPROM_ADDR_ADDR_MASK) |
2309 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2311 for (i = 0; i < 1000; i++) {
2312 tmp = tr32(GRC_EEPROM_ADDR);
2314 if (tmp & EEPROM_ADDR_COMPLETE)
2318 if (!(tmp & EEPROM_ADDR_COMPLETE))
2321 tmp = tr32(GRC_EEPROM_DATA);
2324 * The data will always be opposite the native endian
2325 * format. Perform a blind byteswap to compensate.
2332 #define NVRAM_CMD_TIMEOUT 10000
2334 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2338 tw32(NVRAM_CMD, nvram_cmd);
2339 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2341 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2347 if (i == NVRAM_CMD_TIMEOUT)
2353 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2355 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2356 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2357 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2358 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2359 (tp->nvram_jedecnum == JEDEC_ATMEL))
2361 addr = ((addr / tp->nvram_pagesize) <<
2362 ATMEL_AT45DB0X1B_PAGE_POS) +
2363 (addr % tp->nvram_pagesize);
2368 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2370 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2371 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2372 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2373 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2374 (tp->nvram_jedecnum == JEDEC_ATMEL))
2376 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2377 tp->nvram_pagesize) +
2378 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2383 /* NOTE: Data read in from NVRAM is byteswapped according to
2384 * the byteswapping settings for all other register accesses.
2385 * tg3 devices are BE devices, so on a BE machine, the data
2386 * returned will be exactly as it is seen in NVRAM. On a LE
2387 * machine, the 32-bit value will be byteswapped.
2389 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2393 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2394 return tg3_nvram_read_using_eeprom(tp, offset, val);
2396 offset = tg3_nvram_phys_addr(tp, offset);
2398 if (offset > NVRAM_ADDR_MSK)
2401 ret = tg3_nvram_lock(tp);
2405 tg3_enable_nvram_access(tp);
2407 tw32(NVRAM_ADDR, offset);
2408 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2409 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2412 *val = tr32(NVRAM_RDDATA);
2414 tg3_disable_nvram_access(tp);
2416 tg3_nvram_unlock(tp);
2421 /* Ensures NVRAM data is in bytestream format. */
2422 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2425 int res = tg3_nvram_read(tp, offset, &v);
2427 *val = cpu_to_be32(v);
2431 /* tp->lock is held. */
2432 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2434 u32 addr_high, addr_low;
2437 addr_high = ((tp->dev->dev_addr[0] << 8) |
2438 tp->dev->dev_addr[1]);
2439 addr_low = ((tp->dev->dev_addr[2] << 24) |
2440 (tp->dev->dev_addr[3] << 16) |
2441 (tp->dev->dev_addr[4] << 8) |
2442 (tp->dev->dev_addr[5] << 0));
2443 for (i = 0; i < 4; i++) {
2444 if (i == 1 && skip_mac_1)
2446 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2447 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2450 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2451 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2452 for (i = 0; i < 12; i++) {
2453 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2454 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2458 addr_high = (tp->dev->dev_addr[0] +
2459 tp->dev->dev_addr[1] +
2460 tp->dev->dev_addr[2] +
2461 tp->dev->dev_addr[3] +
2462 tp->dev->dev_addr[4] +
2463 tp->dev->dev_addr[5]) &
2464 TX_BACKOFF_SEED_MASK;
2465 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2468 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2471 bool device_should_wake, do_low_power;
2473 /* Make sure register accesses (indirect or otherwise)
2474 * will function correctly.
2476 pci_write_config_dword(tp->pdev,
2477 TG3PCI_MISC_HOST_CTRL,
2478 tp->misc_host_ctrl);
2482 pci_enable_wake(tp->pdev, state, false);
2483 pci_set_power_state(tp->pdev, PCI_D0);
2485 /* Switch out of Vaux if it is a NIC */
2486 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2487 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2497 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2502 /* Restore the CLKREQ setting. */
2503 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2506 pci_read_config_word(tp->pdev,
2507 tp->pcie_cap + PCI_EXP_LNKCTL,
2509 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2510 pci_write_config_word(tp->pdev,
2511 tp->pcie_cap + PCI_EXP_LNKCTL,
2515 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2516 tw32(TG3PCI_MISC_HOST_CTRL,
2517 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2519 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2520 device_may_wakeup(&tp->pdev->dev) &&
2521 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2523 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2524 do_low_power = false;
2525 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2526 !tp->link_config.phy_is_low_power) {
2527 struct phy_device *phydev;
2528 u32 phyid, advertising;
2530 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2532 tp->link_config.phy_is_low_power = 1;
2534 tp->link_config.orig_speed = phydev->speed;
2535 tp->link_config.orig_duplex = phydev->duplex;
2536 tp->link_config.orig_autoneg = phydev->autoneg;
2537 tp->link_config.orig_advertising = phydev->advertising;
2539 advertising = ADVERTISED_TP |
2541 ADVERTISED_Autoneg |
2542 ADVERTISED_10baseT_Half;
2544 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2545 device_should_wake) {
2546 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2548 ADVERTISED_100baseT_Half |
2549 ADVERTISED_100baseT_Full |
2550 ADVERTISED_10baseT_Full;
2552 advertising |= ADVERTISED_10baseT_Full;
2555 phydev->advertising = advertising;
2557 phy_start_aneg(phydev);
2559 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2560 if (phyid != PHY_ID_BCMAC131) {
2561 phyid &= PHY_BCM_OUI_MASK;
2562 if (phyid == PHY_BCM_OUI_1 ||
2563 phyid == PHY_BCM_OUI_2 ||
2564 phyid == PHY_BCM_OUI_3)
2565 do_low_power = true;
2569 do_low_power = true;
2571 if (tp->link_config.phy_is_low_power == 0) {
2572 tp->link_config.phy_is_low_power = 1;
2573 tp->link_config.orig_speed = tp->link_config.speed;
2574 tp->link_config.orig_duplex = tp->link_config.duplex;
2575 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2578 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2579 tp->link_config.speed = SPEED_10;
2580 tp->link_config.duplex = DUPLEX_HALF;
2581 tp->link_config.autoneg = AUTONEG_ENABLE;
2582 tg3_setup_phy(tp, 0);
2586 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2589 val = tr32(GRC_VCPU_EXT_CTRL);
2590 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2591 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2595 for (i = 0; i < 200; i++) {
2596 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2597 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2602 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2603 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2604 WOL_DRV_STATE_SHUTDOWN |
2608 if (device_should_wake) {
2611 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2613 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2617 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2618 mac_mode = MAC_MODE_PORT_MODE_GMII;
2620 mac_mode = MAC_MODE_PORT_MODE_MII;
2622 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2623 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2625 u32 speed = (tp->tg3_flags &
2626 TG3_FLAG_WOL_SPEED_100MB) ?
2627 SPEED_100 : SPEED_10;
2628 if (tg3_5700_link_polarity(tp, speed))
2629 mac_mode |= MAC_MODE_LINK_POLARITY;
2631 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2634 mac_mode = MAC_MODE_PORT_MODE_TBI;
2637 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2638 tw32(MAC_LED_CTRL, tp->led_ctrl);
2640 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2641 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2642 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2643 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2644 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2645 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2647 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2648 mac_mode |= tp->mac_mode &
2649 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2650 if (mac_mode & MAC_MODE_APE_TX_EN)
2651 mac_mode |= MAC_MODE_TDE_ENABLE;
2654 tw32_f(MAC_MODE, mac_mode);
2657 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2661 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2662 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2663 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2666 base_val = tp->pci_clock_ctrl;
2667 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2668 CLOCK_CTRL_TXCLK_DISABLE);
2670 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2671 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2672 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2673 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2674 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2676 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2677 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2678 u32 newbits1, newbits2;
2680 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2681 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2682 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2683 CLOCK_CTRL_TXCLK_DISABLE |
2685 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2686 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2687 newbits1 = CLOCK_CTRL_625_CORE;
2688 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2690 newbits1 = CLOCK_CTRL_ALTCLK;
2691 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2694 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2697 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2700 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2703 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2704 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2705 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2706 CLOCK_CTRL_TXCLK_DISABLE |
2707 CLOCK_CTRL_44MHZ_CORE);
2709 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2712 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2713 tp->pci_clock_ctrl | newbits3, 40);
2717 if (!(device_should_wake) &&
2718 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2719 tg3_power_down_phy(tp, do_low_power);
2721 tg3_frob_aux_power(tp);
2723 /* Workaround for unstable PLL clock */
2724 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2725 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2726 u32 val = tr32(0x7d00);
2728 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2730 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2733 err = tg3_nvram_lock(tp);
2734 tg3_halt_cpu(tp, RX_CPU_BASE);
2736 tg3_nvram_unlock(tp);
2740 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2742 if (device_should_wake)
2743 pci_enable_wake(tp->pdev, state, true);
2745 /* Finally, set the new power state. */
2746 pci_set_power_state(tp->pdev, state);
2751 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2753 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2754 case MII_TG3_AUX_STAT_10HALF:
2756 *duplex = DUPLEX_HALF;
2759 case MII_TG3_AUX_STAT_10FULL:
2761 *duplex = DUPLEX_FULL;
2764 case MII_TG3_AUX_STAT_100HALF:
2766 *duplex = DUPLEX_HALF;
2769 case MII_TG3_AUX_STAT_100FULL:
2771 *duplex = DUPLEX_FULL;
2774 case MII_TG3_AUX_STAT_1000HALF:
2775 *speed = SPEED_1000;
2776 *duplex = DUPLEX_HALF;
2779 case MII_TG3_AUX_STAT_1000FULL:
2780 *speed = SPEED_1000;
2781 *duplex = DUPLEX_FULL;
2785 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2786 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2788 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2792 *speed = SPEED_INVALID;
2793 *duplex = DUPLEX_INVALID;
2798 static void tg3_phy_copper_begin(struct tg3 *tp)
2803 if (tp->link_config.phy_is_low_power) {
2804 /* Entering low power mode. Disable gigabit and
2805 * 100baseT advertisements.
2807 tg3_writephy(tp, MII_TG3_CTRL, 0);
2809 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2810 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2811 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2812 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2814 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2815 } else if (tp->link_config.speed == SPEED_INVALID) {
2816 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2817 tp->link_config.advertising &=
2818 ~(ADVERTISED_1000baseT_Half |
2819 ADVERTISED_1000baseT_Full);
2821 new_adv = ADVERTISE_CSMA;
2822 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2823 new_adv |= ADVERTISE_10HALF;
2824 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2825 new_adv |= ADVERTISE_10FULL;
2826 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2827 new_adv |= ADVERTISE_100HALF;
2828 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2829 new_adv |= ADVERTISE_100FULL;
2831 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2833 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2835 if (tp->link_config.advertising &
2836 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2838 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2839 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2840 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2841 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2842 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2843 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2844 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2845 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2846 MII_TG3_CTRL_ENABLE_AS_MASTER);
2847 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2849 tg3_writephy(tp, MII_TG3_CTRL, 0);
2852 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2853 new_adv |= ADVERTISE_CSMA;
2855 /* Asking for a specific link mode. */
2856 if (tp->link_config.speed == SPEED_1000) {
2857 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2859 if (tp->link_config.duplex == DUPLEX_FULL)
2860 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2862 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2863 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2864 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2865 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2866 MII_TG3_CTRL_ENABLE_AS_MASTER);
2868 if (tp->link_config.speed == SPEED_100) {
2869 if (tp->link_config.duplex == DUPLEX_FULL)
2870 new_adv |= ADVERTISE_100FULL;
2872 new_adv |= ADVERTISE_100HALF;
2874 if (tp->link_config.duplex == DUPLEX_FULL)
2875 new_adv |= ADVERTISE_10FULL;
2877 new_adv |= ADVERTISE_10HALF;
2879 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2884 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2887 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2888 tp->link_config.speed != SPEED_INVALID) {
2889 u32 bmcr, orig_bmcr;
2891 tp->link_config.active_speed = tp->link_config.speed;
2892 tp->link_config.active_duplex = tp->link_config.duplex;
2895 switch (tp->link_config.speed) {
2901 bmcr |= BMCR_SPEED100;
2905 bmcr |= TG3_BMCR_SPEED1000;
2909 if (tp->link_config.duplex == DUPLEX_FULL)
2910 bmcr |= BMCR_FULLDPLX;
2912 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2913 (bmcr != orig_bmcr)) {
2914 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2915 for (i = 0; i < 1500; i++) {
2919 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2920 tg3_readphy(tp, MII_BMSR, &tmp))
2922 if (!(tmp & BMSR_LSTATUS)) {
2927 tg3_writephy(tp, MII_BMCR, bmcr);
2931 tg3_writephy(tp, MII_BMCR,
2932 BMCR_ANENABLE | BMCR_ANRESTART);
2936 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2940 /* Turn off tap power management. */
2941 /* Set Extended packet length bit */
2942 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2944 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2945 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2947 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2948 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2950 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2951 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2953 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2954 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2956 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2957 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2964 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2966 u32 adv_reg, all_mask = 0;
2968 if (mask & ADVERTISED_10baseT_Half)
2969 all_mask |= ADVERTISE_10HALF;
2970 if (mask & ADVERTISED_10baseT_Full)
2971 all_mask |= ADVERTISE_10FULL;
2972 if (mask & ADVERTISED_100baseT_Half)
2973 all_mask |= ADVERTISE_100HALF;
2974 if (mask & ADVERTISED_100baseT_Full)
2975 all_mask |= ADVERTISE_100FULL;
2977 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2980 if ((adv_reg & all_mask) != all_mask)
2982 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2986 if (mask & ADVERTISED_1000baseT_Half)
2987 all_mask |= ADVERTISE_1000HALF;
2988 if (mask & ADVERTISED_1000baseT_Full)
2989 all_mask |= ADVERTISE_1000FULL;
2991 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2994 if ((tg3_ctrl & all_mask) != all_mask)
3000 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3004 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3007 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3008 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3010 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3011 if (curadv != reqadv)
3014 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3015 tg3_readphy(tp, MII_LPA, rmtadv);
3017 /* Reprogram the advertisement register, even if it
3018 * does not affect the current link. If the link
3019 * gets renegotiated in the future, we can save an
3020 * additional renegotiation cycle by advertising
3021 * it correctly in the first place.
3023 if (curadv != reqadv) {
3024 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3025 ADVERTISE_PAUSE_ASYM);
3026 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3033 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3035 int current_link_up;
3037 u32 lcl_adv, rmt_adv;
3045 (MAC_STATUS_SYNC_CHANGED |
3046 MAC_STATUS_CFG_CHANGED |
3047 MAC_STATUS_MI_COMPLETION |
3048 MAC_STATUS_LNKSTATE_CHANGED));
3051 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3053 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3057 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3059 /* Some third-party PHYs need to be reset on link going
3062 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3063 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3064 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3065 netif_carrier_ok(tp->dev)) {
3066 tg3_readphy(tp, MII_BMSR, &bmsr);
3067 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3068 !(bmsr & BMSR_LSTATUS))
3074 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3075 tg3_readphy(tp, MII_BMSR, &bmsr);
3076 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3077 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3080 if (!(bmsr & BMSR_LSTATUS)) {
3081 err = tg3_init_5401phy_dsp(tp);
3085 tg3_readphy(tp, MII_BMSR, &bmsr);
3086 for (i = 0; i < 1000; i++) {
3088 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3089 (bmsr & BMSR_LSTATUS)) {
3095 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3096 TG3_PHY_REV_BCM5401_B0 &&
3097 !(bmsr & BMSR_LSTATUS) &&
3098 tp->link_config.active_speed == SPEED_1000) {
3099 err = tg3_phy_reset(tp);
3101 err = tg3_init_5401phy_dsp(tp);
3106 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3107 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3108 /* 5701 {A0,B0} CRC bug workaround */
3109 tg3_writephy(tp, 0x15, 0x0a75);
3110 tg3_writephy(tp, 0x1c, 0x8c68);
3111 tg3_writephy(tp, 0x1c, 0x8d68);
3112 tg3_writephy(tp, 0x1c, 0x8c68);
3115 /* Clear pending interrupts... */
3116 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3117 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3119 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3120 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3121 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3122 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3124 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3125 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3126 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3127 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3128 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3130 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3133 current_link_up = 0;
3134 current_speed = SPEED_INVALID;
3135 current_duplex = DUPLEX_INVALID;
3137 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3140 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3141 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3142 if (!(val & (1 << 10))) {
3144 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3150 for (i = 0; i < 100; i++) {
3151 tg3_readphy(tp, MII_BMSR, &bmsr);
3152 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3153 (bmsr & BMSR_LSTATUS))
3158 if (bmsr & BMSR_LSTATUS) {
3161 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3162 for (i = 0; i < 2000; i++) {
3164 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3169 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3174 for (i = 0; i < 200; i++) {
3175 tg3_readphy(tp, MII_BMCR, &bmcr);
3176 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3178 if (bmcr && bmcr != 0x7fff)
3186 tp->link_config.active_speed = current_speed;
3187 tp->link_config.active_duplex = current_duplex;
3189 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3190 if ((bmcr & BMCR_ANENABLE) &&
3191 tg3_copper_is_advertising_all(tp,
3192 tp->link_config.advertising)) {
3193 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3195 current_link_up = 1;
3198 if (!(bmcr & BMCR_ANENABLE) &&
3199 tp->link_config.speed == current_speed &&
3200 tp->link_config.duplex == current_duplex &&
3201 tp->link_config.flowctrl ==
3202 tp->link_config.active_flowctrl) {
3203 current_link_up = 1;
3207 if (current_link_up == 1 &&
3208 tp->link_config.active_duplex == DUPLEX_FULL)
3209 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3213 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3216 tg3_phy_copper_begin(tp);
3218 tg3_readphy(tp, MII_BMSR, &tmp);
3219 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3220 (tmp & BMSR_LSTATUS))
3221 current_link_up = 1;
3224 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3225 if (current_link_up == 1) {
3226 if (tp->link_config.active_speed == SPEED_100 ||
3227 tp->link_config.active_speed == SPEED_10)
3228 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3230 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3231 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3232 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3234 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3236 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3237 if (tp->link_config.active_duplex == DUPLEX_HALF)
3238 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3240 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3241 if (current_link_up == 1 &&
3242 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3243 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3245 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3248 /* ??? Without this setting Netgear GA302T PHY does not
3249 * ??? send/receive packets...
3251 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3252 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3253 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3254 tw32_f(MAC_MI_MODE, tp->mi_mode);
3258 tw32_f(MAC_MODE, tp->mac_mode);
3261 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3262 /* Polled via timer. */
3263 tw32_f(MAC_EVENT, 0);
3265 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3269 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3270 current_link_up == 1 &&
3271 tp->link_config.active_speed == SPEED_1000 &&
3272 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3273 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3276 (MAC_STATUS_SYNC_CHANGED |
3277 MAC_STATUS_CFG_CHANGED));
3280 NIC_SRAM_FIRMWARE_MBOX,
3281 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3284 /* Prevent send BD corruption. */
3285 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3286 u16 oldlnkctl, newlnkctl;
3288 pci_read_config_word(tp->pdev,
3289 tp->pcie_cap + PCI_EXP_LNKCTL,
3291 if (tp->link_config.active_speed == SPEED_100 ||
3292 tp->link_config.active_speed == SPEED_10)
3293 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3295 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3296 if (newlnkctl != oldlnkctl)
3297 pci_write_config_word(tp->pdev,
3298 tp->pcie_cap + PCI_EXP_LNKCTL,
3302 if (current_link_up != netif_carrier_ok(tp->dev)) {
3303 if (current_link_up)
3304 netif_carrier_on(tp->dev);
3306 netif_carrier_off(tp->dev);
3307 tg3_link_report(tp);
3313 struct tg3_fiber_aneginfo {
3315 #define ANEG_STATE_UNKNOWN 0
3316 #define ANEG_STATE_AN_ENABLE 1
3317 #define ANEG_STATE_RESTART_INIT 2
3318 #define ANEG_STATE_RESTART 3
3319 #define ANEG_STATE_DISABLE_LINK_OK 4
3320 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3321 #define ANEG_STATE_ABILITY_DETECT 6
3322 #define ANEG_STATE_ACK_DETECT_INIT 7
3323 #define ANEG_STATE_ACK_DETECT 8
3324 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3325 #define ANEG_STATE_COMPLETE_ACK 10
3326 #define ANEG_STATE_IDLE_DETECT_INIT 11
3327 #define ANEG_STATE_IDLE_DETECT 12
3328 #define ANEG_STATE_LINK_OK 13
3329 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3330 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3333 #define MR_AN_ENABLE 0x00000001
3334 #define MR_RESTART_AN 0x00000002
3335 #define MR_AN_COMPLETE 0x00000004
3336 #define MR_PAGE_RX 0x00000008
3337 #define MR_NP_LOADED 0x00000010
3338 #define MR_TOGGLE_TX 0x00000020
3339 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3340 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3341 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3342 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3343 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3344 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3345 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3346 #define MR_TOGGLE_RX 0x00002000
3347 #define MR_NP_RX 0x00004000
3349 #define MR_LINK_OK 0x80000000
3351 unsigned long link_time, cur_time;
3353 u32 ability_match_cfg;
3354 int ability_match_count;
3356 char ability_match, idle_match, ack_match;
3358 u32 txconfig, rxconfig;
3359 #define ANEG_CFG_NP 0x00000080
3360 #define ANEG_CFG_ACK 0x00000040
3361 #define ANEG_CFG_RF2 0x00000020
3362 #define ANEG_CFG_RF1 0x00000010
3363 #define ANEG_CFG_PS2 0x00000001
3364 #define ANEG_CFG_PS1 0x00008000
3365 #define ANEG_CFG_HD 0x00004000
3366 #define ANEG_CFG_FD 0x00002000
3367 #define ANEG_CFG_INVAL 0x00001f06
3372 #define ANEG_TIMER_ENAB 2
3373 #define ANEG_FAILED -1
3375 #define ANEG_STATE_SETTLE_TIME 10000
3377 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3378 struct tg3_fiber_aneginfo *ap)
3381 unsigned long delta;
3385 if (ap->state == ANEG_STATE_UNKNOWN) {
3389 ap->ability_match_cfg = 0;
3390 ap->ability_match_count = 0;
3391 ap->ability_match = 0;
3397 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3398 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3400 if (rx_cfg_reg != ap->ability_match_cfg) {
3401 ap->ability_match_cfg = rx_cfg_reg;
3402 ap->ability_match = 0;
3403 ap->ability_match_count = 0;
3405 if (++ap->ability_match_count > 1) {
3406 ap->ability_match = 1;
3407 ap->ability_match_cfg = rx_cfg_reg;
3410 if (rx_cfg_reg & ANEG_CFG_ACK)
3418 ap->ability_match_cfg = 0;
3419 ap->ability_match_count = 0;
3420 ap->ability_match = 0;
3426 ap->rxconfig = rx_cfg_reg;
3429 switch (ap->state) {
3430 case ANEG_STATE_UNKNOWN:
3431 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3432 ap->state = ANEG_STATE_AN_ENABLE;
3435 case ANEG_STATE_AN_ENABLE:
3436 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3437 if (ap->flags & MR_AN_ENABLE) {
3440 ap->ability_match_cfg = 0;
3441 ap->ability_match_count = 0;
3442 ap->ability_match = 0;
3446 ap->state = ANEG_STATE_RESTART_INIT;
3448 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3452 case ANEG_STATE_RESTART_INIT:
3453 ap->link_time = ap->cur_time;
3454 ap->flags &= ~(MR_NP_LOADED);
3456 tw32(MAC_TX_AUTO_NEG, 0);
3457 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3458 tw32_f(MAC_MODE, tp->mac_mode);
3461 ret = ANEG_TIMER_ENAB;
3462 ap->state = ANEG_STATE_RESTART;
3465 case ANEG_STATE_RESTART:
3466 delta = ap->cur_time - ap->link_time;
3467 if (delta > ANEG_STATE_SETTLE_TIME)
3468 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3470 ret = ANEG_TIMER_ENAB;
3473 case ANEG_STATE_DISABLE_LINK_OK:
3477 case ANEG_STATE_ABILITY_DETECT_INIT:
3478 ap->flags &= ~(MR_TOGGLE_TX);
3479 ap->txconfig = ANEG_CFG_FD;
3480 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3481 if (flowctrl & ADVERTISE_1000XPAUSE)
3482 ap->txconfig |= ANEG_CFG_PS1;
3483 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3484 ap->txconfig |= ANEG_CFG_PS2;
3485 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3486 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3487 tw32_f(MAC_MODE, tp->mac_mode);
3490 ap->state = ANEG_STATE_ABILITY_DETECT;
3493 case ANEG_STATE_ABILITY_DETECT:
3494 if (ap->ability_match != 0 && ap->rxconfig != 0)
3495 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3498 case ANEG_STATE_ACK_DETECT_INIT:
3499 ap->txconfig |= ANEG_CFG_ACK;
3500 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3501 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3502 tw32_f(MAC_MODE, tp->mac_mode);
3505 ap->state = ANEG_STATE_ACK_DETECT;
3508 case ANEG_STATE_ACK_DETECT:
3509 if (ap->ack_match != 0) {
3510 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3511 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3512 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3514 ap->state = ANEG_STATE_AN_ENABLE;
3516 } else if (ap->ability_match != 0 &&
3517 ap->rxconfig == 0) {
3518 ap->state = ANEG_STATE_AN_ENABLE;
3522 case ANEG_STATE_COMPLETE_ACK_INIT:
3523 if (ap->rxconfig & ANEG_CFG_INVAL) {
3527 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3528 MR_LP_ADV_HALF_DUPLEX |
3529 MR_LP_ADV_SYM_PAUSE |
3530 MR_LP_ADV_ASYM_PAUSE |
3531 MR_LP_ADV_REMOTE_FAULT1 |
3532 MR_LP_ADV_REMOTE_FAULT2 |
3533 MR_LP_ADV_NEXT_PAGE |
3536 if (ap->rxconfig & ANEG_CFG_FD)
3537 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3538 if (ap->rxconfig & ANEG_CFG_HD)
3539 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3540 if (ap->rxconfig & ANEG_CFG_PS1)
3541 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3542 if (ap->rxconfig & ANEG_CFG_PS2)
3543 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3544 if (ap->rxconfig & ANEG_CFG_RF1)
3545 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3546 if (ap->rxconfig & ANEG_CFG_RF2)
3547 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3548 if (ap->rxconfig & ANEG_CFG_NP)
3549 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3551 ap->link_time = ap->cur_time;
3553 ap->flags ^= (MR_TOGGLE_TX);
3554 if (ap->rxconfig & 0x0008)
3555 ap->flags |= MR_TOGGLE_RX;
3556 if (ap->rxconfig & ANEG_CFG_NP)
3557 ap->flags |= MR_NP_RX;
3558 ap->flags |= MR_PAGE_RX;
3560 ap->state = ANEG_STATE_COMPLETE_ACK;
3561 ret = ANEG_TIMER_ENAB;
3564 case ANEG_STATE_COMPLETE_ACK:
3565 if (ap->ability_match != 0 &&
3566 ap->rxconfig == 0) {
3567 ap->state = ANEG_STATE_AN_ENABLE;
3570 delta = ap->cur_time - ap->link_time;
3571 if (delta > ANEG_STATE_SETTLE_TIME) {
3572 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3573 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3575 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3576 !(ap->flags & MR_NP_RX)) {
3577 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3585 case ANEG_STATE_IDLE_DETECT_INIT:
3586 ap->link_time = ap->cur_time;
3587 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3588 tw32_f(MAC_MODE, tp->mac_mode);
3591 ap->state = ANEG_STATE_IDLE_DETECT;
3592 ret = ANEG_TIMER_ENAB;
3595 case ANEG_STATE_IDLE_DETECT:
3596 if (ap->ability_match != 0 &&
3597 ap->rxconfig == 0) {
3598 ap->state = ANEG_STATE_AN_ENABLE;
3601 delta = ap->cur_time - ap->link_time;
3602 if (delta > ANEG_STATE_SETTLE_TIME) {
3603 /* XXX another gem from the Broadcom driver :( */
3604 ap->state = ANEG_STATE_LINK_OK;
3608 case ANEG_STATE_LINK_OK:
3609 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3613 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3614 /* ??? unimplemented */
3617 case ANEG_STATE_NEXT_PAGE_WAIT:
3618 /* ??? unimplemented */
3629 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3632 struct tg3_fiber_aneginfo aninfo;
3633 int status = ANEG_FAILED;
3637 tw32_f(MAC_TX_AUTO_NEG, 0);
3639 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3640 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3643 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3646 memset(&aninfo, 0, sizeof(aninfo));
3647 aninfo.flags |= MR_AN_ENABLE;
3648 aninfo.state = ANEG_STATE_UNKNOWN;
3649 aninfo.cur_time = 0;
3651 while (++tick < 195000) {
3652 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3653 if (status == ANEG_DONE || status == ANEG_FAILED)
3659 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3660 tw32_f(MAC_MODE, tp->mac_mode);
3663 *txflags = aninfo.txconfig;
3664 *rxflags = aninfo.flags;
3666 if (status == ANEG_DONE &&
3667 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3668 MR_LP_ADV_FULL_DUPLEX)))
3674 static void tg3_init_bcm8002(struct tg3 *tp)
3676 u32 mac_status = tr32(MAC_STATUS);
3679 /* Reset when initting first time or we have a link. */
3680 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3681 !(mac_status & MAC_STATUS_PCS_SYNCED))
3684 /* Set PLL lock range. */
3685 tg3_writephy(tp, 0x16, 0x8007);
3688 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3690 /* Wait for reset to complete. */
3691 /* XXX schedule_timeout() ... */
3692 for (i = 0; i < 500; i++)
3695 /* Config mode; select PMA/Ch 1 regs. */
3696 tg3_writephy(tp, 0x10, 0x8411);
3698 /* Enable auto-lock and comdet, select txclk for tx. */
3699 tg3_writephy(tp, 0x11, 0x0a10);
3701 tg3_writephy(tp, 0x18, 0x00a0);
3702 tg3_writephy(tp, 0x16, 0x41ff);
3704 /* Assert and deassert POR. */
3705 tg3_writephy(tp, 0x13, 0x0400);
3707 tg3_writephy(tp, 0x13, 0x0000);
3709 tg3_writephy(tp, 0x11, 0x0a50);
3711 tg3_writephy(tp, 0x11, 0x0a10);
3713 /* Wait for signal to stabilize */
3714 /* XXX schedule_timeout() ... */
3715 for (i = 0; i < 15000; i++)
3718 /* Deselect the channel register so we can read the PHYID
3721 tg3_writephy(tp, 0x10, 0x8011);
3724 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3727 u32 sg_dig_ctrl, sg_dig_status;
3728 u32 serdes_cfg, expected_sg_dig_ctrl;
3729 int workaround, port_a;
3730 int current_link_up;
3733 expected_sg_dig_ctrl = 0;
3736 current_link_up = 0;
3738 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3739 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3741 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3744 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3745 /* preserve bits 20-23 for voltage regulator */
3746 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3749 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3751 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3752 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3754 u32 val = serdes_cfg;
3760 tw32_f(MAC_SERDES_CFG, val);
3763 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3765 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3766 tg3_setup_flow_control(tp, 0, 0);
3767 current_link_up = 1;
3772 /* Want auto-negotiation. */
3773 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3775 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3776 if (flowctrl & ADVERTISE_1000XPAUSE)
3777 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3778 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3779 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3781 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3782 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3783 tp->serdes_counter &&
3784 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3785 MAC_STATUS_RCVD_CFG)) ==
3786 MAC_STATUS_PCS_SYNCED)) {
3787 tp->serdes_counter--;
3788 current_link_up = 1;
3793 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3794 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3796 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3798 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3799 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3800 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3801 MAC_STATUS_SIGNAL_DET)) {
3802 sg_dig_status = tr32(SG_DIG_STATUS);
3803 mac_status = tr32(MAC_STATUS);
3805 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3806 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3807 u32 local_adv = 0, remote_adv = 0;
3809 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3810 local_adv |= ADVERTISE_1000XPAUSE;
3811 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3812 local_adv |= ADVERTISE_1000XPSE_ASYM;
3814 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3815 remote_adv |= LPA_1000XPAUSE;
3816 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3817 remote_adv |= LPA_1000XPAUSE_ASYM;
3819 tg3_setup_flow_control(tp, local_adv, remote_adv);
3820 current_link_up = 1;
3821 tp->serdes_counter = 0;
3822 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3823 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3824 if (tp->serdes_counter)
3825 tp->serdes_counter--;
3828 u32 val = serdes_cfg;
3835 tw32_f(MAC_SERDES_CFG, val);
3838 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3841 /* Link parallel detection - link is up */
3842 /* only if we have PCS_SYNC and not */
3843 /* receiving config code words */
3844 mac_status = tr32(MAC_STATUS);
3845 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3846 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3847 tg3_setup_flow_control(tp, 0, 0);
3848 current_link_up = 1;
3850 TG3_FLG2_PARALLEL_DETECT;
3851 tp->serdes_counter =
3852 SERDES_PARALLEL_DET_TIMEOUT;
3854 goto restart_autoneg;
3858 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3859 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3863 return current_link_up;
3866 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3868 int current_link_up = 0;
3870 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3873 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3874 u32 txflags, rxflags;
3877 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3878 u32 local_adv = 0, remote_adv = 0;
3880 if (txflags & ANEG_CFG_PS1)
3881 local_adv |= ADVERTISE_1000XPAUSE;
3882 if (txflags & ANEG_CFG_PS2)
3883 local_adv |= ADVERTISE_1000XPSE_ASYM;
3885 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3886 remote_adv |= LPA_1000XPAUSE;
3887 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3888 remote_adv |= LPA_1000XPAUSE_ASYM;
3890 tg3_setup_flow_control(tp, local_adv, remote_adv);
3892 current_link_up = 1;
3894 for (i = 0; i < 30; i++) {
3897 (MAC_STATUS_SYNC_CHANGED |
3898 MAC_STATUS_CFG_CHANGED));
3900 if ((tr32(MAC_STATUS) &
3901 (MAC_STATUS_SYNC_CHANGED |
3902 MAC_STATUS_CFG_CHANGED)) == 0)
3906 mac_status = tr32(MAC_STATUS);
3907 if (current_link_up == 0 &&
3908 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3909 !(mac_status & MAC_STATUS_RCVD_CFG))
3910 current_link_up = 1;
3912 tg3_setup_flow_control(tp, 0, 0);
3914 /* Forcing 1000FD link up. */
3915 current_link_up = 1;
3917 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3920 tw32_f(MAC_MODE, tp->mac_mode);
3925 return current_link_up;
3928 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3931 u16 orig_active_speed;
3932 u8 orig_active_duplex;
3934 int current_link_up;
3937 orig_pause_cfg = tp->link_config.active_flowctrl;
3938 orig_active_speed = tp->link_config.active_speed;
3939 orig_active_duplex = tp->link_config.active_duplex;
3941 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3942 netif_carrier_ok(tp->dev) &&
3943 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3944 mac_status = tr32(MAC_STATUS);
3945 mac_status &= (MAC_STATUS_PCS_SYNCED |
3946 MAC_STATUS_SIGNAL_DET |
3947 MAC_STATUS_CFG_CHANGED |
3948 MAC_STATUS_RCVD_CFG);
3949 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3950 MAC_STATUS_SIGNAL_DET)) {
3951 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3952 MAC_STATUS_CFG_CHANGED));
3957 tw32_f(MAC_TX_AUTO_NEG, 0);
3959 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3960 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3961 tw32_f(MAC_MODE, tp->mac_mode);
3964 if (tp->phy_id == TG3_PHY_ID_BCM8002)
3965 tg3_init_bcm8002(tp);
3967 /* Enable link change event even when serdes polling. */
3968 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3971 current_link_up = 0;
3972 mac_status = tr32(MAC_STATUS);
3974 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3975 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3977 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3979 tp->napi[0].hw_status->status =
3980 (SD_STATUS_UPDATED |
3981 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3983 for (i = 0; i < 100; i++) {
3984 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3985 MAC_STATUS_CFG_CHANGED));
3987 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3988 MAC_STATUS_CFG_CHANGED |
3989 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3993 mac_status = tr32(MAC_STATUS);
3994 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3995 current_link_up = 0;
3996 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3997 tp->serdes_counter == 0) {
3998 tw32_f(MAC_MODE, (tp->mac_mode |
3999 MAC_MODE_SEND_CONFIGS));
4001 tw32_f(MAC_MODE, tp->mac_mode);
4005 if (current_link_up == 1) {
4006 tp->link_config.active_speed = SPEED_1000;
4007 tp->link_config.active_duplex = DUPLEX_FULL;
4008 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4009 LED_CTRL_LNKLED_OVERRIDE |
4010 LED_CTRL_1000MBPS_ON));
4012 tp->link_config.active_speed = SPEED_INVALID;
4013 tp->link_config.active_duplex = DUPLEX_INVALID;
4014 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4015 LED_CTRL_LNKLED_OVERRIDE |
4016 LED_CTRL_TRAFFIC_OVERRIDE));
4019 if (current_link_up != netif_carrier_ok(tp->dev)) {
4020 if (current_link_up)
4021 netif_carrier_on(tp->dev);
4023 netif_carrier_off(tp->dev);
4024 tg3_link_report(tp);
4026 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4027 if (orig_pause_cfg != now_pause_cfg ||
4028 orig_active_speed != tp->link_config.active_speed ||
4029 orig_active_duplex != tp->link_config.active_duplex)
4030 tg3_link_report(tp);
4036 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4038 int current_link_up, err = 0;
4042 u32 local_adv, remote_adv;
4044 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4045 tw32_f(MAC_MODE, tp->mac_mode);
4051 (MAC_STATUS_SYNC_CHANGED |
4052 MAC_STATUS_CFG_CHANGED |
4053 MAC_STATUS_MI_COMPLETION |
4054 MAC_STATUS_LNKSTATE_CHANGED));
4060 current_link_up = 0;
4061 current_speed = SPEED_INVALID;
4062 current_duplex = DUPLEX_INVALID;
4064 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4065 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4066 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4067 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4068 bmsr |= BMSR_LSTATUS;
4070 bmsr &= ~BMSR_LSTATUS;
4073 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4075 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4076 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4077 /* do nothing, just check for link up at the end */
4078 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4081 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4082 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4083 ADVERTISE_1000XPAUSE |
4084 ADVERTISE_1000XPSE_ASYM |
4087 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4089 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4090 new_adv |= ADVERTISE_1000XHALF;
4091 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4092 new_adv |= ADVERTISE_1000XFULL;
4094 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4095 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4096 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4097 tg3_writephy(tp, MII_BMCR, bmcr);
4099 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4100 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4101 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4108 bmcr &= ~BMCR_SPEED1000;
4109 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4111 if (tp->link_config.duplex == DUPLEX_FULL)
4112 new_bmcr |= BMCR_FULLDPLX;
4114 if (new_bmcr != bmcr) {
4115 /* BMCR_SPEED1000 is a reserved bit that needs
4116 * to be set on write.
4118 new_bmcr |= BMCR_SPEED1000;
4120 /* Force a linkdown */
4121 if (netif_carrier_ok(tp->dev)) {
4124 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4125 adv &= ~(ADVERTISE_1000XFULL |
4126 ADVERTISE_1000XHALF |
4128 tg3_writephy(tp, MII_ADVERTISE, adv);
4129 tg3_writephy(tp, MII_BMCR, bmcr |
4133 netif_carrier_off(tp->dev);
4135 tg3_writephy(tp, MII_BMCR, new_bmcr);
4137 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4138 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4139 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4141 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4142 bmsr |= BMSR_LSTATUS;
4144 bmsr &= ~BMSR_LSTATUS;
4146 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4150 if (bmsr & BMSR_LSTATUS) {
4151 current_speed = SPEED_1000;
4152 current_link_up = 1;
4153 if (bmcr & BMCR_FULLDPLX)
4154 current_duplex = DUPLEX_FULL;
4156 current_duplex = DUPLEX_HALF;
4161 if (bmcr & BMCR_ANENABLE) {
4164 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4165 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4166 common = local_adv & remote_adv;
4167 if (common & (ADVERTISE_1000XHALF |
4168 ADVERTISE_1000XFULL)) {
4169 if (common & ADVERTISE_1000XFULL)
4170 current_duplex = DUPLEX_FULL;
4172 current_duplex = DUPLEX_HALF;
4174 current_link_up = 0;
4179 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4180 tg3_setup_flow_control(tp, local_adv, remote_adv);
4182 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4183 if (tp->link_config.active_duplex == DUPLEX_HALF)
4184 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4186 tw32_f(MAC_MODE, tp->mac_mode);
4189 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4191 tp->link_config.active_speed = current_speed;
4192 tp->link_config.active_duplex = current_duplex;
4194 if (current_link_up != netif_carrier_ok(tp->dev)) {
4195 if (current_link_up)
4196 netif_carrier_on(tp->dev);
4198 netif_carrier_off(tp->dev);
4199 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4201 tg3_link_report(tp);
4206 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4208 if (tp->serdes_counter) {
4209 /* Give autoneg time to complete. */
4210 tp->serdes_counter--;
4214 if (!netif_carrier_ok(tp->dev) &&
4215 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4218 tg3_readphy(tp, MII_BMCR, &bmcr);
4219 if (bmcr & BMCR_ANENABLE) {
4222 /* Select shadow register 0x1f */
4223 tg3_writephy(tp, 0x1c, 0x7c00);
4224 tg3_readphy(tp, 0x1c, &phy1);
4226 /* Select expansion interrupt status register */
4227 tg3_writephy(tp, 0x17, 0x0f01);
4228 tg3_readphy(tp, 0x15, &phy2);
4229 tg3_readphy(tp, 0x15, &phy2);
4231 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4232 /* We have signal detect and not receiving
4233 * config code words, link is up by parallel
4237 bmcr &= ~BMCR_ANENABLE;
4238 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4239 tg3_writephy(tp, MII_BMCR, bmcr);
4240 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4243 } else if (netif_carrier_ok(tp->dev) &&
4244 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4245 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4248 /* Select expansion interrupt status register */
4249 tg3_writephy(tp, 0x17, 0x0f01);
4250 tg3_readphy(tp, 0x15, &phy2);
4254 /* Config code words received, turn on autoneg. */
4255 tg3_readphy(tp, MII_BMCR, &bmcr);
4256 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4258 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4264 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4268 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
4269 err = tg3_setup_fiber_phy(tp, force_reset);
4270 else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
4271 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4273 err = tg3_setup_copper_phy(tp, force_reset);
4275 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4278 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4279 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4281 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4286 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4287 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4288 tw32(GRC_MISC_CFG, val);
4291 if (tp->link_config.active_speed == SPEED_1000 &&
4292 tp->link_config.active_duplex == DUPLEX_HALF)
4293 tw32(MAC_TX_LENGTHS,
4294 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4295 (6 << TX_LENGTHS_IPG_SHIFT) |
4296 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4298 tw32(MAC_TX_LENGTHS,
4299 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4300 (6 << TX_LENGTHS_IPG_SHIFT) |
4301 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4303 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4304 if (netif_carrier_ok(tp->dev)) {
4305 tw32(HOSTCC_STAT_COAL_TICKS,
4306 tp->coal.stats_block_coalesce_usecs);
4308 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4312 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4313 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4314 if (!netif_carrier_ok(tp->dev))
4315 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4318 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4319 tw32(PCIE_PWR_MGMT_THRESH, val);
4325 /* This is called whenever we suspect that the system chipset is re-
4326 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4327 * is bogus tx completions. We try to recover by setting the
4328 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4331 static void tg3_tx_recover(struct tg3 *tp)
4333 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4334 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4336 netdev_warn(tp->dev,
4337 "The system may be re-ordering memory-mapped I/O "
4338 "cycles to the network device, attempting to recover. "
4339 "Please report the problem to the driver maintainer "
4340 "and include system chipset information.\n");
4342 spin_lock(&tp->lock);
4343 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4344 spin_unlock(&tp->lock);
4347 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4350 return tnapi->tx_pending -
4351 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4354 /* Tigon3 never reports partial packet sends. So we do not
4355 * need special logic to handle SKBs that have not had all
4356 * of their frags sent yet, like SunGEM does.
4358 static void tg3_tx(struct tg3_napi *tnapi)
4360 struct tg3 *tp = tnapi->tp;
4361 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4362 u32 sw_idx = tnapi->tx_cons;
4363 struct netdev_queue *txq;
4364 int index = tnapi - tp->napi;
4366 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4369 txq = netdev_get_tx_queue(tp->dev, index);
4371 while (sw_idx != hw_idx) {
4372 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4373 struct sk_buff *skb = ri->skb;
4376 if (unlikely(skb == NULL)) {
4381 pci_unmap_single(tp->pdev,
4382 pci_unmap_addr(ri, mapping),
4388 sw_idx = NEXT_TX(sw_idx);
4390 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4391 ri = &tnapi->tx_buffers[sw_idx];
4392 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4395 pci_unmap_page(tp->pdev,
4396 pci_unmap_addr(ri, mapping),
4397 skb_shinfo(skb)->frags[i].size,
4399 sw_idx = NEXT_TX(sw_idx);
4404 if (unlikely(tx_bug)) {
4410 tnapi->tx_cons = sw_idx;
4412 /* Need to make the tx_cons update visible to tg3_start_xmit()
4413 * before checking for netif_queue_stopped(). Without the
4414 * memory barrier, there is a small possibility that tg3_start_xmit()
4415 * will miss it and cause the queue to be stopped forever.
4419 if (unlikely(netif_tx_queue_stopped(txq) &&
4420 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4421 __netif_tx_lock(txq, smp_processor_id());
4422 if (netif_tx_queue_stopped(txq) &&
4423 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4424 netif_tx_wake_queue(txq);
4425 __netif_tx_unlock(txq);
4429 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4434 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4435 map_sz, PCI_DMA_FROMDEVICE);
4436 dev_kfree_skb_any(ri->skb);
4440 /* Returns size of skb allocated or < 0 on error.
4442 * We only need to fill in the address because the other members
4443 * of the RX descriptor are invariant, see tg3_init_rings.
4445 * Note the purposeful assymetry of cpu vs. chip accesses. For
4446 * posting buffers we only dirty the first cache line of the RX
4447 * descriptor (containing the address). Whereas for the RX status
4448 * buffers the cpu only reads the last cacheline of the RX descriptor
4449 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4451 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4452 u32 opaque_key, u32 dest_idx_unmasked)
4454 struct tg3_rx_buffer_desc *desc;
4455 struct ring_info *map, *src_map;
4456 struct sk_buff *skb;
4458 int skb_size, dest_idx;
4461 switch (opaque_key) {
4462 case RXD_OPAQUE_RING_STD:
4463 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4464 desc = &tpr->rx_std[dest_idx];
4465 map = &tpr->rx_std_buffers[dest_idx];
4466 skb_size = tp->rx_pkt_map_sz;
4469 case RXD_OPAQUE_RING_JUMBO:
4470 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4471 desc = &tpr->rx_jmb[dest_idx].std;
4472 map = &tpr->rx_jmb_buffers[dest_idx];
4473 skb_size = TG3_RX_JMB_MAP_SZ;
4480 /* Do not overwrite any of the map or rp information
4481 * until we are sure we can commit to a new buffer.
4483 * Callers depend upon this behavior and assume that
4484 * we leave everything unchanged if we fail.
4486 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4490 skb_reserve(skb, tp->rx_offset);
4492 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4493 PCI_DMA_FROMDEVICE);
4494 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4500 pci_unmap_addr_set(map, mapping, mapping);
4502 desc->addr_hi = ((u64)mapping >> 32);
4503 desc->addr_lo = ((u64)mapping & 0xffffffff);
4508 /* We only need to move over in the address because the other
4509 * members of the RX descriptor are invariant. See notes above
4510 * tg3_alloc_rx_skb for full details.
4512 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4513 struct tg3_rx_prodring_set *dpr,
4514 u32 opaque_key, int src_idx,
4515 u32 dest_idx_unmasked)
4517 struct tg3 *tp = tnapi->tp;
4518 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4519 struct ring_info *src_map, *dest_map;
4520 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4523 switch (opaque_key) {
4524 case RXD_OPAQUE_RING_STD:
4525 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4526 dest_desc = &dpr->rx_std[dest_idx];
4527 dest_map = &dpr->rx_std_buffers[dest_idx];
4528 src_desc = &spr->rx_std[src_idx];
4529 src_map = &spr->rx_std_buffers[src_idx];
4532 case RXD_OPAQUE_RING_JUMBO:
4533 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4534 dest_desc = &dpr->rx_jmb[dest_idx].std;
4535 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4536 src_desc = &spr->rx_jmb[src_idx].std;
4537 src_map = &spr->rx_jmb_buffers[src_idx];
4544 dest_map->skb = src_map->skb;
4545 pci_unmap_addr_set(dest_map, mapping,
4546 pci_unmap_addr(src_map, mapping));
4547 dest_desc->addr_hi = src_desc->addr_hi;
4548 dest_desc->addr_lo = src_desc->addr_lo;
4550 /* Ensure that the update to the skb happens after the physical
4551 * addresses have been transferred to the new BD location.
4555 src_map->skb = NULL;
4558 /* The RX ring scheme is composed of multiple rings which post fresh
4559 * buffers to the chip, and one special ring the chip uses to report
4560 * status back to the host.
4562 * The special ring reports the status of received packets to the
4563 * host. The chip does not write into the original descriptor the
4564 * RX buffer was obtained from. The chip simply takes the original
4565 * descriptor as provided by the host, updates the status and length
4566 * field, then writes this into the next status ring entry.
4568 * Each ring the host uses to post buffers to the chip is described
4569 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4570 * it is first placed into the on-chip ram. When the packet's length
4571 * is known, it walks down the TG3_BDINFO entries to select the ring.
4572 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4573 * which is within the range of the new packet's length is chosen.
4575 * The "separate ring for rx status" scheme may sound queer, but it makes
4576 * sense from a cache coherency perspective. If only the host writes
4577 * to the buffer post rings, and only the chip writes to the rx status
4578 * rings, then cache lines never move beyond shared-modified state.
4579 * If both the host and chip were to write into the same ring, cache line
4580 * eviction could occur since both entities want it in an exclusive state.
4582 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4584 struct tg3 *tp = tnapi->tp;
4585 u32 work_mask, rx_std_posted = 0;
4586 u32 std_prod_idx, jmb_prod_idx;
4587 u32 sw_idx = tnapi->rx_rcb_ptr;
4590 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4592 hw_idx = *(tnapi->rx_rcb_prod_idx);
4594 * We need to order the read of hw_idx and the read of
4595 * the opaque cookie.
4600 std_prod_idx = tpr->rx_std_prod_idx;
4601 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4602 while (sw_idx != hw_idx && budget > 0) {
4603 struct ring_info *ri;
4604 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4606 struct sk_buff *skb;
4607 dma_addr_t dma_addr;
4608 u32 opaque_key, desc_idx, *post_ptr;
4610 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4611 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4612 if (opaque_key == RXD_OPAQUE_RING_STD) {
4613 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4614 dma_addr = pci_unmap_addr(ri, mapping);
4616 post_ptr = &std_prod_idx;
4618 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4619 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4620 dma_addr = pci_unmap_addr(ri, mapping);
4622 post_ptr = &jmb_prod_idx;
4624 goto next_pkt_nopost;
4626 work_mask |= opaque_key;
4628 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4629 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4631 tg3_recycle_rx(tnapi, tpr, opaque_key,
4632 desc_idx, *post_ptr);
4634 /* Other statistics kept track of by card. */
4635 tp->net_stats.rx_dropped++;
4639 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4642 if (len > RX_COPY_THRESHOLD &&
4643 tp->rx_offset == NET_IP_ALIGN) {
4644 /* rx_offset will likely not equal NET_IP_ALIGN
4645 * if this is a 5701 card running in PCI-X mode
4646 * [see tg3_get_invariants()]
4650 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4655 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4656 PCI_DMA_FROMDEVICE);
4658 /* Ensure that the update to the skb happens
4659 * after the usage of the old DMA mapping.
4667 struct sk_buff *copy_skb;
4669 tg3_recycle_rx(tnapi, tpr, opaque_key,
4670 desc_idx, *post_ptr);
4672 copy_skb = netdev_alloc_skb(tp->dev,
4673 len + TG3_RAW_IP_ALIGN);
4674 if (copy_skb == NULL)
4675 goto drop_it_no_recycle;
4677 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4678 skb_put(copy_skb, len);
4679 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4680 skb_copy_from_linear_data(skb, copy_skb->data, len);
4681 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4683 /* We'll reuse the original ring buffer. */
4687 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4688 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4689 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4690 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4691 skb->ip_summed = CHECKSUM_UNNECESSARY;
4693 skb->ip_summed = CHECKSUM_NONE;
4695 skb->protocol = eth_type_trans(skb, tp->dev);
4697 if (len > (tp->dev->mtu + ETH_HLEN) &&
4698 skb->protocol != htons(ETH_P_8021Q)) {
4703 #if TG3_VLAN_TAG_USED
4704 if (tp->vlgrp != NULL &&
4705 desc->type_flags & RXD_FLAG_VLAN) {
4706 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4707 desc->err_vlan & RXD_VLAN_MASK, skb);
4710 napi_gro_receive(&tnapi->napi, skb);
4718 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4719 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4720 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4721 tpr->rx_std_prod_idx);
4722 work_mask &= ~RXD_OPAQUE_RING_STD;
4727 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4729 /* Refresh hw_idx to see if there is new work */
4730 if (sw_idx == hw_idx) {
4731 hw_idx = *(tnapi->rx_rcb_prod_idx);
4736 /* ACK the status ring. */
4737 tnapi->rx_rcb_ptr = sw_idx;
4738 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4740 /* Refill RX ring(s). */
4741 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4742 if (work_mask & RXD_OPAQUE_RING_STD) {
4743 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4744 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4745 tpr->rx_std_prod_idx);
4747 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4748 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4749 TG3_RX_JUMBO_RING_SIZE;
4750 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4751 tpr->rx_jmb_prod_idx);
4754 } else if (work_mask) {
4755 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4756 * updated before the producer indices can be updated.
4760 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4761 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4763 if (tnapi != &tp->napi[1])
4764 napi_schedule(&tp->napi[1].napi);
4770 static void tg3_poll_link(struct tg3 *tp)
4772 /* handle link change and other phy events */
4773 if (!(tp->tg3_flags &
4774 (TG3_FLAG_USE_LINKCHG_REG |
4775 TG3_FLAG_POLL_SERDES))) {
4776 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4778 if (sblk->status & SD_STATUS_LINK_CHG) {
4779 sblk->status = SD_STATUS_UPDATED |
4780 (sblk->status & ~SD_STATUS_LINK_CHG);
4781 spin_lock(&tp->lock);
4782 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4784 (MAC_STATUS_SYNC_CHANGED |
4785 MAC_STATUS_CFG_CHANGED |
4786 MAC_STATUS_MI_COMPLETION |
4787 MAC_STATUS_LNKSTATE_CHANGED));
4790 tg3_setup_phy(tp, 0);
4791 spin_unlock(&tp->lock);
4796 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4797 struct tg3_rx_prodring_set *dpr,
4798 struct tg3_rx_prodring_set *spr)
4800 u32 si, di, cpycnt, src_prod_idx;
4804 src_prod_idx = spr->rx_std_prod_idx;
4806 /* Make sure updates to the rx_std_buffers[] entries and the
4807 * standard producer index are seen in the correct order.
4811 if (spr->rx_std_cons_idx == src_prod_idx)
4814 if (spr->rx_std_cons_idx < src_prod_idx)
4815 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4817 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4819 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4821 si = spr->rx_std_cons_idx;
4822 di = dpr->rx_std_prod_idx;
4824 for (i = di; i < di + cpycnt; i++) {
4825 if (dpr->rx_std_buffers[i].skb) {
4835 /* Ensure that updates to the rx_std_buffers ring and the
4836 * shadowed hardware producer ring from tg3_recycle_skb() are
4837 * ordered correctly WRT the skb check above.
4841 memcpy(&dpr->rx_std_buffers[di],
4842 &spr->rx_std_buffers[si],
4843 cpycnt * sizeof(struct ring_info));
4845 for (i = 0; i < cpycnt; i++, di++, si++) {
4846 struct tg3_rx_buffer_desc *sbd, *dbd;
4847 sbd = &spr->rx_std[si];
4848 dbd = &dpr->rx_std[di];
4849 dbd->addr_hi = sbd->addr_hi;
4850 dbd->addr_lo = sbd->addr_lo;
4853 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4855 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4860 src_prod_idx = spr->rx_jmb_prod_idx;
4862 /* Make sure updates to the rx_jmb_buffers[] entries and
4863 * the jumbo producer index are seen in the correct order.
4867 if (spr->rx_jmb_cons_idx == src_prod_idx)
4870 if (spr->rx_jmb_cons_idx < src_prod_idx)
4871 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4873 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4875 cpycnt = min(cpycnt,
4876 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4878 si = spr->rx_jmb_cons_idx;
4879 di = dpr->rx_jmb_prod_idx;
4881 for (i = di; i < di + cpycnt; i++) {
4882 if (dpr->rx_jmb_buffers[i].skb) {
4892 /* Ensure that updates to the rx_jmb_buffers ring and the
4893 * shadowed hardware producer ring from tg3_recycle_skb() are
4894 * ordered correctly WRT the skb check above.
4898 memcpy(&dpr->rx_jmb_buffers[di],
4899 &spr->rx_jmb_buffers[si],
4900 cpycnt * sizeof(struct ring_info));
4902 for (i = 0; i < cpycnt; i++, di++, si++) {
4903 struct tg3_rx_buffer_desc *sbd, *dbd;
4904 sbd = &spr->rx_jmb[si].std;
4905 dbd = &dpr->rx_jmb[di].std;
4906 dbd->addr_hi = sbd->addr_hi;
4907 dbd->addr_lo = sbd->addr_lo;
4910 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4911 TG3_RX_JUMBO_RING_SIZE;
4912 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4913 TG3_RX_JUMBO_RING_SIZE;
4919 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4921 struct tg3 *tp = tnapi->tp;
4923 /* run TX completion thread */
4924 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4926 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4930 /* run RX thread, within the bounds set by NAPI.
4931 * All RX "locking" is done by ensuring outside
4932 * code synchronizes with tg3->napi.poll()
4934 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4935 work_done += tg3_rx(tnapi, budget - work_done);
4937 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4938 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4940 u32 std_prod_idx = dpr->rx_std_prod_idx;
4941 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4943 for (i = 1; i < tp->irq_cnt; i++)
4944 err |= tg3_rx_prodring_xfer(tp, dpr,
4945 tp->napi[i].prodring);
4949 if (std_prod_idx != dpr->rx_std_prod_idx)
4950 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4951 dpr->rx_std_prod_idx);
4953 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4954 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4955 dpr->rx_jmb_prod_idx);
4960 tw32_f(HOSTCC_MODE, tp->coal_now);
4966 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4968 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4969 struct tg3 *tp = tnapi->tp;
4971 struct tg3_hw_status *sblk = tnapi->hw_status;
4974 work_done = tg3_poll_work(tnapi, work_done, budget);
4976 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4979 if (unlikely(work_done >= budget))
4982 /* tp->last_tag is used in tg3_int_reenable() below
4983 * to tell the hw how much work has been processed,
4984 * so we must read it before checking for more work.
4986 tnapi->last_tag = sblk->status_tag;
4987 tnapi->last_irq_tag = tnapi->last_tag;
4990 /* check for RX/TX work to do */
4991 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4992 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
4993 napi_complete(napi);
4994 /* Reenable interrupts. */
4995 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5004 /* work_done is guaranteed to be less than budget. */
5005 napi_complete(napi);
5006 schedule_work(&tp->reset_task);
5010 static int tg3_poll(struct napi_struct *napi, int budget)
5012 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5013 struct tg3 *tp = tnapi->tp;
5015 struct tg3_hw_status *sblk = tnapi->hw_status;
5020 work_done = tg3_poll_work(tnapi, work_done, budget);
5022 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5025 if (unlikely(work_done >= budget))
5028 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5029 /* tp->last_tag is used in tg3_int_reenable() below
5030 * to tell the hw how much work has been processed,
5031 * so we must read it before checking for more work.
5033 tnapi->last_tag = sblk->status_tag;
5034 tnapi->last_irq_tag = tnapi->last_tag;
5037 sblk->status &= ~SD_STATUS_UPDATED;
5039 if (likely(!tg3_has_work(tnapi))) {
5040 napi_complete(napi);
5041 tg3_int_reenable(tnapi);
5049 /* work_done is guaranteed to be less than budget. */
5050 napi_complete(napi);
5051 schedule_work(&tp->reset_task);
5055 static void tg3_irq_quiesce(struct tg3 *tp)
5059 BUG_ON(tp->irq_sync);
5064 for (i = 0; i < tp->irq_cnt; i++)
5065 synchronize_irq(tp->napi[i].irq_vec);
5068 static inline int tg3_irq_sync(struct tg3 *tp)
5070 return tp->irq_sync;
5073 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5074 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5075 * with as well. Most of the time, this is not necessary except when
5076 * shutting down the device.
5078 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5080 spin_lock_bh(&tp->lock);
5082 tg3_irq_quiesce(tp);
5085 static inline void tg3_full_unlock(struct tg3 *tp)
5087 spin_unlock_bh(&tp->lock);
5090 /* One-shot MSI handler - Chip automatically disables interrupt
5091 * after sending MSI so driver doesn't have to do it.
5093 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5095 struct tg3_napi *tnapi = dev_id;
5096 struct tg3 *tp = tnapi->tp;
5098 prefetch(tnapi->hw_status);
5100 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5102 if (likely(!tg3_irq_sync(tp)))
5103 napi_schedule(&tnapi->napi);
5108 /* MSI ISR - No need to check for interrupt sharing and no need to
5109 * flush status block and interrupt mailbox. PCI ordering rules
5110 * guarantee that MSI will arrive after the status block.
5112 static irqreturn_t tg3_msi(int irq, void *dev_id)
5114 struct tg3_napi *tnapi = dev_id;
5115 struct tg3 *tp = tnapi->tp;
5117 prefetch(tnapi->hw_status);
5119 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5121 * Writing any value to intr-mbox-0 clears PCI INTA# and
5122 * chip-internal interrupt pending events.
5123 * Writing non-zero to intr-mbox-0 additional tells the
5124 * NIC to stop sending us irqs, engaging "in-intr-handler"
5127 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5128 if (likely(!tg3_irq_sync(tp)))
5129 napi_schedule(&tnapi->napi);
5131 return IRQ_RETVAL(1);
5134 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5136 struct tg3_napi *tnapi = dev_id;
5137 struct tg3 *tp = tnapi->tp;
5138 struct tg3_hw_status *sblk = tnapi->hw_status;
5139 unsigned int handled = 1;
5141 /* In INTx mode, it is possible for the interrupt to arrive at
5142 * the CPU before the status block posted prior to the interrupt.
5143 * Reading the PCI State register will confirm whether the
5144 * interrupt is ours and will flush the status block.
5146 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5147 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5148 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5155 * Writing any value to intr-mbox-0 clears PCI INTA# and
5156 * chip-internal interrupt pending events.
5157 * Writing non-zero to intr-mbox-0 additional tells the
5158 * NIC to stop sending us irqs, engaging "in-intr-handler"
5161 * Flush the mailbox to de-assert the IRQ immediately to prevent
5162 * spurious interrupts. The flush impacts performance but
5163 * excessive spurious interrupts can be worse in some cases.
5165 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5166 if (tg3_irq_sync(tp))
5168 sblk->status &= ~SD_STATUS_UPDATED;
5169 if (likely(tg3_has_work(tnapi))) {
5170 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5171 napi_schedule(&tnapi->napi);
5173 /* No work, shared interrupt perhaps? re-enable
5174 * interrupts, and flush that PCI write
5176 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5180 return IRQ_RETVAL(handled);
5183 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5185 struct tg3_napi *tnapi = dev_id;
5186 struct tg3 *tp = tnapi->tp;
5187 struct tg3_hw_status *sblk = tnapi->hw_status;
5188 unsigned int handled = 1;
5190 /* In INTx mode, it is possible for the interrupt to arrive at
5191 * the CPU before the status block posted prior to the interrupt.
5192 * Reading the PCI State register will confirm whether the
5193 * interrupt is ours and will flush the status block.
5195 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5196 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5197 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5204 * writing any value to intr-mbox-0 clears PCI INTA# and
5205 * chip-internal interrupt pending events.
5206 * writing non-zero to intr-mbox-0 additional tells the
5207 * NIC to stop sending us irqs, engaging "in-intr-handler"
5210 * Flush the mailbox to de-assert the IRQ immediately to prevent
5211 * spurious interrupts. The flush impacts performance but
5212 * excessive spurious interrupts can be worse in some cases.
5214 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5217 * In a shared interrupt configuration, sometimes other devices'
5218 * interrupts will scream. We record the current status tag here
5219 * so that the above check can report that the screaming interrupts
5220 * are unhandled. Eventually they will be silenced.
5222 tnapi->last_irq_tag = sblk->status_tag;
5224 if (tg3_irq_sync(tp))
5227 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5229 napi_schedule(&tnapi->napi);
5232 return IRQ_RETVAL(handled);
5235 /* ISR for interrupt test */
5236 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5238 struct tg3_napi *tnapi = dev_id;
5239 struct tg3 *tp = tnapi->tp;
5240 struct tg3_hw_status *sblk = tnapi->hw_status;
5242 if ((sblk->status & SD_STATUS_UPDATED) ||
5243 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5244 tg3_disable_ints(tp);
5245 return IRQ_RETVAL(1);
5247 return IRQ_RETVAL(0);
5250 static int tg3_init_hw(struct tg3 *, int);
5251 static int tg3_halt(struct tg3 *, int, int);
5253 /* Restart hardware after configuration changes, self-test, etc.
5254 * Invoked with tp->lock held.
5256 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5257 __releases(tp->lock)
5258 __acquires(tp->lock)
5262 err = tg3_init_hw(tp, reset_phy);
5265 "Failed to re-initialize device, aborting\n");
5266 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5267 tg3_full_unlock(tp);
5268 del_timer_sync(&tp->timer);
5270 tg3_napi_enable(tp);
5272 tg3_full_lock(tp, 0);
5277 #ifdef CONFIG_NET_POLL_CONTROLLER
5278 static void tg3_poll_controller(struct net_device *dev)
5281 struct tg3 *tp = netdev_priv(dev);
5283 for (i = 0; i < tp->irq_cnt; i++)
5284 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5288 static void tg3_reset_task(struct work_struct *work)
5290 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5292 unsigned int restart_timer;
5294 tg3_full_lock(tp, 0);
5296 if (!netif_running(tp->dev)) {
5297 tg3_full_unlock(tp);
5301 tg3_full_unlock(tp);
5307 tg3_full_lock(tp, 1);
5309 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5310 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5312 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5313 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5314 tp->write32_rx_mbox = tg3_write_flush_reg32;
5315 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5316 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5319 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5320 err = tg3_init_hw(tp, 1);
5324 tg3_netif_start(tp);
5327 mod_timer(&tp->timer, jiffies + 1);
5330 tg3_full_unlock(tp);
5336 static void tg3_dump_short_state(struct tg3 *tp)
5338 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5339 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5340 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5341 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5344 static void tg3_tx_timeout(struct net_device *dev)
5346 struct tg3 *tp = netdev_priv(dev);
5348 if (netif_msg_tx_err(tp)) {
5349 netdev_err(dev, "transmit timed out, resetting\n");
5350 tg3_dump_short_state(tp);
5353 schedule_work(&tp->reset_task);
5356 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5357 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5359 u32 base = (u32) mapping & 0xffffffff;
5361 return ((base > 0xffffdcc0) &&
5362 (base + len + 8 < base));
5365 /* Test for DMA addresses > 40-bit */
5366 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5369 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5370 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5371 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5378 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5380 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5381 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5382 struct sk_buff *skb, u32 last_plus_one,
5383 u32 *start, u32 base_flags, u32 mss)
5385 struct tg3 *tp = tnapi->tp;
5386 struct sk_buff *new_skb;
5387 dma_addr_t new_addr = 0;
5391 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5392 new_skb = skb_copy(skb, GFP_ATOMIC);
5394 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5396 new_skb = skb_copy_expand(skb,
5397 skb_headroom(skb) + more_headroom,
5398 skb_tailroom(skb), GFP_ATOMIC);
5404 /* New SKB is guaranteed to be linear. */
5406 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5408 /* Make sure the mapping succeeded */
5409 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5411 dev_kfree_skb(new_skb);
5414 /* Make sure new skb does not cross any 4G boundaries.
5415 * Drop the packet if it does.
5417 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5418 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5419 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5422 dev_kfree_skb(new_skb);
5425 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5426 base_flags, 1 | (mss << 1));
5427 *start = NEXT_TX(entry);
5431 /* Now clean up the sw ring entries. */
5433 while (entry != last_plus_one) {
5437 len = skb_headlen(skb);
5439 len = skb_shinfo(skb)->frags[i-1].size;
5441 pci_unmap_single(tp->pdev,
5442 pci_unmap_addr(&tnapi->tx_buffers[entry],
5444 len, PCI_DMA_TODEVICE);
5446 tnapi->tx_buffers[entry].skb = new_skb;
5447 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5450 tnapi->tx_buffers[entry].skb = NULL;
5452 entry = NEXT_TX(entry);
5461 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5462 dma_addr_t mapping, int len, u32 flags,
5465 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5466 int is_end = (mss_and_is_end & 0x1);
5467 u32 mss = (mss_and_is_end >> 1);
5471 flags |= TXD_FLAG_END;
5472 if (flags & TXD_FLAG_VLAN) {
5473 vlan_tag = flags >> 16;
5476 vlan_tag |= (mss << TXD_MSS_SHIFT);
5478 txd->addr_hi = ((u64) mapping >> 32);
5479 txd->addr_lo = ((u64) mapping & 0xffffffff);
5480 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5481 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5484 /* hard_start_xmit for devices that don't have any bugs and
5485 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5487 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5488 struct net_device *dev)
5490 struct tg3 *tp = netdev_priv(dev);
5491 u32 len, entry, base_flags, mss;
5493 struct tg3_napi *tnapi;
5494 struct netdev_queue *txq;
5495 unsigned int i, last;
5497 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5498 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5499 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5502 /* We are running in BH disabled context with netif_tx_lock
5503 * and TX reclaim runs via tp->napi.poll inside of a software
5504 * interrupt. Furthermore, IRQ processing runs lockless so we have
5505 * no IRQ context deadlocks to worry about either. Rejoice!
5507 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5508 if (!netif_tx_queue_stopped(txq)) {
5509 netif_tx_stop_queue(txq);
5511 /* This is a hard error, log it. */
5513 "BUG! Tx Ring full when queue awake!\n");
5515 return NETDEV_TX_BUSY;
5518 entry = tnapi->tx_prod;
5521 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5522 int tcp_opt_len, ip_tcp_len;
5525 if (skb_header_cloned(skb) &&
5526 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5531 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5532 hdrlen = skb_headlen(skb) - ETH_HLEN;
5534 struct iphdr *iph = ip_hdr(skb);
5536 tcp_opt_len = tcp_optlen(skb);
5537 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5540 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5541 hdrlen = ip_tcp_len + tcp_opt_len;
5544 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5545 mss |= (hdrlen & 0xc) << 12;
5547 base_flags |= 0x00000010;
5548 base_flags |= (hdrlen & 0x3e0) << 5;
5552 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5553 TXD_FLAG_CPU_POST_DMA);
5555 tcp_hdr(skb)->check = 0;
5557 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5558 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5561 #if TG3_VLAN_TAG_USED
5562 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5563 base_flags |= (TXD_FLAG_VLAN |
5564 (vlan_tx_tag_get(skb) << 16));
5567 len = skb_headlen(skb);
5569 /* Queue skb data, a.k.a. the main skb fragment. */
5570 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5571 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5576 tnapi->tx_buffers[entry].skb = skb;
5577 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5579 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5580 !mss && skb->len > ETH_DATA_LEN)
5581 base_flags |= TXD_FLAG_JMB_PKT;
5583 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5584 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5586 entry = NEXT_TX(entry);
5588 /* Now loop through additional data fragments, and queue them. */
5589 if (skb_shinfo(skb)->nr_frags > 0) {
5590 last = skb_shinfo(skb)->nr_frags - 1;
5591 for (i = 0; i <= last; i++) {
5592 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5595 mapping = pci_map_page(tp->pdev,
5598 len, PCI_DMA_TODEVICE);
5599 if (pci_dma_mapping_error(tp->pdev, mapping))
5602 tnapi->tx_buffers[entry].skb = NULL;
5603 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5606 tg3_set_txd(tnapi, entry, mapping, len,
5607 base_flags, (i == last) | (mss << 1));
5609 entry = NEXT_TX(entry);
5613 /* Packets are ready, update Tx producer idx local and on card. */
5614 tw32_tx_mbox(tnapi->prodmbox, entry);
5616 tnapi->tx_prod = entry;
5617 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5618 netif_tx_stop_queue(txq);
5619 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5620 netif_tx_wake_queue(txq);
5626 return NETDEV_TX_OK;
5630 entry = tnapi->tx_prod;
5631 tnapi->tx_buffers[entry].skb = NULL;
5632 pci_unmap_single(tp->pdev,
5633 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5636 for (i = 0; i <= last; i++) {
5637 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5638 entry = NEXT_TX(entry);
5640 pci_unmap_page(tp->pdev,
5641 pci_unmap_addr(&tnapi->tx_buffers[entry],
5643 frag->size, PCI_DMA_TODEVICE);
5647 return NETDEV_TX_OK;
5650 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5651 struct net_device *);
5653 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5654 * TSO header is greater than 80 bytes.
5656 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5658 struct sk_buff *segs, *nskb;
5659 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5661 /* Estimate the number of fragments in the worst case */
5662 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5663 netif_stop_queue(tp->dev);
5664 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5665 return NETDEV_TX_BUSY;
5667 netif_wake_queue(tp->dev);
5670 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5672 goto tg3_tso_bug_end;
5678 tg3_start_xmit_dma_bug(nskb, tp->dev);
5684 return NETDEV_TX_OK;
5687 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5688 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5690 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5691 struct net_device *dev)
5693 struct tg3 *tp = netdev_priv(dev);
5694 u32 len, entry, base_flags, mss;
5695 int would_hit_hwbug;
5697 struct tg3_napi *tnapi;
5698 struct netdev_queue *txq;
5699 unsigned int i, last;
5701 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5702 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5703 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5706 /* We are running in BH disabled context with netif_tx_lock
5707 * and TX reclaim runs via tp->napi.poll inside of a software
5708 * interrupt. Furthermore, IRQ processing runs lockless so we have
5709 * no IRQ context deadlocks to worry about either. Rejoice!
5711 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5712 if (!netif_tx_queue_stopped(txq)) {
5713 netif_tx_stop_queue(txq);
5715 /* This is a hard error, log it. */
5717 "BUG! Tx Ring full when queue awake!\n");
5719 return NETDEV_TX_BUSY;
5722 entry = tnapi->tx_prod;
5724 if (skb->ip_summed == CHECKSUM_PARTIAL)
5725 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5727 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5729 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5731 if (skb_header_cloned(skb) &&
5732 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5737 tcp_opt_len = tcp_optlen(skb);
5738 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5740 hdr_len = ip_tcp_len + tcp_opt_len;
5741 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5742 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5743 return (tg3_tso_bug(tp, skb));
5745 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5746 TXD_FLAG_CPU_POST_DMA);
5750 iph->tot_len = htons(mss + hdr_len);
5751 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5752 tcp_hdr(skb)->check = 0;
5753 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5755 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5760 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5761 mss |= (hdr_len & 0xc) << 12;
5763 base_flags |= 0x00000010;
5764 base_flags |= (hdr_len & 0x3e0) << 5;
5765 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5766 mss |= hdr_len << 9;
5767 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5768 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5769 if (tcp_opt_len || iph->ihl > 5) {
5772 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5773 mss |= (tsflags << 11);
5776 if (tcp_opt_len || iph->ihl > 5) {
5779 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5780 base_flags |= tsflags << 12;
5784 #if TG3_VLAN_TAG_USED
5785 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5786 base_flags |= (TXD_FLAG_VLAN |
5787 (vlan_tx_tag_get(skb) << 16));
5790 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5791 !mss && skb->len > ETH_DATA_LEN)
5792 base_flags |= TXD_FLAG_JMB_PKT;
5794 len = skb_headlen(skb);
5796 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5797 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5802 tnapi->tx_buffers[entry].skb = skb;
5803 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5805 would_hit_hwbug = 0;
5807 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5808 would_hit_hwbug = 1;
5810 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5811 tg3_4g_overflow_test(mapping, len))
5812 would_hit_hwbug = 1;
5814 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5815 tg3_40bit_overflow_test(tp, mapping, len))
5816 would_hit_hwbug = 1;
5818 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5819 would_hit_hwbug = 1;
5821 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5822 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5824 entry = NEXT_TX(entry);
5826 /* Now loop through additional data fragments, and queue them. */
5827 if (skb_shinfo(skb)->nr_frags > 0) {
5828 last = skb_shinfo(skb)->nr_frags - 1;
5829 for (i = 0; i <= last; i++) {
5830 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5833 mapping = pci_map_page(tp->pdev,
5836 len, PCI_DMA_TODEVICE);
5838 tnapi->tx_buffers[entry].skb = NULL;
5839 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5841 if (pci_dma_mapping_error(tp->pdev, mapping))
5844 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5846 would_hit_hwbug = 1;
5848 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5849 tg3_4g_overflow_test(mapping, len))
5850 would_hit_hwbug = 1;
5852 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5853 tg3_40bit_overflow_test(tp, mapping, len))
5854 would_hit_hwbug = 1;
5856 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5857 tg3_set_txd(tnapi, entry, mapping, len,
5858 base_flags, (i == last)|(mss << 1));
5860 tg3_set_txd(tnapi, entry, mapping, len,
5861 base_flags, (i == last));
5863 entry = NEXT_TX(entry);
5867 if (would_hit_hwbug) {
5868 u32 last_plus_one = entry;
5871 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5872 start &= (TG3_TX_RING_SIZE - 1);
5874 /* If the workaround fails due to memory/mapping
5875 * failure, silently drop this packet.
5877 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5878 &start, base_flags, mss))
5884 /* Packets are ready, update Tx producer idx local and on card. */
5885 tw32_tx_mbox(tnapi->prodmbox, entry);
5887 tnapi->tx_prod = entry;
5888 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5889 netif_tx_stop_queue(txq);
5890 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5891 netif_tx_wake_queue(txq);
5897 return NETDEV_TX_OK;
5901 entry = tnapi->tx_prod;
5902 tnapi->tx_buffers[entry].skb = NULL;
5903 pci_unmap_single(tp->pdev,
5904 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5907 for (i = 0; i <= last; i++) {
5908 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5909 entry = NEXT_TX(entry);
5911 pci_unmap_page(tp->pdev,
5912 pci_unmap_addr(&tnapi->tx_buffers[entry],
5914 frag->size, PCI_DMA_TODEVICE);
5918 return NETDEV_TX_OK;
5921 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5926 if (new_mtu > ETH_DATA_LEN) {
5927 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5928 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5929 ethtool_op_set_tso(dev, 0);
5931 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5934 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5935 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5936 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5940 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5942 struct tg3 *tp = netdev_priv(dev);
5945 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5948 if (!netif_running(dev)) {
5949 /* We'll just catch it later when the
5952 tg3_set_mtu(dev, tp, new_mtu);
5960 tg3_full_lock(tp, 1);
5962 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5964 tg3_set_mtu(dev, tp, new_mtu);
5966 err = tg3_restart_hw(tp, 0);
5969 tg3_netif_start(tp);
5971 tg3_full_unlock(tp);
5979 static void tg3_rx_prodring_free(struct tg3 *tp,
5980 struct tg3_rx_prodring_set *tpr)
5984 if (tpr != &tp->prodring[0]) {
5985 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5986 i = (i + 1) % TG3_RX_RING_SIZE)
5987 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5990 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5991 for (i = tpr->rx_jmb_cons_idx;
5992 i != tpr->rx_jmb_prod_idx;
5993 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5994 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6002 for (i = 0; i < TG3_RX_RING_SIZE; i++)
6003 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6006 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6007 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6008 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6013 /* Initialize rx rings for packet processing.
6015 * The chip has been shut down and the driver detached from
6016 * the networking, so no interrupts or new tx packets will
6017 * end up in the driver. tp->{tx,}lock are held and thus
6020 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6021 struct tg3_rx_prodring_set *tpr)
6023 u32 i, rx_pkt_dma_sz;
6025 tpr->rx_std_cons_idx = 0;
6026 tpr->rx_std_prod_idx = 0;
6027 tpr->rx_jmb_cons_idx = 0;
6028 tpr->rx_jmb_prod_idx = 0;
6030 if (tpr != &tp->prodring[0]) {
6031 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6032 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6033 memset(&tpr->rx_jmb_buffers[0], 0,
6034 TG3_RX_JMB_BUFF_RING_SIZE);
6038 /* Zero out all descriptors. */
6039 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6041 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6042 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6043 tp->dev->mtu > ETH_DATA_LEN)
6044 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6045 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6047 /* Initialize invariants of the rings, we only set this
6048 * stuff once. This works because the card does not
6049 * write into the rx buffer posting rings.
6051 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6052 struct tg3_rx_buffer_desc *rxd;
6054 rxd = &tpr->rx_std[i];
6055 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6056 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6057 rxd->opaque = (RXD_OPAQUE_RING_STD |
6058 (i << RXD_OPAQUE_INDEX_SHIFT));
6061 /* Now allocate fresh SKBs for each rx ring. */
6062 for (i = 0; i < tp->rx_pending; i++) {
6063 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6064 netdev_warn(tp->dev,
6065 "Using a smaller RX standard ring. Only "
6066 "%d out of %d buffers were allocated "
6067 "successfully\n", i, tp->rx_pending);
6075 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6078 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6080 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6083 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6084 struct tg3_rx_buffer_desc *rxd;
6086 rxd = &tpr->rx_jmb[i].std;
6087 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6088 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6090 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6091 (i << RXD_OPAQUE_INDEX_SHIFT));
6094 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6095 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6096 netdev_warn(tp->dev,
6097 "Using a smaller RX jumbo ring. Only %d "
6098 "out of %d buffers were allocated "
6099 "successfully\n", i, tp->rx_jumbo_pending);
6102 tp->rx_jumbo_pending = i;
6111 tg3_rx_prodring_free(tp, tpr);
6115 static void tg3_rx_prodring_fini(struct tg3 *tp,
6116 struct tg3_rx_prodring_set *tpr)
6118 kfree(tpr->rx_std_buffers);
6119 tpr->rx_std_buffers = NULL;
6120 kfree(tpr->rx_jmb_buffers);
6121 tpr->rx_jmb_buffers = NULL;
6123 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6124 tpr->rx_std, tpr->rx_std_mapping);
6128 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6129 tpr->rx_jmb, tpr->rx_jmb_mapping);
6134 static int tg3_rx_prodring_init(struct tg3 *tp,
6135 struct tg3_rx_prodring_set *tpr)
6137 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6138 if (!tpr->rx_std_buffers)
6141 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6142 &tpr->rx_std_mapping);
6146 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6147 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6149 if (!tpr->rx_jmb_buffers)
6152 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6153 TG3_RX_JUMBO_RING_BYTES,
6154 &tpr->rx_jmb_mapping);
6162 tg3_rx_prodring_fini(tp, tpr);
6166 /* Free up pending packets in all rx/tx rings.
6168 * The chip has been shut down and the driver detached from
6169 * the networking, so no interrupts or new tx packets will
6170 * end up in the driver. tp->{tx,}lock is not held and we are not
6171 * in an interrupt context and thus may sleep.
6173 static void tg3_free_rings(struct tg3 *tp)
6177 for (j = 0; j < tp->irq_cnt; j++) {
6178 struct tg3_napi *tnapi = &tp->napi[j];
6180 if (!tnapi->tx_buffers)
6183 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6184 struct ring_info *txp;
6185 struct sk_buff *skb;
6188 txp = &tnapi->tx_buffers[i];
6196 pci_unmap_single(tp->pdev,
6197 pci_unmap_addr(txp, mapping),
6204 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6205 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6206 pci_unmap_page(tp->pdev,
6207 pci_unmap_addr(txp, mapping),
6208 skb_shinfo(skb)->frags[k].size,
6213 dev_kfree_skb_any(skb);
6216 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6220 /* Initialize tx/rx rings for packet processing.
6222 * The chip has been shut down and the driver detached from
6223 * the networking, so no interrupts or new tx packets will
6224 * end up in the driver. tp->{tx,}lock are held and thus
6227 static int tg3_init_rings(struct tg3 *tp)
6231 /* Free up all the SKBs. */
6234 for (i = 0; i < tp->irq_cnt; i++) {
6235 struct tg3_napi *tnapi = &tp->napi[i];
6237 tnapi->last_tag = 0;
6238 tnapi->last_irq_tag = 0;
6239 tnapi->hw_status->status = 0;
6240 tnapi->hw_status->status_tag = 0;
6241 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6246 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6248 tnapi->rx_rcb_ptr = 0;
6250 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6252 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6262 * Must not be invoked with interrupt sources disabled and
6263 * the hardware shutdown down.
6265 static void tg3_free_consistent(struct tg3 *tp)
6269 for (i = 0; i < tp->irq_cnt; i++) {
6270 struct tg3_napi *tnapi = &tp->napi[i];
6272 if (tnapi->tx_ring) {
6273 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6274 tnapi->tx_ring, tnapi->tx_desc_mapping);
6275 tnapi->tx_ring = NULL;
6278 kfree(tnapi->tx_buffers);
6279 tnapi->tx_buffers = NULL;
6281 if (tnapi->rx_rcb) {
6282 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6284 tnapi->rx_rcb_mapping);
6285 tnapi->rx_rcb = NULL;
6288 if (tnapi->hw_status) {
6289 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6291 tnapi->status_mapping);
6292 tnapi->hw_status = NULL;
6297 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6298 tp->hw_stats, tp->stats_mapping);
6299 tp->hw_stats = NULL;
6302 for (i = 0; i < tp->irq_cnt; i++)
6303 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6307 * Must not be invoked with interrupt sources disabled and
6308 * the hardware shutdown down. Can sleep.
6310 static int tg3_alloc_consistent(struct tg3 *tp)
6314 for (i = 0; i < tp->irq_cnt; i++) {
6315 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6319 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6320 sizeof(struct tg3_hw_stats),
6321 &tp->stats_mapping);
6325 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6327 for (i = 0; i < tp->irq_cnt; i++) {
6328 struct tg3_napi *tnapi = &tp->napi[i];
6329 struct tg3_hw_status *sblk;
6331 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6333 &tnapi->status_mapping);
6334 if (!tnapi->hw_status)
6337 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6338 sblk = tnapi->hw_status;
6340 /* If multivector TSS is enabled, vector 0 does not handle
6341 * tx interrupts. Don't allocate any resources for it.
6343 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6344 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6345 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6348 if (!tnapi->tx_buffers)
6351 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6353 &tnapi->tx_desc_mapping);
6354 if (!tnapi->tx_ring)
6359 * When RSS is enabled, the status block format changes
6360 * slightly. The "rx_jumbo_consumer", "reserved",
6361 * and "rx_mini_consumer" members get mapped to the
6362 * other three rx return ring producer indexes.
6366 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6369 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6372 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6375 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6379 tnapi->prodring = &tp->prodring[i];
6382 * If multivector RSS is enabled, vector 0 does not handle
6383 * rx or tx interrupts. Don't allocate any resources for it.
6385 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6388 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6389 TG3_RX_RCB_RING_BYTES(tp),
6390 &tnapi->rx_rcb_mapping);
6394 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6400 tg3_free_consistent(tp);
6404 #define MAX_WAIT_CNT 1000
6406 /* To stop a block, clear the enable bit and poll till it
6407 * clears. tp->lock is held.
6409 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6414 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6421 /* We can't enable/disable these bits of the
6422 * 5705/5750, just say success.
6435 for (i = 0; i < MAX_WAIT_CNT; i++) {
6438 if ((val & enable_bit) == 0)
6442 if (i == MAX_WAIT_CNT && !silent) {
6443 dev_err(&tp->pdev->dev,
6444 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6452 /* tp->lock is held. */
6453 static int tg3_abort_hw(struct tg3 *tp, int silent)
6457 tg3_disable_ints(tp);
6459 tp->rx_mode &= ~RX_MODE_ENABLE;
6460 tw32_f(MAC_RX_MODE, tp->rx_mode);
6463 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6464 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6465 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6466 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6467 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6468 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6470 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6471 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6472 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6473 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6474 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6475 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6476 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6478 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6479 tw32_f(MAC_MODE, tp->mac_mode);
6482 tp->tx_mode &= ~TX_MODE_ENABLE;
6483 tw32_f(MAC_TX_MODE, tp->tx_mode);
6485 for (i = 0; i < MAX_WAIT_CNT; i++) {
6487 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6490 if (i >= MAX_WAIT_CNT) {
6491 dev_err(&tp->pdev->dev,
6492 "%s timed out, TX_MODE_ENABLE will not clear "
6493 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6497 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6498 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6499 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6501 tw32(FTQ_RESET, 0xffffffff);
6502 tw32(FTQ_RESET, 0x00000000);
6504 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6505 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6507 for (i = 0; i < tp->irq_cnt; i++) {
6508 struct tg3_napi *tnapi = &tp->napi[i];
6509 if (tnapi->hw_status)
6510 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6513 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6518 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6523 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6524 if (apedata != APE_SEG_SIG_MAGIC)
6527 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6528 if (!(apedata & APE_FW_STATUS_READY))
6531 /* Wait for up to 1 millisecond for APE to service previous event. */
6532 for (i = 0; i < 10; i++) {
6533 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6536 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6538 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6539 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6540 event | APE_EVENT_STATUS_EVENT_PENDING);
6542 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6544 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6550 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6551 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6554 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6559 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6563 case RESET_KIND_INIT:
6564 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6565 APE_HOST_SEG_SIG_MAGIC);
6566 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6567 APE_HOST_SEG_LEN_MAGIC);
6568 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6569 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6570 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6571 APE_HOST_DRIVER_ID_MAGIC);
6572 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6573 APE_HOST_BEHAV_NO_PHYLOCK);
6575 event = APE_EVENT_STATUS_STATE_START;
6577 case RESET_KIND_SHUTDOWN:
6578 /* With the interface we are currently using,
6579 * APE does not track driver state. Wiping
6580 * out the HOST SEGMENT SIGNATURE forces
6581 * the APE to assume OS absent status.
6583 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6585 event = APE_EVENT_STATUS_STATE_UNLOAD;
6587 case RESET_KIND_SUSPEND:
6588 event = APE_EVENT_STATUS_STATE_SUSPEND;
6594 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6596 tg3_ape_send_event(tp, event);
6599 /* tp->lock is held. */
6600 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6602 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6603 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6605 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6607 case RESET_KIND_INIT:
6608 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6612 case RESET_KIND_SHUTDOWN:
6613 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6617 case RESET_KIND_SUSPEND:
6618 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6627 if (kind == RESET_KIND_INIT ||
6628 kind == RESET_KIND_SUSPEND)
6629 tg3_ape_driver_state_change(tp, kind);
6632 /* tp->lock is held. */
6633 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6635 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6637 case RESET_KIND_INIT:
6638 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6639 DRV_STATE_START_DONE);
6642 case RESET_KIND_SHUTDOWN:
6643 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6644 DRV_STATE_UNLOAD_DONE);
6652 if (kind == RESET_KIND_SHUTDOWN)
6653 tg3_ape_driver_state_change(tp, kind);
6656 /* tp->lock is held. */
6657 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6659 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6661 case RESET_KIND_INIT:
6662 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6666 case RESET_KIND_SHUTDOWN:
6667 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6671 case RESET_KIND_SUSPEND:
6672 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6682 static int tg3_poll_fw(struct tg3 *tp)
6687 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6688 /* Wait up to 20ms for init done. */
6689 for (i = 0; i < 200; i++) {
6690 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6697 /* Wait for firmware initialization to complete. */
6698 for (i = 0; i < 100000; i++) {
6699 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6700 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6705 /* Chip might not be fitted with firmware. Some Sun onboard
6706 * parts are configured like that. So don't signal the timeout
6707 * of the above loop as an error, but do report the lack of
6708 * running firmware once.
6711 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6712 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6714 netdev_info(tp->dev, "No firmware running\n");
6717 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6718 /* The 57765 A0 needs a little more
6719 * time to do some important work.
6727 /* Save PCI command register before chip reset */
6728 static void tg3_save_pci_state(struct tg3 *tp)
6730 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6733 /* Restore PCI state after chip reset */
6734 static void tg3_restore_pci_state(struct tg3 *tp)
6738 /* Re-enable indirect register accesses. */
6739 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6740 tp->misc_host_ctrl);
6742 /* Set MAX PCI retry to zero. */
6743 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6744 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6745 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6746 val |= PCISTATE_RETRY_SAME_DMA;
6747 /* Allow reads and writes to the APE register and memory space. */
6748 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6749 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6750 PCISTATE_ALLOW_APE_SHMEM_WR;
6751 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6753 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6755 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6756 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6757 pcie_set_readrq(tp->pdev, 4096);
6759 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6760 tp->pci_cacheline_sz);
6761 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6766 /* Make sure PCI-X relaxed ordering bit is clear. */
6767 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6770 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6772 pcix_cmd &= ~PCI_X_CMD_ERO;
6773 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6777 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6779 /* Chip reset on 5780 will reset MSI enable bit,
6780 * so need to restore it.
6782 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6785 pci_read_config_word(tp->pdev,
6786 tp->msi_cap + PCI_MSI_FLAGS,
6788 pci_write_config_word(tp->pdev,
6789 tp->msi_cap + PCI_MSI_FLAGS,
6790 ctrl | PCI_MSI_FLAGS_ENABLE);
6791 val = tr32(MSGINT_MODE);
6792 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6797 static void tg3_stop_fw(struct tg3 *);
6799 /* tp->lock is held. */
6800 static int tg3_chip_reset(struct tg3 *tp)
6803 void (*write_op)(struct tg3 *, u32, u32);
6808 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6810 /* No matching tg3_nvram_unlock() after this because
6811 * chip reset below will undo the nvram lock.
6813 tp->nvram_lock_cnt = 0;
6815 /* GRC_MISC_CFG core clock reset will clear the memory
6816 * enable bit in PCI register 4 and the MSI enable bit
6817 * on some chips, so we save relevant registers here.
6819 tg3_save_pci_state(tp);
6821 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6822 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6823 tw32(GRC_FASTBOOT_PC, 0);
6826 * We must avoid the readl() that normally takes place.
6827 * It locks machines, causes machine checks, and other
6828 * fun things. So, temporarily disable the 5701
6829 * hardware workaround, while we do the reset.
6831 write_op = tp->write32;
6832 if (write_op == tg3_write_flush_reg32)
6833 tp->write32 = tg3_write32;
6835 /* Prevent the irq handler from reading or writing PCI registers
6836 * during chip reset when the memory enable bit in the PCI command
6837 * register may be cleared. The chip does not generate interrupt
6838 * at this time, but the irq handler may still be called due to irq
6839 * sharing or irqpoll.
6841 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6842 for (i = 0; i < tp->irq_cnt; i++) {
6843 struct tg3_napi *tnapi = &tp->napi[i];
6844 if (tnapi->hw_status) {
6845 tnapi->hw_status->status = 0;
6846 tnapi->hw_status->status_tag = 0;
6848 tnapi->last_tag = 0;
6849 tnapi->last_irq_tag = 0;
6853 for (i = 0; i < tp->irq_cnt; i++)
6854 synchronize_irq(tp->napi[i].irq_vec);
6856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6857 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6858 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6862 val = GRC_MISC_CFG_CORECLK_RESET;
6864 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6865 if (tr32(0x7e2c) == 0x60) {
6868 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6869 tw32(GRC_MISC_CFG, (1 << 29));
6874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6875 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6876 tw32(GRC_VCPU_EXT_CTRL,
6877 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6880 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6881 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6882 tw32(GRC_MISC_CFG, val);
6884 /* restore 5701 hardware bug workaround write method */
6885 tp->write32 = write_op;
6887 /* Unfortunately, we have to delay before the PCI read back.
6888 * Some 575X chips even will not respond to a PCI cfg access
6889 * when the reset command is given to the chip.
6891 * How do these hardware designers expect things to work
6892 * properly if the PCI write is posted for a long period
6893 * of time? It is always necessary to have some method by
6894 * which a register read back can occur to push the write
6895 * out which does the reset.
6897 * For most tg3 variants the trick below was working.
6902 /* Flush PCI posted writes. The normal MMIO registers
6903 * are inaccessible at this time so this is the only
6904 * way to make this reliably (actually, this is no longer
6905 * the case, see above). I tried to use indirect
6906 * register read/write but this upset some 5701 variants.
6908 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6912 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6915 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6919 /* Wait for link training to complete. */
6920 for (i = 0; i < 5000; i++)
6923 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6924 pci_write_config_dword(tp->pdev, 0xc4,
6925 cfg_val | (1 << 15));
6928 /* Clear the "no snoop" and "relaxed ordering" bits. */
6929 pci_read_config_word(tp->pdev,
6930 tp->pcie_cap + PCI_EXP_DEVCTL,
6932 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6933 PCI_EXP_DEVCTL_NOSNOOP_EN);
6935 * Older PCIe devices only support the 128 byte
6936 * MPS setting. Enforce the restriction.
6938 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6939 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6940 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6941 pci_write_config_word(tp->pdev,
6942 tp->pcie_cap + PCI_EXP_DEVCTL,
6945 pcie_set_readrq(tp->pdev, 4096);
6947 /* Clear error status */
6948 pci_write_config_word(tp->pdev,
6949 tp->pcie_cap + PCI_EXP_DEVSTA,
6950 PCI_EXP_DEVSTA_CED |
6951 PCI_EXP_DEVSTA_NFED |
6952 PCI_EXP_DEVSTA_FED |
6953 PCI_EXP_DEVSTA_URD);
6956 tg3_restore_pci_state(tp);
6958 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6961 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6962 val = tr32(MEMARB_MODE);
6963 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6965 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6967 tw32(0x5000, 0x400);
6970 tw32(GRC_MODE, tp->grc_mode);
6972 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6975 tw32(0xc4, val | (1 << 15));
6978 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6979 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6980 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6981 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6982 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6983 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6986 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6987 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6988 tw32_f(MAC_MODE, tp->mac_mode);
6989 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6990 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6991 tw32_f(MAC_MODE, tp->mac_mode);
6992 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6993 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6994 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6995 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6996 tw32_f(MAC_MODE, tp->mac_mode);
6998 tw32_f(MAC_MODE, 0);
7001 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7003 err = tg3_poll_fw(tp);
7009 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7012 phy_addr = tp->phy_addr;
7013 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7015 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7016 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7017 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7018 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7019 TG3_PCIEPHY_TX0CTRL1_NB_EN;
7020 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7023 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7024 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7025 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7026 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7027 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7030 tp->phy_addr = phy_addr;
7033 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7034 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7035 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7036 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7037 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
7040 tw32(0x7c00, val | (1 << 25));
7043 /* Reprobe ASF enable state. */
7044 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7045 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7046 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7047 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7050 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7051 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7052 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7053 tp->last_event_jiffies = jiffies;
7054 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7055 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7062 /* tp->lock is held. */
7063 static void tg3_stop_fw(struct tg3 *tp)
7065 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7066 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7067 /* Wait for RX cpu to ACK the previous event. */
7068 tg3_wait_for_event_ack(tp);
7070 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7072 tg3_generate_fw_event(tp);
7074 /* Wait for RX cpu to ACK this event. */
7075 tg3_wait_for_event_ack(tp);
7079 /* tp->lock is held. */
7080 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7086 tg3_write_sig_pre_reset(tp, kind);
7088 tg3_abort_hw(tp, silent);
7089 err = tg3_chip_reset(tp);
7091 __tg3_set_mac_addr(tp, 0);
7093 tg3_write_sig_legacy(tp, kind);
7094 tg3_write_sig_post_reset(tp, kind);
7102 #define RX_CPU_SCRATCH_BASE 0x30000
7103 #define RX_CPU_SCRATCH_SIZE 0x04000
7104 #define TX_CPU_SCRATCH_BASE 0x34000
7105 #define TX_CPU_SCRATCH_SIZE 0x04000
7107 /* tp->lock is held. */
7108 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7112 BUG_ON(offset == TX_CPU_BASE &&
7113 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7115 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7116 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7118 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7121 if (offset == RX_CPU_BASE) {
7122 for (i = 0; i < 10000; i++) {
7123 tw32(offset + CPU_STATE, 0xffffffff);
7124 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7125 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7129 tw32(offset + CPU_STATE, 0xffffffff);
7130 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7133 for (i = 0; i < 10000; i++) {
7134 tw32(offset + CPU_STATE, 0xffffffff);
7135 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7136 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7142 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7143 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7147 /* Clear firmware's nvram arbitration. */
7148 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7149 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7154 unsigned int fw_base;
7155 unsigned int fw_len;
7156 const __be32 *fw_data;
7159 /* tp->lock is held. */
7160 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7161 int cpu_scratch_size, struct fw_info *info)
7163 int err, lock_err, i;
7164 void (*write_op)(struct tg3 *, u32, u32);
7166 if (cpu_base == TX_CPU_BASE &&
7167 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7169 "%s: Trying to load TX cpu firmware which is 5705\n",
7174 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7175 write_op = tg3_write_mem;
7177 write_op = tg3_write_indirect_reg32;
7179 /* It is possible that bootcode is still loading at this point.
7180 * Get the nvram lock first before halting the cpu.
7182 lock_err = tg3_nvram_lock(tp);
7183 err = tg3_halt_cpu(tp, cpu_base);
7185 tg3_nvram_unlock(tp);
7189 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7190 write_op(tp, cpu_scratch_base + i, 0);
7191 tw32(cpu_base + CPU_STATE, 0xffffffff);
7192 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7193 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7194 write_op(tp, (cpu_scratch_base +
7195 (info->fw_base & 0xffff) +
7197 be32_to_cpu(info->fw_data[i]));
7205 /* tp->lock is held. */
7206 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7208 struct fw_info info;
7209 const __be32 *fw_data;
7212 fw_data = (void *)tp->fw->data;
7214 /* Firmware blob starts with version numbers, followed by
7215 start address and length. We are setting complete length.
7216 length = end_address_of_bss - start_address_of_text.
7217 Remainder is the blob to be loaded contiguously
7218 from start address. */
7220 info.fw_base = be32_to_cpu(fw_data[1]);
7221 info.fw_len = tp->fw->size - 12;
7222 info.fw_data = &fw_data[3];
7224 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7225 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7230 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7231 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7236 /* Now startup only the RX cpu. */
7237 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7238 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7240 for (i = 0; i < 5; i++) {
7241 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7243 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7244 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7245 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7249 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7250 "should be %08x\n", __func__,
7251 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7254 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7255 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7260 /* 5705 needs a special version of the TSO firmware. */
7262 /* tp->lock is held. */
7263 static int tg3_load_tso_firmware(struct tg3 *tp)
7265 struct fw_info info;
7266 const __be32 *fw_data;
7267 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7270 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7273 fw_data = (void *)tp->fw->data;
7275 /* Firmware blob starts with version numbers, followed by
7276 start address and length. We are setting complete length.
7277 length = end_address_of_bss - start_address_of_text.
7278 Remainder is the blob to be loaded contiguously
7279 from start address. */
7281 info.fw_base = be32_to_cpu(fw_data[1]);
7282 cpu_scratch_size = tp->fw_len;
7283 info.fw_len = tp->fw->size - 12;
7284 info.fw_data = &fw_data[3];
7286 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7287 cpu_base = RX_CPU_BASE;
7288 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7290 cpu_base = TX_CPU_BASE;
7291 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7292 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7295 err = tg3_load_firmware_cpu(tp, cpu_base,
7296 cpu_scratch_base, cpu_scratch_size,
7301 /* Now startup the cpu. */
7302 tw32(cpu_base + CPU_STATE, 0xffffffff);
7303 tw32_f(cpu_base + CPU_PC, info.fw_base);
7305 for (i = 0; i < 5; i++) {
7306 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7308 tw32(cpu_base + CPU_STATE, 0xffffffff);
7309 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7310 tw32_f(cpu_base + CPU_PC, info.fw_base);
7315 "%s fails to set CPU PC, is %08x should be %08x\n",
7316 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7319 tw32(cpu_base + CPU_STATE, 0xffffffff);
7320 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7325 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7327 struct tg3 *tp = netdev_priv(dev);
7328 struct sockaddr *addr = p;
7329 int err = 0, skip_mac_1 = 0;
7331 if (!is_valid_ether_addr(addr->sa_data))
7334 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7336 if (!netif_running(dev))
7339 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7340 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7342 addr0_high = tr32(MAC_ADDR_0_HIGH);
7343 addr0_low = tr32(MAC_ADDR_0_LOW);
7344 addr1_high = tr32(MAC_ADDR_1_HIGH);
7345 addr1_low = tr32(MAC_ADDR_1_LOW);
7347 /* Skip MAC addr 1 if ASF is using it. */
7348 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7349 !(addr1_high == 0 && addr1_low == 0))
7352 spin_lock_bh(&tp->lock);
7353 __tg3_set_mac_addr(tp, skip_mac_1);
7354 spin_unlock_bh(&tp->lock);
7359 /* tp->lock is held. */
7360 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7361 dma_addr_t mapping, u32 maxlen_flags,
7365 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7366 ((u64) mapping >> 32));
7368 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7369 ((u64) mapping & 0xffffffff));
7371 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7374 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7376 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7380 static void __tg3_set_rx_mode(struct net_device *);
7381 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7385 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7386 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7387 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7388 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7390 tw32(HOSTCC_TXCOL_TICKS, 0);
7391 tw32(HOSTCC_TXMAX_FRAMES, 0);
7392 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7395 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7396 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7397 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7398 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7400 tw32(HOSTCC_RXCOL_TICKS, 0);
7401 tw32(HOSTCC_RXMAX_FRAMES, 0);
7402 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7405 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7406 u32 val = ec->stats_block_coalesce_usecs;
7408 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7409 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7411 if (!netif_carrier_ok(tp->dev))
7414 tw32(HOSTCC_STAT_COAL_TICKS, val);
7417 for (i = 0; i < tp->irq_cnt - 1; i++) {
7420 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7421 tw32(reg, ec->rx_coalesce_usecs);
7422 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7423 tw32(reg, ec->rx_max_coalesced_frames);
7424 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7425 tw32(reg, ec->rx_max_coalesced_frames_irq);
7427 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7428 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7429 tw32(reg, ec->tx_coalesce_usecs);
7430 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7431 tw32(reg, ec->tx_max_coalesced_frames);
7432 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7433 tw32(reg, ec->tx_max_coalesced_frames_irq);
7437 for (; i < tp->irq_max - 1; i++) {
7438 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7439 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7440 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7442 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7443 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7444 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7445 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7450 /* tp->lock is held. */
7451 static void tg3_rings_reset(struct tg3 *tp)
7454 u32 stblk, txrcb, rxrcb, limit;
7455 struct tg3_napi *tnapi = &tp->napi[0];
7457 /* Disable all transmit rings but the first. */
7458 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7459 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7460 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7461 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7463 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7465 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7466 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7467 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7468 BDINFO_FLAGS_DISABLED);
7471 /* Disable all receive return rings but the first. */
7472 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7473 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7474 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7475 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7476 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7477 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7478 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7480 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7482 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7483 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7484 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7485 BDINFO_FLAGS_DISABLED);
7487 /* Disable interrupts */
7488 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7490 /* Zero mailbox registers. */
7491 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7492 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7493 tp->napi[i].tx_prod = 0;
7494 tp->napi[i].tx_cons = 0;
7495 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7496 tw32_mailbox(tp->napi[i].prodmbox, 0);
7497 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7498 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7500 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7501 tw32_mailbox(tp->napi[0].prodmbox, 0);
7503 tp->napi[0].tx_prod = 0;
7504 tp->napi[0].tx_cons = 0;
7505 tw32_mailbox(tp->napi[0].prodmbox, 0);
7506 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7509 /* Make sure the NIC-based send BD rings are disabled. */
7510 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7511 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7512 for (i = 0; i < 16; i++)
7513 tw32_tx_mbox(mbox + i * 8, 0);
7516 txrcb = NIC_SRAM_SEND_RCB;
7517 rxrcb = NIC_SRAM_RCV_RET_RCB;
7519 /* Clear status block in ram. */
7520 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7522 /* Set status block DMA address */
7523 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7524 ((u64) tnapi->status_mapping >> 32));
7525 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7526 ((u64) tnapi->status_mapping & 0xffffffff));
7528 if (tnapi->tx_ring) {
7529 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7530 (TG3_TX_RING_SIZE <<
7531 BDINFO_FLAGS_MAXLEN_SHIFT),
7532 NIC_SRAM_TX_BUFFER_DESC);
7533 txrcb += TG3_BDINFO_SIZE;
7536 if (tnapi->rx_rcb) {
7537 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7538 (TG3_RX_RCB_RING_SIZE(tp) <<
7539 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7540 rxrcb += TG3_BDINFO_SIZE;
7543 stblk = HOSTCC_STATBLCK_RING1;
7545 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7546 u64 mapping = (u64)tnapi->status_mapping;
7547 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7548 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7550 /* Clear status block in ram. */
7551 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7553 if (tnapi->tx_ring) {
7554 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7555 (TG3_TX_RING_SIZE <<
7556 BDINFO_FLAGS_MAXLEN_SHIFT),
7557 NIC_SRAM_TX_BUFFER_DESC);
7558 txrcb += TG3_BDINFO_SIZE;
7561 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7562 (TG3_RX_RCB_RING_SIZE(tp) <<
7563 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7566 rxrcb += TG3_BDINFO_SIZE;
7570 /* tp->lock is held. */
7571 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7573 u32 val, rdmac_mode;
7575 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7577 tg3_disable_ints(tp);
7581 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7583 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7584 tg3_abort_hw(tp, 1);
7589 err = tg3_chip_reset(tp);
7593 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7595 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7596 val = tr32(TG3_CPMU_CTRL);
7597 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7598 tw32(TG3_CPMU_CTRL, val);
7600 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7601 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7602 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7603 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7605 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7606 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7607 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7608 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7610 val = tr32(TG3_CPMU_HST_ACC);
7611 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7612 val |= CPMU_HST_ACC_MACCLK_6_25;
7613 tw32(TG3_CPMU_HST_ACC, val);
7616 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7617 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7618 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7619 PCIE_PWR_MGMT_L1_THRESH_4MS;
7620 tw32(PCIE_PWR_MGMT_THRESH, val);
7622 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7623 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7625 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7627 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7628 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7631 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7632 u32 grc_mode = tr32(GRC_MODE);
7634 /* Access the lower 1K of PL PCIE block registers. */
7635 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7636 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7638 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7639 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7640 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7642 tw32(GRC_MODE, grc_mode);
7645 /* This works around an issue with Athlon chipsets on
7646 * B3 tigon3 silicon. This bit has no effect on any
7647 * other revision. But do not set this on PCI Express
7648 * chips and don't even touch the clocks if the CPMU is present.
7650 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7651 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7652 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7653 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7656 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7657 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7658 val = tr32(TG3PCI_PCISTATE);
7659 val |= PCISTATE_RETRY_SAME_DMA;
7660 tw32(TG3PCI_PCISTATE, val);
7663 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7664 /* Allow reads and writes to the
7665 * APE register and memory space.
7667 val = tr32(TG3PCI_PCISTATE);
7668 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7669 PCISTATE_ALLOW_APE_SHMEM_WR;
7670 tw32(TG3PCI_PCISTATE, val);
7673 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7674 /* Enable some hw fixes. */
7675 val = tr32(TG3PCI_MSI_DATA);
7676 val |= (1 << 26) | (1 << 28) | (1 << 29);
7677 tw32(TG3PCI_MSI_DATA, val);
7680 /* Descriptor ring init may make accesses to the
7681 * NIC SRAM area to setup the TX descriptors, so we
7682 * can only do this after the hardware has been
7683 * successfully reset.
7685 err = tg3_init_rings(tp);
7689 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7690 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7691 val = tr32(TG3PCI_DMA_RW_CTRL) &
7692 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7693 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7694 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7695 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7696 /* This value is determined during the probe time DMA
7697 * engine test, tg3_test_dma.
7699 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7702 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7703 GRC_MODE_4X_NIC_SEND_RINGS |
7704 GRC_MODE_NO_TX_PHDR_CSUM |
7705 GRC_MODE_NO_RX_PHDR_CSUM);
7706 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7708 /* Pseudo-header checksum is done by hardware logic and not
7709 * the offload processers, so make the chip do the pseudo-
7710 * header checksums on receive. For transmit it is more
7711 * convenient to do the pseudo-header checksum in software
7712 * as Linux does that on transmit for us in all cases.
7714 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7718 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7720 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7721 val = tr32(GRC_MISC_CFG);
7723 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7724 tw32(GRC_MISC_CFG, val);
7726 /* Initialize MBUF/DESC pool. */
7727 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7729 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7730 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7731 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7732 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7734 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7735 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7736 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7737 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7740 fw_len = tp->fw_len;
7741 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7742 tw32(BUFMGR_MB_POOL_ADDR,
7743 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7744 tw32(BUFMGR_MB_POOL_SIZE,
7745 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7748 if (tp->dev->mtu <= ETH_DATA_LEN) {
7749 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7750 tp->bufmgr_config.mbuf_read_dma_low_water);
7751 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7752 tp->bufmgr_config.mbuf_mac_rx_low_water);
7753 tw32(BUFMGR_MB_HIGH_WATER,
7754 tp->bufmgr_config.mbuf_high_water);
7756 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7757 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7758 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7759 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7760 tw32(BUFMGR_MB_HIGH_WATER,
7761 tp->bufmgr_config.mbuf_high_water_jumbo);
7763 tw32(BUFMGR_DMA_LOW_WATER,
7764 tp->bufmgr_config.dma_low_water);
7765 tw32(BUFMGR_DMA_HIGH_WATER,
7766 tp->bufmgr_config.dma_high_water);
7768 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7769 for (i = 0; i < 2000; i++) {
7770 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7775 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7779 /* Setup replenish threshold. */
7780 val = tp->rx_pending / 8;
7783 else if (val > tp->rx_std_max_post)
7784 val = tp->rx_std_max_post;
7785 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7786 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7787 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7789 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7790 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7793 tw32(RCVBDI_STD_THRESH, val);
7795 /* Initialize TG3_BDINFO's at:
7796 * RCVDBDI_STD_BD: standard eth size rx ring
7797 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7798 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7801 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7802 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7803 * ring attribute flags
7804 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7806 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7807 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7809 * The size of each ring is fixed in the firmware, but the location is
7812 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7813 ((u64) tpr->rx_std_mapping >> 32));
7814 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7815 ((u64) tpr->rx_std_mapping & 0xffffffff));
7816 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7817 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7818 NIC_SRAM_RX_BUFFER_DESC);
7820 /* Disable the mini ring */
7821 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7822 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7823 BDINFO_FLAGS_DISABLED);
7825 /* Program the jumbo buffer descriptor ring control
7826 * blocks on those devices that have them.
7828 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7829 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7830 /* Setup replenish threshold. */
7831 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7833 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7834 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7835 ((u64) tpr->rx_jmb_mapping >> 32));
7836 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7837 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7838 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7839 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7840 BDINFO_FLAGS_USE_EXT_RECV);
7841 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7842 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7843 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7845 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7846 BDINFO_FLAGS_DISABLED);
7849 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7850 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7851 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7852 (RX_STD_MAX_SIZE << 2);
7854 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7856 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7858 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7860 tpr->rx_std_prod_idx = tp->rx_pending;
7861 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7863 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7864 tp->rx_jumbo_pending : 0;
7865 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7867 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7868 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7869 tw32(STD_REPLENISH_LWM, 32);
7870 tw32(JMB_REPLENISH_LWM, 16);
7873 tg3_rings_reset(tp);
7875 /* Initialize MAC address and backoff seed. */
7876 __tg3_set_mac_addr(tp, 0);
7878 /* MTU + ethernet header + FCS + optional VLAN tag */
7879 tw32(MAC_RX_MTU_SIZE,
7880 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7882 /* The slot time is changed by tg3_setup_phy if we
7883 * run at gigabit with half duplex.
7885 tw32(MAC_TX_LENGTHS,
7886 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7887 (6 << TX_LENGTHS_IPG_SHIFT) |
7888 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7890 /* Receive rules. */
7891 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7892 tw32(RCVLPC_CONFIG, 0x0181);
7894 /* Calculate RDMAC_MODE setting early, we need it to determine
7895 * the RCVLPC_STATE_ENABLE mask.
7897 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7898 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7899 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7900 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7901 RDMAC_MODE_LNGREAD_ENAB);
7903 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7904 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7906 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7907 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7908 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7909 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7910 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7911 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7913 /* If statement applies to 5705 and 5750 PCI devices only */
7914 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7915 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7916 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7917 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7918 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7919 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7920 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7921 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7922 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7926 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7927 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7929 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7930 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7932 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7933 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7934 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7935 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7937 /* Receive/send statistics. */
7938 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7939 val = tr32(RCVLPC_STATS_ENABLE);
7940 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7941 tw32(RCVLPC_STATS_ENABLE, val);
7942 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7943 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7944 val = tr32(RCVLPC_STATS_ENABLE);
7945 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7946 tw32(RCVLPC_STATS_ENABLE, val);
7948 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7950 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7951 tw32(SNDDATAI_STATSENAB, 0xffffff);
7952 tw32(SNDDATAI_STATSCTRL,
7953 (SNDDATAI_SCTRL_ENABLE |
7954 SNDDATAI_SCTRL_FASTUPD));
7956 /* Setup host coalescing engine. */
7957 tw32(HOSTCC_MODE, 0);
7958 for (i = 0; i < 2000; i++) {
7959 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7964 __tg3_set_coalesce(tp, &tp->coal);
7966 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7967 /* Status/statistics block address. See tg3_timer,
7968 * the tg3_periodic_fetch_stats call there, and
7969 * tg3_get_stats to see how this works for 5705/5750 chips.
7971 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7972 ((u64) tp->stats_mapping >> 32));
7973 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7974 ((u64) tp->stats_mapping & 0xffffffff));
7975 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7977 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7979 /* Clear statistics and status block memory areas */
7980 for (i = NIC_SRAM_STATS_BLK;
7981 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7983 tg3_write_mem(tp, i, 0);
7988 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7990 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7991 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7992 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7993 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7995 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7996 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7997 /* reset to prevent losing 1st rx packet intermittently */
7998 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8002 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8003 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8006 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8007 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8008 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8009 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8010 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8011 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8012 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8015 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8016 * If TG3_FLG2_IS_NIC is zero, we should read the
8017 * register to preserve the GPIO settings for LOMs. The GPIOs,
8018 * whether used as inputs or outputs, are set by boot code after
8021 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8024 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8025 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8026 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8028 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8029 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8030 GRC_LCLCTRL_GPIO_OUTPUT3;
8032 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8033 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8035 tp->grc_local_ctrl &= ~gpio_mask;
8036 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8038 /* GPIO1 must be driven high for eeprom write protect */
8039 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8040 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8041 GRC_LCLCTRL_GPIO_OUTPUT1);
8043 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8046 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8047 val = tr32(MSGINT_MODE);
8048 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8049 tw32(MSGINT_MODE, val);
8052 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8053 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8057 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8058 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8059 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8060 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8061 WDMAC_MODE_LNGREAD_ENAB);
8063 /* If statement applies to 5705 and 5750 PCI devices only */
8064 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8065 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8066 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8067 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8068 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8069 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8071 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8072 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8073 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8074 val |= WDMAC_MODE_RX_ACCEL;
8078 /* Enable host coalescing bug fix */
8079 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8080 val |= WDMAC_MODE_STATUS_TAG_FIX;
8082 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8083 val |= WDMAC_MODE_BURST_ALL_DATA;
8085 tw32_f(WDMAC_MODE, val);
8088 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8091 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8093 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8094 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8095 pcix_cmd |= PCI_X_CMD_READ_2K;
8096 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8097 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8098 pcix_cmd |= PCI_X_CMD_READ_2K;
8100 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8104 tw32_f(RDMAC_MODE, rdmac_mode);
8107 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8108 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8109 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8111 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8113 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8115 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8117 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8118 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8119 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8120 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8121 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8122 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8123 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8124 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8125 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8126 tw32(SNDBDI_MODE, val);
8127 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8129 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8130 err = tg3_load_5701_a0_firmware_fix(tp);
8135 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8136 err = tg3_load_tso_firmware(tp);
8141 tp->tx_mode = TX_MODE_ENABLE;
8142 tw32_f(MAC_TX_MODE, tp->tx_mode);
8145 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8146 u32 reg = MAC_RSS_INDIR_TBL_0;
8147 u8 *ent = (u8 *)&val;
8149 /* Setup the indirection table */
8150 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8151 int idx = i % sizeof(val);
8153 ent[idx] = i % (tp->irq_cnt - 1);
8154 if (idx == sizeof(val) - 1) {
8160 /* Setup the "secret" hash key. */
8161 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8162 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8163 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8164 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8165 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8166 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8167 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8168 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8169 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8170 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8173 tp->rx_mode = RX_MODE_ENABLE;
8174 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8175 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8177 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8178 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8179 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8180 RX_MODE_RSS_IPV6_HASH_EN |
8181 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8182 RX_MODE_RSS_IPV4_HASH_EN |
8183 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8185 tw32_f(MAC_RX_MODE, tp->rx_mode);
8188 tw32(MAC_LED_CTRL, tp->led_ctrl);
8190 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8191 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8192 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8195 tw32_f(MAC_RX_MODE, tp->rx_mode);
8198 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8199 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8200 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8201 /* Set drive transmission level to 1.2V */
8202 /* only if the signal pre-emphasis bit is not set */
8203 val = tr32(MAC_SERDES_CFG);
8206 tw32(MAC_SERDES_CFG, val);
8208 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8209 tw32(MAC_SERDES_CFG, 0x616000);
8212 /* Prevent chip from dropping frames when flow control
8215 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8219 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8221 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8222 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8223 /* Use hardware link auto-negotiation */
8224 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8227 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8228 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8231 tmp = tr32(SERDES_RX_CTRL);
8232 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8233 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8234 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8235 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8238 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8239 if (tp->link_config.phy_is_low_power) {
8240 tp->link_config.phy_is_low_power = 0;
8241 tp->link_config.speed = tp->link_config.orig_speed;
8242 tp->link_config.duplex = tp->link_config.orig_duplex;
8243 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8246 err = tg3_setup_phy(tp, 0);
8250 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8251 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8254 /* Clear CRC stats. */
8255 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8256 tg3_writephy(tp, MII_TG3_TEST1,
8257 tmp | MII_TG3_TEST1_CRC_EN);
8258 tg3_readphy(tp, 0x14, &tmp);
8263 __tg3_set_rx_mode(tp->dev);
8265 /* Initialize receive rules. */
8266 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8267 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8268 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8269 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8271 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8272 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8276 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8280 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8282 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8284 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8286 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8288 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8290 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8292 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8294 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8296 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8298 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8300 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8302 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8304 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8306 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8314 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8315 /* Write our heartbeat update interval to APE. */
8316 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8317 APE_HOST_HEARTBEAT_INT_DISABLE);
8319 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8324 /* Called at device open time to get the chip ready for
8325 * packet processing. Invoked with tp->lock held.
8327 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8329 tg3_switch_clocks(tp);
8331 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8333 return tg3_reset_hw(tp, reset_phy);
8336 #define TG3_STAT_ADD32(PSTAT, REG) \
8337 do { u32 __val = tr32(REG); \
8338 (PSTAT)->low += __val; \
8339 if ((PSTAT)->low < __val) \
8340 (PSTAT)->high += 1; \
8343 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8345 struct tg3_hw_stats *sp = tp->hw_stats;
8347 if (!netif_carrier_ok(tp->dev))
8350 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8351 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8352 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8353 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8354 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8355 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8356 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8357 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8358 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8359 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8360 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8361 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8362 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8364 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8365 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8366 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8367 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8368 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8369 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8370 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8371 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8372 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8373 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8374 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8375 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8376 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8377 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8379 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8380 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8381 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8384 static void tg3_timer(unsigned long __opaque)
8386 struct tg3 *tp = (struct tg3 *) __opaque;
8391 spin_lock(&tp->lock);
8393 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8394 /* All of this garbage is because when using non-tagged
8395 * IRQ status the mailbox/status_block protocol the chip
8396 * uses with the cpu is race prone.
8398 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8399 tw32(GRC_LOCAL_CTRL,
8400 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8402 tw32(HOSTCC_MODE, tp->coalesce_mode |
8403 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8406 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8407 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8408 spin_unlock(&tp->lock);
8409 schedule_work(&tp->reset_task);
8414 /* This part only runs once per second. */
8415 if (!--tp->timer_counter) {
8416 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8417 tg3_periodic_fetch_stats(tp);
8419 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8423 mac_stat = tr32(MAC_STATUS);
8426 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8427 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8429 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8433 tg3_setup_phy(tp, 0);
8434 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8435 u32 mac_stat = tr32(MAC_STATUS);
8438 if (netif_carrier_ok(tp->dev) &&
8439 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8442 if (! netif_carrier_ok(tp->dev) &&
8443 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8444 MAC_STATUS_SIGNAL_DET))) {
8448 if (!tp->serdes_counter) {
8451 ~MAC_MODE_PORT_MODE_MASK));
8453 tw32_f(MAC_MODE, tp->mac_mode);
8456 tg3_setup_phy(tp, 0);
8458 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8459 tg3_serdes_parallel_detect(tp);
8461 tp->timer_counter = tp->timer_multiplier;
8464 /* Heartbeat is only sent once every 2 seconds.
8466 * The heartbeat is to tell the ASF firmware that the host
8467 * driver is still alive. In the event that the OS crashes,
8468 * ASF needs to reset the hardware to free up the FIFO space
8469 * that may be filled with rx packets destined for the host.
8470 * If the FIFO is full, ASF will no longer function properly.
8472 * Unintended resets have been reported on real time kernels
8473 * where the timer doesn't run on time. Netpoll will also have
8476 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8477 * to check the ring condition when the heartbeat is expiring
8478 * before doing the reset. This will prevent most unintended
8481 if (!--tp->asf_counter) {
8482 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8483 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8484 tg3_wait_for_event_ack(tp);
8486 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8487 FWCMD_NICDRV_ALIVE3);
8488 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8489 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8490 TG3_FW_UPDATE_TIMEOUT_SEC);
8492 tg3_generate_fw_event(tp);
8494 tp->asf_counter = tp->asf_multiplier;
8497 spin_unlock(&tp->lock);
8500 tp->timer.expires = jiffies + tp->timer_offset;
8501 add_timer(&tp->timer);
8504 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8507 unsigned long flags;
8509 struct tg3_napi *tnapi = &tp->napi[irq_num];
8511 if (tp->irq_cnt == 1)
8512 name = tp->dev->name;
8514 name = &tnapi->irq_lbl[0];
8515 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8516 name[IFNAMSIZ-1] = 0;
8519 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8521 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8523 flags = IRQF_SAMPLE_RANDOM;
8526 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8527 fn = tg3_interrupt_tagged;
8528 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8531 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8534 static int tg3_test_interrupt(struct tg3 *tp)
8536 struct tg3_napi *tnapi = &tp->napi[0];
8537 struct net_device *dev = tp->dev;
8538 int err, i, intr_ok = 0;
8541 if (!netif_running(dev))
8544 tg3_disable_ints(tp);
8546 free_irq(tnapi->irq_vec, tnapi);
8549 * Turn off MSI one shot mode. Otherwise this test has no
8550 * observable way to know whether the interrupt was delivered.
8552 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8553 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8554 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8555 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8556 tw32(MSGINT_MODE, val);
8559 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8560 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8564 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8565 tg3_enable_ints(tp);
8567 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8570 for (i = 0; i < 5; i++) {
8571 u32 int_mbox, misc_host_ctrl;
8573 int_mbox = tr32_mailbox(tnapi->int_mbox);
8574 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8576 if ((int_mbox != 0) ||
8577 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8585 tg3_disable_ints(tp);
8587 free_irq(tnapi->irq_vec, tnapi);
8589 err = tg3_request_irq(tp, 0);
8595 /* Reenable MSI one shot mode. */
8596 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8597 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8598 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8599 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8600 tw32(MSGINT_MODE, val);
8608 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8609 * successfully restored
8611 static int tg3_test_msi(struct tg3 *tp)
8616 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8619 /* Turn off SERR reporting in case MSI terminates with Master
8622 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8623 pci_write_config_word(tp->pdev, PCI_COMMAND,
8624 pci_cmd & ~PCI_COMMAND_SERR);
8626 err = tg3_test_interrupt(tp);
8628 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8633 /* other failures */
8637 /* MSI test failed, go back to INTx mode */
8638 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8639 "to INTx mode. Please report this failure to the PCI "
8640 "maintainer and include system chipset information\n");
8642 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8644 pci_disable_msi(tp->pdev);
8646 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8648 err = tg3_request_irq(tp, 0);
8652 /* Need to reset the chip because the MSI cycle may have terminated
8653 * with Master Abort.
8655 tg3_full_lock(tp, 1);
8657 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8658 err = tg3_init_hw(tp, 1);
8660 tg3_full_unlock(tp);
8663 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8668 static int tg3_request_firmware(struct tg3 *tp)
8670 const __be32 *fw_data;
8672 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8673 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8678 fw_data = (void *)tp->fw->data;
8680 /* Firmware blob starts with version numbers, followed by
8681 * start address and _full_ length including BSS sections
8682 * (which must be longer than the actual data, of course
8685 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8686 if (tp->fw_len < (tp->fw->size - 12)) {
8687 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8688 tp->fw_len, tp->fw_needed);
8689 release_firmware(tp->fw);
8694 /* We no longer need firmware; we have it. */
8695 tp->fw_needed = NULL;
8699 static bool tg3_enable_msix(struct tg3 *tp)
8701 int i, rc, cpus = num_online_cpus();
8702 struct msix_entry msix_ent[tp->irq_max];
8705 /* Just fallback to the simpler MSI mode. */
8709 * We want as many rx rings enabled as there are cpus.
8710 * The first MSIX vector only deals with link interrupts, etc,
8711 * so we add one to the number of vectors we are requesting.
8713 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8715 for (i = 0; i < tp->irq_max; i++) {
8716 msix_ent[i].entry = i;
8717 msix_ent[i].vector = 0;
8720 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8722 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8724 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8726 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8731 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8733 for (i = 0; i < tp->irq_max; i++)
8734 tp->napi[i].irq_vec = msix_ent[i].vector;
8736 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8737 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8738 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8740 tp->dev->real_num_tx_queues = 1;
8745 static void tg3_ints_init(struct tg3 *tp)
8747 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8748 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8749 /* All MSI supporting chips should support tagged
8750 * status. Assert that this is the case.
8752 netdev_warn(tp->dev,
8753 "MSI without TAGGED_STATUS? Not using MSI\n");
8757 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8758 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8759 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8760 pci_enable_msi(tp->pdev) == 0)
8761 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8763 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8764 u32 msi_mode = tr32(MSGINT_MODE);
8765 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8766 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8767 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8770 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8772 tp->napi[0].irq_vec = tp->pdev->irq;
8773 tp->dev->real_num_tx_queues = 1;
8777 static void tg3_ints_fini(struct tg3 *tp)
8779 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8780 pci_disable_msix(tp->pdev);
8781 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8782 pci_disable_msi(tp->pdev);
8783 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8784 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8787 static int tg3_open(struct net_device *dev)
8789 struct tg3 *tp = netdev_priv(dev);
8792 if (tp->fw_needed) {
8793 err = tg3_request_firmware(tp);
8794 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8798 netdev_warn(tp->dev, "TSO capability disabled\n");
8799 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8800 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8801 netdev_notice(tp->dev, "TSO capability restored\n");
8802 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8806 netif_carrier_off(tp->dev);
8808 err = tg3_set_power_state(tp, PCI_D0);
8812 tg3_full_lock(tp, 0);
8814 tg3_disable_ints(tp);
8815 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8817 tg3_full_unlock(tp);
8820 * Setup interrupts first so we know how
8821 * many NAPI resources to allocate
8825 /* The placement of this call is tied
8826 * to the setup and use of Host TX descriptors.
8828 err = tg3_alloc_consistent(tp);
8832 tg3_napi_enable(tp);
8834 for (i = 0; i < tp->irq_cnt; i++) {
8835 struct tg3_napi *tnapi = &tp->napi[i];
8836 err = tg3_request_irq(tp, i);
8838 for (i--; i >= 0; i--)
8839 free_irq(tnapi->irq_vec, tnapi);
8847 tg3_full_lock(tp, 0);
8849 err = tg3_init_hw(tp, 1);
8851 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8854 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8855 tp->timer_offset = HZ;
8857 tp->timer_offset = HZ / 10;
8859 BUG_ON(tp->timer_offset > HZ);
8860 tp->timer_counter = tp->timer_multiplier =
8861 (HZ / tp->timer_offset);
8862 tp->asf_counter = tp->asf_multiplier =
8863 ((HZ / tp->timer_offset) * 2);
8865 init_timer(&tp->timer);
8866 tp->timer.expires = jiffies + tp->timer_offset;
8867 tp->timer.data = (unsigned long) tp;
8868 tp->timer.function = tg3_timer;
8871 tg3_full_unlock(tp);
8876 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8877 err = tg3_test_msi(tp);
8880 tg3_full_lock(tp, 0);
8881 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8883 tg3_full_unlock(tp);
8888 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8889 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8890 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8891 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8892 u32 val = tr32(PCIE_TRANSACTION_CFG);
8894 tw32(PCIE_TRANSACTION_CFG,
8895 val | PCIE_TRANS_CFG_1SHOT_MSI);
8901 tg3_full_lock(tp, 0);
8903 add_timer(&tp->timer);
8904 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8905 tg3_enable_ints(tp);
8907 tg3_full_unlock(tp);
8909 netif_tx_start_all_queues(dev);
8914 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8915 struct tg3_napi *tnapi = &tp->napi[i];
8916 free_irq(tnapi->irq_vec, tnapi);
8920 tg3_napi_disable(tp);
8921 tg3_free_consistent(tp);
8929 /*static*/ void tg3_dump_state(struct tg3 *tp)
8931 u32 val32, val32_2, val32_3, val32_4, val32_5;
8934 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8936 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8937 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8938 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8942 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8943 tr32(MAC_MODE), tr32(MAC_STATUS));
8944 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8945 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8946 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8947 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8948 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8949 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8951 /* Send data initiator control block */
8952 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8953 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8954 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8955 tr32(SNDDATAI_STATSCTRL));
8957 /* Send data completion control block */
8958 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8960 /* Send BD ring selector block */
8961 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8962 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8964 /* Send BD initiator control block */
8965 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8966 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8968 /* Send BD completion control block */
8969 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8971 /* Receive list placement control block */
8972 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8973 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8974 printk(" RCVLPC_STATSCTRL[%08x]\n",
8975 tr32(RCVLPC_STATSCTRL));
8977 /* Receive data and receive BD initiator control block */
8978 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8979 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8981 /* Receive data completion control block */
8982 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8985 /* Receive BD initiator control block */
8986 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8987 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8989 /* Receive BD completion control block */
8990 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8991 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8993 /* Receive list selector control block */
8994 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8995 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8997 /* Mbuf cluster free block */
8998 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8999 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
9001 /* Host coalescing control block */
9002 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
9003 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
9004 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
9005 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9006 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9007 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
9008 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9009 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9010 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
9011 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
9012 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
9013 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
9015 /* Memory arbiter control block */
9016 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
9017 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
9019 /* Buffer manager control block */
9020 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
9021 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
9022 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
9023 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
9024 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
9025 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
9026 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
9027 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
9029 /* Read DMA control block */
9030 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
9031 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
9033 /* Write DMA control block */
9034 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
9035 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
9037 /* DMA completion block */
9038 printk("DEBUG: DMAC_MODE[%08x]\n",
9042 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
9043 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
9044 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9045 tr32(GRC_LOCAL_CTRL));
9048 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9049 tr32(RCVDBDI_JUMBO_BD + 0x0),
9050 tr32(RCVDBDI_JUMBO_BD + 0x4),
9051 tr32(RCVDBDI_JUMBO_BD + 0x8),
9052 tr32(RCVDBDI_JUMBO_BD + 0xc));
9053 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9054 tr32(RCVDBDI_STD_BD + 0x0),
9055 tr32(RCVDBDI_STD_BD + 0x4),
9056 tr32(RCVDBDI_STD_BD + 0x8),
9057 tr32(RCVDBDI_STD_BD + 0xc));
9058 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9059 tr32(RCVDBDI_MINI_BD + 0x0),
9060 tr32(RCVDBDI_MINI_BD + 0x4),
9061 tr32(RCVDBDI_MINI_BD + 0x8),
9062 tr32(RCVDBDI_MINI_BD + 0xc));
9064 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9065 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9066 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9067 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9068 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9069 val32, val32_2, val32_3, val32_4);
9071 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9072 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9073 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9074 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9075 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9076 val32, val32_2, val32_3, val32_4);
9078 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9079 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9080 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9081 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9082 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9083 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9084 val32, val32_2, val32_3, val32_4, val32_5);
9086 /* SW status block */
9088 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9091 sblk->rx_jumbo_consumer,
9093 sblk->rx_mini_consumer,
9094 sblk->idx[0].rx_producer,
9095 sblk->idx[0].tx_consumer);
9097 /* SW statistics block */
9098 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9099 ((u32 *)tp->hw_stats)[0],
9100 ((u32 *)tp->hw_stats)[1],
9101 ((u32 *)tp->hw_stats)[2],
9102 ((u32 *)tp->hw_stats)[3]);
9105 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9106 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9107 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9108 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9109 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9111 /* NIC side send descriptors. */
9112 for (i = 0; i < 6; i++) {
9115 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9116 + (i * sizeof(struct tg3_tx_buffer_desc));
9117 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9119 readl(txd + 0x0), readl(txd + 0x4),
9120 readl(txd + 0x8), readl(txd + 0xc));
9123 /* NIC side RX descriptors. */
9124 for (i = 0; i < 6; i++) {
9127 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9128 + (i * sizeof(struct tg3_rx_buffer_desc));
9129 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9131 readl(rxd + 0x0), readl(rxd + 0x4),
9132 readl(rxd + 0x8), readl(rxd + 0xc));
9133 rxd += (4 * sizeof(u32));
9134 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9136 readl(rxd + 0x0), readl(rxd + 0x4),
9137 readl(rxd + 0x8), readl(rxd + 0xc));
9140 for (i = 0; i < 6; i++) {
9143 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9144 + (i * sizeof(struct tg3_rx_buffer_desc));
9145 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9147 readl(rxd + 0x0), readl(rxd + 0x4),
9148 readl(rxd + 0x8), readl(rxd + 0xc));
9149 rxd += (4 * sizeof(u32));
9150 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9152 readl(rxd + 0x0), readl(rxd + 0x4),
9153 readl(rxd + 0x8), readl(rxd + 0xc));
9158 static struct net_device_stats *tg3_get_stats(struct net_device *);
9159 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9161 static int tg3_close(struct net_device *dev)
9164 struct tg3 *tp = netdev_priv(dev);
9166 tg3_napi_disable(tp);
9167 cancel_work_sync(&tp->reset_task);
9169 netif_tx_stop_all_queues(dev);
9171 del_timer_sync(&tp->timer);
9175 tg3_full_lock(tp, 1);
9180 tg3_disable_ints(tp);
9182 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9184 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9186 tg3_full_unlock(tp);
9188 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9189 struct tg3_napi *tnapi = &tp->napi[i];
9190 free_irq(tnapi->irq_vec, tnapi);
9195 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9196 sizeof(tp->net_stats_prev));
9197 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9198 sizeof(tp->estats_prev));
9200 tg3_free_consistent(tp);
9202 tg3_set_power_state(tp, PCI_D3hot);
9204 netif_carrier_off(tp->dev);
9209 static inline unsigned long get_stat64(tg3_stat64_t *val)
9213 #if (BITS_PER_LONG == 32)
9216 ret = ((u64)val->high << 32) | ((u64)val->low);
9221 static inline u64 get_estat64(tg3_stat64_t *val)
9223 return ((u64)val->high << 32) | ((u64)val->low);
9226 static unsigned long calc_crc_errors(struct tg3 *tp)
9228 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9230 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9231 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9232 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9235 spin_lock_bh(&tp->lock);
9236 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9237 tg3_writephy(tp, MII_TG3_TEST1,
9238 val | MII_TG3_TEST1_CRC_EN);
9239 tg3_readphy(tp, 0x14, &val);
9242 spin_unlock_bh(&tp->lock);
9244 tp->phy_crc_errors += val;
9246 return tp->phy_crc_errors;
9249 return get_stat64(&hw_stats->rx_fcs_errors);
9252 #define ESTAT_ADD(member) \
9253 estats->member = old_estats->member + \
9254 get_estat64(&hw_stats->member)
9256 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9258 struct tg3_ethtool_stats *estats = &tp->estats;
9259 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9260 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9265 ESTAT_ADD(rx_octets);
9266 ESTAT_ADD(rx_fragments);
9267 ESTAT_ADD(rx_ucast_packets);
9268 ESTAT_ADD(rx_mcast_packets);
9269 ESTAT_ADD(rx_bcast_packets);
9270 ESTAT_ADD(rx_fcs_errors);
9271 ESTAT_ADD(rx_align_errors);
9272 ESTAT_ADD(rx_xon_pause_rcvd);
9273 ESTAT_ADD(rx_xoff_pause_rcvd);
9274 ESTAT_ADD(rx_mac_ctrl_rcvd);
9275 ESTAT_ADD(rx_xoff_entered);
9276 ESTAT_ADD(rx_frame_too_long_errors);
9277 ESTAT_ADD(rx_jabbers);
9278 ESTAT_ADD(rx_undersize_packets);
9279 ESTAT_ADD(rx_in_length_errors);
9280 ESTAT_ADD(rx_out_length_errors);
9281 ESTAT_ADD(rx_64_or_less_octet_packets);
9282 ESTAT_ADD(rx_65_to_127_octet_packets);
9283 ESTAT_ADD(rx_128_to_255_octet_packets);
9284 ESTAT_ADD(rx_256_to_511_octet_packets);
9285 ESTAT_ADD(rx_512_to_1023_octet_packets);
9286 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9287 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9288 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9289 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9290 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9292 ESTAT_ADD(tx_octets);
9293 ESTAT_ADD(tx_collisions);
9294 ESTAT_ADD(tx_xon_sent);
9295 ESTAT_ADD(tx_xoff_sent);
9296 ESTAT_ADD(tx_flow_control);
9297 ESTAT_ADD(tx_mac_errors);
9298 ESTAT_ADD(tx_single_collisions);
9299 ESTAT_ADD(tx_mult_collisions);
9300 ESTAT_ADD(tx_deferred);
9301 ESTAT_ADD(tx_excessive_collisions);
9302 ESTAT_ADD(tx_late_collisions);
9303 ESTAT_ADD(tx_collide_2times);
9304 ESTAT_ADD(tx_collide_3times);
9305 ESTAT_ADD(tx_collide_4times);
9306 ESTAT_ADD(tx_collide_5times);
9307 ESTAT_ADD(tx_collide_6times);
9308 ESTAT_ADD(tx_collide_7times);
9309 ESTAT_ADD(tx_collide_8times);
9310 ESTAT_ADD(tx_collide_9times);
9311 ESTAT_ADD(tx_collide_10times);
9312 ESTAT_ADD(tx_collide_11times);
9313 ESTAT_ADD(tx_collide_12times);
9314 ESTAT_ADD(tx_collide_13times);
9315 ESTAT_ADD(tx_collide_14times);
9316 ESTAT_ADD(tx_collide_15times);
9317 ESTAT_ADD(tx_ucast_packets);
9318 ESTAT_ADD(tx_mcast_packets);
9319 ESTAT_ADD(tx_bcast_packets);
9320 ESTAT_ADD(tx_carrier_sense_errors);
9321 ESTAT_ADD(tx_discards);
9322 ESTAT_ADD(tx_errors);
9324 ESTAT_ADD(dma_writeq_full);
9325 ESTAT_ADD(dma_write_prioq_full);
9326 ESTAT_ADD(rxbds_empty);
9327 ESTAT_ADD(rx_discards);
9328 ESTAT_ADD(rx_errors);
9329 ESTAT_ADD(rx_threshold_hit);
9331 ESTAT_ADD(dma_readq_full);
9332 ESTAT_ADD(dma_read_prioq_full);
9333 ESTAT_ADD(tx_comp_queue_full);
9335 ESTAT_ADD(ring_set_send_prod_index);
9336 ESTAT_ADD(ring_status_update);
9337 ESTAT_ADD(nic_irqs);
9338 ESTAT_ADD(nic_avoided_irqs);
9339 ESTAT_ADD(nic_tx_threshold_hit);
9344 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9346 struct tg3 *tp = netdev_priv(dev);
9347 struct net_device_stats *stats = &tp->net_stats;
9348 struct net_device_stats *old_stats = &tp->net_stats_prev;
9349 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9354 stats->rx_packets = old_stats->rx_packets +
9355 get_stat64(&hw_stats->rx_ucast_packets) +
9356 get_stat64(&hw_stats->rx_mcast_packets) +
9357 get_stat64(&hw_stats->rx_bcast_packets);
9359 stats->tx_packets = old_stats->tx_packets +
9360 get_stat64(&hw_stats->tx_ucast_packets) +
9361 get_stat64(&hw_stats->tx_mcast_packets) +
9362 get_stat64(&hw_stats->tx_bcast_packets);
9364 stats->rx_bytes = old_stats->rx_bytes +
9365 get_stat64(&hw_stats->rx_octets);
9366 stats->tx_bytes = old_stats->tx_bytes +
9367 get_stat64(&hw_stats->tx_octets);
9369 stats->rx_errors = old_stats->rx_errors +
9370 get_stat64(&hw_stats->rx_errors);
9371 stats->tx_errors = old_stats->tx_errors +
9372 get_stat64(&hw_stats->tx_errors) +
9373 get_stat64(&hw_stats->tx_mac_errors) +
9374 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9375 get_stat64(&hw_stats->tx_discards);
9377 stats->multicast = old_stats->multicast +
9378 get_stat64(&hw_stats->rx_mcast_packets);
9379 stats->collisions = old_stats->collisions +
9380 get_stat64(&hw_stats->tx_collisions);
9382 stats->rx_length_errors = old_stats->rx_length_errors +
9383 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9384 get_stat64(&hw_stats->rx_undersize_packets);
9386 stats->rx_over_errors = old_stats->rx_over_errors +
9387 get_stat64(&hw_stats->rxbds_empty);
9388 stats->rx_frame_errors = old_stats->rx_frame_errors +
9389 get_stat64(&hw_stats->rx_align_errors);
9390 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9391 get_stat64(&hw_stats->tx_discards);
9392 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9393 get_stat64(&hw_stats->tx_carrier_sense_errors);
9395 stats->rx_crc_errors = old_stats->rx_crc_errors +
9396 calc_crc_errors(tp);
9398 stats->rx_missed_errors = old_stats->rx_missed_errors +
9399 get_stat64(&hw_stats->rx_discards);
9404 static inline u32 calc_crc(unsigned char *buf, int len)
9412 for (j = 0; j < len; j++) {
9415 for (k = 0; k < 8; k++) {
9428 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9430 /* accept or reject all multicast frames */
9431 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9432 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9433 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9434 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9437 static void __tg3_set_rx_mode(struct net_device *dev)
9439 struct tg3 *tp = netdev_priv(dev);
9442 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9443 RX_MODE_KEEP_VLAN_TAG);
9445 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9448 #if TG3_VLAN_TAG_USED
9450 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9451 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9453 /* By definition, VLAN is disabled always in this
9456 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9457 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9460 if (dev->flags & IFF_PROMISC) {
9461 /* Promiscuous mode. */
9462 rx_mode |= RX_MODE_PROMISC;
9463 } else if (dev->flags & IFF_ALLMULTI) {
9464 /* Accept all multicast. */
9465 tg3_set_multi (tp, 1);
9466 } else if (netdev_mc_empty(dev)) {
9467 /* Reject all multicast. */
9468 tg3_set_multi (tp, 0);
9470 /* Accept one or more multicast(s). */
9471 struct netdev_hw_addr *ha;
9472 u32 mc_filter[4] = { 0, };
9477 netdev_for_each_mc_addr(ha, dev) {
9478 crc = calc_crc(ha->addr, ETH_ALEN);
9480 regidx = (bit & 0x60) >> 5;
9482 mc_filter[regidx] |= (1 << bit);
9485 tw32(MAC_HASH_REG_0, mc_filter[0]);
9486 tw32(MAC_HASH_REG_1, mc_filter[1]);
9487 tw32(MAC_HASH_REG_2, mc_filter[2]);
9488 tw32(MAC_HASH_REG_3, mc_filter[3]);
9491 if (rx_mode != tp->rx_mode) {
9492 tp->rx_mode = rx_mode;
9493 tw32_f(MAC_RX_MODE, rx_mode);
9498 static void tg3_set_rx_mode(struct net_device *dev)
9500 struct tg3 *tp = netdev_priv(dev);
9502 if (!netif_running(dev))
9505 tg3_full_lock(tp, 0);
9506 __tg3_set_rx_mode(dev);
9507 tg3_full_unlock(tp);
9510 #define TG3_REGDUMP_LEN (32 * 1024)
9512 static int tg3_get_regs_len(struct net_device *dev)
9514 return TG3_REGDUMP_LEN;
9517 static void tg3_get_regs(struct net_device *dev,
9518 struct ethtool_regs *regs, void *_p)
9521 struct tg3 *tp = netdev_priv(dev);
9527 memset(p, 0, TG3_REGDUMP_LEN);
9529 if (tp->link_config.phy_is_low_power)
9532 tg3_full_lock(tp, 0);
9534 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9535 #define GET_REG32_LOOP(base,len) \
9536 do { p = (u32 *)(orig_p + (base)); \
9537 for (i = 0; i < len; i += 4) \
9538 __GET_REG32((base) + i); \
9540 #define GET_REG32_1(reg) \
9541 do { p = (u32 *)(orig_p + (reg)); \
9542 __GET_REG32((reg)); \
9545 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9546 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9547 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9548 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9549 GET_REG32_1(SNDDATAC_MODE);
9550 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9551 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9552 GET_REG32_1(SNDBDC_MODE);
9553 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9554 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9555 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9556 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9557 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9558 GET_REG32_1(RCVDCC_MODE);
9559 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9560 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9561 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9562 GET_REG32_1(MBFREE_MODE);
9563 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9564 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9565 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9566 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9567 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9568 GET_REG32_1(RX_CPU_MODE);
9569 GET_REG32_1(RX_CPU_STATE);
9570 GET_REG32_1(RX_CPU_PGMCTR);
9571 GET_REG32_1(RX_CPU_HWBKPT);
9572 GET_REG32_1(TX_CPU_MODE);
9573 GET_REG32_1(TX_CPU_STATE);
9574 GET_REG32_1(TX_CPU_PGMCTR);
9575 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9576 GET_REG32_LOOP(FTQ_RESET, 0x120);
9577 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9578 GET_REG32_1(DMAC_MODE);
9579 GET_REG32_LOOP(GRC_MODE, 0x4c);
9580 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9581 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9584 #undef GET_REG32_LOOP
9587 tg3_full_unlock(tp);
9590 static int tg3_get_eeprom_len(struct net_device *dev)
9592 struct tg3 *tp = netdev_priv(dev);
9594 return tp->nvram_size;
9597 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9599 struct tg3 *tp = netdev_priv(dev);
9602 u32 i, offset, len, b_offset, b_count;
9605 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9608 if (tp->link_config.phy_is_low_power)
9611 offset = eeprom->offset;
9615 eeprom->magic = TG3_EEPROM_MAGIC;
9618 /* adjustments to start on required 4 byte boundary */
9619 b_offset = offset & 3;
9620 b_count = 4 - b_offset;
9621 if (b_count > len) {
9622 /* i.e. offset=1 len=2 */
9625 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9628 memcpy(data, ((char*)&val) + b_offset, b_count);
9631 eeprom->len += b_count;
9634 /* read bytes upto the last 4 byte boundary */
9635 pd = &data[eeprom->len];
9636 for (i = 0; i < (len - (len & 3)); i += 4) {
9637 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9642 memcpy(pd + i, &val, 4);
9647 /* read last bytes not ending on 4 byte boundary */
9648 pd = &data[eeprom->len];
9650 b_offset = offset + len - b_count;
9651 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9654 memcpy(pd, &val, b_count);
9655 eeprom->len += b_count;
9660 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9662 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9664 struct tg3 *tp = netdev_priv(dev);
9666 u32 offset, len, b_offset, odd_len;
9670 if (tp->link_config.phy_is_low_power)
9673 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9674 eeprom->magic != TG3_EEPROM_MAGIC)
9677 offset = eeprom->offset;
9680 if ((b_offset = (offset & 3))) {
9681 /* adjustments to start on required 4 byte boundary */
9682 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9693 /* adjustments to end on required 4 byte boundary */
9695 len = (len + 3) & ~3;
9696 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9702 if (b_offset || odd_len) {
9703 buf = kmalloc(len, GFP_KERNEL);
9707 memcpy(buf, &start, 4);
9709 memcpy(buf+len-4, &end, 4);
9710 memcpy(buf + b_offset, data, eeprom->len);
9713 ret = tg3_nvram_write_block(tp, offset, len, buf);
9721 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9723 struct tg3 *tp = netdev_priv(dev);
9725 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9726 struct phy_device *phydev;
9727 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9729 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9730 return phy_ethtool_gset(phydev, cmd);
9733 cmd->supported = (SUPPORTED_Autoneg);
9735 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9736 cmd->supported |= (SUPPORTED_1000baseT_Half |
9737 SUPPORTED_1000baseT_Full);
9739 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9740 cmd->supported |= (SUPPORTED_100baseT_Half |
9741 SUPPORTED_100baseT_Full |
9742 SUPPORTED_10baseT_Half |
9743 SUPPORTED_10baseT_Full |
9745 cmd->port = PORT_TP;
9747 cmd->supported |= SUPPORTED_FIBRE;
9748 cmd->port = PORT_FIBRE;
9751 cmd->advertising = tp->link_config.advertising;
9752 if (netif_running(dev)) {
9753 cmd->speed = tp->link_config.active_speed;
9754 cmd->duplex = tp->link_config.active_duplex;
9756 cmd->phy_address = tp->phy_addr;
9757 cmd->transceiver = XCVR_INTERNAL;
9758 cmd->autoneg = tp->link_config.autoneg;
9764 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9766 struct tg3 *tp = netdev_priv(dev);
9768 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9769 struct phy_device *phydev;
9770 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9772 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9773 return phy_ethtool_sset(phydev, cmd);
9776 if (cmd->autoneg != AUTONEG_ENABLE &&
9777 cmd->autoneg != AUTONEG_DISABLE)
9780 if (cmd->autoneg == AUTONEG_DISABLE &&
9781 cmd->duplex != DUPLEX_FULL &&
9782 cmd->duplex != DUPLEX_HALF)
9785 if (cmd->autoneg == AUTONEG_ENABLE) {
9786 u32 mask = ADVERTISED_Autoneg |
9788 ADVERTISED_Asym_Pause;
9790 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9791 mask |= ADVERTISED_1000baseT_Half |
9792 ADVERTISED_1000baseT_Full;
9794 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9795 mask |= ADVERTISED_100baseT_Half |
9796 ADVERTISED_100baseT_Full |
9797 ADVERTISED_10baseT_Half |
9798 ADVERTISED_10baseT_Full |
9801 mask |= ADVERTISED_FIBRE;
9803 if (cmd->advertising & ~mask)
9806 mask &= (ADVERTISED_1000baseT_Half |
9807 ADVERTISED_1000baseT_Full |
9808 ADVERTISED_100baseT_Half |
9809 ADVERTISED_100baseT_Full |
9810 ADVERTISED_10baseT_Half |
9811 ADVERTISED_10baseT_Full);
9813 cmd->advertising &= mask;
9815 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9816 if (cmd->speed != SPEED_1000)
9819 if (cmd->duplex != DUPLEX_FULL)
9822 if (cmd->speed != SPEED_100 &&
9823 cmd->speed != SPEED_10)
9828 tg3_full_lock(tp, 0);
9830 tp->link_config.autoneg = cmd->autoneg;
9831 if (cmd->autoneg == AUTONEG_ENABLE) {
9832 tp->link_config.advertising = (cmd->advertising |
9833 ADVERTISED_Autoneg);
9834 tp->link_config.speed = SPEED_INVALID;
9835 tp->link_config.duplex = DUPLEX_INVALID;
9837 tp->link_config.advertising = 0;
9838 tp->link_config.speed = cmd->speed;
9839 tp->link_config.duplex = cmd->duplex;
9842 tp->link_config.orig_speed = tp->link_config.speed;
9843 tp->link_config.orig_duplex = tp->link_config.duplex;
9844 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9846 if (netif_running(dev))
9847 tg3_setup_phy(tp, 1);
9849 tg3_full_unlock(tp);
9854 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9856 struct tg3 *tp = netdev_priv(dev);
9858 strcpy(info->driver, DRV_MODULE_NAME);
9859 strcpy(info->version, DRV_MODULE_VERSION);
9860 strcpy(info->fw_version, tp->fw_ver);
9861 strcpy(info->bus_info, pci_name(tp->pdev));
9864 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9866 struct tg3 *tp = netdev_priv(dev);
9868 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9869 device_can_wakeup(&tp->pdev->dev))
9870 wol->supported = WAKE_MAGIC;
9874 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9875 device_can_wakeup(&tp->pdev->dev))
9876 wol->wolopts = WAKE_MAGIC;
9877 memset(&wol->sopass, 0, sizeof(wol->sopass));
9880 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9882 struct tg3 *tp = netdev_priv(dev);
9883 struct device *dp = &tp->pdev->dev;
9885 if (wol->wolopts & ~WAKE_MAGIC)
9887 if ((wol->wolopts & WAKE_MAGIC) &&
9888 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9891 spin_lock_bh(&tp->lock);
9892 if (wol->wolopts & WAKE_MAGIC) {
9893 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9894 device_set_wakeup_enable(dp, true);
9896 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9897 device_set_wakeup_enable(dp, false);
9899 spin_unlock_bh(&tp->lock);
9904 static u32 tg3_get_msglevel(struct net_device *dev)
9906 struct tg3 *tp = netdev_priv(dev);
9907 return tp->msg_enable;
9910 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9912 struct tg3 *tp = netdev_priv(dev);
9913 tp->msg_enable = value;
9916 static int tg3_set_tso(struct net_device *dev, u32 value)
9918 struct tg3 *tp = netdev_priv(dev);
9920 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9925 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9926 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9927 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9929 dev->features |= NETIF_F_TSO6;
9930 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9931 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9932 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9933 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9934 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9935 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9936 dev->features |= NETIF_F_TSO_ECN;
9938 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9940 return ethtool_op_set_tso(dev, value);
9943 static int tg3_nway_reset(struct net_device *dev)
9945 struct tg3 *tp = netdev_priv(dev);
9948 if (!netif_running(dev))
9951 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9954 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9955 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9957 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9961 spin_lock_bh(&tp->lock);
9963 tg3_readphy(tp, MII_BMCR, &bmcr);
9964 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9965 ((bmcr & BMCR_ANENABLE) ||
9966 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9967 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9971 spin_unlock_bh(&tp->lock);
9977 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9979 struct tg3 *tp = netdev_priv(dev);
9981 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9982 ering->rx_mini_max_pending = 0;
9983 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9984 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9986 ering->rx_jumbo_max_pending = 0;
9988 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9990 ering->rx_pending = tp->rx_pending;
9991 ering->rx_mini_pending = 0;
9992 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9993 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9995 ering->rx_jumbo_pending = 0;
9997 ering->tx_pending = tp->napi[0].tx_pending;
10000 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10002 struct tg3 *tp = netdev_priv(dev);
10003 int i, irq_sync = 0, err = 0;
10005 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
10006 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
10007 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10008 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10009 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10010 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10013 if (netif_running(dev)) {
10015 tg3_netif_stop(tp);
10019 tg3_full_lock(tp, irq_sync);
10021 tp->rx_pending = ering->rx_pending;
10023 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10024 tp->rx_pending > 63)
10025 tp->rx_pending = 63;
10026 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10028 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
10029 tp->napi[i].tx_pending = ering->tx_pending;
10031 if (netif_running(dev)) {
10032 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10033 err = tg3_restart_hw(tp, 1);
10035 tg3_netif_start(tp);
10038 tg3_full_unlock(tp);
10040 if (irq_sync && !err)
10046 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10048 struct tg3 *tp = netdev_priv(dev);
10050 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10052 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10053 epause->rx_pause = 1;
10055 epause->rx_pause = 0;
10057 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10058 epause->tx_pause = 1;
10060 epause->tx_pause = 0;
10063 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10065 struct tg3 *tp = netdev_priv(dev);
10068 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10070 struct phy_device *phydev;
10072 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10074 if (!(phydev->supported & SUPPORTED_Pause) ||
10075 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10076 ((epause->rx_pause && !epause->tx_pause) ||
10077 (!epause->rx_pause && epause->tx_pause))))
10080 tp->link_config.flowctrl = 0;
10081 if (epause->rx_pause) {
10082 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10084 if (epause->tx_pause) {
10085 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10086 newadv = ADVERTISED_Pause;
10088 newadv = ADVERTISED_Pause |
10089 ADVERTISED_Asym_Pause;
10090 } else if (epause->tx_pause) {
10091 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10092 newadv = ADVERTISED_Asym_Pause;
10096 if (epause->autoneg)
10097 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10099 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10101 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10102 u32 oldadv = phydev->advertising &
10103 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10104 if (oldadv != newadv) {
10105 phydev->advertising &=
10106 ~(ADVERTISED_Pause |
10107 ADVERTISED_Asym_Pause);
10108 phydev->advertising |= newadv;
10109 if (phydev->autoneg) {
10111 * Always renegotiate the link to
10112 * inform our link partner of our
10113 * flow control settings, even if the
10114 * flow control is forced. Let
10115 * tg3_adjust_link() do the final
10116 * flow control setup.
10118 return phy_start_aneg(phydev);
10122 if (!epause->autoneg)
10123 tg3_setup_flow_control(tp, 0, 0);
10125 tp->link_config.orig_advertising &=
10126 ~(ADVERTISED_Pause |
10127 ADVERTISED_Asym_Pause);
10128 tp->link_config.orig_advertising |= newadv;
10133 if (netif_running(dev)) {
10134 tg3_netif_stop(tp);
10138 tg3_full_lock(tp, irq_sync);
10140 if (epause->autoneg)
10141 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10143 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10144 if (epause->rx_pause)
10145 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10147 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10148 if (epause->tx_pause)
10149 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10151 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10153 if (netif_running(dev)) {
10154 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10155 err = tg3_restart_hw(tp, 1);
10157 tg3_netif_start(tp);
10160 tg3_full_unlock(tp);
10166 static u32 tg3_get_rx_csum(struct net_device *dev)
10168 struct tg3 *tp = netdev_priv(dev);
10169 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10172 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10174 struct tg3 *tp = netdev_priv(dev);
10176 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10182 spin_lock_bh(&tp->lock);
10184 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10186 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10187 spin_unlock_bh(&tp->lock);
10192 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10194 struct tg3 *tp = netdev_priv(dev);
10196 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10202 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10203 ethtool_op_set_tx_ipv6_csum(dev, data);
10205 ethtool_op_set_tx_csum(dev, data);
10210 static int tg3_get_sset_count (struct net_device *dev, int sset)
10214 return TG3_NUM_TEST;
10216 return TG3_NUM_STATS;
10218 return -EOPNOTSUPP;
10222 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10224 switch (stringset) {
10226 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10229 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10232 WARN_ON(1); /* we need a WARN() */
10237 static int tg3_phys_id(struct net_device *dev, u32 data)
10239 struct tg3 *tp = netdev_priv(dev);
10242 if (!netif_running(tp->dev))
10246 data = UINT_MAX / 2;
10248 for (i = 0; i < (data * 2); i++) {
10250 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10251 LED_CTRL_1000MBPS_ON |
10252 LED_CTRL_100MBPS_ON |
10253 LED_CTRL_10MBPS_ON |
10254 LED_CTRL_TRAFFIC_OVERRIDE |
10255 LED_CTRL_TRAFFIC_BLINK |
10256 LED_CTRL_TRAFFIC_LED);
10259 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10260 LED_CTRL_TRAFFIC_OVERRIDE);
10262 if (msleep_interruptible(500))
10265 tw32(MAC_LED_CTRL, tp->led_ctrl);
10269 static void tg3_get_ethtool_stats (struct net_device *dev,
10270 struct ethtool_stats *estats, u64 *tmp_stats)
10272 struct tg3 *tp = netdev_priv(dev);
10273 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10276 #define NVRAM_TEST_SIZE 0x100
10277 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10278 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10279 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10280 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10281 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10283 static int tg3_test_nvram(struct tg3 *tp)
10287 int i, j, k, err = 0, size;
10289 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10292 if (tg3_nvram_read(tp, 0, &magic) != 0)
10295 if (magic == TG3_EEPROM_MAGIC)
10296 size = NVRAM_TEST_SIZE;
10297 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10298 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10299 TG3_EEPROM_SB_FORMAT_1) {
10300 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10301 case TG3_EEPROM_SB_REVISION_0:
10302 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10304 case TG3_EEPROM_SB_REVISION_2:
10305 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10307 case TG3_EEPROM_SB_REVISION_3:
10308 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10315 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10316 size = NVRAM_SELFBOOT_HW_SIZE;
10320 buf = kmalloc(size, GFP_KERNEL);
10325 for (i = 0, j = 0; i < size; i += 4, j++) {
10326 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10333 /* Selfboot format */
10334 magic = be32_to_cpu(buf[0]);
10335 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10336 TG3_EEPROM_MAGIC_FW) {
10337 u8 *buf8 = (u8 *) buf, csum8 = 0;
10339 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10340 TG3_EEPROM_SB_REVISION_2) {
10341 /* For rev 2, the csum doesn't include the MBA. */
10342 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10344 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10347 for (i = 0; i < size; i++)
10360 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10361 TG3_EEPROM_MAGIC_HW) {
10362 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10363 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10364 u8 *buf8 = (u8 *) buf;
10366 /* Separate the parity bits and the data bytes. */
10367 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10368 if ((i == 0) || (i == 8)) {
10372 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10373 parity[k++] = buf8[i] & msk;
10375 } else if (i == 16) {
10379 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10380 parity[k++] = buf8[i] & msk;
10383 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10384 parity[k++] = buf8[i] & msk;
10387 data[j++] = buf8[i];
10391 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10392 u8 hw8 = hweight8(data[i]);
10394 if ((hw8 & 0x1) && parity[i])
10396 else if (!(hw8 & 0x1) && !parity[i])
10403 /* Bootstrap checksum at offset 0x10 */
10404 csum = calc_crc((unsigned char *) buf, 0x10);
10405 if (csum != be32_to_cpu(buf[0x10/4]))
10408 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10409 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10410 if (csum != be32_to_cpu(buf[0xfc/4]))
10420 #define TG3_SERDES_TIMEOUT_SEC 2
10421 #define TG3_COPPER_TIMEOUT_SEC 6
10423 static int tg3_test_link(struct tg3 *tp)
10427 if (!netif_running(tp->dev))
10430 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10431 max = TG3_SERDES_TIMEOUT_SEC;
10433 max = TG3_COPPER_TIMEOUT_SEC;
10435 for (i = 0; i < max; i++) {
10436 if (netif_carrier_ok(tp->dev))
10439 if (msleep_interruptible(1000))
10446 /* Only test the commonly used registers */
10447 static int tg3_test_registers(struct tg3 *tp)
10449 int i, is_5705, is_5750;
10450 u32 offset, read_mask, write_mask, val, save_val, read_val;
10454 #define TG3_FL_5705 0x1
10455 #define TG3_FL_NOT_5705 0x2
10456 #define TG3_FL_NOT_5788 0x4
10457 #define TG3_FL_NOT_5750 0x8
10461 /* MAC Control Registers */
10462 { MAC_MODE, TG3_FL_NOT_5705,
10463 0x00000000, 0x00ef6f8c },
10464 { MAC_MODE, TG3_FL_5705,
10465 0x00000000, 0x01ef6b8c },
10466 { MAC_STATUS, TG3_FL_NOT_5705,
10467 0x03800107, 0x00000000 },
10468 { MAC_STATUS, TG3_FL_5705,
10469 0x03800100, 0x00000000 },
10470 { MAC_ADDR_0_HIGH, 0x0000,
10471 0x00000000, 0x0000ffff },
10472 { MAC_ADDR_0_LOW, 0x0000,
10473 0x00000000, 0xffffffff },
10474 { MAC_RX_MTU_SIZE, 0x0000,
10475 0x00000000, 0x0000ffff },
10476 { MAC_TX_MODE, 0x0000,
10477 0x00000000, 0x00000070 },
10478 { MAC_TX_LENGTHS, 0x0000,
10479 0x00000000, 0x00003fff },
10480 { MAC_RX_MODE, TG3_FL_NOT_5705,
10481 0x00000000, 0x000007fc },
10482 { MAC_RX_MODE, TG3_FL_5705,
10483 0x00000000, 0x000007dc },
10484 { MAC_HASH_REG_0, 0x0000,
10485 0x00000000, 0xffffffff },
10486 { MAC_HASH_REG_1, 0x0000,
10487 0x00000000, 0xffffffff },
10488 { MAC_HASH_REG_2, 0x0000,
10489 0x00000000, 0xffffffff },
10490 { MAC_HASH_REG_3, 0x0000,
10491 0x00000000, 0xffffffff },
10493 /* Receive Data and Receive BD Initiator Control Registers. */
10494 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10495 0x00000000, 0xffffffff },
10496 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10497 0x00000000, 0xffffffff },
10498 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10499 0x00000000, 0x00000003 },
10500 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10501 0x00000000, 0xffffffff },
10502 { RCVDBDI_STD_BD+0, 0x0000,
10503 0x00000000, 0xffffffff },
10504 { RCVDBDI_STD_BD+4, 0x0000,
10505 0x00000000, 0xffffffff },
10506 { RCVDBDI_STD_BD+8, 0x0000,
10507 0x00000000, 0xffff0002 },
10508 { RCVDBDI_STD_BD+0xc, 0x0000,
10509 0x00000000, 0xffffffff },
10511 /* Receive BD Initiator Control Registers. */
10512 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10513 0x00000000, 0xffffffff },
10514 { RCVBDI_STD_THRESH, TG3_FL_5705,
10515 0x00000000, 0x000003ff },
10516 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10517 0x00000000, 0xffffffff },
10519 /* Host Coalescing Control Registers. */
10520 { HOSTCC_MODE, TG3_FL_NOT_5705,
10521 0x00000000, 0x00000004 },
10522 { HOSTCC_MODE, TG3_FL_5705,
10523 0x00000000, 0x000000f6 },
10524 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10525 0x00000000, 0xffffffff },
10526 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10527 0x00000000, 0x000003ff },
10528 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10529 0x00000000, 0xffffffff },
10530 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10531 0x00000000, 0x000003ff },
10532 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10533 0x00000000, 0xffffffff },
10534 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10535 0x00000000, 0x000000ff },
10536 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10537 0x00000000, 0xffffffff },
10538 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10539 0x00000000, 0x000000ff },
10540 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10541 0x00000000, 0xffffffff },
10542 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10543 0x00000000, 0xffffffff },
10544 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10545 0x00000000, 0xffffffff },
10546 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10547 0x00000000, 0x000000ff },
10548 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10549 0x00000000, 0xffffffff },
10550 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10551 0x00000000, 0x000000ff },
10552 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10553 0x00000000, 0xffffffff },
10554 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10555 0x00000000, 0xffffffff },
10556 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10557 0x00000000, 0xffffffff },
10558 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10559 0x00000000, 0xffffffff },
10560 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10561 0x00000000, 0xffffffff },
10562 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10563 0xffffffff, 0x00000000 },
10564 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10565 0xffffffff, 0x00000000 },
10567 /* Buffer Manager Control Registers. */
10568 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10569 0x00000000, 0x007fff80 },
10570 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10571 0x00000000, 0x007fffff },
10572 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10573 0x00000000, 0x0000003f },
10574 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10575 0x00000000, 0x000001ff },
10576 { BUFMGR_MB_HIGH_WATER, 0x0000,
10577 0x00000000, 0x000001ff },
10578 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10579 0xffffffff, 0x00000000 },
10580 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10581 0xffffffff, 0x00000000 },
10583 /* Mailbox Registers */
10584 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10585 0x00000000, 0x000001ff },
10586 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10587 0x00000000, 0x000001ff },
10588 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10589 0x00000000, 0x000007ff },
10590 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10591 0x00000000, 0x000001ff },
10593 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10596 is_5705 = is_5750 = 0;
10597 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10599 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10603 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10604 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10607 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10610 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10611 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10614 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10617 offset = (u32) reg_tbl[i].offset;
10618 read_mask = reg_tbl[i].read_mask;
10619 write_mask = reg_tbl[i].write_mask;
10621 /* Save the original register content */
10622 save_val = tr32(offset);
10624 /* Determine the read-only value. */
10625 read_val = save_val & read_mask;
10627 /* Write zero to the register, then make sure the read-only bits
10628 * are not changed and the read/write bits are all zeros.
10632 val = tr32(offset);
10634 /* Test the read-only and read/write bits. */
10635 if (((val & read_mask) != read_val) || (val & write_mask))
10638 /* Write ones to all the bits defined by RdMask and WrMask, then
10639 * make sure the read-only bits are not changed and the
10640 * read/write bits are all ones.
10642 tw32(offset, read_mask | write_mask);
10644 val = tr32(offset);
10646 /* Test the read-only bits. */
10647 if ((val & read_mask) != read_val)
10650 /* Test the read/write bits. */
10651 if ((val & write_mask) != write_mask)
10654 tw32(offset, save_val);
10660 if (netif_msg_hw(tp))
10661 netdev_err(tp->dev,
10662 "Register test failed at offset %x\n", offset);
10663 tw32(offset, save_val);
10667 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10669 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10673 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10674 for (j = 0; j < len; j += 4) {
10677 tg3_write_mem(tp, offset + j, test_pattern[i]);
10678 tg3_read_mem(tp, offset + j, &val);
10679 if (val != test_pattern[i])
10686 static int tg3_test_memory(struct tg3 *tp)
10688 static struct mem_entry {
10691 } mem_tbl_570x[] = {
10692 { 0x00000000, 0x00b50},
10693 { 0x00002000, 0x1c000},
10694 { 0xffffffff, 0x00000}
10695 }, mem_tbl_5705[] = {
10696 { 0x00000100, 0x0000c},
10697 { 0x00000200, 0x00008},
10698 { 0x00004000, 0x00800},
10699 { 0x00006000, 0x01000},
10700 { 0x00008000, 0x02000},
10701 { 0x00010000, 0x0e000},
10702 { 0xffffffff, 0x00000}
10703 }, mem_tbl_5755[] = {
10704 { 0x00000200, 0x00008},
10705 { 0x00004000, 0x00800},
10706 { 0x00006000, 0x00800},
10707 { 0x00008000, 0x02000},
10708 { 0x00010000, 0x0c000},
10709 { 0xffffffff, 0x00000}
10710 }, mem_tbl_5906[] = {
10711 { 0x00000200, 0x00008},
10712 { 0x00004000, 0x00400},
10713 { 0x00006000, 0x00400},
10714 { 0x00008000, 0x01000},
10715 { 0x00010000, 0x01000},
10716 { 0xffffffff, 0x00000}
10717 }, mem_tbl_5717[] = {
10718 { 0x00000200, 0x00008},
10719 { 0x00010000, 0x0a000},
10720 { 0x00020000, 0x13c00},
10721 { 0xffffffff, 0x00000}
10722 }, mem_tbl_57765[] = {
10723 { 0x00000200, 0x00008},
10724 { 0x00004000, 0x00800},
10725 { 0x00006000, 0x09800},
10726 { 0x00010000, 0x0a000},
10727 { 0xffffffff, 0x00000}
10729 struct mem_entry *mem_tbl;
10733 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10734 mem_tbl = mem_tbl_5717;
10735 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10736 mem_tbl = mem_tbl_57765;
10737 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10738 mem_tbl = mem_tbl_5755;
10739 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10740 mem_tbl = mem_tbl_5906;
10741 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10742 mem_tbl = mem_tbl_5705;
10744 mem_tbl = mem_tbl_570x;
10746 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10747 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10748 mem_tbl[i].len)) != 0)
10755 #define TG3_MAC_LOOPBACK 0
10756 #define TG3_PHY_LOOPBACK 1
10758 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10760 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10761 u32 desc_idx, coal_now;
10762 struct sk_buff *skb, *rx_skb;
10765 int num_pkts, tx_len, rx_len, i, err;
10766 struct tg3_rx_buffer_desc *desc;
10767 struct tg3_napi *tnapi, *rnapi;
10768 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10770 tnapi = &tp->napi[0];
10771 rnapi = &tp->napi[0];
10772 if (tp->irq_cnt > 1) {
10773 rnapi = &tp->napi[1];
10774 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10775 tnapi = &tp->napi[1];
10777 coal_now = tnapi->coal_now | rnapi->coal_now;
10779 if (loopback_mode == TG3_MAC_LOOPBACK) {
10780 /* HW errata - mac loopback fails in some cases on 5780.
10781 * Normal traffic and PHY loopback are not affected by
10784 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10787 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10788 MAC_MODE_PORT_INT_LPBACK;
10789 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10790 mac_mode |= MAC_MODE_LINK_POLARITY;
10791 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10792 mac_mode |= MAC_MODE_PORT_MODE_MII;
10794 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10795 tw32(MAC_MODE, mac_mode);
10796 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10799 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10800 tg3_phy_fet_toggle_apd(tp, false);
10801 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10803 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10805 tg3_phy_toggle_automdix(tp, 0);
10807 tg3_writephy(tp, MII_BMCR, val);
10810 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10811 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10812 tg3_writephy(tp, MII_TG3_FET_PTEST,
10813 MII_TG3_FET_PTEST_FRC_TX_LINK |
10814 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10815 /* The write needs to be flushed for the AC131 */
10816 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10817 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10818 mac_mode |= MAC_MODE_PORT_MODE_MII;
10820 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10822 /* reset to prevent losing 1st rx packet intermittently */
10823 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10824 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10826 tw32_f(MAC_RX_MODE, tp->rx_mode);
10828 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10829 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10830 if (masked_phy_id == TG3_PHY_ID_BCM5401)
10831 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10832 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10833 mac_mode |= MAC_MODE_LINK_POLARITY;
10834 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10835 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10837 tw32(MAC_MODE, mac_mode);
10845 skb = netdev_alloc_skb(tp->dev, tx_len);
10849 tx_data = skb_put(skb, tx_len);
10850 memcpy(tx_data, tp->dev->dev_addr, 6);
10851 memset(tx_data + 6, 0x0, 8);
10853 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10855 for (i = 14; i < tx_len; i++)
10856 tx_data[i] = (u8) (i & 0xff);
10858 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10859 if (pci_dma_mapping_error(tp->pdev, map)) {
10860 dev_kfree_skb(skb);
10864 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10869 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10873 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10878 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10879 tr32_mailbox(tnapi->prodmbox);
10883 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10884 for (i = 0; i < 35; i++) {
10885 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10890 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10891 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10892 if ((tx_idx == tnapi->tx_prod) &&
10893 (rx_idx == (rx_start_idx + num_pkts)))
10897 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10898 dev_kfree_skb(skb);
10900 if (tx_idx != tnapi->tx_prod)
10903 if (rx_idx != rx_start_idx + num_pkts)
10906 desc = &rnapi->rx_rcb[rx_start_idx];
10907 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10908 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10909 if (opaque_key != RXD_OPAQUE_RING_STD)
10912 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10913 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10916 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10917 if (rx_len != tx_len)
10920 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10922 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10923 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10925 for (i = 14; i < tx_len; i++) {
10926 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10931 /* tg3_free_rings will unmap and free the rx_skb */
10936 #define TG3_MAC_LOOPBACK_FAILED 1
10937 #define TG3_PHY_LOOPBACK_FAILED 2
10938 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10939 TG3_PHY_LOOPBACK_FAILED)
10941 static int tg3_test_loopback(struct tg3 *tp)
10946 if (!netif_running(tp->dev))
10947 return TG3_LOOPBACK_FAILED;
10949 err = tg3_reset_hw(tp, 1);
10951 return TG3_LOOPBACK_FAILED;
10953 /* Turn off gphy autopowerdown. */
10954 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10955 tg3_phy_toggle_apd(tp, false);
10957 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10961 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10963 /* Wait for up to 40 microseconds to acquire lock. */
10964 for (i = 0; i < 4; i++) {
10965 status = tr32(TG3_CPMU_MUTEX_GNT);
10966 if (status == CPMU_MUTEX_GNT_DRIVER)
10971 if (status != CPMU_MUTEX_GNT_DRIVER)
10972 return TG3_LOOPBACK_FAILED;
10974 /* Turn off link-based power management. */
10975 cpmuctrl = tr32(TG3_CPMU_CTRL);
10976 tw32(TG3_CPMU_CTRL,
10977 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10978 CPMU_CTRL_LINK_AWARE_MODE));
10981 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10982 err |= TG3_MAC_LOOPBACK_FAILED;
10984 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10985 tw32(TG3_CPMU_CTRL, cpmuctrl);
10987 /* Release the mutex */
10988 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10991 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10992 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10993 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10994 err |= TG3_PHY_LOOPBACK_FAILED;
10997 /* Re-enable gphy autopowerdown. */
10998 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10999 tg3_phy_toggle_apd(tp, true);
11004 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11007 struct tg3 *tp = netdev_priv(dev);
11009 if (tp->link_config.phy_is_low_power)
11010 tg3_set_power_state(tp, PCI_D0);
11012 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11014 if (tg3_test_nvram(tp) != 0) {
11015 etest->flags |= ETH_TEST_FL_FAILED;
11018 if (tg3_test_link(tp) != 0) {
11019 etest->flags |= ETH_TEST_FL_FAILED;
11022 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11023 int err, err2 = 0, irq_sync = 0;
11025 if (netif_running(dev)) {
11027 tg3_netif_stop(tp);
11031 tg3_full_lock(tp, irq_sync);
11033 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11034 err = tg3_nvram_lock(tp);
11035 tg3_halt_cpu(tp, RX_CPU_BASE);
11036 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11037 tg3_halt_cpu(tp, TX_CPU_BASE);
11039 tg3_nvram_unlock(tp);
11041 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
11044 if (tg3_test_registers(tp) != 0) {
11045 etest->flags |= ETH_TEST_FL_FAILED;
11048 if (tg3_test_memory(tp) != 0) {
11049 etest->flags |= ETH_TEST_FL_FAILED;
11052 if ((data[4] = tg3_test_loopback(tp)) != 0)
11053 etest->flags |= ETH_TEST_FL_FAILED;
11055 tg3_full_unlock(tp);
11057 if (tg3_test_interrupt(tp) != 0) {
11058 etest->flags |= ETH_TEST_FL_FAILED;
11062 tg3_full_lock(tp, 0);
11064 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11065 if (netif_running(dev)) {
11066 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11067 err2 = tg3_restart_hw(tp, 1);
11069 tg3_netif_start(tp);
11072 tg3_full_unlock(tp);
11074 if (irq_sync && !err2)
11077 if (tp->link_config.phy_is_low_power)
11078 tg3_set_power_state(tp, PCI_D3hot);
11082 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11084 struct mii_ioctl_data *data = if_mii(ifr);
11085 struct tg3 *tp = netdev_priv(dev);
11088 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11089 struct phy_device *phydev;
11090 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11092 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11093 return phy_mii_ioctl(phydev, data, cmd);
11098 data->phy_id = tp->phy_addr;
11101 case SIOCGMIIREG: {
11104 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11105 break; /* We have no PHY */
11107 if (tp->link_config.phy_is_low_power)
11110 spin_lock_bh(&tp->lock);
11111 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11112 spin_unlock_bh(&tp->lock);
11114 data->val_out = mii_regval;
11120 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11121 break; /* We have no PHY */
11123 if (tp->link_config.phy_is_low_power)
11126 spin_lock_bh(&tp->lock);
11127 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11128 spin_unlock_bh(&tp->lock);
11136 return -EOPNOTSUPP;
11139 #if TG3_VLAN_TAG_USED
11140 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11142 struct tg3 *tp = netdev_priv(dev);
11144 if (!netif_running(dev)) {
11149 tg3_netif_stop(tp);
11151 tg3_full_lock(tp, 0);
11155 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11156 __tg3_set_rx_mode(dev);
11158 tg3_netif_start(tp);
11160 tg3_full_unlock(tp);
11164 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11166 struct tg3 *tp = netdev_priv(dev);
11168 memcpy(ec, &tp->coal, sizeof(*ec));
11172 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11174 struct tg3 *tp = netdev_priv(dev);
11175 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11176 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11178 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11179 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11180 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11181 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11182 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11185 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11186 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11187 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11188 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11189 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11190 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11191 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11192 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11193 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11194 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11197 /* No rx interrupts will be generated if both are zero */
11198 if ((ec->rx_coalesce_usecs == 0) &&
11199 (ec->rx_max_coalesced_frames == 0))
11202 /* No tx interrupts will be generated if both are zero */
11203 if ((ec->tx_coalesce_usecs == 0) &&
11204 (ec->tx_max_coalesced_frames == 0))
11207 /* Only copy relevant parameters, ignore all others. */
11208 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11209 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11210 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11211 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11212 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11213 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11214 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11215 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11216 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11218 if (netif_running(dev)) {
11219 tg3_full_lock(tp, 0);
11220 __tg3_set_coalesce(tp, &tp->coal);
11221 tg3_full_unlock(tp);
11226 static const struct ethtool_ops tg3_ethtool_ops = {
11227 .get_settings = tg3_get_settings,
11228 .set_settings = tg3_set_settings,
11229 .get_drvinfo = tg3_get_drvinfo,
11230 .get_regs_len = tg3_get_regs_len,
11231 .get_regs = tg3_get_regs,
11232 .get_wol = tg3_get_wol,
11233 .set_wol = tg3_set_wol,
11234 .get_msglevel = tg3_get_msglevel,
11235 .set_msglevel = tg3_set_msglevel,
11236 .nway_reset = tg3_nway_reset,
11237 .get_link = ethtool_op_get_link,
11238 .get_eeprom_len = tg3_get_eeprom_len,
11239 .get_eeprom = tg3_get_eeprom,
11240 .set_eeprom = tg3_set_eeprom,
11241 .get_ringparam = tg3_get_ringparam,
11242 .set_ringparam = tg3_set_ringparam,
11243 .get_pauseparam = tg3_get_pauseparam,
11244 .set_pauseparam = tg3_set_pauseparam,
11245 .get_rx_csum = tg3_get_rx_csum,
11246 .set_rx_csum = tg3_set_rx_csum,
11247 .set_tx_csum = tg3_set_tx_csum,
11248 .set_sg = ethtool_op_set_sg,
11249 .set_tso = tg3_set_tso,
11250 .self_test = tg3_self_test,
11251 .get_strings = tg3_get_strings,
11252 .phys_id = tg3_phys_id,
11253 .get_ethtool_stats = tg3_get_ethtool_stats,
11254 .get_coalesce = tg3_get_coalesce,
11255 .set_coalesce = tg3_set_coalesce,
11256 .get_sset_count = tg3_get_sset_count,
11259 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11261 u32 cursize, val, magic;
11263 tp->nvram_size = EEPROM_CHIP_SIZE;
11265 if (tg3_nvram_read(tp, 0, &magic) != 0)
11268 if ((magic != TG3_EEPROM_MAGIC) &&
11269 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11270 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11274 * Size the chip by reading offsets at increasing powers of two.
11275 * When we encounter our validation signature, we know the addressing
11276 * has wrapped around, and thus have our chip size.
11280 while (cursize < tp->nvram_size) {
11281 if (tg3_nvram_read(tp, cursize, &val) != 0)
11290 tp->nvram_size = cursize;
11293 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11297 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11298 tg3_nvram_read(tp, 0, &val) != 0)
11301 /* Selfboot format */
11302 if (val != TG3_EEPROM_MAGIC) {
11303 tg3_get_eeprom_size(tp);
11307 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11309 /* This is confusing. We want to operate on the
11310 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11311 * call will read from NVRAM and byteswap the data
11312 * according to the byteswapping settings for all
11313 * other register accesses. This ensures the data we
11314 * want will always reside in the lower 16-bits.
11315 * However, the data in NVRAM is in LE format, which
11316 * means the data from the NVRAM read will always be
11317 * opposite the endianness of the CPU. The 16-bit
11318 * byteswap then brings the data to CPU endianness.
11320 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11324 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11327 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11331 nvcfg1 = tr32(NVRAM_CFG1);
11332 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11333 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11335 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11336 tw32(NVRAM_CFG1, nvcfg1);
11339 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11340 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11341 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11342 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11343 tp->nvram_jedecnum = JEDEC_ATMEL;
11344 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11345 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11347 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11348 tp->nvram_jedecnum = JEDEC_ATMEL;
11349 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11351 case FLASH_VENDOR_ATMEL_EEPROM:
11352 tp->nvram_jedecnum = JEDEC_ATMEL;
11353 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11354 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11356 case FLASH_VENDOR_ST:
11357 tp->nvram_jedecnum = JEDEC_ST;
11358 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11359 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11361 case FLASH_VENDOR_SAIFUN:
11362 tp->nvram_jedecnum = JEDEC_SAIFUN;
11363 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11365 case FLASH_VENDOR_SST_SMALL:
11366 case FLASH_VENDOR_SST_LARGE:
11367 tp->nvram_jedecnum = JEDEC_SST;
11368 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11372 tp->nvram_jedecnum = JEDEC_ATMEL;
11373 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11374 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11378 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11380 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11381 case FLASH_5752PAGE_SIZE_256:
11382 tp->nvram_pagesize = 256;
11384 case FLASH_5752PAGE_SIZE_512:
11385 tp->nvram_pagesize = 512;
11387 case FLASH_5752PAGE_SIZE_1K:
11388 tp->nvram_pagesize = 1024;
11390 case FLASH_5752PAGE_SIZE_2K:
11391 tp->nvram_pagesize = 2048;
11393 case FLASH_5752PAGE_SIZE_4K:
11394 tp->nvram_pagesize = 4096;
11396 case FLASH_5752PAGE_SIZE_264:
11397 tp->nvram_pagesize = 264;
11399 case FLASH_5752PAGE_SIZE_528:
11400 tp->nvram_pagesize = 528;
11405 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11409 nvcfg1 = tr32(NVRAM_CFG1);
11411 /* NVRAM protection for TPM */
11412 if (nvcfg1 & (1 << 27))
11413 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11415 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11416 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11417 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11418 tp->nvram_jedecnum = JEDEC_ATMEL;
11419 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11421 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11422 tp->nvram_jedecnum = JEDEC_ATMEL;
11423 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11424 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11426 case FLASH_5752VENDOR_ST_M45PE10:
11427 case FLASH_5752VENDOR_ST_M45PE20:
11428 case FLASH_5752VENDOR_ST_M45PE40:
11429 tp->nvram_jedecnum = JEDEC_ST;
11430 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11431 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11435 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11436 tg3_nvram_get_pagesize(tp, nvcfg1);
11438 /* For eeprom, set pagesize to maximum eeprom size */
11439 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11441 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11442 tw32(NVRAM_CFG1, nvcfg1);
11446 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11448 u32 nvcfg1, protect = 0;
11450 nvcfg1 = tr32(NVRAM_CFG1);
11452 /* NVRAM protection for TPM */
11453 if (nvcfg1 & (1 << 27)) {
11454 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11458 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11460 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11461 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11462 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11463 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11464 tp->nvram_jedecnum = JEDEC_ATMEL;
11465 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11466 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11467 tp->nvram_pagesize = 264;
11468 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11469 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11470 tp->nvram_size = (protect ? 0x3e200 :
11471 TG3_NVRAM_SIZE_512KB);
11472 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11473 tp->nvram_size = (protect ? 0x1f200 :
11474 TG3_NVRAM_SIZE_256KB);
11476 tp->nvram_size = (protect ? 0x1f200 :
11477 TG3_NVRAM_SIZE_128KB);
11479 case FLASH_5752VENDOR_ST_M45PE10:
11480 case FLASH_5752VENDOR_ST_M45PE20:
11481 case FLASH_5752VENDOR_ST_M45PE40:
11482 tp->nvram_jedecnum = JEDEC_ST;
11483 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11484 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11485 tp->nvram_pagesize = 256;
11486 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11487 tp->nvram_size = (protect ?
11488 TG3_NVRAM_SIZE_64KB :
11489 TG3_NVRAM_SIZE_128KB);
11490 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11491 tp->nvram_size = (protect ?
11492 TG3_NVRAM_SIZE_64KB :
11493 TG3_NVRAM_SIZE_256KB);
11495 tp->nvram_size = (protect ?
11496 TG3_NVRAM_SIZE_128KB :
11497 TG3_NVRAM_SIZE_512KB);
11502 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11506 nvcfg1 = tr32(NVRAM_CFG1);
11508 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11509 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11510 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11511 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11512 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11513 tp->nvram_jedecnum = JEDEC_ATMEL;
11514 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11515 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11517 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11518 tw32(NVRAM_CFG1, nvcfg1);
11520 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11521 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11522 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11523 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11524 tp->nvram_jedecnum = JEDEC_ATMEL;
11525 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11526 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11527 tp->nvram_pagesize = 264;
11529 case FLASH_5752VENDOR_ST_M45PE10:
11530 case FLASH_5752VENDOR_ST_M45PE20:
11531 case FLASH_5752VENDOR_ST_M45PE40:
11532 tp->nvram_jedecnum = JEDEC_ST;
11533 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11534 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11535 tp->nvram_pagesize = 256;
11540 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11542 u32 nvcfg1, protect = 0;
11544 nvcfg1 = tr32(NVRAM_CFG1);
11546 /* NVRAM protection for TPM */
11547 if (nvcfg1 & (1 << 27)) {
11548 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11552 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11554 case FLASH_5761VENDOR_ATMEL_ADB021D:
11555 case FLASH_5761VENDOR_ATMEL_ADB041D:
11556 case FLASH_5761VENDOR_ATMEL_ADB081D:
11557 case FLASH_5761VENDOR_ATMEL_ADB161D:
11558 case FLASH_5761VENDOR_ATMEL_MDB021D:
11559 case FLASH_5761VENDOR_ATMEL_MDB041D:
11560 case FLASH_5761VENDOR_ATMEL_MDB081D:
11561 case FLASH_5761VENDOR_ATMEL_MDB161D:
11562 tp->nvram_jedecnum = JEDEC_ATMEL;
11563 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11564 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11565 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11566 tp->nvram_pagesize = 256;
11568 case FLASH_5761VENDOR_ST_A_M45PE20:
11569 case FLASH_5761VENDOR_ST_A_M45PE40:
11570 case FLASH_5761VENDOR_ST_A_M45PE80:
11571 case FLASH_5761VENDOR_ST_A_M45PE16:
11572 case FLASH_5761VENDOR_ST_M_M45PE20:
11573 case FLASH_5761VENDOR_ST_M_M45PE40:
11574 case FLASH_5761VENDOR_ST_M_M45PE80:
11575 case FLASH_5761VENDOR_ST_M_M45PE16:
11576 tp->nvram_jedecnum = JEDEC_ST;
11577 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11578 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11579 tp->nvram_pagesize = 256;
11584 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11587 case FLASH_5761VENDOR_ATMEL_ADB161D:
11588 case FLASH_5761VENDOR_ATMEL_MDB161D:
11589 case FLASH_5761VENDOR_ST_A_M45PE16:
11590 case FLASH_5761VENDOR_ST_M_M45PE16:
11591 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11593 case FLASH_5761VENDOR_ATMEL_ADB081D:
11594 case FLASH_5761VENDOR_ATMEL_MDB081D:
11595 case FLASH_5761VENDOR_ST_A_M45PE80:
11596 case FLASH_5761VENDOR_ST_M_M45PE80:
11597 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11599 case FLASH_5761VENDOR_ATMEL_ADB041D:
11600 case FLASH_5761VENDOR_ATMEL_MDB041D:
11601 case FLASH_5761VENDOR_ST_A_M45PE40:
11602 case FLASH_5761VENDOR_ST_M_M45PE40:
11603 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11605 case FLASH_5761VENDOR_ATMEL_ADB021D:
11606 case FLASH_5761VENDOR_ATMEL_MDB021D:
11607 case FLASH_5761VENDOR_ST_A_M45PE20:
11608 case FLASH_5761VENDOR_ST_M_M45PE20:
11609 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11615 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11617 tp->nvram_jedecnum = JEDEC_ATMEL;
11618 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11619 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11622 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11626 nvcfg1 = tr32(NVRAM_CFG1);
11628 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11629 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11630 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11631 tp->nvram_jedecnum = JEDEC_ATMEL;
11632 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11633 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11635 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11636 tw32(NVRAM_CFG1, nvcfg1);
11638 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11639 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11640 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11641 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11642 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11643 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11644 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11645 tp->nvram_jedecnum = JEDEC_ATMEL;
11646 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11647 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11649 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11650 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11651 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11652 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11653 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11655 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11656 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11657 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11659 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11660 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11661 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11665 case FLASH_5752VENDOR_ST_M45PE10:
11666 case FLASH_5752VENDOR_ST_M45PE20:
11667 case FLASH_5752VENDOR_ST_M45PE40:
11668 tp->nvram_jedecnum = JEDEC_ST;
11669 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11670 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11672 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11673 case FLASH_5752VENDOR_ST_M45PE10:
11674 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11676 case FLASH_5752VENDOR_ST_M45PE20:
11677 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11679 case FLASH_5752VENDOR_ST_M45PE40:
11680 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11685 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11689 tg3_nvram_get_pagesize(tp, nvcfg1);
11690 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11691 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11695 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11699 nvcfg1 = tr32(NVRAM_CFG1);
11701 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11702 case FLASH_5717VENDOR_ATMEL_EEPROM:
11703 case FLASH_5717VENDOR_MICRO_EEPROM:
11704 tp->nvram_jedecnum = JEDEC_ATMEL;
11705 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11706 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11708 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11709 tw32(NVRAM_CFG1, nvcfg1);
11711 case FLASH_5717VENDOR_ATMEL_MDB011D:
11712 case FLASH_5717VENDOR_ATMEL_ADB011B:
11713 case FLASH_5717VENDOR_ATMEL_ADB011D:
11714 case FLASH_5717VENDOR_ATMEL_MDB021D:
11715 case FLASH_5717VENDOR_ATMEL_ADB021B:
11716 case FLASH_5717VENDOR_ATMEL_ADB021D:
11717 case FLASH_5717VENDOR_ATMEL_45USPT:
11718 tp->nvram_jedecnum = JEDEC_ATMEL;
11719 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11720 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11722 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11723 case FLASH_5717VENDOR_ATMEL_MDB021D:
11724 case FLASH_5717VENDOR_ATMEL_ADB021B:
11725 case FLASH_5717VENDOR_ATMEL_ADB021D:
11726 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11729 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11733 case FLASH_5717VENDOR_ST_M_M25PE10:
11734 case FLASH_5717VENDOR_ST_A_M25PE10:
11735 case FLASH_5717VENDOR_ST_M_M45PE10:
11736 case FLASH_5717VENDOR_ST_A_M45PE10:
11737 case FLASH_5717VENDOR_ST_M_M25PE20:
11738 case FLASH_5717VENDOR_ST_A_M25PE20:
11739 case FLASH_5717VENDOR_ST_M_M45PE20:
11740 case FLASH_5717VENDOR_ST_A_M45PE20:
11741 case FLASH_5717VENDOR_ST_25USPT:
11742 case FLASH_5717VENDOR_ST_45USPT:
11743 tp->nvram_jedecnum = JEDEC_ST;
11744 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11745 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11747 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11748 case FLASH_5717VENDOR_ST_M_M25PE20:
11749 case FLASH_5717VENDOR_ST_A_M25PE20:
11750 case FLASH_5717VENDOR_ST_M_M45PE20:
11751 case FLASH_5717VENDOR_ST_A_M45PE20:
11752 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11755 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11760 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11764 tg3_nvram_get_pagesize(tp, nvcfg1);
11765 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11766 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11769 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11770 static void __devinit tg3_nvram_init(struct tg3 *tp)
11772 tw32_f(GRC_EEPROM_ADDR,
11773 (EEPROM_ADDR_FSM_RESET |
11774 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11775 EEPROM_ADDR_CLKPERD_SHIFT)));
11779 /* Enable seeprom accesses. */
11780 tw32_f(GRC_LOCAL_CTRL,
11781 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11784 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11785 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11786 tp->tg3_flags |= TG3_FLAG_NVRAM;
11788 if (tg3_nvram_lock(tp)) {
11789 netdev_warn(tp->dev,
11790 "Cannot get nvram lock, %s failed\n",
11794 tg3_enable_nvram_access(tp);
11796 tp->nvram_size = 0;
11798 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11799 tg3_get_5752_nvram_info(tp);
11800 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11801 tg3_get_5755_nvram_info(tp);
11802 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11803 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11804 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11805 tg3_get_5787_nvram_info(tp);
11806 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11807 tg3_get_5761_nvram_info(tp);
11808 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11809 tg3_get_5906_nvram_info(tp);
11810 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11811 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11812 tg3_get_57780_nvram_info(tp);
11813 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11814 tg3_get_5717_nvram_info(tp);
11816 tg3_get_nvram_info(tp);
11818 if (tp->nvram_size == 0)
11819 tg3_get_nvram_size(tp);
11821 tg3_disable_nvram_access(tp);
11822 tg3_nvram_unlock(tp);
11825 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11827 tg3_get_eeprom_size(tp);
11831 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11832 u32 offset, u32 len, u8 *buf)
11837 for (i = 0; i < len; i += 4) {
11843 memcpy(&data, buf + i, 4);
11846 * The SEEPROM interface expects the data to always be opposite
11847 * the native endian format. We accomplish this by reversing
11848 * all the operations that would have been performed on the
11849 * data from a call to tg3_nvram_read_be32().
11851 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11853 val = tr32(GRC_EEPROM_ADDR);
11854 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11856 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11858 tw32(GRC_EEPROM_ADDR, val |
11859 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11860 (addr & EEPROM_ADDR_ADDR_MASK) |
11861 EEPROM_ADDR_START |
11862 EEPROM_ADDR_WRITE);
11864 for (j = 0; j < 1000; j++) {
11865 val = tr32(GRC_EEPROM_ADDR);
11867 if (val & EEPROM_ADDR_COMPLETE)
11871 if (!(val & EEPROM_ADDR_COMPLETE)) {
11880 /* offset and length are dword aligned */
11881 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11885 u32 pagesize = tp->nvram_pagesize;
11886 u32 pagemask = pagesize - 1;
11890 tmp = kmalloc(pagesize, GFP_KERNEL);
11896 u32 phy_addr, page_off, size;
11898 phy_addr = offset & ~pagemask;
11900 for (j = 0; j < pagesize; j += 4) {
11901 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11902 (__be32 *) (tmp + j));
11909 page_off = offset & pagemask;
11916 memcpy(tmp + page_off, buf, size);
11918 offset = offset + (pagesize - page_off);
11920 tg3_enable_nvram_access(tp);
11923 * Before we can erase the flash page, we need
11924 * to issue a special "write enable" command.
11926 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11928 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11931 /* Erase the target page */
11932 tw32(NVRAM_ADDR, phy_addr);
11934 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11935 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11937 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11940 /* Issue another write enable to start the write. */
11941 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11943 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11946 for (j = 0; j < pagesize; j += 4) {
11949 data = *((__be32 *) (tmp + j));
11951 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11953 tw32(NVRAM_ADDR, phy_addr + j);
11955 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11959 nvram_cmd |= NVRAM_CMD_FIRST;
11960 else if (j == (pagesize - 4))
11961 nvram_cmd |= NVRAM_CMD_LAST;
11963 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11970 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11971 tg3_nvram_exec_cmd(tp, nvram_cmd);
11978 /* offset and length are dword aligned */
11979 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11984 for (i = 0; i < len; i += 4, offset += 4) {
11985 u32 page_off, phy_addr, nvram_cmd;
11988 memcpy(&data, buf + i, 4);
11989 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11991 page_off = offset % tp->nvram_pagesize;
11993 phy_addr = tg3_nvram_phys_addr(tp, offset);
11995 tw32(NVRAM_ADDR, phy_addr);
11997 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11999 if (page_off == 0 || i == 0)
12000 nvram_cmd |= NVRAM_CMD_FIRST;
12001 if (page_off == (tp->nvram_pagesize - 4))
12002 nvram_cmd |= NVRAM_CMD_LAST;
12004 if (i == (len - 4))
12005 nvram_cmd |= NVRAM_CMD_LAST;
12007 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12008 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12009 (tp->nvram_jedecnum == JEDEC_ST) &&
12010 (nvram_cmd & NVRAM_CMD_FIRST)) {
12012 if ((ret = tg3_nvram_exec_cmd(tp,
12013 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12018 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12019 /* We always do complete word writes to eeprom. */
12020 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12023 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12029 /* offset and length are dword aligned */
12030 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12034 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12035 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12036 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12040 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12041 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12045 ret = tg3_nvram_lock(tp);
12049 tg3_enable_nvram_access(tp);
12050 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12051 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12052 tw32(NVRAM_WRITE1, 0x406);
12054 grc_mode = tr32(GRC_MODE);
12055 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12057 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12058 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12060 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12063 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12067 grc_mode = tr32(GRC_MODE);
12068 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12070 tg3_disable_nvram_access(tp);
12071 tg3_nvram_unlock(tp);
12074 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12075 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12082 struct subsys_tbl_ent {
12083 u16 subsys_vendor, subsys_devid;
12087 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12088 /* Broadcom boards. */
12089 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12090 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12091 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12092 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12093 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12094 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12095 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12096 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12097 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12098 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12099 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12100 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12101 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12102 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12103 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12104 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12105 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12106 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12107 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12108 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12109 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12110 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12113 { TG3PCI_SUBVENDOR_ID_3COM,
12114 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12115 { TG3PCI_SUBVENDOR_ID_3COM,
12116 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12117 { TG3PCI_SUBVENDOR_ID_3COM,
12118 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12119 { TG3PCI_SUBVENDOR_ID_3COM,
12120 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12121 { TG3PCI_SUBVENDOR_ID_3COM,
12122 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12125 { TG3PCI_SUBVENDOR_ID_DELL,
12126 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12127 { TG3PCI_SUBVENDOR_ID_DELL,
12128 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12129 { TG3PCI_SUBVENDOR_ID_DELL,
12130 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12131 { TG3PCI_SUBVENDOR_ID_DELL,
12132 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12134 /* Compaq boards. */
12135 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12136 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12137 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12138 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12139 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12140 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12141 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12142 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12143 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12144 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12147 { TG3PCI_SUBVENDOR_ID_IBM,
12148 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12151 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12155 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12156 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12157 tp->pdev->subsystem_vendor) &&
12158 (subsys_id_to_phy_id[i].subsys_devid ==
12159 tp->pdev->subsystem_device))
12160 return &subsys_id_to_phy_id[i];
12165 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12170 /* On some early chips the SRAM cannot be accessed in D3hot state,
12171 * so need make sure we're in D0.
12173 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12174 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12175 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12178 /* Make sure register accesses (indirect or otherwise)
12179 * will function correctly.
12181 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12182 tp->misc_host_ctrl);
12184 /* The memory arbiter has to be enabled in order for SRAM accesses
12185 * to succeed. Normally on powerup the tg3 chip firmware will make
12186 * sure it is enabled, but other entities such as system netboot
12187 * code might disable it.
12189 val = tr32(MEMARB_MODE);
12190 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12192 tp->phy_id = TG3_PHY_ID_INVALID;
12193 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12195 /* Assume an onboard device and WOL capable by default. */
12196 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12198 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12199 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12200 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12201 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12203 val = tr32(VCPU_CFGSHDW);
12204 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12205 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12206 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12207 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12208 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12212 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12213 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12214 u32 nic_cfg, led_cfg;
12215 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12216 int eeprom_phy_serdes = 0;
12218 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12219 tp->nic_sram_data_cfg = nic_cfg;
12221 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12222 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12223 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12224 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12225 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12226 (ver > 0) && (ver < 0x100))
12227 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12229 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12230 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12232 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12233 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12234 eeprom_phy_serdes = 1;
12236 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12237 if (nic_phy_id != 0) {
12238 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12239 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12241 eeprom_phy_id = (id1 >> 16) << 10;
12242 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12243 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12247 tp->phy_id = eeprom_phy_id;
12248 if (eeprom_phy_serdes) {
12249 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12250 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12251 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12253 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12256 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12257 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12258 SHASTA_EXT_LED_MODE_MASK);
12260 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12264 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12265 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12268 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12269 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12272 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12273 tp->led_ctrl = LED_CTRL_MODE_MAC;
12275 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12276 * read on some older 5700/5701 bootcode.
12278 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12280 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12282 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12286 case SHASTA_EXT_LED_SHARED:
12287 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12288 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12289 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12290 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12291 LED_CTRL_MODE_PHY_2);
12294 case SHASTA_EXT_LED_MAC:
12295 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12298 case SHASTA_EXT_LED_COMBO:
12299 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12300 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12301 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12302 LED_CTRL_MODE_PHY_2);
12307 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12308 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12309 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12310 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12312 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12313 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12315 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12316 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12317 if ((tp->pdev->subsystem_vendor ==
12318 PCI_VENDOR_ID_ARIMA) &&
12319 (tp->pdev->subsystem_device == 0x205a ||
12320 tp->pdev->subsystem_device == 0x2063))
12321 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12323 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12324 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12327 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12328 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12329 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12330 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12333 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12334 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12335 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12337 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12338 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12339 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12341 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12342 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12343 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12345 if (cfg2 & (1 << 17))
12346 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12348 /* serdes signal pre-emphasis in register 0x590 set by */
12349 /* bootcode if bit 18 is set */
12350 if (cfg2 & (1 << 18))
12351 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12353 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12354 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12355 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12356 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12358 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12361 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12362 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12363 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12366 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12367 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12368 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12369 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12370 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12371 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12374 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12375 device_set_wakeup_enable(&tp->pdev->dev,
12376 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12379 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12384 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12385 tw32(OTP_CTRL, cmd);
12387 /* Wait for up to 1 ms for command to execute. */
12388 for (i = 0; i < 100; i++) {
12389 val = tr32(OTP_STATUS);
12390 if (val & OTP_STATUS_CMD_DONE)
12395 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12398 /* Read the gphy configuration from the OTP region of the chip. The gphy
12399 * configuration is a 32-bit value that straddles the alignment boundary.
12400 * We do two 32-bit reads and then shift and merge the results.
12402 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12404 u32 bhalf_otp, thalf_otp;
12406 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12408 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12411 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12413 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12416 thalf_otp = tr32(OTP_READ_DATA);
12418 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12420 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12423 bhalf_otp = tr32(OTP_READ_DATA);
12425 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12428 static int __devinit tg3_phy_probe(struct tg3 *tp)
12430 u32 hw_phy_id_1, hw_phy_id_2;
12431 u32 hw_phy_id, hw_phy_id_masked;
12434 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12435 return tg3_phy_init(tp);
12437 /* Reading the PHY ID register can conflict with ASF
12438 * firmware access to the PHY hardware.
12441 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12442 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12443 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12445 /* Now read the physical PHY_ID from the chip and verify
12446 * that it is sane. If it doesn't look good, we fall back
12447 * to either the hard-coded table based PHY_ID and failing
12448 * that the value found in the eeprom area.
12450 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12451 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12453 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12454 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12455 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12457 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12460 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12461 tp->phy_id = hw_phy_id;
12462 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12463 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12465 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12467 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12468 /* Do nothing, phy ID already set up in
12469 * tg3_get_eeprom_hw_cfg().
12472 struct subsys_tbl_ent *p;
12474 /* No eeprom signature? Try the hardcoded
12475 * subsys device table.
12477 p = tg3_lookup_by_subsys(tp);
12481 tp->phy_id = p->phy_id;
12483 tp->phy_id == TG3_PHY_ID_BCM8002)
12484 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12488 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12489 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12490 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12491 u32 bmsr, adv_reg, tg3_ctrl, mask;
12493 tg3_readphy(tp, MII_BMSR, &bmsr);
12494 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12495 (bmsr & BMSR_LSTATUS))
12496 goto skip_phy_reset;
12498 err = tg3_phy_reset(tp);
12502 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12503 ADVERTISE_100HALF | ADVERTISE_100FULL |
12504 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12506 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12507 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12508 MII_TG3_CTRL_ADV_1000_FULL);
12509 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12510 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12511 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12512 MII_TG3_CTRL_ENABLE_AS_MASTER);
12515 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12516 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12517 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12518 if (!tg3_copper_is_advertising_all(tp, mask)) {
12519 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12521 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12522 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12524 tg3_writephy(tp, MII_BMCR,
12525 BMCR_ANENABLE | BMCR_ANRESTART);
12527 tg3_phy_set_wirespeed(tp);
12529 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12530 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12531 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12535 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12536 err = tg3_init_5401phy_dsp(tp);
12540 err = tg3_init_5401phy_dsp(tp);
12543 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12544 tp->link_config.advertising =
12545 (ADVERTISED_1000baseT_Half |
12546 ADVERTISED_1000baseT_Full |
12547 ADVERTISED_Autoneg |
12549 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12550 tp->link_config.advertising &=
12551 ~(ADVERTISED_1000baseT_Half |
12552 ADVERTISED_1000baseT_Full);
12557 static void __devinit tg3_read_vpd(struct tg3 *tp)
12559 u8 vpd_data[TG3_NVM_VPD_LEN];
12560 unsigned int block_end, rosize, len;
12564 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12565 tg3_nvram_read(tp, 0x0, &magic))
12566 goto out_not_found;
12568 if (magic == TG3_EEPROM_MAGIC) {
12569 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12572 /* The data is in little-endian format in NVRAM.
12573 * Use the big-endian read routines to preserve
12574 * the byte order as it exists in NVRAM.
12576 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12577 goto out_not_found;
12579 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12583 unsigned int pos = 0;
12585 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12586 cnt = pci_read_vpd(tp->pdev, pos,
12587 TG3_NVM_VPD_LEN - pos,
12589 if (cnt == -ETIMEDOUT || -EINTR)
12592 goto out_not_found;
12594 if (pos != TG3_NVM_VPD_LEN)
12595 goto out_not_found;
12598 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12599 PCI_VPD_LRDT_RO_DATA);
12601 goto out_not_found;
12603 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12604 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12605 i += PCI_VPD_LRDT_TAG_SIZE;
12607 if (block_end > TG3_NVM_VPD_LEN)
12608 goto out_not_found;
12610 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12611 PCI_VPD_RO_KEYWORD_MFR_ID);
12613 len = pci_vpd_info_field_size(&vpd_data[j]);
12615 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12616 if (j + len > block_end || len != 4 ||
12617 memcmp(&vpd_data[j], "1028", 4))
12620 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12621 PCI_VPD_RO_KEYWORD_VENDOR0);
12625 len = pci_vpd_info_field_size(&vpd_data[j]);
12627 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12628 if (j + len > block_end)
12631 memcpy(tp->fw_ver, &vpd_data[j], len);
12632 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12636 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12637 PCI_VPD_RO_KEYWORD_PARTNO);
12639 goto out_not_found;
12641 len = pci_vpd_info_field_size(&vpd_data[i]);
12643 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12644 if (len > TG3_BPN_SIZE ||
12645 (len + i) > TG3_NVM_VPD_LEN)
12646 goto out_not_found;
12648 memcpy(tp->board_part_number, &vpd_data[i], len);
12653 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12654 strcpy(tp->board_part_number, "BCM95906");
12655 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12656 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12657 strcpy(tp->board_part_number, "BCM57780");
12658 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12659 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12660 strcpy(tp->board_part_number, "BCM57760");
12661 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12662 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12663 strcpy(tp->board_part_number, "BCM57790");
12664 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12665 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12666 strcpy(tp->board_part_number, "BCM57788");
12667 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12668 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12669 strcpy(tp->board_part_number, "BCM57761");
12670 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12671 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12672 strcpy(tp->board_part_number, "BCM57765");
12673 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12674 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12675 strcpy(tp->board_part_number, "BCM57781");
12676 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12677 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12678 strcpy(tp->board_part_number, "BCM57785");
12679 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12680 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12681 strcpy(tp->board_part_number, "BCM57791");
12682 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12683 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12684 strcpy(tp->board_part_number, "BCM57795");
12686 strcpy(tp->board_part_number, "none");
12689 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12693 if (tg3_nvram_read(tp, offset, &val) ||
12694 (val & 0xfc000000) != 0x0c000000 ||
12695 tg3_nvram_read(tp, offset + 4, &val) ||
12702 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12704 u32 val, offset, start, ver_offset;
12706 bool newver = false;
12708 if (tg3_nvram_read(tp, 0xc, &offset) ||
12709 tg3_nvram_read(tp, 0x4, &start))
12712 offset = tg3_nvram_logical_addr(tp, offset);
12714 if (tg3_nvram_read(tp, offset, &val))
12717 if ((val & 0xfc000000) == 0x0c000000) {
12718 if (tg3_nvram_read(tp, offset + 4, &val))
12725 dst_off = strlen(tp->fw_ver);
12728 if (TG3_VER_SIZE - dst_off < 16 ||
12729 tg3_nvram_read(tp, offset + 8, &ver_offset))
12732 offset = offset + ver_offset - start;
12733 for (i = 0; i < 16; i += 4) {
12735 if (tg3_nvram_read_be32(tp, offset + i, &v))
12738 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12743 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12746 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12747 TG3_NVM_BCVER_MAJSFT;
12748 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12749 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12750 "v%d.%02d", major, minor);
12754 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12756 u32 val, major, minor;
12758 /* Use native endian representation */
12759 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12762 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12763 TG3_NVM_HWSB_CFG1_MAJSFT;
12764 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12765 TG3_NVM_HWSB_CFG1_MINSFT;
12767 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12770 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12772 u32 offset, major, minor, build;
12774 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12776 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12779 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12780 case TG3_EEPROM_SB_REVISION_0:
12781 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12783 case TG3_EEPROM_SB_REVISION_2:
12784 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12786 case TG3_EEPROM_SB_REVISION_3:
12787 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12789 case TG3_EEPROM_SB_REVISION_4:
12790 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12792 case TG3_EEPROM_SB_REVISION_5:
12793 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12799 if (tg3_nvram_read(tp, offset, &val))
12802 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12803 TG3_EEPROM_SB_EDH_BLD_SHFT;
12804 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12805 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12806 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12808 if (minor > 99 || build > 26)
12811 offset = strlen(tp->fw_ver);
12812 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12813 " v%d.%02d", major, minor);
12816 offset = strlen(tp->fw_ver);
12817 if (offset < TG3_VER_SIZE - 1)
12818 tp->fw_ver[offset] = 'a' + build - 1;
12822 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12824 u32 val, offset, start;
12827 for (offset = TG3_NVM_DIR_START;
12828 offset < TG3_NVM_DIR_END;
12829 offset += TG3_NVM_DIRENT_SIZE) {
12830 if (tg3_nvram_read(tp, offset, &val))
12833 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12837 if (offset == TG3_NVM_DIR_END)
12840 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12841 start = 0x08000000;
12842 else if (tg3_nvram_read(tp, offset - 4, &start))
12845 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12846 !tg3_fw_img_is_valid(tp, offset) ||
12847 tg3_nvram_read(tp, offset + 8, &val))
12850 offset += val - start;
12852 vlen = strlen(tp->fw_ver);
12854 tp->fw_ver[vlen++] = ',';
12855 tp->fw_ver[vlen++] = ' ';
12857 for (i = 0; i < 4; i++) {
12859 if (tg3_nvram_read_be32(tp, offset, &v))
12862 offset += sizeof(v);
12864 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12865 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12869 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12874 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12879 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12880 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12883 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12884 if (apedata != APE_SEG_SIG_MAGIC)
12887 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12888 if (!(apedata & APE_FW_STATUS_READY))
12891 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12893 vlen = strlen(tp->fw_ver);
12895 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12896 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12897 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12898 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12899 (apedata & APE_FW_VERSION_BLDMSK));
12902 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12905 bool vpd_vers = false;
12907 if (tp->fw_ver[0] != 0)
12910 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12911 strcat(tp->fw_ver, "sb");
12915 if (tg3_nvram_read(tp, 0, &val))
12918 if (val == TG3_EEPROM_MAGIC)
12919 tg3_read_bc_ver(tp);
12920 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12921 tg3_read_sb_ver(tp, val);
12922 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12923 tg3_read_hwsb_ver(tp);
12927 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12928 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12931 tg3_read_mgmtfw_ver(tp);
12934 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12937 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12939 static int __devinit tg3_get_invariants(struct tg3 *tp)
12941 static struct pci_device_id write_reorder_chipsets[] = {
12942 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12943 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12944 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12945 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12946 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12947 PCI_DEVICE_ID_VIA_8385_0) },
12951 u32 pci_state_reg, grc_misc_cfg;
12956 /* Force memory write invalidate off. If we leave it on,
12957 * then on 5700_BX chips we have to enable a workaround.
12958 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12959 * to match the cacheline size. The Broadcom driver have this
12960 * workaround but turns MWI off all the times so never uses
12961 * it. This seems to suggest that the workaround is insufficient.
12963 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12964 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12965 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12967 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12968 * has the register indirect write enable bit set before
12969 * we try to access any of the MMIO registers. It is also
12970 * critical that the PCI-X hw workaround situation is decided
12971 * before that as well.
12973 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12976 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12977 MISC_HOST_CTRL_CHIPREV_SHIFT);
12978 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12979 u32 prod_id_asic_rev;
12981 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12982 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12983 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12984 pci_read_config_dword(tp->pdev,
12985 TG3PCI_GEN2_PRODID_ASICREV,
12986 &prod_id_asic_rev);
12987 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12988 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12989 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12990 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12991 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12992 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12993 pci_read_config_dword(tp->pdev,
12994 TG3PCI_GEN15_PRODID_ASICREV,
12995 &prod_id_asic_rev);
12997 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12998 &prod_id_asic_rev);
13000 tp->pci_chip_rev_id = prod_id_asic_rev;
13003 /* Wrong chip ID in 5752 A0. This code can be removed later
13004 * as A0 is not in production.
13006 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13007 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13009 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13010 * we need to disable memory and use config. cycles
13011 * only to access all registers. The 5702/03 chips
13012 * can mistakenly decode the special cycles from the
13013 * ICH chipsets as memory write cycles, causing corruption
13014 * of register and memory space. Only certain ICH bridges
13015 * will drive special cycles with non-zero data during the
13016 * address phase which can fall within the 5703's address
13017 * range. This is not an ICH bug as the PCI spec allows
13018 * non-zero address during special cycles. However, only
13019 * these ICH bridges are known to drive non-zero addresses
13020 * during special cycles.
13022 * Since special cycles do not cross PCI bridges, we only
13023 * enable this workaround if the 5703 is on the secondary
13024 * bus of these ICH bridges.
13026 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13027 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13028 static struct tg3_dev_id {
13032 } ich_chipsets[] = {
13033 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13035 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13037 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13039 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13043 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13044 struct pci_dev *bridge = NULL;
13046 while (pci_id->vendor != 0) {
13047 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13053 if (pci_id->rev != PCI_ANY_ID) {
13054 if (bridge->revision > pci_id->rev)
13057 if (bridge->subordinate &&
13058 (bridge->subordinate->number ==
13059 tp->pdev->bus->number)) {
13061 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13062 pci_dev_put(bridge);
13068 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13069 static struct tg3_dev_id {
13072 } bridge_chipsets[] = {
13073 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13074 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13077 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13078 struct pci_dev *bridge = NULL;
13080 while (pci_id->vendor != 0) {
13081 bridge = pci_get_device(pci_id->vendor,
13088 if (bridge->subordinate &&
13089 (bridge->subordinate->number <=
13090 tp->pdev->bus->number) &&
13091 (bridge->subordinate->subordinate >=
13092 tp->pdev->bus->number)) {
13093 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13094 pci_dev_put(bridge);
13100 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13101 * DMA addresses > 40-bit. This bridge may have other additional
13102 * 57xx devices behind it in some 4-port NIC designs for example.
13103 * Any tg3 device found behind the bridge will also need the 40-bit
13106 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13107 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13108 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13109 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13110 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13112 struct pci_dev *bridge = NULL;
13115 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13116 PCI_DEVICE_ID_SERVERWORKS_EPB,
13118 if (bridge && bridge->subordinate &&
13119 (bridge->subordinate->number <=
13120 tp->pdev->bus->number) &&
13121 (bridge->subordinate->subordinate >=
13122 tp->pdev->bus->number)) {
13123 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13124 pci_dev_put(bridge);
13130 /* Initialize misc host control in PCI block. */
13131 tp->misc_host_ctrl |= (misc_ctrl_reg &
13132 MISC_HOST_CTRL_CHIPREV);
13133 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13134 tp->misc_host_ctrl);
13136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13137 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13138 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13139 tp->pdev_peer = tg3_find_peer(tp);
13141 /* Intentionally exclude ASIC_REV_5906 */
13142 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13143 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13144 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13145 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13146 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13147 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13148 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13149 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13150 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13152 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13153 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13154 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13155 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13156 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13157 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13159 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13160 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13161 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13163 /* 5700 B0 chips do not support checksumming correctly due
13164 * to hardware bugs.
13166 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13167 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13169 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13170 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13171 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13172 tp->dev->features |= NETIF_F_IPV6_CSUM;
13175 /* Determine TSO capabilities */
13176 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13177 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13178 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13179 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13180 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13181 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13182 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13183 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13184 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13185 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13186 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13187 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13188 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13189 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13190 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13192 tp->fw_needed = FIRMWARE_TG3TSO5;
13194 tp->fw_needed = FIRMWARE_TG3TSO;
13199 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13200 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13201 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13202 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13203 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13204 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13205 tp->pdev_peer == tp->pdev))
13206 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13208 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13209 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13210 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13213 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13214 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13215 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13216 tp->irq_max = TG3_IRQ_MAX_VECS;
13220 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13221 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13222 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13223 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13224 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13225 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13228 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13229 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13230 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13232 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13233 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13234 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13235 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13237 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13240 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13241 if (tp->pcie_cap != 0) {
13244 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13246 pcie_set_readrq(tp->pdev, 4096);
13248 pci_read_config_word(tp->pdev,
13249 tp->pcie_cap + PCI_EXP_LNKCTL,
13251 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13252 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13253 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13254 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13255 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13256 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13257 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13258 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13259 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13260 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13262 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13263 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13264 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13265 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13266 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13267 if (!tp->pcix_cap) {
13268 dev_err(&tp->pdev->dev,
13269 "Cannot find PCI-X capability, aborting\n");
13273 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13274 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13277 /* If we have an AMD 762 or VIA K8T800 chipset, write
13278 * reordering to the mailbox registers done by the host
13279 * controller can cause major troubles. We read back from
13280 * every mailbox register write to force the writes to be
13281 * posted to the chip in order.
13283 if (pci_dev_present(write_reorder_chipsets) &&
13284 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13285 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13287 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13288 &tp->pci_cacheline_sz);
13289 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13290 &tp->pci_lat_timer);
13291 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13292 tp->pci_lat_timer < 64) {
13293 tp->pci_lat_timer = 64;
13294 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13295 tp->pci_lat_timer);
13298 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13299 /* 5700 BX chips need to have their TX producer index
13300 * mailboxes written twice to workaround a bug.
13302 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13304 /* If we are in PCI-X mode, enable register write workaround.
13306 * The workaround is to use indirect register accesses
13307 * for all chip writes not to mailbox registers.
13309 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13312 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13314 /* The chip can have it's power management PCI config
13315 * space registers clobbered due to this bug.
13316 * So explicitly force the chip into D0 here.
13318 pci_read_config_dword(tp->pdev,
13319 tp->pm_cap + PCI_PM_CTRL,
13321 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13322 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13323 pci_write_config_dword(tp->pdev,
13324 tp->pm_cap + PCI_PM_CTRL,
13327 /* Also, force SERR#/PERR# in PCI command. */
13328 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13329 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13330 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13334 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13335 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13336 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13337 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13339 /* Chip-specific fixup from Broadcom driver */
13340 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13341 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13342 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13343 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13346 /* Default fast path register access methods */
13347 tp->read32 = tg3_read32;
13348 tp->write32 = tg3_write32;
13349 tp->read32_mbox = tg3_read32;
13350 tp->write32_mbox = tg3_write32;
13351 tp->write32_tx_mbox = tg3_write32;
13352 tp->write32_rx_mbox = tg3_write32;
13354 /* Various workaround register access methods */
13355 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13356 tp->write32 = tg3_write_indirect_reg32;
13357 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13358 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13359 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13361 * Back to back register writes can cause problems on these
13362 * chips, the workaround is to read back all reg writes
13363 * except those to mailbox regs.
13365 * See tg3_write_indirect_reg32().
13367 tp->write32 = tg3_write_flush_reg32;
13370 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13371 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13372 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13373 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13374 tp->write32_rx_mbox = tg3_write_flush_reg32;
13377 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13378 tp->read32 = tg3_read_indirect_reg32;
13379 tp->write32 = tg3_write_indirect_reg32;
13380 tp->read32_mbox = tg3_read_indirect_mbox;
13381 tp->write32_mbox = tg3_write_indirect_mbox;
13382 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13383 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13388 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13389 pci_cmd &= ~PCI_COMMAND_MEMORY;
13390 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13392 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13393 tp->read32_mbox = tg3_read32_mbox_5906;
13394 tp->write32_mbox = tg3_write32_mbox_5906;
13395 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13396 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13399 if (tp->write32 == tg3_write_indirect_reg32 ||
13400 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13401 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13402 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13403 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13405 /* Get eeprom hw config before calling tg3_set_power_state().
13406 * In particular, the TG3_FLG2_IS_NIC flag must be
13407 * determined before calling tg3_set_power_state() so that
13408 * we know whether or not to switch out of Vaux power.
13409 * When the flag is set, it means that GPIO1 is used for eeprom
13410 * write protect and also implies that it is a LOM where GPIOs
13411 * are not used to switch power.
13413 tg3_get_eeprom_hw_cfg(tp);
13415 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13416 /* Allow reads and writes to the
13417 * APE register and memory space.
13419 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13420 PCISTATE_ALLOW_APE_SHMEM_WR;
13421 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13425 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13426 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13427 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13428 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13429 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13430 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13431 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13433 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13434 * GPIO1 driven high will bring 5700's external PHY out of reset.
13435 * It is also used as eeprom write protect on LOMs.
13437 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13438 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13439 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13440 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13441 GRC_LCLCTRL_GPIO_OUTPUT1);
13442 /* Unused GPIO3 must be driven as output on 5752 because there
13443 * are no pull-up resistors on unused GPIO pins.
13445 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13446 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13448 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13449 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13450 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13451 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13453 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13454 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13455 /* Turn off the debug UART. */
13456 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13457 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13458 /* Keep VMain power. */
13459 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13460 GRC_LCLCTRL_GPIO_OUTPUT0;
13463 /* Force the chip into D0. */
13464 err = tg3_set_power_state(tp, PCI_D0);
13466 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13470 /* Derive initial jumbo mode from MTU assigned in
13471 * ether_setup() via the alloc_etherdev() call
13473 if (tp->dev->mtu > ETH_DATA_LEN &&
13474 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13475 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13477 /* Determine WakeOnLan speed to use. */
13478 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13479 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13480 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13481 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13482 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13484 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13487 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13488 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13490 /* A few boards don't want Ethernet@WireSpeed phy feature */
13491 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13492 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13493 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13494 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13495 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13496 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13497 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13499 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13500 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13501 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13502 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13503 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13505 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13506 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13507 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13508 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13509 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13510 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13511 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13512 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13513 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13514 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13515 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13516 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13517 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13518 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13519 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13521 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13524 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13525 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13526 tp->phy_otp = tg3_read_otp_phycfg(tp);
13527 if (tp->phy_otp == 0)
13528 tp->phy_otp = TG3_OTP_DEFAULT;
13531 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13532 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13534 tp->mi_mode = MAC_MI_MODE_BASE;
13536 tp->coalesce_mode = 0;
13537 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13538 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13539 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13541 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13542 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13543 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13545 err = tg3_mdio_init(tp);
13549 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13550 (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13551 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13554 /* Initialize data/descriptor byte/word swapping. */
13555 val = tr32(GRC_MODE);
13556 val &= GRC_MODE_HOST_STACKUP;
13557 tw32(GRC_MODE, val | tp->grc_mode);
13559 tg3_switch_clocks(tp);
13561 /* Clear this out for sanity. */
13562 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13564 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13566 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13567 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13568 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13570 if (chiprevid == CHIPREV_ID_5701_A0 ||
13571 chiprevid == CHIPREV_ID_5701_B0 ||
13572 chiprevid == CHIPREV_ID_5701_B2 ||
13573 chiprevid == CHIPREV_ID_5701_B5) {
13574 void __iomem *sram_base;
13576 /* Write some dummy words into the SRAM status block
13577 * area, see if it reads back correctly. If the return
13578 * value is bad, force enable the PCIX workaround.
13580 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13582 writel(0x00000000, sram_base);
13583 writel(0x00000000, sram_base + 4);
13584 writel(0xffffffff, sram_base + 4);
13585 if (readl(sram_base) != 0x00000000)
13586 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13591 tg3_nvram_init(tp);
13593 grc_misc_cfg = tr32(GRC_MISC_CFG);
13594 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13596 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13597 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13598 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13599 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13601 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13602 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13603 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13604 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13605 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13606 HOSTCC_MODE_CLRTICK_TXBD);
13608 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13609 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13610 tp->misc_host_ctrl);
13613 /* Preserve the APE MAC_MODE bits */
13614 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13615 tp->mac_mode = tr32(MAC_MODE) |
13616 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13618 tp->mac_mode = TG3_DEF_MAC_MODE;
13620 /* these are limited to 10/100 only */
13621 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13622 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13623 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13624 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13625 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13626 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13627 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13628 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13629 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13630 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13631 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13632 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13633 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13634 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13635 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13636 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13638 err = tg3_phy_probe(tp);
13640 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13641 /* ... but do not return immediately ... */
13646 tg3_read_fw_ver(tp);
13648 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13649 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13651 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13652 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13654 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13657 /* 5700 {AX,BX} chips have a broken status block link
13658 * change bit implementation, so we must use the
13659 * status register in those cases.
13661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13662 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13664 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13666 /* The led_ctrl is set during tg3_phy_probe, here we might
13667 * have to force the link status polling mechanism based
13668 * upon subsystem IDs.
13670 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13671 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13672 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13673 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13674 TG3_FLAG_USE_LINKCHG_REG);
13677 /* For all SERDES we poll the MAC status register. */
13678 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13679 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13681 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13683 tp->rx_offset = NET_IP_ALIGN;
13684 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13685 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13688 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13690 /* Increment the rx prod index on the rx std ring by at most
13691 * 8 for these chips to workaround hw errata.
13693 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13694 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13695 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13696 tp->rx_std_max_post = 8;
13698 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13699 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13700 PCIE_PWR_MGMT_L1_THRESH_MSK;
13705 #ifdef CONFIG_SPARC
13706 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13708 struct net_device *dev = tp->dev;
13709 struct pci_dev *pdev = tp->pdev;
13710 struct device_node *dp = pci_device_to_OF_node(pdev);
13711 const unsigned char *addr;
13714 addr = of_get_property(dp, "local-mac-address", &len);
13715 if (addr && len == 6) {
13716 memcpy(dev->dev_addr, addr, 6);
13717 memcpy(dev->perm_addr, dev->dev_addr, 6);
13723 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13725 struct net_device *dev = tp->dev;
13727 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13728 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13733 static int __devinit tg3_get_device_address(struct tg3 *tp)
13735 struct net_device *dev = tp->dev;
13736 u32 hi, lo, mac_offset;
13739 #ifdef CONFIG_SPARC
13740 if (!tg3_get_macaddr_sparc(tp))
13745 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13746 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13747 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13749 if (tg3_nvram_lock(tp))
13750 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13752 tg3_nvram_unlock(tp);
13753 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13754 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13756 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13759 /* First try to get it from MAC address mailbox. */
13760 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13761 if ((hi >> 16) == 0x484b) {
13762 dev->dev_addr[0] = (hi >> 8) & 0xff;
13763 dev->dev_addr[1] = (hi >> 0) & 0xff;
13765 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13766 dev->dev_addr[2] = (lo >> 24) & 0xff;
13767 dev->dev_addr[3] = (lo >> 16) & 0xff;
13768 dev->dev_addr[4] = (lo >> 8) & 0xff;
13769 dev->dev_addr[5] = (lo >> 0) & 0xff;
13771 /* Some old bootcode may report a 0 MAC address in SRAM */
13772 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13775 /* Next, try NVRAM. */
13776 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13777 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13778 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13779 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13780 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13782 /* Finally just fetch it out of the MAC control regs. */
13784 hi = tr32(MAC_ADDR_0_HIGH);
13785 lo = tr32(MAC_ADDR_0_LOW);
13787 dev->dev_addr[5] = lo & 0xff;
13788 dev->dev_addr[4] = (lo >> 8) & 0xff;
13789 dev->dev_addr[3] = (lo >> 16) & 0xff;
13790 dev->dev_addr[2] = (lo >> 24) & 0xff;
13791 dev->dev_addr[1] = hi & 0xff;
13792 dev->dev_addr[0] = (hi >> 8) & 0xff;
13796 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13797 #ifdef CONFIG_SPARC
13798 if (!tg3_get_default_macaddr_sparc(tp))
13803 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13807 #define BOUNDARY_SINGLE_CACHELINE 1
13808 #define BOUNDARY_MULTI_CACHELINE 2
13810 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13812 int cacheline_size;
13816 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13818 cacheline_size = 1024;
13820 cacheline_size = (int) byte * 4;
13822 /* On 5703 and later chips, the boundary bits have no
13825 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13826 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13827 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13830 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13831 goal = BOUNDARY_MULTI_CACHELINE;
13833 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13834 goal = BOUNDARY_SINGLE_CACHELINE;
13840 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13841 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13842 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13849 /* PCI controllers on most RISC systems tend to disconnect
13850 * when a device tries to burst across a cache-line boundary.
13851 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13853 * Unfortunately, for PCI-E there are only limited
13854 * write-side controls for this, and thus for reads
13855 * we will still get the disconnects. We'll also waste
13856 * these PCI cycles for both read and write for chips
13857 * other than 5700 and 5701 which do not implement the
13860 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13861 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13862 switch (cacheline_size) {
13867 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13868 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13869 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13871 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13872 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13877 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13878 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13882 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13883 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13886 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13887 switch (cacheline_size) {
13891 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13892 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13893 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13899 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13900 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13904 switch (cacheline_size) {
13906 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13907 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13908 DMA_RWCTRL_WRITE_BNDRY_16);
13913 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13914 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13915 DMA_RWCTRL_WRITE_BNDRY_32);
13920 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13921 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13922 DMA_RWCTRL_WRITE_BNDRY_64);
13927 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13928 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13929 DMA_RWCTRL_WRITE_BNDRY_128);
13934 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13935 DMA_RWCTRL_WRITE_BNDRY_256);
13938 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13939 DMA_RWCTRL_WRITE_BNDRY_512);
13943 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13944 DMA_RWCTRL_WRITE_BNDRY_1024);
13953 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13955 struct tg3_internal_buffer_desc test_desc;
13956 u32 sram_dma_descs;
13959 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13961 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13962 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13963 tw32(RDMAC_STATUS, 0);
13964 tw32(WDMAC_STATUS, 0);
13966 tw32(BUFMGR_MODE, 0);
13967 tw32(FTQ_RESET, 0);
13969 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13970 test_desc.addr_lo = buf_dma & 0xffffffff;
13971 test_desc.nic_mbuf = 0x00002100;
13972 test_desc.len = size;
13975 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13976 * the *second* time the tg3 driver was getting loaded after an
13979 * Broadcom tells me:
13980 * ...the DMA engine is connected to the GRC block and a DMA
13981 * reset may affect the GRC block in some unpredictable way...
13982 * The behavior of resets to individual blocks has not been tested.
13984 * Broadcom noted the GRC reset will also reset all sub-components.
13987 test_desc.cqid_sqid = (13 << 8) | 2;
13989 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13992 test_desc.cqid_sqid = (16 << 8) | 7;
13994 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13997 test_desc.flags = 0x00000005;
13999 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14002 val = *(((u32 *)&test_desc) + i);
14003 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14004 sram_dma_descs + (i * sizeof(u32)));
14005 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14007 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14010 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14012 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14015 for (i = 0; i < 40; i++) {
14019 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14021 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14022 if ((val & 0xffff) == sram_dma_descs) {
14033 #define TEST_BUFFER_SIZE 0x2000
14035 static int __devinit tg3_test_dma(struct tg3 *tp)
14037 dma_addr_t buf_dma;
14038 u32 *buf, saved_dma_rwctrl;
14041 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
14047 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14048 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14050 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14052 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14053 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
14056 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14057 /* DMA read watermark not used on PCIE */
14058 tp->dma_rwctrl |= 0x00180000;
14059 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14061 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14062 tp->dma_rwctrl |= 0x003f0000;
14064 tp->dma_rwctrl |= 0x003f000f;
14066 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14067 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14068 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14069 u32 read_water = 0x7;
14071 /* If the 5704 is behind the EPB bridge, we can
14072 * do the less restrictive ONE_DMA workaround for
14073 * better performance.
14075 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14076 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14077 tp->dma_rwctrl |= 0x8000;
14078 else if (ccval == 0x6 || ccval == 0x7)
14079 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14081 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14083 /* Set bit 23 to enable PCIX hw bug fix */
14085 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14086 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14088 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14089 /* 5780 always in PCIX mode */
14090 tp->dma_rwctrl |= 0x00144000;
14091 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14092 /* 5714 always in PCIX mode */
14093 tp->dma_rwctrl |= 0x00148000;
14095 tp->dma_rwctrl |= 0x001b000f;
14099 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14100 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14101 tp->dma_rwctrl &= 0xfffffff0;
14103 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14104 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14105 /* Remove this if it causes problems for some boards. */
14106 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14108 /* On 5700/5701 chips, we need to set this bit.
14109 * Otherwise the chip will issue cacheline transactions
14110 * to streamable DMA memory with not all the byte
14111 * enables turned on. This is an error on several
14112 * RISC PCI controllers, in particular sparc64.
14114 * On 5703/5704 chips, this bit has been reassigned
14115 * a different meaning. In particular, it is used
14116 * on those chips to enable a PCI-X workaround.
14118 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14121 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14124 /* Unneeded, already done by tg3_get_invariants. */
14125 tg3_switch_clocks(tp);
14128 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14129 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14132 /* It is best to perform DMA test with maximum write burst size
14133 * to expose the 5700/5701 write DMA bug.
14135 saved_dma_rwctrl = tp->dma_rwctrl;
14136 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14137 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14142 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14145 /* Send the buffer to the chip. */
14146 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14148 dev_err(&tp->pdev->dev,
14149 "%s: Buffer write failed. err = %d\n",
14155 /* validate data reached card RAM correctly. */
14156 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14158 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14159 if (le32_to_cpu(val) != p[i]) {
14160 dev_err(&tp->pdev->dev,
14161 "%s: Buffer corrupted on device! "
14162 "(%d != %d)\n", __func__, val, i);
14163 /* ret = -ENODEV here? */
14168 /* Now read it back. */
14169 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14171 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14172 "err = %d\n", __func__, ret);
14177 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14181 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14182 DMA_RWCTRL_WRITE_BNDRY_16) {
14183 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14184 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14185 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14188 dev_err(&tp->pdev->dev,
14189 "%s: Buffer corrupted on read back! "
14190 "(%d != %d)\n", __func__, p[i], i);
14196 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14202 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14203 DMA_RWCTRL_WRITE_BNDRY_16) {
14204 static struct pci_device_id dma_wait_state_chipsets[] = {
14205 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14206 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14210 /* DMA test passed without adjusting DMA boundary,
14211 * now look for chipsets that are known to expose the
14212 * DMA bug without failing the test.
14214 if (pci_dev_present(dma_wait_state_chipsets)) {
14215 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14216 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14218 /* Safe to use the calculated DMA boundary. */
14219 tp->dma_rwctrl = saved_dma_rwctrl;
14222 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14226 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14231 static void __devinit tg3_init_link_config(struct tg3 *tp)
14233 tp->link_config.advertising =
14234 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14235 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14236 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14237 ADVERTISED_Autoneg | ADVERTISED_MII);
14238 tp->link_config.speed = SPEED_INVALID;
14239 tp->link_config.duplex = DUPLEX_INVALID;
14240 tp->link_config.autoneg = AUTONEG_ENABLE;
14241 tp->link_config.active_speed = SPEED_INVALID;
14242 tp->link_config.active_duplex = DUPLEX_INVALID;
14243 tp->link_config.phy_is_low_power = 0;
14244 tp->link_config.orig_speed = SPEED_INVALID;
14245 tp->link_config.orig_duplex = DUPLEX_INVALID;
14246 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14249 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14251 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14252 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14253 tp->bufmgr_config.mbuf_read_dma_low_water =
14254 DEFAULT_MB_RDMA_LOW_WATER_5705;
14255 tp->bufmgr_config.mbuf_mac_rx_low_water =
14256 DEFAULT_MB_MACRX_LOW_WATER_57765;
14257 tp->bufmgr_config.mbuf_high_water =
14258 DEFAULT_MB_HIGH_WATER_57765;
14260 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14261 DEFAULT_MB_RDMA_LOW_WATER_5705;
14262 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14263 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14264 tp->bufmgr_config.mbuf_high_water_jumbo =
14265 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14266 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14267 tp->bufmgr_config.mbuf_read_dma_low_water =
14268 DEFAULT_MB_RDMA_LOW_WATER_5705;
14269 tp->bufmgr_config.mbuf_mac_rx_low_water =
14270 DEFAULT_MB_MACRX_LOW_WATER_5705;
14271 tp->bufmgr_config.mbuf_high_water =
14272 DEFAULT_MB_HIGH_WATER_5705;
14273 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14274 tp->bufmgr_config.mbuf_mac_rx_low_water =
14275 DEFAULT_MB_MACRX_LOW_WATER_5906;
14276 tp->bufmgr_config.mbuf_high_water =
14277 DEFAULT_MB_HIGH_WATER_5906;
14280 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14281 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14282 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14283 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14284 tp->bufmgr_config.mbuf_high_water_jumbo =
14285 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14287 tp->bufmgr_config.mbuf_read_dma_low_water =
14288 DEFAULT_MB_RDMA_LOW_WATER;
14289 tp->bufmgr_config.mbuf_mac_rx_low_water =
14290 DEFAULT_MB_MACRX_LOW_WATER;
14291 tp->bufmgr_config.mbuf_high_water =
14292 DEFAULT_MB_HIGH_WATER;
14294 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14295 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14296 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14297 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14298 tp->bufmgr_config.mbuf_high_water_jumbo =
14299 DEFAULT_MB_HIGH_WATER_JUMBO;
14302 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14303 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14306 static char * __devinit tg3_phy_string(struct tg3 *tp)
14308 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14309 case TG3_PHY_ID_BCM5400: return "5400";
14310 case TG3_PHY_ID_BCM5401: return "5401";
14311 case TG3_PHY_ID_BCM5411: return "5411";
14312 case TG3_PHY_ID_BCM5701: return "5701";
14313 case TG3_PHY_ID_BCM5703: return "5703";
14314 case TG3_PHY_ID_BCM5704: return "5704";
14315 case TG3_PHY_ID_BCM5705: return "5705";
14316 case TG3_PHY_ID_BCM5750: return "5750";
14317 case TG3_PHY_ID_BCM5752: return "5752";
14318 case TG3_PHY_ID_BCM5714: return "5714";
14319 case TG3_PHY_ID_BCM5780: return "5780";
14320 case TG3_PHY_ID_BCM5755: return "5755";
14321 case TG3_PHY_ID_BCM5787: return "5787";
14322 case TG3_PHY_ID_BCM5784: return "5784";
14323 case TG3_PHY_ID_BCM5756: return "5722/5756";
14324 case TG3_PHY_ID_BCM5906: return "5906";
14325 case TG3_PHY_ID_BCM5761: return "5761";
14326 case TG3_PHY_ID_BCM5718C: return "5718C";
14327 case TG3_PHY_ID_BCM5718S: return "5718S";
14328 case TG3_PHY_ID_BCM57765: return "57765";
14329 case TG3_PHY_ID_BCM8002: return "8002/serdes";
14330 case 0: return "serdes";
14331 default: return "unknown";
14335 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14337 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14338 strcpy(str, "PCI Express");
14340 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14341 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14343 strcpy(str, "PCIX:");
14345 if ((clock_ctrl == 7) ||
14346 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14347 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14348 strcat(str, "133MHz");
14349 else if (clock_ctrl == 0)
14350 strcat(str, "33MHz");
14351 else if (clock_ctrl == 2)
14352 strcat(str, "50MHz");
14353 else if (clock_ctrl == 4)
14354 strcat(str, "66MHz");
14355 else if (clock_ctrl == 6)
14356 strcat(str, "100MHz");
14358 strcpy(str, "PCI:");
14359 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14360 strcat(str, "66MHz");
14362 strcat(str, "33MHz");
14364 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14365 strcat(str, ":32-bit");
14367 strcat(str, ":64-bit");
14371 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14373 struct pci_dev *peer;
14374 unsigned int func, devnr = tp->pdev->devfn & ~7;
14376 for (func = 0; func < 8; func++) {
14377 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14378 if (peer && peer != tp->pdev)
14382 /* 5704 can be configured in single-port mode, set peer to
14383 * tp->pdev in that case.
14391 * We don't need to keep the refcount elevated; there's no way
14392 * to remove one half of this device without removing the other
14399 static void __devinit tg3_init_coal(struct tg3 *tp)
14401 struct ethtool_coalesce *ec = &tp->coal;
14403 memset(ec, 0, sizeof(*ec));
14404 ec->cmd = ETHTOOL_GCOALESCE;
14405 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14406 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14407 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14408 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14409 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14410 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14411 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14412 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14413 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14415 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14416 HOSTCC_MODE_CLRTICK_TXBD)) {
14417 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14418 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14419 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14420 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14423 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14424 ec->rx_coalesce_usecs_irq = 0;
14425 ec->tx_coalesce_usecs_irq = 0;
14426 ec->stats_block_coalesce_usecs = 0;
14430 static const struct net_device_ops tg3_netdev_ops = {
14431 .ndo_open = tg3_open,
14432 .ndo_stop = tg3_close,
14433 .ndo_start_xmit = tg3_start_xmit,
14434 .ndo_get_stats = tg3_get_stats,
14435 .ndo_validate_addr = eth_validate_addr,
14436 .ndo_set_multicast_list = tg3_set_rx_mode,
14437 .ndo_set_mac_address = tg3_set_mac_addr,
14438 .ndo_do_ioctl = tg3_ioctl,
14439 .ndo_tx_timeout = tg3_tx_timeout,
14440 .ndo_change_mtu = tg3_change_mtu,
14441 #if TG3_VLAN_TAG_USED
14442 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14444 #ifdef CONFIG_NET_POLL_CONTROLLER
14445 .ndo_poll_controller = tg3_poll_controller,
14449 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14450 .ndo_open = tg3_open,
14451 .ndo_stop = tg3_close,
14452 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14453 .ndo_get_stats = tg3_get_stats,
14454 .ndo_validate_addr = eth_validate_addr,
14455 .ndo_set_multicast_list = tg3_set_rx_mode,
14456 .ndo_set_mac_address = tg3_set_mac_addr,
14457 .ndo_do_ioctl = tg3_ioctl,
14458 .ndo_tx_timeout = tg3_tx_timeout,
14459 .ndo_change_mtu = tg3_change_mtu,
14460 #if TG3_VLAN_TAG_USED
14461 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14463 #ifdef CONFIG_NET_POLL_CONTROLLER
14464 .ndo_poll_controller = tg3_poll_controller,
14468 static int __devinit tg3_init_one(struct pci_dev *pdev,
14469 const struct pci_device_id *ent)
14471 struct net_device *dev;
14473 int i, err, pm_cap;
14474 u32 sndmbx, rcvmbx, intmbx;
14476 u64 dma_mask, persist_dma_mask;
14478 printk_once(KERN_INFO "%s\n", version);
14480 err = pci_enable_device(pdev);
14482 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14486 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14488 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14489 goto err_out_disable_pdev;
14492 pci_set_master(pdev);
14494 /* Find power-management capability. */
14495 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14497 dev_err(&pdev->dev,
14498 "Cannot find Power Management capability, aborting\n");
14500 goto err_out_free_res;
14503 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14505 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14507 goto err_out_free_res;
14510 SET_NETDEV_DEV(dev, &pdev->dev);
14512 #if TG3_VLAN_TAG_USED
14513 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14516 tp = netdev_priv(dev);
14519 tp->pm_cap = pm_cap;
14520 tp->rx_mode = TG3_DEF_RX_MODE;
14521 tp->tx_mode = TG3_DEF_TX_MODE;
14524 tp->msg_enable = tg3_debug;
14526 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14528 /* The word/byte swap controls here control register access byte
14529 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14532 tp->misc_host_ctrl =
14533 MISC_HOST_CTRL_MASK_PCI_INT |
14534 MISC_HOST_CTRL_WORD_SWAP |
14535 MISC_HOST_CTRL_INDIR_ACCESS |
14536 MISC_HOST_CTRL_PCISTATE_RW;
14538 /* The NONFRM (non-frame) byte/word swap controls take effect
14539 * on descriptor entries, anything which isn't packet data.
14541 * The StrongARM chips on the board (one for tx, one for rx)
14542 * are running in big-endian mode.
14544 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14545 GRC_MODE_WSWAP_NONFRM_DATA);
14546 #ifdef __BIG_ENDIAN
14547 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14549 spin_lock_init(&tp->lock);
14550 spin_lock_init(&tp->indirect_lock);
14551 INIT_WORK(&tp->reset_task, tg3_reset_task);
14553 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14555 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14557 goto err_out_free_dev;
14560 tg3_init_link_config(tp);
14562 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14563 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14565 dev->ethtool_ops = &tg3_ethtool_ops;
14566 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14567 dev->irq = pdev->irq;
14569 err = tg3_get_invariants(tp);
14571 dev_err(&pdev->dev,
14572 "Problem fetching invariants of chip, aborting\n");
14573 goto err_out_iounmap;
14576 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14577 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14578 dev->netdev_ops = &tg3_netdev_ops;
14580 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14583 /* The EPB bridge inside 5714, 5715, and 5780 and any
14584 * device behind the EPB cannot support DMA addresses > 40-bit.
14585 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14586 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14587 * do DMA address check in tg3_start_xmit().
14589 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14590 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14591 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14592 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14593 #ifdef CONFIG_HIGHMEM
14594 dma_mask = DMA_BIT_MASK(64);
14597 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14599 /* Configure DMA attributes. */
14600 if (dma_mask > DMA_BIT_MASK(32)) {
14601 err = pci_set_dma_mask(pdev, dma_mask);
14603 dev->features |= NETIF_F_HIGHDMA;
14604 err = pci_set_consistent_dma_mask(pdev,
14607 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14608 "DMA for consistent allocations\n");
14609 goto err_out_iounmap;
14613 if (err || dma_mask == DMA_BIT_MASK(32)) {
14614 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14616 dev_err(&pdev->dev,
14617 "No usable DMA configuration, aborting\n");
14618 goto err_out_iounmap;
14622 tg3_init_bufmgr_config(tp);
14624 /* Selectively allow TSO based on operating conditions */
14625 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14626 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14627 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14629 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14630 tp->fw_needed = NULL;
14633 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14634 tp->fw_needed = FIRMWARE_TG3;
14636 /* TSO is on by default on chips that support hardware TSO.
14637 * Firmware TSO on older chips gives lower performance, so it
14638 * is off by default, but can be enabled using ethtool.
14640 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14641 (dev->features & NETIF_F_IP_CSUM))
14642 dev->features |= NETIF_F_TSO;
14644 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14645 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14646 if (dev->features & NETIF_F_IPV6_CSUM)
14647 dev->features |= NETIF_F_TSO6;
14648 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14649 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14650 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14651 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14652 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14653 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14654 dev->features |= NETIF_F_TSO_ECN;
14657 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14658 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14659 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14660 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14661 tp->rx_pending = 63;
14664 err = tg3_get_device_address(tp);
14666 dev_err(&pdev->dev,
14667 "Could not obtain valid ethernet address, aborting\n");
14668 goto err_out_iounmap;
14671 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14672 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14673 if (!tp->aperegs) {
14674 dev_err(&pdev->dev,
14675 "Cannot map APE registers, aborting\n");
14677 goto err_out_iounmap;
14680 tg3_ape_lock_init(tp);
14682 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14683 tg3_read_dash_ver(tp);
14687 * Reset chip in case UNDI or EFI driver did not shutdown
14688 * DMA self test will enable WDMAC and we'll see (spurious)
14689 * pending DMA on the PCI bus at that point.
14691 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14692 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14693 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14694 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14697 err = tg3_test_dma(tp);
14699 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14700 goto err_out_apeunmap;
14703 /* flow control autonegotiation is default behavior */
14704 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14705 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14707 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14708 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14709 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14710 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14711 struct tg3_napi *tnapi = &tp->napi[i];
14714 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14716 tnapi->int_mbox = intmbx;
14722 tnapi->consmbox = rcvmbx;
14723 tnapi->prodmbox = sndmbx;
14726 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14727 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14729 tnapi->coal_now = HOSTCC_MODE_NOW;
14730 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14733 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14737 * If we support MSIX, we'll be using RSS. If we're using
14738 * RSS, the first vector only handles link interrupts and the
14739 * remaining vectors handle rx and tx interrupts. Reuse the
14740 * mailbox values for the next iteration. The values we setup
14741 * above are still useful for the single vectored mode.
14756 pci_set_drvdata(pdev, dev);
14758 err = register_netdev(dev);
14760 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14761 goto err_out_apeunmap;
14764 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14765 tp->board_part_number,
14766 tp->pci_chip_rev_id,
14767 tg3_bus_string(tp, str),
14770 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14771 struct phy_device *phydev;
14772 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14774 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14775 phydev->drv->name, dev_name(&phydev->dev));
14777 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14778 "(WireSpeed[%d])\n", tg3_phy_string(tp),
14779 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14780 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14781 "10/100/1000Base-T")),
14782 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14784 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14785 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14786 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14787 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14788 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14789 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14790 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14792 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14793 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14799 iounmap(tp->aperegs);
14800 tp->aperegs = NULL;
14813 pci_release_regions(pdev);
14815 err_out_disable_pdev:
14816 pci_disable_device(pdev);
14817 pci_set_drvdata(pdev, NULL);
14821 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14823 struct net_device *dev = pci_get_drvdata(pdev);
14826 struct tg3 *tp = netdev_priv(dev);
14829 release_firmware(tp->fw);
14831 flush_scheduled_work();
14833 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14838 unregister_netdev(dev);
14840 iounmap(tp->aperegs);
14841 tp->aperegs = NULL;
14848 pci_release_regions(pdev);
14849 pci_disable_device(pdev);
14850 pci_set_drvdata(pdev, NULL);
14854 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14856 struct net_device *dev = pci_get_drvdata(pdev);
14857 struct tg3 *tp = netdev_priv(dev);
14858 pci_power_t target_state;
14861 /* PCI register 4 needs to be saved whether netif_running() or not.
14862 * MSI address and data need to be saved if using MSI and
14865 pci_save_state(pdev);
14867 if (!netif_running(dev))
14870 flush_scheduled_work();
14872 tg3_netif_stop(tp);
14874 del_timer_sync(&tp->timer);
14876 tg3_full_lock(tp, 1);
14877 tg3_disable_ints(tp);
14878 tg3_full_unlock(tp);
14880 netif_device_detach(dev);
14882 tg3_full_lock(tp, 0);
14883 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14884 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14885 tg3_full_unlock(tp);
14887 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14889 err = tg3_set_power_state(tp, target_state);
14893 tg3_full_lock(tp, 0);
14895 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14896 err2 = tg3_restart_hw(tp, 1);
14900 tp->timer.expires = jiffies + tp->timer_offset;
14901 add_timer(&tp->timer);
14903 netif_device_attach(dev);
14904 tg3_netif_start(tp);
14907 tg3_full_unlock(tp);
14916 static int tg3_resume(struct pci_dev *pdev)
14918 struct net_device *dev = pci_get_drvdata(pdev);
14919 struct tg3 *tp = netdev_priv(dev);
14922 pci_restore_state(tp->pdev);
14924 if (!netif_running(dev))
14927 err = tg3_set_power_state(tp, PCI_D0);
14931 netif_device_attach(dev);
14933 tg3_full_lock(tp, 0);
14935 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14936 err = tg3_restart_hw(tp, 1);
14940 tp->timer.expires = jiffies + tp->timer_offset;
14941 add_timer(&tp->timer);
14943 tg3_netif_start(tp);
14946 tg3_full_unlock(tp);
14954 static struct pci_driver tg3_driver = {
14955 .name = DRV_MODULE_NAME,
14956 .id_table = tg3_pci_tbl,
14957 .probe = tg3_init_one,
14958 .remove = __devexit_p(tg3_remove_one),
14959 .suspend = tg3_suspend,
14960 .resume = tg3_resume
14963 static int __init tg3_init(void)
14965 return pci_register_driver(&tg3_driver);
14968 static void __exit tg3_cleanup(void)
14970 pci_unregister_driver(&tg3_driver);
14973 module_init(tg3_init);
14974 module_exit(tg3_cleanup);