2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
18 #include <linux/config.h>
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
42 #include <net/checksum.h>
44 #include <asm/system.h>
46 #include <asm/byteorder.h>
47 #include <asm/uaccess.h>
50 #include <asm/idprom.h>
51 #include <asm/oplib.h>
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
58 #define TG3_VLAN_TAG_USED 0
62 #define TG3_TSO_SUPPORT 1
64 #define TG3_TSO_SUPPORT 0
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.46"
72 #define DRV_MODULE_RELDATE "Dec 19, 2005"
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
90 #define TG3_TX_TIMEOUT (5 * HZ)
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
115 #define TG3_TX_RING_SIZE 512
116 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 #define TX_BUFFS_AVAIL(TP) \
127 ((TP)->tx_pending - \
128 (((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
129 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
131 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
132 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
134 /* minimum number of free TX descriptors required to wake up TX process */
135 #define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
137 /* number of ETHTOOL_GSTATS u64's */
138 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
140 #define TG3_NUM_TEST 6
142 static char version[] __devinitdata =
143 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
145 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
146 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
147 MODULE_LICENSE("GPL");
148 MODULE_VERSION(DRV_MODULE_VERSION);
150 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
151 module_param(tg3_debug, int, 0);
152 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
154 static struct pci_device_id tg3_pci_tbl[] = {
155 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
157 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
159 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
161 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
163 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
165 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
167 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
169 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
171 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
173 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
175 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
177 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
179 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
181 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
183 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
185 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
187 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
189 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
191 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
193 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
195 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
197 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
199 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
201 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
203 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
205 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
207 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
209 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
211 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
213 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
215 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
217 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
219 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
221 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
223 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
225 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
227 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
229 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
231 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
233 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
235 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
237 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
239 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
241 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
243 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
245 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
250 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
253 const char string[ETH_GSTRING_LEN];
254 } ethtool_stats_keys[TG3_NUM_STATS] = {
257 { "rx_ucast_packets" },
258 { "rx_mcast_packets" },
259 { "rx_bcast_packets" },
261 { "rx_align_errors" },
262 { "rx_xon_pause_rcvd" },
263 { "rx_xoff_pause_rcvd" },
264 { "rx_mac_ctrl_rcvd" },
265 { "rx_xoff_entered" },
266 { "rx_frame_too_long_errors" },
268 { "rx_undersize_packets" },
269 { "rx_in_length_errors" },
270 { "rx_out_length_errors" },
271 { "rx_64_or_less_octet_packets" },
272 { "rx_65_to_127_octet_packets" },
273 { "rx_128_to_255_octet_packets" },
274 { "rx_256_to_511_octet_packets" },
275 { "rx_512_to_1023_octet_packets" },
276 { "rx_1024_to_1522_octet_packets" },
277 { "rx_1523_to_2047_octet_packets" },
278 { "rx_2048_to_4095_octet_packets" },
279 { "rx_4096_to_8191_octet_packets" },
280 { "rx_8192_to_9022_octet_packets" },
287 { "tx_flow_control" },
289 { "tx_single_collisions" },
290 { "tx_mult_collisions" },
292 { "tx_excessive_collisions" },
293 { "tx_late_collisions" },
294 { "tx_collide_2times" },
295 { "tx_collide_3times" },
296 { "tx_collide_4times" },
297 { "tx_collide_5times" },
298 { "tx_collide_6times" },
299 { "tx_collide_7times" },
300 { "tx_collide_8times" },
301 { "tx_collide_9times" },
302 { "tx_collide_10times" },
303 { "tx_collide_11times" },
304 { "tx_collide_12times" },
305 { "tx_collide_13times" },
306 { "tx_collide_14times" },
307 { "tx_collide_15times" },
308 { "tx_ucast_packets" },
309 { "tx_mcast_packets" },
310 { "tx_bcast_packets" },
311 { "tx_carrier_sense_errors" },
315 { "dma_writeq_full" },
316 { "dma_write_prioq_full" },
320 { "rx_threshold_hit" },
322 { "dma_readq_full" },
323 { "dma_read_prioq_full" },
324 { "tx_comp_queue_full" },
326 { "ring_set_send_prod_index" },
327 { "ring_status_update" },
329 { "nic_avoided_irqs" },
330 { "nic_tx_threshold_hit" }
334 const char string[ETH_GSTRING_LEN];
335 } ethtool_test_keys[TG3_NUM_TEST] = {
336 { "nvram test (online) " },
337 { "link test (online) " },
338 { "register test (offline)" },
339 { "memory test (offline)" },
340 { "loopback test (offline)" },
341 { "interrupt test (offline)" },
344 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
346 writel(val, tp->regs + off);
349 static u32 tg3_read32(struct tg3 *tp, u32 off)
351 return (readl(tp->regs + off));
354 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
358 spin_lock_irqsave(&tp->indirect_lock, flags);
359 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
360 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
361 spin_unlock_irqrestore(&tp->indirect_lock, flags);
364 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
366 writel(val, tp->regs + off);
367 readl(tp->regs + off);
370 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
375 spin_lock_irqsave(&tp->indirect_lock, flags);
376 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
377 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
378 spin_unlock_irqrestore(&tp->indirect_lock, flags);
382 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
386 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
387 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
388 TG3_64BIT_REG_LOW, val);
391 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
392 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
393 TG3_64BIT_REG_LOW, val);
397 spin_lock_irqsave(&tp->indirect_lock, flags);
398 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
399 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
400 spin_unlock_irqrestore(&tp->indirect_lock, flags);
402 /* In indirect mode when disabling interrupts, we also need
403 * to clear the interrupt bit in the GRC local ctrl register.
405 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
407 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
408 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
412 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
417 spin_lock_irqsave(&tp->indirect_lock, flags);
418 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
419 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
420 spin_unlock_irqrestore(&tp->indirect_lock, flags);
424 /* usec_wait specifies the wait time in usec when writing to certain registers
425 * where it is unsafe to read back the register without some delay.
426 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
427 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
429 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
431 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
432 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
433 /* Non-posted methods */
434 tp->write32(tp, off, val);
437 tg3_write32(tp, off, val);
442 /* Wait again after the read for the posted method to guarantee that
443 * the wait time is met.
449 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
451 tp->write32_mbox(tp, off, val);
452 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
453 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
454 tp->read32_mbox(tp, off);
457 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
459 void __iomem *mbox = tp->regs + off;
461 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
463 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
467 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
468 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
469 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
470 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
471 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
473 #define tw32(reg,val) tp->write32(tp, reg, val)
474 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
475 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
476 #define tr32(reg) tp->read32(tp, reg)
478 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
482 spin_lock_irqsave(&tp->indirect_lock, flags);
483 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
484 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
486 /* Always leave this as zero. */
487 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
488 spin_unlock_irqrestore(&tp->indirect_lock, flags);
491 static void tg3_write_mem_fast(struct tg3 *tp, u32 off, u32 val)
493 /* If no workaround is needed, write to mem space directly */
494 if (tp->write32 != tg3_write_indirect_reg32)
495 tw32(NIC_SRAM_WIN_BASE + off, val);
497 tg3_write_mem(tp, off, val);
500 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
504 spin_lock_irqsave(&tp->indirect_lock, flags);
505 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
506 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
508 /* Always leave this as zero. */
509 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
510 spin_unlock_irqrestore(&tp->indirect_lock, flags);
513 static void tg3_disable_ints(struct tg3 *tp)
515 tw32(TG3PCI_MISC_HOST_CTRL,
516 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
517 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
520 static inline void tg3_cond_int(struct tg3 *tp)
522 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
523 (tp->hw_status->status & SD_STATUS_UPDATED))
524 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
527 static void tg3_enable_ints(struct tg3 *tp)
532 tw32(TG3PCI_MISC_HOST_CTRL,
533 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
534 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
535 (tp->last_tag << 24));
539 static inline unsigned int tg3_has_work(struct tg3 *tp)
541 struct tg3_hw_status *sblk = tp->hw_status;
542 unsigned int work_exists = 0;
544 /* check for phy events */
545 if (!(tp->tg3_flags &
546 (TG3_FLAG_USE_LINKCHG_REG |
547 TG3_FLAG_POLL_SERDES))) {
548 if (sblk->status & SD_STATUS_LINK_CHG)
551 /* check for RX/TX work to do */
552 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
553 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
560 * similar to tg3_enable_ints, but it accurately determines whether there
561 * is new work pending and can return without flushing the PIO write
562 * which reenables interrupts
564 static void tg3_restart_ints(struct tg3 *tp)
566 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
570 /* When doing tagged status, this work check is unnecessary.
571 * The last_tag we write above tells the chip which piece of
572 * work we've completed.
574 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
576 tw32(HOSTCC_MODE, tp->coalesce_mode |
577 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
580 static inline void tg3_netif_stop(struct tg3 *tp)
582 tp->dev->trans_start = jiffies; /* prevent tx timeout */
583 netif_poll_disable(tp->dev);
584 netif_tx_disable(tp->dev);
587 static inline void tg3_netif_start(struct tg3 *tp)
589 netif_wake_queue(tp->dev);
590 /* NOTE: unconditional netif_wake_queue is only appropriate
591 * so long as all callers are assured to have free tx slots
592 * (such as after tg3_init_hw)
594 netif_poll_enable(tp->dev);
595 tp->hw_status->status |= SD_STATUS_UPDATED;
599 static void tg3_switch_clocks(struct tg3 *tp)
601 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
604 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
607 orig_clock_ctrl = clock_ctrl;
608 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
609 CLOCK_CTRL_CLKRUN_OENABLE |
611 tp->pci_clock_ctrl = clock_ctrl;
613 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
614 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
615 tw32_wait_f(TG3PCI_CLOCK_CTRL,
616 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
618 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
619 tw32_wait_f(TG3PCI_CLOCK_CTRL,
621 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
623 tw32_wait_f(TG3PCI_CLOCK_CTRL,
624 clock_ctrl | (CLOCK_CTRL_ALTCLK),
627 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
630 #define PHY_BUSY_LOOPS 5000
632 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
638 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
640 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
646 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
647 MI_COM_PHY_ADDR_MASK);
648 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
649 MI_COM_REG_ADDR_MASK);
650 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
652 tw32_f(MAC_MI_COM, frame_val);
654 loops = PHY_BUSY_LOOPS;
657 frame_val = tr32(MAC_MI_COM);
659 if ((frame_val & MI_COM_BUSY) == 0) {
661 frame_val = tr32(MAC_MI_COM);
669 *val = frame_val & MI_COM_DATA_MASK;
673 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
674 tw32_f(MAC_MI_MODE, tp->mi_mode);
681 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
687 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
689 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
693 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
694 MI_COM_PHY_ADDR_MASK);
695 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
696 MI_COM_REG_ADDR_MASK);
697 frame_val |= (val & MI_COM_DATA_MASK);
698 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
700 tw32_f(MAC_MI_COM, frame_val);
702 loops = PHY_BUSY_LOOPS;
705 frame_val = tr32(MAC_MI_COM);
706 if ((frame_val & MI_COM_BUSY) == 0) {
708 frame_val = tr32(MAC_MI_COM);
718 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
719 tw32_f(MAC_MI_MODE, tp->mi_mode);
726 static void tg3_phy_set_wirespeed(struct tg3 *tp)
730 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
733 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
734 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
735 tg3_writephy(tp, MII_TG3_AUX_CTRL,
736 (val | (1 << 15) | (1 << 4)));
739 static int tg3_bmcr_reset(struct tg3 *tp)
744 /* OK, reset it, and poll the BMCR_RESET bit until it
745 * clears or we time out.
747 phy_control = BMCR_RESET;
748 err = tg3_writephy(tp, MII_BMCR, phy_control);
754 err = tg3_readphy(tp, MII_BMCR, &phy_control);
758 if ((phy_control & BMCR_RESET) == 0) {
770 static int tg3_wait_macro_done(struct tg3 *tp)
777 if (!tg3_readphy(tp, 0x16, &tmp32)) {
778 if ((tmp32 & 0x1000) == 0)
788 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
790 static const u32 test_pat[4][6] = {
791 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
792 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
793 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
794 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
798 for (chan = 0; chan < 4; chan++) {
801 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
802 (chan * 0x2000) | 0x0200);
803 tg3_writephy(tp, 0x16, 0x0002);
805 for (i = 0; i < 6; i++)
806 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
809 tg3_writephy(tp, 0x16, 0x0202);
810 if (tg3_wait_macro_done(tp)) {
815 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
816 (chan * 0x2000) | 0x0200);
817 tg3_writephy(tp, 0x16, 0x0082);
818 if (tg3_wait_macro_done(tp)) {
823 tg3_writephy(tp, 0x16, 0x0802);
824 if (tg3_wait_macro_done(tp)) {
829 for (i = 0; i < 6; i += 2) {
832 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
833 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
834 tg3_wait_macro_done(tp)) {
840 if (low != test_pat[chan][i] ||
841 high != test_pat[chan][i+1]) {
842 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
843 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
844 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
854 static int tg3_phy_reset_chanpat(struct tg3 *tp)
858 for (chan = 0; chan < 4; chan++) {
861 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
862 (chan * 0x2000) | 0x0200);
863 tg3_writephy(tp, 0x16, 0x0002);
864 for (i = 0; i < 6; i++)
865 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
866 tg3_writephy(tp, 0x16, 0x0202);
867 if (tg3_wait_macro_done(tp))
874 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
876 u32 reg32, phy9_orig;
877 int retries, do_phy_reset, err;
883 err = tg3_bmcr_reset(tp);
889 /* Disable transmitter and interrupt. */
890 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
894 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
896 /* Set full-duplex, 1000 mbps. */
897 tg3_writephy(tp, MII_BMCR,
898 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
900 /* Set to master mode. */
901 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
904 tg3_writephy(tp, MII_TG3_CTRL,
905 (MII_TG3_CTRL_AS_MASTER |
906 MII_TG3_CTRL_ENABLE_AS_MASTER));
908 /* Enable SM_DSP_CLOCK and 6dB. */
909 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
911 /* Block the PHY control access. */
912 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
913 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
915 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
920 err = tg3_phy_reset_chanpat(tp);
924 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
925 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
927 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
928 tg3_writephy(tp, 0x16, 0x0000);
930 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
931 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
932 /* Set Extended packet length bit for jumbo frames */
933 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
936 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
939 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
941 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
943 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
950 /* This will reset the tigon3 PHY if there is no valid
951 * link unless the FORCE argument is non-zero.
953 static int tg3_phy_reset(struct tg3 *tp)
958 err = tg3_readphy(tp, MII_BMSR, &phy_status);
959 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
963 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
964 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
965 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
966 err = tg3_phy_reset_5703_4_5(tp);
972 err = tg3_bmcr_reset(tp);
977 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
978 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
979 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
980 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
981 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
982 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
983 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
985 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
986 tg3_writephy(tp, 0x1c, 0x8d68);
987 tg3_writephy(tp, 0x1c, 0x8d68);
989 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
990 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
991 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
992 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
993 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
994 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
995 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
996 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
997 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
999 /* Set Extended packet length bit (bit 14) on all chips that */
1000 /* support jumbo frames */
1001 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1002 /* Cannot do read-modify-write on 5401 */
1003 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1004 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1007 /* Set bit 14 with read-modify-write to preserve other bits */
1008 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1009 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1010 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1013 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1014 * jumbo frames transmission.
1016 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1019 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1020 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1021 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1024 tg3_phy_set_wirespeed(tp);
1028 static void tg3_frob_aux_power(struct tg3 *tp)
1030 struct tg3 *tp_peer = tp;
1032 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1035 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1036 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1037 struct net_device *dev_peer;
1039 dev_peer = pci_get_drvdata(tp->pdev_peer);
1042 tp_peer = netdev_priv(dev_peer);
1045 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1046 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1047 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1048 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1049 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1050 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1051 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1052 (GRC_LCLCTRL_GPIO_OE0 |
1053 GRC_LCLCTRL_GPIO_OE1 |
1054 GRC_LCLCTRL_GPIO_OE2 |
1055 GRC_LCLCTRL_GPIO_OUTPUT0 |
1056 GRC_LCLCTRL_GPIO_OUTPUT1),
1060 u32 grc_local_ctrl = 0;
1062 if (tp_peer != tp &&
1063 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1066 /* Workaround to prevent overdrawing Amps. */
1067 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1069 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1070 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1071 grc_local_ctrl, 100);
1074 /* On 5753 and variants, GPIO2 cannot be used. */
1075 no_gpio2 = tp->nic_sram_data_cfg &
1076 NIC_SRAM_DATA_CFG_NO_GPIO2;
1078 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1079 GRC_LCLCTRL_GPIO_OE1 |
1080 GRC_LCLCTRL_GPIO_OE2 |
1081 GRC_LCLCTRL_GPIO_OUTPUT1 |
1082 GRC_LCLCTRL_GPIO_OUTPUT2;
1084 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1085 GRC_LCLCTRL_GPIO_OUTPUT2);
1087 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1088 grc_local_ctrl, 100);
1090 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1092 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1093 grc_local_ctrl, 100);
1096 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1097 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1098 grc_local_ctrl, 100);
1102 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1103 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1104 if (tp_peer != tp &&
1105 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1108 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1109 (GRC_LCLCTRL_GPIO_OE1 |
1110 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1112 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1113 GRC_LCLCTRL_GPIO_OE1, 100);
1115 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1116 (GRC_LCLCTRL_GPIO_OE1 |
1117 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1122 static int tg3_setup_phy(struct tg3 *, int);
1124 #define RESET_KIND_SHUTDOWN 0
1125 #define RESET_KIND_INIT 1
1126 #define RESET_KIND_SUSPEND 2
1128 static void tg3_write_sig_post_reset(struct tg3 *, int);
1129 static int tg3_halt_cpu(struct tg3 *, u32);
1130 static int tg3_nvram_lock(struct tg3 *);
1131 static void tg3_nvram_unlock(struct tg3 *);
1133 static int tg3_set_power_state(struct tg3 *tp, int state)
1136 u16 power_control, power_caps;
1137 int pm = tp->pm_cap;
1139 /* Make sure register accesses (indirect or otherwise)
1140 * will function correctly.
1142 pci_write_config_dword(tp->pdev,
1143 TG3PCI_MISC_HOST_CTRL,
1144 tp->misc_host_ctrl);
1146 pci_read_config_word(tp->pdev,
1149 power_control |= PCI_PM_CTRL_PME_STATUS;
1150 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1154 pci_write_config_word(tp->pdev,
1157 udelay(100); /* Delay after power state change */
1159 /* Switch out of Vaux if it is not a LOM */
1160 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
1161 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1178 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1180 tp->dev->name, state);
1184 power_control |= PCI_PM_CTRL_PME_ENABLE;
1186 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1187 tw32(TG3PCI_MISC_HOST_CTRL,
1188 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1190 if (tp->link_config.phy_is_low_power == 0) {
1191 tp->link_config.phy_is_low_power = 1;
1192 tp->link_config.orig_speed = tp->link_config.speed;
1193 tp->link_config.orig_duplex = tp->link_config.duplex;
1194 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1197 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1198 tp->link_config.speed = SPEED_10;
1199 tp->link_config.duplex = DUPLEX_HALF;
1200 tp->link_config.autoneg = AUTONEG_ENABLE;
1201 tg3_setup_phy(tp, 0);
1204 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1208 for (i = 0; i < 200; i++) {
1209 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1210 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1215 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1216 WOL_DRV_STATE_SHUTDOWN |
1217 WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1219 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1221 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1224 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1225 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1228 mac_mode = MAC_MODE_PORT_MODE_MII;
1230 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1231 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1232 mac_mode |= MAC_MODE_LINK_POLARITY;
1234 mac_mode = MAC_MODE_PORT_MODE_TBI;
1237 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1238 tw32(MAC_LED_CTRL, tp->led_ctrl);
1240 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1241 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1242 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1244 tw32_f(MAC_MODE, mac_mode);
1247 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1251 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1252 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1253 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1256 base_val = tp->pci_clock_ctrl;
1257 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1258 CLOCK_CTRL_TXCLK_DISABLE);
1260 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1261 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1262 } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1264 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1265 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1266 u32 newbits1, newbits2;
1268 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1269 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1270 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1271 CLOCK_CTRL_TXCLK_DISABLE |
1273 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1274 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1275 newbits1 = CLOCK_CTRL_625_CORE;
1276 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1278 newbits1 = CLOCK_CTRL_ALTCLK;
1279 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1282 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1285 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1288 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1291 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1292 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1293 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1294 CLOCK_CTRL_TXCLK_DISABLE |
1295 CLOCK_CTRL_44MHZ_CORE);
1297 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1300 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1301 tp->pci_clock_ctrl | newbits3, 40);
1305 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1306 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1307 /* Turn off the PHY */
1308 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1309 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1310 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1311 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1312 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
1313 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1317 tg3_frob_aux_power(tp);
1319 /* Workaround for unstable PLL clock */
1320 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1321 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1322 u32 val = tr32(0x7d00);
1324 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1326 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1328 tg3_halt_cpu(tp, RX_CPU_BASE);
1329 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR0);
1330 tg3_nvram_unlock(tp);
1334 /* Finally, set the new power state. */
1335 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1336 udelay(100); /* Delay after power state change */
1338 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1343 static void tg3_link_report(struct tg3 *tp)
1345 if (!netif_carrier_ok(tp->dev)) {
1346 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1348 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1350 (tp->link_config.active_speed == SPEED_1000 ?
1352 (tp->link_config.active_speed == SPEED_100 ?
1354 (tp->link_config.active_duplex == DUPLEX_FULL ?
1357 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1360 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1361 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1365 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1367 u32 new_tg3_flags = 0;
1368 u32 old_rx_mode = tp->rx_mode;
1369 u32 old_tx_mode = tp->tx_mode;
1371 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1373 /* Convert 1000BaseX flow control bits to 1000BaseT
1374 * bits before resolving flow control.
1376 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1377 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1378 ADVERTISE_PAUSE_ASYM);
1379 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1381 if (local_adv & ADVERTISE_1000XPAUSE)
1382 local_adv |= ADVERTISE_PAUSE_CAP;
1383 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1384 local_adv |= ADVERTISE_PAUSE_ASYM;
1385 if (remote_adv & LPA_1000XPAUSE)
1386 remote_adv |= LPA_PAUSE_CAP;
1387 if (remote_adv & LPA_1000XPAUSE_ASYM)
1388 remote_adv |= LPA_PAUSE_ASYM;
1391 if (local_adv & ADVERTISE_PAUSE_CAP) {
1392 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1393 if (remote_adv & LPA_PAUSE_CAP)
1395 (TG3_FLAG_RX_PAUSE |
1397 else if (remote_adv & LPA_PAUSE_ASYM)
1399 (TG3_FLAG_RX_PAUSE);
1401 if (remote_adv & LPA_PAUSE_CAP)
1403 (TG3_FLAG_RX_PAUSE |
1406 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1407 if ((remote_adv & LPA_PAUSE_CAP) &&
1408 (remote_adv & LPA_PAUSE_ASYM))
1409 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1412 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1413 tp->tg3_flags |= new_tg3_flags;
1415 new_tg3_flags = tp->tg3_flags;
1418 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1419 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1421 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1423 if (old_rx_mode != tp->rx_mode) {
1424 tw32_f(MAC_RX_MODE, tp->rx_mode);
1427 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1428 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1430 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1432 if (old_tx_mode != tp->tx_mode) {
1433 tw32_f(MAC_TX_MODE, tp->tx_mode);
1437 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1439 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1440 case MII_TG3_AUX_STAT_10HALF:
1442 *duplex = DUPLEX_HALF;
1445 case MII_TG3_AUX_STAT_10FULL:
1447 *duplex = DUPLEX_FULL;
1450 case MII_TG3_AUX_STAT_100HALF:
1452 *duplex = DUPLEX_HALF;
1455 case MII_TG3_AUX_STAT_100FULL:
1457 *duplex = DUPLEX_FULL;
1460 case MII_TG3_AUX_STAT_1000HALF:
1461 *speed = SPEED_1000;
1462 *duplex = DUPLEX_HALF;
1465 case MII_TG3_AUX_STAT_1000FULL:
1466 *speed = SPEED_1000;
1467 *duplex = DUPLEX_FULL;
1471 *speed = SPEED_INVALID;
1472 *duplex = DUPLEX_INVALID;
1477 static void tg3_phy_copper_begin(struct tg3 *tp)
1482 if (tp->link_config.phy_is_low_power) {
1483 /* Entering low power mode. Disable gigabit and
1484 * 100baseT advertisements.
1486 tg3_writephy(tp, MII_TG3_CTRL, 0);
1488 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1489 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1490 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1491 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1493 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1494 } else if (tp->link_config.speed == SPEED_INVALID) {
1495 tp->link_config.advertising =
1496 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1497 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1498 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1499 ADVERTISED_Autoneg | ADVERTISED_MII);
1501 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1502 tp->link_config.advertising &=
1503 ~(ADVERTISED_1000baseT_Half |
1504 ADVERTISED_1000baseT_Full);
1506 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1507 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1508 new_adv |= ADVERTISE_10HALF;
1509 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1510 new_adv |= ADVERTISE_10FULL;
1511 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1512 new_adv |= ADVERTISE_100HALF;
1513 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1514 new_adv |= ADVERTISE_100FULL;
1515 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1517 if (tp->link_config.advertising &
1518 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1520 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1521 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1522 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1523 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1524 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1525 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1526 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1527 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1528 MII_TG3_CTRL_ENABLE_AS_MASTER);
1529 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1531 tg3_writephy(tp, MII_TG3_CTRL, 0);
1534 /* Asking for a specific link mode. */
1535 if (tp->link_config.speed == SPEED_1000) {
1536 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1537 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1539 if (tp->link_config.duplex == DUPLEX_FULL)
1540 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1542 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1543 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1544 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1545 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1546 MII_TG3_CTRL_ENABLE_AS_MASTER);
1547 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1549 tg3_writephy(tp, MII_TG3_CTRL, 0);
1551 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1552 if (tp->link_config.speed == SPEED_100) {
1553 if (tp->link_config.duplex == DUPLEX_FULL)
1554 new_adv |= ADVERTISE_100FULL;
1556 new_adv |= ADVERTISE_100HALF;
1558 if (tp->link_config.duplex == DUPLEX_FULL)
1559 new_adv |= ADVERTISE_10FULL;
1561 new_adv |= ADVERTISE_10HALF;
1563 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1567 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1568 tp->link_config.speed != SPEED_INVALID) {
1569 u32 bmcr, orig_bmcr;
1571 tp->link_config.active_speed = tp->link_config.speed;
1572 tp->link_config.active_duplex = tp->link_config.duplex;
1575 switch (tp->link_config.speed) {
1581 bmcr |= BMCR_SPEED100;
1585 bmcr |= TG3_BMCR_SPEED1000;
1589 if (tp->link_config.duplex == DUPLEX_FULL)
1590 bmcr |= BMCR_FULLDPLX;
1592 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1593 (bmcr != orig_bmcr)) {
1594 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1595 for (i = 0; i < 1500; i++) {
1599 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1600 tg3_readphy(tp, MII_BMSR, &tmp))
1602 if (!(tmp & BMSR_LSTATUS)) {
1607 tg3_writephy(tp, MII_BMCR, bmcr);
1611 tg3_writephy(tp, MII_BMCR,
1612 BMCR_ANENABLE | BMCR_ANRESTART);
1616 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1620 /* Turn off tap power management. */
1621 /* Set Extended packet length bit */
1622 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1624 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1625 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1627 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1628 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1630 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1631 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1633 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1634 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1636 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1637 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1644 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1646 u32 adv_reg, all_mask;
1648 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1651 all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1652 ADVERTISE_100HALF | ADVERTISE_100FULL);
1653 if ((adv_reg & all_mask) != all_mask)
1655 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1658 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1661 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1662 MII_TG3_CTRL_ADV_1000_FULL);
1663 if ((tg3_ctrl & all_mask) != all_mask)
1669 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1671 int current_link_up;
1680 (MAC_STATUS_SYNC_CHANGED |
1681 MAC_STATUS_CFG_CHANGED |
1682 MAC_STATUS_MI_COMPLETION |
1683 MAC_STATUS_LNKSTATE_CHANGED));
1686 tp->mi_mode = MAC_MI_MODE_BASE;
1687 tw32_f(MAC_MI_MODE, tp->mi_mode);
1690 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1692 /* Some third-party PHYs need to be reset on link going
1695 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1696 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1697 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1698 netif_carrier_ok(tp->dev)) {
1699 tg3_readphy(tp, MII_BMSR, &bmsr);
1700 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1701 !(bmsr & BMSR_LSTATUS))
1707 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1708 tg3_readphy(tp, MII_BMSR, &bmsr);
1709 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1710 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1713 if (!(bmsr & BMSR_LSTATUS)) {
1714 err = tg3_init_5401phy_dsp(tp);
1718 tg3_readphy(tp, MII_BMSR, &bmsr);
1719 for (i = 0; i < 1000; i++) {
1721 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1722 (bmsr & BMSR_LSTATUS)) {
1728 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1729 !(bmsr & BMSR_LSTATUS) &&
1730 tp->link_config.active_speed == SPEED_1000) {
1731 err = tg3_phy_reset(tp);
1733 err = tg3_init_5401phy_dsp(tp);
1738 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1739 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1740 /* 5701 {A0,B0} CRC bug workaround */
1741 tg3_writephy(tp, 0x15, 0x0a75);
1742 tg3_writephy(tp, 0x1c, 0x8c68);
1743 tg3_writephy(tp, 0x1c, 0x8d68);
1744 tg3_writephy(tp, 0x1c, 0x8c68);
1747 /* Clear pending interrupts... */
1748 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1749 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1751 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1752 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1754 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1756 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1757 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1758 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1759 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1760 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1762 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1765 current_link_up = 0;
1766 current_speed = SPEED_INVALID;
1767 current_duplex = DUPLEX_INVALID;
1769 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1772 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1773 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1774 if (!(val & (1 << 10))) {
1776 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1782 for (i = 0; i < 100; i++) {
1783 tg3_readphy(tp, MII_BMSR, &bmsr);
1784 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1785 (bmsr & BMSR_LSTATUS))
1790 if (bmsr & BMSR_LSTATUS) {
1793 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1794 for (i = 0; i < 2000; i++) {
1796 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1801 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1806 for (i = 0; i < 200; i++) {
1807 tg3_readphy(tp, MII_BMCR, &bmcr);
1808 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1810 if (bmcr && bmcr != 0x7fff)
1815 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1816 if (bmcr & BMCR_ANENABLE) {
1817 current_link_up = 1;
1819 /* Force autoneg restart if we are exiting
1822 if (!tg3_copper_is_advertising_all(tp))
1823 current_link_up = 0;
1825 current_link_up = 0;
1828 if (!(bmcr & BMCR_ANENABLE) &&
1829 tp->link_config.speed == current_speed &&
1830 tp->link_config.duplex == current_duplex) {
1831 current_link_up = 1;
1833 current_link_up = 0;
1837 tp->link_config.active_speed = current_speed;
1838 tp->link_config.active_duplex = current_duplex;
1841 if (current_link_up == 1 &&
1842 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1843 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1844 u32 local_adv, remote_adv;
1846 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1848 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1850 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1853 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1855 /* If we are not advertising full pause capability,
1856 * something is wrong. Bring the link down and reconfigure.
1858 if (local_adv != ADVERTISE_PAUSE_CAP) {
1859 current_link_up = 0;
1861 tg3_setup_flow_control(tp, local_adv, remote_adv);
1865 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1868 tg3_phy_copper_begin(tp);
1870 tg3_readphy(tp, MII_BMSR, &tmp);
1871 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1872 (tmp & BMSR_LSTATUS))
1873 current_link_up = 1;
1876 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1877 if (current_link_up == 1) {
1878 if (tp->link_config.active_speed == SPEED_100 ||
1879 tp->link_config.active_speed == SPEED_10)
1880 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1882 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1884 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1886 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1887 if (tp->link_config.active_duplex == DUPLEX_HALF)
1888 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1890 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1891 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1892 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1893 (current_link_up == 1 &&
1894 tp->link_config.active_speed == SPEED_10))
1895 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1897 if (current_link_up == 1)
1898 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1901 /* ??? Without this setting Netgear GA302T PHY does not
1902 * ??? send/receive packets...
1904 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1905 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1906 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1907 tw32_f(MAC_MI_MODE, tp->mi_mode);
1911 tw32_f(MAC_MODE, tp->mac_mode);
1914 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1915 /* Polled via timer. */
1916 tw32_f(MAC_EVENT, 0);
1918 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1922 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1923 current_link_up == 1 &&
1924 tp->link_config.active_speed == SPEED_1000 &&
1925 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1926 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1929 (MAC_STATUS_SYNC_CHANGED |
1930 MAC_STATUS_CFG_CHANGED));
1933 NIC_SRAM_FIRMWARE_MBOX,
1934 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1937 if (current_link_up != netif_carrier_ok(tp->dev)) {
1938 if (current_link_up)
1939 netif_carrier_on(tp->dev);
1941 netif_carrier_off(tp->dev);
1942 tg3_link_report(tp);
1948 struct tg3_fiber_aneginfo {
1950 #define ANEG_STATE_UNKNOWN 0
1951 #define ANEG_STATE_AN_ENABLE 1
1952 #define ANEG_STATE_RESTART_INIT 2
1953 #define ANEG_STATE_RESTART 3
1954 #define ANEG_STATE_DISABLE_LINK_OK 4
1955 #define ANEG_STATE_ABILITY_DETECT_INIT 5
1956 #define ANEG_STATE_ABILITY_DETECT 6
1957 #define ANEG_STATE_ACK_DETECT_INIT 7
1958 #define ANEG_STATE_ACK_DETECT 8
1959 #define ANEG_STATE_COMPLETE_ACK_INIT 9
1960 #define ANEG_STATE_COMPLETE_ACK 10
1961 #define ANEG_STATE_IDLE_DETECT_INIT 11
1962 #define ANEG_STATE_IDLE_DETECT 12
1963 #define ANEG_STATE_LINK_OK 13
1964 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
1965 #define ANEG_STATE_NEXT_PAGE_WAIT 15
1968 #define MR_AN_ENABLE 0x00000001
1969 #define MR_RESTART_AN 0x00000002
1970 #define MR_AN_COMPLETE 0x00000004
1971 #define MR_PAGE_RX 0x00000008
1972 #define MR_NP_LOADED 0x00000010
1973 #define MR_TOGGLE_TX 0x00000020
1974 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
1975 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
1976 #define MR_LP_ADV_SYM_PAUSE 0x00000100
1977 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
1978 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1979 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1980 #define MR_LP_ADV_NEXT_PAGE 0x00001000
1981 #define MR_TOGGLE_RX 0x00002000
1982 #define MR_NP_RX 0x00004000
1984 #define MR_LINK_OK 0x80000000
1986 unsigned long link_time, cur_time;
1988 u32 ability_match_cfg;
1989 int ability_match_count;
1991 char ability_match, idle_match, ack_match;
1993 u32 txconfig, rxconfig;
1994 #define ANEG_CFG_NP 0x00000080
1995 #define ANEG_CFG_ACK 0x00000040
1996 #define ANEG_CFG_RF2 0x00000020
1997 #define ANEG_CFG_RF1 0x00000010
1998 #define ANEG_CFG_PS2 0x00000001
1999 #define ANEG_CFG_PS1 0x00008000
2000 #define ANEG_CFG_HD 0x00004000
2001 #define ANEG_CFG_FD 0x00002000
2002 #define ANEG_CFG_INVAL 0x00001f06
2007 #define ANEG_TIMER_ENAB 2
2008 #define ANEG_FAILED -1
2010 #define ANEG_STATE_SETTLE_TIME 10000
2012 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2013 struct tg3_fiber_aneginfo *ap)
2015 unsigned long delta;
2019 if (ap->state == ANEG_STATE_UNKNOWN) {
2023 ap->ability_match_cfg = 0;
2024 ap->ability_match_count = 0;
2025 ap->ability_match = 0;
2031 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2032 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2034 if (rx_cfg_reg != ap->ability_match_cfg) {
2035 ap->ability_match_cfg = rx_cfg_reg;
2036 ap->ability_match = 0;
2037 ap->ability_match_count = 0;
2039 if (++ap->ability_match_count > 1) {
2040 ap->ability_match = 1;
2041 ap->ability_match_cfg = rx_cfg_reg;
2044 if (rx_cfg_reg & ANEG_CFG_ACK)
2052 ap->ability_match_cfg = 0;
2053 ap->ability_match_count = 0;
2054 ap->ability_match = 0;
2060 ap->rxconfig = rx_cfg_reg;
2064 case ANEG_STATE_UNKNOWN:
2065 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2066 ap->state = ANEG_STATE_AN_ENABLE;
2069 case ANEG_STATE_AN_ENABLE:
2070 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2071 if (ap->flags & MR_AN_ENABLE) {
2074 ap->ability_match_cfg = 0;
2075 ap->ability_match_count = 0;
2076 ap->ability_match = 0;
2080 ap->state = ANEG_STATE_RESTART_INIT;
2082 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2086 case ANEG_STATE_RESTART_INIT:
2087 ap->link_time = ap->cur_time;
2088 ap->flags &= ~(MR_NP_LOADED);
2090 tw32(MAC_TX_AUTO_NEG, 0);
2091 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2092 tw32_f(MAC_MODE, tp->mac_mode);
2095 ret = ANEG_TIMER_ENAB;
2096 ap->state = ANEG_STATE_RESTART;
2099 case ANEG_STATE_RESTART:
2100 delta = ap->cur_time - ap->link_time;
2101 if (delta > ANEG_STATE_SETTLE_TIME) {
2102 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2104 ret = ANEG_TIMER_ENAB;
2108 case ANEG_STATE_DISABLE_LINK_OK:
2112 case ANEG_STATE_ABILITY_DETECT_INIT:
2113 ap->flags &= ~(MR_TOGGLE_TX);
2114 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2115 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2116 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2117 tw32_f(MAC_MODE, tp->mac_mode);
2120 ap->state = ANEG_STATE_ABILITY_DETECT;
2123 case ANEG_STATE_ABILITY_DETECT:
2124 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2125 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2129 case ANEG_STATE_ACK_DETECT_INIT:
2130 ap->txconfig |= ANEG_CFG_ACK;
2131 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2132 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2133 tw32_f(MAC_MODE, tp->mac_mode);
2136 ap->state = ANEG_STATE_ACK_DETECT;
2139 case ANEG_STATE_ACK_DETECT:
2140 if (ap->ack_match != 0) {
2141 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2142 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2143 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2145 ap->state = ANEG_STATE_AN_ENABLE;
2147 } else if (ap->ability_match != 0 &&
2148 ap->rxconfig == 0) {
2149 ap->state = ANEG_STATE_AN_ENABLE;
2153 case ANEG_STATE_COMPLETE_ACK_INIT:
2154 if (ap->rxconfig & ANEG_CFG_INVAL) {
2158 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2159 MR_LP_ADV_HALF_DUPLEX |
2160 MR_LP_ADV_SYM_PAUSE |
2161 MR_LP_ADV_ASYM_PAUSE |
2162 MR_LP_ADV_REMOTE_FAULT1 |
2163 MR_LP_ADV_REMOTE_FAULT2 |
2164 MR_LP_ADV_NEXT_PAGE |
2167 if (ap->rxconfig & ANEG_CFG_FD)
2168 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2169 if (ap->rxconfig & ANEG_CFG_HD)
2170 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2171 if (ap->rxconfig & ANEG_CFG_PS1)
2172 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2173 if (ap->rxconfig & ANEG_CFG_PS2)
2174 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2175 if (ap->rxconfig & ANEG_CFG_RF1)
2176 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2177 if (ap->rxconfig & ANEG_CFG_RF2)
2178 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2179 if (ap->rxconfig & ANEG_CFG_NP)
2180 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2182 ap->link_time = ap->cur_time;
2184 ap->flags ^= (MR_TOGGLE_TX);
2185 if (ap->rxconfig & 0x0008)
2186 ap->flags |= MR_TOGGLE_RX;
2187 if (ap->rxconfig & ANEG_CFG_NP)
2188 ap->flags |= MR_NP_RX;
2189 ap->flags |= MR_PAGE_RX;
2191 ap->state = ANEG_STATE_COMPLETE_ACK;
2192 ret = ANEG_TIMER_ENAB;
2195 case ANEG_STATE_COMPLETE_ACK:
2196 if (ap->ability_match != 0 &&
2197 ap->rxconfig == 0) {
2198 ap->state = ANEG_STATE_AN_ENABLE;
2201 delta = ap->cur_time - ap->link_time;
2202 if (delta > ANEG_STATE_SETTLE_TIME) {
2203 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2204 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2206 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2207 !(ap->flags & MR_NP_RX)) {
2208 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2216 case ANEG_STATE_IDLE_DETECT_INIT:
2217 ap->link_time = ap->cur_time;
2218 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2219 tw32_f(MAC_MODE, tp->mac_mode);
2222 ap->state = ANEG_STATE_IDLE_DETECT;
2223 ret = ANEG_TIMER_ENAB;
2226 case ANEG_STATE_IDLE_DETECT:
2227 if (ap->ability_match != 0 &&
2228 ap->rxconfig == 0) {
2229 ap->state = ANEG_STATE_AN_ENABLE;
2232 delta = ap->cur_time - ap->link_time;
2233 if (delta > ANEG_STATE_SETTLE_TIME) {
2234 /* XXX another gem from the Broadcom driver :( */
2235 ap->state = ANEG_STATE_LINK_OK;
2239 case ANEG_STATE_LINK_OK:
2240 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2244 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2245 /* ??? unimplemented */
2248 case ANEG_STATE_NEXT_PAGE_WAIT:
2249 /* ??? unimplemented */
2260 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2263 struct tg3_fiber_aneginfo aninfo;
2264 int status = ANEG_FAILED;
2268 tw32_f(MAC_TX_AUTO_NEG, 0);
2270 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2271 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2274 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2277 memset(&aninfo, 0, sizeof(aninfo));
2278 aninfo.flags |= MR_AN_ENABLE;
2279 aninfo.state = ANEG_STATE_UNKNOWN;
2280 aninfo.cur_time = 0;
2282 while (++tick < 195000) {
2283 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2284 if (status == ANEG_DONE || status == ANEG_FAILED)
2290 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2291 tw32_f(MAC_MODE, tp->mac_mode);
2294 *flags = aninfo.flags;
2296 if (status == ANEG_DONE &&
2297 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2298 MR_LP_ADV_FULL_DUPLEX)))
2304 static void tg3_init_bcm8002(struct tg3 *tp)
2306 u32 mac_status = tr32(MAC_STATUS);
2309 /* Reset when initting first time or we have a link. */
2310 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2311 !(mac_status & MAC_STATUS_PCS_SYNCED))
2314 /* Set PLL lock range. */
2315 tg3_writephy(tp, 0x16, 0x8007);
2318 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2320 /* Wait for reset to complete. */
2321 /* XXX schedule_timeout() ... */
2322 for (i = 0; i < 500; i++)
2325 /* Config mode; select PMA/Ch 1 regs. */
2326 tg3_writephy(tp, 0x10, 0x8411);
2328 /* Enable auto-lock and comdet, select txclk for tx. */
2329 tg3_writephy(tp, 0x11, 0x0a10);
2331 tg3_writephy(tp, 0x18, 0x00a0);
2332 tg3_writephy(tp, 0x16, 0x41ff);
2334 /* Assert and deassert POR. */
2335 tg3_writephy(tp, 0x13, 0x0400);
2337 tg3_writephy(tp, 0x13, 0x0000);
2339 tg3_writephy(tp, 0x11, 0x0a50);
2341 tg3_writephy(tp, 0x11, 0x0a10);
2343 /* Wait for signal to stabilize */
2344 /* XXX schedule_timeout() ... */
2345 for (i = 0; i < 15000; i++)
2348 /* Deselect the channel register so we can read the PHYID
2351 tg3_writephy(tp, 0x10, 0x8011);
2354 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2356 u32 sg_dig_ctrl, sg_dig_status;
2357 u32 serdes_cfg, expected_sg_dig_ctrl;
2358 int workaround, port_a;
2359 int current_link_up;
2362 expected_sg_dig_ctrl = 0;
2365 current_link_up = 0;
2367 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2368 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2370 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2373 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2374 /* preserve bits 20-23 for voltage regulator */
2375 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2378 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2380 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2381 if (sg_dig_ctrl & (1 << 31)) {
2383 u32 val = serdes_cfg;
2389 tw32_f(MAC_SERDES_CFG, val);
2391 tw32_f(SG_DIG_CTRL, 0x01388400);
2393 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2394 tg3_setup_flow_control(tp, 0, 0);
2395 current_link_up = 1;
2400 /* Want auto-negotiation. */
2401 expected_sg_dig_ctrl = 0x81388400;
2403 /* Pause capability */
2404 expected_sg_dig_ctrl |= (1 << 11);
2406 /* Asymettric pause */
2407 expected_sg_dig_ctrl |= (1 << 12);
2409 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2411 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2412 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2414 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2416 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2417 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2418 MAC_STATUS_SIGNAL_DET)) {
2421 /* Giver time to negotiate (~200ms) */
2422 for (i = 0; i < 40000; i++) {
2423 sg_dig_status = tr32(SG_DIG_STATUS);
2424 if (sg_dig_status & (0x3))
2428 mac_status = tr32(MAC_STATUS);
2430 if ((sg_dig_status & (1 << 1)) &&
2431 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2432 u32 local_adv, remote_adv;
2434 local_adv = ADVERTISE_PAUSE_CAP;
2436 if (sg_dig_status & (1 << 19))
2437 remote_adv |= LPA_PAUSE_CAP;
2438 if (sg_dig_status & (1 << 20))
2439 remote_adv |= LPA_PAUSE_ASYM;
2441 tg3_setup_flow_control(tp, local_adv, remote_adv);
2442 current_link_up = 1;
2443 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2444 } else if (!(sg_dig_status & (1 << 1))) {
2445 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2446 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2449 u32 val = serdes_cfg;
2456 tw32_f(MAC_SERDES_CFG, val);
2459 tw32_f(SG_DIG_CTRL, 0x01388400);
2462 /* Link parallel detection - link is up */
2463 /* only if we have PCS_SYNC and not */
2464 /* receiving config code words */
2465 mac_status = tr32(MAC_STATUS);
2466 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2467 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2468 tg3_setup_flow_control(tp, 0, 0);
2469 current_link_up = 1;
2476 return current_link_up;
2479 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2481 int current_link_up = 0;
2483 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2484 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2488 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2492 if (fiber_autoneg(tp, &flags)) {
2493 u32 local_adv, remote_adv;
2495 local_adv = ADVERTISE_PAUSE_CAP;
2497 if (flags & MR_LP_ADV_SYM_PAUSE)
2498 remote_adv |= LPA_PAUSE_CAP;
2499 if (flags & MR_LP_ADV_ASYM_PAUSE)
2500 remote_adv |= LPA_PAUSE_ASYM;
2502 tg3_setup_flow_control(tp, local_adv, remote_adv);
2504 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2505 current_link_up = 1;
2507 for (i = 0; i < 30; i++) {
2510 (MAC_STATUS_SYNC_CHANGED |
2511 MAC_STATUS_CFG_CHANGED));
2513 if ((tr32(MAC_STATUS) &
2514 (MAC_STATUS_SYNC_CHANGED |
2515 MAC_STATUS_CFG_CHANGED)) == 0)
2519 mac_status = tr32(MAC_STATUS);
2520 if (current_link_up == 0 &&
2521 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2522 !(mac_status & MAC_STATUS_RCVD_CFG))
2523 current_link_up = 1;
2525 /* Forcing 1000FD link up. */
2526 current_link_up = 1;
2527 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2529 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2534 return current_link_up;
2537 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2540 u16 orig_active_speed;
2541 u8 orig_active_duplex;
2543 int current_link_up;
2547 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2548 TG3_FLAG_TX_PAUSE));
2549 orig_active_speed = tp->link_config.active_speed;
2550 orig_active_duplex = tp->link_config.active_duplex;
2552 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2553 netif_carrier_ok(tp->dev) &&
2554 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2555 mac_status = tr32(MAC_STATUS);
2556 mac_status &= (MAC_STATUS_PCS_SYNCED |
2557 MAC_STATUS_SIGNAL_DET |
2558 MAC_STATUS_CFG_CHANGED |
2559 MAC_STATUS_RCVD_CFG);
2560 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2561 MAC_STATUS_SIGNAL_DET)) {
2562 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2563 MAC_STATUS_CFG_CHANGED));
2568 tw32_f(MAC_TX_AUTO_NEG, 0);
2570 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2571 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2572 tw32_f(MAC_MODE, tp->mac_mode);
2575 if (tp->phy_id == PHY_ID_BCM8002)
2576 tg3_init_bcm8002(tp);
2578 /* Enable link change event even when serdes polling. */
2579 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2582 current_link_up = 0;
2583 mac_status = tr32(MAC_STATUS);
2585 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2586 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2588 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2590 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2591 tw32_f(MAC_MODE, tp->mac_mode);
2594 tp->hw_status->status =
2595 (SD_STATUS_UPDATED |
2596 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2598 for (i = 0; i < 100; i++) {
2599 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2600 MAC_STATUS_CFG_CHANGED));
2602 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2603 MAC_STATUS_CFG_CHANGED)) == 0)
2607 mac_status = tr32(MAC_STATUS);
2608 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2609 current_link_up = 0;
2610 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2611 tw32_f(MAC_MODE, (tp->mac_mode |
2612 MAC_MODE_SEND_CONFIGS));
2614 tw32_f(MAC_MODE, tp->mac_mode);
2618 if (current_link_up == 1) {
2619 tp->link_config.active_speed = SPEED_1000;
2620 tp->link_config.active_duplex = DUPLEX_FULL;
2621 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2622 LED_CTRL_LNKLED_OVERRIDE |
2623 LED_CTRL_1000MBPS_ON));
2625 tp->link_config.active_speed = SPEED_INVALID;
2626 tp->link_config.active_duplex = DUPLEX_INVALID;
2627 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2628 LED_CTRL_LNKLED_OVERRIDE |
2629 LED_CTRL_TRAFFIC_OVERRIDE));
2632 if (current_link_up != netif_carrier_ok(tp->dev)) {
2633 if (current_link_up)
2634 netif_carrier_on(tp->dev);
2636 netif_carrier_off(tp->dev);
2637 tg3_link_report(tp);
2640 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2642 if (orig_pause_cfg != now_pause_cfg ||
2643 orig_active_speed != tp->link_config.active_speed ||
2644 orig_active_duplex != tp->link_config.active_duplex)
2645 tg3_link_report(tp);
2651 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2653 int current_link_up, err = 0;
2658 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2659 tw32_f(MAC_MODE, tp->mac_mode);
2665 (MAC_STATUS_SYNC_CHANGED |
2666 MAC_STATUS_CFG_CHANGED |
2667 MAC_STATUS_MI_COMPLETION |
2668 MAC_STATUS_LNKSTATE_CHANGED));
2674 current_link_up = 0;
2675 current_speed = SPEED_INVALID;
2676 current_duplex = DUPLEX_INVALID;
2678 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2679 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2681 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2683 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2684 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2685 /* do nothing, just check for link up at the end */
2686 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2689 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2690 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2691 ADVERTISE_1000XPAUSE |
2692 ADVERTISE_1000XPSE_ASYM |
2695 /* Always advertise symmetric PAUSE just like copper */
2696 new_adv |= ADVERTISE_1000XPAUSE;
2698 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2699 new_adv |= ADVERTISE_1000XHALF;
2700 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2701 new_adv |= ADVERTISE_1000XFULL;
2703 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2704 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2705 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2706 tg3_writephy(tp, MII_BMCR, bmcr);
2708 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2709 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2710 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2717 bmcr &= ~BMCR_SPEED1000;
2718 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2720 if (tp->link_config.duplex == DUPLEX_FULL)
2721 new_bmcr |= BMCR_FULLDPLX;
2723 if (new_bmcr != bmcr) {
2724 /* BMCR_SPEED1000 is a reserved bit that needs
2725 * to be set on write.
2727 new_bmcr |= BMCR_SPEED1000;
2729 /* Force a linkdown */
2730 if (netif_carrier_ok(tp->dev)) {
2733 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2734 adv &= ~(ADVERTISE_1000XFULL |
2735 ADVERTISE_1000XHALF |
2737 tg3_writephy(tp, MII_ADVERTISE, adv);
2738 tg3_writephy(tp, MII_BMCR, bmcr |
2742 netif_carrier_off(tp->dev);
2744 tg3_writephy(tp, MII_BMCR, new_bmcr);
2746 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2747 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2748 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2752 if (bmsr & BMSR_LSTATUS) {
2753 current_speed = SPEED_1000;
2754 current_link_up = 1;
2755 if (bmcr & BMCR_FULLDPLX)
2756 current_duplex = DUPLEX_FULL;
2758 current_duplex = DUPLEX_HALF;
2760 if (bmcr & BMCR_ANENABLE) {
2761 u32 local_adv, remote_adv, common;
2763 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2764 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2765 common = local_adv & remote_adv;
2766 if (common & (ADVERTISE_1000XHALF |
2767 ADVERTISE_1000XFULL)) {
2768 if (common & ADVERTISE_1000XFULL)
2769 current_duplex = DUPLEX_FULL;
2771 current_duplex = DUPLEX_HALF;
2773 tg3_setup_flow_control(tp, local_adv,
2777 current_link_up = 0;
2781 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2782 if (tp->link_config.active_duplex == DUPLEX_HALF)
2783 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2785 tw32_f(MAC_MODE, tp->mac_mode);
2788 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2790 tp->link_config.active_speed = current_speed;
2791 tp->link_config.active_duplex = current_duplex;
2793 if (current_link_up != netif_carrier_ok(tp->dev)) {
2794 if (current_link_up)
2795 netif_carrier_on(tp->dev);
2797 netif_carrier_off(tp->dev);
2798 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2800 tg3_link_report(tp);
2805 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2807 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2808 /* Give autoneg time to complete. */
2809 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2812 if (!netif_carrier_ok(tp->dev) &&
2813 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2816 tg3_readphy(tp, MII_BMCR, &bmcr);
2817 if (bmcr & BMCR_ANENABLE) {
2820 /* Select shadow register 0x1f */
2821 tg3_writephy(tp, 0x1c, 0x7c00);
2822 tg3_readphy(tp, 0x1c, &phy1);
2824 /* Select expansion interrupt status register */
2825 tg3_writephy(tp, 0x17, 0x0f01);
2826 tg3_readphy(tp, 0x15, &phy2);
2827 tg3_readphy(tp, 0x15, &phy2);
2829 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2830 /* We have signal detect and not receiving
2831 * config code words, link is up by parallel
2835 bmcr &= ~BMCR_ANENABLE;
2836 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2837 tg3_writephy(tp, MII_BMCR, bmcr);
2838 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2842 else if (netif_carrier_ok(tp->dev) &&
2843 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2844 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2847 /* Select expansion interrupt status register */
2848 tg3_writephy(tp, 0x17, 0x0f01);
2849 tg3_readphy(tp, 0x15, &phy2);
2853 /* Config code words received, turn on autoneg. */
2854 tg3_readphy(tp, MII_BMCR, &bmcr);
2855 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2857 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2863 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2867 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2868 err = tg3_setup_fiber_phy(tp, force_reset);
2869 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2870 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2872 err = tg3_setup_copper_phy(tp, force_reset);
2875 if (tp->link_config.active_speed == SPEED_1000 &&
2876 tp->link_config.active_duplex == DUPLEX_HALF)
2877 tw32(MAC_TX_LENGTHS,
2878 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2879 (6 << TX_LENGTHS_IPG_SHIFT) |
2880 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2882 tw32(MAC_TX_LENGTHS,
2883 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2884 (6 << TX_LENGTHS_IPG_SHIFT) |
2885 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2887 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2888 if (netif_carrier_ok(tp->dev)) {
2889 tw32(HOSTCC_STAT_COAL_TICKS,
2890 tp->coal.stats_block_coalesce_usecs);
2892 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2899 /* Tigon3 never reports partial packet sends. So we do not
2900 * need special logic to handle SKBs that have not had all
2901 * of their frags sent yet, like SunGEM does.
2903 static void tg3_tx(struct tg3 *tp)
2905 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2906 u32 sw_idx = tp->tx_cons;
2908 while (sw_idx != hw_idx) {
2909 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2910 struct sk_buff *skb = ri->skb;
2913 if (unlikely(skb == NULL))
2916 pci_unmap_single(tp->pdev,
2917 pci_unmap_addr(ri, mapping),
2923 sw_idx = NEXT_TX(sw_idx);
2925 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2926 if (unlikely(sw_idx == hw_idx))
2929 ri = &tp->tx_buffers[sw_idx];
2930 if (unlikely(ri->skb != NULL))
2933 pci_unmap_page(tp->pdev,
2934 pci_unmap_addr(ri, mapping),
2935 skb_shinfo(skb)->frags[i].size,
2938 sw_idx = NEXT_TX(sw_idx);
2944 tp->tx_cons = sw_idx;
2946 if (unlikely(netif_queue_stopped(tp->dev))) {
2947 spin_lock(&tp->tx_lock);
2948 if (netif_queue_stopped(tp->dev) &&
2949 (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2950 netif_wake_queue(tp->dev);
2951 spin_unlock(&tp->tx_lock);
2955 /* Returns size of skb allocated or < 0 on error.
2957 * We only need to fill in the address because the other members
2958 * of the RX descriptor are invariant, see tg3_init_rings.
2960 * Note the purposeful assymetry of cpu vs. chip accesses. For
2961 * posting buffers we only dirty the first cache line of the RX
2962 * descriptor (containing the address). Whereas for the RX status
2963 * buffers the cpu only reads the last cacheline of the RX descriptor
2964 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2966 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2967 int src_idx, u32 dest_idx_unmasked)
2969 struct tg3_rx_buffer_desc *desc;
2970 struct ring_info *map, *src_map;
2971 struct sk_buff *skb;
2973 int skb_size, dest_idx;
2976 switch (opaque_key) {
2977 case RXD_OPAQUE_RING_STD:
2978 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2979 desc = &tp->rx_std[dest_idx];
2980 map = &tp->rx_std_buffers[dest_idx];
2982 src_map = &tp->rx_std_buffers[src_idx];
2983 skb_size = tp->rx_pkt_buf_sz;
2986 case RXD_OPAQUE_RING_JUMBO:
2987 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2988 desc = &tp->rx_jumbo[dest_idx];
2989 map = &tp->rx_jumbo_buffers[dest_idx];
2991 src_map = &tp->rx_jumbo_buffers[src_idx];
2992 skb_size = RX_JUMBO_PKT_BUF_SZ;
2999 /* Do not overwrite any of the map or rp information
3000 * until we are sure we can commit to a new buffer.
3002 * Callers depend upon this behavior and assume that
3003 * we leave everything unchanged if we fail.
3005 skb = dev_alloc_skb(skb_size);
3010 skb_reserve(skb, tp->rx_offset);
3012 mapping = pci_map_single(tp->pdev, skb->data,
3013 skb_size - tp->rx_offset,
3014 PCI_DMA_FROMDEVICE);
3017 pci_unmap_addr_set(map, mapping, mapping);
3019 if (src_map != NULL)
3020 src_map->skb = NULL;
3022 desc->addr_hi = ((u64)mapping >> 32);
3023 desc->addr_lo = ((u64)mapping & 0xffffffff);
3028 /* We only need to move over in the address because the other
3029 * members of the RX descriptor are invariant. See notes above
3030 * tg3_alloc_rx_skb for full details.
3032 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3033 int src_idx, u32 dest_idx_unmasked)
3035 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3036 struct ring_info *src_map, *dest_map;
3039 switch (opaque_key) {
3040 case RXD_OPAQUE_RING_STD:
3041 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3042 dest_desc = &tp->rx_std[dest_idx];
3043 dest_map = &tp->rx_std_buffers[dest_idx];
3044 src_desc = &tp->rx_std[src_idx];
3045 src_map = &tp->rx_std_buffers[src_idx];
3048 case RXD_OPAQUE_RING_JUMBO:
3049 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3050 dest_desc = &tp->rx_jumbo[dest_idx];
3051 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3052 src_desc = &tp->rx_jumbo[src_idx];
3053 src_map = &tp->rx_jumbo_buffers[src_idx];
3060 dest_map->skb = src_map->skb;
3061 pci_unmap_addr_set(dest_map, mapping,
3062 pci_unmap_addr(src_map, mapping));
3063 dest_desc->addr_hi = src_desc->addr_hi;
3064 dest_desc->addr_lo = src_desc->addr_lo;
3066 src_map->skb = NULL;
3069 #if TG3_VLAN_TAG_USED
3070 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3072 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3076 /* The RX ring scheme is composed of multiple rings which post fresh
3077 * buffers to the chip, and one special ring the chip uses to report
3078 * status back to the host.
3080 * The special ring reports the status of received packets to the
3081 * host. The chip does not write into the original descriptor the
3082 * RX buffer was obtained from. The chip simply takes the original
3083 * descriptor as provided by the host, updates the status and length
3084 * field, then writes this into the next status ring entry.
3086 * Each ring the host uses to post buffers to the chip is described
3087 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3088 * it is first placed into the on-chip ram. When the packet's length
3089 * is known, it walks down the TG3_BDINFO entries to select the ring.
3090 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3091 * which is within the range of the new packet's length is chosen.
3093 * The "separate ring for rx status" scheme may sound queer, but it makes
3094 * sense from a cache coherency perspective. If only the host writes
3095 * to the buffer post rings, and only the chip writes to the rx status
3096 * rings, then cache lines never move beyond shared-modified state.
3097 * If both the host and chip were to write into the same ring, cache line
3098 * eviction could occur since both entities want it in an exclusive state.
3100 static int tg3_rx(struct tg3 *tp, int budget)
3103 u32 sw_idx = tp->rx_rcb_ptr;
3107 hw_idx = tp->hw_status->idx[0].rx_producer;
3109 * We need to order the read of hw_idx and the read of
3110 * the opaque cookie.
3115 while (sw_idx != hw_idx && budget > 0) {
3116 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3118 struct sk_buff *skb;
3119 dma_addr_t dma_addr;
3120 u32 opaque_key, desc_idx, *post_ptr;
3122 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3123 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3124 if (opaque_key == RXD_OPAQUE_RING_STD) {
3125 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3127 skb = tp->rx_std_buffers[desc_idx].skb;
3128 post_ptr = &tp->rx_std_ptr;
3129 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3130 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3132 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3133 post_ptr = &tp->rx_jumbo_ptr;
3136 goto next_pkt_nopost;
3139 work_mask |= opaque_key;
3141 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3142 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3144 tg3_recycle_rx(tp, opaque_key,
3145 desc_idx, *post_ptr);
3147 /* Other statistics kept track of by card. */
3148 tp->net_stats.rx_dropped++;
3152 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3154 if (len > RX_COPY_THRESHOLD
3155 && tp->rx_offset == 2
3156 /* rx_offset != 2 iff this is a 5701 card running
3157 * in PCI-X mode [see tg3_get_invariants()] */
3161 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3162 desc_idx, *post_ptr);
3166 pci_unmap_single(tp->pdev, dma_addr,
3167 skb_size - tp->rx_offset,
3168 PCI_DMA_FROMDEVICE);
3172 struct sk_buff *copy_skb;
3174 tg3_recycle_rx(tp, opaque_key,
3175 desc_idx, *post_ptr);
3177 copy_skb = dev_alloc_skb(len + 2);
3178 if (copy_skb == NULL)
3179 goto drop_it_no_recycle;
3181 copy_skb->dev = tp->dev;
3182 skb_reserve(copy_skb, 2);
3183 skb_put(copy_skb, len);
3184 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3185 memcpy(copy_skb->data, skb->data, len);
3186 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3188 /* We'll reuse the original ring buffer. */
3192 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3193 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3194 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3195 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3196 skb->ip_summed = CHECKSUM_UNNECESSARY;
3198 skb->ip_summed = CHECKSUM_NONE;
3200 skb->protocol = eth_type_trans(skb, tp->dev);
3201 #if TG3_VLAN_TAG_USED
3202 if (tp->vlgrp != NULL &&
3203 desc->type_flags & RXD_FLAG_VLAN) {
3204 tg3_vlan_rx(tp, skb,
3205 desc->err_vlan & RXD_VLAN_MASK);
3208 netif_receive_skb(skb);
3210 tp->dev->last_rx = jiffies;
3218 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3220 /* Refresh hw_idx to see if there is new work */
3221 if (sw_idx == hw_idx) {
3222 hw_idx = tp->hw_status->idx[0].rx_producer;
3227 /* ACK the status ring. */
3228 tp->rx_rcb_ptr = sw_idx;
3229 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3231 /* Refill RX ring(s). */
3232 if (work_mask & RXD_OPAQUE_RING_STD) {
3233 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3234 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3237 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3238 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3239 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3247 static int tg3_poll(struct net_device *netdev, int *budget)
3249 struct tg3 *tp = netdev_priv(netdev);
3250 struct tg3_hw_status *sblk = tp->hw_status;
3253 /* handle link change and other phy events */
3254 if (!(tp->tg3_flags &
3255 (TG3_FLAG_USE_LINKCHG_REG |
3256 TG3_FLAG_POLL_SERDES))) {
3257 if (sblk->status & SD_STATUS_LINK_CHG) {
3258 sblk->status = SD_STATUS_UPDATED |
3259 (sblk->status & ~SD_STATUS_LINK_CHG);
3260 spin_lock(&tp->lock);
3261 tg3_setup_phy(tp, 0);
3262 spin_unlock(&tp->lock);
3266 /* run TX completion thread */
3267 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3271 /* run RX thread, within the bounds set by NAPI.
3272 * All RX "locking" is done by ensuring outside
3273 * code synchronizes with dev->poll()
3275 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3276 int orig_budget = *budget;
3279 if (orig_budget > netdev->quota)
3280 orig_budget = netdev->quota;
3282 work_done = tg3_rx(tp, orig_budget);
3284 *budget -= work_done;
3285 netdev->quota -= work_done;
3288 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3289 tp->last_tag = sblk->status_tag;
3292 sblk->status &= ~SD_STATUS_UPDATED;
3294 /* if no more work, tell net stack and NIC we're done */
3295 done = !tg3_has_work(tp);
3297 netif_rx_complete(netdev);
3298 tg3_restart_ints(tp);
3301 return (done ? 0 : 1);
3304 static void tg3_irq_quiesce(struct tg3 *tp)
3306 BUG_ON(tp->irq_sync);
3311 synchronize_irq(tp->pdev->irq);
3314 static inline int tg3_irq_sync(struct tg3 *tp)
3316 return tp->irq_sync;
3319 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3320 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3321 * with as well. Most of the time, this is not necessary except when
3322 * shutting down the device.
3324 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3327 tg3_irq_quiesce(tp);
3328 spin_lock_bh(&tp->lock);
3329 spin_lock(&tp->tx_lock);
3332 static inline void tg3_full_unlock(struct tg3 *tp)
3334 spin_unlock(&tp->tx_lock);
3335 spin_unlock_bh(&tp->lock);
3338 /* MSI ISR - No need to check for interrupt sharing and no need to
3339 * flush status block and interrupt mailbox. PCI ordering rules
3340 * guarantee that MSI will arrive after the status block.
3342 static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
3344 struct net_device *dev = dev_id;
3345 struct tg3 *tp = netdev_priv(dev);
3347 prefetch(tp->hw_status);
3348 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3350 * Writing any value to intr-mbox-0 clears PCI INTA# and
3351 * chip-internal interrupt pending events.
3352 * Writing non-zero to intr-mbox-0 additional tells the
3353 * NIC to stop sending us irqs, engaging "in-intr-handler"
3356 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3357 if (likely(!tg3_irq_sync(tp)))
3358 netif_rx_schedule(dev); /* schedule NAPI poll */
3360 return IRQ_RETVAL(1);
3363 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3365 struct net_device *dev = dev_id;
3366 struct tg3 *tp = netdev_priv(dev);
3367 struct tg3_hw_status *sblk = tp->hw_status;
3368 unsigned int handled = 1;
3370 /* In INTx mode, it is possible for the interrupt to arrive at
3371 * the CPU before the status block posted prior to the interrupt.
3372 * Reading the PCI State register will confirm whether the
3373 * interrupt is ours and will flush the status block.
3375 if ((sblk->status & SD_STATUS_UPDATED) ||
3376 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3378 * Writing any value to intr-mbox-0 clears PCI INTA# and
3379 * chip-internal interrupt pending events.
3380 * Writing non-zero to intr-mbox-0 additional tells the
3381 * NIC to stop sending us irqs, engaging "in-intr-handler"
3384 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3386 if (tg3_irq_sync(tp))
3388 sblk->status &= ~SD_STATUS_UPDATED;
3389 if (likely(tg3_has_work(tp))) {
3390 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3391 netif_rx_schedule(dev); /* schedule NAPI poll */
3393 /* No work, shared interrupt perhaps? re-enable
3394 * interrupts, and flush that PCI write
3396 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3399 } else { /* shared interrupt */
3403 return IRQ_RETVAL(handled);
3406 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3408 struct net_device *dev = dev_id;
3409 struct tg3 *tp = netdev_priv(dev);
3410 struct tg3_hw_status *sblk = tp->hw_status;
3411 unsigned int handled = 1;
3413 /* In INTx mode, it is possible for the interrupt to arrive at
3414 * the CPU before the status block posted prior to the interrupt.
3415 * Reading the PCI State register will confirm whether the
3416 * interrupt is ours and will flush the status block.
3418 if ((sblk->status_tag != tp->last_tag) ||
3419 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3421 * writing any value to intr-mbox-0 clears PCI INTA# and
3422 * chip-internal interrupt pending events.
3423 * writing non-zero to intr-mbox-0 additional tells the
3424 * NIC to stop sending us irqs, engaging "in-intr-handler"
3427 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3429 if (tg3_irq_sync(tp))
3431 if (netif_rx_schedule_prep(dev)) {
3432 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3433 /* Update last_tag to mark that this status has been
3434 * seen. Because interrupt may be shared, we may be
3435 * racing with tg3_poll(), so only update last_tag
3436 * if tg3_poll() is not scheduled.
3438 tp->last_tag = sblk->status_tag;
3439 __netif_rx_schedule(dev);
3441 } else { /* shared interrupt */
3445 return IRQ_RETVAL(handled);
3448 /* ISR for interrupt test */
3449 static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3450 struct pt_regs *regs)
3452 struct net_device *dev = dev_id;
3453 struct tg3 *tp = netdev_priv(dev);
3454 struct tg3_hw_status *sblk = tp->hw_status;
3456 if ((sblk->status & SD_STATUS_UPDATED) ||
3457 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3458 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3460 return IRQ_RETVAL(1);
3462 return IRQ_RETVAL(0);
3465 static int tg3_init_hw(struct tg3 *);
3466 static int tg3_halt(struct tg3 *, int, int);
3468 #ifdef CONFIG_NET_POLL_CONTROLLER
3469 static void tg3_poll_controller(struct net_device *dev)
3471 struct tg3 *tp = netdev_priv(dev);
3473 tg3_interrupt(tp->pdev->irq, dev, NULL);
3477 static void tg3_reset_task(void *_data)
3479 struct tg3 *tp = _data;
3480 unsigned int restart_timer;
3484 tg3_full_lock(tp, 1);
3486 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3487 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3489 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3492 tg3_netif_start(tp);
3494 tg3_full_unlock(tp);
3497 mod_timer(&tp->timer, jiffies + 1);
3500 static void tg3_tx_timeout(struct net_device *dev)
3502 struct tg3 *tp = netdev_priv(dev);
3504 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3507 schedule_work(&tp->reset_task);
3510 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3511 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3513 u32 base = (u32) mapping & 0xffffffff;
3515 return ((base > 0xffffdcc0) &&
3516 (base + len + 8 < base));
3519 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3521 static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3522 u32 last_plus_one, u32 *start,
3523 u32 base_flags, u32 mss)
3525 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3526 dma_addr_t new_addr = 0;
3533 /* New SKB is guaranteed to be linear. */
3535 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3537 /* Make sure new skb does not cross any 4G boundaries.
3538 * Drop the packet if it does.
3540 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3542 dev_kfree_skb(new_skb);
3545 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3546 base_flags, 1 | (mss << 1));
3547 *start = NEXT_TX(entry);
3551 /* Now clean up the sw ring entries. */
3553 while (entry != last_plus_one) {
3557 len = skb_headlen(skb);
3559 len = skb_shinfo(skb)->frags[i-1].size;
3560 pci_unmap_single(tp->pdev,
3561 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3562 len, PCI_DMA_TODEVICE);
3564 tp->tx_buffers[entry].skb = new_skb;
3565 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3567 tp->tx_buffers[entry].skb = NULL;
3569 entry = NEXT_TX(entry);
3578 static void tg3_set_txd(struct tg3 *tp, int entry,
3579 dma_addr_t mapping, int len, u32 flags,
3582 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3583 int is_end = (mss_and_is_end & 0x1);
3584 u32 mss = (mss_and_is_end >> 1);
3588 flags |= TXD_FLAG_END;
3589 if (flags & TXD_FLAG_VLAN) {
3590 vlan_tag = flags >> 16;
3593 vlan_tag |= (mss << TXD_MSS_SHIFT);
3595 txd->addr_hi = ((u64) mapping >> 32);
3596 txd->addr_lo = ((u64) mapping & 0xffffffff);
3597 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3598 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3601 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3603 struct tg3 *tp = netdev_priv(dev);
3605 u32 len, entry, base_flags, mss;
3606 int would_hit_hwbug;
3608 len = skb_headlen(skb);
3610 /* No BH disabling for tx_lock here. We are running in BH disabled
3611 * context and TX reclaim runs via tp->poll inside of a software
3612 * interrupt. Furthermore, IRQ processing runs lockless so we have
3613 * no IRQ context deadlocks to worry about either. Rejoice!
3615 if (!spin_trylock(&tp->tx_lock))
3616 return NETDEV_TX_LOCKED;
3618 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3619 if (!netif_queue_stopped(dev)) {
3620 netif_stop_queue(dev);
3622 /* This is a hard error, log it. */
3623 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3624 "queue awake!\n", dev->name);
3626 spin_unlock(&tp->tx_lock);
3627 return NETDEV_TX_BUSY;
3630 entry = tp->tx_prod;
3632 if (skb->ip_summed == CHECKSUM_HW)
3633 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3634 #if TG3_TSO_SUPPORT != 0
3636 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3637 (mss = skb_shinfo(skb)->tso_size) != 0) {
3638 int tcp_opt_len, ip_tcp_len;
3640 if (skb_header_cloned(skb) &&
3641 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3646 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3647 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3649 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3650 TXD_FLAG_CPU_POST_DMA);
3652 skb->nh.iph->check = 0;
3653 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3654 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3655 skb->h.th->check = 0;
3656 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3660 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3665 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3666 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3667 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3670 tsflags = ((skb->nh.iph->ihl - 5) +
3671 (tcp_opt_len >> 2));
3672 mss |= (tsflags << 11);
3675 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3678 tsflags = ((skb->nh.iph->ihl - 5) +
3679 (tcp_opt_len >> 2));
3680 base_flags |= tsflags << 12;
3687 #if TG3_VLAN_TAG_USED
3688 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3689 base_flags |= (TXD_FLAG_VLAN |
3690 (vlan_tx_tag_get(skb) << 16));
3693 /* Queue skb data, a.k.a. the main skb fragment. */
3694 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3696 tp->tx_buffers[entry].skb = skb;
3697 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3699 would_hit_hwbug = 0;
3701 if (tg3_4g_overflow_test(mapping, len))
3702 would_hit_hwbug = 1;
3704 tg3_set_txd(tp, entry, mapping, len, base_flags,
3705 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3707 entry = NEXT_TX(entry);
3709 /* Now loop through additional data fragments, and queue them. */
3710 if (skb_shinfo(skb)->nr_frags > 0) {
3711 unsigned int i, last;
3713 last = skb_shinfo(skb)->nr_frags - 1;
3714 for (i = 0; i <= last; i++) {
3715 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3718 mapping = pci_map_page(tp->pdev,
3721 len, PCI_DMA_TODEVICE);
3723 tp->tx_buffers[entry].skb = NULL;
3724 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3726 if (tg3_4g_overflow_test(mapping, len))
3727 would_hit_hwbug = 1;
3729 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3730 tg3_set_txd(tp, entry, mapping, len,
3731 base_flags, (i == last)|(mss << 1));
3733 tg3_set_txd(tp, entry, mapping, len,
3734 base_flags, (i == last));
3736 entry = NEXT_TX(entry);
3740 if (would_hit_hwbug) {
3741 u32 last_plus_one = entry;
3744 start = entry - 1 - skb_shinfo(skb)->nr_frags;
3745 start &= (TG3_TX_RING_SIZE - 1);
3747 /* If the workaround fails due to memory/mapping
3748 * failure, silently drop this packet.
3750 if (tigon3_4gb_hwbug_workaround(tp, skb, last_plus_one,
3751 &start, base_flags, mss))
3757 /* Packets are ready, update Tx producer idx local and on card. */
3758 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3760 tp->tx_prod = entry;
3761 if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
3762 netif_stop_queue(dev);
3763 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
3764 netif_wake_queue(tp->dev);
3769 spin_unlock(&tp->tx_lock);
3771 dev->trans_start = jiffies;
3773 return NETDEV_TX_OK;
3776 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3781 if (new_mtu > ETH_DATA_LEN) {
3782 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
3783 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
3784 ethtool_op_set_tso(dev, 0);
3787 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
3789 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
3790 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
3791 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
3795 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3797 struct tg3 *tp = netdev_priv(dev);
3799 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3802 if (!netif_running(dev)) {
3803 /* We'll just catch it later when the
3806 tg3_set_mtu(dev, tp, new_mtu);
3812 tg3_full_lock(tp, 1);
3814 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3816 tg3_set_mtu(dev, tp, new_mtu);
3820 tg3_netif_start(tp);
3822 tg3_full_unlock(tp);
3827 /* Free up pending packets in all rx/tx rings.
3829 * The chip has been shut down and the driver detached from
3830 * the networking, so no interrupts or new tx packets will
3831 * end up in the driver. tp->{tx,}lock is not held and we are not
3832 * in an interrupt context and thus may sleep.
3834 static void tg3_free_rings(struct tg3 *tp)
3836 struct ring_info *rxp;
3839 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3840 rxp = &tp->rx_std_buffers[i];
3842 if (rxp->skb == NULL)
3844 pci_unmap_single(tp->pdev,
3845 pci_unmap_addr(rxp, mapping),
3846 tp->rx_pkt_buf_sz - tp->rx_offset,
3847 PCI_DMA_FROMDEVICE);
3848 dev_kfree_skb_any(rxp->skb);
3852 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3853 rxp = &tp->rx_jumbo_buffers[i];
3855 if (rxp->skb == NULL)
3857 pci_unmap_single(tp->pdev,
3858 pci_unmap_addr(rxp, mapping),
3859 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3860 PCI_DMA_FROMDEVICE);
3861 dev_kfree_skb_any(rxp->skb);
3865 for (i = 0; i < TG3_TX_RING_SIZE; ) {
3866 struct tx_ring_info *txp;
3867 struct sk_buff *skb;
3870 txp = &tp->tx_buffers[i];
3878 pci_unmap_single(tp->pdev,
3879 pci_unmap_addr(txp, mapping),
3886 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3887 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3888 pci_unmap_page(tp->pdev,
3889 pci_unmap_addr(txp, mapping),
3890 skb_shinfo(skb)->frags[j].size,
3895 dev_kfree_skb_any(skb);
3899 /* Initialize tx/rx rings for packet processing.
3901 * The chip has been shut down and the driver detached from
3902 * the networking, so no interrupts or new tx packets will
3903 * end up in the driver. tp->{tx,}lock are held and thus
3906 static void tg3_init_rings(struct tg3 *tp)
3910 /* Free up all the SKBs. */
3913 /* Zero out all descriptors. */
3914 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3915 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3916 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3917 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3919 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
3920 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
3921 (tp->dev->mtu > ETH_DATA_LEN))
3922 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
3924 /* Initialize invariants of the rings, we only set this
3925 * stuff once. This works because the card does not
3926 * write into the rx buffer posting rings.
3928 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3929 struct tg3_rx_buffer_desc *rxd;
3931 rxd = &tp->rx_std[i];
3932 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
3934 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3935 rxd->opaque = (RXD_OPAQUE_RING_STD |
3936 (i << RXD_OPAQUE_INDEX_SHIFT));
3939 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
3940 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3941 struct tg3_rx_buffer_desc *rxd;
3943 rxd = &tp->rx_jumbo[i];
3944 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3946 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3948 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3949 (i << RXD_OPAQUE_INDEX_SHIFT));
3953 /* Now allocate fresh SKBs for each rx ring. */
3954 for (i = 0; i < tp->rx_pending; i++) {
3955 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3960 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
3961 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3962 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3970 * Must not be invoked with interrupt sources disabled and
3971 * the hardware shutdown down.
3973 static void tg3_free_consistent(struct tg3 *tp)
3975 kfree(tp->rx_std_buffers);
3976 tp->rx_std_buffers = NULL;
3978 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3979 tp->rx_std, tp->rx_std_mapping);
3983 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3984 tp->rx_jumbo, tp->rx_jumbo_mapping);
3985 tp->rx_jumbo = NULL;
3988 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3989 tp->rx_rcb, tp->rx_rcb_mapping);
3993 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3994 tp->tx_ring, tp->tx_desc_mapping);
3997 if (tp->hw_status) {
3998 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3999 tp->hw_status, tp->status_mapping);
4000 tp->hw_status = NULL;
4003 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4004 tp->hw_stats, tp->stats_mapping);
4005 tp->hw_stats = NULL;
4010 * Must not be invoked with interrupt sources disabled and
4011 * the hardware shutdown down. Can sleep.
4013 static int tg3_alloc_consistent(struct tg3 *tp)
4015 tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4017 TG3_RX_JUMBO_RING_SIZE)) +
4018 (sizeof(struct tx_ring_info) *
4021 if (!tp->rx_std_buffers)
4024 memset(tp->rx_std_buffers, 0,
4025 (sizeof(struct ring_info) *
4027 TG3_RX_JUMBO_RING_SIZE)) +
4028 (sizeof(struct tx_ring_info) *
4031 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4032 tp->tx_buffers = (struct tx_ring_info *)
4033 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4035 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4036 &tp->rx_std_mapping);
4040 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4041 &tp->rx_jumbo_mapping);
4046 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4047 &tp->rx_rcb_mapping);
4051 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4052 &tp->tx_desc_mapping);
4056 tp->hw_status = pci_alloc_consistent(tp->pdev,
4058 &tp->status_mapping);
4062 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4063 sizeof(struct tg3_hw_stats),
4064 &tp->stats_mapping);
4068 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4069 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4074 tg3_free_consistent(tp);
4078 #define MAX_WAIT_CNT 1000
4080 /* To stop a block, clear the enable bit and poll till it
4081 * clears. tp->lock is held.
4083 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4088 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4095 /* We can't enable/disable these bits of the
4096 * 5705/5750, just say success.
4109 for (i = 0; i < MAX_WAIT_CNT; i++) {
4112 if ((val & enable_bit) == 0)
4116 if (i == MAX_WAIT_CNT && !silent) {
4117 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4118 "ofs=%lx enable_bit=%x\n",
4126 /* tp->lock is held. */
4127 static int tg3_abort_hw(struct tg3 *tp, int silent)
4131 tg3_disable_ints(tp);
4133 tp->rx_mode &= ~RX_MODE_ENABLE;
4134 tw32_f(MAC_RX_MODE, tp->rx_mode);
4137 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4138 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4139 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4140 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4141 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4142 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4144 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4145 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4146 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4147 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4148 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4149 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4150 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4152 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4153 tw32_f(MAC_MODE, tp->mac_mode);
4156 tp->tx_mode &= ~TX_MODE_ENABLE;
4157 tw32_f(MAC_TX_MODE, tp->tx_mode);
4159 for (i = 0; i < MAX_WAIT_CNT; i++) {
4161 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4164 if (i >= MAX_WAIT_CNT) {
4165 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4166 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4167 tp->dev->name, tr32(MAC_TX_MODE));
4171 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4172 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4173 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4175 tw32(FTQ_RESET, 0xffffffff);
4176 tw32(FTQ_RESET, 0x00000000);
4178 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4179 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4182 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4184 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4189 /* tp->lock is held. */
4190 static int tg3_nvram_lock(struct tg3 *tp)
4192 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4195 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4196 for (i = 0; i < 8000; i++) {
4197 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4207 /* tp->lock is held. */
4208 static void tg3_nvram_unlock(struct tg3 *tp)
4210 if (tp->tg3_flags & TG3_FLAG_NVRAM)
4211 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4214 /* tp->lock is held. */
4215 static void tg3_enable_nvram_access(struct tg3 *tp)
4217 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4218 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4219 u32 nvaccess = tr32(NVRAM_ACCESS);
4221 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4225 /* tp->lock is held. */
4226 static void tg3_disable_nvram_access(struct tg3 *tp)
4228 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4229 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4230 u32 nvaccess = tr32(NVRAM_ACCESS);
4232 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4236 /* tp->lock is held. */
4237 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4239 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4240 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4241 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4243 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4245 case RESET_KIND_INIT:
4246 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4250 case RESET_KIND_SHUTDOWN:
4251 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4255 case RESET_KIND_SUSPEND:
4256 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4266 /* tp->lock is held. */
4267 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4269 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4271 case RESET_KIND_INIT:
4272 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4273 DRV_STATE_START_DONE);
4276 case RESET_KIND_SHUTDOWN:
4277 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4278 DRV_STATE_UNLOAD_DONE);
4287 /* tp->lock is held. */
4288 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4290 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4292 case RESET_KIND_INIT:
4293 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4297 case RESET_KIND_SHUTDOWN:
4298 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4302 case RESET_KIND_SUSPEND:
4303 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4313 static void tg3_stop_fw(struct tg3 *);
4315 /* tp->lock is held. */
4316 static int tg3_chip_reset(struct tg3 *tp)
4319 void (*write_op)(struct tg3 *, u32, u32);
4322 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4326 * We must avoid the readl() that normally takes place.
4327 * It locks machines, causes machine checks, and other
4328 * fun things. So, temporarily disable the 5701
4329 * hardware workaround, while we do the reset.
4331 write_op = tp->write32;
4332 if (write_op == tg3_write_flush_reg32)
4333 tp->write32 = tg3_write32;
4336 val = GRC_MISC_CFG_CORECLK_RESET;
4338 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4339 if (tr32(0x7e2c) == 0x60) {
4342 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4343 tw32(GRC_MISC_CFG, (1 << 29));
4348 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4349 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4350 tw32(GRC_MISC_CFG, val);
4352 /* restore 5701 hardware bug workaround write method */
4353 tp->write32 = write_op;
4355 /* Unfortunately, we have to delay before the PCI read back.
4356 * Some 575X chips even will not respond to a PCI cfg access
4357 * when the reset command is given to the chip.
4359 * How do these hardware designers expect things to work
4360 * properly if the PCI write is posted for a long period
4361 * of time? It is always necessary to have some method by
4362 * which a register read back can occur to push the write
4363 * out which does the reset.
4365 * For most tg3 variants the trick below was working.
4370 /* Flush PCI posted writes. The normal MMIO registers
4371 * are inaccessible at this time so this is the only
4372 * way to make this reliably (actually, this is no longer
4373 * the case, see above). I tried to use indirect
4374 * register read/write but this upset some 5701 variants.
4376 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4380 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4381 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4385 /* Wait for link training to complete. */
4386 for (i = 0; i < 5000; i++)
4389 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4390 pci_write_config_dword(tp->pdev, 0xc4,
4391 cfg_val | (1 << 15));
4393 /* Set PCIE max payload size and clear error status. */
4394 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4397 /* Re-enable indirect register accesses. */
4398 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4399 tp->misc_host_ctrl);
4401 /* Set MAX PCI retry to zero. */
4402 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4403 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4404 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4405 val |= PCISTATE_RETRY_SAME_DMA;
4406 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4408 pci_restore_state(tp->pdev);
4410 /* Make sure PCI-X relaxed ordering bit is clear. */
4411 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4412 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4413 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4415 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4418 /* Chip reset on 5780 will reset MSI enable bit,
4419 * so need to restore it.
4421 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4424 pci_read_config_word(tp->pdev,
4425 tp->msi_cap + PCI_MSI_FLAGS,
4427 pci_write_config_word(tp->pdev,
4428 tp->msi_cap + PCI_MSI_FLAGS,
4429 ctrl | PCI_MSI_FLAGS_ENABLE);
4430 val = tr32(MSGINT_MODE);
4431 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4434 val = tr32(MEMARB_MODE);
4435 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4438 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4440 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4442 tw32(0x5000, 0x400);
4445 tw32(GRC_MODE, tp->grc_mode);
4447 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4448 u32 val = tr32(0xc4);
4450 tw32(0xc4, val | (1 << 15));
4453 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4454 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4455 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4456 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4457 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4458 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4461 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4462 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4463 tw32_f(MAC_MODE, tp->mac_mode);
4464 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4465 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4466 tw32_f(MAC_MODE, tp->mac_mode);
4468 tw32_f(MAC_MODE, 0);
4471 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4472 /* Wait for firmware initialization to complete. */
4473 for (i = 0; i < 100000; i++) {
4474 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4475 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4480 printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4481 "firmware will not restart magic=%08x\n",
4482 tp->dev->name, val);
4487 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4488 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4489 u32 val = tr32(0x7c00);
4491 tw32(0x7c00, val | (1 << 25));
4494 /* Reprobe ASF enable state. */
4495 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4496 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4497 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4498 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4501 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4502 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4503 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4504 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4505 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4512 /* tp->lock is held. */
4513 static void tg3_stop_fw(struct tg3 *tp)
4515 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4519 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4520 val = tr32(GRC_RX_CPU_EVENT);
4522 tw32(GRC_RX_CPU_EVENT, val);
4524 /* Wait for RX cpu to ACK the event. */
4525 for (i = 0; i < 100; i++) {
4526 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4533 /* tp->lock is held. */
4534 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4540 tg3_write_sig_pre_reset(tp, kind);
4542 tg3_abort_hw(tp, silent);
4543 err = tg3_chip_reset(tp);
4545 tg3_write_sig_legacy(tp, kind);
4546 tg3_write_sig_post_reset(tp, kind);
4554 #define TG3_FW_RELEASE_MAJOR 0x0
4555 #define TG3_FW_RELASE_MINOR 0x0
4556 #define TG3_FW_RELEASE_FIX 0x0
4557 #define TG3_FW_START_ADDR 0x08000000
4558 #define TG3_FW_TEXT_ADDR 0x08000000
4559 #define TG3_FW_TEXT_LEN 0x9c0
4560 #define TG3_FW_RODATA_ADDR 0x080009c0
4561 #define TG3_FW_RODATA_LEN 0x60
4562 #define TG3_FW_DATA_ADDR 0x08000a40
4563 #define TG3_FW_DATA_LEN 0x20
4564 #define TG3_FW_SBSS_ADDR 0x08000a60
4565 #define TG3_FW_SBSS_LEN 0xc
4566 #define TG3_FW_BSS_ADDR 0x08000a70
4567 #define TG3_FW_BSS_LEN 0x10
4569 static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4570 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4571 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4572 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4573 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4574 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4575 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4576 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4577 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4578 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4579 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4580 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4581 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4582 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4583 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4584 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4585 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4586 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4587 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4588 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4589 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4590 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4591 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4592 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4596 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4597 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4598 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4599 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4600 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4601 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4602 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4603 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4604 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4605 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4606 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4607 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4608 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4609 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4610 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4611 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4612 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4613 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4614 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4615 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4616 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4617 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4618 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4619 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4620 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4621 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4622 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4623 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4624 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4625 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4626 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4627 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4628 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4629 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4630 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4631 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4632 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4633 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4634 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4635 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4636 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4637 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4638 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4639 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4640 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4641 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4642 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4643 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4644 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4645 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4646 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4647 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4648 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4649 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4650 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4651 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4652 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4653 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4654 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4655 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4656 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4657 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4658 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4659 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4660 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4663 static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4664 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4665 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4666 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4667 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4671 #if 0 /* All zeros, don't eat up space with it. */
4672 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4673 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4674 0x00000000, 0x00000000, 0x00000000, 0x00000000
4678 #define RX_CPU_SCRATCH_BASE 0x30000
4679 #define RX_CPU_SCRATCH_SIZE 0x04000
4680 #define TX_CPU_SCRATCH_BASE 0x34000
4681 #define TX_CPU_SCRATCH_SIZE 0x04000
4683 /* tp->lock is held. */
4684 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4688 if (offset == TX_CPU_BASE &&
4689 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4692 if (offset == RX_CPU_BASE) {
4693 for (i = 0; i < 10000; i++) {
4694 tw32(offset + CPU_STATE, 0xffffffff);
4695 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4696 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4700 tw32(offset + CPU_STATE, 0xffffffff);
4701 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
4704 for (i = 0; i < 10000; i++) {
4705 tw32(offset + CPU_STATE, 0xffffffff);
4706 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4707 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4713 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4716 (offset == RX_CPU_BASE ? "RX" : "TX"));
4723 unsigned int text_base;
4724 unsigned int text_len;
4726 unsigned int rodata_base;
4727 unsigned int rodata_len;
4729 unsigned int data_base;
4730 unsigned int data_len;
4734 /* tp->lock is held. */
4735 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4736 int cpu_scratch_size, struct fw_info *info)
4739 void (*write_op)(struct tg3 *, u32, u32);
4741 if (cpu_base == TX_CPU_BASE &&
4742 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4743 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4744 "TX cpu firmware on %s which is 5705.\n",
4749 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4750 write_op = tg3_write_mem;
4752 write_op = tg3_write_indirect_reg32;
4754 /* It is possible that bootcode is still loading at this point.
4755 * Get the nvram lock first before halting the cpu.
4758 err = tg3_halt_cpu(tp, cpu_base);
4759 tg3_nvram_unlock(tp);
4763 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4764 write_op(tp, cpu_scratch_base + i, 0);
4765 tw32(cpu_base + CPU_STATE, 0xffffffff);
4766 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4767 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4768 write_op(tp, (cpu_scratch_base +
4769 (info->text_base & 0xffff) +
4772 info->text_data[i] : 0));
4773 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4774 write_op(tp, (cpu_scratch_base +
4775 (info->rodata_base & 0xffff) +
4777 (info->rodata_data ?
4778 info->rodata_data[i] : 0));
4779 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4780 write_op(tp, (cpu_scratch_base +
4781 (info->data_base & 0xffff) +
4784 info->data_data[i] : 0));
4792 /* tp->lock is held. */
4793 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4795 struct fw_info info;
4798 info.text_base = TG3_FW_TEXT_ADDR;
4799 info.text_len = TG3_FW_TEXT_LEN;
4800 info.text_data = &tg3FwText[0];
4801 info.rodata_base = TG3_FW_RODATA_ADDR;
4802 info.rodata_len = TG3_FW_RODATA_LEN;
4803 info.rodata_data = &tg3FwRodata[0];
4804 info.data_base = TG3_FW_DATA_ADDR;
4805 info.data_len = TG3_FW_DATA_LEN;
4806 info.data_data = NULL;
4808 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4809 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4814 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4815 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4820 /* Now startup only the RX cpu. */
4821 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4822 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4824 for (i = 0; i < 5; i++) {
4825 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4827 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4828 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
4829 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4833 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4834 "to set RX CPU PC, is %08x should be %08x\n",
4835 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4839 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4840 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
4845 #if TG3_TSO_SUPPORT != 0
4847 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
4848 #define TG3_TSO_FW_RELASE_MINOR 0x6
4849 #define TG3_TSO_FW_RELEASE_FIX 0x0
4850 #define TG3_TSO_FW_START_ADDR 0x08000000
4851 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
4852 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
4853 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
4854 #define TG3_TSO_FW_RODATA_LEN 0x60
4855 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
4856 #define TG3_TSO_FW_DATA_LEN 0x30
4857 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
4858 #define TG3_TSO_FW_SBSS_LEN 0x2c
4859 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
4860 #define TG3_TSO_FW_BSS_LEN 0x894
4862 static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4863 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4864 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4865 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4866 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4867 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4868 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4869 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4870 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4871 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4872 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4873 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4874 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4875 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4876 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4877 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4878 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4879 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4880 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4881 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4882 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4883 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4884 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4885 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4886 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4887 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4888 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4889 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4890 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4891 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4892 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4893 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4894 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4895 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4896 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4897 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4898 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4899 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4900 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4901 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4902 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4903 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4904 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4905 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4906 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4907 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4908 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4909 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4910 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4911 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4912 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4913 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4914 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4915 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4916 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4917 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4918 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4919 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4920 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4921 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4922 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4923 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4924 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4925 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4926 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4927 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4928 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4929 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4930 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4931 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4932 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4933 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4934 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4935 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4936 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4937 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4938 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4939 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4940 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4941 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4942 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4943 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4944 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4945 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4946 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4947 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4948 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4949 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4950 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4951 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4952 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4953 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4954 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4955 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4956 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4957 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4958 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4959 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4960 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4961 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4962 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4963 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4964 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4965 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4966 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4967 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4968 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4969 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4970 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4971 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4972 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4973 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4974 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4975 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4976 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4977 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4978 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4979 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4980 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4981 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4982 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4983 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4984 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4985 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4986 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4987 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4988 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4989 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4990 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4991 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4992 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4993 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4994 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4995 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4996 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4997 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4998 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4999 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5000 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5001 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5002 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5003 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5004 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5005 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5006 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5007 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5008 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5009 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5010 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5011 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5012 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5013 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5014 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5015 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5016 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5017 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5018 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5019 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5020 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5021 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5022 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5023 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5024 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5025 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5026 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5027 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5028 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5029 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5030 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5031 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5032 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5033 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5034 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5035 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5036 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5037 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5038 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5039 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5040 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5041 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5042 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5043 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5044 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5045 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5046 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5047 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5048 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5049 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5050 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5051 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5052 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5053 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5054 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5055 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5056 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5057 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5058 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5059 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5060 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5061 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5062 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5063 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5064 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5065 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5066 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5067 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5068 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5069 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5070 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5071 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5072 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5073 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5074 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5075 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5076 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5077 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5078 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5079 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5080 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5081 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5082 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5083 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5084 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5085 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5086 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5087 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5088 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5089 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5090 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5091 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5092 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5093 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5094 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5095 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5096 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5097 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5098 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5099 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5100 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5101 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5102 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5103 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5104 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5105 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5106 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5107 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5108 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5109 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5110 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5111 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5112 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5113 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5114 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5115 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5116 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5117 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5118 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5119 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5120 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5121 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5122 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5123 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5124 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5125 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5126 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5127 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5128 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5129 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5130 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5131 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5132 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5133 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5134 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5135 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5136 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5137 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5138 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5139 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5140 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5141 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5142 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5143 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5144 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5145 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5146 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5149 static u32 tg3TsoFwRodata[] = {
5150 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5151 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5152 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5153 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5157 static u32 tg3TsoFwData[] = {
5158 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5159 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5163 /* 5705 needs a special version of the TSO firmware. */
5164 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5165 #define TG3_TSO5_FW_RELASE_MINOR 0x2
5166 #define TG3_TSO5_FW_RELEASE_FIX 0x0
5167 #define TG3_TSO5_FW_START_ADDR 0x00010000
5168 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5169 #define TG3_TSO5_FW_TEXT_LEN 0xe90
5170 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5171 #define TG3_TSO5_FW_RODATA_LEN 0x50
5172 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5173 #define TG3_TSO5_FW_DATA_LEN 0x20
5174 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5175 #define TG3_TSO5_FW_SBSS_LEN 0x28
5176 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5177 #define TG3_TSO5_FW_BSS_LEN 0x88
5179 static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5180 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5181 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5182 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5183 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5184 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5185 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5186 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5187 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5188 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5189 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5190 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5191 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5192 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5193 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5194 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5195 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5196 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5197 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5198 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5199 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5200 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5201 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5202 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5203 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5204 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5205 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5206 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5207 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5208 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5209 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5210 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5211 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5212 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5213 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5214 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5215 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5216 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5217 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5218 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5219 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5220 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5221 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5222 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5223 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5224 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5225 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5226 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5227 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5228 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5229 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5230 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5231 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5232 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5233 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5234 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5235 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5236 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5237 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5238 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5239 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5240 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5241 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5242 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5243 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5244 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5245 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5246 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5247 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5248 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5249 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5250 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5251 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5252 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5253 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5254 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5255 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5256 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5257 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5258 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5259 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5260 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5261 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5262 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5263 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5264 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5265 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5266 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5267 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5268 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5269 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5270 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5271 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5272 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5273 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5274 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5275 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5276 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5277 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5278 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5279 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5280 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5281 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5282 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5283 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5284 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5285 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5286 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5287 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5288 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5289 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5290 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5291 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5292 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5293 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5294 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5295 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5296 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5297 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5298 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5299 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5300 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5301 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5302 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5303 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5304 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5305 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5306 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5307 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5308 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5309 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5310 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5311 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5312 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5313 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5314 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5315 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5316 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5317 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5318 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5319 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5320 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5321 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5322 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5323 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5324 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5325 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5326 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5327 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5328 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5329 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5330 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5331 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5332 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5333 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5334 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5335 0x00000000, 0x00000000, 0x00000000,
5338 static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5339 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5340 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5341 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5342 0x00000000, 0x00000000, 0x00000000,
5345 static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5346 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5347 0x00000000, 0x00000000, 0x00000000,
5350 /* tp->lock is held. */
5351 static int tg3_load_tso_firmware(struct tg3 *tp)
5353 struct fw_info info;
5354 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5357 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5360 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5361 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5362 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5363 info.text_data = &tg3Tso5FwText[0];
5364 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5365 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5366 info.rodata_data = &tg3Tso5FwRodata[0];
5367 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5368 info.data_len = TG3_TSO5_FW_DATA_LEN;
5369 info.data_data = &tg3Tso5FwData[0];
5370 cpu_base = RX_CPU_BASE;
5371 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5372 cpu_scratch_size = (info.text_len +
5375 TG3_TSO5_FW_SBSS_LEN +
5376 TG3_TSO5_FW_BSS_LEN);
5378 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5379 info.text_len = TG3_TSO_FW_TEXT_LEN;
5380 info.text_data = &tg3TsoFwText[0];
5381 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5382 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5383 info.rodata_data = &tg3TsoFwRodata[0];
5384 info.data_base = TG3_TSO_FW_DATA_ADDR;
5385 info.data_len = TG3_TSO_FW_DATA_LEN;
5386 info.data_data = &tg3TsoFwData[0];
5387 cpu_base = TX_CPU_BASE;
5388 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5389 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5392 err = tg3_load_firmware_cpu(tp, cpu_base,
5393 cpu_scratch_base, cpu_scratch_size,
5398 /* Now startup the cpu. */
5399 tw32(cpu_base + CPU_STATE, 0xffffffff);
5400 tw32_f(cpu_base + CPU_PC, info.text_base);
5402 for (i = 0; i < 5; i++) {
5403 if (tr32(cpu_base + CPU_PC) == info.text_base)
5405 tw32(cpu_base + CPU_STATE, 0xffffffff);
5406 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5407 tw32_f(cpu_base + CPU_PC, info.text_base);
5411 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5412 "to set CPU PC, is %08x should be %08x\n",
5413 tp->dev->name, tr32(cpu_base + CPU_PC),
5417 tw32(cpu_base + CPU_STATE, 0xffffffff);
5418 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5422 #endif /* TG3_TSO_SUPPORT != 0 */
5424 /* tp->lock is held. */
5425 static void __tg3_set_mac_addr(struct tg3 *tp)
5427 u32 addr_high, addr_low;
5430 addr_high = ((tp->dev->dev_addr[0] << 8) |
5431 tp->dev->dev_addr[1]);
5432 addr_low = ((tp->dev->dev_addr[2] << 24) |
5433 (tp->dev->dev_addr[3] << 16) |
5434 (tp->dev->dev_addr[4] << 8) |
5435 (tp->dev->dev_addr[5] << 0));
5436 for (i = 0; i < 4; i++) {
5437 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5438 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5441 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5442 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5443 for (i = 0; i < 12; i++) {
5444 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5445 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5449 addr_high = (tp->dev->dev_addr[0] +
5450 tp->dev->dev_addr[1] +
5451 tp->dev->dev_addr[2] +
5452 tp->dev->dev_addr[3] +
5453 tp->dev->dev_addr[4] +
5454 tp->dev->dev_addr[5]) &
5455 TX_BACKOFF_SEED_MASK;
5456 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5459 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5461 struct tg3 *tp = netdev_priv(dev);
5462 struct sockaddr *addr = p;
5464 if (!is_valid_ether_addr(addr->sa_data))
5467 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5469 spin_lock_bh(&tp->lock);
5470 __tg3_set_mac_addr(tp);
5471 spin_unlock_bh(&tp->lock);
5476 /* tp->lock is held. */
5477 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5478 dma_addr_t mapping, u32 maxlen_flags,
5482 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5483 ((u64) mapping >> 32));
5485 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5486 ((u64) mapping & 0xffffffff));
5488 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5491 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5493 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5497 static void __tg3_set_rx_mode(struct net_device *);
5498 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5500 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5501 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5502 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5503 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5504 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5505 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5506 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5508 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5509 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5510 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5511 u32 val = ec->stats_block_coalesce_usecs;
5513 if (!netif_carrier_ok(tp->dev))
5516 tw32(HOSTCC_STAT_COAL_TICKS, val);
5520 /* tp->lock is held. */
5521 static int tg3_reset_hw(struct tg3 *tp)
5523 u32 val, rdmac_mode;
5526 tg3_disable_ints(tp);
5530 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5532 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5533 tg3_abort_hw(tp, 1);
5536 err = tg3_chip_reset(tp);
5540 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5542 /* This works around an issue with Athlon chipsets on
5543 * B3 tigon3 silicon. This bit has no effect on any
5544 * other revision. But do not set this on PCI Express
5547 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5548 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5549 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5551 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5552 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5553 val = tr32(TG3PCI_PCISTATE);
5554 val |= PCISTATE_RETRY_SAME_DMA;
5555 tw32(TG3PCI_PCISTATE, val);
5558 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5559 /* Enable some hw fixes. */
5560 val = tr32(TG3PCI_MSI_DATA);
5561 val |= (1 << 26) | (1 << 28) | (1 << 29);
5562 tw32(TG3PCI_MSI_DATA, val);
5565 /* Descriptor ring init may make accesses to the
5566 * NIC SRAM area to setup the TX descriptors, so we
5567 * can only do this after the hardware has been
5568 * successfully reset.
5572 /* This value is determined during the probe time DMA
5573 * engine test, tg3_test_dma.
5575 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5577 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5578 GRC_MODE_4X_NIC_SEND_RINGS |
5579 GRC_MODE_NO_TX_PHDR_CSUM |
5580 GRC_MODE_NO_RX_PHDR_CSUM);
5581 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5582 if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5583 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5584 if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5585 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5589 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5591 /* Setup the timer prescalar register. Clock is always 66Mhz. */
5592 val = tr32(GRC_MISC_CFG);
5594 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5595 tw32(GRC_MISC_CFG, val);
5597 /* Initialize MBUF/DESC pool. */
5598 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5600 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5601 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5602 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5603 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5605 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5606 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5607 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5609 #if TG3_TSO_SUPPORT != 0
5610 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5613 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5614 TG3_TSO5_FW_RODATA_LEN +
5615 TG3_TSO5_FW_DATA_LEN +
5616 TG3_TSO5_FW_SBSS_LEN +
5617 TG3_TSO5_FW_BSS_LEN);
5618 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5619 tw32(BUFMGR_MB_POOL_ADDR,
5620 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5621 tw32(BUFMGR_MB_POOL_SIZE,
5622 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5626 if (tp->dev->mtu <= ETH_DATA_LEN) {
5627 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5628 tp->bufmgr_config.mbuf_read_dma_low_water);
5629 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5630 tp->bufmgr_config.mbuf_mac_rx_low_water);
5631 tw32(BUFMGR_MB_HIGH_WATER,
5632 tp->bufmgr_config.mbuf_high_water);
5634 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5635 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5636 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5637 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5638 tw32(BUFMGR_MB_HIGH_WATER,
5639 tp->bufmgr_config.mbuf_high_water_jumbo);
5641 tw32(BUFMGR_DMA_LOW_WATER,
5642 tp->bufmgr_config.dma_low_water);
5643 tw32(BUFMGR_DMA_HIGH_WATER,
5644 tp->bufmgr_config.dma_high_water);
5646 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5647 for (i = 0; i < 2000; i++) {
5648 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5653 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5658 /* Setup replenish threshold. */
5659 tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5661 /* Initialize TG3_BDINFO's at:
5662 * RCVDBDI_STD_BD: standard eth size rx ring
5663 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
5664 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
5667 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
5668 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
5669 * ring attribute flags
5670 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
5672 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5673 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5675 * The size of each ring is fixed in the firmware, but the location is
5678 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5679 ((u64) tp->rx_std_mapping >> 32));
5680 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5681 ((u64) tp->rx_std_mapping & 0xffffffff));
5682 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5683 NIC_SRAM_RX_BUFFER_DESC);
5685 /* Don't even try to program the JUMBO/MINI buffer descriptor
5688 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5689 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5690 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5692 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5693 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5695 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5696 BDINFO_FLAGS_DISABLED);
5698 /* Setup replenish threshold. */
5699 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5701 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5702 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5703 ((u64) tp->rx_jumbo_mapping >> 32));
5704 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5705 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5706 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5707 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5708 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5709 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5711 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5712 BDINFO_FLAGS_DISABLED);
5717 /* There is only one send ring on 5705/5750, no need to explicitly
5718 * disable the others.
5720 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5721 /* Clear out send RCB ring in SRAM. */
5722 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5723 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5724 BDINFO_FLAGS_DISABLED);
5729 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5730 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5732 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5733 tp->tx_desc_mapping,
5734 (TG3_TX_RING_SIZE <<
5735 BDINFO_FLAGS_MAXLEN_SHIFT),
5736 NIC_SRAM_TX_BUFFER_DESC);
5738 /* There is only one receive return ring on 5705/5750, no need
5739 * to explicitly disable the others.
5741 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5742 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5743 i += TG3_BDINFO_SIZE) {
5744 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5745 BDINFO_FLAGS_DISABLED);
5750 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5752 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5754 (TG3_RX_RCB_RING_SIZE(tp) <<
5755 BDINFO_FLAGS_MAXLEN_SHIFT),
5758 tp->rx_std_ptr = tp->rx_pending;
5759 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5762 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
5763 tp->rx_jumbo_pending : 0;
5764 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5767 /* Initialize MAC address and backoff seed. */
5768 __tg3_set_mac_addr(tp);
5770 /* MTU + ethernet header + FCS + optional VLAN tag */
5771 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5773 /* The slot time is changed by tg3_setup_phy if we
5774 * run at gigabit with half duplex.
5776 tw32(MAC_TX_LENGTHS,
5777 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5778 (6 << TX_LENGTHS_IPG_SHIFT) |
5779 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5781 /* Receive rules. */
5782 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5783 tw32(RCVLPC_CONFIG, 0x0181);
5785 /* Calculate RDMAC_MODE setting early, we need it to determine
5786 * the RCVLPC_STATE_ENABLE mask.
5788 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5789 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5790 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5791 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5792 RDMAC_MODE_LNGREAD_ENAB);
5793 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5794 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
5796 /* If statement applies to 5705 and 5750 PCI devices only */
5797 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5798 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5799 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
5800 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5801 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5802 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5803 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5804 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5805 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5806 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5810 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5811 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5813 #if TG3_TSO_SUPPORT != 0
5814 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5815 rdmac_mode |= (1 << 27);
5818 /* Receive/send statistics. */
5819 if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5820 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5821 val = tr32(RCVLPC_STATS_ENABLE);
5822 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5823 tw32(RCVLPC_STATS_ENABLE, val);
5825 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5827 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5828 tw32(SNDDATAI_STATSENAB, 0xffffff);
5829 tw32(SNDDATAI_STATSCTRL,
5830 (SNDDATAI_SCTRL_ENABLE |
5831 SNDDATAI_SCTRL_FASTUPD));
5833 /* Setup host coalescing engine. */
5834 tw32(HOSTCC_MODE, 0);
5835 for (i = 0; i < 2000; i++) {
5836 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5841 __tg3_set_coalesce(tp, &tp->coal);
5843 /* set status block DMA address */
5844 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5845 ((u64) tp->status_mapping >> 32));
5846 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5847 ((u64) tp->status_mapping & 0xffffffff));
5849 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5850 /* Status/statistics block address. See tg3_timer,
5851 * the tg3_periodic_fetch_stats call there, and
5852 * tg3_get_stats to see how this works for 5705/5750 chips.
5854 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5855 ((u64) tp->stats_mapping >> 32));
5856 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5857 ((u64) tp->stats_mapping & 0xffffffff));
5858 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5859 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5862 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5864 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5865 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5866 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5867 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5869 /* Clear statistics/status block in chip, and status block in ram. */
5870 for (i = NIC_SRAM_STATS_BLK;
5871 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5873 tg3_write_mem(tp, i, 0);
5876 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5878 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5879 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
5880 /* reset to prevent losing 1st rx packet intermittently */
5881 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5885 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5886 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5887 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5890 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5891 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5892 * register to preserve the GPIO settings for LOMs. The GPIOs,
5893 * whether used as inputs or outputs, are set by boot code after
5896 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5899 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5900 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
5902 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5903 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5904 GRC_LCLCTRL_GPIO_OUTPUT3;
5906 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5908 /* GPIO1 must be driven high for eeprom write protect */
5909 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5910 GRC_LCLCTRL_GPIO_OUTPUT1);
5912 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5915 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
5918 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5919 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5923 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5924 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5925 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5926 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5927 WDMAC_MODE_LNGREAD_ENAB);
5929 /* If statement applies to 5705 and 5750 PCI devices only */
5930 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5931 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5932 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
5933 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5934 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5935 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5937 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5938 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5939 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5940 val |= WDMAC_MODE_RX_ACCEL;
5944 tw32_f(WDMAC_MODE, val);
5947 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5948 val = tr32(TG3PCI_X_CAPS);
5949 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5950 val &= ~PCIX_CAPS_BURST_MASK;
5951 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5952 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5953 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5954 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5955 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5956 val |= (tp->split_mode_max_reqs <<
5957 PCIX_CAPS_SPLIT_SHIFT);
5959 tw32(TG3PCI_X_CAPS, val);
5962 tw32_f(RDMAC_MODE, rdmac_mode);
5965 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5966 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5967 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5968 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5969 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5970 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5971 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5972 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5973 #if TG3_TSO_SUPPORT != 0
5974 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5975 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5977 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5978 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5980 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5981 err = tg3_load_5701_a0_firmware_fix(tp);
5986 #if TG3_TSO_SUPPORT != 0
5987 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5988 err = tg3_load_tso_firmware(tp);
5994 tp->tx_mode = TX_MODE_ENABLE;
5995 tw32_f(MAC_TX_MODE, tp->tx_mode);
5998 tp->rx_mode = RX_MODE_ENABLE;
5999 tw32_f(MAC_RX_MODE, tp->rx_mode);
6002 if (tp->link_config.phy_is_low_power) {
6003 tp->link_config.phy_is_low_power = 0;
6004 tp->link_config.speed = tp->link_config.orig_speed;
6005 tp->link_config.duplex = tp->link_config.orig_duplex;
6006 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6009 tp->mi_mode = MAC_MI_MODE_BASE;
6010 tw32_f(MAC_MI_MODE, tp->mi_mode);
6013 tw32(MAC_LED_CTRL, tp->led_ctrl);
6015 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6016 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6017 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6020 tw32_f(MAC_RX_MODE, tp->rx_mode);
6023 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6024 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6025 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6026 /* Set drive transmission level to 1.2V */
6027 /* only if the signal pre-emphasis bit is not set */
6028 val = tr32(MAC_SERDES_CFG);
6031 tw32(MAC_SERDES_CFG, val);
6033 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6034 tw32(MAC_SERDES_CFG, 0x616000);
6037 /* Prevent chip from dropping frames when flow control
6040 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6043 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6044 /* Use hardware link auto-negotiation */
6045 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6048 err = tg3_setup_phy(tp, 1);
6052 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6055 /* Clear CRC stats. */
6056 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6057 tg3_writephy(tp, 0x1e, tmp | 0x8000);
6058 tg3_readphy(tp, 0x14, &tmp);
6062 __tg3_set_rx_mode(tp->dev);
6064 /* Initialize receive rules. */
6065 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6066 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6067 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6068 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6070 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6071 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6075 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6079 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6081 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6083 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6085 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6087 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6089 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6091 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6093 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6095 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6097 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6099 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6101 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6103 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6105 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6113 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6118 /* Called at device open time to get the chip ready for
6119 * packet processing. Invoked with tp->lock held.
6121 static int tg3_init_hw(struct tg3 *tp)
6125 /* Force the chip into D0. */
6126 err = tg3_set_power_state(tp, 0);
6130 tg3_switch_clocks(tp);
6132 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6134 err = tg3_reset_hw(tp);
6140 #define TG3_STAT_ADD32(PSTAT, REG) \
6141 do { u32 __val = tr32(REG); \
6142 (PSTAT)->low += __val; \
6143 if ((PSTAT)->low < __val) \
6144 (PSTAT)->high += 1; \
6147 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6149 struct tg3_hw_stats *sp = tp->hw_stats;
6151 if (!netif_carrier_ok(tp->dev))
6154 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6155 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6156 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6157 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6158 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6159 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6160 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6161 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6162 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6163 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6164 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6165 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6166 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6168 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6169 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6170 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6171 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6172 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6173 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6174 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6175 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6176 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6177 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6178 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6179 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6180 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6181 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6184 static void tg3_timer(unsigned long __opaque)
6186 struct tg3 *tp = (struct tg3 *) __opaque;
6188 spin_lock(&tp->lock);
6190 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6191 /* All of this garbage is because when using non-tagged
6192 * IRQ status the mailbox/status_block protocol the chip
6193 * uses with the cpu is race prone.
6195 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6196 tw32(GRC_LOCAL_CTRL,
6197 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6199 tw32(HOSTCC_MODE, tp->coalesce_mode |
6200 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6203 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6204 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6205 spin_unlock(&tp->lock);
6206 schedule_work(&tp->reset_task);
6211 /* This part only runs once per second. */
6212 if (!--tp->timer_counter) {
6213 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6214 tg3_periodic_fetch_stats(tp);
6216 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6220 mac_stat = tr32(MAC_STATUS);
6223 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6224 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6226 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6230 tg3_setup_phy(tp, 0);
6231 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6232 u32 mac_stat = tr32(MAC_STATUS);
6235 if (netif_carrier_ok(tp->dev) &&
6236 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6239 if (! netif_carrier_ok(tp->dev) &&
6240 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6241 MAC_STATUS_SIGNAL_DET))) {
6247 ~MAC_MODE_PORT_MODE_MASK));
6249 tw32_f(MAC_MODE, tp->mac_mode);
6251 tg3_setup_phy(tp, 0);
6253 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6254 tg3_serdes_parallel_detect(tp);
6256 tp->timer_counter = tp->timer_multiplier;
6259 /* Heartbeat is only sent once every 2 seconds. */
6260 if (!--tp->asf_counter) {
6261 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6264 tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_MBOX,
6265 FWCMD_NICDRV_ALIVE2);
6266 tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6267 /* 5 seconds timeout */
6268 tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6269 val = tr32(GRC_RX_CPU_EVENT);
6271 tw32(GRC_RX_CPU_EVENT, val);
6273 tp->asf_counter = tp->asf_multiplier;
6276 spin_unlock(&tp->lock);
6278 tp->timer.expires = jiffies + tp->timer_offset;
6279 add_timer(&tp->timer);
6282 static int tg3_test_interrupt(struct tg3 *tp)
6284 struct net_device *dev = tp->dev;
6288 if (!netif_running(dev))
6291 tg3_disable_ints(tp);
6293 free_irq(tp->pdev->irq, dev);
6295 err = request_irq(tp->pdev->irq, tg3_test_isr,
6296 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6300 tp->hw_status->status &= ~SD_STATUS_UPDATED;
6301 tg3_enable_ints(tp);
6303 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6306 for (i = 0; i < 5; i++) {
6307 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6314 tg3_disable_ints(tp);
6316 free_irq(tp->pdev->irq, dev);
6318 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6319 err = request_irq(tp->pdev->irq, tg3_msi,
6320 SA_SAMPLE_RANDOM, dev->name, dev);
6322 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6323 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6324 fn = tg3_interrupt_tagged;
6325 err = request_irq(tp->pdev->irq, fn,
6326 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6338 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6339 * successfully restored
6341 static int tg3_test_msi(struct tg3 *tp)
6343 struct net_device *dev = tp->dev;
6347 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6350 /* Turn off SERR reporting in case MSI terminates with Master
6353 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6354 pci_write_config_word(tp->pdev, PCI_COMMAND,
6355 pci_cmd & ~PCI_COMMAND_SERR);
6357 err = tg3_test_interrupt(tp);
6359 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6364 /* other failures */
6368 /* MSI test failed, go back to INTx mode */
6369 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6370 "switching to INTx mode. Please report this failure to "
6371 "the PCI maintainer and include system chipset information.\n",
6374 free_irq(tp->pdev->irq, dev);
6375 pci_disable_msi(tp->pdev);
6377 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6380 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6381 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6382 fn = tg3_interrupt_tagged;
6384 err = request_irq(tp->pdev->irq, fn,
6385 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6390 /* Need to reset the chip because the MSI cycle may have terminated
6391 * with Master Abort.
6393 tg3_full_lock(tp, 1);
6395 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6396 err = tg3_init_hw(tp);
6398 tg3_full_unlock(tp);
6401 free_irq(tp->pdev->irq, dev);
6406 static int tg3_open(struct net_device *dev)
6408 struct tg3 *tp = netdev_priv(dev);
6411 tg3_full_lock(tp, 0);
6413 tg3_disable_ints(tp);
6414 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6416 tg3_full_unlock(tp);
6418 /* The placement of this call is tied
6419 * to the setup and use of Host TX descriptors.
6421 err = tg3_alloc_consistent(tp);
6425 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6426 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6427 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
6428 /* All MSI supporting chips should support tagged
6429 * status. Assert that this is the case.
6431 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6432 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6433 "Not using MSI.\n", tp->dev->name);
6434 } else if (pci_enable_msi(tp->pdev) == 0) {
6437 msi_mode = tr32(MSGINT_MODE);
6438 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6439 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6442 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6443 err = request_irq(tp->pdev->irq, tg3_msi,
6444 SA_SAMPLE_RANDOM, dev->name, dev);
6446 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6447 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6448 fn = tg3_interrupt_tagged;
6450 err = request_irq(tp->pdev->irq, fn,
6451 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6455 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6456 pci_disable_msi(tp->pdev);
6457 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6459 tg3_free_consistent(tp);
6463 tg3_full_lock(tp, 0);
6465 err = tg3_init_hw(tp);
6467 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6470 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6471 tp->timer_offset = HZ;
6473 tp->timer_offset = HZ / 10;
6475 BUG_ON(tp->timer_offset > HZ);
6476 tp->timer_counter = tp->timer_multiplier =
6477 (HZ / tp->timer_offset);
6478 tp->asf_counter = tp->asf_multiplier =
6479 ((HZ / tp->timer_offset) * 2);
6481 init_timer(&tp->timer);
6482 tp->timer.expires = jiffies + tp->timer_offset;
6483 tp->timer.data = (unsigned long) tp;
6484 tp->timer.function = tg3_timer;
6487 tg3_full_unlock(tp);
6490 free_irq(tp->pdev->irq, dev);
6491 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6492 pci_disable_msi(tp->pdev);
6493 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6495 tg3_free_consistent(tp);
6499 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6500 err = tg3_test_msi(tp);
6503 tg3_full_lock(tp, 0);
6505 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6506 pci_disable_msi(tp->pdev);
6507 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6509 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6511 tg3_free_consistent(tp);
6513 tg3_full_unlock(tp);
6519 tg3_full_lock(tp, 0);
6521 add_timer(&tp->timer);
6522 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
6523 tg3_enable_ints(tp);
6525 tg3_full_unlock(tp);
6527 netif_start_queue(dev);
6533 /*static*/ void tg3_dump_state(struct tg3 *tp)
6535 u32 val32, val32_2, val32_3, val32_4, val32_5;
6539 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6540 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6541 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6545 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6546 tr32(MAC_MODE), tr32(MAC_STATUS));
6547 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6548 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6549 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6550 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6551 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6552 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6554 /* Send data initiator control block */
6555 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6556 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6557 printk(" SNDDATAI_STATSCTRL[%08x]\n",
6558 tr32(SNDDATAI_STATSCTRL));
6560 /* Send data completion control block */
6561 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6563 /* Send BD ring selector block */
6564 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6565 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6567 /* Send BD initiator control block */
6568 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6569 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6571 /* Send BD completion control block */
6572 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6574 /* Receive list placement control block */
6575 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6576 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6577 printk(" RCVLPC_STATSCTRL[%08x]\n",
6578 tr32(RCVLPC_STATSCTRL));
6580 /* Receive data and receive BD initiator control block */
6581 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6582 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6584 /* Receive data completion control block */
6585 printk("DEBUG: RCVDCC_MODE[%08x]\n",
6588 /* Receive BD initiator control block */
6589 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6590 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6592 /* Receive BD completion control block */
6593 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6594 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6596 /* Receive list selector control block */
6597 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6598 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6600 /* Mbuf cluster free block */
6601 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6602 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6604 /* Host coalescing control block */
6605 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6606 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6607 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6608 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6609 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6610 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6611 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6612 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6613 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6614 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6615 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6616 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6618 /* Memory arbiter control block */
6619 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6620 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6622 /* Buffer manager control block */
6623 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6624 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6625 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6626 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6627 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6628 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6629 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6630 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6632 /* Read DMA control block */
6633 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6634 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6636 /* Write DMA control block */
6637 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6638 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6640 /* DMA completion block */
6641 printk("DEBUG: DMAC_MODE[%08x]\n",
6645 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6646 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6647 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6648 tr32(GRC_LOCAL_CTRL));
6651 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6652 tr32(RCVDBDI_JUMBO_BD + 0x0),
6653 tr32(RCVDBDI_JUMBO_BD + 0x4),
6654 tr32(RCVDBDI_JUMBO_BD + 0x8),
6655 tr32(RCVDBDI_JUMBO_BD + 0xc));
6656 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6657 tr32(RCVDBDI_STD_BD + 0x0),
6658 tr32(RCVDBDI_STD_BD + 0x4),
6659 tr32(RCVDBDI_STD_BD + 0x8),
6660 tr32(RCVDBDI_STD_BD + 0xc));
6661 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6662 tr32(RCVDBDI_MINI_BD + 0x0),
6663 tr32(RCVDBDI_MINI_BD + 0x4),
6664 tr32(RCVDBDI_MINI_BD + 0x8),
6665 tr32(RCVDBDI_MINI_BD + 0xc));
6667 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6668 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6669 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6670 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6671 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6672 val32, val32_2, val32_3, val32_4);
6674 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6675 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6676 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6677 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6678 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6679 val32, val32_2, val32_3, val32_4);
6681 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6682 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6683 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6684 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6685 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6686 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6687 val32, val32_2, val32_3, val32_4, val32_5);
6689 /* SW status block */
6690 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6691 tp->hw_status->status,
6692 tp->hw_status->status_tag,
6693 tp->hw_status->rx_jumbo_consumer,
6694 tp->hw_status->rx_consumer,
6695 tp->hw_status->rx_mini_consumer,
6696 tp->hw_status->idx[0].rx_producer,
6697 tp->hw_status->idx[0].tx_consumer);
6699 /* SW statistics block */
6700 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6701 ((u32 *)tp->hw_stats)[0],
6702 ((u32 *)tp->hw_stats)[1],
6703 ((u32 *)tp->hw_stats)[2],
6704 ((u32 *)tp->hw_stats)[3]);
6707 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
6708 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6709 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6710 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6711 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
6713 /* NIC side send descriptors. */
6714 for (i = 0; i < 6; i++) {
6717 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6718 + (i * sizeof(struct tg3_tx_buffer_desc));
6719 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6721 readl(txd + 0x0), readl(txd + 0x4),
6722 readl(txd + 0x8), readl(txd + 0xc));
6725 /* NIC side RX descriptors. */
6726 for (i = 0; i < 6; i++) {
6729 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6730 + (i * sizeof(struct tg3_rx_buffer_desc));
6731 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6733 readl(rxd + 0x0), readl(rxd + 0x4),
6734 readl(rxd + 0x8), readl(rxd + 0xc));
6735 rxd += (4 * sizeof(u32));
6736 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6738 readl(rxd + 0x0), readl(rxd + 0x4),
6739 readl(rxd + 0x8), readl(rxd + 0xc));
6742 for (i = 0; i < 6; i++) {
6745 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6746 + (i * sizeof(struct tg3_rx_buffer_desc));
6747 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6749 readl(rxd + 0x0), readl(rxd + 0x4),
6750 readl(rxd + 0x8), readl(rxd + 0xc));
6751 rxd += (4 * sizeof(u32));
6752 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6754 readl(rxd + 0x0), readl(rxd + 0x4),
6755 readl(rxd + 0x8), readl(rxd + 0xc));
6760 static struct net_device_stats *tg3_get_stats(struct net_device *);
6761 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6763 static int tg3_close(struct net_device *dev)
6765 struct tg3 *tp = netdev_priv(dev);
6767 netif_stop_queue(dev);
6769 del_timer_sync(&tp->timer);
6771 tg3_full_lock(tp, 1);
6776 tg3_disable_ints(tp);
6778 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6781 ~(TG3_FLAG_INIT_COMPLETE |
6782 TG3_FLAG_GOT_SERDES_FLOWCTL);
6783 netif_carrier_off(tp->dev);
6785 tg3_full_unlock(tp);
6787 free_irq(tp->pdev->irq, dev);
6788 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6789 pci_disable_msi(tp->pdev);
6790 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6793 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6794 sizeof(tp->net_stats_prev));
6795 memcpy(&tp->estats_prev, tg3_get_estats(tp),
6796 sizeof(tp->estats_prev));
6798 tg3_free_consistent(tp);
6803 static inline unsigned long get_stat64(tg3_stat64_t *val)
6807 #if (BITS_PER_LONG == 32)
6810 ret = ((u64)val->high << 32) | ((u64)val->low);
6815 static unsigned long calc_crc_errors(struct tg3 *tp)
6817 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6819 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6820 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6821 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6824 spin_lock_bh(&tp->lock);
6825 if (!tg3_readphy(tp, 0x1e, &val)) {
6826 tg3_writephy(tp, 0x1e, val | 0x8000);
6827 tg3_readphy(tp, 0x14, &val);
6830 spin_unlock_bh(&tp->lock);
6832 tp->phy_crc_errors += val;
6834 return tp->phy_crc_errors;
6837 return get_stat64(&hw_stats->rx_fcs_errors);
6840 #define ESTAT_ADD(member) \
6841 estats->member = old_estats->member + \
6842 get_stat64(&hw_stats->member)
6844 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6846 struct tg3_ethtool_stats *estats = &tp->estats;
6847 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6848 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6853 ESTAT_ADD(rx_octets);
6854 ESTAT_ADD(rx_fragments);
6855 ESTAT_ADD(rx_ucast_packets);
6856 ESTAT_ADD(rx_mcast_packets);
6857 ESTAT_ADD(rx_bcast_packets);
6858 ESTAT_ADD(rx_fcs_errors);
6859 ESTAT_ADD(rx_align_errors);
6860 ESTAT_ADD(rx_xon_pause_rcvd);
6861 ESTAT_ADD(rx_xoff_pause_rcvd);
6862 ESTAT_ADD(rx_mac_ctrl_rcvd);
6863 ESTAT_ADD(rx_xoff_entered);
6864 ESTAT_ADD(rx_frame_too_long_errors);
6865 ESTAT_ADD(rx_jabbers);
6866 ESTAT_ADD(rx_undersize_packets);
6867 ESTAT_ADD(rx_in_length_errors);
6868 ESTAT_ADD(rx_out_length_errors);
6869 ESTAT_ADD(rx_64_or_less_octet_packets);
6870 ESTAT_ADD(rx_65_to_127_octet_packets);
6871 ESTAT_ADD(rx_128_to_255_octet_packets);
6872 ESTAT_ADD(rx_256_to_511_octet_packets);
6873 ESTAT_ADD(rx_512_to_1023_octet_packets);
6874 ESTAT_ADD(rx_1024_to_1522_octet_packets);
6875 ESTAT_ADD(rx_1523_to_2047_octet_packets);
6876 ESTAT_ADD(rx_2048_to_4095_octet_packets);
6877 ESTAT_ADD(rx_4096_to_8191_octet_packets);
6878 ESTAT_ADD(rx_8192_to_9022_octet_packets);
6880 ESTAT_ADD(tx_octets);
6881 ESTAT_ADD(tx_collisions);
6882 ESTAT_ADD(tx_xon_sent);
6883 ESTAT_ADD(tx_xoff_sent);
6884 ESTAT_ADD(tx_flow_control);
6885 ESTAT_ADD(tx_mac_errors);
6886 ESTAT_ADD(tx_single_collisions);
6887 ESTAT_ADD(tx_mult_collisions);
6888 ESTAT_ADD(tx_deferred);
6889 ESTAT_ADD(tx_excessive_collisions);
6890 ESTAT_ADD(tx_late_collisions);
6891 ESTAT_ADD(tx_collide_2times);
6892 ESTAT_ADD(tx_collide_3times);
6893 ESTAT_ADD(tx_collide_4times);
6894 ESTAT_ADD(tx_collide_5times);
6895 ESTAT_ADD(tx_collide_6times);
6896 ESTAT_ADD(tx_collide_7times);
6897 ESTAT_ADD(tx_collide_8times);
6898 ESTAT_ADD(tx_collide_9times);
6899 ESTAT_ADD(tx_collide_10times);
6900 ESTAT_ADD(tx_collide_11times);
6901 ESTAT_ADD(tx_collide_12times);
6902 ESTAT_ADD(tx_collide_13times);
6903 ESTAT_ADD(tx_collide_14times);
6904 ESTAT_ADD(tx_collide_15times);
6905 ESTAT_ADD(tx_ucast_packets);
6906 ESTAT_ADD(tx_mcast_packets);
6907 ESTAT_ADD(tx_bcast_packets);
6908 ESTAT_ADD(tx_carrier_sense_errors);
6909 ESTAT_ADD(tx_discards);
6910 ESTAT_ADD(tx_errors);
6912 ESTAT_ADD(dma_writeq_full);
6913 ESTAT_ADD(dma_write_prioq_full);
6914 ESTAT_ADD(rxbds_empty);
6915 ESTAT_ADD(rx_discards);
6916 ESTAT_ADD(rx_errors);
6917 ESTAT_ADD(rx_threshold_hit);
6919 ESTAT_ADD(dma_readq_full);
6920 ESTAT_ADD(dma_read_prioq_full);
6921 ESTAT_ADD(tx_comp_queue_full);
6923 ESTAT_ADD(ring_set_send_prod_index);
6924 ESTAT_ADD(ring_status_update);
6925 ESTAT_ADD(nic_irqs);
6926 ESTAT_ADD(nic_avoided_irqs);
6927 ESTAT_ADD(nic_tx_threshold_hit);
6932 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6934 struct tg3 *tp = netdev_priv(dev);
6935 struct net_device_stats *stats = &tp->net_stats;
6936 struct net_device_stats *old_stats = &tp->net_stats_prev;
6937 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6942 stats->rx_packets = old_stats->rx_packets +
6943 get_stat64(&hw_stats->rx_ucast_packets) +
6944 get_stat64(&hw_stats->rx_mcast_packets) +
6945 get_stat64(&hw_stats->rx_bcast_packets);
6947 stats->tx_packets = old_stats->tx_packets +
6948 get_stat64(&hw_stats->tx_ucast_packets) +
6949 get_stat64(&hw_stats->tx_mcast_packets) +
6950 get_stat64(&hw_stats->tx_bcast_packets);
6952 stats->rx_bytes = old_stats->rx_bytes +
6953 get_stat64(&hw_stats->rx_octets);
6954 stats->tx_bytes = old_stats->tx_bytes +
6955 get_stat64(&hw_stats->tx_octets);
6957 stats->rx_errors = old_stats->rx_errors +
6958 get_stat64(&hw_stats->rx_errors);
6959 stats->tx_errors = old_stats->tx_errors +
6960 get_stat64(&hw_stats->tx_errors) +
6961 get_stat64(&hw_stats->tx_mac_errors) +
6962 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6963 get_stat64(&hw_stats->tx_discards);
6965 stats->multicast = old_stats->multicast +
6966 get_stat64(&hw_stats->rx_mcast_packets);
6967 stats->collisions = old_stats->collisions +
6968 get_stat64(&hw_stats->tx_collisions);
6970 stats->rx_length_errors = old_stats->rx_length_errors +
6971 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6972 get_stat64(&hw_stats->rx_undersize_packets);
6974 stats->rx_over_errors = old_stats->rx_over_errors +
6975 get_stat64(&hw_stats->rxbds_empty);
6976 stats->rx_frame_errors = old_stats->rx_frame_errors +
6977 get_stat64(&hw_stats->rx_align_errors);
6978 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6979 get_stat64(&hw_stats->tx_discards);
6980 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6981 get_stat64(&hw_stats->tx_carrier_sense_errors);
6983 stats->rx_crc_errors = old_stats->rx_crc_errors +
6984 calc_crc_errors(tp);
6986 stats->rx_missed_errors = old_stats->rx_missed_errors +
6987 get_stat64(&hw_stats->rx_discards);
6992 static inline u32 calc_crc(unsigned char *buf, int len)
7000 for (j = 0; j < len; j++) {
7003 for (k = 0; k < 8; k++) {
7017 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7019 /* accept or reject all multicast frames */
7020 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7021 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7022 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7023 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7026 static void __tg3_set_rx_mode(struct net_device *dev)
7028 struct tg3 *tp = netdev_priv(dev);
7031 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7032 RX_MODE_KEEP_VLAN_TAG);
7034 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7037 #if TG3_VLAN_TAG_USED
7039 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7040 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7042 /* By definition, VLAN is disabled always in this
7045 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7046 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7049 if (dev->flags & IFF_PROMISC) {
7050 /* Promiscuous mode. */
7051 rx_mode |= RX_MODE_PROMISC;
7052 } else if (dev->flags & IFF_ALLMULTI) {
7053 /* Accept all multicast. */
7054 tg3_set_multi (tp, 1);
7055 } else if (dev->mc_count < 1) {
7056 /* Reject all multicast. */
7057 tg3_set_multi (tp, 0);
7059 /* Accept one or more multicast(s). */
7060 struct dev_mc_list *mclist;
7062 u32 mc_filter[4] = { 0, };
7067 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7068 i++, mclist = mclist->next) {
7070 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7072 regidx = (bit & 0x60) >> 5;
7074 mc_filter[regidx] |= (1 << bit);
7077 tw32(MAC_HASH_REG_0, mc_filter[0]);
7078 tw32(MAC_HASH_REG_1, mc_filter[1]);
7079 tw32(MAC_HASH_REG_2, mc_filter[2]);
7080 tw32(MAC_HASH_REG_3, mc_filter[3]);
7083 if (rx_mode != tp->rx_mode) {
7084 tp->rx_mode = rx_mode;
7085 tw32_f(MAC_RX_MODE, rx_mode);
7090 static void tg3_set_rx_mode(struct net_device *dev)
7092 struct tg3 *tp = netdev_priv(dev);
7094 tg3_full_lock(tp, 0);
7095 __tg3_set_rx_mode(dev);
7096 tg3_full_unlock(tp);
7099 #define TG3_REGDUMP_LEN (32 * 1024)
7101 static int tg3_get_regs_len(struct net_device *dev)
7103 return TG3_REGDUMP_LEN;
7106 static void tg3_get_regs(struct net_device *dev,
7107 struct ethtool_regs *regs, void *_p)
7110 struct tg3 *tp = netdev_priv(dev);
7116 memset(p, 0, TG3_REGDUMP_LEN);
7118 tg3_full_lock(tp, 0);
7120 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
7121 #define GET_REG32_LOOP(base,len) \
7122 do { p = (u32 *)(orig_p + (base)); \
7123 for (i = 0; i < len; i += 4) \
7124 __GET_REG32((base) + i); \
7126 #define GET_REG32_1(reg) \
7127 do { p = (u32 *)(orig_p + (reg)); \
7128 __GET_REG32((reg)); \
7131 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7132 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7133 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7134 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7135 GET_REG32_1(SNDDATAC_MODE);
7136 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7137 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7138 GET_REG32_1(SNDBDC_MODE);
7139 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7140 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7141 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7142 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7143 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7144 GET_REG32_1(RCVDCC_MODE);
7145 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7146 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7147 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7148 GET_REG32_1(MBFREE_MODE);
7149 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7150 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7151 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7152 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7153 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7154 GET_REG32_1(RX_CPU_MODE);
7155 GET_REG32_1(RX_CPU_STATE);
7156 GET_REG32_1(RX_CPU_PGMCTR);
7157 GET_REG32_1(RX_CPU_HWBKPT);
7158 GET_REG32_1(TX_CPU_MODE);
7159 GET_REG32_1(TX_CPU_STATE);
7160 GET_REG32_1(TX_CPU_PGMCTR);
7161 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7162 GET_REG32_LOOP(FTQ_RESET, 0x120);
7163 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7164 GET_REG32_1(DMAC_MODE);
7165 GET_REG32_LOOP(GRC_MODE, 0x4c);
7166 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7167 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7170 #undef GET_REG32_LOOP
7173 tg3_full_unlock(tp);
7176 static int tg3_get_eeprom_len(struct net_device *dev)
7178 struct tg3 *tp = netdev_priv(dev);
7180 return tp->nvram_size;
7183 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7185 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7187 struct tg3 *tp = netdev_priv(dev);
7190 u32 i, offset, len, val, b_offset, b_count;
7192 offset = eeprom->offset;
7196 eeprom->magic = TG3_EEPROM_MAGIC;
7199 /* adjustments to start on required 4 byte boundary */
7200 b_offset = offset & 3;
7201 b_count = 4 - b_offset;
7202 if (b_count > len) {
7203 /* i.e. offset=1 len=2 */
7206 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7209 val = cpu_to_le32(val);
7210 memcpy(data, ((char*)&val) + b_offset, b_count);
7213 eeprom->len += b_count;
7216 /* read bytes upto the last 4 byte boundary */
7217 pd = &data[eeprom->len];
7218 for (i = 0; i < (len - (len & 3)); i += 4) {
7219 ret = tg3_nvram_read(tp, offset + i, &val);
7224 val = cpu_to_le32(val);
7225 memcpy(pd + i, &val, 4);
7230 /* read last bytes not ending on 4 byte boundary */
7231 pd = &data[eeprom->len];
7233 b_offset = offset + len - b_count;
7234 ret = tg3_nvram_read(tp, b_offset, &val);
7237 val = cpu_to_le32(val);
7238 memcpy(pd, ((char*)&val), b_count);
7239 eeprom->len += b_count;
7244 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7246 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7248 struct tg3 *tp = netdev_priv(dev);
7250 u32 offset, len, b_offset, odd_len, start, end;
7253 if (eeprom->magic != TG3_EEPROM_MAGIC)
7256 offset = eeprom->offset;
7259 if ((b_offset = (offset & 3))) {
7260 /* adjustments to start on required 4 byte boundary */
7261 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7264 start = cpu_to_le32(start);
7273 /* adjustments to end on required 4 byte boundary */
7275 len = (len + 3) & ~3;
7276 ret = tg3_nvram_read(tp, offset+len-4, &end);
7279 end = cpu_to_le32(end);
7283 if (b_offset || odd_len) {
7284 buf = kmalloc(len, GFP_KERNEL);
7288 memcpy(buf, &start, 4);
7290 memcpy(buf+len-4, &end, 4);
7291 memcpy(buf + b_offset, data, eeprom->len);
7294 ret = tg3_nvram_write_block(tp, offset, len, buf);
7302 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7304 struct tg3 *tp = netdev_priv(dev);
7306 cmd->supported = (SUPPORTED_Autoneg);
7308 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7309 cmd->supported |= (SUPPORTED_1000baseT_Half |
7310 SUPPORTED_1000baseT_Full);
7312 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
7313 cmd->supported |= (SUPPORTED_100baseT_Half |
7314 SUPPORTED_100baseT_Full |
7315 SUPPORTED_10baseT_Half |
7316 SUPPORTED_10baseT_Full |
7319 cmd->supported |= SUPPORTED_FIBRE;
7321 cmd->advertising = tp->link_config.advertising;
7322 if (netif_running(dev)) {
7323 cmd->speed = tp->link_config.active_speed;
7324 cmd->duplex = tp->link_config.active_duplex;
7327 cmd->phy_address = PHY_ADDR;
7328 cmd->transceiver = 0;
7329 cmd->autoneg = tp->link_config.autoneg;
7335 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7337 struct tg3 *tp = netdev_priv(dev);
7339 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7340 /* These are the only valid advertisement bits allowed. */
7341 if (cmd->autoneg == AUTONEG_ENABLE &&
7342 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7343 ADVERTISED_1000baseT_Full |
7344 ADVERTISED_Autoneg |
7347 /* Fiber can only do SPEED_1000. */
7348 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7349 (cmd->speed != SPEED_1000))
7351 /* Copper cannot force SPEED_1000. */
7352 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7353 (cmd->speed == SPEED_1000))
7355 else if ((cmd->speed == SPEED_1000) &&
7356 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7359 tg3_full_lock(tp, 0);
7361 tp->link_config.autoneg = cmd->autoneg;
7362 if (cmd->autoneg == AUTONEG_ENABLE) {
7363 tp->link_config.advertising = cmd->advertising;
7364 tp->link_config.speed = SPEED_INVALID;
7365 tp->link_config.duplex = DUPLEX_INVALID;
7367 tp->link_config.advertising = 0;
7368 tp->link_config.speed = cmd->speed;
7369 tp->link_config.duplex = cmd->duplex;
7372 if (netif_running(dev))
7373 tg3_setup_phy(tp, 1);
7375 tg3_full_unlock(tp);
7380 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7382 struct tg3 *tp = netdev_priv(dev);
7384 strcpy(info->driver, DRV_MODULE_NAME);
7385 strcpy(info->version, DRV_MODULE_VERSION);
7386 strcpy(info->bus_info, pci_name(tp->pdev));
7389 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7391 struct tg3 *tp = netdev_priv(dev);
7393 wol->supported = WAKE_MAGIC;
7395 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7396 wol->wolopts = WAKE_MAGIC;
7397 memset(&wol->sopass, 0, sizeof(wol->sopass));
7400 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7402 struct tg3 *tp = netdev_priv(dev);
7404 if (wol->wolopts & ~WAKE_MAGIC)
7406 if ((wol->wolopts & WAKE_MAGIC) &&
7407 tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7408 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7411 spin_lock_bh(&tp->lock);
7412 if (wol->wolopts & WAKE_MAGIC)
7413 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7415 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7416 spin_unlock_bh(&tp->lock);
7421 static u32 tg3_get_msglevel(struct net_device *dev)
7423 struct tg3 *tp = netdev_priv(dev);
7424 return tp->msg_enable;
7427 static void tg3_set_msglevel(struct net_device *dev, u32 value)
7429 struct tg3 *tp = netdev_priv(dev);
7430 tp->msg_enable = value;
7433 #if TG3_TSO_SUPPORT != 0
7434 static int tg3_set_tso(struct net_device *dev, u32 value)
7436 struct tg3 *tp = netdev_priv(dev);
7438 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7443 return ethtool_op_set_tso(dev, value);
7447 static int tg3_nway_reset(struct net_device *dev)
7449 struct tg3 *tp = netdev_priv(dev);
7453 if (!netif_running(dev))
7456 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7459 spin_lock_bh(&tp->lock);
7461 tg3_readphy(tp, MII_BMCR, &bmcr);
7462 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7463 ((bmcr & BMCR_ANENABLE) ||
7464 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
7465 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
7469 spin_unlock_bh(&tp->lock);
7474 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7476 struct tg3 *tp = netdev_priv(dev);
7478 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7479 ering->rx_mini_max_pending = 0;
7480 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7482 ering->rx_pending = tp->rx_pending;
7483 ering->rx_mini_pending = 0;
7484 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7485 ering->tx_pending = tp->tx_pending;
7488 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7490 struct tg3 *tp = netdev_priv(dev);
7493 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7494 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7495 (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7498 if (netif_running(dev)) {
7503 tg3_full_lock(tp, irq_sync);
7505 tp->rx_pending = ering->rx_pending;
7507 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7508 tp->rx_pending > 63)
7509 tp->rx_pending = 63;
7510 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7511 tp->tx_pending = ering->tx_pending;
7513 if (netif_running(dev)) {
7514 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7516 tg3_netif_start(tp);
7519 tg3_full_unlock(tp);
7524 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7526 struct tg3 *tp = netdev_priv(dev);
7528 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7529 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7530 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7533 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7535 struct tg3 *tp = netdev_priv(dev);
7538 if (netif_running(dev)) {
7543 tg3_full_lock(tp, irq_sync);
7545 if (epause->autoneg)
7546 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7548 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7549 if (epause->rx_pause)
7550 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7552 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7553 if (epause->tx_pause)
7554 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7556 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7558 if (netif_running(dev)) {
7559 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7561 tg3_netif_start(tp);
7564 tg3_full_unlock(tp);
7569 static u32 tg3_get_rx_csum(struct net_device *dev)
7571 struct tg3 *tp = netdev_priv(dev);
7572 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7575 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7577 struct tg3 *tp = netdev_priv(dev);
7579 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7585 spin_lock_bh(&tp->lock);
7587 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7589 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7590 spin_unlock_bh(&tp->lock);
7595 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7597 struct tg3 *tp = netdev_priv(dev);
7599 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7606 dev->features |= NETIF_F_IP_CSUM;
7608 dev->features &= ~NETIF_F_IP_CSUM;
7613 static int tg3_get_stats_count (struct net_device *dev)
7615 return TG3_NUM_STATS;
7618 static int tg3_get_test_count (struct net_device *dev)
7620 return TG3_NUM_TEST;
7623 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7625 switch (stringset) {
7627 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
7630 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
7633 WARN_ON(1); /* we need a WARN() */
7638 static int tg3_phys_id(struct net_device *dev, u32 data)
7640 struct tg3 *tp = netdev_priv(dev);
7643 if (!netif_running(tp->dev))
7649 for (i = 0; i < (data * 2); i++) {
7651 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
7652 LED_CTRL_1000MBPS_ON |
7653 LED_CTRL_100MBPS_ON |
7654 LED_CTRL_10MBPS_ON |
7655 LED_CTRL_TRAFFIC_OVERRIDE |
7656 LED_CTRL_TRAFFIC_BLINK |
7657 LED_CTRL_TRAFFIC_LED);
7660 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
7661 LED_CTRL_TRAFFIC_OVERRIDE);
7663 if (msleep_interruptible(500))
7666 tw32(MAC_LED_CTRL, tp->led_ctrl);
7670 static void tg3_get_ethtool_stats (struct net_device *dev,
7671 struct ethtool_stats *estats, u64 *tmp_stats)
7673 struct tg3 *tp = netdev_priv(dev);
7674 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7677 #define NVRAM_TEST_SIZE 0x100
7679 static int tg3_test_nvram(struct tg3 *tp)
7684 buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
7688 for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
7691 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
7693 buf[j] = cpu_to_le32(val);
7695 if (i < NVRAM_TEST_SIZE)
7699 if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
7702 /* Bootstrap checksum at offset 0x10 */
7703 csum = calc_crc((unsigned char *) buf, 0x10);
7704 if(csum != cpu_to_le32(buf[0x10/4]))
7707 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
7708 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
7709 if (csum != cpu_to_le32(buf[0xfc/4]))
7719 #define TG3_SERDES_TIMEOUT_SEC 2
7720 #define TG3_COPPER_TIMEOUT_SEC 6
7722 static int tg3_test_link(struct tg3 *tp)
7726 if (!netif_running(tp->dev))
7729 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
7730 max = TG3_SERDES_TIMEOUT_SEC;
7732 max = TG3_COPPER_TIMEOUT_SEC;
7734 for (i = 0; i < max; i++) {
7735 if (netif_carrier_ok(tp->dev))
7738 if (msleep_interruptible(1000))
7745 /* Only test the commonly used registers */
7746 static int tg3_test_registers(struct tg3 *tp)
7749 u32 offset, read_mask, write_mask, val, save_val, read_val;
7753 #define TG3_FL_5705 0x1
7754 #define TG3_FL_NOT_5705 0x2
7755 #define TG3_FL_NOT_5788 0x4
7759 /* MAC Control Registers */
7760 { MAC_MODE, TG3_FL_NOT_5705,
7761 0x00000000, 0x00ef6f8c },
7762 { MAC_MODE, TG3_FL_5705,
7763 0x00000000, 0x01ef6b8c },
7764 { MAC_STATUS, TG3_FL_NOT_5705,
7765 0x03800107, 0x00000000 },
7766 { MAC_STATUS, TG3_FL_5705,
7767 0x03800100, 0x00000000 },
7768 { MAC_ADDR_0_HIGH, 0x0000,
7769 0x00000000, 0x0000ffff },
7770 { MAC_ADDR_0_LOW, 0x0000,
7771 0x00000000, 0xffffffff },
7772 { MAC_RX_MTU_SIZE, 0x0000,
7773 0x00000000, 0x0000ffff },
7774 { MAC_TX_MODE, 0x0000,
7775 0x00000000, 0x00000070 },
7776 { MAC_TX_LENGTHS, 0x0000,
7777 0x00000000, 0x00003fff },
7778 { MAC_RX_MODE, TG3_FL_NOT_5705,
7779 0x00000000, 0x000007fc },
7780 { MAC_RX_MODE, TG3_FL_5705,
7781 0x00000000, 0x000007dc },
7782 { MAC_HASH_REG_0, 0x0000,
7783 0x00000000, 0xffffffff },
7784 { MAC_HASH_REG_1, 0x0000,
7785 0x00000000, 0xffffffff },
7786 { MAC_HASH_REG_2, 0x0000,
7787 0x00000000, 0xffffffff },
7788 { MAC_HASH_REG_3, 0x0000,
7789 0x00000000, 0xffffffff },
7791 /* Receive Data and Receive BD Initiator Control Registers. */
7792 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
7793 0x00000000, 0xffffffff },
7794 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
7795 0x00000000, 0xffffffff },
7796 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
7797 0x00000000, 0x00000003 },
7798 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
7799 0x00000000, 0xffffffff },
7800 { RCVDBDI_STD_BD+0, 0x0000,
7801 0x00000000, 0xffffffff },
7802 { RCVDBDI_STD_BD+4, 0x0000,
7803 0x00000000, 0xffffffff },
7804 { RCVDBDI_STD_BD+8, 0x0000,
7805 0x00000000, 0xffff0002 },
7806 { RCVDBDI_STD_BD+0xc, 0x0000,
7807 0x00000000, 0xffffffff },
7809 /* Receive BD Initiator Control Registers. */
7810 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
7811 0x00000000, 0xffffffff },
7812 { RCVBDI_STD_THRESH, TG3_FL_5705,
7813 0x00000000, 0x000003ff },
7814 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
7815 0x00000000, 0xffffffff },
7817 /* Host Coalescing Control Registers. */
7818 { HOSTCC_MODE, TG3_FL_NOT_5705,
7819 0x00000000, 0x00000004 },
7820 { HOSTCC_MODE, TG3_FL_5705,
7821 0x00000000, 0x000000f6 },
7822 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
7823 0x00000000, 0xffffffff },
7824 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
7825 0x00000000, 0x000003ff },
7826 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
7827 0x00000000, 0xffffffff },
7828 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
7829 0x00000000, 0x000003ff },
7830 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
7831 0x00000000, 0xffffffff },
7832 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7833 0x00000000, 0x000000ff },
7834 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
7835 0x00000000, 0xffffffff },
7836 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7837 0x00000000, 0x000000ff },
7838 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
7839 0x00000000, 0xffffffff },
7840 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
7841 0x00000000, 0xffffffff },
7842 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7843 0x00000000, 0xffffffff },
7844 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7845 0x00000000, 0x000000ff },
7846 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7847 0x00000000, 0xffffffff },
7848 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7849 0x00000000, 0x000000ff },
7850 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
7851 0x00000000, 0xffffffff },
7852 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
7853 0x00000000, 0xffffffff },
7854 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
7855 0x00000000, 0xffffffff },
7856 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
7857 0x00000000, 0xffffffff },
7858 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
7859 0x00000000, 0xffffffff },
7860 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
7861 0xffffffff, 0x00000000 },
7862 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
7863 0xffffffff, 0x00000000 },
7865 /* Buffer Manager Control Registers. */
7866 { BUFMGR_MB_POOL_ADDR, 0x0000,
7867 0x00000000, 0x007fff80 },
7868 { BUFMGR_MB_POOL_SIZE, 0x0000,
7869 0x00000000, 0x007fffff },
7870 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
7871 0x00000000, 0x0000003f },
7872 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
7873 0x00000000, 0x000001ff },
7874 { BUFMGR_MB_HIGH_WATER, 0x0000,
7875 0x00000000, 0x000001ff },
7876 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
7877 0xffffffff, 0x00000000 },
7878 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
7879 0xffffffff, 0x00000000 },
7881 /* Mailbox Registers */
7882 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
7883 0x00000000, 0x000001ff },
7884 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
7885 0x00000000, 0x000001ff },
7886 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
7887 0x00000000, 0x000007ff },
7888 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
7889 0x00000000, 0x000001ff },
7891 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
7894 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7899 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
7900 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
7903 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
7906 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7907 (reg_tbl[i].flags & TG3_FL_NOT_5788))
7910 offset = (u32) reg_tbl[i].offset;
7911 read_mask = reg_tbl[i].read_mask;
7912 write_mask = reg_tbl[i].write_mask;
7914 /* Save the original register content */
7915 save_val = tr32(offset);
7917 /* Determine the read-only value. */
7918 read_val = save_val & read_mask;
7920 /* Write zero to the register, then make sure the read-only bits
7921 * are not changed and the read/write bits are all zeros.
7927 /* Test the read-only and read/write bits. */
7928 if (((val & read_mask) != read_val) || (val & write_mask))
7931 /* Write ones to all the bits defined by RdMask and WrMask, then
7932 * make sure the read-only bits are not changed and the
7933 * read/write bits are all ones.
7935 tw32(offset, read_mask | write_mask);
7939 /* Test the read-only bits. */
7940 if ((val & read_mask) != read_val)
7943 /* Test the read/write bits. */
7944 if ((val & write_mask) != write_mask)
7947 tw32(offset, save_val);
7953 printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
7954 tw32(offset, save_val);
7958 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
7960 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7964 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
7965 for (j = 0; j < len; j += 4) {
7968 tg3_write_mem(tp, offset + j, test_pattern[i]);
7969 tg3_read_mem(tp, offset + j, &val);
7970 if (val != test_pattern[i])
7977 static int tg3_test_memory(struct tg3 *tp)
7979 static struct mem_entry {
7982 } mem_tbl_570x[] = {
7983 { 0x00000000, 0x00b50},
7984 { 0x00002000, 0x1c000},
7985 { 0xffffffff, 0x00000}
7986 }, mem_tbl_5705[] = {
7987 { 0x00000100, 0x0000c},
7988 { 0x00000200, 0x00008},
7989 { 0x00004000, 0x00800},
7990 { 0x00006000, 0x01000},
7991 { 0x00008000, 0x02000},
7992 { 0x00010000, 0x0e000},
7993 { 0xffffffff, 0x00000}
7995 struct mem_entry *mem_tbl;
7999 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8000 mem_tbl = mem_tbl_5705;
8002 mem_tbl = mem_tbl_570x;
8004 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8005 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8006 mem_tbl[i].len)) != 0)
8013 #define TG3_MAC_LOOPBACK 0
8014 #define TG3_PHY_LOOPBACK 1
8016 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8018 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8020 struct sk_buff *skb, *rx_skb;
8023 int num_pkts, tx_len, rx_len, i, err;
8024 struct tg3_rx_buffer_desc *desc;
8026 if (loopback_mode == TG3_MAC_LOOPBACK) {
8027 /* HW errata - mac loopback fails in some cases on 5780.
8028 * Normal traffic and PHY loopback are not affected by
8031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8034 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8035 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
8036 MAC_MODE_PORT_MODE_GMII;
8037 tw32(MAC_MODE, mac_mode);
8038 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8039 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
8042 /* reset to prevent losing 1st rx packet intermittently */
8043 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8044 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8046 tw32_f(MAC_RX_MODE, tp->rx_mode);
8048 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8049 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
8050 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
8051 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8052 tw32(MAC_MODE, mac_mode);
8060 skb = dev_alloc_skb(tx_len);
8061 tx_data = skb_put(skb, tx_len);
8062 memcpy(tx_data, tp->dev->dev_addr, 6);
8063 memset(tx_data + 6, 0x0, 8);
8065 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8067 for (i = 14; i < tx_len; i++)
8068 tx_data[i] = (u8) (i & 0xff);
8070 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8072 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8077 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8081 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8086 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8088 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8092 for (i = 0; i < 10; i++) {
8093 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8098 tx_idx = tp->hw_status->idx[0].tx_consumer;
8099 rx_idx = tp->hw_status->idx[0].rx_producer;
8100 if ((tx_idx == tp->tx_prod) &&
8101 (rx_idx == (rx_start_idx + num_pkts)))
8105 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8108 if (tx_idx != tp->tx_prod)
8111 if (rx_idx != rx_start_idx + num_pkts)
8114 desc = &tp->rx_rcb[rx_start_idx];
8115 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8116 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8117 if (opaque_key != RXD_OPAQUE_RING_STD)
8120 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8121 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8124 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8125 if (rx_len != tx_len)
8128 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8130 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8131 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8133 for (i = 14; i < tx_len; i++) {
8134 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8139 /* tg3_free_rings will unmap and free the rx_skb */
8144 #define TG3_MAC_LOOPBACK_FAILED 1
8145 #define TG3_PHY_LOOPBACK_FAILED 2
8146 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
8147 TG3_PHY_LOOPBACK_FAILED)
8149 static int tg3_test_loopback(struct tg3 *tp)
8153 if (!netif_running(tp->dev))
8154 return TG3_LOOPBACK_FAILED;
8158 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8159 err |= TG3_MAC_LOOPBACK_FAILED;
8160 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8161 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8162 err |= TG3_PHY_LOOPBACK_FAILED;
8168 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8171 struct tg3 *tp = netdev_priv(dev);
8173 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8175 if (tg3_test_nvram(tp) != 0) {
8176 etest->flags |= ETH_TEST_FL_FAILED;
8179 if (tg3_test_link(tp) != 0) {
8180 etest->flags |= ETH_TEST_FL_FAILED;
8183 if (etest->flags & ETH_TEST_FL_OFFLINE) {
8186 if (netif_running(dev)) {
8191 tg3_full_lock(tp, irq_sync);
8193 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8195 tg3_halt_cpu(tp, RX_CPU_BASE);
8196 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8197 tg3_halt_cpu(tp, TX_CPU_BASE);
8198 tg3_nvram_unlock(tp);
8200 if (tg3_test_registers(tp) != 0) {
8201 etest->flags |= ETH_TEST_FL_FAILED;
8204 if (tg3_test_memory(tp) != 0) {
8205 etest->flags |= ETH_TEST_FL_FAILED;
8208 if ((data[4] = tg3_test_loopback(tp)) != 0)
8209 etest->flags |= ETH_TEST_FL_FAILED;
8211 tg3_full_unlock(tp);
8213 if (tg3_test_interrupt(tp) != 0) {
8214 etest->flags |= ETH_TEST_FL_FAILED;
8218 tg3_full_lock(tp, 0);
8220 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8221 if (netif_running(dev)) {
8222 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8224 tg3_netif_start(tp);
8227 tg3_full_unlock(tp);
8231 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8233 struct mii_ioctl_data *data = if_mii(ifr);
8234 struct tg3 *tp = netdev_priv(dev);
8239 data->phy_id = PHY_ADDR;
8245 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8246 break; /* We have no PHY */
8248 spin_lock_bh(&tp->lock);
8249 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
8250 spin_unlock_bh(&tp->lock);
8252 data->val_out = mii_regval;
8258 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8259 break; /* We have no PHY */
8261 if (!capable(CAP_NET_ADMIN))
8264 spin_lock_bh(&tp->lock);
8265 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
8266 spin_unlock_bh(&tp->lock);
8277 #if TG3_VLAN_TAG_USED
8278 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
8280 struct tg3 *tp = netdev_priv(dev);
8282 tg3_full_lock(tp, 0);
8286 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
8287 __tg3_set_rx_mode(dev);
8289 tg3_full_unlock(tp);
8292 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
8294 struct tg3 *tp = netdev_priv(dev);
8296 tg3_full_lock(tp, 0);
8298 tp->vlgrp->vlan_devices[vid] = NULL;
8299 tg3_full_unlock(tp);
8303 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8305 struct tg3 *tp = netdev_priv(dev);
8307 memcpy(ec, &tp->coal, sizeof(*ec));
8311 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8313 struct tg3 *tp = netdev_priv(dev);
8314 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
8315 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
8317 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8318 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
8319 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
8320 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
8321 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
8324 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
8325 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
8326 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
8327 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
8328 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
8329 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
8330 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
8331 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
8332 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
8333 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
8336 /* No rx interrupts will be generated if both are zero */
8337 if ((ec->rx_coalesce_usecs == 0) &&
8338 (ec->rx_max_coalesced_frames == 0))
8341 /* No tx interrupts will be generated if both are zero */
8342 if ((ec->tx_coalesce_usecs == 0) &&
8343 (ec->tx_max_coalesced_frames == 0))
8346 /* Only copy relevant parameters, ignore all others. */
8347 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
8348 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
8349 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
8350 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
8351 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
8352 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
8353 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
8354 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
8355 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
8357 if (netif_running(dev)) {
8358 tg3_full_lock(tp, 0);
8359 __tg3_set_coalesce(tp, &tp->coal);
8360 tg3_full_unlock(tp);
8365 static struct ethtool_ops tg3_ethtool_ops = {
8366 .get_settings = tg3_get_settings,
8367 .set_settings = tg3_set_settings,
8368 .get_drvinfo = tg3_get_drvinfo,
8369 .get_regs_len = tg3_get_regs_len,
8370 .get_regs = tg3_get_regs,
8371 .get_wol = tg3_get_wol,
8372 .set_wol = tg3_set_wol,
8373 .get_msglevel = tg3_get_msglevel,
8374 .set_msglevel = tg3_set_msglevel,
8375 .nway_reset = tg3_nway_reset,
8376 .get_link = ethtool_op_get_link,
8377 .get_eeprom_len = tg3_get_eeprom_len,
8378 .get_eeprom = tg3_get_eeprom,
8379 .set_eeprom = tg3_set_eeprom,
8380 .get_ringparam = tg3_get_ringparam,
8381 .set_ringparam = tg3_set_ringparam,
8382 .get_pauseparam = tg3_get_pauseparam,
8383 .set_pauseparam = tg3_set_pauseparam,
8384 .get_rx_csum = tg3_get_rx_csum,
8385 .set_rx_csum = tg3_set_rx_csum,
8386 .get_tx_csum = ethtool_op_get_tx_csum,
8387 .set_tx_csum = tg3_set_tx_csum,
8388 .get_sg = ethtool_op_get_sg,
8389 .set_sg = ethtool_op_set_sg,
8390 #if TG3_TSO_SUPPORT != 0
8391 .get_tso = ethtool_op_get_tso,
8392 .set_tso = tg3_set_tso,
8394 .self_test_count = tg3_get_test_count,
8395 .self_test = tg3_self_test,
8396 .get_strings = tg3_get_strings,
8397 .phys_id = tg3_phys_id,
8398 .get_stats_count = tg3_get_stats_count,
8399 .get_ethtool_stats = tg3_get_ethtool_stats,
8400 .get_coalesce = tg3_get_coalesce,
8401 .set_coalesce = tg3_set_coalesce,
8402 .get_perm_addr = ethtool_op_get_perm_addr,
8405 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
8409 tp->nvram_size = EEPROM_CHIP_SIZE;
8411 if (tg3_nvram_read(tp, 0, &val) != 0)
8414 if (swab32(val) != TG3_EEPROM_MAGIC)
8418 * Size the chip by reading offsets at increasing powers of two.
8419 * When we encounter our validation signature, we know the addressing
8420 * has wrapped around, and thus have our chip size.
8424 while (cursize < tp->nvram_size) {
8425 if (tg3_nvram_read(tp, cursize, &val) != 0)
8428 if (swab32(val) == TG3_EEPROM_MAGIC)
8434 tp->nvram_size = cursize;
8437 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
8441 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
8443 tp->nvram_size = (val >> 16) * 1024;
8447 tp->nvram_size = 0x20000;
8450 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
8454 nvcfg1 = tr32(NVRAM_CFG1);
8455 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
8456 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8459 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8460 tw32(NVRAM_CFG1, nvcfg1);
8463 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
8464 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8465 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8466 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
8467 tp->nvram_jedecnum = JEDEC_ATMEL;
8468 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8469 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8471 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
8472 tp->nvram_jedecnum = JEDEC_ATMEL;
8473 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
8475 case FLASH_VENDOR_ATMEL_EEPROM:
8476 tp->nvram_jedecnum = JEDEC_ATMEL;
8477 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8478 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8480 case FLASH_VENDOR_ST:
8481 tp->nvram_jedecnum = JEDEC_ST;
8482 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
8483 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8485 case FLASH_VENDOR_SAIFUN:
8486 tp->nvram_jedecnum = JEDEC_SAIFUN;
8487 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
8489 case FLASH_VENDOR_SST_SMALL:
8490 case FLASH_VENDOR_SST_LARGE:
8491 tp->nvram_jedecnum = JEDEC_SST;
8492 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
8497 tp->nvram_jedecnum = JEDEC_ATMEL;
8498 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8499 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8503 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
8507 nvcfg1 = tr32(NVRAM_CFG1);
8509 /* NVRAM protection for TPM */
8510 if (nvcfg1 & (1 << 27))
8511 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8513 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8514 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
8515 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
8516 tp->nvram_jedecnum = JEDEC_ATMEL;
8517 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8519 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
8520 tp->nvram_jedecnum = JEDEC_ATMEL;
8521 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8522 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8524 case FLASH_5752VENDOR_ST_M45PE10:
8525 case FLASH_5752VENDOR_ST_M45PE20:
8526 case FLASH_5752VENDOR_ST_M45PE40:
8527 tp->nvram_jedecnum = JEDEC_ST;
8528 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8529 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8533 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
8534 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8535 case FLASH_5752PAGE_SIZE_256:
8536 tp->nvram_pagesize = 256;
8538 case FLASH_5752PAGE_SIZE_512:
8539 tp->nvram_pagesize = 512;
8541 case FLASH_5752PAGE_SIZE_1K:
8542 tp->nvram_pagesize = 1024;
8544 case FLASH_5752PAGE_SIZE_2K:
8545 tp->nvram_pagesize = 2048;
8547 case FLASH_5752PAGE_SIZE_4K:
8548 tp->nvram_pagesize = 4096;
8550 case FLASH_5752PAGE_SIZE_264:
8551 tp->nvram_pagesize = 264;
8556 /* For eeprom, set pagesize to maximum eeprom size */
8557 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8559 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8560 tw32(NVRAM_CFG1, nvcfg1);
8564 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
8565 static void __devinit tg3_nvram_init(struct tg3 *tp)
8569 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
8572 tw32_f(GRC_EEPROM_ADDR,
8573 (EEPROM_ADDR_FSM_RESET |
8574 (EEPROM_DEFAULT_CLOCK_PERIOD <<
8575 EEPROM_ADDR_CLKPERD_SHIFT)));
8577 /* XXX schedule_timeout() ... */
8578 for (j = 0; j < 100; j++)
8581 /* Enable seeprom accesses. */
8582 tw32_f(GRC_LOCAL_CTRL,
8583 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
8586 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8587 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
8588 tp->tg3_flags |= TG3_FLAG_NVRAM;
8591 tg3_enable_nvram_access(tp);
8593 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8594 tg3_get_5752_nvram_info(tp);
8596 tg3_get_nvram_info(tp);
8598 tg3_get_nvram_size(tp);
8600 tg3_disable_nvram_access(tp);
8601 tg3_nvram_unlock(tp);
8604 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
8606 tg3_get_eeprom_size(tp);
8610 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
8611 u32 offset, u32 *val)
8616 if (offset > EEPROM_ADDR_ADDR_MASK ||
8620 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
8621 EEPROM_ADDR_DEVID_MASK |
8623 tw32(GRC_EEPROM_ADDR,
8625 (0 << EEPROM_ADDR_DEVID_SHIFT) |
8626 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
8627 EEPROM_ADDR_ADDR_MASK) |
8628 EEPROM_ADDR_READ | EEPROM_ADDR_START);
8630 for (i = 0; i < 10000; i++) {
8631 tmp = tr32(GRC_EEPROM_ADDR);
8633 if (tmp & EEPROM_ADDR_COMPLETE)
8637 if (!(tmp & EEPROM_ADDR_COMPLETE))
8640 *val = tr32(GRC_EEPROM_DATA);
8644 #define NVRAM_CMD_TIMEOUT 10000
8646 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
8650 tw32(NVRAM_CMD, nvram_cmd);
8651 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
8653 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
8658 if (i == NVRAM_CMD_TIMEOUT) {
8664 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
8668 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8669 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
8673 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
8674 return tg3_nvram_read_using_eeprom(tp, offset, val);
8676 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
8677 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8678 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8680 offset = ((offset / tp->nvram_pagesize) <<
8681 ATMEL_AT45DB0X1B_PAGE_POS) +
8682 (offset % tp->nvram_pagesize);
8685 if (offset > NVRAM_ADDR_MSK)
8690 tg3_enable_nvram_access(tp);
8692 tw32(NVRAM_ADDR, offset);
8693 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
8694 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
8697 *val = swab32(tr32(NVRAM_RDDATA));
8699 tg3_disable_nvram_access(tp);
8701 tg3_nvram_unlock(tp);
8706 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
8707 u32 offset, u32 len, u8 *buf)
8712 for (i = 0; i < len; i += 4) {
8717 memcpy(&data, buf + i, 4);
8719 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
8721 val = tr32(GRC_EEPROM_ADDR);
8722 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
8724 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
8726 tw32(GRC_EEPROM_ADDR, val |
8727 (0 << EEPROM_ADDR_DEVID_SHIFT) |
8728 (addr & EEPROM_ADDR_ADDR_MASK) |
8732 for (j = 0; j < 10000; j++) {
8733 val = tr32(GRC_EEPROM_ADDR);
8735 if (val & EEPROM_ADDR_COMPLETE)
8739 if (!(val & EEPROM_ADDR_COMPLETE)) {
8748 /* offset and length are dword aligned */
8749 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
8753 u32 pagesize = tp->nvram_pagesize;
8754 u32 pagemask = pagesize - 1;
8758 tmp = kmalloc(pagesize, GFP_KERNEL);
8764 u32 phy_addr, page_off, size;
8766 phy_addr = offset & ~pagemask;
8768 for (j = 0; j < pagesize; j += 4) {
8769 if ((ret = tg3_nvram_read(tp, phy_addr + j,
8770 (u32 *) (tmp + j))))
8776 page_off = offset & pagemask;
8783 memcpy(tmp + page_off, buf, size);
8785 offset = offset + (pagesize - page_off);
8787 /* Nvram lock released by tg3_nvram_read() above,
8788 * so need to get it again.
8791 tg3_enable_nvram_access(tp);
8794 * Before we can erase the flash page, we need
8795 * to issue a special "write enable" command.
8797 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8799 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8802 /* Erase the target page */
8803 tw32(NVRAM_ADDR, phy_addr);
8805 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
8806 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
8808 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8811 /* Issue another write enable to start the write. */
8812 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8814 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8817 for (j = 0; j < pagesize; j += 4) {
8820 data = *((u32 *) (tmp + j));
8821 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8823 tw32(NVRAM_ADDR, phy_addr + j);
8825 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
8829 nvram_cmd |= NVRAM_CMD_FIRST;
8830 else if (j == (pagesize - 4))
8831 nvram_cmd |= NVRAM_CMD_LAST;
8833 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8840 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8841 tg3_nvram_exec_cmd(tp, nvram_cmd);
8848 /* offset and length are dword aligned */
8849 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
8854 for (i = 0; i < len; i += 4, offset += 4) {
8855 u32 data, page_off, phy_addr, nvram_cmd;
8857 memcpy(&data, buf + i, 4);
8858 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8860 page_off = offset % tp->nvram_pagesize;
8862 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8863 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8865 phy_addr = ((offset / tp->nvram_pagesize) <<
8866 ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
8872 tw32(NVRAM_ADDR, phy_addr);
8874 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
8876 if ((page_off == 0) || (i == 0))
8877 nvram_cmd |= NVRAM_CMD_FIRST;
8878 else if (page_off == (tp->nvram_pagesize - 4))
8879 nvram_cmd |= NVRAM_CMD_LAST;
8882 nvram_cmd |= NVRAM_CMD_LAST;
8884 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
8885 (tp->nvram_jedecnum == JEDEC_ST) &&
8886 (nvram_cmd & NVRAM_CMD_FIRST)) {
8888 if ((ret = tg3_nvram_exec_cmd(tp,
8889 NVRAM_CMD_WREN | NVRAM_CMD_GO |
8894 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8895 /* We always do complete word writes to eeprom. */
8896 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
8899 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8905 /* offset and length are dword aligned */
8906 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
8910 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8911 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
8915 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
8916 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
8917 ~GRC_LCLCTRL_GPIO_OUTPUT1);
8921 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
8922 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
8929 tg3_enable_nvram_access(tp);
8930 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
8931 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
8932 tw32(NVRAM_WRITE1, 0x406);
8934 grc_mode = tr32(GRC_MODE);
8935 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
8937 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
8938 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8940 ret = tg3_nvram_write_block_buffered(tp, offset, len,
8944 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
8948 grc_mode = tr32(GRC_MODE);
8949 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
8951 tg3_disable_nvram_access(tp);
8952 tg3_nvram_unlock(tp);
8955 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
8956 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8963 struct subsys_tbl_ent {
8964 u16 subsys_vendor, subsys_devid;
8968 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
8969 /* Broadcom boards. */
8970 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
8971 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
8972 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
8973 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
8974 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
8975 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
8976 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
8977 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
8978 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
8979 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
8980 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
8983 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
8984 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
8985 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
8986 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
8987 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
8990 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
8991 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
8992 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
8993 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
8995 /* Compaq boards. */
8996 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
8997 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
8998 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
8999 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9000 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9003 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9006 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9010 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9011 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9012 tp->pdev->subsystem_vendor) &&
9013 (subsys_id_to_phy_id[i].subsys_devid ==
9014 tp->pdev->subsystem_device))
9015 return &subsys_id_to_phy_id[i];
9020 /* Since this function may be called in D3-hot power state during
9021 * tg3_init_one(), only config cycles are allowed.
9023 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9027 /* Make sure register accesses (indirect or otherwise)
9028 * will function correctly.
9030 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9031 tp->misc_host_ctrl);
9033 tp->phy_id = PHY_ID_INVALID;
9034 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9036 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9037 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9038 u32 nic_cfg, led_cfg;
9039 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9040 int eeprom_phy_serdes = 0;
9042 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9043 tp->nic_sram_data_cfg = nic_cfg;
9045 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9046 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9047 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9048 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9049 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9050 (ver > 0) && (ver < 0x100))
9051 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9053 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9054 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
9055 eeprom_phy_serdes = 1;
9057 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
9058 if (nic_phy_id != 0) {
9059 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
9060 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
9062 eeprom_phy_id = (id1 >> 16) << 10;
9063 eeprom_phy_id |= (id2 & 0xfc00) << 16;
9064 eeprom_phy_id |= (id2 & 0x03ff) << 0;
9068 tp->phy_id = eeprom_phy_id;
9069 if (eeprom_phy_serdes) {
9070 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
9071 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
9073 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9076 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9077 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
9078 SHASTA_EXT_LED_MODE_MASK);
9080 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
9084 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
9085 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9088 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
9089 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9092 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
9093 tp->led_ctrl = LED_CTRL_MODE_MAC;
9095 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
9096 * read on some older 5700/5701 bootcode.
9098 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
9100 GET_ASIC_REV(tp->pci_chip_rev_id) ==
9102 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9106 case SHASTA_EXT_LED_SHARED:
9107 tp->led_ctrl = LED_CTRL_MODE_SHARED;
9108 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
9109 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
9110 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9111 LED_CTRL_MODE_PHY_2);
9114 case SHASTA_EXT_LED_MAC:
9115 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
9118 case SHASTA_EXT_LED_COMBO:
9119 tp->led_ctrl = LED_CTRL_MODE_COMBO;
9120 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
9121 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9122 LED_CTRL_MODE_PHY_2);
9127 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9128 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
9129 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
9130 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9132 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9133 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9134 (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
9135 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9137 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9138 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
9139 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9140 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
9142 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
9143 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
9145 if (cfg2 & (1 << 17))
9146 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
9148 /* serdes signal pre-emphasis in register 0x590 set by */
9149 /* bootcode if bit 18 is set */
9150 if (cfg2 & (1 << 18))
9151 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
9155 static int __devinit tg3_phy_probe(struct tg3 *tp)
9157 u32 hw_phy_id_1, hw_phy_id_2;
9158 u32 hw_phy_id, hw_phy_id_masked;
9161 /* Reading the PHY ID register can conflict with ASF
9162 * firwmare access to the PHY hardware.
9165 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
9166 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
9168 /* Now read the physical PHY_ID from the chip and verify
9169 * that it is sane. If it doesn't look good, we fall back
9170 * to either the hard-coded table based PHY_ID and failing
9171 * that the value found in the eeprom area.
9173 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
9174 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
9176 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
9177 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
9178 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
9180 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
9183 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
9184 tp->phy_id = hw_phy_id;
9185 if (hw_phy_id_masked == PHY_ID_BCM8002)
9186 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9188 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
9190 if (tp->phy_id != PHY_ID_INVALID) {
9191 /* Do nothing, phy ID already set up in
9192 * tg3_get_eeprom_hw_cfg().
9195 struct subsys_tbl_ent *p;
9197 /* No eeprom signature? Try the hardcoded
9198 * subsys device table.
9200 p = lookup_by_subsys(tp);
9204 tp->phy_id = p->phy_id;
9206 tp->phy_id == PHY_ID_BCM8002)
9207 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9211 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
9212 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
9213 u32 bmsr, adv_reg, tg3_ctrl;
9215 tg3_readphy(tp, MII_BMSR, &bmsr);
9216 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
9217 (bmsr & BMSR_LSTATUS))
9218 goto skip_phy_reset;
9220 err = tg3_phy_reset(tp);
9224 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
9225 ADVERTISE_100HALF | ADVERTISE_100FULL |
9226 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
9228 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
9229 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
9230 MII_TG3_CTRL_ADV_1000_FULL);
9231 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9232 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
9233 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
9234 MII_TG3_CTRL_ENABLE_AS_MASTER);
9237 if (!tg3_copper_is_advertising_all(tp)) {
9238 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9240 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9241 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9243 tg3_writephy(tp, MII_BMCR,
9244 BMCR_ANENABLE | BMCR_ANRESTART);
9246 tg3_phy_set_wirespeed(tp);
9248 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9249 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9250 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9254 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9255 err = tg3_init_5401phy_dsp(tp);
9260 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
9261 err = tg3_init_5401phy_dsp(tp);
9264 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9265 tp->link_config.advertising =
9266 (ADVERTISED_1000baseT_Half |
9267 ADVERTISED_1000baseT_Full |
9268 ADVERTISED_Autoneg |
9270 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9271 tp->link_config.advertising &=
9272 ~(ADVERTISED_1000baseT_Half |
9273 ADVERTISED_1000baseT_Full);
9278 static void __devinit tg3_read_partno(struct tg3 *tp)
9280 unsigned char vpd_data[256];
9283 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9284 /* Sun decided not to put the necessary bits in the
9285 * NVRAM of their onboard tg3 parts :(
9287 strcpy(tp->board_part_number, "Sun 570X");
9291 for (i = 0; i < 256; i += 4) {
9294 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
9297 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
9298 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
9299 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
9300 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
9303 /* Now parse and find the part number. */
9304 for (i = 0; i < 256; ) {
9305 unsigned char val = vpd_data[i];
9308 if (val == 0x82 || val == 0x91) {
9311 (vpd_data[i + 2] << 8)));
9318 block_end = (i + 3 +
9320 (vpd_data[i + 2] << 8)));
9322 while (i < block_end) {
9323 if (vpd_data[i + 0] == 'P' &&
9324 vpd_data[i + 1] == 'N') {
9325 int partno_len = vpd_data[i + 2];
9327 if (partno_len > 24)
9330 memcpy(tp->board_part_number,
9339 /* Part number not found. */
9344 strcpy(tp->board_part_number, "none");
9347 #ifdef CONFIG_SPARC64
9348 static int __devinit tg3_is_sun_570X(struct tg3 *tp)
9350 struct pci_dev *pdev = tp->pdev;
9351 struct pcidev_cookie *pcp = pdev->sysdata;
9354 int node = pcp->prom_node;
9358 err = prom_getproperty(node, "subsystem-vendor-id",
9359 (char *) &venid, sizeof(venid));
9360 if (err == 0 || err == -1)
9362 if (venid == PCI_VENDOR_ID_SUN)
9369 static int __devinit tg3_get_invariants(struct tg3 *tp)
9371 static struct pci_device_id write_reorder_chipsets[] = {
9372 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
9373 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
9374 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
9375 PCI_DEVICE_ID_VIA_8385_0) },
9379 u32 cacheline_sz_reg;
9380 u32 pci_state_reg, grc_misc_cfg;
9385 #ifdef CONFIG_SPARC64
9386 if (tg3_is_sun_570X(tp))
9387 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
9390 /* Force memory write invalidate off. If we leave it on,
9391 * then on 5700_BX chips we have to enable a workaround.
9392 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
9393 * to match the cacheline size. The Broadcom driver have this
9394 * workaround but turns MWI off all the times so never uses
9395 * it. This seems to suggest that the workaround is insufficient.
9397 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9398 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
9399 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9401 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
9402 * has the register indirect write enable bit set before
9403 * we try to access any of the MMIO registers. It is also
9404 * critical that the PCI-X hw workaround situation is decided
9405 * before that as well.
9407 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9410 tp->pci_chip_rev_id = (misc_ctrl_reg >>
9411 MISC_HOST_CTRL_CHIPREV_SHIFT);
9413 /* Wrong chip ID in 5752 A0. This code can be removed later
9414 * as A0 is not in production.
9416 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
9417 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
9419 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
9420 * we need to disable memory and use config. cycles
9421 * only to access all registers. The 5702/03 chips
9422 * can mistakenly decode the special cycles from the
9423 * ICH chipsets as memory write cycles, causing corruption
9424 * of register and memory space. Only certain ICH bridges
9425 * will drive special cycles with non-zero data during the
9426 * address phase which can fall within the 5703's address
9427 * range. This is not an ICH bug as the PCI spec allows
9428 * non-zero address during special cycles. However, only
9429 * these ICH bridges are known to drive non-zero addresses
9430 * during special cycles.
9432 * Since special cycles do not cross PCI bridges, we only
9433 * enable this workaround if the 5703 is on the secondary
9434 * bus of these ICH bridges.
9436 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
9437 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
9438 static struct tg3_dev_id {
9442 } ich_chipsets[] = {
9443 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
9445 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
9447 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
9449 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
9453 struct tg3_dev_id *pci_id = &ich_chipsets[0];
9454 struct pci_dev *bridge = NULL;
9456 while (pci_id->vendor != 0) {
9457 bridge = pci_get_device(pci_id->vendor, pci_id->device,
9463 if (pci_id->rev != PCI_ANY_ID) {
9466 pci_read_config_byte(bridge, PCI_REVISION_ID,
9468 if (rev > pci_id->rev)
9471 if (bridge->subordinate &&
9472 (bridge->subordinate->number ==
9473 tp->pdev->bus->number)) {
9475 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
9476 pci_dev_put(bridge);
9482 /* Find msi capability. */
9483 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
9484 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
9485 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
9486 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
9489 /* Initialize misc host control in PCI block. */
9490 tp->misc_host_ctrl |= (misc_ctrl_reg &
9491 MISC_HOST_CTRL_CHIPREV);
9492 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9493 tp->misc_host_ctrl);
9495 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9498 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
9499 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
9500 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
9501 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
9503 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
9504 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
9505 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
9506 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
9508 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
9509 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
9510 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
9512 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9513 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
9515 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
9516 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
9517 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
9518 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
9520 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
9521 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
9523 /* If we have an AMD 762 or VIA K8T800 chipset, write
9524 * reordering to the mailbox registers done by the host
9525 * controller can cause major troubles. We read back from
9526 * every mailbox register write to force the writes to be
9527 * posted to the chip in order.
9529 if (pci_dev_present(write_reorder_chipsets) &&
9530 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9531 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
9533 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9534 tp->pci_lat_timer < 64) {
9535 tp->pci_lat_timer = 64;
9537 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
9538 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
9539 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
9540 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
9542 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9546 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9549 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
9550 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
9552 /* If this is a 5700 BX chipset, and we are in PCI-X
9553 * mode, enable register write workaround.
9555 * The workaround is to use indirect register accesses
9556 * for all chip writes not to mailbox registers.
9558 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
9562 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9564 /* The chip can have it's power management PCI config
9565 * space registers clobbered due to this bug.
9566 * So explicitly force the chip into D0 here.
9568 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9570 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
9571 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9572 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9575 /* Also, force SERR#/PERR# in PCI command. */
9576 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9577 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
9578 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9582 /* 5700 BX chips need to have their TX producer index mailboxes
9583 * written twice to workaround a bug.
9585 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
9586 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
9588 /* Back to back register writes can cause problems on this chip,
9589 * the workaround is to read back all reg writes except those to
9590 * mailbox regs. See tg3_write_indirect_reg32().
9592 * PCI Express 5750_A0 rev chips need this workaround too.
9594 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
9595 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
9596 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
9597 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
9599 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
9600 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
9601 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
9602 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
9604 /* Chip-specific fixup from Broadcom driver */
9605 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
9606 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
9607 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
9608 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
9611 /* Default fast path register access methods */
9612 tp->read32 = tg3_read32;
9613 tp->write32 = tg3_write32;
9614 tp->read32_mbox = tg3_read32;
9615 tp->write32_mbox = tg3_write32;
9616 tp->write32_tx_mbox = tg3_write32;
9617 tp->write32_rx_mbox = tg3_write32;
9619 /* Various workaround register access methods */
9620 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
9621 tp->write32 = tg3_write_indirect_reg32;
9622 else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
9623 tp->write32 = tg3_write_flush_reg32;
9625 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
9626 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
9627 tp->write32_tx_mbox = tg3_write32_tx_mbox;
9628 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
9629 tp->write32_rx_mbox = tg3_write_flush_reg32;
9632 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
9633 tp->read32 = tg3_read_indirect_reg32;
9634 tp->write32 = tg3_write_indirect_reg32;
9635 tp->read32_mbox = tg3_read_indirect_mbox;
9636 tp->write32_mbox = tg3_write_indirect_mbox;
9637 tp->write32_tx_mbox = tg3_write_indirect_mbox;
9638 tp->write32_rx_mbox = tg3_write_indirect_mbox;
9643 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9644 pci_cmd &= ~PCI_COMMAND_MEMORY;
9645 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9648 /* Get eeprom hw config before calling tg3_set_power_state().
9649 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
9650 * determined before calling tg3_set_power_state() so that
9651 * we know whether or not to switch out of Vaux power.
9652 * When the flag is set, it means that GPIO1 is used for eeprom
9653 * write protect and also implies that it is a LOM where GPIOs
9654 * are not used to switch power.
9656 tg3_get_eeprom_hw_cfg(tp);
9658 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
9659 * GPIO1 driven high will bring 5700's external PHY out of reset.
9660 * It is also used as eeprom write protect on LOMs.
9662 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
9663 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9664 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
9665 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9666 GRC_LCLCTRL_GPIO_OUTPUT1);
9667 /* Unused GPIO3 must be driven as output on 5752 because there
9668 * are no pull-up resistors on unused GPIO pins.
9670 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9671 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
9673 /* Force the chip into D0. */
9674 err = tg3_set_power_state(tp, 0);
9676 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
9677 pci_name(tp->pdev));
9681 /* 5700 B0 chips do not support checksumming correctly due
9684 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
9685 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
9687 /* Pseudo-header checksum is done by hardware logic and not
9688 * the offload processers, so make the chip do the pseudo-
9689 * header checksums on receive. For transmit it is more
9690 * convenient to do the pseudo-header checksum in software
9691 * as Linux does that on transmit for us in all cases.
9693 tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
9694 tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
9696 /* Derive initial jumbo mode from MTU assigned in
9697 * ether_setup() via the alloc_etherdev() call
9699 if (tp->dev->mtu > ETH_DATA_LEN &&
9700 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
9701 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
9703 /* Determine WakeOnLan speed to use. */
9704 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9705 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9706 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
9707 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
9708 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
9710 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
9713 /* A few boards don't want Ethernet@WireSpeed phy feature */
9714 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9715 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
9716 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
9717 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
9718 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9719 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
9721 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
9722 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
9723 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
9724 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
9725 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
9727 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9728 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
9730 tp->coalesce_mode = 0;
9731 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
9732 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
9733 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
9735 /* Initialize MAC MI mode, polling disabled. */
9736 tw32_f(MAC_MI_MODE, tp->mi_mode);
9739 /* Initialize data/descriptor byte/word swapping. */
9740 val = tr32(GRC_MODE);
9741 val &= GRC_MODE_HOST_STACKUP;
9742 tw32(GRC_MODE, val | tp->grc_mode);
9744 tg3_switch_clocks(tp);
9746 /* Clear this out for sanity. */
9747 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9749 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9751 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
9752 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
9753 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
9755 if (chiprevid == CHIPREV_ID_5701_A0 ||
9756 chiprevid == CHIPREV_ID_5701_B0 ||
9757 chiprevid == CHIPREV_ID_5701_B2 ||
9758 chiprevid == CHIPREV_ID_5701_B5) {
9759 void __iomem *sram_base;
9761 /* Write some dummy words into the SRAM status block
9762 * area, see if it reads back correctly. If the return
9763 * value is bad, force enable the PCIX workaround.
9765 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
9767 writel(0x00000000, sram_base);
9768 writel(0x00000000, sram_base + 4);
9769 writel(0xffffffff, sram_base + 4);
9770 if (readl(sram_base) != 0x00000000)
9771 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9778 grc_misc_cfg = tr32(GRC_MISC_CFG);
9779 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
9781 /* Broadcom's driver says that CIOBE multisplit has a bug */
9783 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9784 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
9785 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
9786 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
9789 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9790 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
9791 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
9792 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
9794 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9795 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
9796 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
9797 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
9798 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
9799 HOSTCC_MODE_CLRTICK_TXBD);
9801 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
9802 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9803 tp->misc_host_ctrl);
9806 /* these are limited to 10/100 only */
9807 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9808 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
9809 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9810 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9811 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
9812 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
9813 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
9814 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9815 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
9816 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
9817 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
9819 err = tg3_phy_probe(tp);
9821 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
9822 pci_name(tp->pdev), err);
9823 /* ... but do not return immediately ... */
9826 tg3_read_partno(tp);
9828 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
9829 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9831 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9832 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
9834 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9837 /* 5700 {AX,BX} chips have a broken status block link
9838 * change bit implementation, so we must use the
9839 * status register in those cases.
9841 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9842 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
9844 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
9846 /* The led_ctrl is set during tg3_phy_probe, here we might
9847 * have to force the link status polling mechanism based
9848 * upon subsystem IDs.
9850 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
9851 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9852 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
9853 TG3_FLAG_USE_LINKCHG_REG);
9856 /* For all SERDES we poll the MAC status register. */
9857 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9858 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
9860 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
9862 /* It seems all chips can get confused if TX buffers
9863 * straddle the 4GB address boundary in some cases.
9865 tp->dev->hard_start_xmit = tg3_start_xmit;
9868 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
9869 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
9872 /* By default, disable wake-on-lan. User can change this
9873 * using ETHTOOL_SWOL.
9875 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9880 #ifdef CONFIG_SPARC64
9881 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
9883 struct net_device *dev = tp->dev;
9884 struct pci_dev *pdev = tp->pdev;
9885 struct pcidev_cookie *pcp = pdev->sysdata;
9888 int node = pcp->prom_node;
9890 if (prom_getproplen(node, "local-mac-address") == 6) {
9891 prom_getproperty(node, "local-mac-address",
9893 memcpy(dev->perm_addr, dev->dev_addr, 6);
9900 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
9902 struct net_device *dev = tp->dev;
9904 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
9905 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
9910 static int __devinit tg3_get_device_address(struct tg3 *tp)
9912 struct net_device *dev = tp->dev;
9913 u32 hi, lo, mac_offset;
9915 #ifdef CONFIG_SPARC64
9916 if (!tg3_get_macaddr_sparc(tp))
9921 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9922 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
9923 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9924 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
9926 if (tg3_nvram_lock(tp))
9927 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
9929 tg3_nvram_unlock(tp);
9932 /* First try to get it from MAC address mailbox. */
9933 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
9934 if ((hi >> 16) == 0x484b) {
9935 dev->dev_addr[0] = (hi >> 8) & 0xff;
9936 dev->dev_addr[1] = (hi >> 0) & 0xff;
9938 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
9939 dev->dev_addr[2] = (lo >> 24) & 0xff;
9940 dev->dev_addr[3] = (lo >> 16) & 0xff;
9941 dev->dev_addr[4] = (lo >> 8) & 0xff;
9942 dev->dev_addr[5] = (lo >> 0) & 0xff;
9944 /* Next, try NVRAM. */
9945 else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
9946 !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
9947 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
9948 dev->dev_addr[0] = ((hi >> 16) & 0xff);
9949 dev->dev_addr[1] = ((hi >> 24) & 0xff);
9950 dev->dev_addr[2] = ((lo >> 0) & 0xff);
9951 dev->dev_addr[3] = ((lo >> 8) & 0xff);
9952 dev->dev_addr[4] = ((lo >> 16) & 0xff);
9953 dev->dev_addr[5] = ((lo >> 24) & 0xff);
9955 /* Finally just fetch it out of the MAC control regs. */
9957 hi = tr32(MAC_ADDR_0_HIGH);
9958 lo = tr32(MAC_ADDR_0_LOW);
9960 dev->dev_addr[5] = lo & 0xff;
9961 dev->dev_addr[4] = (lo >> 8) & 0xff;
9962 dev->dev_addr[3] = (lo >> 16) & 0xff;
9963 dev->dev_addr[2] = (lo >> 24) & 0xff;
9964 dev->dev_addr[1] = hi & 0xff;
9965 dev->dev_addr[0] = (hi >> 8) & 0xff;
9968 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9969 #ifdef CONFIG_SPARC64
9970 if (!tg3_get_default_macaddr_sparc(tp))
9975 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
9979 #define BOUNDARY_SINGLE_CACHELINE 1
9980 #define BOUNDARY_MULTI_CACHELINE 2
9982 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
9988 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
9990 cacheline_size = 1024;
9992 cacheline_size = (int) byte * 4;
9994 /* On 5703 and later chips, the boundary bits have no
9997 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9998 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
9999 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10002 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
10003 goal = BOUNDARY_MULTI_CACHELINE;
10005 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
10006 goal = BOUNDARY_SINGLE_CACHELINE;
10015 /* PCI controllers on most RISC systems tend to disconnect
10016 * when a device tries to burst across a cache-line boundary.
10017 * Therefore, letting tg3 do so just wastes PCI bandwidth.
10019 * Unfortunately, for PCI-E there are only limited
10020 * write-side controls for this, and thus for reads
10021 * we will still get the disconnects. We'll also waste
10022 * these PCI cycles for both read and write for chips
10023 * other than 5700 and 5701 which do not implement the
10026 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10027 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
10028 switch (cacheline_size) {
10033 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10034 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
10035 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
10037 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10038 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10043 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
10044 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
10048 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10049 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10052 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10053 switch (cacheline_size) {
10057 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10058 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10059 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
10065 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10066 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
10070 switch (cacheline_size) {
10072 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10073 val |= (DMA_RWCTRL_READ_BNDRY_16 |
10074 DMA_RWCTRL_WRITE_BNDRY_16);
10079 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10080 val |= (DMA_RWCTRL_READ_BNDRY_32 |
10081 DMA_RWCTRL_WRITE_BNDRY_32);
10086 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10087 val |= (DMA_RWCTRL_READ_BNDRY_64 |
10088 DMA_RWCTRL_WRITE_BNDRY_64);
10093 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10094 val |= (DMA_RWCTRL_READ_BNDRY_128 |
10095 DMA_RWCTRL_WRITE_BNDRY_128);
10100 val |= (DMA_RWCTRL_READ_BNDRY_256 |
10101 DMA_RWCTRL_WRITE_BNDRY_256);
10104 val |= (DMA_RWCTRL_READ_BNDRY_512 |
10105 DMA_RWCTRL_WRITE_BNDRY_512);
10109 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
10110 DMA_RWCTRL_WRITE_BNDRY_1024);
10119 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
10121 struct tg3_internal_buffer_desc test_desc;
10122 u32 sram_dma_descs;
10125 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
10127 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
10128 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
10129 tw32(RDMAC_STATUS, 0);
10130 tw32(WDMAC_STATUS, 0);
10132 tw32(BUFMGR_MODE, 0);
10133 tw32(FTQ_RESET, 0);
10135 test_desc.addr_hi = ((u64) buf_dma) >> 32;
10136 test_desc.addr_lo = buf_dma & 0xffffffff;
10137 test_desc.nic_mbuf = 0x00002100;
10138 test_desc.len = size;
10141 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
10142 * the *second* time the tg3 driver was getting loaded after an
10145 * Broadcom tells me:
10146 * ...the DMA engine is connected to the GRC block and a DMA
10147 * reset may affect the GRC block in some unpredictable way...
10148 * The behavior of resets to individual blocks has not been tested.
10150 * Broadcom noted the GRC reset will also reset all sub-components.
10153 test_desc.cqid_sqid = (13 << 8) | 2;
10155 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
10158 test_desc.cqid_sqid = (16 << 8) | 7;
10160 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
10163 test_desc.flags = 0x00000005;
10165 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
10168 val = *(((u32 *)&test_desc) + i);
10169 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
10170 sram_dma_descs + (i * sizeof(u32)));
10171 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
10173 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
10176 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
10178 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
10182 for (i = 0; i < 40; i++) {
10186 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
10188 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
10189 if ((val & 0xffff) == sram_dma_descs) {
10200 #define TEST_BUFFER_SIZE 0x2000
10202 static int __devinit tg3_test_dma(struct tg3 *tp)
10204 dma_addr_t buf_dma;
10205 u32 *buf, saved_dma_rwctrl;
10208 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
10214 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
10215 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
10217 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
10219 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10220 /* DMA read watermark not used on PCIE */
10221 tp->dma_rwctrl |= 0x00180000;
10222 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
10223 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
10224 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
10225 tp->dma_rwctrl |= 0x003f0000;
10227 tp->dma_rwctrl |= 0x003f000f;
10229 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10230 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
10231 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
10233 if (ccval == 0x6 || ccval == 0x7)
10234 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
10236 /* Set bit 23 to enable PCIX hw bug fix */
10237 tp->dma_rwctrl |= 0x009f0000;
10238 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
10239 /* 5780 always in PCIX mode */
10240 tp->dma_rwctrl |= 0x00144000;
10241 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10242 /* 5714 always in PCIX mode */
10243 tp->dma_rwctrl |= 0x00148000;
10245 tp->dma_rwctrl |= 0x001b000f;
10249 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10250 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10251 tp->dma_rwctrl &= 0xfffffff0;
10253 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10254 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
10255 /* Remove this if it causes problems for some boards. */
10256 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
10258 /* On 5700/5701 chips, we need to set this bit.
10259 * Otherwise the chip will issue cacheline transactions
10260 * to streamable DMA memory with not all the byte
10261 * enables turned on. This is an error on several
10262 * RISC PCI controllers, in particular sparc64.
10264 * On 5703/5704 chips, this bit has been reassigned
10265 * a different meaning. In particular, it is used
10266 * on those chips to enable a PCI-X workaround.
10268 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
10271 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10274 /* Unneeded, already done by tg3_get_invariants. */
10275 tg3_switch_clocks(tp);
10279 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10280 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
10283 /* It is best to perform DMA test with maximum write burst size
10284 * to expose the 5700/5701 write DMA bug.
10286 saved_dma_rwctrl = tp->dma_rwctrl;
10287 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10288 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10293 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
10296 /* Send the buffer to the chip. */
10297 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
10299 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
10304 /* validate data reached card RAM correctly. */
10305 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10307 tg3_read_mem(tp, 0x2100 + (i*4), &val);
10308 if (le32_to_cpu(val) != p[i]) {
10309 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
10310 /* ret = -ENODEV here? */
10315 /* Now read it back. */
10316 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
10318 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
10324 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10328 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10329 DMA_RWCTRL_WRITE_BNDRY_16) {
10330 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10331 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10332 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10335 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
10341 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
10347 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10348 DMA_RWCTRL_WRITE_BNDRY_16) {
10349 static struct pci_device_id dma_wait_state_chipsets[] = {
10350 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
10351 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
10355 /* DMA test passed without adjusting DMA boundary,
10356 * now look for chipsets that are known to expose the
10357 * DMA bug without failing the test.
10359 if (pci_dev_present(dma_wait_state_chipsets)) {
10360 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10361 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10364 /* Safe to use the calculated DMA boundary. */
10365 tp->dma_rwctrl = saved_dma_rwctrl;
10367 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10371 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
10376 static void __devinit tg3_init_link_config(struct tg3 *tp)
10378 tp->link_config.advertising =
10379 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10380 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10381 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
10382 ADVERTISED_Autoneg | ADVERTISED_MII);
10383 tp->link_config.speed = SPEED_INVALID;
10384 tp->link_config.duplex = DUPLEX_INVALID;
10385 tp->link_config.autoneg = AUTONEG_ENABLE;
10386 netif_carrier_off(tp->dev);
10387 tp->link_config.active_speed = SPEED_INVALID;
10388 tp->link_config.active_duplex = DUPLEX_INVALID;
10389 tp->link_config.phy_is_low_power = 0;
10390 tp->link_config.orig_speed = SPEED_INVALID;
10391 tp->link_config.orig_duplex = DUPLEX_INVALID;
10392 tp->link_config.orig_autoneg = AUTONEG_INVALID;
10395 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
10397 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10398 tp->bufmgr_config.mbuf_read_dma_low_water =
10399 DEFAULT_MB_RDMA_LOW_WATER_5705;
10400 tp->bufmgr_config.mbuf_mac_rx_low_water =
10401 DEFAULT_MB_MACRX_LOW_WATER_5705;
10402 tp->bufmgr_config.mbuf_high_water =
10403 DEFAULT_MB_HIGH_WATER_5705;
10405 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10406 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
10407 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10408 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
10409 tp->bufmgr_config.mbuf_high_water_jumbo =
10410 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
10412 tp->bufmgr_config.mbuf_read_dma_low_water =
10413 DEFAULT_MB_RDMA_LOW_WATER;
10414 tp->bufmgr_config.mbuf_mac_rx_low_water =
10415 DEFAULT_MB_MACRX_LOW_WATER;
10416 tp->bufmgr_config.mbuf_high_water =
10417 DEFAULT_MB_HIGH_WATER;
10419 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10420 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
10421 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10422 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
10423 tp->bufmgr_config.mbuf_high_water_jumbo =
10424 DEFAULT_MB_HIGH_WATER_JUMBO;
10427 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
10428 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
10431 static char * __devinit tg3_phy_string(struct tg3 *tp)
10433 switch (tp->phy_id & PHY_ID_MASK) {
10434 case PHY_ID_BCM5400: return "5400";
10435 case PHY_ID_BCM5401: return "5401";
10436 case PHY_ID_BCM5411: return "5411";
10437 case PHY_ID_BCM5701: return "5701";
10438 case PHY_ID_BCM5703: return "5703";
10439 case PHY_ID_BCM5704: return "5704";
10440 case PHY_ID_BCM5705: return "5705";
10441 case PHY_ID_BCM5750: return "5750";
10442 case PHY_ID_BCM5752: return "5752";
10443 case PHY_ID_BCM5714: return "5714";
10444 case PHY_ID_BCM5780: return "5780";
10445 case PHY_ID_BCM8002: return "8002/serdes";
10446 case 0: return "serdes";
10447 default: return "unknown";
10451 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
10453 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10454 strcpy(str, "PCI Express");
10456 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
10457 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
10459 strcpy(str, "PCIX:");
10461 if ((clock_ctrl == 7) ||
10462 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
10463 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
10464 strcat(str, "133MHz");
10465 else if (clock_ctrl == 0)
10466 strcat(str, "33MHz");
10467 else if (clock_ctrl == 2)
10468 strcat(str, "50MHz");
10469 else if (clock_ctrl == 4)
10470 strcat(str, "66MHz");
10471 else if (clock_ctrl == 6)
10472 strcat(str, "100MHz");
10473 else if (clock_ctrl == 7)
10474 strcat(str, "133MHz");
10476 strcpy(str, "PCI:");
10477 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
10478 strcat(str, "66MHz");
10480 strcat(str, "33MHz");
10482 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
10483 strcat(str, ":32-bit");
10485 strcat(str, ":64-bit");
10489 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
10491 struct pci_dev *peer;
10492 unsigned int func, devnr = tp->pdev->devfn & ~7;
10494 for (func = 0; func < 8; func++) {
10495 peer = pci_get_slot(tp->pdev->bus, devnr | func);
10496 if (peer && peer != tp->pdev)
10500 /* 5704 can be configured in single-port mode, set peer to
10501 * tp->pdev in that case.
10509 * We don't need to keep the refcount elevated; there's no way
10510 * to remove one half of this device without removing the other
10517 static void __devinit tg3_init_coal(struct tg3 *tp)
10519 struct ethtool_coalesce *ec = &tp->coal;
10521 memset(ec, 0, sizeof(*ec));
10522 ec->cmd = ETHTOOL_GCOALESCE;
10523 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
10524 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
10525 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
10526 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
10527 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
10528 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
10529 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
10530 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
10531 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
10533 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
10534 HOSTCC_MODE_CLRTICK_TXBD)) {
10535 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
10536 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
10537 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
10538 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
10541 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10542 ec->rx_coalesce_usecs_irq = 0;
10543 ec->tx_coalesce_usecs_irq = 0;
10544 ec->stats_block_coalesce_usecs = 0;
10548 static int __devinit tg3_init_one(struct pci_dev *pdev,
10549 const struct pci_device_id *ent)
10551 static int tg3_version_printed = 0;
10552 unsigned long tg3reg_base, tg3reg_len;
10553 struct net_device *dev;
10555 int i, err, pci_using_dac, pm_cap;
10558 if (tg3_version_printed++ == 0)
10559 printk(KERN_INFO "%s", version);
10561 err = pci_enable_device(pdev);
10563 printk(KERN_ERR PFX "Cannot enable PCI device, "
10568 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10569 printk(KERN_ERR PFX "Cannot find proper PCI device "
10570 "base address, aborting.\n");
10572 goto err_out_disable_pdev;
10575 err = pci_request_regions(pdev, DRV_MODULE_NAME);
10577 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
10579 goto err_out_disable_pdev;
10582 pci_set_master(pdev);
10584 /* Find power-management capability. */
10585 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10587 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
10590 goto err_out_free_res;
10593 /* Configure DMA attributes. */
10594 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
10597 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
10599 printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
10600 "for consistent allocations\n");
10601 goto err_out_free_res;
10604 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
10606 printk(KERN_ERR PFX "No usable DMA configuration, "
10608 goto err_out_free_res;
10613 tg3reg_base = pci_resource_start(pdev, 0);
10614 tg3reg_len = pci_resource_len(pdev, 0);
10616 dev = alloc_etherdev(sizeof(*tp));
10618 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
10620 goto err_out_free_res;
10623 SET_MODULE_OWNER(dev);
10624 SET_NETDEV_DEV(dev, &pdev->dev);
10627 dev->features |= NETIF_F_HIGHDMA;
10628 dev->features |= NETIF_F_LLTX;
10629 #if TG3_VLAN_TAG_USED
10630 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
10631 dev->vlan_rx_register = tg3_vlan_rx_register;
10632 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
10635 tp = netdev_priv(dev);
10638 tp->pm_cap = pm_cap;
10639 tp->mac_mode = TG3_DEF_MAC_MODE;
10640 tp->rx_mode = TG3_DEF_RX_MODE;
10641 tp->tx_mode = TG3_DEF_TX_MODE;
10642 tp->mi_mode = MAC_MI_MODE_BASE;
10644 tp->msg_enable = tg3_debug;
10646 tp->msg_enable = TG3_DEF_MSG_ENABLE;
10648 /* The word/byte swap controls here control register access byte
10649 * swapping. DMA data byte swapping is controlled in the GRC_MODE
10652 tp->misc_host_ctrl =
10653 MISC_HOST_CTRL_MASK_PCI_INT |
10654 MISC_HOST_CTRL_WORD_SWAP |
10655 MISC_HOST_CTRL_INDIR_ACCESS |
10656 MISC_HOST_CTRL_PCISTATE_RW;
10658 /* The NONFRM (non-frame) byte/word swap controls take effect
10659 * on descriptor entries, anything which isn't packet data.
10661 * The StrongARM chips on the board (one for tx, one for rx)
10662 * are running in big-endian mode.
10664 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
10665 GRC_MODE_WSWAP_NONFRM_DATA);
10666 #ifdef __BIG_ENDIAN
10667 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
10669 spin_lock_init(&tp->lock);
10670 spin_lock_init(&tp->tx_lock);
10671 spin_lock_init(&tp->indirect_lock);
10672 INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
10674 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
10675 if (tp->regs == 0UL) {
10676 printk(KERN_ERR PFX "Cannot map device registers, "
10679 goto err_out_free_dev;
10682 tg3_init_link_config(tp);
10684 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
10685 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
10686 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
10688 dev->open = tg3_open;
10689 dev->stop = tg3_close;
10690 dev->get_stats = tg3_get_stats;
10691 dev->set_multicast_list = tg3_set_rx_mode;
10692 dev->set_mac_address = tg3_set_mac_addr;
10693 dev->do_ioctl = tg3_ioctl;
10694 dev->tx_timeout = tg3_tx_timeout;
10695 dev->poll = tg3_poll;
10696 dev->ethtool_ops = &tg3_ethtool_ops;
10698 dev->watchdog_timeo = TG3_TX_TIMEOUT;
10699 dev->change_mtu = tg3_change_mtu;
10700 dev->irq = pdev->irq;
10701 #ifdef CONFIG_NET_POLL_CONTROLLER
10702 dev->poll_controller = tg3_poll_controller;
10705 err = tg3_get_invariants(tp);
10707 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
10709 goto err_out_iounmap;
10712 tg3_init_bufmgr_config(tp);
10714 #if TG3_TSO_SUPPORT != 0
10715 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
10716 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10718 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10719 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10720 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
10721 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
10722 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
10724 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10727 /* TSO is off by default, user can enable using ethtool. */
10729 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
10730 dev->features |= NETIF_F_TSO;
10735 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
10736 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
10737 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
10738 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
10739 tp->rx_pending = 63;
10742 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10743 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
10744 tp->pdev_peer = tg3_find_peer(tp);
10746 err = tg3_get_device_address(tp);
10748 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
10750 goto err_out_iounmap;
10754 * Reset chip in case UNDI or EFI driver did not shutdown
10755 * DMA self test will enable WDMAC and we'll see (spurious)
10756 * pending DMA on the PCI bus at that point.
10758 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
10759 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10760 pci_save_state(tp->pdev);
10761 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
10762 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10765 err = tg3_test_dma(tp);
10767 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
10768 goto err_out_iounmap;
10771 /* Tigon3 can do ipv4 only... and some chips have buggy
10774 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
10775 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
10776 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10778 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10780 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
10781 dev->features &= ~NETIF_F_HIGHDMA;
10783 /* flow control autonegotiation is default behavior */
10784 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10788 /* Now that we have fully setup the chip, save away a snapshot
10789 * of the PCI config space. We need to restore this after
10790 * GRC_MISC_CFG core clock resets and some resume events.
10792 pci_save_state(tp->pdev);
10794 err = register_netdev(dev);
10796 printk(KERN_ERR PFX "Cannot register net device, "
10798 goto err_out_iounmap;
10801 pci_set_drvdata(pdev, dev);
10803 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
10805 tp->board_part_number,
10806 tp->pci_chip_rev_id,
10807 tg3_phy_string(tp),
10808 tg3_bus_string(tp, str),
10809 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
10811 for (i = 0; i < 6; i++)
10812 printk("%2.2x%c", dev->dev_addr[i],
10813 i == 5 ? '\n' : ':');
10815 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
10816 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
10819 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
10820 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
10821 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
10822 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
10823 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
10824 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
10825 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
10826 printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
10827 dev->name, tp->dma_rwctrl);
10841 pci_release_regions(pdev);
10843 err_out_disable_pdev:
10844 pci_disable_device(pdev);
10845 pci_set_drvdata(pdev, NULL);
10849 static void __devexit tg3_remove_one(struct pci_dev *pdev)
10851 struct net_device *dev = pci_get_drvdata(pdev);
10854 struct tg3 *tp = netdev_priv(dev);
10856 unregister_netdev(dev);
10862 pci_release_regions(pdev);
10863 pci_disable_device(pdev);
10864 pci_set_drvdata(pdev, NULL);
10868 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
10870 struct net_device *dev = pci_get_drvdata(pdev);
10871 struct tg3 *tp = netdev_priv(dev);
10874 if (!netif_running(dev))
10877 tg3_netif_stop(tp);
10879 del_timer_sync(&tp->timer);
10881 tg3_full_lock(tp, 1);
10882 tg3_disable_ints(tp);
10883 tg3_full_unlock(tp);
10885 netif_device_detach(dev);
10887 tg3_full_lock(tp, 0);
10888 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10889 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
10890 tg3_full_unlock(tp);
10892 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
10894 tg3_full_lock(tp, 0);
10896 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10899 tp->timer.expires = jiffies + tp->timer_offset;
10900 add_timer(&tp->timer);
10902 netif_device_attach(dev);
10903 tg3_netif_start(tp);
10905 tg3_full_unlock(tp);
10911 static int tg3_resume(struct pci_dev *pdev)
10913 struct net_device *dev = pci_get_drvdata(pdev);
10914 struct tg3 *tp = netdev_priv(dev);
10917 if (!netif_running(dev))
10920 pci_restore_state(tp->pdev);
10922 err = tg3_set_power_state(tp, 0);
10926 netif_device_attach(dev);
10928 tg3_full_lock(tp, 0);
10930 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10933 tp->timer.expires = jiffies + tp->timer_offset;
10934 add_timer(&tp->timer);
10936 tg3_netif_start(tp);
10938 tg3_full_unlock(tp);
10943 static struct pci_driver tg3_driver = {
10944 .name = DRV_MODULE_NAME,
10945 .id_table = tg3_pci_tbl,
10946 .probe = tg3_init_one,
10947 .remove = __devexit_p(tg3_remove_one),
10948 .suspend = tg3_suspend,
10949 .resume = tg3_resume
10952 static int __init tg3_init(void)
10954 return pci_module_init(&tg3_driver);
10957 static void __exit tg3_cleanup(void)
10959 pci_unregister_driver(&tg3_driver);
10962 module_init(tg3_init);
10963 module_exit(tg3_cleanup);