drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2011 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mdio.h>
  36 #include <linux/mii.h>
  37 #include <linux/phy.h>
  38 #include <linux/brcmphy.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/ip.h>
  41 #include <linux/tcp.h>
  42 #include <linux/workqueue.h>
  43 #include <linux/prefetch.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/firmware.h>
  46
  47 #include <net/checksum.h>
  48 #include <net/ip.h>
  49
  50 #include <asm/system.h>
  51 #include <linux/io.h>
  52 #include <asm/byteorder.h>
  53 #include <linux/uaccess.h>
  54
  55 #ifdef CONFIG_SPARC
  56 #include <asm/idprom.h>
  57 #include <asm/prom.h>
  58 #endif
  59
  60 #define BAR_0   0
  61 #define BAR_2   2
  62
  63 #include "tg3.h"
  64
  65 /* Functions & macros to verify TG3_FLAGS types */
  66
  67 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
  68 {
  69         return test_bit(flag, bits);
  70 }
  71
  72 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
  73 {
  74         set_bit(flag, bits);
  75 }
  76
  77 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
  78 {
  79         clear_bit(flag, bits);
  80 }
  81
  82 #define tg3_flag(tp, flag)                              \
  83         _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
  84 #define tg3_flag_set(tp, flag)                          \
  85         _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
  86 #define tg3_flag_clear(tp, flag)                        \
  87         _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
  88
  89 #define DRV_MODULE_NAME         "tg3"
  90 #define TG3_MAJ_NUM                     3
  91 #define TG3_MIN_NUM                     118
  92 #define DRV_MODULE_VERSION      \
  93         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  94 #define DRV_MODULE_RELDATE      "April 22, 2011"
  95
  96 #define TG3_DEF_MAC_MODE        0
  97 #define TG3_DEF_RX_MODE         0
  98 #define TG3_DEF_TX_MODE         0
  99 #define TG3_DEF_MSG_ENABLE        \
 100         (NETIF_MSG_DRV          | \
 101          NETIF_MSG_PROBE        | \
 102          NETIF_MSG_LINK         | \
 103          NETIF_MSG_TIMER        | \
 104          NETIF_MSG_IFDOWN       | \
 105          NETIF_MSG_IFUP         | \
 106          NETIF_MSG_RX_ERR       | \
 107          NETIF_MSG_TX_ERR)
 108
 109 /* length of time before we decide the hardware is borked,
 110  * and dev->tx_timeout() should be called to fix the problem
 111  */
 112
 113 #define TG3_TX_TIMEOUT                  (5 * HZ)
 114
 115 /* hardware minimum and maximum for a single frame's data payload */
 116 #define TG3_MIN_MTU                     60
 117 #define TG3_MAX_MTU(tp) \
 118         (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
 119
 120 /* These numbers seem to be hard coded in the NIC firmware somehow.
 121  * You can't change the ring sizes, but you can change where you place
 122  * them in the NIC onboard memory.
 123  */
 124 #define TG3_RX_STD_RING_SIZE(tp) \
 125         (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
 126          TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
 127 #define TG3_DEF_RX_RING_PENDING         200
 128 #define TG3_RX_JMB_RING_SIZE(tp) \
 129         (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
 130          TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
 131 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 132 #define TG3_RSS_INDIR_TBL_SIZE          128
 133
 134 /* Do not place this n-ring entries value into the tp struct itself,
 135  * we really want to expose these constants to GCC so that modulo et
 136  * al.  operations are done with shifts and masks instead of with
 137  * hw multiply/modulo instructions.  Another solution would be to
 138  * replace things like '% foo' with '& (foo - 1)'.
 139  */
 140
 141 #define TG3_TX_RING_SIZE                512
 142 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 143
 144 #define TG3_RX_STD_RING_BYTES(tp) \
 145         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
 146 #define TG3_RX_JMB_RING_BYTES(tp) \
 147         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
 148 #define TG3_RX_RCB_RING_BYTES(tp) \
 149         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
 150 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 151                                  TG3_TX_RING_SIZE)
 152 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 153
 154 #define TG3_DMA_BYTE_ENAB               64
 155
 156 #define TG3_RX_STD_DMA_SZ               1536
 157 #define TG3_RX_JMB_DMA_SZ               9046
 158
 159 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 160
 161 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 162 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 163
 164 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
 165         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
 166
 167 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
 168         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
 169
 170 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 171  * that are at least dword aligned when used in PCIX mode.  The driver
 172  * works around this bug by double copying the packet.  This workaround
 173  * is built into the normal double copy length check for efficiency.
 174  *
 175  * However, the double copy is only necessary on those architectures
 176  * where unaligned memory accesses are inefficient.  For those architectures
 177  * where unaligned memory accesses incur little penalty, we can reintegrate
 178  * the 5701 in the normal rx path.  Doing so saves a device structure
 179  * dereference by hardcoding the double copy threshold in place.
 180  */
 181 #define TG3_RX_COPY_THRESHOLD           256
 182 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 183         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 184 #else
 185         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 186 #endif
 187
 188 /* minimum number of free TX descriptors required to wake up TX process */
 189 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 190
 191 #define TG3_RAW_IP_ALIGN 2
 192
 193 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 194
 195 #define FIRMWARE_TG3            "tigon/tg3.bin"
 196 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 197 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 198
 199 static char version[] __devinitdata =
 200         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 201
 202 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 203 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 204 MODULE_LICENSE("GPL");
 205 MODULE_VERSION(DRV_MODULE_VERSION);
 206 MODULE_FIRMWARE(FIRMWARE_TG3);
 207 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 208 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 209
 210 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 211 module_param(tg3_debug, int, 0);
 212 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 213
 214 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 282         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 283         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 284         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 285         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 286         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 287         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
 288         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 289         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 290         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 291         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 292         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 293         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 294         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 295         {}
 296 };
 297
 298 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 299
 300 static const struct {
 301         const char string[ETH_GSTRING_LEN];
 302 } ethtool_stats_keys[] = {
 303         { "rx_octets" },
 304         { "rx_fragments" },
 305         { "rx_ucast_packets" },
 306         { "rx_mcast_packets" },
 307         { "rx_bcast_packets" },
 308         { "rx_fcs_errors" },
 309         { "rx_align_errors" },
 310         { "rx_xon_pause_rcvd" },
 311         { "rx_xoff_pause_rcvd" },
 312         { "rx_mac_ctrl_rcvd" },
 313         { "rx_xoff_entered" },
 314         { "rx_frame_too_long_errors" },
 315         { "rx_jabbers" },
 316         { "rx_undersize_packets" },
 317         { "rx_in_length_errors" },
 318         { "rx_out_length_errors" },
 319         { "rx_64_or_less_octet_packets" },
 320         { "rx_65_to_127_octet_packets" },
 321         { "rx_128_to_255_octet_packets" },
 322         { "rx_256_to_511_octet_packets" },
 323         { "rx_512_to_1023_octet_packets" },
 324         { "rx_1024_to_1522_octet_packets" },
 325         { "rx_1523_to_2047_octet_packets" },
 326         { "rx_2048_to_4095_octet_packets" },
 327         { "rx_4096_to_8191_octet_packets" },
 328         { "rx_8192_to_9022_octet_packets" },
 329
 330         { "tx_octets" },
 331         { "tx_collisions" },
 332
 333         { "tx_xon_sent" },
 334         { "tx_xoff_sent" },
 335         { "tx_flow_control" },
 336         { "tx_mac_errors" },
 337         { "tx_single_collisions" },
 338         { "tx_mult_collisions" },
 339         { "tx_deferred" },
 340         { "tx_excessive_collisions" },
 341         { "tx_late_collisions" },
 342         { "tx_collide_2times" },
 343         { "tx_collide_3times" },
 344         { "tx_collide_4times" },
 345         { "tx_collide_5times" },
 346         { "tx_collide_6times" },
 347         { "tx_collide_7times" },
 348         { "tx_collide_8times" },
 349         { "tx_collide_9times" },
 350         { "tx_collide_10times" },
 351         { "tx_collide_11times" },
 352         { "tx_collide_12times" },
 353         { "tx_collide_13times" },
 354         { "tx_collide_14times" },
 355         { "tx_collide_15times" },
 356         { "tx_ucast_packets" },
 357         { "tx_mcast_packets" },
 358         { "tx_bcast_packets" },
 359         { "tx_carrier_sense_errors" },
 360         { "tx_discards" },
 361         { "tx_errors" },
 362
 363         { "dma_writeq_full" },
 364         { "dma_write_prioq_full" },
 365         { "rxbds_empty" },
 366         { "rx_discards" },
 367         { "rx_errors" },
 368         { "rx_threshold_hit" },
 369
 370         { "dma_readq_full" },
 371         { "dma_read_prioq_full" },
 372         { "tx_comp_queue_full" },
 373
 374         { "ring_set_send_prod_index" },
 375         { "ring_status_update" },
 376         { "nic_irqs" },
 377         { "nic_avoided_irqs" },
 378         { "nic_tx_threshold_hit" },
 379
 380         { "mbuf_lwm_thresh_hit" },
 381 };
 382
 383 #define TG3_NUM_STATS   ARRAY_SIZE(ethtool_stats_keys)
 384
 385
 386 static const struct {
 387         const char string[ETH_GSTRING_LEN];
 388 } ethtool_test_keys[] = {
 389         { "nvram test     (online) " },
 390         { "link test      (online) " },
 391         { "register test  (offline)" },
 392         { "memory test    (offline)" },
 393         { "loopback test  (offline)" },
 394         { "interrupt test (offline)" },
 395 };
 396
 397 #define TG3_NUM_TEST    ARRAY_SIZE(ethtool_test_keys)
 398
 399
 400 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 401 {
 402         writel(val, tp->regs + off);
 403 }
 404
 405 static u32 tg3_read32(struct tg3 *tp, u32 off)
 406 {
 407         return readl(tp->regs + off);
 408 }
 409
 410 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 411 {
 412         writel(val, tp->aperegs + off);
 413 }
 414
 415 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 416 {
 417         return readl(tp->aperegs + off);
 418 }
 419
 420 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 421 {
 422         unsigned long flags;
 423
 424         spin_lock_irqsave(&tp->indirect_lock, flags);
 425         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 426         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 427         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 428 }
 429
 430 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 431 {
 432         writel(val, tp->regs + off);
 433         readl(tp->regs + off);
 434 }
 435
 436 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 437 {
 438         unsigned long flags;
 439         u32 val;
 440
 441         spin_lock_irqsave(&tp->indirect_lock, flags);
 442         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 443         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 444         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 445         return val;
 446 }
 447
 448 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 449 {
 450         unsigned long flags;
 451
 452         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 453                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 454                                        TG3_64BIT_REG_LOW, val);
 455                 return;
 456         }
 457         if (off == TG3_RX_STD_PROD_IDX_REG) {
 458                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 459                                        TG3_64BIT_REG_LOW, val);
 460                 return;
 461         }
 462
 463         spin_lock_irqsave(&tp->indirect_lock, flags);
 464         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 465         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 466         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 467
 468         /* In indirect mode when disabling interrupts, we also need
 469          * to clear the interrupt bit in the GRC local ctrl register.
 470          */
 471         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 472             (val == 0x1)) {
 473                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 474                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 475         }
 476 }
 477
 478 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 479 {
 480         unsigned long flags;
 481         u32 val;
 482
 483         spin_lock_irqsave(&tp->indirect_lock, flags);
 484         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 485         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 486         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 487         return val;
 488 }
 489
 490 /* usec_wait specifies the wait time in usec when writing to certain registers
 491  * where it is unsafe to read back the register without some delay.
 492  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 493  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 494  */
 495 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 496 {
 497         if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
 498                 /* Non-posted methods */
 499                 tp->write32(tp, off, val);
 500         else {
 501                 /* Posted method */
 502                 tg3_write32(tp, off, val);
 503                 if (usec_wait)
 504                         udelay(usec_wait);
 505                 tp->read32(tp, off);
 506         }
 507         /* Wait again after the read for the posted method to guarantee that
 508          * the wait time is met.
 509          */
 510         if (usec_wait)
 511                 udelay(usec_wait);
 512 }
 513
 514 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 515 {
 516         tp->write32_mbox(tp, off, val);
 517         if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
 518                 tp->read32_mbox(tp, off);
 519 }
 520
 521 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 522 {
 523         void __iomem *mbox = tp->regs + off;
 524         writel(val, mbox);
 525         if (tg3_flag(tp, TXD_MBOX_HWBUG))
 526                 writel(val, mbox);
 527         if (tg3_flag(tp, MBOX_WRITE_REORDER))
 528                 readl(mbox);
 529 }
 530
 531 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 532 {
 533         return readl(tp->regs + off + GRCMBOX_BASE);
 534 }
 535
 536 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 537 {
 538         writel(val, tp->regs + off + GRCMBOX_BASE);
 539 }
 540
 541 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 542 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 543 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 544 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 545 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 546
 547 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 548 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 549 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 550 #define tr32(reg)                       tp->read32(tp, reg)
 551
 552 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 553 {
 554         unsigned long flags;
 555
 556         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 557             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 558                 return;
 559
 560         spin_lock_irqsave(&tp->indirect_lock, flags);
 561         if (tg3_flag(tp, SRAM_USE_CONFIG)) {
 562                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 563                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 564
 565                 /* Always leave this as zero. */
 566                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 567         } else {
 568                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 569                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 570
 571                 /* Always leave this as zero. */
 572                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 573         }
 574         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 575 }
 576
 577 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 578 {
 579         unsigned long flags;
 580
 581         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 582             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 583                 *val = 0;
 584                 return;
 585         }
 586
 587         spin_lock_irqsave(&tp->indirect_lock, flags);
 588         if (tg3_flag(tp, SRAM_USE_CONFIG)) {
 589                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 590                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 591
 592                 /* Always leave this as zero. */
 593                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 594         } else {
 595                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 596                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 597
 598                 /* Always leave this as zero. */
 599                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 600         }
 601         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 602 }
 603
 604 static void tg3_ape_lock_init(struct tg3 *tp)
 605 {
 606         int i;
 607         u32 regbase;
 608
 609         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 610                 regbase = TG3_APE_LOCK_GRANT;
 611         else
 612                 regbase = TG3_APE_PER_LOCK_GRANT;
 613
 614         /* Make sure the driver hasn't any stale locks. */
 615         for (i = 0; i < 8; i++)
 616                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 617 }
 618
 619 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 620 {
 621         int i, off;
 622         int ret = 0;
 623         u32 status, req, gnt;
 624
 625         if (!tg3_flag(tp, ENABLE_APE))
 626                 return 0;
 627
 628         switch (locknum) {
 629         case TG3_APE_LOCK_GRC:
 630         case TG3_APE_LOCK_MEM:
 631                 break;
 632         default:
 633                 return -EINVAL;
 634         }
 635
 636         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 637                 req = TG3_APE_LOCK_REQ;
 638                 gnt = TG3_APE_LOCK_GRANT;
 639         } else {
 640                 req = TG3_APE_PER_LOCK_REQ;
 641                 gnt = TG3_APE_PER_LOCK_GRANT;
 642         }
 643
 644         off = 4 * locknum;
 645
 646         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 647
 648         /* Wait for up to 1 millisecond to acquire lock. */
 649         for (i = 0; i < 100; i++) {
 650                 status = tg3_ape_read32(tp, gnt + off);
 651                 if (status == APE_LOCK_GRANT_DRIVER)
 652                         break;
 653                 udelay(10);
 654         }
 655
 656         if (status != APE_LOCK_GRANT_DRIVER) {
 657                 /* Revoke the lock request. */
 658                 tg3_ape_write32(tp, gnt + off,
 659                                 APE_LOCK_GRANT_DRIVER);
 660
 661                 ret = -EBUSY;
 662         }
 663
 664         return ret;
 665 }
 666
 667 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 668 {
 669         u32 gnt;
 670
 671         if (!tg3_flag(tp, ENABLE_APE))
 672                 return;
 673
 674         switch (locknum) {
 675         case TG3_APE_LOCK_GRC:
 676         case TG3_APE_LOCK_MEM:
 677                 break;
 678         default:
 679                 return;
 680         }
 681
 682         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 683                 gnt = TG3_APE_LOCK_GRANT;
 684         else
 685                 gnt = TG3_APE_PER_LOCK_GRANT;
 686
 687         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 688 }
 689
 690 static void tg3_disable_ints(struct tg3 *tp)
 691 {
 692         int i;
 693
 694         tw32(TG3PCI_MISC_HOST_CTRL,
 695              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 696         for (i = 0; i < tp->irq_max; i++)
 697                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 698 }
 699
 700 static void tg3_enable_ints(struct tg3 *tp)
 701 {
 702         int i;
 703
 704         tp->irq_sync = 0;
 705         wmb();
 706
 707         tw32(TG3PCI_MISC_HOST_CTRL,
 708              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 709
 710         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 711         for (i = 0; i < tp->irq_cnt; i++) {
 712                 struct tg3_napi *tnapi = &tp->napi[i];
 713
 714                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 715                 if (tg3_flag(tp, 1SHOT_MSI))
 716                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 717
 718                 tp->coal_now |= tnapi->coal_now;
 719         }
 720
 721         /* Force an initial interrupt */
 722         if (!tg3_flag(tp, TAGGED_STATUS) &&
 723             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 724                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 725         else
 726                 tw32(HOSTCC_MODE, tp->coal_now);
 727
 728         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 729 }
 730
 731 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 732 {
 733         struct tg3 *tp = tnapi->tp;
 734         struct tg3_hw_status *sblk = tnapi->hw_status;
 735         unsigned int work_exists = 0;
 736
 737         /* check for phy events */
 738         if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
 739                 if (sblk->status & SD_STATUS_LINK_CHG)
 740                         work_exists = 1;
 741         }
 742         /* check for RX/TX work to do */
 743         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 744             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 745                 work_exists = 1;
 746
 747         return work_exists;
 748 }
 749
 750 /* tg3_int_reenable
 751  *  similar to tg3_enable_ints, but it accurately determines whether there
 752  *  is new work pending and can return without flushing the PIO write
 753  *  which reenables interrupts
 754  */
 755 static void tg3_int_reenable(struct tg3_napi *tnapi)
 756 {
 757         struct tg3 *tp = tnapi->tp;
 758
 759         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 760         mmiowb();
 761
 762         /* When doing tagged status, this work check is unnecessary.
 763          * The last_tag we write above tells the chip which piece of
 764          * work we've completed.
 765          */
 766         if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
 767                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 768                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 769 }
 770
 771 static void tg3_switch_clocks(struct tg3 *tp)
 772 {
 773         u32 clock_ctrl;
 774         u32 orig_clock_ctrl;
 775
 776         if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
 777                 return;
 778
 779         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 780
 781         orig_clock_ctrl = clock_ctrl;
 782         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 783                        CLOCK_CTRL_CLKRUN_OENABLE |
 784                        0x1f);
 785         tp->pci_clock_ctrl = clock_ctrl;
 786
 787         if (tg3_flag(tp, 5705_PLUS)) {
 788                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 789                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 790                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 791                 }
 792         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 793                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 794                             clock_ctrl |
 795                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 796                             40);
 797                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 798                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 799                             40);
 800         }
 801         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 802 }
 803
 804 #define PHY_BUSY_LOOPS  5000
 805
 806 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 807 {
 808         u32 frame_val;
 809         unsigned int loops;
 810         int ret;
 811
 812         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 813                 tw32_f(MAC_MI_MODE,
 814                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 815                 udelay(80);
 816         }
 817
 818         *val = 0x0;
 819
 820         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 821                       MI_COM_PHY_ADDR_MASK);
 822         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 823                       MI_COM_REG_ADDR_MASK);
 824         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 825
 826         tw32_f(MAC_MI_COM, frame_val);
 827
 828         loops = PHY_BUSY_LOOPS;
 829         while (loops != 0) {
 830                 udelay(10);
 831                 frame_val = tr32(MAC_MI_COM);
 832
 833                 if ((frame_val & MI_COM_BUSY) == 0) {
 834                         udelay(5);
 835                         frame_val = tr32(MAC_MI_COM);
 836                         break;
 837                 }
 838                 loops -= 1;
 839         }
 840
 841         ret = -EBUSY;
 842         if (loops != 0) {
 843                 *val = frame_val & MI_COM_DATA_MASK;
 844                 ret = 0;
 845         }
 846
 847         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 848                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 849                 udelay(80);
 850         }
 851
 852         return ret;
 853 }
 854
 855 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 856 {
 857         u32 frame_val;
 858         unsigned int loops;
 859         int ret;
 860
 861         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 862             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 863                 return 0;
 864
 865         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 866                 tw32_f(MAC_MI_MODE,
 867                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 868                 udelay(80);
 869         }
 870
 871         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 872                       MI_COM_PHY_ADDR_MASK);
 873         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 874                       MI_COM_REG_ADDR_MASK);
 875         frame_val |= (val & MI_COM_DATA_MASK);
 876         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 877
 878         tw32_f(MAC_MI_COM, frame_val);
 879
 880         loops = PHY_BUSY_LOOPS;
 881         while (loops != 0) {
 882                 udelay(10);
 883                 frame_val = tr32(MAC_MI_COM);
 884                 if ((frame_val & MI_COM_BUSY) == 0) {
 885                         udelay(5);
 886                         frame_val = tr32(MAC_MI_COM);
 887                         break;
 888                 }
 889                 loops -= 1;
 890         }
 891
 892         ret = -EBUSY;
 893         if (loops != 0)
 894                 ret = 0;
 895
 896         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 897                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 898                 udelay(80);
 899         }
 900
 901         return ret;
 902 }
 903
 904 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
 905 {
 906         int err;
 907
 908         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
 909         if (err)
 910                 goto done;
 911
 912         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
 913         if (err)
 914                 goto done;
 915
 916         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
 917                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
 918         if (err)
 919                 goto done;
 920
 921         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
 922
 923 done:
 924         return err;
 925 }
 926
 927 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
 928 {
 929         int err;
 930
 931         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
 932         if (err)
 933                 goto done;
 934
 935         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
 936         if (err)
 937                 goto done;
 938
 939         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
 940                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
 941         if (err)
 942                 goto done;
 943
 944         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
 945
 946 done:
 947         return err;
 948 }
 949
 950 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
 951 {
 952         int err;
 953
 954         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
 955         if (!err)
 956                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
 957
 958         return err;
 959 }
 960
 961 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
 962 {
 963         int err;
 964
 965         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
 966         if (!err)
 967                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
 968
 969         return err;
 970 }
 971
 972 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
 973 {
 974         int err;
 975
 976         err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
 977                            (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
 978                            MII_TG3_AUXCTL_SHDWSEL_MISC);
 979         if (!err)
 980                 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
 981
 982         return err;
 983 }
 984
 985 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
 986 {
 987         if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
 988                 set |= MII_TG3_AUXCTL_MISC_WREN;
 989
 990         return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
 991 }
 992
 993 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
 994         tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
 995                              MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
 996                              MII_TG3_AUXCTL_ACTL_TX_6DB)
 997
 998 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
 999         tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1000                              MII_TG3_AUXCTL_ACTL_TX_6DB);
1001
1002 static int tg3_bmcr_reset(struct tg3 *tp)
1003 {
1004         u32 phy_control;
1005         int limit, err;
1006
1007         /* OK, reset it, and poll the BMCR_RESET bit until it
1008          * clears or we time out.
1009          */
1010         phy_control = BMCR_RESET;
1011         err = tg3_writephy(tp, MII_BMCR, phy_control);
1012         if (err != 0)
1013                 return -EBUSY;
1014
1015         limit = 5000;
1016         while (limit--) {
1017                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1018                 if (err != 0)
1019                         return -EBUSY;
1020
1021                 if ((phy_control & BMCR_RESET) == 0) {
1022                         udelay(40);
1023                         break;
1024                 }
1025                 udelay(10);
1026         }
1027         if (limit < 0)
1028                 return -EBUSY;
1029
1030         return 0;
1031 }
1032
1033 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1034 {
1035         struct tg3 *tp = bp->priv;
1036         u32 val;
1037
1038         spin_lock_bh(&tp->lock);
1039
1040         if (tg3_readphy(tp, reg, &val))
1041                 val = -EIO;
1042
1043         spin_unlock_bh(&tp->lock);
1044
1045         return val;
1046 }
1047
1048 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1049 {
1050         struct tg3 *tp = bp->priv;
1051         u32 ret = 0;
1052
1053         spin_lock_bh(&tp->lock);
1054
1055         if (tg3_writephy(tp, reg, val))
1056                 ret = -EIO;
1057
1058         spin_unlock_bh(&tp->lock);
1059
1060         return ret;
1061 }
1062
1063 static int tg3_mdio_reset(struct mii_bus *bp)
1064 {
1065         return 0;
1066 }
1067
1068 static void tg3_mdio_config_5785(struct tg3 *tp)
1069 {
1070         u32 val;
1071         struct phy_device *phydev;
1072
1073         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1074         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1075         case PHY_ID_BCM50610:
1076         case PHY_ID_BCM50610M:
1077                 val = MAC_PHYCFG2_50610_LED_MODES;
1078                 break;
1079         case PHY_ID_BCMAC131:
1080                 val = MAC_PHYCFG2_AC131_LED_MODES;
1081                 break;
1082         case PHY_ID_RTL8211C:
1083                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1084                 break;
1085         case PHY_ID_RTL8201E:
1086                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1087                 break;
1088         default:
1089                 return;
1090         }
1091
1092         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1093                 tw32(MAC_PHYCFG2, val);
1094
1095                 val = tr32(MAC_PHYCFG1);
1096                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1097                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1098                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1099                 tw32(MAC_PHYCFG1, val);
1100
1101                 return;
1102         }
1103
1104         if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1105                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1106                        MAC_PHYCFG2_FMODE_MASK_MASK |
1107                        MAC_PHYCFG2_GMODE_MASK_MASK |
1108                        MAC_PHYCFG2_ACT_MASK_MASK   |
1109                        MAC_PHYCFG2_QUAL_MASK_MASK |
1110                        MAC_PHYCFG2_INBAND_ENABLE;
1111
1112         tw32(MAC_PHYCFG2, val);
1113
1114         val = tr32(MAC_PHYCFG1);
1115         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1116                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1117         if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1118                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1119                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1120                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1121                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1122         }
1123         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1124                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1125         tw32(MAC_PHYCFG1, val);
1126
1127         val = tr32(MAC_EXT_RGMII_MODE);
1128         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1129                  MAC_RGMII_MODE_RX_QUALITY |
1130                  MAC_RGMII_MODE_RX_ACTIVITY |
1131                  MAC_RGMII_MODE_RX_ENG_DET |
1132                  MAC_RGMII_MODE_TX_ENABLE |
1133                  MAC_RGMII_MODE_TX_LOWPWR |
1134                  MAC_RGMII_MODE_TX_RESET);
1135         if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1136                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1137                         val |= MAC_RGMII_MODE_RX_INT_B |
1138                                MAC_RGMII_MODE_RX_QUALITY |
1139                                MAC_RGMII_MODE_RX_ACTIVITY |
1140                                MAC_RGMII_MODE_RX_ENG_DET;
1141                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1142                         val |= MAC_RGMII_MODE_TX_ENABLE |
1143                                MAC_RGMII_MODE_TX_LOWPWR |
1144                                MAC_RGMII_MODE_TX_RESET;
1145         }
1146         tw32(MAC_EXT_RGMII_MODE, val);
1147 }
1148
1149 static void tg3_mdio_start(struct tg3 *tp)
1150 {
1151         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1152         tw32_f(MAC_MI_MODE, tp->mi_mode);
1153         udelay(80);
1154
1155         if (tg3_flag(tp, MDIOBUS_INITED) &&
1156             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1157                 tg3_mdio_config_5785(tp);
1158 }
1159
1160 static int tg3_mdio_init(struct tg3 *tp)
1161 {
1162         int i;
1163         u32 reg;
1164         struct phy_device *phydev;
1165
1166         if (tg3_flag(tp, 5717_PLUS)) {
1167                 u32 is_serdes;
1168
1169                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1170
1171                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1172                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1173                 else
1174                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1175                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1176                 if (is_serdes)
1177                         tp->phy_addr += 7;
1178         } else
1179                 tp->phy_addr = TG3_PHY_MII_ADDR;
1180
1181         tg3_mdio_start(tp);
1182
1183         if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1184                 return 0;
1185
1186         tp->mdio_bus = mdiobus_alloc();
1187         if (tp->mdio_bus == NULL)
1188                 return -ENOMEM;
1189
1190         tp->mdio_bus->name     = "tg3 mdio bus";
1191         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1192                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1193         tp->mdio_bus->priv     = tp;
1194         tp->mdio_bus->parent   = &tp->pdev->dev;
1195         tp->mdio_bus->read     = &tg3_mdio_read;
1196         tp->mdio_bus->write    = &tg3_mdio_write;
1197         tp->mdio_bus->reset    = &tg3_mdio_reset;
1198         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1199         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1200
1201         for (i = 0; i < PHY_MAX_ADDR; i++)
1202                 tp->mdio_bus->irq[i] = PHY_POLL;
1203
1204         /* The bus registration will look for all the PHYs on the mdio bus.
1205          * Unfortunately, it does not ensure the PHY is powered up before
1206          * accessing the PHY ID registers.  A chip reset is the
1207          * quickest way to bring the device back to an operational state..
1208          */
1209         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1210                 tg3_bmcr_reset(tp);
1211
1212         i = mdiobus_register(tp->mdio_bus);
1213         if (i) {
1214                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1215                 mdiobus_free(tp->mdio_bus);
1216                 return i;
1217         }
1218
1219         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1220
1221         if (!phydev || !phydev->drv) {
1222                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1223                 mdiobus_unregister(tp->mdio_bus);
1224                 mdiobus_free(tp->mdio_bus);
1225                 return -ENODEV;
1226         }
1227
1228         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1229         case PHY_ID_BCM57780:
1230                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1231                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1232                 break;
1233         case PHY_ID_BCM50610:
1234         case PHY_ID_BCM50610M:
1235                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1236                                      PHY_BRCM_RX_REFCLK_UNUSED |
1237                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1238                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1239                 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1240                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1241                 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1242                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1243                 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1244                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1245                 /* fallthru */
1246         case PHY_ID_RTL8211C:
1247                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1248                 break;
1249         case PHY_ID_RTL8201E:
1250         case PHY_ID_BCMAC131:
1251                 phydev->interface = PHY_INTERFACE_MODE_MII;
1252                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1253                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1254                 break;
1255         }
1256
1257         tg3_flag_set(tp, MDIOBUS_INITED);
1258
1259         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1260                 tg3_mdio_config_5785(tp);
1261
1262         return 0;
1263 }
1264
1265 static void tg3_mdio_fini(struct tg3 *tp)
1266 {
1267         if (tg3_flag(tp, MDIOBUS_INITED)) {
1268                 tg3_flag_clear(tp, MDIOBUS_INITED);
1269                 mdiobus_unregister(tp->mdio_bus);
1270                 mdiobus_free(tp->mdio_bus);
1271         }
1272 }
1273
1274 /* tp->lock is held. */
1275 static inline void tg3_generate_fw_event(struct tg3 *tp)
1276 {
1277         u32 val;
1278
1279         val = tr32(GRC_RX_CPU_EVENT);
1280         val |= GRC_RX_CPU_DRIVER_EVENT;
1281         tw32_f(GRC_RX_CPU_EVENT, val);
1282
1283         tp->last_event_jiffies = jiffies;
1284 }
1285
1286 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1287
1288 /* tp->lock is held. */
1289 static void tg3_wait_for_event_ack(struct tg3 *tp)
1290 {
1291         int i;
1292         unsigned int delay_cnt;
1293         long time_remain;
1294
1295         /* If enough time has passed, no wait is necessary. */
1296         time_remain = (long)(tp->last_event_jiffies + 1 +
1297                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1298                       (long)jiffies;
1299         if (time_remain < 0)
1300                 return;
1301
1302         /* Check if we can shorten the wait time. */
1303         delay_cnt = jiffies_to_usecs(time_remain);
1304         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1305                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1306         delay_cnt = (delay_cnt >> 3) + 1;
1307
1308         for (i = 0; i < delay_cnt; i++) {
1309                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1310                         break;
1311                 udelay(8);
1312         }
1313 }
1314
1315 /* tp->lock is held. */
1316 static void tg3_ump_link_report(struct tg3 *tp)
1317 {
1318         u32 reg;
1319         u32 val;
1320
1321         if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1322                 return;
1323
1324         tg3_wait_for_event_ack(tp);
1325
1326         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1327
1328         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1329
1330         val = 0;
1331         if (!tg3_readphy(tp, MII_BMCR, &reg))
1332                 val = reg << 16;
1333         if (!tg3_readphy(tp, MII_BMSR, &reg))
1334                 val |= (reg & 0xffff);
1335         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1336
1337         val = 0;
1338         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1339                 val = reg << 16;
1340         if (!tg3_readphy(tp, MII_LPA, &reg))
1341                 val |= (reg & 0xffff);
1342         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1343
1344         val = 0;
1345         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1346                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1347                         val = reg << 16;
1348                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1349                         val |= (reg & 0xffff);
1350         }
1351         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1352
1353         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1354                 val = reg << 16;
1355         else
1356                 val = 0;
1357         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1358
1359         tg3_generate_fw_event(tp);
1360 }
1361
1362 static void tg3_link_report(struct tg3 *tp)
1363 {
1364         if (!netif_carrier_ok(tp->dev)) {
1365                 netif_info(tp, link, tp->dev, "Link is down\n");
1366                 tg3_ump_link_report(tp);
1367         } else if (netif_msg_link(tp)) {
1368                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1369                             (tp->link_config.active_speed == SPEED_1000 ?
1370                              1000 :
1371                              (tp->link_config.active_speed == SPEED_100 ?
1372                               100 : 10)),
1373                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1374                              "full" : "half"));
1375
1376                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1377                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1378                             "on" : "off",
1379                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1380                             "on" : "off");
1381
1382                 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1383                         netdev_info(tp->dev, "EEE is %s\n",
1384                                     tp->setlpicnt ? "enabled" : "disabled");
1385
1386                 tg3_ump_link_report(tp);
1387         }
1388 }
1389
1390 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1391 {
1392         u16 miireg;
1393
1394         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1395                 miireg = ADVERTISE_PAUSE_CAP;
1396         else if (flow_ctrl & FLOW_CTRL_TX)
1397                 miireg = ADVERTISE_PAUSE_ASYM;
1398         else if (flow_ctrl & FLOW_CTRL_RX)
1399                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1400         else
1401                 miireg = 0;
1402
1403         return miireg;
1404 }
1405
1406 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1407 {
1408         u16 miireg;
1409
1410         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1411                 miireg = ADVERTISE_1000XPAUSE;
1412         else if (flow_ctrl & FLOW_CTRL_TX)
1413                 miireg = ADVERTISE_1000XPSE_ASYM;
1414         else if (flow_ctrl & FLOW_CTRL_RX)
1415                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1416         else
1417                 miireg = 0;
1418
1419         return miireg;
1420 }
1421
1422 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1423 {
1424         u8 cap = 0;
1425
1426         if (lcladv & ADVERTISE_1000XPAUSE) {
1427                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1428                         if (rmtadv & LPA_1000XPAUSE)
1429                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1430                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1431                                 cap = FLOW_CTRL_RX;
1432                 } else {
1433                         if (rmtadv & LPA_1000XPAUSE)
1434                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1435                 }
1436         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1437                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1438                         cap = FLOW_CTRL_TX;
1439         }
1440
1441         return cap;
1442 }
1443
1444 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1445 {
1446         u8 autoneg;
1447         u8 flowctrl = 0;
1448         u32 old_rx_mode = tp->rx_mode;
1449         u32 old_tx_mode = tp->tx_mode;
1450
1451         if (tg3_flag(tp, USE_PHYLIB))
1452                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1453         else
1454                 autoneg = tp->link_config.autoneg;
1455
1456         if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1457                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1458                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1459                 else
1460                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1461         } else
1462                 flowctrl = tp->link_config.flowctrl;
1463
1464         tp->link_config.active_flowctrl = flowctrl;
1465
1466         if (flowctrl & FLOW_CTRL_RX)
1467                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1468         else
1469                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1470
1471         if (old_rx_mode != tp->rx_mode)
1472                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1473
1474         if (flowctrl & FLOW_CTRL_TX)
1475                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1476         else
1477                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1478
1479         if (old_tx_mode != tp->tx_mode)
1480                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1481 }
1482
1483 static void tg3_adjust_link(struct net_device *dev)
1484 {
1485         u8 oldflowctrl, linkmesg = 0;
1486         u32 mac_mode, lcl_adv, rmt_adv;
1487         struct tg3 *tp = netdev_priv(dev);
1488         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1489
1490         spin_lock_bh(&tp->lock);
1491
1492         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1493                                     MAC_MODE_HALF_DUPLEX);
1494
1495         oldflowctrl = tp->link_config.active_flowctrl;
1496
1497         if (phydev->link) {
1498                 lcl_adv = 0;
1499                 rmt_adv = 0;
1500
1501                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1502                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1503                 else if (phydev->speed == SPEED_1000 ||
1504                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1505                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1506                 else
1507                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1508
1509                 if (phydev->duplex == DUPLEX_HALF)
1510                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1511                 else {
1512                         lcl_adv = tg3_advert_flowctrl_1000T(
1513                                   tp->link_config.flowctrl);
1514
1515                         if (phydev->pause)
1516                                 rmt_adv = LPA_PAUSE_CAP;
1517                         if (phydev->asym_pause)
1518                                 rmt_adv |= LPA_PAUSE_ASYM;
1519                 }
1520
1521                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1522         } else
1523                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1524
1525         if (mac_mode != tp->mac_mode) {
1526                 tp->mac_mode = mac_mode;
1527                 tw32_f(MAC_MODE, tp->mac_mode);
1528                 udelay(40);
1529         }
1530
1531         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1532                 if (phydev->speed == SPEED_10)
1533                         tw32(MAC_MI_STAT,
1534                              MAC_MI_STAT_10MBPS_MODE |
1535                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1536                 else
1537                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1538         }
1539
1540         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1541                 tw32(MAC_TX_LENGTHS,
1542                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1543                       (6 << TX_LENGTHS_IPG_SHIFT) |
1544                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1545         else
1546                 tw32(MAC_TX_LENGTHS,
1547                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1548                       (6 << TX_LENGTHS_IPG_SHIFT) |
1549                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1550
1551         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1552             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1553             phydev->speed != tp->link_config.active_speed ||
1554             phydev->duplex != tp->link_config.active_duplex ||
1555             oldflowctrl != tp->link_config.active_flowctrl)
1556                 linkmesg = 1;
1557
1558         tp->link_config.active_speed = phydev->speed;
1559         tp->link_config.active_duplex = phydev->duplex;
1560
1561         spin_unlock_bh(&tp->lock);
1562
1563         if (linkmesg)
1564                 tg3_link_report(tp);
1565 }
1566
1567 static int tg3_phy_init(struct tg3 *tp)
1568 {
1569         struct phy_device *phydev;
1570
1571         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1572                 return 0;
1573
1574         /* Bring the PHY back to a known state. */
1575         tg3_bmcr_reset(tp);
1576
1577         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1578
1579         /* Attach the MAC to the PHY. */
1580         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1581                              phydev->dev_flags, phydev->interface);
1582         if (IS_ERR(phydev)) {
1583                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1584                 return PTR_ERR(phydev);
1585         }
1586
1587         /* Mask with MAC supported features. */
1588         switch (phydev->interface) {
1589         case PHY_INTERFACE_MODE_GMII:
1590         case PHY_INTERFACE_MODE_RGMII:
1591                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1592                         phydev->supported &= (PHY_GBIT_FEATURES |
1593                                               SUPPORTED_Pause |
1594                                               SUPPORTED_Asym_Pause);
1595                         break;
1596                 }
1597                 /* fallthru */
1598         case PHY_INTERFACE_MODE_MII:
1599                 phydev->supported &= (PHY_BASIC_FEATURES |
1600                                       SUPPORTED_Pause |
1601                                       SUPPORTED_Asym_Pause);
1602                 break;
1603         default:
1604                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1605                 return -EINVAL;
1606         }
1607
1608         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1609
1610         phydev->advertising = phydev->supported;
1611
1612         return 0;
1613 }
1614
1615 static void tg3_phy_start(struct tg3 *tp)
1616 {
1617         struct phy_device *phydev;
1618
1619         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1620                 return;
1621
1622         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1623
1624         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1625                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1626                 phydev->speed = tp->link_config.orig_speed;
1627                 phydev->duplex = tp->link_config.orig_duplex;
1628                 phydev->autoneg = tp->link_config.orig_autoneg;
1629                 phydev->advertising = tp->link_config.orig_advertising;
1630         }
1631
1632         phy_start(phydev);
1633
1634         phy_start_aneg(phydev);
1635 }
1636
1637 static void tg3_phy_stop(struct tg3 *tp)
1638 {
1639         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1640                 return;
1641
1642         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1643 }
1644
1645 static void tg3_phy_fini(struct tg3 *tp)
1646 {
1647         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1648                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1649                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1650         }
1651 }
1652
1653 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1654 {
1655         u32 phytest;
1656
1657         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1658                 u32 phy;
1659
1660                 tg3_writephy(tp, MII_TG3_FET_TEST,
1661                              phytest | MII_TG3_FET_SHADOW_EN);
1662                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1663                         if (enable)
1664                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1665                         else
1666                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1667                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1668                 }
1669                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1670         }
1671 }
1672
1673 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1674 {
1675         u32 reg;
1676
1677         if (!tg3_flag(tp, 5705_PLUS) ||
1678             (tg3_flag(tp, 5717_PLUS) &&
1679              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1680                 return;
1681
1682         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1683                 tg3_phy_fet_toggle_apd(tp, enable);
1684                 return;
1685         }
1686
1687         reg = MII_TG3_MISC_SHDW_WREN |
1688               MII_TG3_MISC_SHDW_SCR5_SEL |
1689               MII_TG3_MISC_SHDW_SCR5_LPED |
1690               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1691               MII_TG3_MISC_SHDW_SCR5_SDTL |
1692               MII_TG3_MISC_SHDW_SCR5_C125OE;
1693         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1694                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1695
1696         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1697
1698
1699         reg = MII_TG3_MISC_SHDW_WREN |
1700               MII_TG3_MISC_SHDW_APD_SEL |
1701               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1702         if (enable)
1703                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1704
1705         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1706 }
1707
1708 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1709 {
1710         u32 phy;
1711
1712         if (!tg3_flag(tp, 5705_PLUS) ||
1713             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1714                 return;
1715
1716         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1717                 u32 ephy;
1718
1719                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1720                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1721
1722                         tg3_writephy(tp, MII_TG3_FET_TEST,
1723                                      ephy | MII_TG3_FET_SHADOW_EN);
1724                         if (!tg3_readphy(tp, reg, &phy)) {
1725                                 if (enable)
1726                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1727                                 else
1728                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1729                                 tg3_writephy(tp, reg, phy);
1730                         }
1731                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1732                 }
1733         } else {
1734                 int ret;
1735
1736                 ret = tg3_phy_auxctl_read(tp,
1737                                           MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
1738                 if (!ret) {
1739                         if (enable)
1740                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1741                         else
1742                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1743                         tg3_phy_auxctl_write(tp,
1744                                              MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
1745                 }
1746         }
1747 }
1748
1749 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1750 {
1751         int ret;
1752         u32 val;
1753
1754         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1755                 return;
1756
1757         ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
1758         if (!ret)
1759                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
1760                                      val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1761 }
1762
1763 static void tg3_phy_apply_otp(struct tg3 *tp)
1764 {
1765         u32 otp, phy;
1766
1767         if (!tp->phy_otp)
1768                 return;
1769
1770         otp = tp->phy_otp;
1771
1772         if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
1773                 return;
1774
1775         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1776         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1777         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1778
1779         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1780               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1781         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1782
1783         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1784         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1785         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1786
1787         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1788         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1789
1790         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1791         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1792
1793         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1794               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1795         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1796
1797         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
1798 }
1799
1800 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1801 {
1802         u32 val;
1803
1804         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1805                 return;
1806
1807         tp->setlpicnt = 0;
1808
1809         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1810             current_link_up == 1 &&
1811             tp->link_config.active_duplex == DUPLEX_FULL &&
1812             (tp->link_config.active_speed == SPEED_100 ||
1813              tp->link_config.active_speed == SPEED_1000)) {
1814                 u32 eeectl;
1815
1816                 if (tp->link_config.active_speed == SPEED_1000)
1817                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1818                 else
1819                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1820
1821                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1822
1823                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1824                                   TG3_CL45_D7_EEERES_STAT, &val);
1825
1826                 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1827                     val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1828                         tp->setlpicnt = 2;
1829         }
1830
1831         if (!tp->setlpicnt) {
1832                 val = tr32(TG3_CPMU_EEE_MODE);
1833                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1834         }
1835 }
1836
1837 static void tg3_phy_eee_enable(struct tg3 *tp)
1838 {
1839         u32 val;
1840
1841         if (tp->link_config.active_speed == SPEED_1000 &&
1842             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1843              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
1844              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
1845             !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
1846                 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0003);
1847                 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
1848         }
1849
1850         val = tr32(TG3_CPMU_EEE_MODE);
1851         tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
1852 }
1853
1854 static int tg3_wait_macro_done(struct tg3 *tp)
1855 {
1856         int limit = 100;
1857
1858         while (limit--) {
1859                 u32 tmp32;
1860
1861                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1862                         if ((tmp32 & 0x1000) == 0)
1863                                 break;
1864                 }
1865         }
1866         if (limit < 0)
1867                 return -EBUSY;
1868
1869         return 0;
1870 }
1871
1872 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1873 {
1874         static const u32 test_pat[4][6] = {
1875         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1876         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1877         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1878         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1879         };
1880         int chan;
1881
1882         for (chan = 0; chan < 4; chan++) {
1883                 int i;
1884
1885                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1886                              (chan * 0x2000) | 0x0200);
1887                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1888
1889                 for (i = 0; i < 6; i++)
1890                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1891                                      test_pat[chan][i]);
1892
1893                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1894                 if (tg3_wait_macro_done(tp)) {
1895                         *resetp = 1;
1896                         return -EBUSY;
1897                 }
1898
1899                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1900                              (chan * 0x2000) | 0x0200);
1901                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1902                 if (tg3_wait_macro_done(tp)) {
1903                         *resetp = 1;
1904                         return -EBUSY;
1905                 }
1906
1907                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1908                 if (tg3_wait_macro_done(tp)) {
1909                         *resetp = 1;
1910                         return -EBUSY;
1911                 }
1912
1913                 for (i = 0; i < 6; i += 2) {
1914                         u32 low, high;
1915
1916                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1917                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1918                             tg3_wait_macro_done(tp)) {
1919                                 *resetp = 1;
1920                                 return -EBUSY;
1921                         }
1922                         low &= 0x7fff;
1923                         high &= 0x000f;
1924                         if (low != test_pat[chan][i] ||
1925                             high != test_pat[chan][i+1]) {
1926                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1927                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1928                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1929
1930                                 return -EBUSY;
1931                         }
1932                 }
1933         }
1934
1935         return 0;
1936 }
1937
1938 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1939 {
1940         int chan;
1941
1942         for (chan = 0; chan < 4; chan++) {
1943                 int i;
1944
1945                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1946                              (chan * 0x2000) | 0x0200);
1947                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1948                 for (i = 0; i < 6; i++)
1949                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1950                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1951                 if (tg3_wait_macro_done(tp))
1952                         return -EBUSY;
1953         }
1954
1955         return 0;
1956 }
1957
1958 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1959 {
1960         u32 reg32, phy9_orig;
1961         int retries, do_phy_reset, err;
1962
1963         retries = 10;
1964         do_phy_reset = 1;
1965         do {
1966                 if (do_phy_reset) {
1967                         err = tg3_bmcr_reset(tp);
1968                         if (err)
1969                                 return err;
1970                         do_phy_reset = 0;
1971                 }
1972
1973                 /* Disable transmitter and interrupt.  */
1974                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1975                         continue;
1976
1977                 reg32 |= 0x3000;
1978                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1979
1980                 /* Set full-duplex, 1000 mbps.  */
1981                 tg3_writephy(tp, MII_BMCR,
1982                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1983
1984                 /* Set to master mode.  */
1985                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1986                         continue;
1987
1988                 tg3_writephy(tp, MII_TG3_CTRL,
1989                              (MII_TG3_CTRL_AS_MASTER |
1990                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1991
1992                 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
1993                 if (err)
1994                         return err;
1995
1996                 /* Block the PHY control access.  */
1997                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1998
1999                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2000                 if (!err)
2001                         break;
2002         } while (--retries);
2003
2004         err = tg3_phy_reset_chanpat(tp);
2005         if (err)
2006                 return err;
2007
2008         tg3_phydsp_write(tp, 0x8005, 0x0000);
2009
2010         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2011         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2012
2013         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2014
2015         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
2016
2017         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2018                 reg32 &= ~0x3000;
2019                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2020         } else if (!err)
2021                 err = -EBUSY;
2022
2023         return err;
2024 }
2025
2026 /* This will reset the tigon3 PHY if there is no valid
2027  * link unless the FORCE argument is non-zero.
2028  */
2029 static int tg3_phy_reset(struct tg3 *tp)
2030 {
2031         u32 val, cpmuctrl;
2032         int err;
2033
2034         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2035                 val = tr32(GRC_MISC_CFG);
2036                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2037                 udelay(40);
2038         }
2039         err  = tg3_readphy(tp, MII_BMSR, &val);
2040         err |= tg3_readphy(tp, MII_BMSR, &val);
2041         if (err != 0)
2042                 return -EBUSY;
2043
2044         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2045                 netif_carrier_off(tp->dev);
2046                 tg3_link_report(tp);
2047         }
2048
2049         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2050             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2051             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2052                 err = tg3_phy_reset_5703_4_5(tp);
2053                 if (err)
2054                         return err;
2055                 goto out;
2056         }
2057
2058         cpmuctrl = 0;
2059         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2060             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2061                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2062                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2063                         tw32(TG3_CPMU_CTRL,
2064                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2065         }
2066
2067         err = tg3_bmcr_reset(tp);
2068         if (err)
2069                 return err;
2070
2071         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2072                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2073                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2074
2075                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2076         }
2077
2078         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2079             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2080                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2081                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2082                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2083                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2084                         udelay(40);
2085                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2086                 }
2087         }
2088
2089         if (tg3_flag(tp, 5717_PLUS) &&
2090             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2091                 return 0;
2092
2093         tg3_phy_apply_otp(tp);
2094
2095         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2096                 tg3_phy_toggle_apd(tp, true);
2097         else
2098                 tg3_phy_toggle_apd(tp, false);
2099
2100 out:
2101         if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2102             !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2103                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2104                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2105                 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2106         }
2107
2108         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2109                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2110                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2111         }
2112
2113         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2114                 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2115                         tg3_phydsp_write(tp, 0x000a, 0x310b);
2116                         tg3_phydsp_write(tp, 0x201f, 0x9506);
2117                         tg3_phydsp_write(tp, 0x401f, 0x14e2);
2118                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2119                 }
2120         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2121                 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2122                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2123                         if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2124                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2125                                 tg3_writephy(tp, MII_TG3_TEST1,
2126                                              MII_TG3_TEST1_TRIM_EN | 0x4);
2127                         } else
2128                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2129
2130                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2131                 }
2132         }
2133
2134         /* Set Extended packet length bit (bit 14) on all chips that */
2135         /* support jumbo frames */
2136         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2137                 /* Cannot do read-modify-write on 5401 */
2138                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2139         } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2140                 /* Set bit 14 with read-modify-write to preserve other bits */
2141                 err = tg3_phy_auxctl_read(tp,
2142                                           MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2143                 if (!err)
2144                         tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2145                                            val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2146         }
2147
2148         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2149          * jumbo frames transmission.
2150          */
2151         if (tg3_flag(tp, JUMBO_CAPABLE)) {
2152                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2153                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2154                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2155         }
2156
2157         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2158                 /* adjust output voltage */
2159                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2160         }
2161
2162         tg3_phy_toggle_automdix(tp, 1);
2163         tg3_phy_set_wirespeed(tp);
2164         return 0;
2165 }
2166
2167 static void tg3_frob_aux_power(struct tg3 *tp)
2168 {
2169         bool need_vaux = false;
2170
2171         /* The GPIOs do something completely different on 57765. */
2172         if (!tg3_flag(tp, IS_NIC) ||
2173             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2174             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2175                 return;
2176
2177         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2178              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2179              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2180              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
2181             tp->pdev_peer != tp->pdev) {
2182                 struct net_device *dev_peer;
2183
2184                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2185
2186                 /* remove_one() may have been run on the peer. */
2187                 if (dev_peer) {
2188                         struct tg3 *tp_peer = netdev_priv(dev_peer);
2189
2190                         if (tg3_flag(tp_peer, INIT_COMPLETE))
2191                                 return;
2192
2193                         if (tg3_flag(tp_peer, WOL_ENABLE) ||
2194                             tg3_flag(tp_peer, ENABLE_ASF))
2195                                 need_vaux = true;
2196                 }
2197         }
2198
2199         if (tg3_flag(tp, WOL_ENABLE) || tg3_flag(tp, ENABLE_ASF))
2200                 need_vaux = true;
2201
2202         if (need_vaux) {
2203                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2204                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2205                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2206                                     (GRC_LCLCTRL_GPIO_OE0 |
2207                                      GRC_LCLCTRL_GPIO_OE1 |
2208                                      GRC_LCLCTRL_GPIO_OE2 |
2209                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2210                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2211                                     100);
2212                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2213                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2214                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2215                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2216                                              GRC_LCLCTRL_GPIO_OE1 |
2217                                              GRC_LCLCTRL_GPIO_OE2 |
2218                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2219                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2220                                              tp->grc_local_ctrl;
2221                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2222
2223                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2224                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2225
2226                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2227                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2228                 } else {
2229                         u32 no_gpio2;
2230                         u32 grc_local_ctrl = 0;
2231
2232                         /* Workaround to prevent overdrawing Amps. */
2233                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2234                             ASIC_REV_5714) {
2235                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2236                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2237                                             grc_local_ctrl, 100);
2238                         }
2239
2240                         /* On 5753 and variants, GPIO2 cannot be used. */
2241                         no_gpio2 = tp->nic_sram_data_cfg &
2242                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2243
2244                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2245                                          GRC_LCLCTRL_GPIO_OE1 |
2246                                          GRC_LCLCTRL_GPIO_OE2 |
2247                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2248                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2249                         if (no_gpio2) {
2250                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2251                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2252                         }
2253                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2254                                                     grc_local_ctrl, 100);
2255
2256                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2257
2258                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2259                                                     grc_local_ctrl, 100);
2260
2261                         if (!no_gpio2) {
2262                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2263                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2264                                             grc_local_ctrl, 100);
2265                         }
2266                 }
2267         } else {
2268                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2269                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2270                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2271                                     (GRC_LCLCTRL_GPIO_OE1 |
2272                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2273
2274                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2275                                     GRC_LCLCTRL_GPIO_OE1, 100);
2276
2277                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2278                                     (GRC_LCLCTRL_GPIO_OE1 |
2279                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2280                 }
2281         }
2282 }
2283
2284 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2285 {
2286         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2287                 return 1;
2288         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2289                 if (speed != SPEED_10)
2290                         return 1;
2291         } else if (speed == SPEED_10)
2292                 return 1;
2293
2294         return 0;
2295 }
2296
2297 static int tg3_setup_phy(struct tg3 *, int);
2298
2299 #define RESET_KIND_SHUTDOWN     0
2300 #define RESET_KIND_INIT         1
2301 #define RESET_KIND_SUSPEND      2
2302
2303 static void tg3_write_sig_post_reset(struct tg3 *, int);
2304 static int tg3_halt_cpu(struct tg3 *, u32);
2305
2306 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2307 {
2308         u32 val;
2309
2310         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2311                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2312                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2313                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2314
2315                         sg_dig_ctrl |=
2316                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2317                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2318                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2319                 }
2320                 return;
2321         }
2322
2323         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2324                 tg3_bmcr_reset(tp);
2325                 val = tr32(GRC_MISC_CFG);
2326                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2327                 udelay(40);
2328                 return;
2329         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2330                 u32 phytest;
2331                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2332                         u32 phy;
2333
2334                         tg3_writephy(tp, MII_ADVERTISE, 0);
2335                         tg3_writephy(tp, MII_BMCR,
2336                                      BMCR_ANENABLE | BMCR_ANRESTART);
2337
2338                         tg3_writephy(tp, MII_TG3_FET_TEST,
2339                                      phytest | MII_TG3_FET_SHADOW_EN);
2340                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2341                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2342                                 tg3_writephy(tp,
2343                                              MII_TG3_FET_SHDW_AUXMODE4,
2344                                              phy);
2345                         }
2346                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2347                 }
2348                 return;
2349         } else if (do_low_power) {
2350                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2351                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2352
2353                 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2354                       MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2355                       MII_TG3_AUXCTL_PCTL_VREG_11V;
2356                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2357         }
2358
2359         /* The PHY should not be powered down on some chips because
2360          * of bugs.
2361          */
2362         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2363             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2364             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2365              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2366                 return;
2367
2368         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2369             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2370                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2371                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2372                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2373                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2374         }
2375
2376         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2377 }
2378
2379 /* tp->lock is held. */
2380 static int tg3_nvram_lock(struct tg3 *tp)
2381 {
2382         if (tg3_flag(tp, NVRAM)) {
2383                 int i;
2384
2385                 if (tp->nvram_lock_cnt == 0) {
2386                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2387                         for (i = 0; i < 8000; i++) {
2388                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2389                                         break;
2390                                 udelay(20);
2391                         }
2392                         if (i == 8000) {
2393                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2394                                 return -ENODEV;
2395                         }
2396                 }
2397                 tp->nvram_lock_cnt++;
2398         }
2399         return 0;
2400 }
2401
2402 /* tp->lock is held. */
2403 static void tg3_nvram_unlock(struct tg3 *tp)
2404 {
2405         if (tg3_flag(tp, NVRAM)) {
2406                 if (tp->nvram_lock_cnt > 0)
2407                         tp->nvram_lock_cnt--;
2408                 if (tp->nvram_lock_cnt == 0)
2409                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2410         }
2411 }
2412
2413 /* tp->lock is held. */
2414 static void tg3_enable_nvram_access(struct tg3 *tp)
2415 {
2416         if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2417                 u32 nvaccess = tr32(NVRAM_ACCESS);
2418
2419                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2420         }
2421 }
2422
2423 /* tp->lock is held. */
2424 static void tg3_disable_nvram_access(struct tg3 *tp)
2425 {
2426         if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2427                 u32 nvaccess = tr32(NVRAM_ACCESS);
2428
2429                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2430         }
2431 }
2432
2433 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2434                                         u32 offset, u32 *val)
2435 {
2436         u32 tmp;
2437         int i;
2438
2439         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2440                 return -EINVAL;
2441
2442         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2443                                         EEPROM_ADDR_DEVID_MASK |
2444                                         EEPROM_ADDR_READ);
2445         tw32(GRC_EEPROM_ADDR,
2446              tmp |
2447              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2448              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2449               EEPROM_ADDR_ADDR_MASK) |
2450              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2451
2452         for (i = 0; i < 1000; i++) {
2453                 tmp = tr32(GRC_EEPROM_ADDR);
2454
2455                 if (tmp & EEPROM_ADDR_COMPLETE)
2456                         break;
2457                 msleep(1);
2458         }
2459         if (!(tmp & EEPROM_ADDR_COMPLETE))
2460                 return -EBUSY;
2461
2462         tmp = tr32(GRC_EEPROM_DATA);
2463
2464         /*
2465          * The data will always be opposite the native endian
2466          * format.  Perform a blind byteswap to compensate.
2467          */
2468         *val = swab32(tmp);
2469
2470         return 0;
2471 }
2472
2473 #define NVRAM_CMD_TIMEOUT 10000
2474
2475 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2476 {
2477         int i;
2478
2479         tw32(NVRAM_CMD, nvram_cmd);
2480         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2481                 udelay(10);
2482                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2483                         udelay(10);
2484                         break;
2485                 }
2486         }
2487
2488         if (i == NVRAM_CMD_TIMEOUT)
2489                 return -EBUSY;
2490
2491         return 0;
2492 }
2493
2494 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2495 {
2496         if (tg3_flag(tp, NVRAM) &&
2497             tg3_flag(tp, NVRAM_BUFFERED) &&
2498             tg3_flag(tp, FLASH) &&
2499             !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2500             (tp->nvram_jedecnum == JEDEC_ATMEL))
2501
2502                 addr = ((addr / tp->nvram_pagesize) <<
2503                         ATMEL_AT45DB0X1B_PAGE_POS) +
2504                        (addr % tp->nvram_pagesize);
2505
2506         return addr;
2507 }
2508
2509 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2510 {
2511         if (tg3_flag(tp, NVRAM) &&
2512             tg3_flag(tp, NVRAM_BUFFERED) &&
2513             tg3_flag(tp, FLASH) &&
2514             !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2515             (tp->nvram_jedecnum == JEDEC_ATMEL))
2516
2517                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2518                         tp->nvram_pagesize) +
2519                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2520
2521         return addr;
2522 }
2523
2524 /* NOTE: Data read in from NVRAM is byteswapped according to
2525  * the byteswapping settings for all other register accesses.
2526  * tg3 devices are BE devices, so on a BE machine, the data
2527  * returned will be exactly as it is seen in NVRAM.  On a LE
2528  * machine, the 32-bit value will be byteswapped.
2529  */
2530 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2531 {
2532         int ret;
2533
2534         if (!tg3_flag(tp, NVRAM))
2535                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2536
2537         offset = tg3_nvram_phys_addr(tp, offset);
2538
2539         if (offset > NVRAM_ADDR_MSK)
2540                 return -EINVAL;
2541
2542         ret = tg3_nvram_lock(tp);
2543         if (ret)
2544                 return ret;
2545
2546         tg3_enable_nvram_access(tp);
2547
2548         tw32(NVRAM_ADDR, offset);
2549         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2550                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2551
2552         if (ret == 0)
2553                 *val = tr32(NVRAM_RDDATA);
2554
2555         tg3_disable_nvram_access(tp);
2556
2557         tg3_nvram_unlock(tp);
2558
2559         return ret;
2560 }
2561
2562 /* Ensures NVRAM data is in bytestream format. */
2563 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2564 {
2565         u32 v;
2566         int res = tg3_nvram_read(tp, offset, &v);
2567         if (!res)
2568                 *val = cpu_to_be32(v);
2569         return res;
2570 }
2571
2572 /* tp->lock is held. */
2573 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2574 {
2575         u32 addr_high, addr_low;
2576         int i;
2577
2578         addr_high = ((tp->dev->dev_addr[0] << 8) |
2579                      tp->dev->dev_addr[1]);
2580         addr_low = ((tp->dev->dev_addr[2] << 24) |
2581                     (tp->dev->dev_addr[3] << 16) |
2582                     (tp->dev->dev_addr[4] <<  8) |
2583                     (tp->dev->dev_addr[5] <<  0));
2584         for (i = 0; i < 4; i++) {
2585                 if (i == 1 && skip_mac_1)
2586                         continue;
2587                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2588                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2589         }
2590
2591         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2592             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2593                 for (i = 0; i < 12; i++) {
2594                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2595                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2596                 }
2597         }
2598
2599         addr_high = (tp->dev->dev_addr[0] +
2600                      tp->dev->dev_addr[1] +
2601                      tp->dev->dev_addr[2] +
2602                      tp->dev->dev_addr[3] +
2603                      tp->dev->dev_addr[4] +
2604                      tp->dev->dev_addr[5]) &
2605                 TX_BACKOFF_SEED_MASK;
2606         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2607 }
2608
2609 static void tg3_enable_register_access(struct tg3 *tp)
2610 {
2611         /*
2612          * Make sure register accesses (indirect or otherwise) will function
2613          * correctly.
2614          */
2615         pci_write_config_dword(tp->pdev,
2616                                TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2617 }
2618
2619 static int tg3_power_up(struct tg3 *tp)
2620 {
2621         tg3_enable_register_access(tp);
2622
2623         pci_set_power_state(tp->pdev, PCI_D0);
2624
2625         /* Switch out of Vaux if it is a NIC */
2626         if (tg3_flag(tp, IS_NIC))
2627                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2628
2629         return 0;
2630 }
2631
2632 static int tg3_power_down_prepare(struct tg3 *tp)
2633 {
2634         u32 misc_host_ctrl;
2635         bool device_should_wake, do_low_power;
2636
2637         tg3_enable_register_access(tp);
2638
2639         /* Restore the CLKREQ setting. */
2640         if (tg3_flag(tp, CLKREQ_BUG)) {
2641                 u16 lnkctl;
2642
2643                 pci_read_config_word(tp->pdev,
2644                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2645                                      &lnkctl);
2646                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2647                 pci_write_config_word(tp->pdev,
2648                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2649                                       lnkctl);
2650         }
2651
2652         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2653         tw32(TG3PCI_MISC_HOST_CTRL,
2654              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2655
2656         device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2657                              tg3_flag(tp, WOL_ENABLE);
2658
2659         if (tg3_flag(tp, USE_PHYLIB)) {
2660                 do_low_power = false;
2661                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2662                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2663                         struct phy_device *phydev;
2664                         u32 phyid, advertising;
2665
2666                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2667
2668                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2669
2670                         tp->link_config.orig_speed = phydev->speed;
2671                         tp->link_config.orig_duplex = phydev->duplex;
2672                         tp->link_config.orig_autoneg = phydev->autoneg;
2673                         tp->link_config.orig_advertising = phydev->advertising;
2674
2675                         advertising = ADVERTISED_TP |
2676                                       ADVERTISED_Pause |
2677                                       ADVERTISED_Autoneg |
2678                                       ADVERTISED_10baseT_Half;
2679
2680                         if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
2681                                 if (tg3_flag(tp, WOL_SPEED_100MB))
2682                                         advertising |=
2683                                                 ADVERTISED_100baseT_Half |
2684                                                 ADVERTISED_100baseT_Full |
2685                                                 ADVERTISED_10baseT_Full;
2686                                 else
2687                                         advertising |= ADVERTISED_10baseT_Full;
2688                         }
2689
2690                         phydev->advertising = advertising;
2691
2692                         phy_start_aneg(phydev);
2693
2694                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2695                         if (phyid != PHY_ID_BCMAC131) {
2696                                 phyid &= PHY_BCM_OUI_MASK;
2697                                 if (phyid == PHY_BCM_OUI_1 ||
2698                                     phyid == PHY_BCM_OUI_2 ||
2699                                     phyid == PHY_BCM_OUI_3)
2700                                         do_low_power = true;
2701                         }
2702                 }
2703         } else {
2704                 do_low_power = true;
2705
2706                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2707                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2708                         tp->link_config.orig_speed = tp->link_config.speed;
2709                         tp->link_config.orig_duplex = tp->link_config.duplex;
2710                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2711                 }
2712
2713                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2714                         tp->link_config.speed = SPEED_10;
2715                         tp->link_config.duplex = DUPLEX_HALF;
2716                         tp->link_config.autoneg = AUTONEG_ENABLE;
2717                         tg3_setup_phy(tp, 0);
2718                 }
2719         }
2720
2721         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2722                 u32 val;
2723
2724                 val = tr32(GRC_VCPU_EXT_CTRL);
2725                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2726         } else if (!tg3_flag(tp, ENABLE_ASF)) {
2727                 int i;
2728                 u32 val;
2729
2730                 for (i = 0; i < 200; i++) {
2731                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2732                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2733                                 break;
2734                         msleep(1);
2735                 }
2736         }
2737         if (tg3_flag(tp, WOL_CAP))
2738                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2739                                                      WOL_DRV_STATE_SHUTDOWN |
2740                                                      WOL_DRV_WOL |
2741                                                      WOL_SET_MAGIC_PKT);
2742
2743         if (device_should_wake) {
2744                 u32 mac_mode;
2745
2746                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2747                         if (do_low_power &&
2748                             !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
2749                                 tg3_phy_auxctl_write(tp,
2750                                                MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
2751                                                MII_TG3_AUXCTL_PCTL_WOL_EN |
2752                                                MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2753                                                MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
2754                                 udelay(40);
2755                         }
2756
2757                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2758                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2759                         else
2760                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2761
2762                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2763                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2764                             ASIC_REV_5700) {
2765                                 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
2766                                              SPEED_100 : SPEED_10;
2767                                 if (tg3_5700_link_polarity(tp, speed))
2768                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2769                                 else
2770                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2771                         }
2772                 } else {
2773                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2774                 }
2775
2776                 if (!tg3_flag(tp, 5750_PLUS))
2777                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2778
2779                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2780                 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
2781                     (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
2782                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2783
2784                 if (tg3_flag(tp, ENABLE_APE))
2785                         mac_mode |= MAC_MODE_APE_TX_EN |
2786                                     MAC_MODE_APE_RX_EN |
2787                                     MAC_MODE_TDE_ENABLE;
2788
2789                 tw32_f(MAC_MODE, mac_mode);
2790                 udelay(100);
2791
2792                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2793                 udelay(10);
2794         }
2795
2796         if (!tg3_flag(tp, WOL_SPEED_100MB) &&
2797             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2798              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2799                 u32 base_val;
2800
2801                 base_val = tp->pci_clock_ctrl;
2802                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2803                              CLOCK_CTRL_TXCLK_DISABLE);
2804
2805                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2806                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2807         } else if (tg3_flag(tp, 5780_CLASS) ||
2808                    tg3_flag(tp, CPMU_PRESENT) ||
2809                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2810                 /* do nothing */
2811         } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
2812                 u32 newbits1, newbits2;
2813
2814                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2815                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2816                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2817                                     CLOCK_CTRL_TXCLK_DISABLE |
2818                                     CLOCK_CTRL_ALTCLK);
2819                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2820                 } else if (tg3_flag(tp, 5705_PLUS)) {
2821                         newbits1 = CLOCK_CTRL_625_CORE;
2822                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2823                 } else {
2824                         newbits1 = CLOCK_CTRL_ALTCLK;
2825                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2826                 }
2827
2828                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2829                             40);
2830
2831                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2832                             40);
2833
2834                 if (!tg3_flag(tp, 5705_PLUS)) {
2835                         u32 newbits3;
2836
2837                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2838                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2839                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2840                                             CLOCK_CTRL_TXCLK_DISABLE |
2841                                             CLOCK_CTRL_44MHZ_CORE);
2842                         } else {
2843                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2844                         }
2845
2846                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2847                                     tp->pci_clock_ctrl | newbits3, 40);
2848                 }
2849         }
2850
2851         if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
2852                 tg3_power_down_phy(tp, do_low_power);
2853
2854         tg3_frob_aux_power(tp);
2855
2856         /* Workaround for unstable PLL clock */
2857         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2858             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2859                 u32 val = tr32(0x7d00);
2860
2861                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2862                 tw32(0x7d00, val);
2863                 if (!tg3_flag(tp, ENABLE_ASF)) {
2864                         int err;
2865
2866                         err = tg3_nvram_lock(tp);
2867                         tg3_halt_cpu(tp, RX_CPU_BASE);
2868                         if (!err)
2869                                 tg3_nvram_unlock(tp);
2870                 }
2871         }
2872
2873         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2874
2875         return 0;
2876 }
2877
2878 static void tg3_power_down(struct tg3 *tp)
2879 {
2880         tg3_power_down_prepare(tp);
2881
2882         pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
2883         pci_set_power_state(tp->pdev, PCI_D3hot);
2884 }
2885
2886 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2887 {
2888         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2889         case MII_TG3_AUX_STAT_10HALF:
2890                 *speed = SPEED_10;
2891                 *duplex = DUPLEX_HALF;
2892                 break;
2893
2894         case MII_TG3_AUX_STAT_10FULL:
2895                 *speed = SPEED_10;
2896                 *duplex = DUPLEX_FULL;
2897                 break;
2898
2899         case MII_TG3_AUX_STAT_100HALF:
2900                 *speed = SPEED_100;
2901                 *duplex = DUPLEX_HALF;
2902                 break;
2903
2904         case MII_TG3_AUX_STAT_100FULL:
2905                 *speed = SPEED_100;
2906                 *duplex = DUPLEX_FULL;
2907                 break;
2908
2909         case MII_TG3_AUX_STAT_1000HALF:
2910                 *speed = SPEED_1000;
2911                 *duplex = DUPLEX_HALF;
2912                 break;
2913
2914         case MII_TG3_AUX_STAT_1000FULL:
2915                 *speed = SPEED_1000;
2916                 *duplex = DUPLEX_FULL;
2917                 break;
2918
2919         default:
2920                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2921                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2922                                  SPEED_10;
2923                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2924                                   DUPLEX_HALF;
2925                         break;
2926                 }
2927                 *speed = SPEED_INVALID;
2928                 *duplex = DUPLEX_INVALID;
2929                 break;
2930         }
2931 }
2932
2933 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
2934 {
2935         int err = 0;
2936         u32 val, new_adv;
2937
2938         new_adv = ADVERTISE_CSMA;
2939         if (advertise & ADVERTISED_10baseT_Half)
2940                 new_adv |= ADVERTISE_10HALF;
2941         if (advertise & ADVERTISED_10baseT_Full)
2942                 new_adv |= ADVERTISE_10FULL;
2943         if (advertise & ADVERTISED_100baseT_Half)
2944                 new_adv |= ADVERTISE_100HALF;
2945         if (advertise & ADVERTISED_100baseT_Full)
2946                 new_adv |= ADVERTISE_100FULL;
2947
2948         new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
2949
2950         err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
2951         if (err)
2952                 goto done;
2953
2954         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2955                 goto done;
2956
2957         new_adv = 0;
2958         if (advertise & ADVERTISED_1000baseT_Half)
2959                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2960         if (advertise & ADVERTISED_1000baseT_Full)
2961                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2962
2963         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2964             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2965                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2966                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2967
2968         err = tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2969         if (err)
2970                 goto done;
2971
2972         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2973                 goto done;
2974
2975         tw32(TG3_CPMU_EEE_MODE,
2976              tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2977
2978         err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2979         if (!err) {
2980                 u32 err2;
2981
2982                 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
2983                 case ASIC_REV_5717:
2984                 case ASIC_REV_57765:
2985                         if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2986                                 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
2987                                                  MII_TG3_DSP_CH34TP2_HIBW01);
2988                         /* Fall through */
2989                 case ASIC_REV_5719:
2990                         val = MII_TG3_DSP_TAP26_ALNOKO |
2991                               MII_TG3_DSP_TAP26_RMRXSTO |
2992                               MII_TG3_DSP_TAP26_OPCSINPT;
2993                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2994                 }
2995
2996                 val = 0;
2997                 /* Advertise 100-BaseTX EEE ability */
2998                 if (advertise & ADVERTISED_100baseT_Full)
2999                         val |= MDIO_AN_EEE_ADV_100TX;
3000                 /* Advertise 1000-BaseT EEE ability */
3001                 if (advertise & ADVERTISED_1000baseT_Full)
3002                         val |= MDIO_AN_EEE_ADV_1000T;
3003                 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3004
3005                 err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
3006                 if (!err)
3007                         err = err2;
3008         }
3009
3010 done:
3011         return err;
3012 }
3013
3014 static void tg3_phy_copper_begin(struct tg3 *tp)
3015 {
3016         u32 new_adv;
3017         int i;
3018
3019         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
3020                 new_adv = ADVERTISED_10baseT_Half |
3021                           ADVERTISED_10baseT_Full;
3022                 if (tg3_flag(tp, WOL_SPEED_100MB))
3023                         new_adv |= ADVERTISED_100baseT_Half |
3024                                    ADVERTISED_100baseT_Full;
3025
3026                 tg3_phy_autoneg_cfg(tp, new_adv,
3027                                     FLOW_CTRL_TX | FLOW_CTRL_RX);
3028         } else if (tp->link_config.speed == SPEED_INVALID) {
3029                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3030                         tp->link_config.advertising &=
3031                                 ~(ADVERTISED_1000baseT_Half |
3032                                   ADVERTISED_1000baseT_Full);
3033
3034                 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
3035                                     tp->link_config.flowctrl);
3036         } else {
3037                 /* Asking for a specific link mode. */
3038                 if (tp->link_config.speed == SPEED_1000) {
3039                         if (tp->link_config.duplex == DUPLEX_FULL)
3040                                 new_adv = ADVERTISED_1000baseT_Full;
3041                         else
3042                                 new_adv = ADVERTISED_1000baseT_Half;
3043                 } else if (tp->link_config.speed == SPEED_100) {
3044                         if (tp->link_config.duplex == DUPLEX_FULL)
3045                                 new_adv = ADVERTISED_100baseT_Full;
3046                         else
3047                                 new_adv = ADVERTISED_100baseT_Half;
3048                 } else {
3049                         if (tp->link_config.duplex == DUPLEX_FULL)
3050                                 new_adv = ADVERTISED_10baseT_Full;
3051                         else
3052                                 new_adv = ADVERTISED_10baseT_Half;
3053                 }
3054
3055                 tg3_phy_autoneg_cfg(tp, new_adv,
3056                                     tp->link_config.flowctrl);
3057         }
3058
3059         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3060             tp->link_config.speed != SPEED_INVALID) {
3061                 u32 bmcr, orig_bmcr;
3062
3063                 tp->link_config.active_speed = tp->link_config.speed;
3064                 tp->link_config.active_duplex = tp->link_config.duplex;
3065
3066                 bmcr = 0;
3067                 switch (tp->link_config.speed) {
3068                 default:
3069                 case SPEED_10:
3070                         break;
3071
3072                 case SPEED_100:
3073                         bmcr |= BMCR_SPEED100;
3074                         break;
3075
3076                 case SPEED_1000:
3077                         bmcr |= TG3_BMCR_SPEED1000;
3078                         break;
3079                 }
3080
3081                 if (tp->link_config.duplex == DUPLEX_FULL)
3082                         bmcr |= BMCR_FULLDPLX;
3083
3084                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3085                     (bmcr != orig_bmcr)) {
3086                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3087                         for (i = 0; i < 1500; i++) {
3088                                 u32 tmp;
3089
3090                                 udelay(10);
3091                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3092                                     tg3_readphy(tp, MII_BMSR, &tmp))
3093                                         continue;
3094                                 if (!(tmp & BMSR_LSTATUS)) {
3095                                         udelay(40);
3096                                         break;
3097                                 }
3098                         }
3099                         tg3_writephy(tp, MII_BMCR, bmcr);
3100                         udelay(40);
3101                 }
3102         } else {
3103                 tg3_writephy(tp, MII_BMCR,
3104                              BMCR_ANENABLE | BMCR_ANRESTART);
3105         }
3106 }
3107
3108 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3109 {
3110         int err;
3111
3112         /* Turn off tap power management. */
3113         /* Set Extended packet length bit */
3114         err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
3115
3116         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3117         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3118         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3119         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3120         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3121
3122         udelay(40);
3123
3124         return err;
3125 }
3126
3127 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3128 {
3129         u32 adv_reg, all_mask = 0;
3130
3131         if (mask & ADVERTISED_10baseT_Half)
3132                 all_mask |= ADVERTISE_10HALF;
3133         if (mask & ADVERTISED_10baseT_Full)
3134                 all_mask |= ADVERTISE_10FULL;
3135         if (mask & ADVERTISED_100baseT_Half)
3136                 all_mask |= ADVERTISE_100HALF;
3137         if (mask & ADVERTISED_100baseT_Full)
3138                 all_mask |= ADVERTISE_100FULL;
3139
3140         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3141                 return 0;
3142
3143         if ((adv_reg & all_mask) != all_mask)
3144                 return 0;
3145         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3146                 u32 tg3_ctrl;
3147
3148                 all_mask = 0;
3149                 if (mask & ADVERTISED_1000baseT_Half)
3150                         all_mask |= ADVERTISE_1000HALF;
3151                 if (mask & ADVERTISED_1000baseT_Full)
3152                         all_mask |= ADVERTISE_1000FULL;
3153
3154                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3155                         return 0;
3156
3157                 if ((tg3_ctrl & all_mask) != all_mask)
3158                         return 0;
3159         }
3160         return 1;
3161 }
3162
3163 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3164 {
3165         u32 curadv, reqadv;
3166
3167         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3168                 return 1;
3169
3170         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3171         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3172
3173         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3174                 if (curadv != reqadv)
3175                         return 0;
3176
3177                 if (tg3_flag(tp, PAUSE_AUTONEG))
3178                         tg3_readphy(tp, MII_LPA, rmtadv);
3179         } else {
3180                 /* Reprogram the advertisement register, even if it
3181                  * does not affect the current link.  If the link
3182                  * gets renegotiated in the future, we can save an
3183                  * additional renegotiation cycle by advertising
3184                  * it correctly in the first place.
3185                  */
3186                 if (curadv != reqadv) {
3187                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3188                                      ADVERTISE_PAUSE_ASYM);
3189                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3190                 }
3191         }
3192
3193         return 1;
3194 }
3195
3196 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3197 {
3198         int current_link_up;
3199         u32 bmsr, val;
3200         u32 lcl_adv, rmt_adv;
3201         u16 current_speed;
3202         u8 current_duplex;
3203         int i, err;
3204
3205         tw32(MAC_EVENT, 0);
3206
3207         tw32_f(MAC_STATUS,
3208              (MAC_STATUS_SYNC_CHANGED |
3209               MAC_STATUS_CFG_CHANGED |
3210               MAC_STATUS_MI_COMPLETION |
3211               MAC_STATUS_LNKSTATE_CHANGED));
3212         udelay(40);
3213
3214         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3215                 tw32_f(MAC_MI_MODE,
3216                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3217                 udelay(80);
3218         }
3219
3220         tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
3221
3222         /* Some third-party PHYs need to be reset on link going
3223          * down.
3224          */
3225         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3226              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3227              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3228             netif_carrier_ok(tp->dev)) {
3229                 tg3_readphy(tp, MII_BMSR, &bmsr);
3230                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3231                     !(bmsr & BMSR_LSTATUS))
3232                         force_reset = 1;
3233         }
3234         if (force_reset)
3235                 tg3_phy_reset(tp);
3236
3237         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3238                 tg3_readphy(tp, MII_BMSR, &bmsr);
3239                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3240                     !tg3_flag(tp, INIT_COMPLETE))
3241                         bmsr = 0;
3242
3243                 if (!(bmsr & BMSR_LSTATUS)) {
3244                         err = tg3_init_5401phy_dsp(tp);
3245                         if (err)
3246                                 return err;
3247
3248                         tg3_readphy(tp, MII_BMSR, &bmsr);
3249                         for (i = 0; i < 1000; i++) {
3250                                 udelay(10);
3251                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3252                                     (bmsr & BMSR_LSTATUS)) {
3253                                         udelay(40);
3254                                         break;
3255                                 }
3256                         }
3257
3258                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3259                             TG3_PHY_REV_BCM5401_B0 &&
3260                             !(bmsr & BMSR_LSTATUS) &&
3261                             tp->link_config.active_speed == SPEED_1000) {
3262                                 err = tg3_phy_reset(tp);
3263                                 if (!err)
3264                                         err = tg3_init_5401phy_dsp(tp);
3265                                 if (err)
3266                                         return err;
3267                         }
3268                 }
3269         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3270                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3271                 /* 5701 {A0,B0} CRC bug workaround */
3272                 tg3_writephy(tp, 0x15, 0x0a75);
3273                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3274                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3275                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3276         }
3277
3278         /* Clear pending interrupts... */
3279         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3280         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3281
3282         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3283                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3284         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3285                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3286
3287         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3288             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3289                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3290                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3291                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3292                 else
3293                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3294         }
3295
3296         current_link_up = 0;
3297         current_speed = SPEED_INVALID;
3298         current_duplex = DUPLEX_INVALID;
3299
3300         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3301                 err = tg3_phy_auxctl_read(tp,
3302                                           MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3303                                           &val);
3304                 if (!err && !(val & (1 << 10))) {
3305                         tg3_phy_auxctl_write(tp,
3306                                              MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3307                                              val | (1 << 10));
3308                         goto relink;
3309                 }
3310         }
3311
3312         bmsr = 0;
3313         for (i = 0; i < 100; i++) {
3314                 tg3_readphy(tp, MII_BMSR, &bmsr);
3315                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3316                     (bmsr & BMSR_LSTATUS))
3317                         break;
3318                 udelay(40);
3319         }
3320
3321         if (bmsr & BMSR_LSTATUS) {
3322                 u32 aux_stat, bmcr;
3323
3324                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3325                 for (i = 0; i < 2000; i++) {
3326                         udelay(10);
3327                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3328                             aux_stat)
3329                                 break;
3330                 }
3331
3332                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3333                                              &current_speed,
3334                                              &current_duplex);
3335
3336                 bmcr = 0;
3337                 for (i = 0; i < 200; i++) {
3338                         tg3_readphy(tp, MII_BMCR, &bmcr);
3339                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3340                                 continue;
3341                         if (bmcr && bmcr != 0x7fff)
3342                                 break;
3343                         udelay(10);
3344                 }
3345
3346                 lcl_adv = 0;
3347                 rmt_adv = 0;
3348
3349                 tp->link_config.active_speed = current_speed;
3350                 tp->link_config.active_duplex = current_duplex;
3351
3352                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3353                         if ((bmcr & BMCR_ANENABLE) &&
3354                             tg3_copper_is_advertising_all(tp,
3355                                                 tp->link_config.advertising)) {
3356                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3357                                                                   &rmt_adv))
3358                                         current_link_up = 1;
3359                         }
3360                 } else {
3361                         if (!(bmcr & BMCR_ANENABLE) &&
3362                             tp->link_config.speed == current_speed &&
3363                             tp->link_config.duplex == current_duplex &&
3364                             tp->link_config.flowctrl ==
3365                             tp->link_config.active_flowctrl) {
3366                                 current_link_up = 1;
3367                         }
3368                 }
3369
3370                 if (current_link_up == 1 &&
3371                     tp->link_config.active_duplex == DUPLEX_FULL)
3372                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3373         }
3374
3375 relink:
3376         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3377                 tg3_phy_copper_begin(tp);
3378
3379                 tg3_readphy(tp, MII_BMSR, &bmsr);
3380                 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
3381                     (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
3382                         current_link_up = 1;
3383         }
3384
3385         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3386         if (current_link_up == 1) {
3387                 if (tp->link_config.active_speed == SPEED_100 ||
3388                     tp->link_config.active_speed == SPEED_10)
3389                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3390                 else
3391                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3392         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3393                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3394         else
3395                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3396
3397         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3398         if (tp->link_config.active_duplex == DUPLEX_HALF)
3399                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3400
3401         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3402                 if (current_link_up == 1 &&
3403                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3404                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3405                 else
3406                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3407         }
3408
3409         /* ??? Without this setting Netgear GA302T PHY does not
3410          * ??? send/receive packets...
3411          */
3412         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3413             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3414                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3415                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3416                 udelay(80);
3417         }
3418
3419         tw32_f(MAC_MODE, tp->mac_mode);
3420         udelay(40);
3421
3422         tg3_phy_eee_adjust(tp, current_link_up);
3423
3424         if (tg3_flag(tp, USE_LINKCHG_REG)) {
3425                 /* Polled via timer. */
3426                 tw32_f(MAC_EVENT, 0);
3427         } else {
3428                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3429         }
3430         udelay(40);
3431
3432         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3433             current_link_up == 1 &&
3434             tp->link_config.active_speed == SPEED_1000 &&
3435             (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
3436                 udelay(120);
3437                 tw32_f(MAC_STATUS,
3438                      (MAC_STATUS_SYNC_CHANGED |
3439                       MAC_STATUS_CFG_CHANGED));
3440                 udelay(40);
3441                 tg3_write_mem(tp,
3442                               NIC_SRAM_FIRMWARE_MBOX,
3443                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3444         }
3445
3446         /* Prevent send BD corruption. */
3447         if (tg3_flag(tp, CLKREQ_BUG)) {
3448                 u16 oldlnkctl, newlnkctl;
3449
3450                 pci_read_config_word(tp->pdev,
3451                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3452                                      &oldlnkctl);
3453                 if (tp->link_config.active_speed == SPEED_100 ||
3454                     tp->link_config.active_speed == SPEED_10)
3455                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3456                 else
3457                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3458                 if (newlnkctl != oldlnkctl)
3459                         pci_write_config_word(tp->pdev,
3460                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3461                                               newlnkctl);
3462         }
3463
3464         if (current_link_up != netif_carrier_ok(tp->dev)) {
3465                 if (current_link_up)
3466                         netif_carrier_on(tp->dev);
3467                 else
3468                         netif_carrier_off(tp->dev);
3469                 tg3_link_report(tp);
3470         }
3471
3472         return 0;
3473 }
3474
3475 struct tg3_fiber_aneginfo {
3476         int state;
3477 #define ANEG_STATE_UNKNOWN              0
3478 #define ANEG_STATE_AN_ENABLE            1
3479 #define ANEG_STATE_RESTART_INIT         2
3480 #define ANEG_STATE_RESTART              3
3481 #define ANEG_STATE_DISABLE_LINK_OK      4
3482 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3483 #define ANEG_STATE_ABILITY_DETECT       6
3484 #define ANEG_STATE_ACK_DETECT_INIT      7
3485 #define ANEG_STATE_ACK_DETECT           8
3486 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3487 #define ANEG_STATE_COMPLETE_ACK         10
3488 #define ANEG_STATE_IDLE_DETECT_INIT     11
3489 #define ANEG_STATE_IDLE_DETECT          12
3490 #define ANEG_STATE_LINK_OK              13
3491 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3492 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3493
3494         u32 flags;
3495 #define MR_AN_ENABLE            0x00000001
3496 #define MR_RESTART_AN           0x00000002
3497 #define MR_AN_COMPLETE          0x00000004
3498 #define MR_PAGE_RX              0x00000008
3499 #define MR_NP_LOADED            0x00000010
3500 #define MR_TOGGLE_TX            0x00000020
3501 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3502 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3503 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3504 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3505 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3506 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3507 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3508 #define MR_TOGGLE_RX            0x00002000
3509 #define MR_NP_RX                0x00004000
3510
3511 #define MR_LINK_OK              0x80000000
3512
3513         unsigned long link_time, cur_time;
3514
3515         u32 ability_match_cfg;
3516         int ability_match_count;
3517
3518         char ability_match, idle_match, ack_match;
3519
3520         u32 txconfig, rxconfig;
3521 #define ANEG_CFG_NP             0x00000080
3522 #define ANEG_CFG_ACK            0x00000040
3523 #define ANEG_CFG_RF2            0x00000020
3524 #define ANEG_CFG_RF1            0x00000010
3525 #define ANEG_CFG_PS2            0x00000001
3526 #define ANEG_CFG_PS1            0x00008000
3527 #define ANEG_CFG_HD             0x00004000
3528 #define ANEG_CFG_FD             0x00002000
3529 #define ANEG_CFG_INVAL          0x00001f06
3530
3531 };
3532 #define ANEG_OK         0
3533 #define ANEG_DONE       1
3534 #define ANEG_TIMER_ENAB 2
3535 #define ANEG_FAILED     -1
3536
3537 #define ANEG_STATE_SETTLE_TIME  10000
3538
3539 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3540                                    struct tg3_fiber_aneginfo *ap)
3541 {
3542         u16 flowctrl;
3543         unsigned long delta;
3544         u32 rx_cfg_reg;
3545         int ret;
3546
3547         if (ap->state == ANEG_STATE_UNKNOWN) {
3548                 ap->rxconfig = 0;
3549                 ap->link_time = 0;
3550                 ap->cur_time = 0;
3551                 ap->ability_match_cfg = 0;
3552                 ap->ability_match_count = 0;
3553                 ap->ability_match = 0;
3554                 ap->idle_match = 0;
3555                 ap->ack_match = 0;
3556         }
3557         ap->cur_time++;
3558
3559         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3560                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3561
3562                 if (rx_cfg_reg != ap->ability_match_cfg) {
3563                         ap->ability_match_cfg = rx_cfg_reg;
3564                         ap->ability_match = 0;
3565                         ap->ability_match_count = 0;
3566                 } else {
3567                         if (++ap->ability_match_count > 1) {
3568                                 ap->ability_match = 1;
3569                                 ap->ability_match_cfg = rx_cfg_reg;
3570                         }
3571                 }
3572                 if (rx_cfg_reg & ANEG_CFG_ACK)
3573                         ap->ack_match = 1;
3574                 else
3575                         ap->ack_match = 0;
3576
3577                 ap->idle_match = 0;
3578         } else {
3579                 ap->idle_match = 1;
3580                 ap->ability_match_cfg = 0;
3581                 ap->ability_match_count = 0;
3582                 ap->ability_match = 0;
3583                 ap->ack_match = 0;
3584
3585                 rx_cfg_reg = 0;
3586         }
3587
3588         ap->rxconfig = rx_cfg_reg;
3589         ret = ANEG_OK;
3590
3591         switch (ap->state) {
3592         case ANEG_STATE_UNKNOWN:
3593                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3594                         ap->state = ANEG_STATE_AN_ENABLE;
3595
3596                 /* fallthru */
3597         case ANEG_STATE_AN_ENABLE:
3598                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3599                 if (ap->flags & MR_AN_ENABLE) {
3600                         ap->link_time = 0;
3601                         ap->cur_time = 0;
3602                         ap->ability_match_cfg = 0;
3603                         ap->ability_match_count = 0;
3604                         ap->ability_match = 0;
3605                         ap->idle_match = 0;
3606                         ap->ack_match = 0;
3607
3608                         ap->state = ANEG_STATE_RESTART_INIT;
3609                 } else {
3610                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3611                 }
3612                 break;
3613
3614         case ANEG_STATE_RESTART_INIT:
3615                 ap->link_time = ap->cur_time;
3616                 ap->flags &= ~(MR_NP_LOADED);
3617                 ap->txconfig = 0;
3618                 tw32(MAC_TX_AUTO_NEG, 0);
3619                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3620                 tw32_f(MAC_MODE, tp->mac_mode);
3621                 udelay(40);
3622
3623                 ret = ANEG_TIMER_ENAB;
3624                 ap->state = ANEG_STATE_RESTART;
3625
3626                 /* fallthru */
3627         case ANEG_STATE_RESTART:
3628                 delta = ap->cur_time - ap->link_time;
3629                 if (delta > ANEG_STATE_SETTLE_TIME)
3630                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3631                 else
3632                         ret = ANEG_TIMER_ENAB;
3633                 break;
3634
3635         case ANEG_STATE_DISABLE_LINK_OK:
3636                 ret = ANEG_DONE;
3637                 break;
3638
3639         case ANEG_STATE_ABILITY_DETECT_INIT:
3640                 ap->flags &= ~(MR_TOGGLE_TX);
3641                 ap->txconfig = ANEG_CFG_FD;
3642                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3643                 if (flowctrl & ADVERTISE_1000XPAUSE)
3644                         ap->txconfig |= ANEG_CFG_PS1;
3645                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3646                         ap->txconfig |= ANEG_CFG_PS2;
3647                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3648                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3649                 tw32_f(MAC_MODE, tp->mac_mode);
3650                 udelay(40);
3651
3652                 ap->state = ANEG_STATE_ABILITY_DETECT;
3653                 break;
3654
3655         case ANEG_STATE_ABILITY_DETECT:
3656                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3657                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3658                 break;
3659
3660         case ANEG_STATE_ACK_DETECT_INIT:
3661                 ap->txconfig |= ANEG_CFG_ACK;
3662                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3663                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3664                 tw32_f(MAC_MODE, tp->mac_mode);
3665                 udelay(40);
3666
3667                 ap->state = ANEG_STATE_ACK_DETECT;
3668
3669                 /* fallthru */
3670         case ANEG_STATE_ACK_DETECT:
3671                 if (ap->ack_match != 0) {
3672                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3673                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3674                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3675                         } else {
3676                                 ap->state = ANEG_STATE_AN_ENABLE;
3677                         }
3678                 } else if (ap->ability_match != 0 &&
3679                            ap->rxconfig == 0) {
3680                         ap->state = ANEG_STATE_AN_ENABLE;
3681                 }
3682                 break;
3683
3684         case ANEG_STATE_COMPLETE_ACK_INIT:
3685                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3686                         ret = ANEG_FAILED;
3687                         break;
3688                 }
3689                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3690                                MR_LP_ADV_HALF_DUPLEX |
3691                                MR_LP_ADV_SYM_PAUSE |
3692                                MR_LP_ADV_ASYM_PAUSE |
3693                                MR_LP_ADV_REMOTE_FAULT1 |
3694                                MR_LP_ADV_REMOTE_FAULT2 |
3695                                MR_LP_ADV_NEXT_PAGE |
3696                                MR_TOGGLE_RX |
3697                                MR_NP_RX);
3698                 if (ap->rxconfig & ANEG_CFG_FD)
3699                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3700                 if (ap->rxconfig & ANEG_CFG_HD)
3701                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3702                 if (ap->rxconfig & ANEG_CFG_PS1)
3703                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3704                 if (ap->rxconfig & ANEG_CFG_PS2)
3705                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3706                 if (ap->rxconfig & ANEG_CFG_RF1)
3707                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3708                 if (ap->rxconfig & ANEG_CFG_RF2)
3709                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3710                 if (ap->rxconfig & ANEG_CFG_NP)
3711                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3712
3713                 ap->link_time = ap->cur_time;
3714
3715                 ap->flags ^= (MR_TOGGLE_TX);
3716                 if (ap->rxconfig & 0x0008)
3717                         ap->flags |= MR_TOGGLE_RX;
3718                 if (ap->rxconfig & ANEG_CFG_NP)
3719                         ap->flags |= MR_NP_RX;
3720                 ap->flags |= MR_PAGE_RX;
3721
3722                 ap->state = ANEG_STATE_COMPLETE_ACK;
3723                 ret = ANEG_TIMER_ENAB;
3724                 break;
3725
3726         case ANEG_STATE_COMPLETE_ACK:
3727                 if (ap->ability_match != 0 &&
3728                     ap->rxconfig == 0) {
3729                         ap->state = ANEG_STATE_AN_ENABLE;
3730                         break;
3731                 }
3732                 delta = ap->cur_time - ap->link_time;
3733                 if (delta > ANEG_STATE_SETTLE_TIME) {
3734                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3735                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3736                         } else {
3737                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3738                                     !(ap->flags & MR_NP_RX)) {
3739                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3740                                 } else {
3741                                         ret = ANEG_FAILED;
3742                                 }
3743                         }
3744                 }
3745                 break;
3746
3747         case ANEG_STATE_IDLE_DETECT_INIT:
3748                 ap->link_time = ap->cur_time;
3749                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3750                 tw32_f(MAC_MODE, tp->mac_mode);
3751                 udelay(40);
3752
3753                 ap->state = ANEG_STATE_IDLE_DETECT;
3754                 ret = ANEG_TIMER_ENAB;
3755                 break;
3756
3757         case ANEG_STATE_IDLE_DETECT:
3758                 if (ap->ability_match != 0 &&
3759                     ap->rxconfig == 0) {
3760                         ap->state = ANEG_STATE_AN_ENABLE;
3761                         break;
3762                 }
3763                 delta = ap->cur_time - ap->link_time;
3764                 if (delta > ANEG_STATE_SETTLE_TIME) {
3765                         /* XXX another gem from the Broadcom driver :( */
3766                         ap->state = ANEG_STATE_LINK_OK;
3767                 }
3768                 break;
3769
3770         case ANEG_STATE_LINK_OK:
3771                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3772                 ret = ANEG_DONE;
3773                 break;
3774
3775         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3776                 /* ??? unimplemented */
3777                 break;
3778
3779         case ANEG_STATE_NEXT_PAGE_WAIT:
3780                 /* ??? unimplemented */
3781                 break;
3782
3783         default:
3784                 ret = ANEG_FAILED;
3785                 break;
3786         }
3787
3788         return ret;
3789 }
3790
3791 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3792 {
3793         int res = 0;
3794         struct tg3_fiber_aneginfo aninfo;
3795         int status = ANEG_FAILED;
3796         unsigned int tick;
3797         u32 tmp;
3798
3799         tw32_f(MAC_TX_AUTO_NEG, 0);
3800
3801         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3802         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3803         udelay(40);
3804
3805         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3806         udelay(40);
3807
3808         memset(&aninfo, 0, sizeof(aninfo));
3809         aninfo.flags |= MR_AN_ENABLE;
3810         aninfo.state = ANEG_STATE_UNKNOWN;
3811         aninfo.cur_time = 0;
3812         tick = 0;
3813         while (++tick < 195000) {
3814                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3815                 if (status == ANEG_DONE || status == ANEG_FAILED)
3816                         break;
3817
3818                 udelay(1);
3819         }
3820
3821         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3822         tw32_f(MAC_MODE, tp->mac_mode);
3823         udelay(40);
3824
3825         *txflags = aninfo.txconfig;
3826         *rxflags = aninfo.flags;
3827
3828         if (status == ANEG_DONE &&
3829             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3830                              MR_LP_ADV_FULL_DUPLEX)))
3831                 res = 1;
3832
3833         return res;
3834 }
3835
3836 static void tg3_init_bcm8002(struct tg3 *tp)
3837 {
3838         u32 mac_status = tr32(MAC_STATUS);
3839         int i;
3840
3841         /* Reset when initting first time or we have a link. */
3842         if (tg3_flag(tp, INIT_COMPLETE) &&
3843             !(mac_status & MAC_STATUS_PCS_SYNCED))
3844                 return;
3845
3846         /* Set PLL lock range. */
3847         tg3_writephy(tp, 0x16, 0x8007);
3848
3849         /* SW reset */
3850         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3851
3852         /* Wait for reset to complete. */
3853         /* XXX schedule_timeout() ... */
3854         for (i = 0; i < 500; i++)
3855                 udelay(10);
3856
3857         /* Config mode; select PMA/Ch 1 regs. */
3858         tg3_writephy(tp, 0x10, 0x8411);
3859
3860         /* Enable auto-lock and comdet, select txclk for tx. */
3861         tg3_writephy(tp, 0x11, 0x0a10);
3862
3863         tg3_writephy(tp, 0x18, 0x00a0);
3864         tg3_writephy(tp, 0x16, 0x41ff);
3865
3866         /* Assert and deassert POR. */
3867         tg3_writephy(tp, 0x13, 0x0400);
3868         udelay(40);
3869         tg3_writephy(tp, 0x13, 0x0000);
3870
3871         tg3_writephy(tp, 0x11, 0x0a50);
3872         udelay(40);
3873         tg3_writephy(tp, 0x11, 0x0a10);
3874
3875         /* Wait for signal to stabilize */
3876         /* XXX schedule_timeout() ... */
3877         for (i = 0; i < 15000; i++)
3878                 udelay(10);
3879
3880         /* Deselect the channel register so we can read the PHYID
3881          * later.
3882          */
3883         tg3_writephy(tp, 0x10, 0x8011);
3884 }
3885
3886 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3887 {
3888         u16 flowctrl;
3889         u32 sg_dig_ctrl, sg_dig_status;
3890         u32 serdes_cfg, expected_sg_dig_ctrl;
3891         int workaround, port_a;
3892         int current_link_up;
3893
3894         serdes_cfg = 0;
3895         expected_sg_dig_ctrl = 0;
3896         workaround = 0;
3897         port_a = 1;
3898         current_link_up = 0;
3899
3900         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3901             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3902                 workaround = 1;
3903                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3904                         port_a = 0;
3905
3906                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3907                 /* preserve bits 20-23 for voltage regulator */
3908                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3909         }
3910
3911         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3912
3913         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3914                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3915                         if (workaround) {
3916                                 u32 val = serdes_cfg;
3917
3918                                 if (port_a)
3919                                         val |= 0xc010000;
3920                                 else
3921                                         val |= 0x4010000;
3922                                 tw32_f(MAC_SERDES_CFG, val);
3923                         }
3924
3925                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3926                 }
3927                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3928                         tg3_setup_flow_control(tp, 0, 0);
3929                         current_link_up = 1;
3930                 }
3931                 goto out;
3932         }
3933
3934         /* Want auto-negotiation.  */
3935         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3936
3937         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3938         if (flowctrl & ADVERTISE_1000XPAUSE)
3939                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3940         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3941                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3942
3943         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3944                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3945                     tp->serdes_counter &&
3946                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3947                                     MAC_STATUS_RCVD_CFG)) ==
3948                      MAC_STATUS_PCS_SYNCED)) {
3949                         tp->serdes_counter--;
3950                         current_link_up = 1;
3951                         goto out;
3952                 }
3953 restart_autoneg:
3954                 if (workaround)
3955                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3956                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3957                 udelay(5);
3958                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3959
3960                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3961                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3962         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3963                                  MAC_STATUS_SIGNAL_DET)) {
3964                 sg_dig_status = tr32(SG_DIG_STATUS);
3965                 mac_status = tr32(MAC_STATUS);
3966
3967                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3968                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3969                         u32 local_adv = 0, remote_adv = 0;
3970
3971                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3972                                 local_adv |= ADVERTISE_1000XPAUSE;
3973                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3974                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3975
3976                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3977                                 remote_adv |= LPA_1000XPAUSE;
3978                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3979                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3980
3981                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3982                         current_link_up = 1;
3983                         tp->serdes_counter = 0;
3984                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3985                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3986                         if (tp->serdes_counter)
3987                                 tp->serdes_counter--;
3988                         else {
3989                                 if (workaround) {
3990                                         u32 val = serdes_cfg;
3991
3992                                         if (port_a)
3993                                                 val |= 0xc010000;
3994                                         else
3995                                                 val |= 0x4010000;
3996
3997                                         tw32_f(MAC_SERDES_CFG, val);
3998                                 }
3999
4000                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4001                                 udelay(40);
4002
4003                                 /* Link parallel detection - link is up */
4004                                 /* only if we have PCS_SYNC and not */
4005                                 /* receiving config code words */
4006                                 mac_status = tr32(MAC_STATUS);
4007                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4008                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
4009                                         tg3_setup_flow_control(tp, 0, 0);
4010                                         current_link_up = 1;
4011                                         tp->phy_flags |=
4012                                                 TG3_PHYFLG_PARALLEL_DETECT;
4013                                         tp->serdes_counter =
4014                                                 SERDES_PARALLEL_DET_TIMEOUT;
4015                                 } else
4016                                         goto restart_autoneg;
4017                         }
4018                 }
4019         } else {
4020                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4021                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4022         }
4023
4024 out:
4025         return current_link_up;
4026 }
4027
4028 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4029 {
4030         int current_link_up = 0;
4031
4032         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
4033                 goto out;
4034
4035         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4036                 u32 txflags, rxflags;
4037                 int i;
4038
4039                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4040                         u32 local_adv = 0, remote_adv = 0;
4041
4042                         if (txflags & ANEG_CFG_PS1)
4043                                 local_adv |= ADVERTISE_1000XPAUSE;
4044                         if (txflags & ANEG_CFG_PS2)
4045                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
4046
4047                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
4048                                 remote_adv |= LPA_1000XPAUSE;
4049                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4050                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4051
4052                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4053
4054                         current_link_up = 1;
4055                 }
4056                 for (i = 0; i < 30; i++) {
4057                         udelay(20);
4058                         tw32_f(MAC_STATUS,
4059                                (MAC_STATUS_SYNC_CHANGED |
4060                                 MAC_STATUS_CFG_CHANGED));
4061                         udelay(40);
4062                         if ((tr32(MAC_STATUS) &
4063                              (MAC_STATUS_SYNC_CHANGED |
4064                               MAC_STATUS_CFG_CHANGED)) == 0)
4065                                 break;
4066                 }
4067
4068                 mac_status = tr32(MAC_STATUS);
4069                 if (current_link_up == 0 &&
4070                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4071                     !(mac_status & MAC_STATUS_RCVD_CFG))
4072                         current_link_up = 1;
4073         } else {
4074                 tg3_setup_flow_control(tp, 0, 0);
4075
4076                 /* Forcing 1000FD link up. */
4077                 current_link_up = 1;
4078
4079                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4080                 udelay(40);
4081
4082                 tw32_f(MAC_MODE, tp->mac_mode);
4083                 udelay(40);
4084         }
4085
4086 out:
4087         return current_link_up;
4088 }
4089
4090 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4091 {
4092         u32 orig_pause_cfg;
4093         u16 orig_active_speed;
4094         u8 orig_active_duplex;
4095         u32 mac_status;
4096         int current_link_up;
4097         int i;
4098
4099         orig_pause_cfg = tp->link_config.active_flowctrl;
4100         orig_active_speed = tp->link_config.active_speed;
4101         orig_active_duplex = tp->link_config.active_duplex;
4102
4103         if (!tg3_flag(tp, HW_AUTONEG) &&
4104             netif_carrier_ok(tp->dev) &&
4105             tg3_flag(tp, INIT_COMPLETE)) {
4106                 mac_status = tr32(MAC_STATUS);
4107                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4108                                MAC_STATUS_SIGNAL_DET |
4109                                MAC_STATUS_CFG_CHANGED |
4110                                MAC_STATUS_RCVD_CFG);
4111                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4112                                    MAC_STATUS_SIGNAL_DET)) {
4113                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4114                                             MAC_STATUS_CFG_CHANGED));
4115                         return 0;
4116                 }
4117         }
4118
4119         tw32_f(MAC_TX_AUTO_NEG, 0);
4120
4121         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4122         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4123         tw32_f(MAC_MODE, tp->mac_mode);
4124         udelay(40);
4125
4126         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4127                 tg3_init_bcm8002(tp);
4128
4129         /* Enable link change event even when serdes polling.  */
4130         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4131         udelay(40);
4132
4133         current_link_up = 0;
4134         mac_status = tr32(MAC_STATUS);
4135
4136         if (tg3_flag(tp, HW_AUTONEG))
4137                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4138         else
4139                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4140
4141         tp->napi[0].hw_status->status =
4142                 (SD_STATUS_UPDATED |
4143                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4144
4145         for (i = 0; i < 100; i++) {
4146                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4147                                     MAC_STATUS_CFG_CHANGED));
4148                 udelay(5);
4149                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4150                                          MAC_STATUS_CFG_CHANGED |
4151                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4152                         break;
4153         }
4154
4155         mac_status = tr32(MAC_STATUS);
4156         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4157                 current_link_up = 0;
4158                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4159                     tp->serdes_counter == 0) {
4160                         tw32_f(MAC_MODE, (tp->mac_mode |
4161                                           MAC_MODE_SEND_CONFIGS));
4162                         udelay(1);
4163                         tw32_f(MAC_MODE, tp->mac_mode);
4164                 }
4165         }
4166
4167         if (current_link_up == 1) {
4168                 tp->link_config.active_speed = SPEED_1000;
4169                 tp->link_config.active_duplex = DUPLEX_FULL;
4170                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4171                                     LED_CTRL_LNKLED_OVERRIDE |
4172                                     LED_CTRL_1000MBPS_ON));
4173         } else {
4174                 tp->link_config.active_speed = SPEED_INVALID;
4175                 tp->link_config.active_duplex = DUPLEX_INVALID;
4176                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4177                                     LED_CTRL_LNKLED_OVERRIDE |
4178                                     LED_CTRL_TRAFFIC_OVERRIDE));
4179         }
4180
4181         if (current_link_up != netif_carrier_ok(tp->dev)) {
4182                 if (current_link_up)
4183                         netif_carrier_on(tp->dev);
4184                 else
4185                         netif_carrier_off(tp->dev);
4186                 tg3_link_report(tp);
4187         } else {
4188                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4189                 if (orig_pause_cfg != now_pause_cfg ||
4190                     orig_active_speed != tp->link_config.active_speed ||
4191                     orig_active_duplex != tp->link_config.active_duplex)
4192                         tg3_link_report(tp);
4193         }
4194
4195         return 0;
4196 }
4197
4198 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4199 {
4200         int current_link_up, err = 0;
4201         u32 bmsr, bmcr;
4202         u16 current_speed;
4203         u8 current_duplex;
4204         u32 local_adv, remote_adv;
4205
4206         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4207         tw32_f(MAC_MODE, tp->mac_mode);
4208         udelay(40);
4209
4210         tw32(MAC_EVENT, 0);
4211
4212         tw32_f(MAC_STATUS,
4213              (MAC_STATUS_SYNC_CHANGED |
4214               MAC_STATUS_CFG_CHANGED |
4215               MAC_STATUS_MI_COMPLETION |
4216               MAC_STATUS_LNKSTATE_CHANGED));
4217         udelay(40);
4218
4219         if (force_reset)
4220                 tg3_phy_reset(tp);
4221
4222         current_link_up = 0;
4223         current_speed = SPEED_INVALID;
4224         current_duplex = DUPLEX_INVALID;
4225
4226         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4227         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4228         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4229                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4230                         bmsr |= BMSR_LSTATUS;
4231                 else
4232                         bmsr &= ~BMSR_LSTATUS;
4233         }
4234
4235         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4236
4237         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4238             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4239                 /* do nothing, just check for link up at the end */
4240         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4241                 u32 adv, new_adv;
4242
4243                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4244                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4245                                   ADVERTISE_1000XPAUSE |
4246                                   ADVERTISE_1000XPSE_ASYM |
4247                                   ADVERTISE_SLCT);
4248
4249                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4250
4251                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4252                         new_adv |= ADVERTISE_1000XHALF;
4253                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4254                         new_adv |= ADVERTISE_1000XFULL;
4255
4256                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4257                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4258                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4259                         tg3_writephy(tp, MII_BMCR, bmcr);
4260
4261                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4262                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4263                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4264
4265                         return err;
4266                 }
4267         } else {
4268                 u32 new_bmcr;
4269
4270                 bmcr &= ~BMCR_SPEED1000;
4271                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4272
4273                 if (tp->link_config.duplex == DUPLEX_FULL)
4274                         new_bmcr |= BMCR_FULLDPLX;
4275
4276                 if (new_bmcr != bmcr) {
4277                         /* BMCR_SPEED1000 is a reserved bit that needs
4278                          * to be set on write.
4279                          */
4280                         new_bmcr |= BMCR_SPEED1000;
4281
4282                         /* Force a linkdown */
4283                         if (netif_carrier_ok(tp->dev)) {
4284                                 u32 adv;
4285
4286                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4287                                 adv &= ~(ADVERTISE_1000XFULL |
4288                                          ADVERTISE_1000XHALF |
4289                                          ADVERTISE_SLCT);
4290                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4291                                 tg3_writephy(tp, MII_BMCR, bmcr |
4292                                                            BMCR_ANRESTART |
4293                                                            BMCR_ANENABLE);
4294                                 udelay(10);
4295                                 netif_carrier_off(tp->dev);
4296                         }
4297                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4298                         bmcr = new_bmcr;
4299                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4300                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4301                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4302                             ASIC_REV_5714) {
4303                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4304                                         bmsr |= BMSR_LSTATUS;
4305                                 else
4306                                         bmsr &= ~BMSR_LSTATUS;
4307                         }
4308                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4309                 }
4310         }
4311
4312         if (bmsr & BMSR_LSTATUS) {
4313                 current_speed = SPEED_1000;
4314                 current_link_up = 1;
4315                 if (bmcr & BMCR_FULLDPLX)
4316                         current_duplex = DUPLEX_FULL;
4317                 else
4318                         current_duplex = DUPLEX_HALF;
4319
4320                 local_adv = 0;
4321                 remote_adv = 0;
4322
4323                 if (bmcr & BMCR_ANENABLE) {
4324                         u32 common;
4325
4326                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4327                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4328                         common = local_adv & remote_adv;
4329                         if (common & (ADVERTISE_1000XHALF |
4330                                       ADVERTISE_1000XFULL)) {
4331                                 if (common & ADVERTISE_1000XFULL)
4332                                         current_duplex = DUPLEX_FULL;
4333                                 else
4334                                         current_duplex = DUPLEX_HALF;
4335                         } else if (!tg3_flag(tp, 5780_CLASS)) {
4336                                 /* Link is up via parallel detect */
4337                         } else {
4338                                 current_link_up = 0;
4339                         }
4340                 }
4341         }
4342
4343         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4344                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4345
4346         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4347         if (tp->link_config.active_duplex == DUPLEX_HALF)
4348                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4349
4350         tw32_f(MAC_MODE, tp->mac_mode);
4351         udelay(40);
4352
4353         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4354
4355         tp->link_config.active_speed = current_speed;
4356         tp->link_config.active_duplex = current_duplex;
4357
4358         if (current_link_up != netif_carrier_ok(tp->dev)) {
4359                 if (current_link_up)
4360                         netif_carrier_on(tp->dev);
4361                 else {
4362                         netif_carrier_off(tp->dev);
4363                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4364                 }
4365                 tg3_link_report(tp);
4366         }
4367         return err;
4368 }
4369
4370 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4371 {
4372         if (tp->serdes_counter) {
4373                 /* Give autoneg time to complete. */
4374                 tp->serdes_counter--;
4375                 return;
4376         }
4377
4378         if (!netif_carrier_ok(tp->dev) &&
4379             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4380                 u32 bmcr;
4381
4382                 tg3_readphy(tp, MII_BMCR, &bmcr);
4383                 if (bmcr & BMCR_ANENABLE) {
4384                         u32 phy1, phy2;
4385
4386                         /* Select shadow register 0x1f */
4387                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4388                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4389
4390                         /* Select expansion interrupt status register */
4391                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4392                                          MII_TG3_DSP_EXP1_INT_STAT);
4393                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4394                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4395
4396                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4397                                 /* We have signal detect and not receiving
4398                                  * config code words, link is up by parallel
4399                                  * detection.
4400                                  */
4401
4402                                 bmcr &= ~BMCR_ANENABLE;
4403                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4404                                 tg3_writephy(tp, MII_BMCR, bmcr);
4405                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4406                         }
4407                 }
4408         } else if (netif_carrier_ok(tp->dev) &&
4409                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4410                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4411                 u32 phy2;
4412
4413                 /* Select expansion interrupt status register */
4414                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4415                                  MII_TG3_DSP_EXP1_INT_STAT);
4416                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4417                 if (phy2 & 0x20) {
4418                         u32 bmcr;
4419
4420                         /* Config code words received, turn on autoneg. */
4421                         tg3_readphy(tp, MII_BMCR, &bmcr);
4422                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4423
4424                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4425
4426                 }
4427         }
4428 }
4429
4430 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4431 {
4432         u32 val;
4433         int err;
4434
4435         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4436                 err = tg3_setup_fiber_phy(tp, force_reset);
4437         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4438                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4439         else
4440                 err = tg3_setup_copper_phy(tp, force_reset);
4441
4442         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4443                 u32 scale;
4444
4445                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4446                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4447                         scale = 65;
4448                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4449                         scale = 6;
4450                 else
4451                         scale = 12;
4452
4453                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4454                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4455                 tw32(GRC_MISC_CFG, val);
4456         }
4457
4458         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4459               (6 << TX_LENGTHS_IPG_SHIFT);
4460         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
4461                 val |= tr32(MAC_TX_LENGTHS) &
4462                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
4463                         TX_LENGTHS_CNT_DWN_VAL_MSK);
4464
4465         if (tp->link_config.active_speed == SPEED_1000 &&
4466             tp->link_config.active_duplex == DUPLEX_HALF)
4467                 tw32(MAC_TX_LENGTHS, val |
4468                      (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
4469         else
4470                 tw32(MAC_TX_LENGTHS, val |
4471                      (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
4472
4473         if (!tg3_flag(tp, 5705_PLUS)) {
4474                 if (netif_carrier_ok(tp->dev)) {
4475                         tw32(HOSTCC_STAT_COAL_TICKS,
4476                              tp->coal.stats_block_coalesce_usecs);
4477                 } else {
4478                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4479                 }
4480         }
4481
4482         if (tg3_flag(tp, ASPM_WORKAROUND)) {
4483                 val = tr32(PCIE_PWR_MGMT_THRESH);
4484                 if (!netif_carrier_ok(tp->dev))
4485                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4486                               tp->pwrmgmt_thresh;
4487                 else
4488                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4489                 tw32(PCIE_PWR_MGMT_THRESH, val);
4490         }
4491
4492         return err;
4493 }
4494
4495 static inline int tg3_irq_sync(struct tg3 *tp)
4496 {
4497         return tp->irq_sync;
4498 }
4499
4500 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
4501 {
4502         int i;
4503
4504         dst = (u32 *)((u8 *)dst + off);
4505         for (i = 0; i < len; i += sizeof(u32))
4506                 *dst++ = tr32(off + i);
4507 }
4508
4509 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
4510 {
4511         tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
4512         tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
4513         tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
4514         tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
4515         tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
4516         tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
4517         tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
4518         tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
4519         tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
4520         tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
4521         tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
4522         tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
4523         tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
4524         tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
4525         tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
4526         tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
4527         tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
4528         tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
4529         tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
4530
4531         if (tg3_flag(tp, SUPPORT_MSIX))
4532                 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
4533
4534         tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
4535         tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
4536         tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
4537         tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
4538         tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
4539         tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
4540         tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
4541         tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
4542
4543         if (!tg3_flag(tp, 5705_PLUS)) {
4544                 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
4545                 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
4546                 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
4547         }
4548
4549         tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
4550         tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
4551         tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
4552         tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
4553         tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
4554
4555         if (tg3_flag(tp, NVRAM))
4556                 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
4557 }
4558
4559 static void tg3_dump_state(struct tg3 *tp)
4560 {
4561         int i;
4562         u32 *regs;
4563
4564         regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
4565         if (!regs) {
4566                 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
4567                 return;
4568         }
4569
4570         if (tg3_flag(tp, PCI_EXPRESS)) {
4571                 /* Read up to but not including private PCI registers */
4572                 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
4573                         regs[i / sizeof(u32)] = tr32(i);
4574         } else
4575                 tg3_dump_legacy_regs(tp, regs);
4576
4577         for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
4578                 if (!regs[i + 0] && !regs[i + 1] &&
4579                     !regs[i + 2] && !regs[i + 3])
4580                         continue;
4581
4582                 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
4583                            i * 4,
4584                            regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
4585         }
4586
4587         kfree(regs);
4588
4589         for (i = 0; i < tp->irq_cnt; i++) {
4590                 struct tg3_napi *tnapi = &tp->napi[i];
4591
4592                 /* SW status block */
4593                 netdev_err(tp->dev,
4594                          "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
4595                            i,
4596                            tnapi->hw_status->status,
4597                            tnapi->hw_status->status_tag,
4598                            tnapi->hw_status->rx_jumbo_consumer,
4599                            tnapi->hw_status->rx_consumer,
4600                            tnapi->hw_status->rx_mini_consumer,
4601                            tnapi->hw_status->idx[0].rx_producer,
4602                            tnapi->hw_status->idx[0].tx_consumer);
4603
4604                 netdev_err(tp->dev,
4605                 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
4606                            i,
4607                            tnapi->last_tag, tnapi->last_irq_tag,
4608                            tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
4609                            tnapi->rx_rcb_ptr,
4610                            tnapi->prodring.rx_std_prod_idx,
4611                            tnapi->prodring.rx_std_cons_idx,
4612                            tnapi->prodring.rx_jmb_prod_idx,
4613                            tnapi->prodring.rx_jmb_cons_idx);
4614         }
4615 }
4616
4617 /* This is called whenever we suspect that the system chipset is re-
4618  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4619  * is bogus tx completions. We try to recover by setting the
4620  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4621  * in the workqueue.
4622  */
4623 static void tg3_tx_recover(struct tg3 *tp)
4624 {
4625         BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
4626                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4627
4628         netdev_warn(tp->dev,
4629                     "The system may be re-ordering memory-mapped I/O "
4630                     "cycles to the network device, attempting to recover. "
4631                     "Please report the problem to the driver maintainer "
4632                     "and include system chipset information.\n");
4633
4634         spin_lock(&tp->lock);
4635         tg3_flag_set(tp, TX_RECOVERY_PENDING);
4636         spin_unlock(&tp->lock);
4637 }
4638
4639 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4640 {
4641         /* Tell compiler to fetch tx indices from memory. */
4642         barrier();
4643         return tnapi->tx_pending -
4644                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4645 }
4646
4647 /* Tigon3 never reports partial packet sends.  So we do not
4648  * need special logic to handle SKBs that have not had all
4649  * of their frags sent yet, like SunGEM does.
4650  */
4651 static void tg3_tx(struct tg3_napi *tnapi)
4652 {
4653         struct tg3 *tp = tnapi->tp;
4654         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4655         u32 sw_idx = tnapi->tx_cons;
4656         struct netdev_queue *txq;
4657         int index = tnapi - tp->napi;
4658
4659         if (tg3_flag(tp, ENABLE_TSS))
4660                 index--;
4661
4662         txq = netdev_get_tx_queue(tp->dev, index);
4663
4664         while (sw_idx != hw_idx) {
4665                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4666                 struct sk_buff *skb = ri->skb;
4667                 int i, tx_bug = 0;
4668
4669                 if (unlikely(skb == NULL)) {
4670                         tg3_tx_recover(tp);
4671                         return;
4672                 }
4673
4674                 pci_unmap_single(tp->pdev,
4675                                  dma_unmap_addr(ri, mapping),
4676                                  skb_headlen(skb),
4677                                  PCI_DMA_TODEVICE);
4678
4679                 ri->skb = NULL;
4680
4681                 sw_idx = NEXT_TX(sw_idx);
4682
4683                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4684                         ri = &tnapi->tx_buffers[sw_idx];
4685                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4686                                 tx_bug = 1;
4687
4688                         pci_unmap_page(tp->pdev,
4689                                        dma_unmap_addr(ri, mapping),
4690                                        skb_shinfo(skb)->frags[i].size,
4691                                        PCI_DMA_TODEVICE);
4692                         sw_idx = NEXT_TX(sw_idx);
4693                 }
4694
4695                 dev_kfree_skb(skb);
4696
4697                 if (unlikely(tx_bug)) {
4698                         tg3_tx_recover(tp);
4699                         return;
4700                 }
4701         }
4702
4703         tnapi->tx_cons = sw_idx;
4704
4705         /* Need to make the tx_cons update visible to tg3_start_xmit()
4706          * before checking for netif_queue_stopped().  Without the
4707          * memory barrier, there is a small possibility that tg3_start_xmit()
4708          * will miss it and cause the queue to be stopped forever.
4709          */
4710         smp_mb();
4711
4712         if (unlikely(netif_tx_queue_stopped(txq) &&
4713                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4714                 __netif_tx_lock(txq, smp_processor_id());
4715                 if (netif_tx_queue_stopped(txq) &&
4716                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4717                         netif_tx_wake_queue(txq);
4718                 __netif_tx_unlock(txq);
4719         }
4720 }
4721
4722 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4723 {
4724         if (!ri->skb)
4725                 return;
4726
4727         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4728                          map_sz, PCI_DMA_FROMDEVICE);
4729         dev_kfree_skb_any(ri->skb);
4730         ri->skb = NULL;
4731 }
4732
4733 /* Returns size of skb allocated or < 0 on error.
4734  *
4735  * We only need to fill in the address because the other members
4736  * of the RX descriptor are invariant, see tg3_init_rings.
4737  *
4738  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4739  * posting buffers we only dirty the first cache line of the RX
4740  * descriptor (containing the address).  Whereas for the RX status
4741  * buffers the cpu only reads the last cacheline of the RX descriptor
4742  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4743  */
4744 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4745                             u32 opaque_key, u32 dest_idx_unmasked)
4746 {
4747         struct tg3_rx_buffer_desc *desc;
4748         struct ring_info *map;
4749         struct sk_buff *skb;
4750         dma_addr_t mapping;
4751         int skb_size, dest_idx;
4752
4753         switch (opaque_key) {
4754         case RXD_OPAQUE_RING_STD:
4755                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4756                 desc = &tpr->rx_std[dest_idx];
4757                 map = &tpr->rx_std_buffers[dest_idx];
4758                 skb_size = tp->rx_pkt_map_sz;
4759                 break;
4760
4761         case RXD_OPAQUE_RING_JUMBO:
4762                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4763                 desc = &tpr->rx_jmb[dest_idx].std;
4764                 map = &tpr->rx_jmb_buffers[dest_idx];
4765                 skb_size = TG3_RX_JMB_MAP_SZ;
4766                 break;
4767
4768         default:
4769                 return -EINVAL;
4770         }
4771
4772         /* Do not overwrite any of the map or rp information
4773          * until we are sure we can commit to a new buffer.
4774          *
4775          * Callers depend upon this behavior and assume that
4776          * we leave everything unchanged if we fail.
4777          */
4778         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4779         if (skb == NULL)
4780                 return -ENOMEM;
4781
4782         skb_reserve(skb, tp->rx_offset);
4783
4784         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4785                                  PCI_DMA_FROMDEVICE);
4786         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4787                 dev_kfree_skb(skb);
4788                 return -EIO;
4789         }
4790
4791         map->skb = skb;
4792         dma_unmap_addr_set(map, mapping, mapping);
4793
4794         desc->addr_hi = ((u64)mapping >> 32);
4795         desc->addr_lo = ((u64)mapping & 0xffffffff);
4796
4797         return skb_size;
4798 }
4799
4800 /* We only need to move over in the address because the other
4801  * members of the RX descriptor are invariant.  See notes above
4802  * tg3_alloc_rx_skb for full details.
4803  */
4804 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4805                            struct tg3_rx_prodring_set *dpr,
4806                            u32 opaque_key, int src_idx,
4807                            u32 dest_idx_unmasked)
4808 {
4809         struct tg3 *tp = tnapi->tp;
4810         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4811         struct ring_info *src_map, *dest_map;
4812         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4813         int dest_idx;
4814
4815         switch (opaque_key) {
4816         case RXD_OPAQUE_RING_STD:
4817                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4818                 dest_desc = &dpr->rx_std[dest_idx];
4819                 dest_map = &dpr->rx_std_buffers[dest_idx];
4820                 src_desc = &spr->rx_std[src_idx];
4821                 src_map = &spr->rx_std_buffers[src_idx];
4822                 break;
4823
4824         case RXD_OPAQUE_RING_JUMBO:
4825                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4826                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4827                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4828                 src_desc = &spr->rx_jmb[src_idx].std;
4829                 src_map = &spr->rx_jmb_buffers[src_idx];
4830                 break;
4831
4832         default:
4833                 return;
4834         }
4835
4836         dest_map->skb = src_map->skb;
4837         dma_unmap_addr_set(dest_map, mapping,
4838                            dma_unmap_addr(src_map, mapping));
4839         dest_desc->addr_hi = src_desc->addr_hi;
4840         dest_desc->addr_lo = src_desc->addr_lo;
4841
4842         /* Ensure that the update to the skb happens after the physical
4843          * addresses have been transferred to the new BD location.
4844          */
4845         smp_wmb();
4846
4847         src_map->skb = NULL;
4848 }
4849
4850 /* The RX ring scheme is composed of multiple rings which post fresh
4851  * buffers to the chip, and one special ring the chip uses to report
4852  * status back to the host.
4853  *
4854  * The special ring reports the status of received packets to the
4855  * host.  The chip does not write into the original descriptor the
4856  * RX buffer was obtained from.  The chip simply takes the original
4857  * descriptor as provided by the host, updates the status and length
4858  * field, then writes this into the next status ring entry.
4859  *
4860  * Each ring the host uses to post buffers to the chip is described
4861  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4862  * it is first placed into the on-chip ram.  When the packet's length
4863  * is known, it walks down the TG3_BDINFO entries to select the ring.
4864  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4865  * which is within the range of the new packet's length is chosen.
4866  *
4867  * The "separate ring for rx status" scheme may sound queer, but it makes
4868  * sense from a cache coherency perspective.  If only the host writes
4869  * to the buffer post rings, and only the chip writes to the rx status
4870  * rings, then cache lines never move beyond shared-modified state.
4871  * If both the host and chip were to write into the same ring, cache line
4872  * eviction could occur since both entities want it in an exclusive state.
4873  */
4874 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4875 {
4876         struct tg3 *tp = tnapi->tp;
4877         u32 work_mask, rx_std_posted = 0;
4878         u32 std_prod_idx, jmb_prod_idx;
4879         u32 sw_idx = tnapi->rx_rcb_ptr;
4880         u16 hw_idx;
4881         int received;
4882         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4883
4884         hw_idx = *(tnapi->rx_rcb_prod_idx);
4885         /*
4886          * We need to order the read of hw_idx and the read of
4887          * the opaque cookie.
4888          */
4889         rmb();
4890         work_mask = 0;
4891         received = 0;
4892         std_prod_idx = tpr->rx_std_prod_idx;
4893         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4894         while (sw_idx != hw_idx && budget > 0) {
4895                 struct ring_info *ri;
4896                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4897                 unsigned int len;
4898                 struct sk_buff *skb;
4899                 dma_addr_t dma_addr;
4900                 u32 opaque_key, desc_idx, *post_ptr;
4901
4902                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4903                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4904                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4905                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4906                         dma_addr = dma_unmap_addr(ri, mapping);
4907                         skb = ri->skb;
4908                         post_ptr = &std_prod_idx;
4909                         rx_std_posted++;
4910                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4911                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4912                         dma_addr = dma_unmap_addr(ri, mapping);
4913                         skb = ri->skb;
4914                         post_ptr = &jmb_prod_idx;
4915                 } else
4916                         goto next_pkt_nopost;
4917
4918                 work_mask |= opaque_key;
4919
4920                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4921                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4922                 drop_it:
4923                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4924                                        desc_idx, *post_ptr);
4925                 drop_it_no_recycle:
4926                         /* Other statistics kept track of by card. */
4927                         tp->rx_dropped++;
4928                         goto next_pkt;
4929                 }
4930
4931                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4932                       ETH_FCS_LEN;
4933
4934                 if (len > TG3_RX_COPY_THRESH(tp)) {
4935                         int skb_size;
4936
4937                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4938                                                     *post_ptr);
4939                         if (skb_size < 0)
4940                                 goto drop_it;
4941
4942                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4943                                          PCI_DMA_FROMDEVICE);
4944
4945                         /* Ensure that the update to the skb happens
4946                          * after the usage of the old DMA mapping.
4947                          */
4948                         smp_wmb();
4949
4950                         ri->skb = NULL;
4951
4952                         skb_put(skb, len);
4953                 } else {
4954                         struct sk_buff *copy_skb;
4955
4956                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4957                                        desc_idx, *post_ptr);
4958
4959                         copy_skb = netdev_alloc_skb(tp->dev, len +
4960                                                     TG3_RAW_IP_ALIGN);
4961                         if (copy_skb == NULL)
4962                                 goto drop_it_no_recycle;
4963
4964                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4965                         skb_put(copy_skb, len);
4966                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4967                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4968                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4969
4970                         /* We'll reuse the original ring buffer. */
4971                         skb = copy_skb;
4972                 }
4973
4974                 if ((tp->dev->features & NETIF_F_RXCSUM) &&
4975                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4976                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4977                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4978                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4979                 else
4980                         skb_checksum_none_assert(skb);
4981
4982                 skb->protocol = eth_type_trans(skb, tp->dev);
4983
4984                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4985                     skb->protocol != htons(ETH_P_8021Q)) {
4986                         dev_kfree_skb(skb);
4987                         goto drop_it_no_recycle;
4988                 }
4989
4990                 if (desc->type_flags & RXD_FLAG_VLAN &&
4991                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4992                         __vlan_hwaccel_put_tag(skb,
4993                                                desc->err_vlan & RXD_VLAN_MASK);
4994
4995                 napi_gro_receive(&tnapi->napi, skb);
4996
4997                 received++;
4998                 budget--;
4999
5000 next_pkt:
5001                 (*post_ptr)++;
5002
5003                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
5004                         tpr->rx_std_prod_idx = std_prod_idx &
5005                                                tp->rx_std_ring_mask;
5006                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5007                                      tpr->rx_std_prod_idx);
5008                         work_mask &= ~RXD_OPAQUE_RING_STD;
5009                         rx_std_posted = 0;
5010                 }
5011 next_pkt_nopost:
5012                 sw_idx++;
5013                 sw_idx &= tp->rx_ret_ring_mask;
5014
5015                 /* Refresh hw_idx to see if there is new work */
5016                 if (sw_idx == hw_idx) {
5017                         hw_idx = *(tnapi->rx_rcb_prod_idx);
5018                         rmb();
5019                 }
5020         }
5021
5022         /* ACK the status ring. */
5023         tnapi->rx_rcb_ptr = sw_idx;
5024         tw32_rx_mbox(tnapi->consmbox, sw_idx);
5025
5026         /* Refill RX ring(s). */
5027         if (!tg3_flag(tp, ENABLE_RSS)) {
5028                 if (work_mask & RXD_OPAQUE_RING_STD) {
5029                         tpr->rx_std_prod_idx = std_prod_idx &
5030                                                tp->rx_std_ring_mask;
5031                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5032                                      tpr->rx_std_prod_idx);
5033                 }
5034                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
5035                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
5036                                                tp->rx_jmb_ring_mask;
5037                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5038                                      tpr->rx_jmb_prod_idx);
5039                 }
5040                 mmiowb();
5041         } else if (work_mask) {
5042                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5043                  * updated before the producer indices can be updated.
5044                  */
5045                 smp_wmb();
5046
5047                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5048                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5049
5050                 if (tnapi != &tp->napi[1])
5051                         napi_schedule(&tp->napi[1].napi);
5052         }
5053
5054         return received;
5055 }
5056
5057 static void tg3_poll_link(struct tg3 *tp)
5058 {
5059         /* handle link change and other phy events */
5060         if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
5061                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5062
5063                 if (sblk->status & SD_STATUS_LINK_CHG) {
5064                         sblk->status = SD_STATUS_UPDATED |
5065                                        (sblk->status & ~SD_STATUS_LINK_CHG);
5066                         spin_lock(&tp->lock);
5067                         if (tg3_flag(tp, USE_PHYLIB)) {
5068                                 tw32_f(MAC_STATUS,
5069                                      (MAC_STATUS_SYNC_CHANGED |
5070                                       MAC_STATUS_CFG_CHANGED |
5071                                       MAC_STATUS_MI_COMPLETION |
5072                                       MAC_STATUS_LNKSTATE_CHANGED));
5073                                 udelay(40);
5074                         } else
5075                                 tg3_setup_phy(tp, 0);
5076                         spin_unlock(&tp->lock);
5077                 }
5078         }
5079 }
5080
5081 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5082                                 struct tg3_rx_prodring_set *dpr,
5083                                 struct tg3_rx_prodring_set *spr)
5084 {
5085         u32 si, di, cpycnt, src_prod_idx;
5086         int i, err = 0;
5087
5088         while (1) {
5089                 src_prod_idx = spr->rx_std_prod_idx;
5090
5091                 /* Make sure updates to the rx_std_buffers[] entries and the
5092                  * standard producer index are seen in the correct order.
5093                  */
5094                 smp_rmb();
5095
5096                 if (spr->rx_std_cons_idx == src_prod_idx)
5097                         break;
5098
5099                 if (spr->rx_std_cons_idx < src_prod_idx)
5100                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5101                 else
5102                         cpycnt = tp->rx_std_ring_mask + 1 -
5103                                  spr->rx_std_cons_idx;
5104
5105                 cpycnt = min(cpycnt,
5106                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
5107
5108                 si = spr->rx_std_cons_idx;
5109                 di = dpr->rx_std_prod_idx;
5110
5111                 for (i = di; i < di + cpycnt; i++) {
5112                         if (dpr->rx_std_buffers[i].skb) {
5113                                 cpycnt = i - di;
5114                                 err = -ENOSPC;
5115                                 break;
5116                         }
5117                 }
5118
5119                 if (!cpycnt)
5120                         break;
5121
5122                 /* Ensure that updates to the rx_std_buffers ring and the
5123                  * shadowed hardware producer ring from tg3_recycle_skb() are
5124                  * ordered correctly WRT the skb check above.
5125                  */
5126                 smp_rmb();
5127
5128                 memcpy(&dpr->rx_std_buffers[di],
5129                        &spr->rx_std_buffers[si],
5130                        cpycnt * sizeof(struct ring_info));
5131
5132                 for (i = 0; i < cpycnt; i++, di++, si++) {
5133                         struct tg3_rx_buffer_desc *sbd, *dbd;
5134                         sbd = &spr->rx_std[si];
5135                         dbd = &dpr->rx_std[di];
5136                         dbd->addr_hi = sbd->addr_hi;
5137                         dbd->addr_lo = sbd->addr_lo;
5138                 }
5139
5140                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5141                                        tp->rx_std_ring_mask;
5142                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5143                                        tp->rx_std_ring_mask;
5144         }
5145
5146         while (1) {
5147                 src_prod_idx = spr->rx_jmb_prod_idx;
5148
5149                 /* Make sure updates to the rx_jmb_buffers[] entries and
5150                  * the jumbo producer index are seen in the correct order.
5151                  */
5152                 smp_rmb();
5153
5154                 if (spr->rx_jmb_cons_idx == src_prod_idx)
5155                         break;
5156
5157                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5158                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5159                 else
5160                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5161                                  spr->rx_jmb_cons_idx;
5162
5163                 cpycnt = min(cpycnt,
5164                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5165
5166                 si = spr->rx_jmb_cons_idx;
5167                 di = dpr->rx_jmb_prod_idx;
5168
5169                 for (i = di; i < di + cpycnt; i++) {
5170                         if (dpr->rx_jmb_buffers[i].skb) {
5171                                 cpycnt = i - di;
5172                                 err = -ENOSPC;
5173                                 break;
5174                         }
5175                 }
5176
5177                 if (!cpycnt)
5178                         break;
5179
5180                 /* Ensure that updates to the rx_jmb_buffers ring and the
5181                  * shadowed hardware producer ring from tg3_recycle_skb() are
5182                  * ordered correctly WRT the skb check above.
5183                  */
5184                 smp_rmb();
5185
5186                 memcpy(&dpr->rx_jmb_buffers[di],
5187                        &spr->rx_jmb_buffers[si],
5188                        cpycnt * sizeof(struct ring_info));
5189
5190                 for (i = 0; i < cpycnt; i++, di++, si++) {
5191                         struct tg3_rx_buffer_desc *sbd, *dbd;
5192                         sbd = &spr->rx_jmb[si].std;
5193                         dbd = &dpr->rx_jmb[di].std;
5194                         dbd->addr_hi = sbd->addr_hi;
5195                         dbd->addr_lo = sbd->addr_lo;
5196                 }
5197
5198                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5199                                        tp->rx_jmb_ring_mask;
5200                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5201                                        tp->rx_jmb_ring_mask;
5202         }
5203
5204         return err;
5205 }
5206
5207 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5208 {
5209         struct tg3 *tp = tnapi->tp;
5210
5211         /* run TX completion thread */
5212         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5213                 tg3_tx(tnapi);
5214                 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5215                         return work_done;
5216         }
5217
5218         /* run RX thread, within the bounds set by NAPI.
5219          * All RX "locking" is done by ensuring outside
5220          * code synchronizes with tg3->napi.poll()
5221          */
5222         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5223                 work_done += tg3_rx(tnapi, budget - work_done);
5224
5225         if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
5226                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5227                 int i, err = 0;
5228                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5229                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5230
5231                 for (i = 1; i < tp->irq_cnt; i++)
5232                         err |= tg3_rx_prodring_xfer(tp, dpr,
5233                                                     &tp->napi[i].prodring);
5234
5235                 wmb();
5236
5237                 if (std_prod_idx != dpr->rx_std_prod_idx)
5238                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5239                                      dpr->rx_std_prod_idx);
5240
5241                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5242                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5243                                      dpr->rx_jmb_prod_idx);
5244
5245                 mmiowb();
5246
5247                 if (err)
5248                         tw32_f(HOSTCC_MODE, tp->coal_now);
5249         }
5250
5251         return work_done;
5252 }
5253
5254 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5255 {
5256         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5257         struct tg3 *tp = tnapi->tp;
5258         int work_done = 0;
5259         struct tg3_hw_status *sblk = tnapi->hw_status;
5260
5261         while (1) {
5262                 work_done = tg3_poll_work(tnapi, work_done, budget);
5263
5264                 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5265                         goto tx_recovery;
5266
5267                 if (unlikely(work_done >= budget))
5268                         break;
5269
5270                 /* tp->last_tag is used in tg3_int_reenable() below
5271                  * to tell the hw how much work has been processed,
5272                  * so we must read it before checking for more work.
5273                  */
5274                 tnapi->last_tag = sblk->status_tag;
5275                 tnapi->last_irq_tag = tnapi->last_tag;
5276                 rmb();
5277
5278                 /* check for RX/TX work to do */
5279                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5280                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5281                         napi_complete(napi);
5282                         /* Reenable interrupts. */
5283                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5284                         mmiowb();
5285                         break;
5286                 }
5287         }
5288
5289         return work_done;
5290
5291 tx_recovery:
5292         /* work_done is guaranteed to be less than budget. */
5293         napi_complete(napi);
5294         schedule_work(&tp->reset_task);
5295         return work_done;
5296 }
5297
5298 static void tg3_process_error(struct tg3 *tp)
5299 {
5300         u32 val;
5301         bool real_error = false;
5302
5303         if (tg3_flag(tp, ERROR_PROCESSED))
5304                 return;
5305
5306         /* Check Flow Attention register */
5307         val = tr32(HOSTCC_FLOW_ATTN);
5308         if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
5309                 netdev_err(tp->dev, "FLOW Attention error.  Resetting chip.\n");
5310                 real_error = true;
5311         }
5312
5313         if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
5314                 netdev_err(tp->dev, "MSI Status error.  Resetting chip.\n");
5315                 real_error = true;
5316         }
5317
5318         if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
5319                 netdev_err(tp->dev, "DMA Status error.  Resetting chip.\n");
5320                 real_error = true;
5321         }
5322
5323         if (!real_error)
5324                 return;
5325
5326         tg3_dump_state(tp);
5327
5328         tg3_flag_set(tp, ERROR_PROCESSED);
5329         schedule_work(&tp->reset_task);
5330 }
5331
5332 static int tg3_poll(struct napi_struct *napi, int budget)
5333 {
5334         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5335         struct tg3 *tp = tnapi->tp;
5336         int work_done = 0;
5337         struct tg3_hw_status *sblk = tnapi->hw_status;
5338
5339         while (1) {
5340                 if (sblk->status & SD_STATUS_ERROR)
5341                         tg3_process_error(tp);
5342
5343                 tg3_poll_link(tp);
5344
5345                 work_done = tg3_poll_work(tnapi, work_done, budget);
5346
5347                 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5348                         goto tx_recovery;
5349
5350                 if (unlikely(work_done >= budget))
5351                         break;
5352
5353                 if (tg3_flag(tp, TAGGED_STATUS)) {
5354                         /* tp->last_tag is used in tg3_int_reenable() below
5355                          * to tell the hw how much work has been processed,
5356                          * so we must read it before checking for more work.
5357                          */
5358                         tnapi->last_tag = sblk->status_tag;
5359                         tnapi->last_irq_tag = tnapi->last_tag;
5360                         rmb();
5361                 } else
5362                         sblk->status &= ~SD_STATUS_UPDATED;
5363
5364                 if (likely(!tg3_has_work(tnapi))) {
5365                         napi_complete(napi);
5366                         tg3_int_reenable(tnapi);
5367                         break;
5368                 }
5369         }
5370
5371         return work_done;
5372
5373 tx_recovery:
5374         /* work_done is guaranteed to be less than budget. */
5375         napi_complete(napi);
5376         schedule_work(&tp->reset_task);
5377         return work_done;
5378 }
5379
5380 static void tg3_napi_disable(struct tg3 *tp)
5381 {
5382         int i;
5383
5384         for (i = tp->irq_cnt - 1; i >= 0; i--)
5385                 napi_disable(&tp->napi[i].napi);
5386 }
5387
5388 static void tg3_napi_enable(struct tg3 *tp)
5389 {
5390         int i;
5391
5392         for (i = 0; i < tp->irq_cnt; i++)
5393                 napi_enable(&tp->napi[i].napi);
5394 }
5395
5396 static void tg3_napi_init(struct tg3 *tp)
5397 {
5398         int i;
5399
5400         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5401         for (i = 1; i < tp->irq_cnt; i++)
5402                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5403 }
5404
5405 static void tg3_napi_fini(struct tg3 *tp)
5406 {
5407         int i;
5408
5409         for (i = 0; i < tp->irq_cnt; i++)
5410                 netif_napi_del(&tp->napi[i].napi);
5411 }
5412
5413 static inline void tg3_netif_stop(struct tg3 *tp)
5414 {
5415         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5416         tg3_napi_disable(tp);
5417         netif_tx_disable(tp->dev);
5418 }
5419
5420 static inline void tg3_netif_start(struct tg3 *tp)
5421 {
5422         /* NOTE: unconditional netif_tx_wake_all_queues is only
5423          * appropriate so long as all callers are assured to
5424          * have free tx slots (such as after tg3_init_hw)
5425          */
5426         netif_tx_wake_all_queues(tp->dev);
5427
5428         tg3_napi_enable(tp);
5429         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5430         tg3_enable_ints(tp);
5431 }
5432
5433 static void tg3_irq_quiesce(struct tg3 *tp)
5434 {
5435         int i;
5436
5437         BUG_ON(tp->irq_sync);
5438
5439         tp->irq_sync = 1;
5440         smp_mb();
5441
5442         for (i = 0; i < tp->irq_cnt; i++)
5443                 synchronize_irq(tp->napi[i].irq_vec);
5444 }
5445
5446 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5447  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5448  * with as well.  Most of the time, this is not necessary except when
5449  * shutting down the device.
5450  */
5451 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5452 {
5453         spin_lock_bh(&tp->lock);
5454         if (irq_sync)
5455                 tg3_irq_quiesce(tp);
5456 }
5457
5458 static inline void tg3_full_unlock(struct tg3 *tp)
5459 {
5460         spin_unlock_bh(&tp->lock);
5461 }
5462
5463 /* One-shot MSI handler - Chip automatically disables interrupt
5464  * after sending MSI so driver doesn't have to do it.
5465  */
5466 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5467 {
5468         struct tg3_napi *tnapi = dev_id;
5469         struct tg3 *tp = tnapi->tp;
5470
5471         prefetch(tnapi->hw_status);
5472         if (tnapi->rx_rcb)
5473                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5474
5475         if (likely(!tg3_irq_sync(tp)))
5476                 napi_schedule(&tnapi->napi);
5477
5478         return IRQ_HANDLED;
5479 }
5480
5481 /* MSI ISR - No need to check for interrupt sharing and no need to
5482  * flush status block and interrupt mailbox. PCI ordering rules
5483  * guarantee that MSI will arrive after the status block.
5484  */
5485 static irqreturn_t tg3_msi(int irq, void *dev_id)
5486 {
5487         struct tg3_napi *tnapi = dev_id;
5488         struct tg3 *tp = tnapi->tp;
5489
5490         prefetch(tnapi->hw_status);
5491         if (tnapi->rx_rcb)
5492                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5493         /*
5494          * Writing any value to intr-mbox-0 clears PCI INTA# and
5495          * chip-internal interrupt pending events.
5496          * Writing non-zero to intr-mbox-0 additional tells the
5497          * NIC to stop sending us irqs, engaging "in-intr-handler"
5498          * event coalescing.
5499          */
5500         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5501         if (likely(!tg3_irq_sync(tp)))
5502                 napi_schedule(&tnapi->napi);
5503
5504         return IRQ_RETVAL(1);
5505 }
5506
5507 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5508 {
5509         struct tg3_napi *tnapi = dev_id;
5510         struct tg3 *tp = tnapi->tp;
5511         struct tg3_hw_status *sblk = tnapi->hw_status;
5512         unsigned int handled = 1;
5513
5514         /* In INTx mode, it is possible for the interrupt to arrive at
5515          * the CPU before the status block posted prior to the interrupt.
5516          * Reading the PCI State register will confirm whether the
5517          * interrupt is ours and will flush the status block.
5518          */
5519         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5520                 if (tg3_flag(tp, CHIP_RESETTING) ||
5521                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5522                         handled = 0;
5523                         goto out;
5524                 }
5525         }
5526
5527         /*
5528          * Writing any value to intr-mbox-0 clears PCI INTA# and
5529          * chip-internal interrupt pending events.
5530          * Writing non-zero to intr-mbox-0 additional tells the
5531          * NIC to stop sending us irqs, engaging "in-intr-handler"
5532          * event coalescing.
5533          *
5534          * Flush the mailbox to de-assert the IRQ immediately to prevent
5535          * spurious interrupts.  The flush impacts performance but
5536          * excessive spurious interrupts can be worse in some cases.
5537          */
5538         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5539         if (tg3_irq_sync(tp))
5540                 goto out;
5541         sblk->status &= ~SD_STATUS_UPDATED;
5542         if (likely(tg3_has_work(tnapi))) {
5543                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5544                 napi_schedule(&tnapi->napi);
5545         } else {
5546                 /* No work, shared interrupt perhaps?  re-enable
5547                  * interrupts, and flush that PCI write
5548                  */
5549                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5550                                0x00000000);
5551         }
5552 out:
5553         return IRQ_RETVAL(handled);
5554 }
5555
5556 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5557 {
5558         struct tg3_napi *tnapi = dev_id;
5559         struct tg3 *tp = tnapi->tp;
5560         struct tg3_hw_status *sblk = tnapi->hw_status;
5561         unsigned int handled = 1;
5562
5563         /* In INTx mode, it is possible for the interrupt to arrive at
5564          * the CPU before the status block posted prior to the interrupt.
5565          * Reading the PCI State register will confirm whether the
5566          * interrupt is ours and will flush the status block.
5567          */
5568         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5569                 if (tg3_flag(tp, CHIP_RESETTING) ||
5570                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5571                         handled = 0;
5572                         goto out;
5573                 }
5574         }
5575
5576         /*
5577          * writing any value to intr-mbox-0 clears PCI INTA# and
5578          * chip-internal interrupt pending events.
5579          * writing non-zero to intr-mbox-0 additional tells the
5580          * NIC to stop sending us irqs, engaging "in-intr-handler"
5581          * event coalescing.
5582          *
5583          * Flush the mailbox to de-assert the IRQ immediately to prevent
5584          * spurious interrupts.  The flush impacts performance but
5585          * excessive spurious interrupts can be worse in some cases.
5586          */
5587         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5588
5589         /*
5590          * In a shared interrupt configuration, sometimes other devices'
5591          * interrupts will scream.  We record the current status tag here
5592          * so that the above check can report that the screaming interrupts
5593          * are unhandled.  Eventually they will be silenced.
5594          */
5595         tnapi->last_irq_tag = sblk->status_tag;
5596
5597         if (tg3_irq_sync(tp))
5598                 goto out;
5599
5600         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5601
5602         napi_schedule(&tnapi->napi);
5603
5604 out:
5605         return IRQ_RETVAL(handled);
5606 }
5607
5608 /* ISR for interrupt test */
5609 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5610 {
5611         struct tg3_napi *tnapi = dev_id;
5612         struct tg3 *tp = tnapi->tp;
5613         struct tg3_hw_status *sblk = tnapi->hw_status;
5614
5615         if ((sblk->status & SD_STATUS_UPDATED) ||
5616             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5617                 tg3_disable_ints(tp);
5618                 return IRQ_RETVAL(1);
5619         }
5620         return IRQ_RETVAL(0);
5621 }
5622
5623 static int tg3_init_hw(struct tg3 *, int);
5624 static int tg3_halt(struct tg3 *, int, int);
5625
5626 /* Restart hardware after configuration changes, self-test, etc.
5627  * Invoked with tp->lock held.
5628  */
5629 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5630         __releases(tp->lock)
5631         __acquires(tp->lock)
5632 {
5633         int err;
5634
5635         err = tg3_init_hw(tp, reset_phy);
5636         if (err) {
5637                 netdev_err(tp->dev,
5638                            "Failed to re-initialize device, aborting\n");
5639                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5640                 tg3_full_unlock(tp);
5641                 del_timer_sync(&tp->timer);
5642                 tp->irq_sync = 0;
5643                 tg3_napi_enable(tp);
5644                 dev_close(tp->dev);
5645                 tg3_full_lock(tp, 0);
5646         }
5647         return err;
5648 }
5649
5650 #ifdef CONFIG_NET_POLL_CONTROLLER
5651 static void tg3_poll_controller(struct net_device *dev)
5652 {
5653         int i;
5654         struct tg3 *tp = netdev_priv(dev);
5655
5656         for (i = 0; i < tp->irq_cnt; i++)
5657                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5658 }
5659 #endif
5660
5661 static void tg3_reset_task(struct work_struct *work)
5662 {
5663         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5664         int err;
5665         unsigned int restart_timer;
5666
5667         tg3_full_lock(tp, 0);
5668
5669         if (!netif_running(tp->dev)) {
5670                 tg3_full_unlock(tp);
5671                 return;
5672         }
5673
5674         tg3_full_unlock(tp);
5675
5676         tg3_phy_stop(tp);
5677
5678         tg3_netif_stop(tp);
5679
5680         tg3_full_lock(tp, 1);
5681
5682         restart_timer = tg3_flag(tp, RESTART_TIMER);
5683         tg3_flag_clear(tp, RESTART_TIMER);
5684
5685         if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
5686                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5687                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5688                 tg3_flag_set(tp, MBOX_WRITE_REORDER);
5689                 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
5690         }
5691
5692         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5693         err = tg3_init_hw(tp, 1);
5694         if (err)
5695                 goto out;
5696
5697         tg3_netif_start(tp);
5698
5699         if (restart_timer)
5700                 mod_timer(&tp->timer, jiffies + 1);
5701
5702 out:
5703         tg3_full_unlock(tp);
5704
5705         if (!err)
5706                 tg3_phy_start(tp);
5707 }
5708
5709 static void tg3_tx_timeout(struct net_device *dev)
5710 {
5711         struct tg3 *tp = netdev_priv(dev);
5712
5713         if (netif_msg_tx_err(tp)) {
5714                 netdev_err(dev, "transmit timed out, resetting\n");
5715                 tg3_dump_state(tp);
5716         }
5717
5718         schedule_work(&tp->reset_task);
5719 }
5720
5721 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5722 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5723 {
5724         u32 base = (u32) mapping & 0xffffffff;
5725
5726         return (base > 0xffffdcc0) && (base + len + 8 < base);
5727 }
5728
5729 /* Test for DMA addresses > 40-bit */
5730 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5731                                           int len)
5732 {
5733 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5734         if (tg3_flag(tp, 40BIT_DMA_BUG))
5735                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5736         return 0;
5737 #else
5738         return 0;
5739 #endif
5740 }
5741
5742 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5743                         dma_addr_t mapping, int len, u32 flags,
5744                         u32 mss_and_is_end)
5745 {
5746         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5747         int is_end = (mss_and_is_end & 0x1);
5748         u32 mss = (mss_and_is_end >> 1);
5749         u32 vlan_tag = 0;
5750
5751         if (is_end)
5752                 flags |= TXD_FLAG_END;
5753         if (flags & TXD_FLAG_VLAN) {
5754                 vlan_tag = flags >> 16;
5755                 flags &= 0xffff;
5756         }
5757         vlan_tag |= (mss << TXD_MSS_SHIFT);
5758
5759         txd->addr_hi = ((u64) mapping >> 32);
5760         txd->addr_lo = ((u64) mapping & 0xffffffff);
5761         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5762         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5763 }
5764
5765 static void tg3_skb_error_unmap(struct tg3_napi *tnapi,
5766                                 struct sk_buff *skb, int last)
5767 {
5768         int i;
5769         u32 entry = tnapi->tx_prod;
5770         struct ring_info *txb = &tnapi->tx_buffers[entry];
5771
5772         pci_unmap_single(tnapi->tp->pdev,
5773                          dma_unmap_addr(txb, mapping),
5774                          skb_headlen(skb),
5775                          PCI_DMA_TODEVICE);
5776         for (i = 0; i <= last; i++) {
5777                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5778
5779                 entry = NEXT_TX(entry);
5780                 txb = &tnapi->tx_buffers[entry];
5781
5782                 pci_unmap_page(tnapi->tp->pdev,
5783                                dma_unmap_addr(txb, mapping),
5784                                frag->size, PCI_DMA_TODEVICE);
5785         }
5786 }
5787
5788 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5789 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5790                                        struct sk_buff *skb,
5791                                        u32 base_flags, u32 mss)
5792 {
5793         struct tg3 *tp = tnapi->tp;
5794         struct sk_buff *new_skb;
5795         dma_addr_t new_addr = 0;
5796         u32 entry = tnapi->tx_prod;
5797         int ret = 0;
5798
5799         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5800                 new_skb = skb_copy(skb, GFP_ATOMIC);
5801         else {
5802                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5803
5804                 new_skb = skb_copy_expand(skb,
5805                                           skb_headroom(skb) + more_headroom,
5806                                           skb_tailroom(skb), GFP_ATOMIC);
5807         }
5808
5809         if (!new_skb) {
5810                 ret = -1;
5811         } else {
5812                 /* New SKB is guaranteed to be linear. */
5813                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5814                                           PCI_DMA_TODEVICE);
5815                 /* Make sure the mapping succeeded */
5816                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5817                         ret = -1;
5818                         dev_kfree_skb(new_skb);
5819
5820                 /* Make sure new skb does not cross any 4G boundaries.
5821                  * Drop the packet if it does.
5822                  */
5823                 } else if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
5824                            tg3_4g_overflow_test(new_addr, new_skb->len)) {
5825                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5826                                          PCI_DMA_TODEVICE);
5827                         ret = -1;
5828                         dev_kfree_skb(new_skb);
5829                 } else {
5830                         tnapi->tx_buffers[entry].skb = new_skb;
5831                         dma_unmap_addr_set(&tnapi->tx_buffers[entry],
5832                                            mapping, new_addr);
5833
5834                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5835                                     base_flags, 1 | (mss << 1));
5836                 }
5837         }
5838
5839         dev_kfree_skb(skb);
5840
5841         return ret;
5842 }
5843
5844 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
5845
5846 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5847  * TSO header is greater than 80 bytes.
5848  */
5849 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5850 {
5851         struct sk_buff *segs, *nskb;
5852         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5853
5854         /* Estimate the number of fragments in the worst case */
5855         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5856                 netif_stop_queue(tp->dev);
5857
5858                 /* netif_tx_stop_queue() must be done before checking
5859                  * checking tx index in tg3_tx_avail() below, because in
5860                  * tg3_tx(), we update tx index before checking for
5861                  * netif_tx_queue_stopped().
5862                  */
5863                 smp_mb();
5864                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5865                         return NETDEV_TX_BUSY;
5866
5867                 netif_wake_queue(tp->dev);
5868         }
5869
5870         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5871         if (IS_ERR(segs))
5872                 goto tg3_tso_bug_end;
5873
5874         do {
5875                 nskb = segs;
5876                 segs = segs->next;
5877                 nskb->next = NULL;
5878                 tg3_start_xmit(nskb, tp->dev);
5879         } while (segs);
5880
5881 tg3_tso_bug_end:
5882         dev_kfree_skb(skb);
5883
5884         return NETDEV_TX_OK;
5885 }
5886
5887 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5888  * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
5889  */
5890 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5891 {
5892         struct tg3 *tp = netdev_priv(dev);
5893         u32 len, entry, base_flags, mss;
5894         int i = -1, would_hit_hwbug;
5895         dma_addr_t mapping;
5896         struct tg3_napi *tnapi;
5897         struct netdev_queue *txq;
5898         unsigned int last;
5899
5900         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5901         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5902         if (tg3_flag(tp, ENABLE_TSS))
5903                 tnapi++;
5904
5905         /* We are running in BH disabled context with netif_tx_lock
5906          * and TX reclaim runs via tp->napi.poll inside of a software
5907          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5908          * no IRQ context deadlocks to worry about either.  Rejoice!
5909          */
5910         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5911                 if (!netif_tx_queue_stopped(txq)) {
5912                         netif_tx_stop_queue(txq);
5913
5914                         /* This is a hard error, log it. */
5915                         netdev_err(dev,
5916                                    "BUG! Tx Ring full when queue awake!\n");
5917                 }
5918                 return NETDEV_TX_BUSY;
5919         }
5920
5921         entry = tnapi->tx_prod;
5922         base_flags = 0;
5923         if (skb->ip_summed == CHECKSUM_PARTIAL)
5924                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5925
5926         mss = skb_shinfo(skb)->gso_size;
5927         if (mss) {
5928                 struct iphdr *iph;
5929                 u32 tcp_opt_len, hdr_len;
5930
5931                 if (skb_header_cloned(skb) &&
5932                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5933                         dev_kfree_skb(skb);
5934                         goto out_unlock;
5935                 }
5936
5937                 iph = ip_hdr(skb);
5938                 tcp_opt_len = tcp_optlen(skb);
5939
5940                 if (skb_is_gso_v6(skb)) {
5941                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5942                 } else {
5943                         u32 ip_tcp_len;
5944
5945                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5946                         hdr_len = ip_tcp_len + tcp_opt_len;
5947
5948                         iph->check = 0;
5949                         iph->tot_len = htons(mss + hdr_len);
5950                 }
5951
5952                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5953                     tg3_flag(tp, TSO_BUG))
5954                         return tg3_tso_bug(tp, skb);
5955
5956                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5957                                TXD_FLAG_CPU_POST_DMA);
5958
5959                 if (tg3_flag(tp, HW_TSO_1) ||
5960                     tg3_flag(tp, HW_TSO_2) ||
5961                     tg3_flag(tp, HW_TSO_3)) {
5962                         tcp_hdr(skb)->check = 0;
5963                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5964                 } else
5965                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5966                                                                  iph->daddr, 0,
5967                                                                  IPPROTO_TCP,
5968                                                                  0);
5969
5970                 if (tg3_flag(tp, HW_TSO_3)) {
5971                         mss |= (hdr_len & 0xc) << 12;
5972                         if (hdr_len & 0x10)
5973                                 base_flags |= 0x00000010;
5974                         base_flags |= (hdr_len & 0x3e0) << 5;
5975                 } else if (tg3_flag(tp, HW_TSO_2))
5976                         mss |= hdr_len << 9;
5977                 else if (tg3_flag(tp, HW_TSO_1) ||
5978                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5979                         if (tcp_opt_len || iph->ihl > 5) {
5980                                 int tsflags;
5981
5982                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5983                                 mss |= (tsflags << 11);
5984                         }
5985                 } else {
5986                         if (tcp_opt_len || iph->ihl > 5) {
5987                                 int tsflags;
5988
5989                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5990                                 base_flags |= tsflags << 12;
5991                         }
5992                 }
5993         }
5994
5995         if (vlan_tx_tag_present(skb))
5996                 base_flags |= (TXD_FLAG_VLAN |
5997                                (vlan_tx_tag_get(skb) << 16));
5998
5999         if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
6000             !mss && skb->len > VLAN_ETH_FRAME_LEN)
6001                 base_flags |= TXD_FLAG_JMB_PKT;
6002
6003         len = skb_headlen(skb);
6004
6005         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6006         if (pci_dma_mapping_error(tp->pdev, mapping)) {
6007                 dev_kfree_skb(skb);
6008                 goto out_unlock;
6009         }
6010
6011         tnapi->tx_buffers[entry].skb = skb;
6012         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6013
6014         would_hit_hwbug = 0;
6015
6016         if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
6017                 would_hit_hwbug = 1;
6018
6019         if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
6020             tg3_4g_overflow_test(mapping, len))
6021                 would_hit_hwbug = 1;
6022
6023         if (tg3_flag(tp, 40BIT_DMA_LIMIT_BUG) &&
6024             tg3_40bit_overflow_test(tp, mapping, len))
6025                 would_hit_hwbug = 1;
6026
6027         if (tg3_flag(tp, 5701_DMA_BUG))
6028                 would_hit_hwbug = 1;
6029
6030         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6031                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6032
6033         entry = NEXT_TX(entry);
6034
6035         /* Now loop through additional data fragments, and queue them. */
6036         if (skb_shinfo(skb)->nr_frags > 0) {
6037                 last = skb_shinfo(skb)->nr_frags - 1;
6038                 for (i = 0; i <= last; i++) {
6039                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6040
6041                         len = frag->size;
6042                         mapping = pci_map_page(tp->pdev,
6043                                                frag->page,
6044                                                frag->page_offset,
6045                                                len, PCI_DMA_TODEVICE);
6046
6047                         tnapi->tx_buffers[entry].skb = NULL;
6048                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6049                                            mapping);
6050                         if (pci_dma_mapping_error(tp->pdev, mapping))
6051                                 goto dma_error;
6052
6053                         if (tg3_flag(tp, SHORT_DMA_BUG) &&
6054                             len <= 8)
6055                                 would_hit_hwbug = 1;
6056
6057                         if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
6058                             tg3_4g_overflow_test(mapping, len))
6059                                 would_hit_hwbug = 1;
6060
6061                         if (tg3_flag(tp, 40BIT_DMA_LIMIT_BUG) &&
6062                             tg3_40bit_overflow_test(tp, mapping, len))
6063                                 would_hit_hwbug = 1;
6064
6065                         if (tg3_flag(tp, HW_TSO_1) ||
6066                             tg3_flag(tp, HW_TSO_2) ||
6067                             tg3_flag(tp, HW_TSO_3))
6068                                 tg3_set_txd(tnapi, entry, mapping, len,
6069                                             base_flags, (i == last)|(mss << 1));
6070                         else
6071                                 tg3_set_txd(tnapi, entry, mapping, len,
6072                                             base_flags, (i == last));
6073
6074                         entry = NEXT_TX(entry);
6075                 }
6076         }
6077
6078         if (would_hit_hwbug) {
6079                 tg3_skb_error_unmap(tnapi, skb, i);
6080
6081                 /* If the workaround fails due to memory/mapping
6082                  * failure, silently drop this packet.
6083                  */
6084                 if (tigon3_dma_hwbug_workaround(tnapi, skb, base_flags, mss))
6085                         goto out_unlock;
6086
6087                 entry = NEXT_TX(tnapi->tx_prod);
6088         }
6089
6090         /* Packets are ready, update Tx producer idx local and on card. */
6091         tw32_tx_mbox(tnapi->prodmbox, entry);
6092
6093         tnapi->tx_prod = entry;
6094         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6095                 netif_tx_stop_queue(txq);
6096
6097                 /* netif_tx_stop_queue() must be done before checking
6098                  * checking tx index in tg3_tx_avail() below, because in
6099                  * tg3_tx(), we update tx index before checking for
6100                  * netif_tx_queue_stopped().
6101                  */
6102                 smp_mb();
6103                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6104                         netif_tx_wake_queue(txq);
6105         }
6106
6107 out_unlock:
6108         mmiowb();
6109
6110         return NETDEV_TX_OK;
6111
6112 dma_error:
6113         tg3_skb_error_unmap(tnapi, skb, i);
6114         dev_kfree_skb(skb);
6115         tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
6116         return NETDEV_TX_OK;
6117 }
6118
6119 static void tg3_set_loopback(struct net_device *dev, u32 features)
6120 {
6121         struct tg3 *tp = netdev_priv(dev);
6122
6123         if (features & NETIF_F_LOOPBACK) {
6124                 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
6125                         return;
6126
6127                 /*
6128                  * Clear MAC_MODE_HALF_DUPLEX or you won't get packets back in
6129                  * loopback mode if Half-Duplex mode was negotiated earlier.
6130                  */
6131                 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
6132
6133                 /* Enable internal MAC loopback mode */
6134                 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
6135                 spin_lock_bh(&tp->lock);
6136                 tw32(MAC_MODE, tp->mac_mode);
6137                 netif_carrier_on(tp->dev);
6138                 spin_unlock_bh(&tp->lock);
6139                 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
6140         } else {
6141                 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
6142                         return;
6143
6144                 /* Disable internal MAC loopback mode */
6145                 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
6146                 spin_lock_bh(&tp->lock);
6147                 tw32(MAC_MODE, tp->mac_mode);
6148                 /* Force link status check */
6149                 tg3_setup_phy(tp, 1);
6150                 spin_unlock_bh(&tp->lock);
6151                 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
6152         }
6153 }
6154
6155 static u32 tg3_fix_features(struct net_device *dev, u32 features)
6156 {
6157         struct tg3 *tp = netdev_priv(dev);
6158
6159         if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
6160                 features &= ~NETIF_F_ALL_TSO;
6161
6162         return features;
6163 }
6164
6165 static int tg3_set_features(struct net_device *dev, u32 features)
6166 {
6167         u32 changed = dev->features ^ features;
6168
6169         if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
6170                 tg3_set_loopback(dev, features);
6171
6172         return 0;
6173 }
6174
6175 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6176                                int new_mtu)
6177 {
6178         dev->mtu = new_mtu;
6179
6180         if (new_mtu > ETH_DATA_LEN) {
6181                 if (tg3_flag(tp, 5780_CLASS)) {
6182                         netdev_update_features(dev);
6183                         tg3_flag_clear(tp, TSO_CAPABLE);
6184                 } else {
6185                         tg3_flag_set(tp, JUMBO_RING_ENABLE);
6186                 }
6187         } else {
6188                 if (tg3_flag(tp, 5780_CLASS)) {
6189                         tg3_flag_set(tp, TSO_CAPABLE);
6190                         netdev_update_features(dev);
6191                 }
6192                 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
6193         }
6194 }
6195
6196 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6197 {
6198         struct tg3 *tp = netdev_priv(dev);
6199         int err;
6200
6201         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6202                 return -EINVAL;
6203
6204         if (!netif_running(dev)) {
6205                 /* We'll just catch it later when the
6206                  * device is up'd.
6207                  */
6208                 tg3_set_mtu(dev, tp, new_mtu);
6209                 return 0;
6210         }
6211
6212         tg3_phy_stop(tp);
6213
6214         tg3_netif_stop(tp);
6215
6216         tg3_full_lock(tp, 1);
6217
6218         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6219
6220         tg3_set_mtu(dev, tp, new_mtu);
6221
6222         err = tg3_restart_hw(tp, 0);
6223
6224         if (!err)
6225                 tg3_netif_start(tp);
6226
6227         tg3_full_unlock(tp);
6228
6229         if (!err)
6230                 tg3_phy_start(tp);
6231
6232         return err;
6233 }
6234
6235 static void tg3_rx_prodring_free(struct tg3 *tp,
6236                                  struct tg3_rx_prodring_set *tpr)
6237 {
6238         int i;
6239
6240         if (tpr != &tp->napi[0].prodring) {
6241                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6242                      i = (i + 1) & tp->rx_std_ring_mask)
6243                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6244                                         tp->rx_pkt_map_sz);
6245
6246                 if (tg3_flag(tp, JUMBO_CAPABLE)) {
6247                         for (i = tpr->rx_jmb_cons_idx;
6248                              i != tpr->rx_jmb_prod_idx;
6249                              i = (i + 1) & tp->rx_jmb_ring_mask) {
6250                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6251                                                 TG3_RX_JMB_MAP_SZ);
6252                         }
6253                 }
6254
6255                 return;
6256         }
6257
6258         for (i = 0; i <= tp->rx_std_ring_mask; i++)
6259                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6260                                 tp->rx_pkt_map_sz);
6261
6262         if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
6263                 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6264                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6265                                         TG3_RX_JMB_MAP_SZ);
6266         }
6267 }
6268
6269 /* Initialize rx rings for packet processing.
6270  *
6271  * The chip has been shut down and the driver detached from
6272  * the networking, so no interrupts or new tx packets will
6273  * end up in the driver.  tp->{tx,}lock are held and thus
6274  * we may not sleep.
6275  */
6276 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6277                                  struct tg3_rx_prodring_set *tpr)
6278 {
6279         u32 i, rx_pkt_dma_sz;
6280
6281         tpr->rx_std_cons_idx = 0;
6282         tpr->rx_std_prod_idx = 0;
6283         tpr->rx_jmb_cons_idx = 0;
6284         tpr->rx_jmb_prod_idx = 0;
6285
6286         if (tpr != &tp->napi[0].prodring) {
6287                 memset(&tpr->rx_std_buffers[0], 0,
6288                        TG3_RX_STD_BUFF_RING_SIZE(tp));
6289                 if (tpr->rx_jmb_buffers)
6290                         memset(&tpr->rx_jmb_buffers[0], 0,
6291                                TG3_RX_JMB_BUFF_RING_SIZE(tp));
6292                 goto done;
6293         }
6294
6295         /* Zero out all descriptors. */
6296         memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6297
6298         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6299         if (tg3_flag(tp, 5780_CLASS) &&
6300             tp->dev->mtu > ETH_DATA_LEN)
6301                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6302         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6303
6304         /* Initialize invariants of the rings, we only set this
6305          * stuff once.  This works because the card does not
6306          * write into the rx buffer posting rings.
6307          */
6308         for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6309                 struct tg3_rx_buffer_desc *rxd;
6310
6311                 rxd = &tpr->rx_std[i];
6312                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6313                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6314                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6315                                (i << RXD_OPAQUE_INDEX_SHIFT));
6316         }
6317
6318         /* Now allocate fresh SKBs for each rx ring. */
6319         for (i = 0; i < tp->rx_pending; i++) {
6320                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6321                         netdev_warn(tp->dev,
6322                                     "Using a smaller RX standard ring. Only "
6323                                     "%d out of %d buffers were allocated "
6324                                     "successfully\n", i, tp->rx_pending);
6325                         if (i == 0)
6326                                 goto initfail;
6327                         tp->rx_pending = i;
6328                         break;
6329                 }
6330         }
6331
6332         if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
6333                 goto done;
6334
6335         memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6336
6337         if (!tg3_flag(tp, JUMBO_RING_ENABLE))
6338                 goto done;
6339
6340         for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6341                 struct tg3_rx_buffer_desc *rxd;
6342
6343                 rxd = &tpr->rx_jmb[i].std;
6344                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6345                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6346                                   RXD_FLAG_JUMBO;
6347                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6348                        (i << RXD_OPAQUE_INDEX_SHIFT));
6349         }
6350
6351         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6352                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6353                         netdev_warn(tp->dev,
6354                                     "Using a smaller RX jumbo ring. Only %d "
6355                                     "out of %d buffers were allocated "
6356                                     "successfully\n", i, tp->rx_jumbo_pending);
6357                         if (i == 0)
6358                                 goto initfail;
6359                         tp->rx_jumbo_pending = i;
6360                         break;
6361                 }
6362         }
6363
6364 done:
6365         return 0;
6366
6367 initfail:
6368         tg3_rx_prodring_free(tp, tpr);
6369         return -ENOMEM;
6370 }
6371
6372 static void tg3_rx_prodring_fini(struct tg3 *tp,
6373                                  struct tg3_rx_prodring_set *tpr)
6374 {
6375         kfree(tpr->rx_std_buffers);
6376         tpr->rx_std_buffers = NULL;
6377         kfree(tpr->rx_jmb_buffers);
6378         tpr->rx_jmb_buffers = NULL;
6379         if (tpr->rx_std) {
6380                 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
6381                                   tpr->rx_std, tpr->rx_std_mapping);
6382                 tpr->rx_std = NULL;
6383         }
6384         if (tpr->rx_jmb) {
6385                 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
6386                                   tpr->rx_jmb, tpr->rx_jmb_mapping);
6387                 tpr->rx_jmb = NULL;
6388         }
6389 }
6390
6391 static int tg3_rx_prodring_init(struct tg3 *tp,
6392                                 struct tg3_rx_prodring_set *tpr)
6393 {
6394         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6395                                       GFP_KERNEL);
6396         if (!tpr->rx_std_buffers)
6397                 return -ENOMEM;
6398
6399         tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
6400                                          TG3_RX_STD_RING_BYTES(tp),
6401                                          &tpr->rx_std_mapping,
6402                                          GFP_KERNEL);
6403         if (!tpr->rx_std)
6404                 goto err_out;
6405
6406         if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
6407                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6408                                               GFP_KERNEL);
6409                 if (!tpr->rx_jmb_buffers)
6410                         goto err_out;
6411
6412                 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
6413                                                  TG3_RX_JMB_RING_BYTES(tp),
6414                                                  &tpr->rx_jmb_mapping,
6415                                                  GFP_KERNEL);
6416                 if (!tpr->rx_jmb)
6417                         goto err_out;
6418         }
6419
6420         return 0;
6421
6422 err_out:
6423         tg3_rx_prodring_fini(tp, tpr);
6424         return -ENOMEM;
6425 }
6426
6427 /* Free up pending packets in all rx/tx rings.
6428  *
6429  * The chip has been shut down and the driver detached from
6430  * the networking, so no interrupts or new tx packets will
6431  * end up in the driver.  tp->{tx,}lock is not held and we are not
6432  * in an interrupt context and thus may sleep.
6433  */
6434 static void tg3_free_rings(struct tg3 *tp)
6435 {
6436         int i, j;
6437
6438         for (j = 0; j < tp->irq_cnt; j++) {
6439                 struct tg3_napi *tnapi = &tp->napi[j];
6440
6441                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6442
6443                 if (!tnapi->tx_buffers)
6444                         continue;
6445
6446                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6447                         struct ring_info *txp;
6448                         struct sk_buff *skb;
6449                         unsigned int k;
6450
6451                         txp = &tnapi->tx_buffers[i];
6452                         skb = txp->skb;
6453
6454                         if (skb == NULL) {
6455                                 i++;
6456                                 continue;
6457                         }
6458
6459                         pci_unmap_single(tp->pdev,
6460                                          dma_unmap_addr(txp, mapping),
6461                                          skb_headlen(skb),
6462                                          PCI_DMA_TODEVICE);
6463                         txp->skb = NULL;
6464
6465                         i++;
6466
6467                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6468                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6469                                 pci_unmap_page(tp->pdev,
6470                                                dma_unmap_addr(txp, mapping),
6471                                                skb_shinfo(skb)->frags[k].size,
6472                                                PCI_DMA_TODEVICE);
6473                                 i++;
6474                         }
6475
6476                         dev_kfree_skb_any(skb);
6477                 }
6478         }
6479 }
6480
6481 /* Initialize tx/rx rings for packet processing.
6482  *
6483  * The chip has been shut down and the driver detached from
6484  * the networking, so no interrupts or new tx packets will
6485  * end up in the driver.  tp->{tx,}lock are held and thus
6486  * we may not sleep.
6487  */
6488 static int tg3_init_rings(struct tg3 *tp)
6489 {
6490         int i;
6491
6492         /* Free up all the SKBs. */
6493         tg3_free_rings(tp);
6494
6495         for (i = 0; i < tp->irq_cnt; i++) {
6496                 struct tg3_napi *tnapi = &tp->napi[i];
6497
6498                 tnapi->last_tag = 0;
6499                 tnapi->last_irq_tag = 0;
6500                 tnapi->hw_status->status = 0;
6501                 tnapi->hw_status->status_tag = 0;
6502                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6503
6504                 tnapi->tx_prod = 0;
6505                 tnapi->tx_cons = 0;
6506                 if (tnapi->tx_ring)
6507                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6508
6509                 tnapi->rx_rcb_ptr = 0;
6510                 if (tnapi->rx_rcb)
6511                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6512
6513                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6514                         tg3_free_rings(tp);
6515                         return -ENOMEM;
6516                 }
6517         }
6518
6519         return 0;
6520 }
6521
6522 /*
6523  * Must not be invoked with interrupt sources disabled and
6524  * the hardware shutdown down.
6525  */
6526 static void tg3_free_consistent(struct tg3 *tp)
6527 {
6528         int i;
6529
6530         for (i = 0; i < tp->irq_cnt; i++) {
6531                 struct tg3_napi *tnapi = &tp->napi[i];
6532
6533                 if (tnapi->tx_ring) {
6534                         dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
6535                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6536                         tnapi->tx_ring = NULL;
6537                 }
6538
6539                 kfree(tnapi->tx_buffers);
6540                 tnapi->tx_buffers = NULL;
6541
6542                 if (tnapi->rx_rcb) {
6543                         dma_free_coherent(&tp->pdev->dev,
6544                                           TG3_RX_RCB_RING_BYTES(tp),
6545                                           tnapi->rx_rcb,
6546                                           tnapi->rx_rcb_mapping);
6547                         tnapi->rx_rcb = NULL;
6548                 }
6549
6550                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6551
6552                 if (tnapi->hw_status) {
6553                         dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
6554                                           tnapi->hw_status,
6555                                           tnapi->status_mapping);
6556                         tnapi->hw_status = NULL;
6557                 }
6558         }
6559
6560         if (tp->hw_stats) {
6561                 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
6562                                   tp->hw_stats, tp->stats_mapping);
6563                 tp->hw_stats = NULL;
6564         }
6565 }
6566
6567 /*
6568  * Must not be invoked with interrupt sources disabled and
6569  * the hardware shutdown down.  Can sleep.
6570  */
6571 static int tg3_alloc_consistent(struct tg3 *tp)
6572 {
6573         int i;
6574
6575         tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
6576                                           sizeof(struct tg3_hw_stats),
6577                                           &tp->stats_mapping,
6578                                           GFP_KERNEL);
6579         if (!tp->hw_stats)
6580                 goto err_out;
6581
6582         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6583
6584         for (i = 0; i < tp->irq_cnt; i++) {
6585                 struct tg3_napi *tnapi = &tp->napi[i];
6586                 struct tg3_hw_status *sblk;
6587
6588                 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
6589                                                       TG3_HW_STATUS_SIZE,
6590                                                       &tnapi->status_mapping,
6591                                                       GFP_KERNEL);
6592                 if (!tnapi->hw_status)
6593                         goto err_out;
6594
6595                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6596                 sblk = tnapi->hw_status;
6597
6598                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6599                         goto err_out;
6600
6601                 /* If multivector TSS is enabled, vector 0 does not handle
6602                  * tx interrupts.  Don't allocate any resources for it.
6603                  */
6604                 if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
6605                     (i && tg3_flag(tp, ENABLE_TSS))) {
6606                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6607                                                     TG3_TX_RING_SIZE,
6608                                                     GFP_KERNEL);
6609                         if (!tnapi->tx_buffers)
6610                                 goto err_out;
6611
6612                         tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
6613                                                             TG3_TX_RING_BYTES,
6614                                                         &tnapi->tx_desc_mapping,
6615                                                             GFP_KERNEL);
6616                         if (!tnapi->tx_ring)
6617                                 goto err_out;
6618                 }
6619
6620                 /*
6621                  * When RSS is enabled, the status block format changes
6622                  * slightly.  The "rx_jumbo_consumer", "reserved",
6623                  * and "rx_mini_consumer" members get mapped to the
6624                  * other three rx return ring producer indexes.
6625                  */
6626                 switch (i) {
6627                 default:
6628                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6629                         break;
6630                 case 2:
6631                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6632                         break;
6633                 case 3:
6634                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6635                         break;
6636                 case 4:
6637                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6638                         break;
6639                 }
6640
6641                 /*
6642                  * If multivector RSS is enabled, vector 0 does not handle
6643                  * rx or tx interrupts.  Don't allocate any resources for it.
6644                  */
6645                 if (!i && tg3_flag(tp, ENABLE_RSS))
6646                         continue;
6647
6648                 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
6649                                                    TG3_RX_RCB_RING_BYTES(tp),
6650                                                    &tnapi->rx_rcb_mapping,
6651                                                    GFP_KERNEL);
6652                 if (!tnapi->rx_rcb)
6653                         goto err_out;
6654
6655                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6656         }
6657
6658         return 0;
6659
6660 err_out:
6661         tg3_free_consistent(tp);
6662         return -ENOMEM;
6663 }
6664
6665 #define MAX_WAIT_CNT 1000
6666
6667 /* To stop a block, clear the enable bit and poll till it
6668  * clears.  tp->lock is held.
6669  */
6670 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6671 {
6672         unsigned int i;
6673         u32 val;
6674
6675         if (tg3_flag(tp, 5705_PLUS)) {
6676                 switch (ofs) {
6677                 case RCVLSC_MODE:
6678                 case DMAC_MODE:
6679                 case MBFREE_MODE:
6680                 case BUFMGR_MODE:
6681                 case MEMARB_MODE:
6682                         /* We can't enable/disable these bits of the
6683                          * 5705/5750, just say success.
6684                          */
6685                         return 0;
6686
6687                 default:
6688                         break;
6689                 }
6690         }
6691
6692         val = tr32(ofs);
6693         val &= ~enable_bit;
6694         tw32_f(ofs, val);
6695
6696         for (i = 0; i < MAX_WAIT_CNT; i++) {
6697                 udelay(100);
6698                 val = tr32(ofs);
6699                 if ((val & enable_bit) == 0)
6700                         break;
6701         }
6702
6703         if (i == MAX_WAIT_CNT && !silent) {
6704                 dev_err(&tp->pdev->dev,
6705                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6706                         ofs, enable_bit);
6707                 return -ENODEV;
6708         }
6709
6710         return 0;
6711 }
6712
6713 /* tp->lock is held. */
6714 static int tg3_abort_hw(struct tg3 *tp, int silent)
6715 {
6716         int i, err;
6717
6718         tg3_disable_ints(tp);
6719
6720         tp->rx_mode &= ~RX_MODE_ENABLE;
6721         tw32_f(MAC_RX_MODE, tp->rx_mode);
6722         udelay(10);
6723
6724         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6725         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6726         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6727         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6728         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6729         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6730
6731         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6732         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6733         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6734         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6735         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6736         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6737         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6738
6739         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6740         tw32_f(MAC_MODE, tp->mac_mode);
6741         udelay(40);
6742
6743         tp->tx_mode &= ~TX_MODE_ENABLE;
6744         tw32_f(MAC_TX_MODE, tp->tx_mode);
6745
6746         for (i = 0; i < MAX_WAIT_CNT; i++) {
6747                 udelay(100);
6748                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6749                         break;
6750         }
6751         if (i >= MAX_WAIT_CNT) {
6752                 dev_err(&tp->pdev->dev,
6753                         "%s timed out, TX_MODE_ENABLE will not clear "
6754                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6755                 err |= -ENODEV;
6756         }
6757
6758         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6759         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6760         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6761
6762         tw32(FTQ_RESET, 0xffffffff);
6763         tw32(FTQ_RESET, 0x00000000);
6764
6765         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6766         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6767
6768         for (i = 0; i < tp->irq_cnt; i++) {
6769                 struct tg3_napi *tnapi = &tp->napi[i];
6770                 if (tnapi->hw_status)
6771                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6772         }
6773         if (tp->hw_stats)
6774                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6775
6776         return err;
6777 }
6778
6779 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6780 {
6781         int i;
6782         u32 apedata;
6783
6784         /* NCSI does not support APE events */
6785         if (tg3_flag(tp, APE_HAS_NCSI))
6786                 return;
6787
6788         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6789         if (apedata != APE_SEG_SIG_MAGIC)
6790                 return;
6791
6792         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6793         if (!(apedata & APE_FW_STATUS_READY))
6794                 return;
6795
6796         /* Wait for up to 1 millisecond for APE to service previous event. */
6797         for (i = 0; i < 10; i++) {
6798                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6799                         return;
6800
6801                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6802
6803                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6804                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6805                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6806
6807                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6808
6809                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6810                         break;
6811
6812                 udelay(100);
6813         }
6814
6815         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6816                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6817 }
6818
6819 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6820 {
6821         u32 event;
6822         u32 apedata;
6823
6824         if (!tg3_flag(tp, ENABLE_APE))
6825                 return;
6826
6827         switch (kind) {
6828         case RESET_KIND_INIT:
6829                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6830                                 APE_HOST_SEG_SIG_MAGIC);
6831                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6832                                 APE_HOST_SEG_LEN_MAGIC);
6833                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6834                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6835                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6836                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6837                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6838                                 APE_HOST_BEHAV_NO_PHYLOCK);
6839                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6840                                     TG3_APE_HOST_DRVR_STATE_START);
6841
6842                 event = APE_EVENT_STATUS_STATE_START;
6843                 break;
6844         case RESET_KIND_SHUTDOWN:
6845                 /* With the interface we are currently using,
6846                  * APE does not track driver state.  Wiping
6847                  * out the HOST SEGMENT SIGNATURE forces
6848                  * the APE to assume OS absent status.
6849                  */
6850                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6851
6852                 if (device_may_wakeup(&tp->pdev->dev) &&
6853                     tg3_flag(tp, WOL_ENABLE)) {
6854                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6855                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6856                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6857                 } else
6858                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6859
6860                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6861
6862                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6863                 break;
6864         case RESET_KIND_SUSPEND:
6865                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6866                 break;
6867         default:
6868                 return;
6869         }
6870
6871         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6872
6873         tg3_ape_send_event(tp, event);
6874 }
6875
6876 /* tp->lock is held. */
6877 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6878 {
6879         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6880                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6881
6882         if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
6883                 switch (kind) {
6884                 case RESET_KIND_INIT:
6885                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6886                                       DRV_STATE_START);
6887                         break;
6888
6889                 case RESET_KIND_SHUTDOWN:
6890                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6891                                       DRV_STATE_UNLOAD);
6892                         break;
6893
6894                 case RESET_KIND_SUSPEND:
6895                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6896                                       DRV_STATE_SUSPEND);
6897                         break;
6898
6899                 default:
6900                         break;
6901                 }
6902         }
6903
6904         if (kind == RESET_KIND_INIT ||
6905             kind == RESET_KIND_SUSPEND)
6906                 tg3_ape_driver_state_change(tp, kind);
6907 }
6908
6909 /* tp->lock is held. */
6910 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6911 {
6912         if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
6913                 switch (kind) {
6914                 case RESET_KIND_INIT:
6915                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6916                                       DRV_STATE_START_DONE);
6917                         break;
6918
6919                 case RESET_KIND_SHUTDOWN:
6920                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6921                                       DRV_STATE_UNLOAD_DONE);
6922                         break;
6923
6924                 default:
6925                         break;
6926                 }
6927         }
6928
6929         if (kind == RESET_KIND_SHUTDOWN)
6930                 tg3_ape_driver_state_change(tp, kind);
6931 }
6932
6933 /* tp->lock is held. */
6934 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6935 {
6936         if (tg3_flag(tp, ENABLE_ASF)) {
6937                 switch (kind) {
6938                 case RESET_KIND_INIT:
6939                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6940                                       DRV_STATE_START);
6941                         break;
6942
6943                 case RESET_KIND_SHUTDOWN:
6944                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6945                                       DRV_STATE_UNLOAD);
6946                         break;
6947
6948                 case RESET_KIND_SUSPEND:
6949                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6950                                       DRV_STATE_SUSPEND);
6951                         break;
6952
6953                 default:
6954                         break;
6955                 }
6956         }
6957 }
6958
6959 static int tg3_poll_fw(struct tg3 *tp)
6960 {
6961         int i;
6962         u32 val;
6963
6964         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6965                 /* Wait up to 20ms for init done. */
6966                 for (i = 0; i < 200; i++) {
6967                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6968                                 return 0;
6969                         udelay(100);
6970                 }
6971                 return -ENODEV;
6972         }
6973
6974         /* Wait for firmware initialization to complete. */
6975         for (i = 0; i < 100000; i++) {
6976                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6977                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6978                         break;
6979                 udelay(10);
6980         }
6981
6982         /* Chip might not be fitted with firmware.  Some Sun onboard
6983          * parts are configured like that.  So don't signal the timeout
6984          * of the above loop as an error, but do report the lack of
6985          * running firmware once.
6986          */
6987         if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
6988                 tg3_flag_set(tp, NO_FWARE_REPORTED);
6989
6990                 netdev_info(tp->dev, "No firmware running\n");
6991         }
6992
6993         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6994                 /* The 57765 A0 needs a little more
6995                  * time to do some important work.
6996                  */
6997                 mdelay(10);
6998         }
6999
7000         return 0;
7001 }
7002
7003 /* Save PCI command register before chip reset */
7004 static void tg3_save_pci_state(struct tg3 *tp)
7005 {
7006         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
7007 }
7008
7009 /* Restore PCI state after chip reset */
7010 static void tg3_restore_pci_state(struct tg3 *tp)
7011 {
7012         u32 val;
7013
7014         /* Re-enable indirect register accesses. */
7015         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7016                                tp->misc_host_ctrl);
7017
7018         /* Set MAX PCI retry to zero. */
7019         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7020         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7021             tg3_flag(tp, PCIX_MODE))
7022                 val |= PCISTATE_RETRY_SAME_DMA;
7023         /* Allow reads and writes to the APE register and memory space. */
7024         if (tg3_flag(tp, ENABLE_APE))
7025                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7026                        PCISTATE_ALLOW_APE_SHMEM_WR |
7027                        PCISTATE_ALLOW_APE_PSPACE_WR;
7028         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7029
7030         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7031
7032         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7033                 if (tg3_flag(tp, PCI_EXPRESS))
7034                         pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7035                 else {
7036                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7037                                               tp->pci_cacheline_sz);
7038                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7039                                               tp->pci_lat_timer);
7040                 }
7041         }
7042
7043         /* Make sure PCI-X relaxed ordering bit is clear. */
7044         if (tg3_flag(tp, PCIX_MODE)) {
7045                 u16 pcix_cmd;
7046
7047                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7048                                      &pcix_cmd);
7049                 pcix_cmd &= ~PCI_X_CMD_ERO;
7050                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7051                                       pcix_cmd);
7052         }
7053
7054         if (tg3_flag(tp, 5780_CLASS)) {
7055
7056                 /* Chip reset on 5780 will reset MSI enable bit,
7057                  * so need to restore it.
7058                  */
7059                 if (tg3_flag(tp, USING_MSI)) {
7060                         u16 ctrl;
7061
7062                         pci_read_config_word(tp->pdev,
7063                                              tp->msi_cap + PCI_MSI_FLAGS,
7064                                              &ctrl);
7065                         pci_write_config_word(tp->pdev,
7066                                               tp->msi_cap + PCI_MSI_FLAGS,
7067                                               ctrl | PCI_MSI_FLAGS_ENABLE);
7068                         val = tr32(MSGINT_MODE);
7069                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7070                 }
7071         }
7072 }
7073
7074 static void tg3_stop_fw(struct tg3 *);
7075
7076 /* tp->lock is held. */
7077 static int tg3_chip_reset(struct tg3 *tp)
7078 {
7079         u32 val;
7080         void (*write_op)(struct tg3 *, u32, u32);
7081         int i, err;
7082
7083         tg3_nvram_lock(tp);
7084
7085         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7086
7087         /* No matching tg3_nvram_unlock() after this because
7088          * chip reset below will undo the nvram lock.
7089          */
7090         tp->nvram_lock_cnt = 0;
7091
7092         /* GRC_MISC_CFG core clock reset will clear the memory
7093          * enable bit in PCI register 4 and the MSI enable bit
7094          * on some chips, so we save relevant registers here.
7095          */
7096         tg3_save_pci_state(tp);
7097
7098         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7099             tg3_flag(tp, 5755_PLUS))
7100                 tw32(GRC_FASTBOOT_PC, 0);
7101
7102         /*
7103          * We must avoid the readl() that normally takes place.
7104          * It locks machines, causes machine checks, and other
7105          * fun things.  So, temporarily disable the 5701
7106          * hardware workaround, while we do the reset.
7107          */
7108         write_op = tp->write32;
7109         if (write_op == tg3_write_flush_reg32)
7110                 tp->write32 = tg3_write32;
7111
7112         /* Prevent the irq handler from reading or writing PCI registers
7113          * during chip reset when the memory enable bit in the PCI command
7114          * register may be cleared.  The chip does not generate interrupt
7115          * at this time, but the irq handler may still be called due to irq
7116          * sharing or irqpoll.
7117          */
7118         tg3_flag_set(tp, CHIP_RESETTING);
7119         for (i = 0; i < tp->irq_cnt; i++) {
7120                 struct tg3_napi *tnapi = &tp->napi[i];
7121                 if (tnapi->hw_status) {
7122                         tnapi->hw_status->status = 0;
7123                         tnapi->hw_status->status_tag = 0;
7124                 }
7125                 tnapi->last_tag = 0;
7126                 tnapi->last_irq_tag = 0;
7127         }
7128         smp_mb();
7129
7130         for (i = 0; i < tp->irq_cnt; i++)
7131                 synchronize_irq(tp->napi[i].irq_vec);
7132
7133         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7134                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7135                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7136         }
7137
7138         /* do the reset */
7139         val = GRC_MISC_CFG_CORECLK_RESET;
7140
7141         if (tg3_flag(tp, PCI_EXPRESS)) {
7142                 /* Force PCIe 1.0a mode */
7143                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7144                     !tg3_flag(tp, 57765_PLUS) &&
7145                     tr32(TG3_PCIE_PHY_TSTCTL) ==
7146                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7147                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7148
7149                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7150                         tw32(GRC_MISC_CFG, (1 << 29));
7151                         val |= (1 << 29);
7152                 }
7153         }
7154
7155         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7156                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7157                 tw32(GRC_VCPU_EXT_CTRL,
7158                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7159         }
7160
7161         /* Manage gphy power for all CPMU absent PCIe devices. */
7162         if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
7163                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7164
7165         tw32(GRC_MISC_CFG, val);
7166
7167         /* restore 5701 hardware bug workaround write method */
7168         tp->write32 = write_op;
7169
7170         /* Unfortunately, we have to delay before the PCI read back.
7171          * Some 575X chips even will not respond to a PCI cfg access
7172          * when the reset command is given to the chip.
7173          *
7174          * How do these hardware designers expect things to work
7175          * properly if the PCI write is posted for a long period
7176          * of time?  It is always necessary to have some method by
7177          * which a register read back can occur to push the write
7178          * out which does the reset.
7179          *
7180          * For most tg3 variants the trick below was working.
7181          * Ho hum...
7182          */
7183         udelay(120);
7184
7185         /* Flush PCI posted writes.  The normal MMIO registers
7186          * are inaccessible at this time so this is the only
7187          * way to make this reliably (actually, this is no longer
7188          * the case, see above).  I tried to use indirect
7189          * register read/write but this upset some 5701 variants.
7190          */
7191         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7192
7193         udelay(120);
7194
7195         if (tg3_flag(tp, PCI_EXPRESS) && tp->pcie_cap) {
7196                 u16 val16;
7197
7198                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7199                         int i;
7200                         u32 cfg_val;
7201
7202                         /* Wait for link training to complete.  */
7203                         for (i = 0; i < 5000; i++)
7204                                 udelay(100);
7205
7206                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7207                         pci_write_config_dword(tp->pdev, 0xc4,
7208                                                cfg_val | (1 << 15));
7209                 }
7210
7211                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7212                 pci_read_config_word(tp->pdev,
7213                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7214                                      &val16);
7215                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7216                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7217                 /*
7218                  * Older PCIe devices only support the 128 byte
7219                  * MPS setting.  Enforce the restriction.
7220                  */
7221                 if (!tg3_flag(tp, CPMU_PRESENT))
7222                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7223                 pci_write_config_word(tp->pdev,
7224                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7225                                       val16);
7226
7227                 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7228
7229                 /* Clear error status */
7230                 pci_write_config_word(tp->pdev,
7231                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7232                                       PCI_EXP_DEVSTA_CED |
7233                                       PCI_EXP_DEVSTA_NFED |
7234                                       PCI_EXP_DEVSTA_FED |
7235                                       PCI_EXP_DEVSTA_URD);
7236         }
7237
7238         tg3_restore_pci_state(tp);
7239
7240         tg3_flag_clear(tp, CHIP_RESETTING);
7241         tg3_flag_clear(tp, ERROR_PROCESSED);
7242
7243         val = 0;
7244         if (tg3_flag(tp, 5780_CLASS))
7245                 val = tr32(MEMARB_MODE);
7246         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7247
7248         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7249                 tg3_stop_fw(tp);
7250                 tw32(0x5000, 0x400);
7251         }
7252
7253         tw32(GRC_MODE, tp->grc_mode);
7254
7255         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7256                 val = tr32(0xc4);
7257
7258                 tw32(0xc4, val | (1 << 15));
7259         }
7260
7261         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7262             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7263                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7264                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7265                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7266                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7267         }
7268
7269         if (tg3_flag(tp, ENABLE_APE))
7270                 tp->mac_mode = MAC_MODE_APE_TX_EN |
7271                                MAC_MODE_APE_RX_EN |
7272                                MAC_MODE_TDE_ENABLE;
7273
7274         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7275                 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
7276                 val = tp->mac_mode;
7277         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7278                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7279                 val = tp->mac_mode;
7280         } else
7281                 val = 0;
7282
7283         tw32_f(MAC_MODE, val);
7284         udelay(40);
7285
7286         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7287
7288         err = tg3_poll_fw(tp);
7289         if (err)
7290                 return err;
7291
7292         tg3_mdio_start(tp);
7293
7294         if (tg3_flag(tp, PCI_EXPRESS) &&
7295             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7296             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7297             !tg3_flag(tp, 57765_PLUS)) {
7298                 val = tr32(0x7c00);
7299
7300                 tw32(0x7c00, val | (1 << 25));
7301         }
7302
7303         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
7304                 val = tr32(TG3_CPMU_CLCK_ORIDE);
7305                 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
7306         }
7307
7308         /* Reprobe ASF enable state.  */
7309         tg3_flag_clear(tp, ENABLE_ASF);
7310         tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
7311         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7312         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7313                 u32 nic_cfg;
7314
7315                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7316                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7317                         tg3_flag_set(tp, ENABLE_ASF);
7318                         tp->last_event_jiffies = jiffies;
7319                         if (tg3_flag(tp, 5750_PLUS))
7320                                 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
7321                 }
7322         }
7323
7324         return 0;
7325 }
7326
7327 /* tp->lock is held. */
7328 static void tg3_stop_fw(struct tg3 *tp)
7329 {
7330         if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7331                 /* Wait for RX cpu to ACK the previous event. */
7332                 tg3_wait_for_event_ack(tp);
7333
7334                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7335
7336                 tg3_generate_fw_event(tp);
7337
7338                 /* Wait for RX cpu to ACK this event. */
7339                 tg3_wait_for_event_ack(tp);
7340         }
7341 }
7342
7343 /* tp->lock is held. */
7344 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7345 {
7346         int err;
7347
7348         tg3_stop_fw(tp);
7349
7350         tg3_write_sig_pre_reset(tp, kind);
7351
7352         tg3_abort_hw(tp, silent);
7353         err = tg3_chip_reset(tp);
7354
7355         __tg3_set_mac_addr(tp, 0);
7356
7357         tg3_write_sig_legacy(tp, kind);
7358         tg3_write_sig_post_reset(tp, kind);
7359
7360         if (err)
7361                 return err;
7362
7363         return 0;
7364 }
7365
7366 #define RX_CPU_SCRATCH_BASE     0x30000
7367 #define RX_CPU_SCRATCH_SIZE     0x04000
7368 #define TX_CPU_SCRATCH_BASE     0x34000
7369 #define TX_CPU_SCRATCH_SIZE     0x04000
7370
7371 /* tp->lock is held. */
7372 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7373 {
7374         int i;
7375
7376         BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
7377
7378         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7379                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7380
7381                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7382                 return 0;
7383         }
7384         if (offset == RX_CPU_BASE) {
7385                 for (i = 0; i < 10000; i++) {
7386                         tw32(offset + CPU_STATE, 0xffffffff);
7387                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7388                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7389                                 break;
7390                 }
7391
7392                 tw32(offset + CPU_STATE, 0xffffffff);
7393                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7394                 udelay(10);
7395         } else {
7396                 for (i = 0; i < 10000; i++) {
7397                         tw32(offset + CPU_STATE, 0xffffffff);
7398                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7399                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7400                                 break;
7401                 }
7402         }
7403
7404         if (i >= 10000) {
7405                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7406                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7407                 return -ENODEV;
7408         }
7409
7410         /* Clear firmware's nvram arbitration. */
7411         if (tg3_flag(tp, NVRAM))
7412                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7413         return 0;
7414 }
7415
7416 struct fw_info {
7417         unsigned int fw_base;
7418         unsigned int fw_len;
7419         const __be32 *fw_data;
7420 };
7421
7422 /* tp->lock is held. */
7423 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7424                                  int cpu_scratch_size, struct fw_info *info)
7425 {
7426         int err, lock_err, i;
7427         void (*write_op)(struct tg3 *, u32, u32);
7428
7429         if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
7430                 netdev_err(tp->dev,
7431                            "%s: Trying to load TX cpu firmware which is 5705\n",
7432                            __func__);
7433                 return -EINVAL;
7434         }
7435
7436         if (tg3_flag(tp, 5705_PLUS))
7437                 write_op = tg3_write_mem;
7438         else
7439                 write_op = tg3_write_indirect_reg32;
7440
7441         /* It is possible that bootcode is still loading at this point.
7442          * Get the nvram lock first before halting the cpu.
7443          */
7444         lock_err = tg3_nvram_lock(tp);
7445         err = tg3_halt_cpu(tp, cpu_base);
7446         if (!lock_err)
7447                 tg3_nvram_unlock(tp);
7448         if (err)
7449                 goto out;
7450
7451         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7452                 write_op(tp, cpu_scratch_base + i, 0);
7453         tw32(cpu_base + CPU_STATE, 0xffffffff);
7454         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7455         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7456                 write_op(tp, (cpu_scratch_base +
7457                               (info->fw_base & 0xffff) +
7458                               (i * sizeof(u32))),
7459                               be32_to_cpu(info->fw_data[i]));
7460
7461         err = 0;
7462
7463 out:
7464         return err;
7465 }
7466
7467 /* tp->lock is held. */
7468 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7469 {
7470         struct fw_info info;
7471         const __be32 *fw_data;
7472         int err, i;
7473
7474         fw_data = (void *)tp->fw->data;
7475
7476         /* Firmware blob starts with version numbers, followed by
7477            start address and length. We are setting complete length.
7478            length = end_address_of_bss - start_address_of_text.
7479            Remainder is the blob to be loaded contiguously
7480            from start address. */
7481
7482         info.fw_base = be32_to_cpu(fw_data[1]);
7483         info.fw_len = tp->fw->size - 12;
7484         info.fw_data = &fw_data[3];
7485
7486         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7487                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7488                                     &info);
7489         if (err)
7490                 return err;
7491
7492         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7493                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7494                                     &info);
7495         if (err)
7496                 return err;
7497
7498         /* Now startup only the RX cpu. */
7499         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7500         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7501
7502         for (i = 0; i < 5; i++) {
7503                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7504                         break;
7505                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7506                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7507                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7508                 udelay(1000);
7509         }
7510         if (i >= 5) {
7511                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7512                            "should be %08x\n", __func__,
7513                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7514                 return -ENODEV;
7515         }
7516         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7517         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7518
7519         return 0;
7520 }
7521
7522 /* tp->lock is held. */
7523 static int tg3_load_tso_firmware(struct tg3 *tp)
7524 {
7525         struct fw_info info;
7526         const __be32 *fw_data;
7527         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7528         int err, i;
7529
7530         if (tg3_flag(tp, HW_TSO_1) ||
7531             tg3_flag(tp, HW_TSO_2) ||
7532             tg3_flag(tp, HW_TSO_3))
7533                 return 0;
7534
7535         fw_data = (void *)tp->fw->data;
7536
7537         /* Firmware blob starts with version numbers, followed by
7538            start address and length. We are setting complete length.
7539            length = end_address_of_bss - start_address_of_text.
7540            Remainder is the blob to be loaded contiguously
7541            from start address. */
7542
7543         info.fw_base = be32_to_cpu(fw_data[1]);
7544         cpu_scratch_size = tp->fw_len;
7545         info.fw_len = tp->fw->size - 12;
7546         info.fw_data = &fw_data[3];
7547
7548         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7549                 cpu_base = RX_CPU_BASE;
7550                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7551         } else {
7552                 cpu_base = TX_CPU_BASE;
7553                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7554                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7555         }
7556
7557         err = tg3_load_firmware_cpu(tp, cpu_base,
7558                                     cpu_scratch_base, cpu_scratch_size,
7559                                     &info);
7560         if (err)
7561                 return err;
7562
7563         /* Now startup the cpu. */
7564         tw32(cpu_base + CPU_STATE, 0xffffffff);
7565         tw32_f(cpu_base + CPU_PC, info.fw_base);
7566
7567         for (i = 0; i < 5; i++) {
7568                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7569                         break;
7570                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7571                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7572                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7573                 udelay(1000);
7574         }
7575         if (i >= 5) {
7576                 netdev_err(tp->dev,
7577                            "%s fails to set CPU PC, is %08x should be %08x\n",
7578                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7579                 return -ENODEV;
7580         }
7581         tw32(cpu_base + CPU_STATE, 0xffffffff);
7582         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7583         return 0;
7584 }
7585
7586
7587 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7588 {
7589         struct tg3 *tp = netdev_priv(dev);
7590         struct sockaddr *addr = p;
7591         int err = 0, skip_mac_1 = 0;
7592
7593         if (!is_valid_ether_addr(addr->sa_data))
7594                 return -EINVAL;
7595
7596         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7597
7598         if (!netif_running(dev))
7599                 return 0;
7600
7601         if (tg3_flag(tp, ENABLE_ASF)) {
7602                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7603
7604                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7605                 addr0_low = tr32(MAC_ADDR_0_LOW);
7606                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7607                 addr1_low = tr32(MAC_ADDR_1_LOW);
7608
7609                 /* Skip MAC addr 1 if ASF is using it. */
7610                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7611                     !(addr1_high == 0 && addr1_low == 0))
7612                         skip_mac_1 = 1;
7613         }
7614         spin_lock_bh(&tp->lock);
7615         __tg3_set_mac_addr(tp, skip_mac_1);
7616         spin_unlock_bh(&tp->lock);
7617
7618         return err;
7619 }
7620
7621 /* tp->lock is held. */
7622 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7623                            dma_addr_t mapping, u32 maxlen_flags,
7624                            u32 nic_addr)
7625 {
7626         tg3_write_mem(tp,
7627                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7628                       ((u64) mapping >> 32));
7629         tg3_write_mem(tp,
7630                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7631                       ((u64) mapping & 0xffffffff));
7632         tg3_write_mem(tp,
7633                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7634                        maxlen_flags);
7635
7636         if (!tg3_flag(tp, 5705_PLUS))
7637                 tg3_write_mem(tp,
7638                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7639                               nic_addr);
7640 }
7641
7642 static void __tg3_set_rx_mode(struct net_device *);
7643 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7644 {
7645         int i;
7646
7647         if (!tg3_flag(tp, ENABLE_TSS)) {
7648                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7649                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7650                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7651         } else {
7652                 tw32(HOSTCC_TXCOL_TICKS, 0);
7653                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7654                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7655         }
7656
7657         if (!tg3_flag(tp, ENABLE_RSS)) {
7658                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7659                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7660                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7661         } else {
7662                 tw32(HOSTCC_RXCOL_TICKS, 0);
7663                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7664                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7665         }
7666
7667         if (!tg3_flag(tp, 5705_PLUS)) {
7668                 u32 val = ec->stats_block_coalesce_usecs;
7669
7670                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7671                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7672
7673                 if (!netif_carrier_ok(tp->dev))
7674                         val = 0;
7675
7676                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7677         }
7678
7679         for (i = 0; i < tp->irq_cnt - 1; i++) {
7680                 u32 reg;
7681
7682                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7683                 tw32(reg, ec->rx_coalesce_usecs);
7684                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7685                 tw32(reg, ec->rx_max_coalesced_frames);
7686                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7687                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7688
7689                 if (tg3_flag(tp, ENABLE_TSS)) {
7690                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7691                         tw32(reg, ec->tx_coalesce_usecs);
7692                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7693                         tw32(reg, ec->tx_max_coalesced_frames);
7694                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7695                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7696                 }
7697         }
7698
7699         for (; i < tp->irq_max - 1; i++) {
7700                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7701                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7702                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7703
7704                 if (tg3_flag(tp, ENABLE_TSS)) {
7705                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7706                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7707                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7708                 }
7709         }
7710 }
7711
7712 /* tp->lock is held. */
7713 static void tg3_rings_reset(struct tg3 *tp)
7714 {
7715         int i;
7716         u32 stblk, txrcb, rxrcb, limit;
7717         struct tg3_napi *tnapi = &tp->napi[0];
7718
7719         /* Disable all transmit rings but the first. */
7720         if (!tg3_flag(tp, 5705_PLUS))
7721                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7722         else if (tg3_flag(tp, 5717_PLUS))
7723                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7724         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7725                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7726         else
7727                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7728
7729         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7730              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7731                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7732                               BDINFO_FLAGS_DISABLED);
7733
7734
7735         /* Disable all receive return rings but the first. */
7736         if (tg3_flag(tp, 5717_PLUS))
7737                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7738         else if (!tg3_flag(tp, 5705_PLUS))
7739                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7740         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7741                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7742                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7743         else
7744                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7745
7746         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7747              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7748                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7749                               BDINFO_FLAGS_DISABLED);
7750
7751         /* Disable interrupts */
7752         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7753
7754         /* Zero mailbox registers. */
7755         if (tg3_flag(tp, SUPPORT_MSIX)) {
7756                 for (i = 1; i < tp->irq_max; i++) {
7757                         tp->napi[i].tx_prod = 0;
7758                         tp->napi[i].tx_cons = 0;
7759                         if (tg3_flag(tp, ENABLE_TSS))
7760                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7761                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7762                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7763                 }
7764                 if (!tg3_flag(tp, ENABLE_TSS))
7765                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7766         } else {
7767                 tp->napi[0].tx_prod = 0;
7768                 tp->napi[0].tx_cons = 0;
7769                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7770                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7771         }
7772
7773         /* Make sure the NIC-based send BD rings are disabled. */
7774         if (!tg3_flag(tp, 5705_PLUS)) {
7775                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7776                 for (i = 0; i < 16; i++)
7777                         tw32_tx_mbox(mbox + i * 8, 0);
7778         }
7779
7780         txrcb = NIC_SRAM_SEND_RCB;
7781         rxrcb = NIC_SRAM_RCV_RET_RCB;
7782
7783         /* Clear status block in ram. */
7784         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7785
7786         /* Set status block DMA address */
7787         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7788              ((u64) tnapi->status_mapping >> 32));
7789         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7790              ((u64) tnapi->status_mapping & 0xffffffff));
7791
7792         if (tnapi->tx_ring) {
7793                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7794                                (TG3_TX_RING_SIZE <<
7795                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7796                                NIC_SRAM_TX_BUFFER_DESC);
7797                 txrcb += TG3_BDINFO_SIZE;
7798         }
7799
7800         if (tnapi->rx_rcb) {
7801                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7802                                (tp->rx_ret_ring_mask + 1) <<
7803                                 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7804                 rxrcb += TG3_BDINFO_SIZE;
7805         }
7806
7807         stblk = HOSTCC_STATBLCK_RING1;
7808
7809         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7810                 u64 mapping = (u64)tnapi->status_mapping;
7811                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7812                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7813
7814                 /* Clear status block in ram. */
7815                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7816
7817                 if (tnapi->tx_ring) {
7818                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7819                                        (TG3_TX_RING_SIZE <<
7820                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7821                                        NIC_SRAM_TX_BUFFER_DESC);
7822                         txrcb += TG3_BDINFO_SIZE;
7823                 }
7824
7825                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7826                                ((tp->rx_ret_ring_mask + 1) <<
7827                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7828
7829                 stblk += 8;
7830                 rxrcb += TG3_BDINFO_SIZE;
7831         }
7832 }
7833
7834 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
7835 {
7836         u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
7837
7838         if (!tg3_flag(tp, 5750_PLUS) ||
7839             tg3_flag(tp, 5780_CLASS) ||
7840             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
7841             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7842                 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
7843         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7844                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
7845                 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
7846         else
7847                 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
7848
7849         nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
7850         host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
7851
7852         val = min(nic_rep_thresh, host_rep_thresh);
7853         tw32(RCVBDI_STD_THRESH, val);
7854
7855         if (tg3_flag(tp, 57765_PLUS))
7856                 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
7857
7858         if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
7859                 return;
7860
7861         if (!tg3_flag(tp, 5705_PLUS))
7862                 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
7863         else
7864                 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717;
7865
7866         host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
7867
7868         val = min(bdcache_maxcnt / 2, host_rep_thresh);
7869         tw32(RCVBDI_JUMBO_THRESH, val);
7870
7871         if (tg3_flag(tp, 57765_PLUS))
7872                 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
7873 }
7874
7875 /* tp->lock is held. */
7876 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7877 {
7878         u32 val, rdmac_mode;
7879         int i, err, limit;
7880         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7881
7882         tg3_disable_ints(tp);
7883
7884         tg3_stop_fw(tp);
7885
7886         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7887
7888         if (tg3_flag(tp, INIT_COMPLETE))
7889                 tg3_abort_hw(tp, 1);
7890
7891         /* Enable MAC control of LPI */
7892         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7893                 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7894                        TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7895                        TG3_CPMU_EEE_LNKIDL_UART_IDL);
7896
7897                 tw32_f(TG3_CPMU_EEE_CTRL,
7898                        TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7899
7900                 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7901                       TG3_CPMU_EEEMD_LPI_IN_TX |
7902                       TG3_CPMU_EEEMD_LPI_IN_RX |
7903                       TG3_CPMU_EEEMD_EEE_ENABLE;
7904
7905                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7906                         val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
7907
7908                 if (tg3_flag(tp, ENABLE_APE))
7909                         val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
7910
7911                 tw32_f(TG3_CPMU_EEE_MODE, val);
7912
7913                 tw32_f(TG3_CPMU_EEE_DBTMR1,
7914                        TG3_CPMU_DBTMR1_PCIEXIT_2047US |
7915                        TG3_CPMU_DBTMR1_LNKIDLE_2047US);
7916
7917                 tw32_f(TG3_CPMU_EEE_DBTMR2,
7918                        TG3_CPMU_DBTMR2_APE_TX_2047US |
7919                        TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
7920         }
7921
7922         if (reset_phy)
7923                 tg3_phy_reset(tp);
7924
7925         err = tg3_chip_reset(tp);
7926         if (err)
7927                 return err;
7928
7929         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7930
7931         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7932                 val = tr32(TG3_CPMU_CTRL);
7933                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7934                 tw32(TG3_CPMU_CTRL, val);
7935
7936                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7937                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7938                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7939                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7940
7941                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7942                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7943                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7944                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7945
7946                 val = tr32(TG3_CPMU_HST_ACC);
7947                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7948                 val |= CPMU_HST_ACC_MACCLK_6_25;
7949                 tw32(TG3_CPMU_HST_ACC, val);
7950         }
7951
7952         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7953                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7954                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7955                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7956                 tw32(PCIE_PWR_MGMT_THRESH, val);
7957
7958                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7959                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7960
7961                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7962
7963                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7964                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7965         }
7966
7967         if (tg3_flag(tp, L1PLLPD_EN)) {
7968                 u32 grc_mode = tr32(GRC_MODE);
7969
7970                 /* Access the lower 1K of PL PCIE block registers. */
7971                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7972                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7973
7974                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7975                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7976                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7977
7978                 tw32(GRC_MODE, grc_mode);
7979         }
7980
7981         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7982                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7983                         u32 grc_mode = tr32(GRC_MODE);
7984
7985                         /* Access the lower 1K of PL PCIE block registers. */
7986                         val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7987                         tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7988
7989                         val = tr32(TG3_PCIE_TLDLPL_PORT +
7990                                    TG3_PCIE_PL_LO_PHYCTL5);
7991                         tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7992                              val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7993
7994                         tw32(GRC_MODE, grc_mode);
7995                 }
7996
7997                 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
7998                         u32 grc_mode = tr32(GRC_MODE);
7999
8000                         /* Access the lower 1K of DL PCIE block registers. */
8001                         val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8002                         tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
8003
8004                         val = tr32(TG3_PCIE_TLDLPL_PORT +
8005                                    TG3_PCIE_DL_LO_FTSMAX);
8006                         val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
8007                         tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
8008                              val | TG3_PCIE_DL_LO_FTSMAX_VAL);
8009
8010                         tw32(GRC_MODE, grc_mode);
8011                 }
8012
8013                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8014                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8015                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8016                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8017         }
8018
8019         /* This works around an issue with Athlon chipsets on
8020          * B3 tigon3 silicon.  This bit has no effect on any
8021          * other revision.  But do not set this on PCI Express
8022          * chips and don't even touch the clocks if the CPMU is present.
8023          */
8024         if (!tg3_flag(tp, CPMU_PRESENT)) {
8025                 if (!tg3_flag(tp, PCI_EXPRESS))
8026                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8027                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8028         }
8029
8030         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8031             tg3_flag(tp, PCIX_MODE)) {
8032                 val = tr32(TG3PCI_PCISTATE);
8033                 val |= PCISTATE_RETRY_SAME_DMA;
8034                 tw32(TG3PCI_PCISTATE, val);
8035         }
8036
8037         if (tg3_flag(tp, ENABLE_APE)) {
8038                 /* Allow reads and writes to the
8039                  * APE register and memory space.
8040                  */
8041                 val = tr32(TG3PCI_PCISTATE);
8042                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8043                        PCISTATE_ALLOW_APE_SHMEM_WR |
8044                        PCISTATE_ALLOW_APE_PSPACE_WR;
8045                 tw32(TG3PCI_PCISTATE, val);
8046         }
8047
8048         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8049                 /* Enable some hw fixes.  */
8050                 val = tr32(TG3PCI_MSI_DATA);
8051                 val |= (1 << 26) | (1 << 28) | (1 << 29);
8052                 tw32(TG3PCI_MSI_DATA, val);
8053         }
8054
8055         /* Descriptor ring init may make accesses to the
8056          * NIC SRAM area to setup the TX descriptors, so we
8057          * can only do this after the hardware has been
8058          * successfully reset.
8059          */
8060         err = tg3_init_rings(tp);
8061         if (err)
8062                 return err;
8063
8064         if (tg3_flag(tp, 57765_PLUS)) {
8065                 val = tr32(TG3PCI_DMA_RW_CTRL) &
8066                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8067                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8068                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8069                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8070                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8071                         val |= DMA_RWCTRL_TAGGED_STAT_WA;
8072                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8073         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8074                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
8075                 /* This value is determined during the probe time DMA
8076                  * engine test, tg3_test_dma.
8077                  */
8078                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8079         }
8080
8081         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8082                           GRC_MODE_4X_NIC_SEND_RINGS |
8083                           GRC_MODE_NO_TX_PHDR_CSUM |
8084                           GRC_MODE_NO_RX_PHDR_CSUM);
8085         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
8086
8087         /* Pseudo-header checksum is done by hardware logic and not
8088          * the offload processers, so make the chip do the pseudo-
8089          * header checksums on receive.  For transmit it is more
8090          * convenient to do the pseudo-header checksum in software
8091          * as Linux does that on transmit for us in all cases.
8092          */
8093         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8094
8095         tw32(GRC_MODE,
8096              tp->grc_mode |
8097              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8098
8099         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
8100         val = tr32(GRC_MISC_CFG);
8101         val &= ~0xff;
8102         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8103         tw32(GRC_MISC_CFG, val);
8104
8105         /* Initialize MBUF/DESC pool. */
8106         if (tg3_flag(tp, 5750_PLUS)) {
8107                 /* Do nothing.  */
8108         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8109                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8110                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8111                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8112                 else
8113                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8114                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8115                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8116         } else if (tg3_flag(tp, TSO_CAPABLE)) {
8117                 int fw_len;
8118
8119                 fw_len = tp->fw_len;
8120                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8121                 tw32(BUFMGR_MB_POOL_ADDR,
8122                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8123                 tw32(BUFMGR_MB_POOL_SIZE,
8124                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8125         }
8126
8127         if (tp->dev->mtu <= ETH_DATA_LEN) {
8128                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8129                      tp->bufmgr_config.mbuf_read_dma_low_water);
8130                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8131                      tp->bufmgr_config.mbuf_mac_rx_low_water);
8132                 tw32(BUFMGR_MB_HIGH_WATER,
8133                      tp->bufmgr_config.mbuf_high_water);
8134         } else {
8135                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8136                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8137                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8138                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8139                 tw32(BUFMGR_MB_HIGH_WATER,
8140                      tp->bufmgr_config.mbuf_high_water_jumbo);
8141         }
8142         tw32(BUFMGR_DMA_LOW_WATER,
8143              tp->bufmgr_config.dma_low_water);
8144         tw32(BUFMGR_DMA_HIGH_WATER,
8145              tp->bufmgr_config.dma_high_water);
8146
8147         val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8148         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8149                 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8150         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8151             tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8152             tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
8153                 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
8154         tw32(BUFMGR_MODE, val);
8155         for (i = 0; i < 2000; i++) {
8156                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8157                         break;
8158                 udelay(10);
8159         }
8160         if (i >= 2000) {
8161                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8162                 return -ENODEV;
8163         }
8164
8165         if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8166                 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8167
8168         tg3_setup_rxbd_thresholds(tp);
8169
8170         /* Initialize TG3_BDINFO's at:
8171          *  RCVDBDI_STD_BD:     standard eth size rx ring
8172          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
8173          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
8174          *
8175          * like so:
8176          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
8177          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
8178          *                              ring attribute flags
8179          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
8180          *
8181          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8182          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8183          *
8184          * The size of each ring is fixed in the firmware, but the location is
8185          * configurable.
8186          */
8187         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8188              ((u64) tpr->rx_std_mapping >> 32));
8189         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8190              ((u64) tpr->rx_std_mapping & 0xffffffff));
8191         if (!tg3_flag(tp, 5717_PLUS))
8192                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8193                      NIC_SRAM_RX_BUFFER_DESC);
8194
8195         /* Disable the mini ring */
8196         if (!tg3_flag(tp, 5705_PLUS))
8197                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8198                      BDINFO_FLAGS_DISABLED);
8199
8200         /* Program the jumbo buffer descriptor ring control
8201          * blocks on those devices that have them.
8202          */
8203         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8204             (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
8205
8206                 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
8207                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8208                              ((u64) tpr->rx_jmb_mapping >> 32));
8209                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8210                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8211                         val = TG3_RX_JMB_RING_SIZE(tp) <<
8212                               BDINFO_FLAGS_MAXLEN_SHIFT;
8213                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8214                              val | BDINFO_FLAGS_USE_EXT_RECV);
8215                         if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
8216                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8217                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8218                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8219                 } else {
8220                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8221                              BDINFO_FLAGS_DISABLED);
8222                 }
8223
8224                 if (tg3_flag(tp, 57765_PLUS)) {
8225                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8226                                 val = TG3_RX_STD_MAX_SIZE_5700;
8227                         else
8228                                 val = TG3_RX_STD_MAX_SIZE_5717;
8229                         val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8230                         val |= (TG3_RX_STD_DMA_SZ << 2);
8231                 } else
8232                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8233         } else
8234                 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8235
8236         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8237
8238         tpr->rx_std_prod_idx = tp->rx_pending;
8239         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8240
8241         tpr->rx_jmb_prod_idx =
8242                 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
8243         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8244
8245         tg3_rings_reset(tp);
8246
8247         /* Initialize MAC address and backoff seed. */
8248         __tg3_set_mac_addr(tp, 0);
8249
8250         /* MTU + ethernet header + FCS + optional VLAN tag */
8251         tw32(MAC_RX_MTU_SIZE,
8252              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8253
8254         /* The slot time is changed by tg3_setup_phy if we
8255          * run at gigabit with half duplex.
8256          */
8257         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8258               (6 << TX_LENGTHS_IPG_SHIFT) |
8259               (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8260
8261         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8262                 val |= tr32(MAC_TX_LENGTHS) &
8263                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
8264                         TX_LENGTHS_CNT_DWN_VAL_MSK);
8265
8266         tw32(MAC_TX_LENGTHS, val);
8267
8268         /* Receive rules. */
8269         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8270         tw32(RCVLPC_CONFIG, 0x0181);
8271
8272         /* Calculate RDMAC_MODE setting early, we need it to determine
8273          * the RCVLPC_STATE_ENABLE mask.
8274          */
8275         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8276                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8277                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8278                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8279                       RDMAC_MODE_LNGREAD_ENAB);
8280
8281         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8282                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8283
8284         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8285             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8286             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8287                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8288                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8289                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8290
8291         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8292             tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8293                 if (tg3_flag(tp, TSO_CAPABLE) &&
8294                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8295                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8296                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8297                            !tg3_flag(tp, IS_5788)) {
8298                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8299                 }
8300         }
8301
8302         if (tg3_flag(tp, PCI_EXPRESS))
8303                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8304
8305         if (tg3_flag(tp, HW_TSO_1) ||
8306             tg3_flag(tp, HW_TSO_2) ||
8307             tg3_flag(tp, HW_TSO_3))
8308                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8309
8310         if (tg3_flag(tp, 57765_PLUS) ||
8311             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8312             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8313                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8314
8315         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8316                 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8317
8318         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8319             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8320             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8321             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8322             tg3_flag(tp, 57765_PLUS)) {
8323                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8324                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8325                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8326                         val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8327                                  TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8328                                  TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8329                         val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8330                                TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8331                                TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8332                 }
8333                 tw32(TG3_RDMA_RSRVCTRL_REG,
8334                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8335         }
8336
8337         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8338             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8339                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8340                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8341                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8342                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8343         }
8344
8345         /* Receive/send statistics. */
8346         if (tg3_flag(tp, 5750_PLUS)) {
8347                 val = tr32(RCVLPC_STATS_ENABLE);
8348                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8349                 tw32(RCVLPC_STATS_ENABLE, val);
8350         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8351                    tg3_flag(tp, TSO_CAPABLE)) {
8352                 val = tr32(RCVLPC_STATS_ENABLE);
8353                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8354                 tw32(RCVLPC_STATS_ENABLE, val);
8355         } else {
8356                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8357         }
8358         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8359         tw32(SNDDATAI_STATSENAB, 0xffffff);
8360         tw32(SNDDATAI_STATSCTRL,
8361              (SNDDATAI_SCTRL_ENABLE |
8362               SNDDATAI_SCTRL_FASTUPD));
8363
8364         /* Setup host coalescing engine. */
8365         tw32(HOSTCC_MODE, 0);
8366         for (i = 0; i < 2000; i++) {
8367                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8368                         break;
8369                 udelay(10);
8370         }
8371
8372         __tg3_set_coalesce(tp, &tp->coal);
8373
8374         if (!tg3_flag(tp, 5705_PLUS)) {
8375                 /* Status/statistics block address.  See tg3_timer,
8376                  * the tg3_periodic_fetch_stats call there, and
8377                  * tg3_get_stats to see how this works for 5705/5750 chips.
8378                  */
8379                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8380                      ((u64) tp->stats_mapping >> 32));
8381                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8382                      ((u64) tp->stats_mapping & 0xffffffff));
8383                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8384
8385                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8386
8387                 /* Clear statistics and status block memory areas */
8388                 for (i = NIC_SRAM_STATS_BLK;
8389                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8390                      i += sizeof(u32)) {
8391                         tg3_write_mem(tp, i, 0);
8392                         udelay(40);
8393                 }
8394         }
8395
8396         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8397
8398         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8399         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8400         if (!tg3_flag(tp, 5705_PLUS))
8401                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8402
8403         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8404                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8405                 /* reset to prevent losing 1st rx packet intermittently */
8406                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8407                 udelay(10);
8408         }
8409
8410         if (tg3_flag(tp, ENABLE_APE))
8411                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8412         else
8413                 tp->mac_mode = 0;
8414         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8415                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8416         if (!tg3_flag(tp, 5705_PLUS) &&
8417             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8418             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8419                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8420         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8421         udelay(40);
8422
8423         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8424          * If TG3_FLAG_IS_NIC is zero, we should read the
8425          * register to preserve the GPIO settings for LOMs. The GPIOs,
8426          * whether used as inputs or outputs, are set by boot code after
8427          * reset.
8428          */
8429         if (!tg3_flag(tp, IS_NIC)) {
8430                 u32 gpio_mask;
8431
8432                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8433                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8434                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8435
8436                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8437                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8438                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8439
8440                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8441                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8442
8443                 tp->grc_local_ctrl &= ~gpio_mask;
8444                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8445
8446                 /* GPIO1 must be driven high for eeprom write protect */
8447                 if (tg3_flag(tp, EEPROM_WRITE_PROT))
8448                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8449                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8450         }
8451         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8452         udelay(100);
8453
8454         if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) {
8455                 val = tr32(MSGINT_MODE);
8456                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8457                 tw32(MSGINT_MODE, val);
8458         }
8459
8460         if (!tg3_flag(tp, 5705_PLUS)) {
8461                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8462                 udelay(40);
8463         }
8464
8465         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8466                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8467                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8468                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8469                WDMAC_MODE_LNGREAD_ENAB);
8470
8471         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8472             tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8473                 if (tg3_flag(tp, TSO_CAPABLE) &&
8474                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8475                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8476                         /* nothing */
8477                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8478                            !tg3_flag(tp, IS_5788)) {
8479                         val |= WDMAC_MODE_RX_ACCEL;
8480                 }
8481         }
8482
8483         /* Enable host coalescing bug fix */
8484         if (tg3_flag(tp, 5755_PLUS))
8485                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8486
8487         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8488                 val |= WDMAC_MODE_BURST_ALL_DATA;
8489
8490         tw32_f(WDMAC_MODE, val);
8491         udelay(40);
8492
8493         if (tg3_flag(tp, PCIX_MODE)) {
8494                 u16 pcix_cmd;
8495
8496                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8497                                      &pcix_cmd);
8498                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8499                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8500                         pcix_cmd |= PCI_X_CMD_READ_2K;
8501                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8502                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8503                         pcix_cmd |= PCI_X_CMD_READ_2K;
8504                 }
8505                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8506                                       pcix_cmd);
8507         }
8508
8509         tw32_f(RDMAC_MODE, rdmac_mode);
8510         udelay(40);
8511
8512         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8513         if (!tg3_flag(tp, 5705_PLUS))
8514                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8515
8516         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8517                 tw32(SNDDATAC_MODE,
8518                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8519         else
8520                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8521
8522         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8523         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8524         val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8525         if (tg3_flag(tp, LRG_PROD_RING_CAP))
8526                 val |= RCVDBDI_MODE_LRG_RING_SZ;
8527         tw32(RCVDBDI_MODE, val);
8528         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8529         if (tg3_flag(tp, HW_TSO_1) ||
8530             tg3_flag(tp, HW_TSO_2) ||
8531             tg3_flag(tp, HW_TSO_3))
8532                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8533         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8534         if (tg3_flag(tp, ENABLE_TSS))
8535                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8536         tw32(SNDBDI_MODE, val);
8537         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8538
8539         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8540                 err = tg3_load_5701_a0_firmware_fix(tp);
8541                 if (err)
8542                         return err;
8543         }
8544
8545         if (tg3_flag(tp, TSO_CAPABLE)) {
8546                 err = tg3_load_tso_firmware(tp);
8547                 if (err)
8548                         return err;
8549         }
8550
8551         tp->tx_mode = TX_MODE_ENABLE;
8552
8553         if (tg3_flag(tp, 5755_PLUS) ||
8554             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8555                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8556
8557         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8558                 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
8559                 tp->tx_mode &= ~val;
8560                 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
8561         }
8562
8563         tw32_f(MAC_TX_MODE, tp->tx_mode);
8564         udelay(100);
8565
8566         if (tg3_flag(tp, ENABLE_RSS)) {
8567                 u32 reg = MAC_RSS_INDIR_TBL_0;
8568                 u8 *ent = (u8 *)&val;
8569
8570                 /* Setup the indirection table */
8571                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8572                         int idx = i % sizeof(val);
8573
8574                         ent[idx] = i % (tp->irq_cnt - 1);
8575                         if (idx == sizeof(val) - 1) {
8576                                 tw32(reg, val);
8577                                 reg += 4;
8578                         }
8579                 }
8580
8581                 /* Setup the "secret" hash key. */
8582                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8583                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8584                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8585                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8586                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8587                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8588                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8589                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8590                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8591                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8592         }
8593
8594         tp->rx_mode = RX_MODE_ENABLE;
8595         if (tg3_flag(tp, 5755_PLUS))
8596                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8597
8598         if (tg3_flag(tp, ENABLE_RSS))
8599                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8600                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8601                                RX_MODE_RSS_IPV6_HASH_EN |
8602                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8603                                RX_MODE_RSS_IPV4_HASH_EN |
8604                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8605
8606         tw32_f(MAC_RX_MODE, tp->rx_mode);
8607         udelay(10);
8608
8609         tw32(MAC_LED_CTRL, tp->led_ctrl);
8610
8611         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8612         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8613                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8614                 udelay(10);
8615         }
8616         tw32_f(MAC_RX_MODE, tp->rx_mode);
8617         udelay(10);
8618
8619         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8620                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8621                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8622                         /* Set drive transmission level to 1.2V  */
8623                         /* only if the signal pre-emphasis bit is not set  */
8624                         val = tr32(MAC_SERDES_CFG);
8625                         val &= 0xfffff000;
8626                         val |= 0x880;
8627                         tw32(MAC_SERDES_CFG, val);
8628                 }
8629                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8630                         tw32(MAC_SERDES_CFG, 0x616000);
8631         }
8632
8633         /* Prevent chip from dropping frames when flow control
8634          * is enabled.
8635          */
8636         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8637                 val = 1;
8638         else
8639                 val = 2;
8640         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8641
8642         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8643             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8644                 /* Use hardware link auto-negotiation */
8645                 tg3_flag_set(tp, HW_AUTONEG);
8646         }
8647
8648         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8649             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8650                 u32 tmp;
8651
8652                 tmp = tr32(SERDES_RX_CTRL);
8653                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8654                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8655                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8656                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8657         }
8658
8659         if (!tg3_flag(tp, USE_PHYLIB)) {
8660                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8661                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8662                         tp->link_config.speed = tp->link_config.orig_speed;
8663                         tp->link_config.duplex = tp->link_config.orig_duplex;
8664                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8665                 }
8666
8667                 err = tg3_setup_phy(tp, 0);
8668                 if (err)
8669                         return err;
8670
8671                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8672                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8673                         u32 tmp;
8674
8675                         /* Clear CRC stats. */
8676                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8677                                 tg3_writephy(tp, MII_TG3_TEST1,
8678                                              tmp | MII_TG3_TEST1_CRC_EN);
8679                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8680                         }
8681                 }
8682         }
8683
8684         __tg3_set_rx_mode(tp->dev);
8685
8686         /* Initialize receive rules. */
8687         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8688         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8689         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8690         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8691
8692         if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
8693                 limit = 8;
8694         else
8695                 limit = 16;
8696         if (tg3_flag(tp, ENABLE_ASF))
8697                 limit -= 4;
8698         switch (limit) {
8699         case 16:
8700                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8701         case 15:
8702                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8703         case 14:
8704                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8705         case 13:
8706                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8707         case 12:
8708                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8709         case 11:
8710                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8711         case 10:
8712                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8713         case 9:
8714                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8715         case 8:
8716                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8717         case 7:
8718                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8719         case 6:
8720                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8721         case 5:
8722                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8723         case 4:
8724                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8725         case 3:
8726                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8727         case 2:
8728         case 1:
8729
8730         default:
8731                 break;
8732         }
8733
8734         if (tg3_flag(tp, ENABLE_APE))
8735                 /* Write our heartbeat update interval to APE. */
8736                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8737                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8738
8739         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8740
8741         return 0;
8742 }
8743
8744 /* Called at device open time to get the chip ready for
8745  * packet processing.  Invoked with tp->lock held.
8746  */
8747 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8748 {
8749         tg3_switch_clocks(tp);
8750
8751         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8752
8753         return tg3_reset_hw(tp, reset_phy);
8754 }
8755
8756 #define TG3_STAT_ADD32(PSTAT, REG) \
8757 do {    u32 __val = tr32(REG); \
8758         (PSTAT)->low += __val; \
8759         if ((PSTAT)->low < __val) \
8760                 (PSTAT)->high += 1; \
8761 } while (0)
8762
8763 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8764 {
8765         struct tg3_hw_stats *sp = tp->hw_stats;
8766
8767         if (!netif_carrier_ok(tp->dev))
8768                 return;
8769
8770         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8771         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8772         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8773         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8774         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8775         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8776         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8777         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8778         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8779         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8780         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8781         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8782         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8783
8784         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8785         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8786         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8787         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8788         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8789         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8790         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8791         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8792         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8793         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8794         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8795         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8796         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8797         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8798
8799         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8800         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
8801                 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8802         } else {
8803                 u32 val = tr32(HOSTCC_FLOW_ATTN);
8804                 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
8805                 if (val) {
8806                         tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
8807                         sp->rx_discards.low += val;
8808                         if (sp->rx_discards.low < val)
8809                                 sp->rx_discards.high += 1;
8810                 }
8811                 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
8812         }
8813         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8814 }
8815
8816 static void tg3_timer(unsigned long __opaque)
8817 {
8818         struct tg3 *tp = (struct tg3 *) __opaque;
8819
8820         if (tp->irq_sync)
8821                 goto restart_timer;
8822
8823         spin_lock(&tp->lock);
8824
8825         if (!tg3_flag(tp, TAGGED_STATUS)) {
8826                 /* All of this garbage is because when using non-tagged
8827                  * IRQ status the mailbox/status_block protocol the chip
8828                  * uses with the cpu is race prone.
8829                  */
8830                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8831                         tw32(GRC_LOCAL_CTRL,
8832                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8833                 } else {
8834                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8835                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8836                 }
8837
8838                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8839                         tg3_flag_set(tp, RESTART_TIMER);
8840                         spin_unlock(&tp->lock);
8841                         schedule_work(&tp->reset_task);
8842                         return;
8843                 }
8844         }
8845
8846         /* This part only runs once per second. */
8847         if (!--tp->timer_counter) {
8848                 if (tg3_flag(tp, 5705_PLUS))
8849                         tg3_periodic_fetch_stats(tp);
8850
8851                 if (tp->setlpicnt && !--tp->setlpicnt)
8852                         tg3_phy_eee_enable(tp);
8853
8854                 if (tg3_flag(tp, USE_LINKCHG_REG)) {
8855                         u32 mac_stat;
8856                         int phy_event;
8857
8858                         mac_stat = tr32(MAC_STATUS);
8859
8860                         phy_event = 0;
8861                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8862                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8863                                         phy_event = 1;
8864                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8865                                 phy_event = 1;
8866
8867                         if (phy_event)
8868                                 tg3_setup_phy(tp, 0);
8869                 } else if (tg3_flag(tp, POLL_SERDES)) {
8870                         u32 mac_stat = tr32(MAC_STATUS);
8871                         int need_setup = 0;
8872
8873                         if (netif_carrier_ok(tp->dev) &&
8874                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8875                                 need_setup = 1;
8876                         }
8877                         if (!netif_carrier_ok(tp->dev) &&
8878                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8879                                          MAC_STATUS_SIGNAL_DET))) {
8880                                 need_setup = 1;
8881                         }
8882                         if (need_setup) {
8883                                 if (!tp->serdes_counter) {
8884                                         tw32_f(MAC_MODE,
8885                                              (tp->mac_mode &
8886                                               ~MAC_MODE_PORT_MODE_MASK));
8887                                         udelay(40);
8888                                         tw32_f(MAC_MODE, tp->mac_mode);
8889                                         udelay(40);
8890                                 }
8891                                 tg3_setup_phy(tp, 0);
8892                         }
8893                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8894                            tg3_flag(tp, 5780_CLASS)) {
8895                         tg3_serdes_parallel_detect(tp);
8896                 }
8897
8898                 tp->timer_counter = tp->timer_multiplier;
8899         }
8900
8901         /* Heartbeat is only sent once every 2 seconds.
8902          *
8903          * The heartbeat is to tell the ASF firmware that the host
8904          * driver is still alive.  In the event that the OS crashes,
8905          * ASF needs to reset the hardware to free up the FIFO space
8906          * that may be filled with rx packets destined for the host.
8907          * If the FIFO is full, ASF will no longer function properly.
8908          *
8909          * Unintended resets have been reported on real time kernels
8910          * where the timer doesn't run on time.  Netpoll will also have
8911          * same problem.
8912          *
8913          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8914          * to check the ring condition when the heartbeat is expiring
8915          * before doing the reset.  This will prevent most unintended
8916          * resets.
8917          */
8918         if (!--tp->asf_counter) {
8919                 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
8920                         tg3_wait_for_event_ack(tp);
8921
8922                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8923                                       FWCMD_NICDRV_ALIVE3);
8924                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8925                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8926                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8927
8928                         tg3_generate_fw_event(tp);
8929                 }
8930                 tp->asf_counter = tp->asf_multiplier;
8931         }
8932
8933         spin_unlock(&tp->lock);
8934
8935 restart_timer:
8936         tp->timer.expires = jiffies + tp->timer_offset;
8937         add_timer(&tp->timer);
8938 }
8939
8940 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8941 {
8942         irq_handler_t fn;
8943         unsigned long flags;
8944         char *name;
8945         struct tg3_napi *tnapi = &tp->napi[irq_num];
8946
8947         if (tp->irq_cnt == 1)
8948                 name = tp->dev->name;
8949         else {
8950                 name = &tnapi->irq_lbl[0];
8951                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8952                 name[IFNAMSIZ-1] = 0;
8953         }
8954
8955         if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
8956                 fn = tg3_msi;
8957                 if (tg3_flag(tp, 1SHOT_MSI))
8958                         fn = tg3_msi_1shot;
8959                 flags = 0;
8960         } else {
8961                 fn = tg3_interrupt;
8962                 if (tg3_flag(tp, TAGGED_STATUS))
8963                         fn = tg3_interrupt_tagged;
8964                 flags = IRQF_SHARED;
8965         }
8966
8967         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8968 }
8969
8970 static int tg3_test_interrupt(struct tg3 *tp)
8971 {
8972         struct tg3_napi *tnapi = &tp->napi[0];
8973         struct net_device *dev = tp->dev;
8974         int err, i, intr_ok = 0;
8975         u32 val;
8976
8977         if (!netif_running(dev))
8978                 return -ENODEV;
8979
8980         tg3_disable_ints(tp);
8981
8982         free_irq(tnapi->irq_vec, tnapi);
8983
8984         /*
8985          * Turn off MSI one shot mode.  Otherwise this test has no
8986          * observable way to know whether the interrupt was delivered.
8987          */
8988         if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
8989                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8990                 tw32(MSGINT_MODE, val);
8991         }
8992
8993         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8994                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8995         if (err)
8996                 return err;
8997
8998         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8999         tg3_enable_ints(tp);
9000
9001         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9002                tnapi->coal_now);
9003
9004         for (i = 0; i < 5; i++) {
9005                 u32 int_mbox, misc_host_ctrl;
9006
9007                 int_mbox = tr32_mailbox(tnapi->int_mbox);
9008                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9009
9010                 if ((int_mbox != 0) ||
9011                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
9012                         intr_ok = 1;
9013                         break;
9014                 }
9015
9016                 msleep(10);
9017         }
9018
9019         tg3_disable_ints(tp);
9020
9021         free_irq(tnapi->irq_vec, tnapi);
9022
9023         err = tg3_request_irq(tp, 0);
9024
9025         if (err)
9026                 return err;
9027
9028         if (intr_ok) {
9029                 /* Reenable MSI one shot mode. */
9030                 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
9031                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9032                         tw32(MSGINT_MODE, val);
9033                 }
9034                 return 0;
9035         }
9036
9037         return -EIO;
9038 }
9039
9040 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9041  * successfully restored
9042  */
9043 static int tg3_test_msi(struct tg3 *tp)
9044 {
9045         int err;
9046         u16 pci_cmd;
9047
9048         if (!tg3_flag(tp, USING_MSI))
9049                 return 0;
9050
9051         /* Turn off SERR reporting in case MSI terminates with Master
9052          * Abort.
9053          */
9054         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9055         pci_write_config_word(tp->pdev, PCI_COMMAND,
9056                               pci_cmd & ~PCI_COMMAND_SERR);
9057
9058         err = tg3_test_interrupt(tp);
9059
9060         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9061
9062         if (!err)
9063                 return 0;
9064
9065         /* other failures */
9066         if (err != -EIO)
9067                 return err;
9068
9069         /* MSI test failed, go back to INTx mode */
9070         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
9071                     "to INTx mode. Please report this failure to the PCI "
9072                     "maintainer and include system chipset information\n");
9073
9074         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9075
9076         pci_disable_msi(tp->pdev);
9077
9078         tg3_flag_clear(tp, USING_MSI);
9079         tp->napi[0].irq_vec = tp->pdev->irq;
9080
9081         err = tg3_request_irq(tp, 0);
9082         if (err)
9083                 return err;
9084
9085         /* Need to reset the chip because the MSI cycle may have terminated
9086          * with Master Abort.
9087          */
9088         tg3_full_lock(tp, 1);
9089
9090         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9091         err = tg3_init_hw(tp, 1);
9092
9093         tg3_full_unlock(tp);
9094
9095         if (err)
9096                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9097
9098         return err;
9099 }
9100
9101 static int tg3_request_firmware(struct tg3 *tp)
9102 {
9103         const __be32 *fw_data;
9104
9105         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
9106                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9107                            tp->fw_needed);
9108                 return -ENOENT;
9109         }
9110
9111         fw_data = (void *)tp->fw->data;
9112
9113         /* Firmware blob starts with version numbers, followed by
9114          * start address and _full_ length including BSS sections
9115          * (which must be longer than the actual data, of course
9116          */
9117
9118         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
9119         if (tp->fw_len < (tp->fw->size - 12)) {
9120                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9121                            tp->fw_len, tp->fw_needed);
9122                 release_firmware(tp->fw);
9123                 tp->fw = NULL;
9124                 return -EINVAL;
9125         }
9126
9127         /* We no longer need firmware; we have it. */
9128         tp->fw_needed = NULL;
9129         return 0;
9130 }
9131
9132 static bool tg3_enable_msix(struct tg3 *tp)
9133 {
9134         int i, rc, cpus = num_online_cpus();
9135         struct msix_entry msix_ent[tp->irq_max];
9136
9137         if (cpus == 1)
9138                 /* Just fallback to the simpler MSI mode. */
9139                 return false;
9140
9141         /*
9142          * We want as many rx rings enabled as there are cpus.
9143          * The first MSIX vector only deals with link interrupts, etc,
9144          * so we add one to the number of vectors we are requesting.
9145          */
9146         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9147
9148         for (i = 0; i < tp->irq_max; i++) {
9149                 msix_ent[i].entry  = i;
9150                 msix_ent[i].vector = 0;
9151         }
9152
9153         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9154         if (rc < 0) {
9155                 return false;
9156         } else if (rc != 0) {
9157                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9158                         return false;
9159                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9160                               tp->irq_cnt, rc);
9161                 tp->irq_cnt = rc;
9162         }
9163
9164         for (i = 0; i < tp->irq_max; i++)
9165                 tp->napi[i].irq_vec = msix_ent[i].vector;
9166
9167         netif_set_real_num_tx_queues(tp->dev, 1);
9168         rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9169         if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9170                 pci_disable_msix(tp->pdev);
9171                 return false;
9172         }
9173
9174         if (tp->irq_cnt > 1) {
9175                 tg3_flag_set(tp, ENABLE_RSS);
9176
9177                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9178                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9179                         tg3_flag_set(tp, ENABLE_TSS);
9180                         netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9181                 }
9182         }
9183
9184         return true;
9185 }
9186
9187 static void tg3_ints_init(struct tg3 *tp)
9188 {
9189         if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
9190             !tg3_flag(tp, TAGGED_STATUS)) {
9191                 /* All MSI supporting chips should support tagged
9192                  * status.  Assert that this is the case.
9193                  */
9194                 netdev_warn(tp->dev,
9195                             "MSI without TAGGED_STATUS? Not using MSI\n");
9196                 goto defcfg;
9197         }
9198
9199         if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
9200                 tg3_flag_set(tp, USING_MSIX);
9201         else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
9202                 tg3_flag_set(tp, USING_MSI);
9203
9204         if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9205                 u32 msi_mode = tr32(MSGINT_MODE);
9206                 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
9207                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9208                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9209         }
9210 defcfg:
9211         if (!tg3_flag(tp, USING_MSIX)) {
9212                 tp->irq_cnt = 1;
9213                 tp->napi[0].irq_vec = tp->pdev->irq;
9214                 netif_set_real_num_tx_queues(tp->dev, 1);
9215                 netif_set_real_num_rx_queues(tp->dev, 1);
9216         }
9217 }
9218
9219 static void tg3_ints_fini(struct tg3 *tp)
9220 {
9221         if (tg3_flag(tp, USING_MSIX))
9222                 pci_disable_msix(tp->pdev);
9223         else if (tg3_flag(tp, USING_MSI))
9224                 pci_disable_msi(tp->pdev);
9225         tg3_flag_clear(tp, USING_MSI);
9226         tg3_flag_clear(tp, USING_MSIX);
9227         tg3_flag_clear(tp, ENABLE_RSS);
9228         tg3_flag_clear(tp, ENABLE_TSS);
9229 }
9230
9231 static int tg3_open(struct net_device *dev)
9232 {
9233         struct tg3 *tp = netdev_priv(dev);
9234         int i, err;
9235
9236         if (tp->fw_needed) {
9237                 err = tg3_request_firmware(tp);
9238                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9239                         if (err)
9240                                 return err;
9241                 } else if (err) {
9242                         netdev_warn(tp->dev, "TSO capability disabled\n");
9243                         tg3_flag_clear(tp, TSO_CAPABLE);
9244                 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
9245                         netdev_notice(tp->dev, "TSO capability restored\n");
9246                         tg3_flag_set(tp, TSO_CAPABLE);
9247                 }
9248         }
9249
9250         netif_carrier_off(tp->dev);
9251
9252         err = tg3_power_up(tp);
9253         if (err)
9254                 return err;
9255
9256         tg3_full_lock(tp, 0);
9257
9258         tg3_disable_ints(tp);
9259         tg3_flag_clear(tp, INIT_COMPLETE);
9260
9261         tg3_full_unlock(tp);
9262
9263         /*
9264          * Setup interrupts first so we know how
9265          * many NAPI resources to allocate
9266          */
9267         tg3_ints_init(tp);
9268
9269         /* The placement of this call is tied
9270          * to the setup and use of Host TX descriptors.
9271          */
9272         err = tg3_alloc_consistent(tp);
9273         if (err)
9274                 goto err_out1;
9275
9276         tg3_napi_init(tp);
9277
9278         tg3_napi_enable(tp);
9279
9280         for (i = 0; i < tp->irq_cnt; i++) {
9281                 struct tg3_napi *tnapi = &tp->napi[i];
9282                 err = tg3_request_irq(tp, i);
9283                 if (err) {
9284                         for (i--; i >= 0; i--)
9285                                 free_irq(tnapi->irq_vec, tnapi);
9286                         break;
9287                 }
9288         }
9289
9290         if (err)
9291                 goto err_out2;
9292
9293         tg3_full_lock(tp, 0);
9294
9295         err = tg3_init_hw(tp, 1);
9296         if (err) {
9297                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9298                 tg3_free_rings(tp);
9299         } else {
9300                 if (tg3_flag(tp, TAGGED_STATUS))
9301                         tp->timer_offset = HZ;
9302                 else
9303                         tp->timer_offset = HZ / 10;
9304
9305                 BUG_ON(tp->timer_offset > HZ);
9306                 tp->timer_counter = tp->timer_multiplier =
9307                         (HZ / tp->timer_offset);
9308                 tp->asf_counter = tp->asf_multiplier =
9309                         ((HZ / tp->timer_offset) * 2);
9310
9311                 init_timer(&tp->timer);
9312                 tp->timer.expires = jiffies + tp->timer_offset;
9313                 tp->timer.data = (unsigned long) tp;
9314                 tp->timer.function = tg3_timer;
9315         }
9316
9317         tg3_full_unlock(tp);
9318
9319         if (err)
9320                 goto err_out3;
9321
9322         if (tg3_flag(tp, USING_MSI)) {
9323                 err = tg3_test_msi(tp);
9324
9325                 if (err) {
9326                         tg3_full_lock(tp, 0);
9327                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9328                         tg3_free_rings(tp);
9329                         tg3_full_unlock(tp);
9330
9331                         goto err_out2;
9332                 }
9333
9334                 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
9335                         u32 val = tr32(PCIE_TRANSACTION_CFG);
9336
9337                         tw32(PCIE_TRANSACTION_CFG,
9338                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9339                 }
9340         }
9341
9342         tg3_phy_start(tp);
9343
9344         tg3_full_lock(tp, 0);
9345
9346         add_timer(&tp->timer);
9347         tg3_flag_set(tp, INIT_COMPLETE);
9348         tg3_enable_ints(tp);
9349
9350         tg3_full_unlock(tp);
9351
9352         netif_tx_start_all_queues(dev);
9353
9354         /*
9355          * Reset loopback feature if it was turned on while the device was down
9356          * make sure that it's installed properly now.
9357          */
9358         if (dev->features & NETIF_F_LOOPBACK)
9359                 tg3_set_loopback(dev, dev->features);
9360
9361         return 0;
9362
9363 err_out3:
9364         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9365                 struct tg3_napi *tnapi = &tp->napi[i];
9366                 free_irq(tnapi->irq_vec, tnapi);
9367         }
9368
9369 err_out2:
9370         tg3_napi_disable(tp);
9371         tg3_napi_fini(tp);
9372         tg3_free_consistent(tp);
9373
9374 err_out1:
9375         tg3_ints_fini(tp);
9376         return err;
9377 }
9378
9379 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9380                                                  struct rtnl_link_stats64 *);
9381 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9382
9383 static int tg3_close(struct net_device *dev)
9384 {
9385         int i;
9386         struct tg3 *tp = netdev_priv(dev);
9387
9388         tg3_napi_disable(tp);
9389         cancel_work_sync(&tp->reset_task);
9390
9391         netif_tx_stop_all_queues(dev);
9392
9393         del_timer_sync(&tp->timer);
9394
9395         tg3_phy_stop(tp);
9396
9397         tg3_full_lock(tp, 1);
9398
9399         tg3_disable_ints(tp);
9400
9401         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9402         tg3_free_rings(tp);
9403         tg3_flag_clear(tp, INIT_COMPLETE);
9404
9405         tg3_full_unlock(tp);
9406
9407         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9408                 struct tg3_napi *tnapi = &tp->napi[i];
9409                 free_irq(tnapi->irq_vec, tnapi);
9410         }
9411
9412         tg3_ints_fini(tp);
9413
9414         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9415
9416         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9417                sizeof(tp->estats_prev));
9418
9419         tg3_napi_fini(tp);
9420
9421         tg3_free_consistent(tp);
9422
9423         tg3_power_down(tp);
9424
9425         netif_carrier_off(tp->dev);
9426
9427         return 0;
9428 }
9429
9430 static inline u64 get_stat64(tg3_stat64_t *val)
9431 {
9432        return ((u64)val->high << 32) | ((u64)val->low);
9433 }
9434
9435 static u64 calc_crc_errors(struct tg3 *tp)
9436 {
9437         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9438
9439         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9440             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9441              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9442                 u32 val;
9443
9444                 spin_lock_bh(&tp->lock);
9445                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9446                         tg3_writephy(tp, MII_TG3_TEST1,
9447                                      val | MII_TG3_TEST1_CRC_EN);
9448                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9449                 } else
9450                         val = 0;
9451                 spin_unlock_bh(&tp->lock);
9452
9453                 tp->phy_crc_errors += val;
9454
9455                 return tp->phy_crc_errors;
9456         }
9457
9458         return get_stat64(&hw_stats->rx_fcs_errors);
9459 }
9460
9461 #define ESTAT_ADD(member) \
9462         estats->member =        old_estats->member + \
9463                                 get_stat64(&hw_stats->member)
9464
9465 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9466 {
9467         struct tg3_ethtool_stats *estats = &tp->estats;
9468         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9469         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9470
9471         if (!hw_stats)
9472                 return old_estats;
9473
9474         ESTAT_ADD(rx_octets);
9475         ESTAT_ADD(rx_fragments);
9476         ESTAT_ADD(rx_ucast_packets);
9477         ESTAT_ADD(rx_mcast_packets);
9478         ESTAT_ADD(rx_bcast_packets);
9479         ESTAT_ADD(rx_fcs_errors);
9480         ESTAT_ADD(rx_align_errors);
9481         ESTAT_ADD(rx_xon_pause_rcvd);
9482         ESTAT_ADD(rx_xoff_pause_rcvd);
9483         ESTAT_ADD(rx_mac_ctrl_rcvd);
9484         ESTAT_ADD(rx_xoff_entered);
9485         ESTAT_ADD(rx_frame_too_long_errors);
9486         ESTAT_ADD(rx_jabbers);
9487         ESTAT_ADD(rx_undersize_packets);
9488         ESTAT_ADD(rx_in_length_errors);
9489         ESTAT_ADD(rx_out_length_errors);
9490         ESTAT_ADD(rx_64_or_less_octet_packets);
9491         ESTAT_ADD(rx_65_to_127_octet_packets);
9492         ESTAT_ADD(rx_128_to_255_octet_packets);
9493         ESTAT_ADD(rx_256_to_511_octet_packets);
9494         ESTAT_ADD(rx_512_to_1023_octet_packets);
9495         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9496         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9497         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9498         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9499         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9500
9501         ESTAT_ADD(tx_octets);
9502         ESTAT_ADD(tx_collisions);
9503         ESTAT_ADD(tx_xon_sent);
9504         ESTAT_ADD(tx_xoff_sent);
9505         ESTAT_ADD(tx_flow_control);
9506         ESTAT_ADD(tx_mac_errors);
9507         ESTAT_ADD(tx_single_collisions);
9508         ESTAT_ADD(tx_mult_collisions);
9509         ESTAT_ADD(tx_deferred);
9510         ESTAT_ADD(tx_excessive_collisions);
9511         ESTAT_ADD(tx_late_collisions);
9512         ESTAT_ADD(tx_collide_2times);
9513         ESTAT_ADD(tx_collide_3times);
9514         ESTAT_ADD(tx_collide_4times);
9515         ESTAT_ADD(tx_collide_5times);
9516         ESTAT_ADD(tx_collide_6times);
9517         ESTAT_ADD(tx_collide_7times);
9518         ESTAT_ADD(tx_collide_8times);
9519         ESTAT_ADD(tx_collide_9times);
9520         ESTAT_ADD(tx_collide_10times);
9521         ESTAT_ADD(tx_collide_11times);
9522         ESTAT_ADD(tx_collide_12times);
9523         ESTAT_ADD(tx_collide_13times);
9524         ESTAT_ADD(tx_collide_14times);
9525         ESTAT_ADD(tx_collide_15times);
9526         ESTAT_ADD(tx_ucast_packets);
9527         ESTAT_ADD(tx_mcast_packets);
9528         ESTAT_ADD(tx_bcast_packets);
9529         ESTAT_ADD(tx_carrier_sense_errors);
9530         ESTAT_ADD(tx_discards);
9531         ESTAT_ADD(tx_errors);
9532
9533         ESTAT_ADD(dma_writeq_full);
9534         ESTAT_ADD(dma_write_prioq_full);
9535         ESTAT_ADD(rxbds_empty);
9536         ESTAT_ADD(rx_discards);
9537         ESTAT_ADD(rx_errors);
9538         ESTAT_ADD(rx_threshold_hit);
9539
9540         ESTAT_ADD(dma_readq_full);
9541         ESTAT_ADD(dma_read_prioq_full);
9542         ESTAT_ADD(tx_comp_queue_full);
9543
9544         ESTAT_ADD(ring_set_send_prod_index);
9545         ESTAT_ADD(ring_status_update);
9546         ESTAT_ADD(nic_irqs);
9547         ESTAT_ADD(nic_avoided_irqs);
9548         ESTAT_ADD(nic_tx_threshold_hit);
9549
9550         ESTAT_ADD(mbuf_lwm_thresh_hit);
9551
9552         return estats;
9553 }
9554
9555 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9556                                                  struct rtnl_link_stats64 *stats)
9557 {
9558         struct tg3 *tp = netdev_priv(dev);
9559         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9560         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9561
9562         if (!hw_stats)
9563                 return old_stats;
9564
9565         stats->rx_packets = old_stats->rx_packets +
9566                 get_stat64(&hw_stats->rx_ucast_packets) +
9567                 get_stat64(&hw_stats->rx_mcast_packets) +
9568                 get_stat64(&hw_stats->rx_bcast_packets);
9569
9570         stats->tx_packets = old_stats->tx_packets +
9571                 get_stat64(&hw_stats->tx_ucast_packets) +
9572                 get_stat64(&hw_stats->tx_mcast_packets) +
9573                 get_stat64(&hw_stats->tx_bcast_packets);
9574
9575         stats->rx_bytes = old_stats->rx_bytes +
9576                 get_stat64(&hw_stats->rx_octets);
9577         stats->tx_bytes = old_stats->tx_bytes +
9578                 get_stat64(&hw_stats->tx_octets);
9579
9580         stats->rx_errors = old_stats->rx_errors +
9581                 get_stat64(&hw_stats->rx_errors);
9582         stats->tx_errors = old_stats->tx_errors +
9583                 get_stat64(&hw_stats->tx_errors) +
9584                 get_stat64(&hw_stats->tx_mac_errors) +
9585                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9586                 get_stat64(&hw_stats->tx_discards);
9587
9588         stats->multicast = old_stats->multicast +
9589                 get_stat64(&hw_stats->rx_mcast_packets);
9590         stats->collisions = old_stats->collisions +
9591                 get_stat64(&hw_stats->tx_collisions);
9592
9593         stats->rx_length_errors = old_stats->rx_length_errors +
9594                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9595                 get_stat64(&hw_stats->rx_undersize_packets);
9596
9597         stats->rx_over_errors = old_stats->rx_over_errors +
9598                 get_stat64(&hw_stats->rxbds_empty);
9599         stats->rx_frame_errors = old_stats->rx_frame_errors +
9600                 get_stat64(&hw_stats->rx_align_errors);
9601         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9602                 get_stat64(&hw_stats->tx_discards);
9603         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9604                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9605
9606         stats->rx_crc_errors = old_stats->rx_crc_errors +
9607                 calc_crc_errors(tp);
9608
9609         stats->rx_missed_errors = old_stats->rx_missed_errors +
9610                 get_stat64(&hw_stats->rx_discards);
9611
9612         stats->rx_dropped = tp->rx_dropped;
9613
9614         return stats;
9615 }
9616
9617 static inline u32 calc_crc(unsigned char *buf, int len)
9618 {
9619         u32 reg;
9620         u32 tmp;
9621         int j, k;
9622
9623         reg = 0xffffffff;
9624
9625         for (j = 0; j < len; j++) {
9626                 reg ^= buf[j];
9627
9628                 for (k = 0; k < 8; k++) {
9629                         tmp = reg & 0x01;
9630
9631                         reg >>= 1;
9632
9633                         if (tmp)
9634                                 reg ^= 0xedb88320;
9635                 }
9636         }
9637
9638         return ~reg;
9639 }
9640
9641 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9642 {
9643         /* accept or reject all multicast frames */
9644         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9645         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9646         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9647         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9648 }
9649
9650 static void __tg3_set_rx_mode(struct net_device *dev)
9651 {
9652         struct tg3 *tp = netdev_priv(dev);
9653         u32 rx_mode;
9654
9655         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9656                                   RX_MODE_KEEP_VLAN_TAG);
9657
9658 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9659         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9660          * flag clear.
9661          */
9662         if (!tg3_flag(tp, ENABLE_ASF))
9663                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9664 #endif
9665
9666         if (dev->flags & IFF_PROMISC) {
9667                 /* Promiscuous mode. */
9668                 rx_mode |= RX_MODE_PROMISC;
9669         } else if (dev->flags & IFF_ALLMULTI) {
9670                 /* Accept all multicast. */
9671                 tg3_set_multi(tp, 1);
9672         } else if (netdev_mc_empty(dev)) {
9673                 /* Reject all multicast. */
9674                 tg3_set_multi(tp, 0);
9675         } else {
9676                 /* Accept one or more multicast(s). */
9677                 struct netdev_hw_addr *ha;
9678                 u32 mc_filter[4] = { 0, };
9679                 u32 regidx;
9680                 u32 bit;
9681                 u32 crc;
9682
9683                 netdev_for_each_mc_addr(ha, dev) {
9684                         crc = calc_crc(ha->addr, ETH_ALEN);
9685                         bit = ~crc & 0x7f;
9686                         regidx = (bit & 0x60) >> 5;
9687                         bit &= 0x1f;
9688                         mc_filter[regidx] |= (1 << bit);
9689                 }
9690
9691                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9692                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9693                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9694                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9695         }
9696
9697         if (rx_mode != tp->rx_mode) {
9698                 tp->rx_mode = rx_mode;
9699                 tw32_f(MAC_RX_MODE, rx_mode);
9700                 udelay(10);
9701         }
9702 }
9703
9704 static void tg3_set_rx_mode(struct net_device *dev)
9705 {
9706         struct tg3 *tp = netdev_priv(dev);
9707
9708         if (!netif_running(dev))
9709                 return;
9710
9711         tg3_full_lock(tp, 0);
9712         __tg3_set_rx_mode(dev);
9713         tg3_full_unlock(tp);
9714 }
9715
9716 static int tg3_get_regs_len(struct net_device *dev)
9717 {
9718         return TG3_REG_BLK_SIZE;
9719 }
9720
9721 static void tg3_get_regs(struct net_device *dev,
9722                 struct ethtool_regs *regs, void *_p)
9723 {
9724         struct tg3 *tp = netdev_priv(dev);
9725
9726         regs->version = 0;
9727
9728         memset(_p, 0, TG3_REG_BLK_SIZE);
9729
9730         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9731                 return;
9732
9733         tg3_full_lock(tp, 0);
9734
9735         tg3_dump_legacy_regs(tp, (u32 *)_p);
9736
9737         tg3_full_unlock(tp);
9738 }
9739
9740 static int tg3_get_eeprom_len(struct net_device *dev)
9741 {
9742         struct tg3 *tp = netdev_priv(dev);
9743
9744         return tp->nvram_size;
9745 }
9746
9747 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9748 {
9749         struct tg3 *tp = netdev_priv(dev);
9750         int ret;
9751         u8  *pd;
9752         u32 i, offset, len, b_offset, b_count;
9753         __be32 val;
9754
9755         if (tg3_flag(tp, NO_NVRAM))
9756                 return -EINVAL;
9757
9758         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9759                 return -EAGAIN;
9760
9761         offset = eeprom->offset;
9762         len = eeprom->len;
9763         eeprom->len = 0;
9764
9765         eeprom->magic = TG3_EEPROM_MAGIC;
9766
9767         if (offset & 3) {
9768                 /* adjustments to start on required 4 byte boundary */
9769                 b_offset = offset & 3;
9770                 b_count = 4 - b_offset;
9771                 if (b_count > len) {
9772                         /* i.e. offset=1 len=2 */
9773                         b_count = len;
9774                 }
9775                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9776                 if (ret)
9777                         return ret;
9778                 memcpy(data, ((char *)&val) + b_offset, b_count);
9779                 len -= b_count;
9780                 offset += b_count;
9781                 eeprom->len += b_count;
9782         }
9783
9784         /* read bytes up to the last 4 byte boundary */
9785         pd = &data[eeprom->len];
9786         for (i = 0; i < (len - (len & 3)); i += 4) {
9787                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9788                 if (ret) {
9789                         eeprom->len += i;
9790                         return ret;
9791                 }
9792                 memcpy(pd + i, &val, 4);
9793         }
9794         eeprom->len += i;
9795
9796         if (len & 3) {
9797                 /* read last bytes not ending on 4 byte boundary */
9798                 pd = &data[eeprom->len];
9799                 b_count = len & 3;
9800                 b_offset = offset + len - b_count;
9801                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9802                 if (ret)
9803                         return ret;
9804                 memcpy(pd, &val, b_count);
9805                 eeprom->len += b_count;
9806         }
9807         return 0;
9808 }
9809
9810 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9811
9812 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9813 {
9814         struct tg3 *tp = netdev_priv(dev);
9815         int ret;
9816         u32 offset, len, b_offset, odd_len;
9817         u8 *buf;
9818         __be32 start, end;
9819
9820         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9821                 return -EAGAIN;
9822
9823         if (tg3_flag(tp, NO_NVRAM) ||
9824             eeprom->magic != TG3_EEPROM_MAGIC)
9825                 return -EINVAL;
9826
9827         offset = eeprom->offset;
9828         len = eeprom->len;
9829
9830         if ((b_offset = (offset & 3))) {
9831                 /* adjustments to start on required 4 byte boundary */
9832                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9833                 if (ret)
9834                         return ret;
9835                 len += b_offset;
9836                 offset &= ~3;
9837                 if (len < 4)
9838                         len = 4;
9839         }
9840
9841         odd_len = 0;
9842         if (len & 3) {
9843                 /* adjustments to end on required 4 byte boundary */
9844                 odd_len = 1;
9845                 len = (len + 3) & ~3;
9846                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9847                 if (ret)
9848                         return ret;
9849         }
9850
9851         buf = data;
9852         if (b_offset || odd_len) {
9853                 buf = kmalloc(len, GFP_KERNEL);
9854                 if (!buf)
9855                         return -ENOMEM;
9856                 if (b_offset)
9857                         memcpy(buf, &start, 4);
9858                 if (odd_len)
9859                         memcpy(buf+len-4, &end, 4);
9860                 memcpy(buf + b_offset, data, eeprom->len);
9861         }
9862
9863         ret = tg3_nvram_write_block(tp, offset, len, buf);
9864
9865         if (buf != data)
9866                 kfree(buf);
9867
9868         return ret;
9869 }
9870
9871 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9872 {
9873         struct tg3 *tp = netdev_priv(dev);
9874
9875         if (tg3_flag(tp, USE_PHYLIB)) {
9876                 struct phy_device *phydev;
9877                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9878                         return -EAGAIN;
9879                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9880                 return phy_ethtool_gset(phydev, cmd);
9881         }
9882
9883         cmd->supported = (SUPPORTED_Autoneg);
9884
9885         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9886                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9887                                    SUPPORTED_1000baseT_Full);
9888
9889         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9890                 cmd->supported |= (SUPPORTED_100baseT_Half |
9891                                   SUPPORTED_100baseT_Full |
9892                                   SUPPORTED_10baseT_Half |
9893                                   SUPPORTED_10baseT_Full |
9894                                   SUPPORTED_TP);
9895                 cmd->port = PORT_TP;
9896         } else {
9897                 cmd->supported |= SUPPORTED_FIBRE;
9898                 cmd->port = PORT_FIBRE;
9899         }
9900
9901         cmd->advertising = tp->link_config.advertising;
9902         if (netif_running(dev)) {
9903                 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
9904                 cmd->duplex = tp->link_config.active_duplex;
9905         } else {
9906                 ethtool_cmd_speed_set(cmd, SPEED_INVALID);
9907                 cmd->duplex = DUPLEX_INVALID;
9908         }
9909         cmd->phy_address = tp->phy_addr;
9910         cmd->transceiver = XCVR_INTERNAL;
9911         cmd->autoneg = tp->link_config.autoneg;
9912         cmd->maxtxpkt = 0;
9913         cmd->maxrxpkt = 0;
9914         return 0;
9915 }
9916
9917 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9918 {
9919         struct tg3 *tp = netdev_priv(dev);
9920         u32 speed = ethtool_cmd_speed(cmd);
9921
9922         if (tg3_flag(tp, USE_PHYLIB)) {
9923                 struct phy_device *phydev;
9924                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9925                         return -EAGAIN;
9926                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9927                 return phy_ethtool_sset(phydev, cmd);
9928         }
9929
9930         if (cmd->autoneg != AUTONEG_ENABLE &&
9931             cmd->autoneg != AUTONEG_DISABLE)
9932                 return -EINVAL;
9933
9934         if (cmd->autoneg == AUTONEG_DISABLE &&
9935             cmd->duplex != DUPLEX_FULL &&
9936             cmd->duplex != DUPLEX_HALF)
9937                 return -EINVAL;
9938
9939         if (cmd->autoneg == AUTONEG_ENABLE) {
9940                 u32 mask = ADVERTISED_Autoneg |
9941                            ADVERTISED_Pause |
9942                            ADVERTISED_Asym_Pause;
9943
9944                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9945                         mask |= ADVERTISED_1000baseT_Half |
9946                                 ADVERTISED_1000baseT_Full;
9947
9948                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9949                         mask |= ADVERTISED_100baseT_Half |
9950                                 ADVERTISED_100baseT_Full |
9951                                 ADVERTISED_10baseT_Half |
9952                                 ADVERTISED_10baseT_Full |
9953                                 ADVERTISED_TP;
9954                 else
9955                         mask |= ADVERTISED_FIBRE;
9956
9957                 if (cmd->advertising & ~mask)
9958                         return -EINVAL;
9959
9960                 mask &= (ADVERTISED_1000baseT_Half |
9961                          ADVERTISED_1000baseT_Full |
9962                          ADVERTISED_100baseT_Half |
9963                          ADVERTISED_100baseT_Full |
9964                          ADVERTISED_10baseT_Half |
9965                          ADVERTISED_10baseT_Full);
9966
9967                 cmd->advertising &= mask;
9968         } else {
9969                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9970                         if (speed != SPEED_1000)
9971                                 return -EINVAL;
9972
9973                         if (cmd->duplex != DUPLEX_FULL)
9974                                 return -EINVAL;
9975                 } else {
9976                         if (speed != SPEED_100 &&
9977                             speed != SPEED_10)
9978                                 return -EINVAL;
9979                 }
9980         }
9981
9982         tg3_full_lock(tp, 0);
9983
9984         tp->link_config.autoneg = cmd->autoneg;
9985         if (cmd->autoneg == AUTONEG_ENABLE) {
9986                 tp->link_config.advertising = (cmd->advertising |
9987                                               ADVERTISED_Autoneg);
9988                 tp->link_config.speed = SPEED_INVALID;
9989                 tp->link_config.duplex = DUPLEX_INVALID;
9990         } else {
9991                 tp->link_config.advertising = 0;
9992                 tp->link_config.speed = speed;
9993                 tp->link_config.duplex = cmd->duplex;
9994         }
9995
9996         tp->link_config.orig_speed = tp->link_config.speed;
9997         tp->link_config.orig_duplex = tp->link_config.duplex;
9998         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9999
10000         if (netif_running(dev))
10001                 tg3_setup_phy(tp, 1);
10002
10003         tg3_full_unlock(tp);
10004
10005         return 0;
10006 }
10007
10008 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10009 {
10010         struct tg3 *tp = netdev_priv(dev);
10011
10012         strcpy(info->driver, DRV_MODULE_NAME);
10013         strcpy(info->version, DRV_MODULE_VERSION);
10014         strcpy(info->fw_version, tp->fw_ver);
10015         strcpy(info->bus_info, pci_name(tp->pdev));
10016 }
10017
10018 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10019 {
10020         struct tg3 *tp = netdev_priv(dev);
10021
10022         if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
10023                 wol->supported = WAKE_MAGIC;
10024         else
10025                 wol->supported = 0;
10026         wol->wolopts = 0;
10027         if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
10028                 wol->wolopts = WAKE_MAGIC;
10029         memset(&wol->sopass, 0, sizeof(wol->sopass));
10030 }
10031
10032 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10033 {
10034         struct tg3 *tp = netdev_priv(dev);
10035         struct device *dp = &tp->pdev->dev;
10036
10037         if (wol->wolopts & ~WAKE_MAGIC)
10038                 return -EINVAL;
10039         if ((wol->wolopts & WAKE_MAGIC) &&
10040             !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
10041                 return -EINVAL;
10042
10043         device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10044
10045         spin_lock_bh(&tp->lock);
10046         if (device_may_wakeup(dp))
10047                 tg3_flag_set(tp, WOL_ENABLE);
10048         else
10049                 tg3_flag_clear(tp, WOL_ENABLE);
10050         spin_unlock_bh(&tp->lock);
10051
10052         return 0;
10053 }
10054
10055 static u32 tg3_get_msglevel(struct net_device *dev)
10056 {
10057         struct tg3 *tp = netdev_priv(dev);
10058         return tp->msg_enable;
10059 }
10060
10061 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10062 {
10063         struct tg3 *tp = netdev_priv(dev);
10064         tp->msg_enable = value;
10065 }
10066
10067 static int tg3_nway_reset(struct net_device *dev)
10068 {
10069         struct tg3 *tp = netdev_priv(dev);
10070         int r;
10071
10072         if (!netif_running(dev))
10073                 return -EAGAIN;
10074
10075         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10076                 return -EINVAL;
10077
10078         if (tg3_flag(tp, USE_PHYLIB)) {
10079                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10080                         return -EAGAIN;
10081                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10082         } else {
10083                 u32 bmcr;
10084
10085                 spin_lock_bh(&tp->lock);
10086                 r = -EINVAL;
10087                 tg3_readphy(tp, MII_BMCR, &bmcr);
10088                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10089                     ((bmcr & BMCR_ANENABLE) ||
10090                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10091                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10092                                                    BMCR_ANENABLE);
10093                         r = 0;
10094                 }
10095                 spin_unlock_bh(&tp->lock);
10096         }
10097
10098         return r;
10099 }
10100
10101 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10102 {
10103         struct tg3 *tp = netdev_priv(dev);
10104
10105         ering->rx_max_pending = tp->rx_std_ring_mask;
10106         ering->rx_mini_max_pending = 0;
10107         if (tg3_flag(tp, JUMBO_RING_ENABLE))
10108                 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10109         else
10110                 ering->rx_jumbo_max_pending = 0;
10111
10112         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10113
10114         ering->rx_pending = tp->rx_pending;
10115         ering->rx_mini_pending = 0;
10116         if (tg3_flag(tp, JUMBO_RING_ENABLE))
10117                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10118         else
10119                 ering->rx_jumbo_pending = 0;
10120
10121         ering->tx_pending = tp->napi[0].tx_pending;
10122 }
10123
10124 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10125 {
10126         struct tg3 *tp = netdev_priv(dev);
10127         int i, irq_sync = 0, err = 0;
10128
10129         if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10130             (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10131             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10132             (ering->tx_pending <= MAX_SKB_FRAGS) ||
10133             (tg3_flag(tp, TSO_BUG) &&
10134              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10135                 return -EINVAL;
10136
10137         if (netif_running(dev)) {
10138                 tg3_phy_stop(tp);
10139                 tg3_netif_stop(tp);
10140                 irq_sync = 1;
10141         }
10142
10143         tg3_full_lock(tp, irq_sync);
10144
10145         tp->rx_pending = ering->rx_pending;
10146
10147         if (tg3_flag(tp, MAX_RXPEND_64) &&
10148             tp->rx_pending > 63)
10149                 tp->rx_pending = 63;
10150         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10151
10152         for (i = 0; i < tp->irq_max; i++)
10153                 tp->napi[i].tx_pending = ering->tx_pending;
10154
10155         if (netif_running(dev)) {
10156                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10157                 err = tg3_restart_hw(tp, 1);
10158                 if (!err)
10159                         tg3_netif_start(tp);
10160         }
10161
10162         tg3_full_unlock(tp);
10163
10164         if (irq_sync && !err)
10165                 tg3_phy_start(tp);
10166
10167         return err;
10168 }
10169
10170 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10171 {
10172         struct tg3 *tp = netdev_priv(dev);
10173
10174         epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
10175
10176         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10177                 epause->rx_pause = 1;
10178         else
10179                 epause->rx_pause = 0;
10180
10181         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10182                 epause->tx_pause = 1;
10183         else
10184                 epause->tx_pause = 0;
10185 }
10186
10187 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10188 {
10189         struct tg3 *tp = netdev_priv(dev);
10190         int err = 0;
10191
10192         if (tg3_flag(tp, USE_PHYLIB)) {
10193                 u32 newadv;
10194                 struct phy_device *phydev;
10195
10196                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10197
10198                 if (!(phydev->supported & SUPPORTED_Pause) ||
10199                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10200                      (epause->rx_pause != epause->tx_pause)))
10201                         return -EINVAL;
10202
10203                 tp->link_config.flowctrl = 0;
10204                 if (epause->rx_pause) {
10205                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10206
10207                         if (epause->tx_pause) {
10208                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10209                                 newadv = ADVERTISED_Pause;
10210                         } else
10211                                 newadv = ADVERTISED_Pause |
10212                                          ADVERTISED_Asym_Pause;
10213                 } else if (epause->tx_pause) {
10214                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10215                         newadv = ADVERTISED_Asym_Pause;
10216                 } else
10217                         newadv = 0;
10218
10219                 if (epause->autoneg)
10220                         tg3_flag_set(tp, PAUSE_AUTONEG);
10221                 else
10222                         tg3_flag_clear(tp, PAUSE_AUTONEG);
10223
10224                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10225                         u32 oldadv = phydev->advertising &
10226                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10227                         if (oldadv != newadv) {
10228                                 phydev->advertising &=
10229                                         ~(ADVERTISED_Pause |
10230                                           ADVERTISED_Asym_Pause);
10231                                 phydev->advertising |= newadv;
10232                                 if (phydev->autoneg) {
10233                                         /*
10234                                          * Always renegotiate the link to
10235                                          * inform our link partner of our
10236                                          * flow control settings, even if the
10237                                          * flow control is forced.  Let
10238                                          * tg3_adjust_link() do the final
10239                                          * flow control setup.
10240                                          */
10241                                         return phy_start_aneg(phydev);
10242                                 }
10243                         }
10244
10245                         if (!epause->autoneg)
10246                                 tg3_setup_flow_control(tp, 0, 0);
10247                 } else {
10248                         tp->link_config.orig_advertising &=
10249                                         ~(ADVERTISED_Pause |
10250                                           ADVERTISED_Asym_Pause);
10251                         tp->link_config.orig_advertising |= newadv;
10252                 }
10253         } else {
10254                 int irq_sync = 0;
10255
10256                 if (netif_running(dev)) {
10257                         tg3_netif_stop(tp);
10258                         irq_sync = 1;
10259                 }
10260
10261                 tg3_full_lock(tp, irq_sync);
10262
10263                 if (epause->autoneg)
10264                         tg3_flag_set(tp, PAUSE_AUTONEG);
10265                 else
10266                         tg3_flag_clear(tp, PAUSE_AUTONEG);
10267                 if (epause->rx_pause)
10268                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10269                 else
10270                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10271                 if (epause->tx_pause)
10272                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10273                 else
10274                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10275
10276                 if (netif_running(dev)) {
10277                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10278                         err = tg3_restart_hw(tp, 1);
10279                         if (!err)
10280                                 tg3_netif_start(tp);
10281                 }
10282
10283                 tg3_full_unlock(tp);
10284         }
10285
10286         return err;
10287 }
10288
10289 static int tg3_get_sset_count(struct net_device *dev, int sset)
10290 {
10291         switch (sset) {
10292         case ETH_SS_TEST:
10293                 return TG3_NUM_TEST;
10294         case ETH_SS_STATS:
10295                 return TG3_NUM_STATS;
10296         default:
10297                 return -EOPNOTSUPP;
10298         }
10299 }
10300
10301 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10302 {
10303         switch (stringset) {
10304         case ETH_SS_STATS:
10305                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10306                 break;
10307         case ETH_SS_TEST:
10308                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10309                 break;
10310         default:
10311                 WARN_ON(1);     /* we need a WARN() */
10312                 break;
10313         }
10314 }
10315
10316 static int tg3_set_phys_id(struct net_device *dev,
10317                             enum ethtool_phys_id_state state)
10318 {
10319         struct tg3 *tp = netdev_priv(dev);
10320
10321         if (!netif_running(tp->dev))
10322                 return -EAGAIN;
10323
10324         switch (state) {
10325         case ETHTOOL_ID_ACTIVE:
10326                 return 1;       /* cycle on/off once per second */
10327
10328         case ETHTOOL_ID_ON:
10329                 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10330                      LED_CTRL_1000MBPS_ON |
10331                      LED_CTRL_100MBPS_ON |
10332                      LED_CTRL_10MBPS_ON |
10333                      LED_CTRL_TRAFFIC_OVERRIDE |
10334                      LED_CTRL_TRAFFIC_BLINK |
10335                      LED_CTRL_TRAFFIC_LED);
10336                 break;
10337
10338         case ETHTOOL_ID_OFF:
10339                 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10340                      LED_CTRL_TRAFFIC_OVERRIDE);
10341                 break;
10342
10343         case ETHTOOL_ID_INACTIVE:
10344                 tw32(MAC_LED_CTRL, tp->led_ctrl);
10345                 break;
10346         }
10347
10348         return 0;
10349 }
10350
10351 static void tg3_get_ethtool_stats(struct net_device *dev,
10352                                    struct ethtool_stats *estats, u64 *tmp_stats)
10353 {
10354         struct tg3 *tp = netdev_priv(dev);
10355         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10356 }
10357
10358 static __be32 * tg3_vpd_readblock(struct tg3 *tp)
10359 {
10360         int i;
10361         __be32 *buf;
10362         u32 offset = 0, len = 0;
10363         u32 magic, val;
10364
10365         if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
10366                 return NULL;
10367
10368         if (magic == TG3_EEPROM_MAGIC) {
10369                 for (offset = TG3_NVM_DIR_START;
10370                      offset < TG3_NVM_DIR_END;
10371                      offset += TG3_NVM_DIRENT_SIZE) {
10372                         if (tg3_nvram_read(tp, offset, &val))
10373                                 return NULL;
10374
10375                         if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
10376                             TG3_NVM_DIRTYPE_EXTVPD)
10377                                 break;
10378                 }
10379
10380                 if (offset != TG3_NVM_DIR_END) {
10381                         len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
10382                         if (tg3_nvram_read(tp, offset + 4, &offset))
10383                                 return NULL;
10384
10385                         offset = tg3_nvram_logical_addr(tp, offset);
10386                 }
10387         }
10388
10389         if (!offset || !len) {
10390                 offset = TG3_NVM_VPD_OFF;
10391                 len = TG3_NVM_VPD_LEN;
10392         }
10393
10394         buf = kmalloc(len, GFP_KERNEL);
10395         if (buf == NULL)
10396                 return NULL;
10397
10398         if (magic == TG3_EEPROM_MAGIC) {
10399                 for (i = 0; i < len; i += 4) {
10400                         /* The data is in little-endian format in NVRAM.
10401                          * Use the big-endian read routines to preserve
10402                          * the byte order as it exists in NVRAM.
10403                          */
10404                         if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
10405                                 goto error;
10406                 }
10407         } else {
10408                 u8 *ptr;
10409                 ssize_t cnt;
10410                 unsigned int pos = 0;
10411
10412                 ptr = (u8 *)&buf[0];
10413                 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
10414                         cnt = pci_read_vpd(tp->pdev, pos,
10415                                            len - pos, ptr);
10416                         if (cnt == -ETIMEDOUT || cnt == -EINTR)
10417                                 cnt = 0;
10418                         else if (cnt < 0)
10419                                 goto error;
10420                 }
10421                 if (pos != len)
10422                         goto error;
10423         }
10424
10425         return buf;
10426
10427 error:
10428         kfree(buf);
10429         return NULL;
10430 }
10431
10432 #define NVRAM_TEST_SIZE 0x100
10433 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10434 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10435 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10436 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10437 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10438
10439 static int tg3_test_nvram(struct tg3 *tp)
10440 {
10441         u32 csum, magic;
10442         __be32 *buf;
10443         int i, j, k, err = 0, size;
10444
10445         if (tg3_flag(tp, NO_NVRAM))
10446                 return 0;
10447
10448         if (tg3_nvram_read(tp, 0, &magic) != 0)
10449                 return -EIO;
10450
10451         if (magic == TG3_EEPROM_MAGIC)
10452                 size = NVRAM_TEST_SIZE;
10453         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10454                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10455                     TG3_EEPROM_SB_FORMAT_1) {
10456                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10457                         case TG3_EEPROM_SB_REVISION_0:
10458                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10459                                 break;
10460                         case TG3_EEPROM_SB_REVISION_2:
10461                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10462                                 break;
10463                         case TG3_EEPROM_SB_REVISION_3:
10464                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10465                                 break;
10466                         default:
10467                                 return 0;
10468                         }
10469                 } else
10470                         return 0;
10471         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10472                 size = NVRAM_SELFBOOT_HW_SIZE;
10473         else
10474                 return -EIO;
10475
10476         buf = kmalloc(size, GFP_KERNEL);
10477         if (buf == NULL)
10478                 return -ENOMEM;
10479
10480         err = -EIO;
10481         for (i = 0, j = 0; i < size; i += 4, j++) {
10482                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10483                 if (err)
10484                         break;
10485         }
10486         if (i < size)
10487                 goto out;
10488
10489         /* Selfboot format */
10490         magic = be32_to_cpu(buf[0]);
10491         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10492             TG3_EEPROM_MAGIC_FW) {
10493                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10494
10495                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10496                     TG3_EEPROM_SB_REVISION_2) {
10497                         /* For rev 2, the csum doesn't include the MBA. */
10498                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10499                                 csum8 += buf8[i];
10500                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10501                                 csum8 += buf8[i];
10502                 } else {
10503                         for (i = 0; i < size; i++)
10504                                 csum8 += buf8[i];
10505                 }
10506
10507                 if (csum8 == 0) {
10508                         err = 0;
10509                         goto out;
10510                 }
10511
10512                 err = -EIO;
10513                 goto out;
10514         }
10515
10516         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10517             TG3_EEPROM_MAGIC_HW) {
10518                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10519                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10520                 u8 *buf8 = (u8 *) buf;
10521
10522                 /* Separate the parity bits and the data bytes.  */
10523                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10524                         if ((i == 0) || (i == 8)) {
10525                                 int l;
10526                                 u8 msk;
10527
10528                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10529                                         parity[k++] = buf8[i] & msk;
10530                                 i++;
10531                         } else if (i == 16) {
10532                                 int l;
10533                                 u8 msk;
10534
10535                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10536                                         parity[k++] = buf8[i] & msk;
10537                                 i++;
10538
10539                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10540                                         parity[k++] = buf8[i] & msk;
10541                                 i++;
10542                         }
10543                         data[j++] = buf8[i];
10544                 }
10545
10546                 err = -EIO;
10547                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10548                         u8 hw8 = hweight8(data[i]);
10549
10550                         if ((hw8 & 0x1) && parity[i])
10551                                 goto out;
10552                         else if (!(hw8 & 0x1) && !parity[i])
10553                                 goto out;
10554                 }
10555                 err = 0;
10556                 goto out;
10557         }
10558
10559         err = -EIO;
10560
10561         /* Bootstrap checksum at offset 0x10 */
10562         csum = calc_crc((unsigned char *) buf, 0x10);
10563         if (csum != le32_to_cpu(buf[0x10/4]))
10564                 goto out;
10565
10566         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10567         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10568         if (csum != le32_to_cpu(buf[0xfc/4]))
10569                 goto out;
10570
10571         kfree(buf);
10572
10573         buf = tg3_vpd_readblock(tp);
10574         if (!buf)
10575                 return -ENOMEM;
10576
10577         i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN,
10578                              PCI_VPD_LRDT_RO_DATA);
10579         if (i > 0) {
10580                 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
10581                 if (j < 0)
10582                         goto out;
10583
10584                 if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN)
10585                         goto out;
10586
10587                 i += PCI_VPD_LRDT_TAG_SIZE;
10588                 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
10589                                               PCI_VPD_RO_KEYWORD_CHKSUM);
10590                 if (j > 0) {
10591                         u8 csum8 = 0;
10592
10593                         j += PCI_VPD_INFO_FLD_HDR_SIZE;
10594
10595                         for (i = 0; i <= j; i++)
10596                                 csum8 += ((u8 *)buf)[i];
10597
10598                         if (csum8)
10599                                 goto out;
10600                 }
10601         }
10602
10603         err = 0;
10604
10605 out:
10606         kfree(buf);
10607         return err;
10608 }
10609
10610 #define TG3_SERDES_TIMEOUT_SEC  2
10611 #define TG3_COPPER_TIMEOUT_SEC  6
10612
10613 static int tg3_test_link(struct tg3 *tp)
10614 {
10615         int i, max;
10616
10617         if (!netif_running(tp->dev))
10618                 return -ENODEV;
10619
10620         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10621                 max = TG3_SERDES_TIMEOUT_SEC;
10622         else
10623                 max = TG3_COPPER_TIMEOUT_SEC;
10624
10625         for (i = 0; i < max; i++) {
10626                 if (netif_carrier_ok(tp->dev))
10627                         return 0;
10628
10629                 if (msleep_interruptible(1000))
10630                         break;
10631         }
10632
10633         return -EIO;
10634 }
10635
10636 /* Only test the commonly used registers */
10637 static int tg3_test_registers(struct tg3 *tp)
10638 {
10639         int i, is_5705, is_5750;
10640         u32 offset, read_mask, write_mask, val, save_val, read_val;
10641         static struct {
10642                 u16 offset;
10643                 u16 flags;
10644 #define TG3_FL_5705     0x1
10645 #define TG3_FL_NOT_5705 0x2
10646 #define TG3_FL_NOT_5788 0x4
10647 #define TG3_FL_NOT_5750 0x8
10648                 u32 read_mask;
10649                 u32 write_mask;
10650         } reg_tbl[] = {
10651                 /* MAC Control Registers */
10652                 { MAC_MODE, TG3_FL_NOT_5705,
10653                         0x00000000, 0x00ef6f8c },
10654                 { MAC_MODE, TG3_FL_5705,
10655                         0x00000000, 0x01ef6b8c },
10656                 { MAC_STATUS, TG3_FL_NOT_5705,
10657                         0x03800107, 0x00000000 },
10658                 { MAC_STATUS, TG3_FL_5705,
10659                         0x03800100, 0x00000000 },
10660                 { MAC_ADDR_0_HIGH, 0x0000,
10661                         0x00000000, 0x0000ffff },
10662                 { MAC_ADDR_0_LOW, 0x0000,
10663                         0x00000000, 0xffffffff },
10664                 { MAC_RX_MTU_SIZE, 0x0000,
10665                         0x00000000, 0x0000ffff },
10666                 { MAC_TX_MODE, 0x0000,
10667                         0x00000000, 0x00000070 },
10668                 { MAC_TX_LENGTHS, 0x0000,
10669                         0x00000000, 0x00003fff },
10670                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10671                         0x00000000, 0x000007fc },
10672                 { MAC_RX_MODE, TG3_FL_5705,
10673                         0x00000000, 0x000007dc },
10674                 { MAC_HASH_REG_0, 0x0000,
10675                         0x00000000, 0xffffffff },
10676                 { MAC_HASH_REG_1, 0x0000,
10677                         0x00000000, 0xffffffff },
10678                 { MAC_HASH_REG_2, 0x0000,
10679                         0x00000000, 0xffffffff },
10680                 { MAC_HASH_REG_3, 0x0000,
10681                         0x00000000, 0xffffffff },
10682
10683                 /* Receive Data and Receive BD Initiator Control Registers. */
10684                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10685                         0x00000000, 0xffffffff },
10686                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10687                         0x00000000, 0xffffffff },
10688                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10689                         0x00000000, 0x00000003 },
10690                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10691                         0x00000000, 0xffffffff },
10692                 { RCVDBDI_STD_BD+0, 0x0000,
10693                         0x00000000, 0xffffffff },
10694                 { RCVDBDI_STD_BD+4, 0x0000,
10695                         0x00000000, 0xffffffff },
10696                 { RCVDBDI_STD_BD+8, 0x0000,
10697                         0x00000000, 0xffff0002 },
10698                 { RCVDBDI_STD_BD+0xc, 0x0000,
10699                         0x00000000, 0xffffffff },
10700
10701                 /* Receive BD Initiator Control Registers. */
10702                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10703                         0x00000000, 0xffffffff },
10704                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10705                         0x00000000, 0x000003ff },
10706                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10707                         0x00000000, 0xffffffff },
10708
10709                 /* Host Coalescing Control Registers. */
10710                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10711                         0x00000000, 0x00000004 },
10712                 { HOSTCC_MODE, TG3_FL_5705,
10713                         0x00000000, 0x000000f6 },
10714                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10715                         0x00000000, 0xffffffff },
10716                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10717                         0x00000000, 0x000003ff },
10718                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10719                         0x00000000, 0xffffffff },
10720                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10721                         0x00000000, 0x000003ff },
10722                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10723                         0x00000000, 0xffffffff },
10724                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10725                         0x00000000, 0x000000ff },
10726                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10727                         0x00000000, 0xffffffff },
10728                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10729                         0x00000000, 0x000000ff },
10730                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10731                         0x00000000, 0xffffffff },
10732                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10733                         0x00000000, 0xffffffff },
10734                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10735                         0x00000000, 0xffffffff },
10736                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10737                         0x00000000, 0x000000ff },
10738                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10739                         0x00000000, 0xffffffff },
10740                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10741                         0x00000000, 0x000000ff },
10742                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10743                         0x00000000, 0xffffffff },
10744                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10745                         0x00000000, 0xffffffff },
10746                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10747                         0x00000000, 0xffffffff },
10748                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10749                         0x00000000, 0xffffffff },
10750                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10751                         0x00000000, 0xffffffff },
10752                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10753                         0xffffffff, 0x00000000 },
10754                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10755                         0xffffffff, 0x00000000 },
10756
10757                 /* Buffer Manager Control Registers. */
10758                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10759                         0x00000000, 0x007fff80 },
10760                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10761                         0x00000000, 0x007fffff },
10762                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10763                         0x00000000, 0x0000003f },
10764                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10765                         0x00000000, 0x000001ff },
10766                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10767                         0x00000000, 0x000001ff },
10768                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10769                         0xffffffff, 0x00000000 },
10770                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10771                         0xffffffff, 0x00000000 },
10772
10773                 /* Mailbox Registers */
10774                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10775                         0x00000000, 0x000001ff },
10776                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10777                         0x00000000, 0x000001ff },
10778                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10779                         0x00000000, 0x000007ff },
10780                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10781                         0x00000000, 0x000001ff },
10782
10783                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10784         };
10785
10786         is_5705 = is_5750 = 0;
10787         if (tg3_flag(tp, 5705_PLUS)) {
10788                 is_5705 = 1;
10789                 if (tg3_flag(tp, 5750_PLUS))
10790                         is_5750 = 1;
10791         }
10792
10793         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10794                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10795                         continue;
10796
10797                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10798                         continue;
10799
10800                 if (tg3_flag(tp, IS_5788) &&
10801                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10802                         continue;
10803
10804                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10805                         continue;
10806
10807                 offset = (u32) reg_tbl[i].offset;
10808                 read_mask = reg_tbl[i].read_mask;
10809                 write_mask = reg_tbl[i].write_mask;
10810
10811                 /* Save the original register content */
10812                 save_val = tr32(offset);
10813
10814                 /* Determine the read-only value. */
10815                 read_val = save_val & read_mask;
10816
10817                 /* Write zero to the register, then make sure the read-only bits
10818                  * are not changed and the read/write bits are all zeros.
10819                  */
10820                 tw32(offset, 0);
10821
10822                 val = tr32(offset);
10823
10824                 /* Test the read-only and read/write bits. */
10825                 if (((val & read_mask) != read_val) || (val & write_mask))
10826                         goto out;
10827
10828                 /* Write ones to all the bits defined by RdMask and WrMask, then
10829                  * make sure the read-only bits are not changed and the
10830                  * read/write bits are all ones.
10831                  */
10832                 tw32(offset, read_mask | write_mask);
10833
10834                 val = tr32(offset);
10835
10836                 /* Test the read-only bits. */
10837                 if ((val & read_mask) != read_val)
10838                         goto out;
10839
10840                 /* Test the read/write bits. */
10841                 if ((val & write_mask) != write_mask)
10842                         goto out;
10843
10844                 tw32(offset, save_val);
10845         }
10846
10847         return 0;
10848
10849 out:
10850         if (netif_msg_hw(tp))
10851                 netdev_err(tp->dev,
10852                            "Register test failed at offset %x\n", offset);
10853         tw32(offset, save_val);
10854         return -EIO;
10855 }
10856
10857 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10858 {
10859         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10860         int i;
10861         u32 j;
10862
10863         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10864                 for (j = 0; j < len; j += 4) {
10865                         u32 val;
10866
10867                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10868                         tg3_read_mem(tp, offset + j, &val);
10869                         if (val != test_pattern[i])
10870                                 return -EIO;
10871                 }
10872         }
10873         return 0;
10874 }
10875
10876 static int tg3_test_memory(struct tg3 *tp)
10877 {
10878         static struct mem_entry {
10879                 u32 offset;
10880                 u32 len;
10881         } mem_tbl_570x[] = {
10882                 { 0x00000000, 0x00b50},
10883                 { 0x00002000, 0x1c000},
10884                 { 0xffffffff, 0x00000}
10885         }, mem_tbl_5705[] = {
10886                 { 0x00000100, 0x0000c},
10887                 { 0x00000200, 0x00008},
10888                 { 0x00004000, 0x00800},
10889                 { 0x00006000, 0x01000},
10890                 { 0x00008000, 0x02000},
10891                 { 0x00010000, 0x0e000},
10892                 { 0xffffffff, 0x00000}
10893         }, mem_tbl_5755[] = {
10894                 { 0x00000200, 0x00008},
10895                 { 0x00004000, 0x00800},
10896                 { 0x00006000, 0x00800},
10897                 { 0x00008000, 0x02000},
10898                 { 0x00010000, 0x0c000},
10899                 { 0xffffffff, 0x00000}
10900         }, mem_tbl_5906[] = {
10901                 { 0x00000200, 0x00008},
10902                 { 0x00004000, 0x00400},
10903                 { 0x00006000, 0x00400},
10904                 { 0x00008000, 0x01000},
10905                 { 0x00010000, 0x01000},
10906                 { 0xffffffff, 0x00000}
10907         }, mem_tbl_5717[] = {
10908                 { 0x00000200, 0x00008},
10909                 { 0x00010000, 0x0a000},
10910                 { 0x00020000, 0x13c00},
10911                 { 0xffffffff, 0x00000}
10912         }, mem_tbl_57765[] = {
10913                 { 0x00000200, 0x00008},
10914                 { 0x00004000, 0x00800},
10915                 { 0x00006000, 0x09800},
10916                 { 0x00010000, 0x0a000},
10917                 { 0xffffffff, 0x00000}
10918         };
10919         struct mem_entry *mem_tbl;
10920         int err = 0;
10921         int i;
10922
10923         if (tg3_flag(tp, 5717_PLUS))
10924                 mem_tbl = mem_tbl_5717;
10925         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10926                 mem_tbl = mem_tbl_57765;
10927         else if (tg3_flag(tp, 5755_PLUS))
10928                 mem_tbl = mem_tbl_5755;
10929         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10930                 mem_tbl = mem_tbl_5906;
10931         else if (tg3_flag(tp, 5705_PLUS))
10932                 mem_tbl = mem_tbl_5705;
10933         else
10934                 mem_tbl = mem_tbl_570x;
10935
10936         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10937                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10938                 if (err)
10939                         break;
10940         }
10941
10942         return err;
10943 }
10944
10945 #define TG3_MAC_LOOPBACK        0
10946 #define TG3_PHY_LOOPBACK        1
10947 #define TG3_TSO_LOOPBACK        2
10948
10949 #define TG3_TSO_MSS             500
10950
10951 #define TG3_TSO_IP_HDR_LEN      20
10952 #define TG3_TSO_TCP_HDR_LEN     20
10953 #define TG3_TSO_TCP_OPT_LEN     12
10954
10955 static const u8 tg3_tso_header[] = {
10956 0x08, 0x00,
10957 0x45, 0x00, 0x00, 0x00,
10958 0x00, 0x00, 0x40, 0x00,
10959 0x40, 0x06, 0x00, 0x00,
10960 0x0a, 0x00, 0x00, 0x01,
10961 0x0a, 0x00, 0x00, 0x02,
10962 0x0d, 0x00, 0xe0, 0x00,
10963 0x00, 0x00, 0x01, 0x00,
10964 0x00, 0x00, 0x02, 0x00,
10965 0x80, 0x10, 0x10, 0x00,
10966 0x14, 0x09, 0x00, 0x00,
10967 0x01, 0x01, 0x08, 0x0a,
10968 0x11, 0x11, 0x11, 0x11,
10969 0x11, 0x11, 0x11, 0x11,
10970 };
10971
10972 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode)
10973 {
10974         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10975         u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
10976         struct sk_buff *skb, *rx_skb;
10977         u8 *tx_data;
10978         dma_addr_t map;
10979         int num_pkts, tx_len, rx_len, i, err;
10980         struct tg3_rx_buffer_desc *desc;
10981         struct tg3_napi *tnapi, *rnapi;
10982         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10983
10984         tnapi = &tp->napi[0];
10985         rnapi = &tp->napi[0];
10986         if (tp->irq_cnt > 1) {
10987                 if (tg3_flag(tp, ENABLE_RSS))
10988                         rnapi = &tp->napi[1];
10989                 if (tg3_flag(tp, ENABLE_TSS))
10990                         tnapi = &tp->napi[1];
10991         }
10992         coal_now = tnapi->coal_now | rnapi->coal_now;
10993
10994         if (loopback_mode == TG3_MAC_LOOPBACK) {
10995                 /* HW errata - mac loopback fails in some cases on 5780.
10996                  * Normal traffic and PHY loopback are not affected by
10997                  * errata.  Also, the MAC loopback test is deprecated for
10998                  * all newer ASIC revisions.
10999                  */
11000                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11001                     tg3_flag(tp, CPMU_PRESENT))
11002                         return 0;
11003
11004                 mac_mode = tp->mac_mode &
11005                            ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
11006                 mac_mode |= MAC_MODE_PORT_INT_LPBACK;
11007                 if (!tg3_flag(tp, 5705_PLUS))
11008                         mac_mode |= MAC_MODE_LINK_POLARITY;
11009                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
11010                         mac_mode |= MAC_MODE_PORT_MODE_MII;
11011                 else
11012                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
11013                 tw32(MAC_MODE, mac_mode);
11014         } else {
11015                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
11016                         tg3_phy_fet_toggle_apd(tp, false);
11017                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
11018                 } else
11019                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
11020
11021                 tg3_phy_toggle_automdix(tp, 0);
11022
11023                 tg3_writephy(tp, MII_BMCR, val);
11024                 udelay(40);
11025
11026                 mac_mode = tp->mac_mode &
11027                            ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
11028                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
11029                         tg3_writephy(tp, MII_TG3_FET_PTEST,
11030                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
11031                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
11032                         /* The write needs to be flushed for the AC131 */
11033                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11034                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
11035                         mac_mode |= MAC_MODE_PORT_MODE_MII;
11036                 } else
11037                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
11038
11039                 /* reset to prevent losing 1st rx packet intermittently */
11040                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
11041                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
11042                         udelay(10);
11043                         tw32_f(MAC_RX_MODE, tp->rx_mode);
11044                 }
11045                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
11046                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
11047                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
11048                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
11049                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
11050                                 mac_mode |= MAC_MODE_LINK_POLARITY;
11051                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
11052                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
11053                 }
11054                 tw32(MAC_MODE, mac_mode);
11055
11056                 /* Wait for link */
11057                 for (i = 0; i < 100; i++) {
11058                         if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
11059                                 break;
11060                         mdelay(1);
11061                 }
11062         }
11063
11064         err = -EIO;
11065
11066         tx_len = pktsz;
11067         skb = netdev_alloc_skb(tp->dev, tx_len);
11068         if (!skb)
11069                 return -ENOMEM;
11070
11071         tx_data = skb_put(skb, tx_len);
11072         memcpy(tx_data, tp->dev->dev_addr, 6);
11073         memset(tx_data + 6, 0x0, 8);
11074
11075         tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
11076
11077         if (loopback_mode == TG3_TSO_LOOPBACK) {
11078                 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
11079
11080                 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
11081                               TG3_TSO_TCP_OPT_LEN;
11082
11083                 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
11084                        sizeof(tg3_tso_header));
11085                 mss = TG3_TSO_MSS;
11086
11087                 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
11088                 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
11089
11090                 /* Set the total length field in the IP header */
11091                 iph->tot_len = htons((u16)(mss + hdr_len));
11092
11093                 base_flags = (TXD_FLAG_CPU_PRE_DMA |
11094                               TXD_FLAG_CPU_POST_DMA);
11095
11096                 if (tg3_flag(tp, HW_TSO_1) ||
11097                     tg3_flag(tp, HW_TSO_2) ||
11098                     tg3_flag(tp, HW_TSO_3)) {
11099                         struct tcphdr *th;
11100                         val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
11101                         th = (struct tcphdr *)&tx_data[val];
11102                         th->check = 0;
11103                 } else
11104                         base_flags |= TXD_FLAG_TCPUDP_CSUM;
11105
11106                 if (tg3_flag(tp, HW_TSO_3)) {
11107                         mss |= (hdr_len & 0xc) << 12;
11108                         if (hdr_len & 0x10)
11109                                 base_flags |= 0x00000010;
11110                         base_flags |= (hdr_len & 0x3e0) << 5;
11111                 } else if (tg3_flag(tp, HW_TSO_2))
11112                         mss |= hdr_len << 9;
11113                 else if (tg3_flag(tp, HW_TSO_1) ||
11114                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
11115                         mss |= (TG3_TSO_TCP_OPT_LEN << 9);
11116                 } else {
11117                         base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
11118                 }
11119
11120                 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
11121         } else {
11122                 num_pkts = 1;
11123                 data_off = ETH_HLEN;
11124         }
11125
11126         for (i = data_off; i < tx_len; i++)
11127                 tx_data[i] = (u8) (i & 0xff);
11128
11129         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11130         if (pci_dma_mapping_error(tp->pdev, map)) {
11131                 dev_kfree_skb(skb);
11132                 return -EIO;
11133         }
11134
11135         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11136                rnapi->coal_now);
11137
11138         udelay(10);
11139
11140         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11141
11142         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len,
11143                     base_flags, (mss << 1) | 1);
11144
11145         tnapi->tx_prod++;
11146
11147         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11148         tr32_mailbox(tnapi->prodmbox);
11149
11150         udelay(10);
11151
11152         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
11153         for (i = 0; i < 35; i++) {
11154                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11155                        coal_now);
11156
11157                 udelay(10);
11158
11159                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11160                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11161                 if ((tx_idx == tnapi->tx_prod) &&
11162                     (rx_idx == (rx_start_idx + num_pkts)))
11163                         break;
11164         }
11165
11166         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
11167         dev_kfree_skb(skb);
11168
11169         if (tx_idx != tnapi->tx_prod)
11170                 goto out;
11171
11172         if (rx_idx != rx_start_idx + num_pkts)
11173                 goto out;
11174
11175         val = data_off;
11176         while (rx_idx != rx_start_idx) {
11177                 desc = &rnapi->rx_rcb[rx_start_idx++];
11178                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11179                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11180
11181                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11182                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11183                         goto out;
11184
11185                 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
11186                          - ETH_FCS_LEN;
11187
11188                 if (loopback_mode != TG3_TSO_LOOPBACK) {
11189                         if (rx_len != tx_len)
11190                                 goto out;
11191
11192                         if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
11193                                 if (opaque_key != RXD_OPAQUE_RING_STD)
11194                                         goto out;
11195                         } else {
11196                                 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
11197                                         goto out;
11198                         }
11199                 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
11200                            (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
11201                             >> RXD_TCPCSUM_SHIFT != 0xffff) {
11202                         goto out;
11203                 }
11204
11205                 if (opaque_key == RXD_OPAQUE_RING_STD) {
11206                         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11207                         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
11208                                              mapping);
11209                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
11210                         rx_skb = tpr->rx_jmb_buffers[desc_idx].skb;
11211                         map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
11212                                              mapping);
11213                 } else
11214                         goto out;
11215
11216                 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
11217                                             PCI_DMA_FROMDEVICE);
11218
11219                 for (i = data_off; i < rx_len; i++, val++) {
11220                         if (*(rx_skb->data + i) != (u8) (val & 0xff))
11221                                 goto out;
11222                 }
11223         }
11224
11225         err = 0;
11226
11227         /* tg3_free_rings will unmap and free the rx_skb */
11228 out:
11229         return err;
11230 }
11231
11232 #define TG3_STD_LOOPBACK_FAILED         1
11233 #define TG3_JMB_LOOPBACK_FAILED         2
11234 #define TG3_TSO_LOOPBACK_FAILED         4
11235
11236 #define TG3_MAC_LOOPBACK_SHIFT          0
11237 #define TG3_PHY_LOOPBACK_SHIFT          4
11238 #define TG3_LOOPBACK_FAILED             0x00000077
11239
11240 static int tg3_test_loopback(struct tg3 *tp)
11241 {
11242         int err = 0;
11243         u32 eee_cap, cpmuctrl = 0;
11244
11245         if (!netif_running(tp->dev))
11246                 return TG3_LOOPBACK_FAILED;
11247
11248         eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11249         tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11250
11251         err = tg3_reset_hw(tp, 1);
11252         if (err) {
11253                 err = TG3_LOOPBACK_FAILED;
11254                 goto done;
11255         }
11256
11257         if (tg3_flag(tp, ENABLE_RSS)) {
11258                 int i;
11259
11260                 /* Reroute all rx packets to the 1st queue */
11261                 for (i = MAC_RSS_INDIR_TBL_0;
11262                      i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
11263                         tw32(i, 0x0);
11264         }
11265
11266         /* Turn off gphy autopowerdown. */
11267         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11268                 tg3_phy_toggle_apd(tp, false);
11269
11270         if (tg3_flag(tp, CPMU_PRESENT)) {
11271                 int i;
11272                 u32 status;
11273
11274                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11275
11276                 /* Wait for up to 40 microseconds to acquire lock. */
11277                 for (i = 0; i < 4; i++) {
11278                         status = tr32(TG3_CPMU_MUTEX_GNT);
11279                         if (status == CPMU_MUTEX_GNT_DRIVER)
11280                                 break;
11281                         udelay(10);
11282                 }
11283
11284                 if (status != CPMU_MUTEX_GNT_DRIVER) {
11285                         err = TG3_LOOPBACK_FAILED;
11286                         goto done;
11287                 }
11288
11289                 /* Turn off link-based power management. */
11290                 cpmuctrl = tr32(TG3_CPMU_CTRL);
11291                 tw32(TG3_CPMU_CTRL,
11292                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11293                                   CPMU_CTRL_LINK_AWARE_MODE));
11294         }
11295
11296         if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_MAC_LOOPBACK))
11297                 err |= TG3_STD_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT;
11298
11299         if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11300             tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_MAC_LOOPBACK))
11301                 err |= TG3_JMB_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT;
11302
11303         if (tg3_flag(tp, CPMU_PRESENT)) {
11304                 tw32(TG3_CPMU_CTRL, cpmuctrl);
11305
11306                 /* Release the mutex */
11307                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11308         }
11309
11310         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11311             !tg3_flag(tp, USE_PHYLIB)) {
11312                 if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_PHY_LOOPBACK))
11313                         err |= TG3_STD_LOOPBACK_FAILED <<
11314                                TG3_PHY_LOOPBACK_SHIFT;
11315                 if (tg3_flag(tp, TSO_CAPABLE) &&
11316                     tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_TSO_LOOPBACK))
11317                         err |= TG3_TSO_LOOPBACK_FAILED <<
11318                                TG3_PHY_LOOPBACK_SHIFT;
11319                 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11320                     tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_PHY_LOOPBACK))
11321                         err |= TG3_JMB_LOOPBACK_FAILED <<
11322                                TG3_PHY_LOOPBACK_SHIFT;
11323         }
11324
11325         /* Re-enable gphy autopowerdown. */
11326         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11327                 tg3_phy_toggle_apd(tp, true);
11328
11329 done:
11330         tp->phy_flags |= eee_cap;
11331
11332         return err;
11333 }
11334
11335 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11336                           u64 *data)
11337 {
11338         struct tg3 *tp = netdev_priv(dev);
11339
11340         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11341                 tg3_power_up(tp);
11342
11343         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11344
11345         if (tg3_test_nvram(tp) != 0) {
11346                 etest->flags |= ETH_TEST_FL_FAILED;
11347                 data[0] = 1;
11348         }
11349         if (tg3_test_link(tp) != 0) {
11350                 etest->flags |= ETH_TEST_FL_FAILED;
11351                 data[1] = 1;
11352         }
11353         if (etest->flags & ETH_TEST_FL_OFFLINE) {
11354                 int err, err2 = 0, irq_sync = 0;
11355
11356                 if (netif_running(dev)) {
11357                         tg3_phy_stop(tp);
11358                         tg3_netif_stop(tp);
11359                         irq_sync = 1;
11360                 }
11361
11362                 tg3_full_lock(tp, irq_sync);
11363
11364                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11365                 err = tg3_nvram_lock(tp);
11366                 tg3_halt_cpu(tp, RX_CPU_BASE);
11367                 if (!tg3_flag(tp, 5705_PLUS))
11368                         tg3_halt_cpu(tp, TX_CPU_BASE);
11369                 if (!err)
11370                         tg3_nvram_unlock(tp);
11371
11372                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11373                         tg3_phy_reset(tp);
11374
11375                 if (tg3_test_registers(tp) != 0) {
11376                         etest->flags |= ETH_TEST_FL_FAILED;
11377                         data[2] = 1;
11378                 }
11379                 if (tg3_test_memory(tp) != 0) {
11380                         etest->flags |= ETH_TEST_FL_FAILED;
11381                         data[3] = 1;
11382                 }
11383                 if ((data[4] = tg3_test_loopback(tp)) != 0)
11384                         etest->flags |= ETH_TEST_FL_FAILED;
11385
11386                 tg3_full_unlock(tp);
11387
11388                 if (tg3_test_interrupt(tp) != 0) {
11389                         etest->flags |= ETH_TEST_FL_FAILED;
11390                         data[5] = 1;
11391                 }
11392
11393                 tg3_full_lock(tp, 0);
11394
11395                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11396                 if (netif_running(dev)) {
11397                         tg3_flag_set(tp, INIT_COMPLETE);
11398                         err2 = tg3_restart_hw(tp, 1);
11399                         if (!err2)
11400                                 tg3_netif_start(tp);
11401                 }
11402
11403                 tg3_full_unlock(tp);
11404
11405                 if (irq_sync && !err2)
11406                         tg3_phy_start(tp);
11407         }
11408         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11409                 tg3_power_down(tp);
11410
11411 }
11412
11413 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11414 {
11415         struct mii_ioctl_data *data = if_mii(ifr);
11416         struct tg3 *tp = netdev_priv(dev);
11417         int err;
11418
11419         if (tg3_flag(tp, USE_PHYLIB)) {
11420                 struct phy_device *phydev;
11421                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11422                         return -EAGAIN;
11423                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11424                 return phy_mii_ioctl(phydev, ifr, cmd);
11425         }
11426
11427         switch (cmd) {
11428         case SIOCGMIIPHY:
11429                 data->phy_id = tp->phy_addr;
11430
11431                 /* fallthru */
11432         case SIOCGMIIREG: {
11433                 u32 mii_regval;
11434
11435                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11436                         break;                  /* We have no PHY */
11437
11438                 if (!netif_running(dev))
11439                         return -EAGAIN;
11440
11441                 spin_lock_bh(&tp->lock);
11442                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11443                 spin_unlock_bh(&tp->lock);
11444
11445                 data->val_out = mii_regval;
11446
11447                 return err;
11448         }
11449
11450         case SIOCSMIIREG:
11451                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11452                         break;                  /* We have no PHY */
11453
11454                 if (!netif_running(dev))
11455                         return -EAGAIN;
11456
11457                 spin_lock_bh(&tp->lock);
11458                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11459                 spin_unlock_bh(&tp->lock);
11460
11461                 return err;
11462
11463         default:
11464                 /* do nothing */
11465                 break;
11466         }
11467         return -EOPNOTSUPP;
11468 }
11469
11470 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11471 {
11472         struct tg3 *tp = netdev_priv(dev);
11473
11474         memcpy(ec, &tp->coal, sizeof(*ec));
11475         return 0;
11476 }
11477
11478 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11479 {
11480         struct tg3 *tp = netdev_priv(dev);
11481         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11482         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11483
11484         if (!tg3_flag(tp, 5705_PLUS)) {
11485                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11486                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11487                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11488                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11489         }
11490
11491         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11492             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11493             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11494             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11495             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11496             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11497             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11498             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11499             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11500             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11501                 return -EINVAL;
11502
11503         /* No rx interrupts will be generated if both are zero */
11504         if ((ec->rx_coalesce_usecs == 0) &&
11505             (ec->rx_max_coalesced_frames == 0))
11506                 return -EINVAL;
11507
11508         /* No tx interrupts will be generated if both are zero */
11509         if ((ec->tx_coalesce_usecs == 0) &&
11510             (ec->tx_max_coalesced_frames == 0))
11511                 return -EINVAL;
11512
11513         /* Only copy relevant parameters, ignore all others. */
11514         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11515         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11516         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11517         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11518         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11519         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11520         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11521         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11522         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11523
11524         if (netif_running(dev)) {
11525                 tg3_full_lock(tp, 0);
11526                 __tg3_set_coalesce(tp, &tp->coal);
11527                 tg3_full_unlock(tp);
11528         }
11529         return 0;
11530 }
11531
11532 static const struct ethtool_ops tg3_ethtool_ops = {
11533         .get_settings           = tg3_get_settings,
11534         .set_settings           = tg3_set_settings,
11535         .get_drvinfo            = tg3_get_drvinfo,
11536         .get_regs_len           = tg3_get_regs_len,
11537         .get_regs               = tg3_get_regs,
11538         .get_wol                = tg3_get_wol,
11539         .set_wol                = tg3_set_wol,
11540         .get_msglevel           = tg3_get_msglevel,
11541         .set_msglevel           = tg3_set_msglevel,
11542         .nway_reset             = tg3_nway_reset,
11543         .get_link               = ethtool_op_get_link,
11544         .get_eeprom_len         = tg3_get_eeprom_len,
11545         .get_eeprom             = tg3_get_eeprom,
11546         .set_eeprom             = tg3_set_eeprom,
11547         .get_ringparam          = tg3_get_ringparam,
11548         .set_ringparam          = tg3_set_ringparam,
11549         .get_pauseparam         = tg3_get_pauseparam,
11550         .set_pauseparam         = tg3_set_pauseparam,
11551         .self_test              = tg3_self_test,
11552         .get_strings            = tg3_get_strings,
11553         .set_phys_id            = tg3_set_phys_id,
11554         .get_ethtool_stats      = tg3_get_ethtool_stats,
11555         .get_coalesce           = tg3_get_coalesce,
11556         .set_coalesce           = tg3_set_coalesce,
11557         .get_sset_count         = tg3_get_sset_count,
11558 };
11559
11560 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11561 {
11562         u32 cursize, val, magic;
11563
11564         tp->nvram_size = EEPROM_CHIP_SIZE;
11565
11566         if (tg3_nvram_read(tp, 0, &magic) != 0)
11567                 return;
11568
11569         if ((magic != TG3_EEPROM_MAGIC) &&
11570             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11571             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11572                 return;
11573
11574         /*
11575          * Size the chip by reading offsets at increasing powers of two.
11576          * When we encounter our validation signature, we know the addressing
11577          * has wrapped around, and thus have our chip size.
11578          */
11579         cursize = 0x10;
11580
11581         while (cursize < tp->nvram_size) {
11582                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11583                         return;
11584
11585                 if (val == magic)
11586                         break;
11587
11588                 cursize <<= 1;
11589         }
11590
11591         tp->nvram_size = cursize;
11592 }
11593
11594 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11595 {
11596         u32 val;
11597
11598         if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
11599                 return;
11600
11601         /* Selfboot format */
11602         if (val != TG3_EEPROM_MAGIC) {
11603                 tg3_get_eeprom_size(tp);
11604                 return;
11605         }
11606
11607         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11608                 if (val != 0) {
11609                         /* This is confusing.  We want to operate on the
11610                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11611                          * call will read from NVRAM and byteswap the data
11612                          * according to the byteswapping settings for all
11613                          * other register accesses.  This ensures the data we
11614                          * want will always reside in the lower 16-bits.
11615                          * However, the data in NVRAM is in LE format, which
11616                          * means the data from the NVRAM read will always be
11617                          * opposite the endianness of the CPU.  The 16-bit
11618                          * byteswap then brings the data to CPU endianness.
11619                          */
11620                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11621                         return;
11622                 }
11623         }
11624         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11625 }
11626
11627 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11628 {
11629         u32 nvcfg1;
11630
11631         nvcfg1 = tr32(NVRAM_CFG1);
11632         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11633                 tg3_flag_set(tp, FLASH);
11634         } else {
11635                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11636                 tw32(NVRAM_CFG1, nvcfg1);
11637         }
11638
11639         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11640             tg3_flag(tp, 5780_CLASS)) {
11641                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11642                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11643                         tp->nvram_jedecnum = JEDEC_ATMEL;
11644                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11645                         tg3_flag_set(tp, NVRAM_BUFFERED);
11646                         break;
11647                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11648                         tp->nvram_jedecnum = JEDEC_ATMEL;
11649                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11650                         break;
11651                 case FLASH_VENDOR_ATMEL_EEPROM:
11652                         tp->nvram_jedecnum = JEDEC_ATMEL;
11653                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11654                         tg3_flag_set(tp, NVRAM_BUFFERED);
11655                         break;
11656                 case FLASH_VENDOR_ST:
11657                         tp->nvram_jedecnum = JEDEC_ST;
11658                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11659                         tg3_flag_set(tp, NVRAM_BUFFERED);
11660                         break;
11661                 case FLASH_VENDOR_SAIFUN:
11662                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11663                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11664                         break;
11665                 case FLASH_VENDOR_SST_SMALL:
11666                 case FLASH_VENDOR_SST_LARGE:
11667                         tp->nvram_jedecnum = JEDEC_SST;
11668                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11669                         break;
11670                 }
11671         } else {
11672                 tp->nvram_jedecnum = JEDEC_ATMEL;
11673                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11674                 tg3_flag_set(tp, NVRAM_BUFFERED);
11675         }
11676 }
11677
11678 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11679 {
11680         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11681         case FLASH_5752PAGE_SIZE_256:
11682                 tp->nvram_pagesize = 256;
11683                 break;
11684         case FLASH_5752PAGE_SIZE_512:
11685                 tp->nvram_pagesize = 512;
11686                 break;
11687         case FLASH_5752PAGE_SIZE_1K:
11688                 tp->nvram_pagesize = 1024;
11689                 break;
11690         case FLASH_5752PAGE_SIZE_2K:
11691                 tp->nvram_pagesize = 2048;
11692                 break;
11693         case FLASH_5752PAGE_SIZE_4K:
11694                 tp->nvram_pagesize = 4096;
11695                 break;
11696         case FLASH_5752PAGE_SIZE_264:
11697                 tp->nvram_pagesize = 264;
11698                 break;
11699         case FLASH_5752PAGE_SIZE_528:
11700                 tp->nvram_pagesize = 528;
11701                 break;
11702         }
11703 }
11704
11705 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11706 {
11707         u32 nvcfg1;
11708
11709         nvcfg1 = tr32(NVRAM_CFG1);
11710
11711         /* NVRAM protection for TPM */
11712         if (nvcfg1 & (1 << 27))
11713                 tg3_flag_set(tp, PROTECTED_NVRAM);
11714
11715         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11716         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11717         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11718                 tp->nvram_jedecnum = JEDEC_ATMEL;
11719                 tg3_flag_set(tp, NVRAM_BUFFERED);
11720                 break;
11721         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11722                 tp->nvram_jedecnum = JEDEC_ATMEL;
11723                 tg3_flag_set(tp, NVRAM_BUFFERED);
11724                 tg3_flag_set(tp, FLASH);
11725                 break;
11726         case FLASH_5752VENDOR_ST_M45PE10:
11727         case FLASH_5752VENDOR_ST_M45PE20:
11728         case FLASH_5752VENDOR_ST_M45PE40:
11729                 tp->nvram_jedecnum = JEDEC_ST;
11730                 tg3_flag_set(tp, NVRAM_BUFFERED);
11731                 tg3_flag_set(tp, FLASH);
11732                 break;
11733         }
11734
11735         if (tg3_flag(tp, FLASH)) {
11736                 tg3_nvram_get_pagesize(tp, nvcfg1);
11737         } else {
11738                 /* For eeprom, set pagesize to maximum eeprom size */
11739                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11740
11741                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11742                 tw32(NVRAM_CFG1, nvcfg1);
11743         }
11744 }
11745
11746 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11747 {
11748         u32 nvcfg1, protect = 0;
11749
11750         nvcfg1 = tr32(NVRAM_CFG1);
11751
11752         /* NVRAM protection for TPM */
11753         if (nvcfg1 & (1 << 27)) {
11754                 tg3_flag_set(tp, PROTECTED_NVRAM);
11755                 protect = 1;
11756         }
11757
11758         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11759         switch (nvcfg1) {
11760         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11761         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11762         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11763         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11764                 tp->nvram_jedecnum = JEDEC_ATMEL;
11765                 tg3_flag_set(tp, NVRAM_BUFFERED);
11766                 tg3_flag_set(tp, FLASH);
11767                 tp->nvram_pagesize = 264;
11768                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11769                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11770                         tp->nvram_size = (protect ? 0x3e200 :
11771                                           TG3_NVRAM_SIZE_512KB);
11772                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11773                         tp->nvram_size = (protect ? 0x1f200 :
11774                                           TG3_NVRAM_SIZE_256KB);
11775                 else
11776                         tp->nvram_size = (protect ? 0x1f200 :
11777                                           TG3_NVRAM_SIZE_128KB);
11778                 break;
11779         case FLASH_5752VENDOR_ST_M45PE10:
11780         case FLASH_5752VENDOR_ST_M45PE20:
11781         case FLASH_5752VENDOR_ST_M45PE40:
11782                 tp->nvram_jedecnum = JEDEC_ST;
11783                 tg3_flag_set(tp, NVRAM_BUFFERED);
11784                 tg3_flag_set(tp, FLASH);
11785                 tp->nvram_pagesize = 256;
11786                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11787                         tp->nvram_size = (protect ?
11788                                           TG3_NVRAM_SIZE_64KB :
11789                                           TG3_NVRAM_SIZE_128KB);
11790                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11791                         tp->nvram_size = (protect ?
11792                                           TG3_NVRAM_SIZE_64KB :
11793                                           TG3_NVRAM_SIZE_256KB);
11794                 else
11795                         tp->nvram_size = (protect ?
11796                                           TG3_NVRAM_SIZE_128KB :
11797                                           TG3_NVRAM_SIZE_512KB);
11798                 break;
11799         }
11800 }
11801
11802 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11803 {
11804         u32 nvcfg1;
11805
11806         nvcfg1 = tr32(NVRAM_CFG1);
11807
11808         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11809         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11810         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11811         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11812         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11813                 tp->nvram_jedecnum = JEDEC_ATMEL;
11814                 tg3_flag_set(tp, NVRAM_BUFFERED);
11815                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11816
11817                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11818                 tw32(NVRAM_CFG1, nvcfg1);
11819                 break;
11820         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11821         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11822         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11823         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11824                 tp->nvram_jedecnum = JEDEC_ATMEL;
11825                 tg3_flag_set(tp, NVRAM_BUFFERED);
11826                 tg3_flag_set(tp, FLASH);
11827                 tp->nvram_pagesize = 264;
11828                 break;
11829         case FLASH_5752VENDOR_ST_M45PE10:
11830         case FLASH_5752VENDOR_ST_M45PE20:
11831         case FLASH_5752VENDOR_ST_M45PE40:
11832                 tp->nvram_jedecnum = JEDEC_ST;
11833                 tg3_flag_set(tp, NVRAM_BUFFERED);
11834                 tg3_flag_set(tp, FLASH);
11835                 tp->nvram_pagesize = 256;
11836                 break;
11837         }
11838 }
11839
11840 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11841 {
11842         u32 nvcfg1, protect = 0;
11843
11844         nvcfg1 = tr32(NVRAM_CFG1);
11845
11846         /* NVRAM protection for TPM */
11847         if (nvcfg1 & (1 << 27)) {
11848                 tg3_flag_set(tp, PROTECTED_NVRAM);
11849                 protect = 1;
11850         }
11851
11852         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11853         switch (nvcfg1) {
11854         case FLASH_5761VENDOR_ATMEL_ADB021D:
11855         case FLASH_5761VENDOR_ATMEL_ADB041D:
11856         case FLASH_5761VENDOR_ATMEL_ADB081D:
11857         case FLASH_5761VENDOR_ATMEL_ADB161D:
11858         case FLASH_5761VENDOR_ATMEL_MDB021D:
11859         case FLASH_5761VENDOR_ATMEL_MDB041D:
11860         case FLASH_5761VENDOR_ATMEL_MDB081D:
11861         case FLASH_5761VENDOR_ATMEL_MDB161D:
11862                 tp->nvram_jedecnum = JEDEC_ATMEL;
11863                 tg3_flag_set(tp, NVRAM_BUFFERED);
11864                 tg3_flag_set(tp, FLASH);
11865                 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
11866                 tp->nvram_pagesize = 256;
11867                 break;
11868         case FLASH_5761VENDOR_ST_A_M45PE20:
11869         case FLASH_5761VENDOR_ST_A_M45PE40:
11870         case FLASH_5761VENDOR_ST_A_M45PE80:
11871         case FLASH_5761VENDOR_ST_A_M45PE16:
11872         case FLASH_5761VENDOR_ST_M_M45PE20:
11873         case FLASH_5761VENDOR_ST_M_M45PE40:
11874         case FLASH_5761VENDOR_ST_M_M45PE80:
11875         case FLASH_5761VENDOR_ST_M_M45PE16:
11876                 tp->nvram_jedecnum = JEDEC_ST;
11877                 tg3_flag_set(tp, NVRAM_BUFFERED);
11878                 tg3_flag_set(tp, FLASH);
11879                 tp->nvram_pagesize = 256;
11880                 break;
11881         }
11882
11883         if (protect) {
11884                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11885         } else {
11886                 switch (nvcfg1) {
11887                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11888                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11889                 case FLASH_5761VENDOR_ST_A_M45PE16:
11890                 case FLASH_5761VENDOR_ST_M_M45PE16:
11891                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11892                         break;
11893                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11894                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11895                 case FLASH_5761VENDOR_ST_A_M45PE80:
11896                 case FLASH_5761VENDOR_ST_M_M45PE80:
11897                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11898                         break;
11899                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11900                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11901                 case FLASH_5761VENDOR_ST_A_M45PE40:
11902                 case FLASH_5761VENDOR_ST_M_M45PE40:
11903                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11904                         break;
11905                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11906                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11907                 case FLASH_5761VENDOR_ST_A_M45PE20:
11908                 case FLASH_5761VENDOR_ST_M_M45PE20:
11909                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11910                         break;
11911                 }
11912         }
11913 }
11914
11915 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11916 {
11917         tp->nvram_jedecnum = JEDEC_ATMEL;
11918         tg3_flag_set(tp, NVRAM_BUFFERED);
11919         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11920 }
11921
11922 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11923 {
11924         u32 nvcfg1;
11925
11926         nvcfg1 = tr32(NVRAM_CFG1);
11927
11928         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11929         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11930         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11931                 tp->nvram_jedecnum = JEDEC_ATMEL;
11932                 tg3_flag_set(tp, NVRAM_BUFFERED);
11933                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11934
11935                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11936                 tw32(NVRAM_CFG1, nvcfg1);
11937                 return;
11938         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11939         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11940         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11941         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11942         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11943         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11944         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11945                 tp->nvram_jedecnum = JEDEC_ATMEL;
11946                 tg3_flag_set(tp, NVRAM_BUFFERED);
11947                 tg3_flag_set(tp, FLASH);
11948
11949                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11950                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11951                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11952                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11953                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11954                         break;
11955                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11956                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11957                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11958                         break;
11959                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11960                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11961                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11962                         break;
11963                 }
11964                 break;
11965         case FLASH_5752VENDOR_ST_M45PE10:
11966         case FLASH_5752VENDOR_ST_M45PE20:
11967         case FLASH_5752VENDOR_ST_M45PE40:
11968                 tp->nvram_jedecnum = JEDEC_ST;
11969                 tg3_flag_set(tp, NVRAM_BUFFERED);
11970                 tg3_flag_set(tp, FLASH);
11971
11972                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11973                 case FLASH_5752VENDOR_ST_M45PE10:
11974                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11975                         break;
11976                 case FLASH_5752VENDOR_ST_M45PE20:
11977                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11978                         break;
11979                 case FLASH_5752VENDOR_ST_M45PE40:
11980                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11981                         break;
11982                 }
11983                 break;
11984         default:
11985                 tg3_flag_set(tp, NO_NVRAM);
11986                 return;
11987         }
11988
11989         tg3_nvram_get_pagesize(tp, nvcfg1);
11990         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11991                 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
11992 }
11993
11994
11995 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11996 {
11997         u32 nvcfg1;
11998
11999         nvcfg1 = tr32(NVRAM_CFG1);
12000
12001         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12002         case FLASH_5717VENDOR_ATMEL_EEPROM:
12003         case FLASH_5717VENDOR_MICRO_EEPROM:
12004                 tp->nvram_jedecnum = JEDEC_ATMEL;
12005                 tg3_flag_set(tp, NVRAM_BUFFERED);
12006                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12007
12008                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12009                 tw32(NVRAM_CFG1, nvcfg1);
12010                 return;
12011         case FLASH_5717VENDOR_ATMEL_MDB011D:
12012         case FLASH_5717VENDOR_ATMEL_ADB011B:
12013         case FLASH_5717VENDOR_ATMEL_ADB011D:
12014         case FLASH_5717VENDOR_ATMEL_MDB021D:
12015         case FLASH_5717VENDOR_ATMEL_ADB021B:
12016         case FLASH_5717VENDOR_ATMEL_ADB021D:
12017         case FLASH_5717VENDOR_ATMEL_45USPT:
12018                 tp->nvram_jedecnum = JEDEC_ATMEL;
12019                 tg3_flag_set(tp, NVRAM_BUFFERED);
12020                 tg3_flag_set(tp, FLASH);
12021
12022                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12023                 case FLASH_5717VENDOR_ATMEL_MDB021D:
12024                         /* Detect size with tg3_nvram_get_size() */
12025                         break;
12026                 case FLASH_5717VENDOR_ATMEL_ADB021B:
12027                 case FLASH_5717VENDOR_ATMEL_ADB021D:
12028                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12029                         break;
12030                 default:
12031                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12032                         break;
12033                 }
12034                 break;
12035         case FLASH_5717VENDOR_ST_M_M25PE10:
12036         case FLASH_5717VENDOR_ST_A_M25PE10:
12037         case FLASH_5717VENDOR_ST_M_M45PE10:
12038         case FLASH_5717VENDOR_ST_A_M45PE10:
12039         case FLASH_5717VENDOR_ST_M_M25PE20:
12040         case FLASH_5717VENDOR_ST_A_M25PE20:
12041         case FLASH_5717VENDOR_ST_M_M45PE20:
12042         case FLASH_5717VENDOR_ST_A_M45PE20:
12043         case FLASH_5717VENDOR_ST_25USPT:
12044         case FLASH_5717VENDOR_ST_45USPT:
12045                 tp->nvram_jedecnum = JEDEC_ST;
12046                 tg3_flag_set(tp, NVRAM_BUFFERED);
12047                 tg3_flag_set(tp, FLASH);
12048
12049                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12050                 case FLASH_5717VENDOR_ST_M_M25PE20:
12051                 case FLASH_5717VENDOR_ST_M_M45PE20:
12052                         /* Detect size with tg3_nvram_get_size() */
12053                         break;
12054                 case FLASH_5717VENDOR_ST_A_M25PE20:
12055                 case FLASH_5717VENDOR_ST_A_M45PE20:
12056                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12057                         break;
12058                 default:
12059                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12060                         break;
12061                 }
12062                 break;
12063         default:
12064                 tg3_flag_set(tp, NO_NVRAM);
12065                 return;
12066         }
12067
12068         tg3_nvram_get_pagesize(tp, nvcfg1);
12069         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12070                 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12071 }
12072
12073 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12074 {
12075         u32 nvcfg1, nvmpinstrp;
12076
12077         nvcfg1 = tr32(NVRAM_CFG1);
12078         nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
12079
12080         switch (nvmpinstrp) {
12081         case FLASH_5720_EEPROM_HD:
12082         case FLASH_5720_EEPROM_LD:
12083                 tp->nvram_jedecnum = JEDEC_ATMEL;
12084                 tg3_flag_set(tp, NVRAM_BUFFERED);
12085
12086                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12087                 tw32(NVRAM_CFG1, nvcfg1);
12088                 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
12089                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12090                 else
12091                         tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
12092                 return;
12093         case FLASH_5720VENDOR_M_ATMEL_DB011D:
12094         case FLASH_5720VENDOR_A_ATMEL_DB011B:
12095         case FLASH_5720VENDOR_A_ATMEL_DB011D:
12096         case FLASH_5720VENDOR_M_ATMEL_DB021D:
12097         case FLASH_5720VENDOR_A_ATMEL_DB021B:
12098         case FLASH_5720VENDOR_A_ATMEL_DB021D:
12099         case FLASH_5720VENDOR_M_ATMEL_DB041D:
12100         case FLASH_5720VENDOR_A_ATMEL_DB041B:
12101         case FLASH_5720VENDOR_A_ATMEL_DB041D:
12102         case FLASH_5720VENDOR_M_ATMEL_DB081D:
12103         case FLASH_5720VENDOR_A_ATMEL_DB081D:
12104         case FLASH_5720VENDOR_ATMEL_45USPT:
12105                 tp->nvram_jedecnum = JEDEC_ATMEL;
12106                 tg3_flag_set(tp, NVRAM_BUFFERED);
12107                 tg3_flag_set(tp, FLASH);
12108
12109                 switch (nvmpinstrp) {
12110                 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12111                 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12112                 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12113                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12114                         break;
12115                 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12116                 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12117                 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12118                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12119                         break;
12120                 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12121                 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12122                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12123                         break;
12124                 default:
12125                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12126                         break;
12127                 }
12128                 break;
12129         case FLASH_5720VENDOR_M_ST_M25PE10:
12130         case FLASH_5720VENDOR_M_ST_M45PE10:
12131         case FLASH_5720VENDOR_A_ST_M25PE10:
12132         case FLASH_5720VENDOR_A_ST_M45PE10:
12133         case FLASH_5720VENDOR_M_ST_M25PE20:
12134         case FLASH_5720VENDOR_M_ST_M45PE20:
12135         case FLASH_5720VENDOR_A_ST_M25PE20:
12136         case FLASH_5720VENDOR_A_ST_M45PE20:
12137         case FLASH_5720VENDOR_M_ST_M25PE40:
12138         case FLASH_5720VENDOR_M_ST_M45PE40:
12139         case FLASH_5720VENDOR_A_ST_M25PE40:
12140         case FLASH_5720VENDOR_A_ST_M45PE40:
12141         case FLASH_5720VENDOR_M_ST_M25PE80:
12142         case FLASH_5720VENDOR_M_ST_M45PE80:
12143         case FLASH_5720VENDOR_A_ST_M25PE80:
12144         case FLASH_5720VENDOR_A_ST_M45PE80:
12145         case FLASH_5720VENDOR_ST_25USPT:
12146         case FLASH_5720VENDOR_ST_45USPT:
12147                 tp->nvram_jedecnum = JEDEC_ST;
12148                 tg3_flag_set(tp, NVRAM_BUFFERED);
12149                 tg3_flag_set(tp, FLASH);
12150
12151                 switch (nvmpinstrp) {
12152                 case FLASH_5720VENDOR_M_ST_M25PE20:
12153                 case FLASH_5720VENDOR_M_ST_M45PE20:
12154                 case FLASH_5720VENDOR_A_ST_M25PE20:
12155                 case FLASH_5720VENDOR_A_ST_M45PE20:
12156                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12157                         break;
12158                 case FLASH_5720VENDOR_M_ST_M25PE40:
12159                 case FLASH_5720VENDOR_M_ST_M45PE40:
12160                 case FLASH_5720VENDOR_A_ST_M25PE40:
12161                 case FLASH_5720VENDOR_A_ST_M45PE40:
12162                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12163                         break;
12164                 case FLASH_5720VENDOR_M_ST_M25PE80:
12165                 case FLASH_5720VENDOR_M_ST_M45PE80:
12166                 case FLASH_5720VENDOR_A_ST_M25PE80:
12167                 case FLASH_5720VENDOR_A_ST_M45PE80:
12168                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12169                         break;
12170                 default:
12171                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12172                         break;
12173                 }
12174                 break;
12175         default:
12176                 tg3_flag_set(tp, NO_NVRAM);
12177                 return;
12178         }
12179
12180         tg3_nvram_get_pagesize(tp, nvcfg1);
12181         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12182                 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12183 }
12184
12185 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12186 static void __devinit tg3_nvram_init(struct tg3 *tp)
12187 {
12188         tw32_f(GRC_EEPROM_ADDR,
12189              (EEPROM_ADDR_FSM_RESET |
12190               (EEPROM_DEFAULT_CLOCK_PERIOD <<
12191                EEPROM_ADDR_CLKPERD_SHIFT)));
12192
12193         msleep(1);
12194
12195         /* Enable seeprom accesses. */
12196         tw32_f(GRC_LOCAL_CTRL,
12197              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12198         udelay(100);
12199
12200         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12201             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12202                 tg3_flag_set(tp, NVRAM);
12203
12204                 if (tg3_nvram_lock(tp)) {
12205                         netdev_warn(tp->dev,
12206                                     "Cannot get nvram lock, %s failed\n",
12207                                     __func__);
12208                         return;
12209                 }
12210                 tg3_enable_nvram_access(tp);
12211
12212                 tp->nvram_size = 0;
12213
12214                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12215                         tg3_get_5752_nvram_info(tp);
12216                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12217                         tg3_get_5755_nvram_info(tp);
12218                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12219                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12220                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12221                         tg3_get_5787_nvram_info(tp);
12222                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12223                         tg3_get_5761_nvram_info(tp);
12224                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12225                         tg3_get_5906_nvram_info(tp);
12226                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12227                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12228                         tg3_get_57780_nvram_info(tp);
12229                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12230                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
12231                         tg3_get_5717_nvram_info(tp);
12232                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12233                         tg3_get_5720_nvram_info(tp);
12234                 else
12235                         tg3_get_nvram_info(tp);
12236
12237                 if (tp->nvram_size == 0)
12238                         tg3_get_nvram_size(tp);
12239
12240                 tg3_disable_nvram_access(tp);
12241                 tg3_nvram_unlock(tp);
12242
12243         } else {
12244                 tg3_flag_clear(tp, NVRAM);
12245                 tg3_flag_clear(tp, NVRAM_BUFFERED);
12246
12247                 tg3_get_eeprom_size(tp);
12248         }
12249 }
12250
12251 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
12252                                     u32 offset, u32 len, u8 *buf)
12253 {
12254         int i, j, rc = 0;
12255         u32 val;
12256
12257         for (i = 0; i < len; i += 4) {
12258                 u32 addr;
12259                 __be32 data;
12260
12261                 addr = offset + i;
12262
12263                 memcpy(&data, buf + i, 4);
12264
12265                 /*
12266                  * The SEEPROM interface expects the data to always be opposite
12267                  * the native endian format.  We accomplish this by reversing
12268                  * all the operations that would have been performed on the
12269                  * data from a call to tg3_nvram_read_be32().
12270                  */
12271                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
12272
12273                 val = tr32(GRC_EEPROM_ADDR);
12274                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
12275
12276                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
12277                         EEPROM_ADDR_READ);
12278                 tw32(GRC_EEPROM_ADDR, val |
12279                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
12280                         (addr & EEPROM_ADDR_ADDR_MASK) |
12281                         EEPROM_ADDR_START |
12282                         EEPROM_ADDR_WRITE);
12283
12284                 for (j = 0; j < 1000; j++) {
12285                         val = tr32(GRC_EEPROM_ADDR);
12286
12287                         if (val & EEPROM_ADDR_COMPLETE)
12288                                 break;
12289                         msleep(1);
12290                 }
12291                 if (!(val & EEPROM_ADDR_COMPLETE)) {
12292                         rc = -EBUSY;
12293                         break;
12294                 }
12295         }
12296
12297         return rc;
12298 }
12299
12300 /* offset and length are dword aligned */
12301 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12302                 u8 *buf)
12303 {
12304         int ret = 0;
12305         u32 pagesize = tp->nvram_pagesize;
12306         u32 pagemask = pagesize - 1;
12307         u32 nvram_cmd;
12308         u8 *tmp;
12309
12310         tmp = kmalloc(pagesize, GFP_KERNEL);
12311         if (tmp == NULL)
12312                 return -ENOMEM;
12313
12314         while (len) {
12315                 int j;
12316                 u32 phy_addr, page_off, size;
12317
12318                 phy_addr = offset & ~pagemask;
12319
12320                 for (j = 0; j < pagesize; j += 4) {
12321                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
12322                                                   (__be32 *) (tmp + j));
12323                         if (ret)
12324                                 break;
12325                 }
12326                 if (ret)
12327                         break;
12328
12329                 page_off = offset & pagemask;
12330                 size = pagesize;
12331                 if (len < size)
12332                         size = len;
12333
12334                 len -= size;
12335
12336                 memcpy(tmp + page_off, buf, size);
12337
12338                 offset = offset + (pagesize - page_off);
12339
12340                 tg3_enable_nvram_access(tp);
12341
12342                 /*
12343                  * Before we can erase the flash page, we need
12344                  * to issue a special "write enable" command.
12345                  */
12346                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12347
12348                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12349                         break;
12350
12351                 /* Erase the target page */
12352                 tw32(NVRAM_ADDR, phy_addr);
12353
12354                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12355                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12356
12357                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12358                         break;
12359
12360                 /* Issue another write enable to start the write. */
12361                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12362
12363                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12364                         break;
12365
12366                 for (j = 0; j < pagesize; j += 4) {
12367                         __be32 data;
12368
12369                         data = *((__be32 *) (tmp + j));
12370
12371                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
12372
12373                         tw32(NVRAM_ADDR, phy_addr + j);
12374
12375                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12376                                 NVRAM_CMD_WR;
12377
12378                         if (j == 0)
12379                                 nvram_cmd |= NVRAM_CMD_FIRST;
12380                         else if (j == (pagesize - 4))
12381                                 nvram_cmd |= NVRAM_CMD_LAST;
12382
12383                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12384                                 break;
12385                 }
12386                 if (ret)
12387                         break;
12388         }
12389
12390         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12391         tg3_nvram_exec_cmd(tp, nvram_cmd);
12392
12393         kfree(tmp);
12394
12395         return ret;
12396 }
12397
12398 /* offset and length are dword aligned */
12399 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12400                 u8 *buf)
12401 {
12402         int i, ret = 0;
12403
12404         for (i = 0; i < len; i += 4, offset += 4) {
12405                 u32 page_off, phy_addr, nvram_cmd;
12406                 __be32 data;
12407
12408                 memcpy(&data, buf + i, 4);
12409                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12410
12411                 page_off = offset % tp->nvram_pagesize;
12412
12413                 phy_addr = tg3_nvram_phys_addr(tp, offset);
12414
12415                 tw32(NVRAM_ADDR, phy_addr);
12416
12417                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12418
12419                 if (page_off == 0 || i == 0)
12420                         nvram_cmd |= NVRAM_CMD_FIRST;
12421                 if (page_off == (tp->nvram_pagesize - 4))
12422                         nvram_cmd |= NVRAM_CMD_LAST;
12423
12424                 if (i == (len - 4))
12425                         nvram_cmd |= NVRAM_CMD_LAST;
12426
12427                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12428                     !tg3_flag(tp, 5755_PLUS) &&
12429                     (tp->nvram_jedecnum == JEDEC_ST) &&
12430                     (nvram_cmd & NVRAM_CMD_FIRST)) {
12431
12432                         if ((ret = tg3_nvram_exec_cmd(tp,
12433                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12434                                 NVRAM_CMD_DONE)))
12435
12436                                 break;
12437                 }
12438                 if (!tg3_flag(tp, FLASH)) {
12439                         /* We always do complete word writes to eeprom. */
12440                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12441                 }
12442
12443                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12444                         break;
12445         }
12446         return ret;
12447 }
12448
12449 /* offset and length are dword aligned */
12450 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12451 {
12452         int ret;
12453
12454         if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12455                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12456                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
12457                 udelay(40);
12458         }
12459
12460         if (!tg3_flag(tp, NVRAM)) {
12461                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12462         } else {
12463                 u32 grc_mode;
12464
12465                 ret = tg3_nvram_lock(tp);
12466                 if (ret)
12467                         return ret;
12468
12469                 tg3_enable_nvram_access(tp);
12470                 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
12471                         tw32(NVRAM_WRITE1, 0x406);
12472
12473                 grc_mode = tr32(GRC_MODE);
12474                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12475
12476                 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
12477                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12478                                 buf);
12479                 } else {
12480                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12481                                 buf);
12482                 }
12483
12484                 grc_mode = tr32(GRC_MODE);
12485                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12486
12487                 tg3_disable_nvram_access(tp);
12488                 tg3_nvram_unlock(tp);
12489         }
12490
12491         if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12492                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12493                 udelay(40);
12494         }
12495
12496         return ret;
12497 }
12498
12499 struct subsys_tbl_ent {
12500         u16 subsys_vendor, subsys_devid;
12501         u32 phy_id;
12502 };
12503
12504 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12505         /* Broadcom boards. */
12506         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12507           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12508         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12509           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12510         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12511           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12512         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12513           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12514         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12515           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12516         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12517           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12518         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12519           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12520         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12521           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12522         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12523           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12524         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12525           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12526         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12527           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12528
12529         /* 3com boards. */
12530         { TG3PCI_SUBVENDOR_ID_3COM,
12531           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12532         { TG3PCI_SUBVENDOR_ID_3COM,
12533           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12534         { TG3PCI_SUBVENDOR_ID_3COM,
12535           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12536         { TG3PCI_SUBVENDOR_ID_3COM,
12537           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12538         { TG3PCI_SUBVENDOR_ID_3COM,
12539           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12540
12541         /* DELL boards. */
12542         { TG3PCI_SUBVENDOR_ID_DELL,
12543           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12544         { TG3PCI_SUBVENDOR_ID_DELL,
12545           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12546         { TG3PCI_SUBVENDOR_ID_DELL,
12547           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12548         { TG3PCI_SUBVENDOR_ID_DELL,
12549           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12550
12551         /* Compaq boards. */
12552         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12553           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12554         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12555           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12556         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12557           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12558         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12559           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12560         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12561           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12562
12563         /* IBM boards. */
12564         { TG3PCI_SUBVENDOR_ID_IBM,
12565           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12566 };
12567
12568 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12569 {
12570         int i;
12571
12572         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12573                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12574                      tp->pdev->subsystem_vendor) &&
12575                     (subsys_id_to_phy_id[i].subsys_devid ==
12576                      tp->pdev->subsystem_device))
12577                         return &subsys_id_to_phy_id[i];
12578         }
12579         return NULL;
12580 }
12581
12582 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12583 {
12584         u32 val;
12585         u16 pmcsr;
12586
12587         /* On some early chips the SRAM cannot be accessed in D3hot state,
12588          * so need make sure we're in D0.
12589          */
12590         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12591         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12592         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12593         msleep(1);
12594
12595         /* Make sure register accesses (indirect or otherwise)
12596          * will function correctly.
12597          */
12598         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12599                                tp->misc_host_ctrl);
12600
12601         /* The memory arbiter has to be enabled in order for SRAM accesses
12602          * to succeed.  Normally on powerup the tg3 chip firmware will make
12603          * sure it is enabled, but other entities such as system netboot
12604          * code might disable it.
12605          */
12606         val = tr32(MEMARB_MODE);
12607         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12608
12609         tp->phy_id = TG3_PHY_ID_INVALID;
12610         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12611
12612         /* Assume an onboard device and WOL capable by default.  */
12613         tg3_flag_set(tp, EEPROM_WRITE_PROT);
12614         tg3_flag_set(tp, WOL_CAP);
12615
12616         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12617                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12618                         tg3_flag_clear(tp, EEPROM_WRITE_PROT);
12619                         tg3_flag_set(tp, IS_NIC);
12620                 }
12621                 val = tr32(VCPU_CFGSHDW);
12622                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12623                         tg3_flag_set(tp, ASPM_WORKAROUND);
12624                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12625                     (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
12626                         tg3_flag_set(tp, WOL_ENABLE);
12627                         device_set_wakeup_enable(&tp->pdev->dev, true);
12628                 }
12629                 goto done;
12630         }
12631
12632         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12633         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12634                 u32 nic_cfg, led_cfg;
12635                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12636                 int eeprom_phy_serdes = 0;
12637
12638                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12639                 tp->nic_sram_data_cfg = nic_cfg;
12640
12641                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12642                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12643                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12644                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12645                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12646                     (ver > 0) && (ver < 0x100))
12647                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12648
12649                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12650                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12651
12652                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12653                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12654                         eeprom_phy_serdes = 1;
12655
12656                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12657                 if (nic_phy_id != 0) {
12658                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12659                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12660
12661                         eeprom_phy_id  = (id1 >> 16) << 10;
12662                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12663                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12664                 } else
12665                         eeprom_phy_id = 0;
12666
12667                 tp->phy_id = eeprom_phy_id;
12668                 if (eeprom_phy_serdes) {
12669                         if (!tg3_flag(tp, 5705_PLUS))
12670                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12671                         else
12672                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12673                 }
12674
12675                 if (tg3_flag(tp, 5750_PLUS))
12676                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12677                                     SHASTA_EXT_LED_MODE_MASK);
12678                 else
12679                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12680
12681                 switch (led_cfg) {
12682                 default:
12683                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12684                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12685                         break;
12686
12687                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12688                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12689                         break;
12690
12691                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12692                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12693
12694                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12695                          * read on some older 5700/5701 bootcode.
12696                          */
12697                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12698                             ASIC_REV_5700 ||
12699                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12700                             ASIC_REV_5701)
12701                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12702
12703                         break;
12704
12705                 case SHASTA_EXT_LED_SHARED:
12706                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12707                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12708                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12709                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12710                                                  LED_CTRL_MODE_PHY_2);
12711                         break;
12712
12713                 case SHASTA_EXT_LED_MAC:
12714                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12715                         break;
12716
12717                 case SHASTA_EXT_LED_COMBO:
12718                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12719                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12720                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12721                                                  LED_CTRL_MODE_PHY_2);
12722                         break;
12723
12724                 }
12725
12726                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12727                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12728                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12729                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12730
12731                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12732                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12733
12734                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12735                         tg3_flag_set(tp, EEPROM_WRITE_PROT);
12736                         if ((tp->pdev->subsystem_vendor ==
12737                              PCI_VENDOR_ID_ARIMA) &&
12738                             (tp->pdev->subsystem_device == 0x205a ||
12739                              tp->pdev->subsystem_device == 0x2063))
12740                                 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
12741                 } else {
12742                         tg3_flag_clear(tp, EEPROM_WRITE_PROT);
12743                         tg3_flag_set(tp, IS_NIC);
12744                 }
12745
12746                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12747                         tg3_flag_set(tp, ENABLE_ASF);
12748                         if (tg3_flag(tp, 5750_PLUS))
12749                                 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
12750                 }
12751
12752                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12753                     tg3_flag(tp, 5750_PLUS))
12754                         tg3_flag_set(tp, ENABLE_APE);
12755
12756                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12757                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12758                         tg3_flag_clear(tp, WOL_CAP);
12759
12760                 if (tg3_flag(tp, WOL_CAP) &&
12761                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
12762                         tg3_flag_set(tp, WOL_ENABLE);
12763                         device_set_wakeup_enable(&tp->pdev->dev, true);
12764                 }
12765
12766                 if (cfg2 & (1 << 17))
12767                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12768
12769                 /* serdes signal pre-emphasis in register 0x590 set by */
12770                 /* bootcode if bit 18 is set */
12771                 if (cfg2 & (1 << 18))
12772                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12773
12774                 if ((tg3_flag(tp, 57765_PLUS) ||
12775                      (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12776                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12777                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12778                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12779
12780                 if (tg3_flag(tp, PCI_EXPRESS) &&
12781                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12782                     !tg3_flag(tp, 57765_PLUS)) {
12783                         u32 cfg3;
12784
12785                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12786                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12787                                 tg3_flag_set(tp, ASPM_WORKAROUND);
12788                 }
12789
12790                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12791                         tg3_flag_set(tp, RGMII_INBAND_DISABLE);
12792                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12793                         tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
12794                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12795                         tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
12796         }
12797 done:
12798         if (tg3_flag(tp, WOL_CAP))
12799                 device_set_wakeup_enable(&tp->pdev->dev,
12800                                          tg3_flag(tp, WOL_ENABLE));
12801         else
12802                 device_set_wakeup_capable(&tp->pdev->dev, false);
12803 }
12804
12805 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12806 {
12807         int i;
12808         u32 val;
12809
12810         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12811         tw32(OTP_CTRL, cmd);
12812
12813         /* Wait for up to 1 ms for command to execute. */
12814         for (i = 0; i < 100; i++) {
12815                 val = tr32(OTP_STATUS);
12816                 if (val & OTP_STATUS_CMD_DONE)
12817                         break;
12818                 udelay(10);
12819         }
12820
12821         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12822 }
12823
12824 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12825  * configuration is a 32-bit value that straddles the alignment boundary.
12826  * We do two 32-bit reads and then shift and merge the results.
12827  */
12828 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12829 {
12830         u32 bhalf_otp, thalf_otp;
12831
12832         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12833
12834         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12835                 return 0;
12836
12837         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12838
12839         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12840                 return 0;
12841
12842         thalf_otp = tr32(OTP_READ_DATA);
12843
12844         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12845
12846         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12847                 return 0;
12848
12849         bhalf_otp = tr32(OTP_READ_DATA);
12850
12851         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12852 }
12853
12854 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
12855 {
12856         u32 adv = ADVERTISED_Autoneg |
12857                   ADVERTISED_Pause;
12858
12859         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12860                 adv |= ADVERTISED_1000baseT_Half |
12861                        ADVERTISED_1000baseT_Full;
12862
12863         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12864                 adv |= ADVERTISED_100baseT_Half |
12865                        ADVERTISED_100baseT_Full |
12866                        ADVERTISED_10baseT_Half |
12867                        ADVERTISED_10baseT_Full |
12868                        ADVERTISED_TP;
12869         else
12870                 adv |= ADVERTISED_FIBRE;
12871
12872         tp->link_config.advertising = adv;
12873         tp->link_config.speed = SPEED_INVALID;
12874         tp->link_config.duplex = DUPLEX_INVALID;
12875         tp->link_config.autoneg = AUTONEG_ENABLE;
12876         tp->link_config.active_speed = SPEED_INVALID;
12877         tp->link_config.active_duplex = DUPLEX_INVALID;
12878         tp->link_config.orig_speed = SPEED_INVALID;
12879         tp->link_config.orig_duplex = DUPLEX_INVALID;
12880         tp->link_config.orig_autoneg = AUTONEG_INVALID;
12881 }
12882
12883 static int __devinit tg3_phy_probe(struct tg3 *tp)
12884 {
12885         u32 hw_phy_id_1, hw_phy_id_2;
12886         u32 hw_phy_id, hw_phy_id_masked;
12887         int err;
12888
12889         /* flow control autonegotiation is default behavior */
12890         tg3_flag_set(tp, PAUSE_AUTONEG);
12891         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
12892
12893         if (tg3_flag(tp, USE_PHYLIB))
12894                 return tg3_phy_init(tp);
12895
12896         /* Reading the PHY ID register can conflict with ASF
12897          * firmware access to the PHY hardware.
12898          */
12899         err = 0;
12900         if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
12901                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12902         } else {
12903                 /* Now read the physical PHY_ID from the chip and verify
12904                  * that it is sane.  If it doesn't look good, we fall back
12905                  * to either the hard-coded table based PHY_ID and failing
12906                  * that the value found in the eeprom area.
12907                  */
12908                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12909                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12910
12911                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12912                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12913                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12914
12915                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12916         }
12917
12918         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12919                 tp->phy_id = hw_phy_id;
12920                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12921                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12922                 else
12923                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12924         } else {
12925                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12926                         /* Do nothing, phy ID already set up in
12927                          * tg3_get_eeprom_hw_cfg().
12928                          */
12929                 } else {
12930                         struct subsys_tbl_ent *p;
12931
12932                         /* No eeprom signature?  Try the hardcoded
12933                          * subsys device table.
12934                          */
12935                         p = tg3_lookup_by_subsys(tp);
12936                         if (!p)
12937                                 return -ENODEV;
12938
12939                         tp->phy_id = p->phy_id;
12940                         if (!tp->phy_id ||
12941                             tp->phy_id == TG3_PHY_ID_BCM8002)
12942                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12943                 }
12944         }
12945
12946         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12947             ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
12948               tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
12949              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12950               tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
12951                 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12952
12953         tg3_phy_init_link_config(tp);
12954
12955         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12956             !tg3_flag(tp, ENABLE_APE) &&
12957             !tg3_flag(tp, ENABLE_ASF)) {
12958                 u32 bmsr, mask;
12959
12960                 tg3_readphy(tp, MII_BMSR, &bmsr);
12961                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12962                     (bmsr & BMSR_LSTATUS))
12963                         goto skip_phy_reset;
12964
12965                 err = tg3_phy_reset(tp);
12966                 if (err)
12967                         return err;
12968
12969                 tg3_phy_set_wirespeed(tp);
12970
12971                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12972                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12973                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12974                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12975                         tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
12976                                             tp->link_config.flowctrl);
12977
12978                         tg3_writephy(tp, MII_BMCR,
12979                                      BMCR_ANENABLE | BMCR_ANRESTART);
12980                 }
12981         }
12982
12983 skip_phy_reset:
12984         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12985                 err = tg3_init_5401phy_dsp(tp);
12986                 if (err)
12987                         return err;
12988
12989                 err = tg3_init_5401phy_dsp(tp);
12990         }
12991
12992         return err;
12993 }
12994
12995 static void __devinit tg3_read_vpd(struct tg3 *tp)
12996 {
12997         u8 *vpd_data;
12998         unsigned int block_end, rosize, len;
12999         int j, i = 0;
13000
13001         vpd_data = (u8 *)tg3_vpd_readblock(tp);
13002         if (!vpd_data)
13003                 goto out_no_vpd;
13004
13005         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
13006                              PCI_VPD_LRDT_RO_DATA);
13007         if (i < 0)
13008                 goto out_not_found;
13009
13010         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
13011         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
13012         i += PCI_VPD_LRDT_TAG_SIZE;
13013
13014         if (block_end > TG3_NVM_VPD_LEN)
13015                 goto out_not_found;
13016
13017         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13018                                       PCI_VPD_RO_KEYWORD_MFR_ID);
13019         if (j > 0) {
13020                 len = pci_vpd_info_field_size(&vpd_data[j]);
13021
13022                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13023                 if (j + len > block_end || len != 4 ||
13024                     memcmp(&vpd_data[j], "1028", 4))
13025                         goto partno;
13026
13027                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13028                                               PCI_VPD_RO_KEYWORD_VENDOR0);
13029                 if (j < 0)
13030                         goto partno;
13031
13032                 len = pci_vpd_info_field_size(&vpd_data[j]);
13033
13034                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13035                 if (j + len > block_end)
13036                         goto partno;
13037
13038                 memcpy(tp->fw_ver, &vpd_data[j], len);
13039                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
13040         }
13041
13042 partno:
13043         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13044                                       PCI_VPD_RO_KEYWORD_PARTNO);
13045         if (i < 0)
13046                 goto out_not_found;
13047
13048         len = pci_vpd_info_field_size(&vpd_data[i]);
13049
13050         i += PCI_VPD_INFO_FLD_HDR_SIZE;
13051         if (len > TG3_BPN_SIZE ||
13052             (len + i) > TG3_NVM_VPD_LEN)
13053                 goto out_not_found;
13054
13055         memcpy(tp->board_part_number, &vpd_data[i], len);
13056
13057 out_not_found:
13058         kfree(vpd_data);
13059         if (tp->board_part_number[0])
13060                 return;
13061
13062 out_no_vpd:
13063         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13064                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
13065                         strcpy(tp->board_part_number, "BCM5717");
13066                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
13067                         strcpy(tp->board_part_number, "BCM5718");
13068                 else
13069                         goto nomatch;
13070         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
13071                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
13072                         strcpy(tp->board_part_number, "BCM57780");
13073                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13074                         strcpy(tp->board_part_number, "BCM57760");
13075                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13076                         strcpy(tp->board_part_number, "BCM57790");
13077                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13078                         strcpy(tp->board_part_number, "BCM57788");
13079                 else
13080                         goto nomatch;
13081         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13082                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13083                         strcpy(tp->board_part_number, "BCM57761");
13084                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13085                         strcpy(tp->board_part_number, "BCM57765");
13086                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13087                         strcpy(tp->board_part_number, "BCM57781");
13088                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13089                         strcpy(tp->board_part_number, "BCM57785");
13090                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13091                         strcpy(tp->board_part_number, "BCM57791");
13092                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13093                         strcpy(tp->board_part_number, "BCM57795");
13094                 else
13095                         goto nomatch;
13096         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13097                 strcpy(tp->board_part_number, "BCM95906");
13098         } else {
13099 nomatch:
13100                 strcpy(tp->board_part_number, "none");
13101         }
13102 }
13103
13104 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
13105 {
13106         u32 val;
13107
13108         if (tg3_nvram_read(tp, offset, &val) ||
13109             (val & 0xfc000000) != 0x0c000000 ||
13110             tg3_nvram_read(tp, offset + 4, &val) ||
13111             val != 0)
13112                 return 0;
13113
13114         return 1;
13115 }
13116
13117 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13118 {
13119         u32 val, offset, start, ver_offset;
13120         int i, dst_off;
13121         bool newver = false;
13122
13123         if (tg3_nvram_read(tp, 0xc, &offset) ||
13124             tg3_nvram_read(tp, 0x4, &start))
13125                 return;
13126
13127         offset = tg3_nvram_logical_addr(tp, offset);
13128
13129         if (tg3_nvram_read(tp, offset, &val))
13130                 return;
13131
13132         if ((val & 0xfc000000) == 0x0c000000) {
13133                 if (tg3_nvram_read(tp, offset + 4, &val))
13134                         return;
13135
13136                 if (val == 0)
13137                         newver = true;
13138         }
13139
13140         dst_off = strlen(tp->fw_ver);
13141
13142         if (newver) {
13143                 if (TG3_VER_SIZE - dst_off < 16 ||
13144                     tg3_nvram_read(tp, offset + 8, &ver_offset))
13145                         return;
13146
13147                 offset = offset + ver_offset - start;
13148                 for (i = 0; i < 16; i += 4) {
13149                         __be32 v;
13150                         if (tg3_nvram_read_be32(tp, offset + i, &v))
13151                                 return;
13152
13153                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
13154                 }
13155         } else {
13156                 u32 major, minor;
13157
13158                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13159                         return;
13160
13161                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13162                         TG3_NVM_BCVER_MAJSFT;
13163                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
13164                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13165                          "v%d.%02d", major, minor);
13166         }
13167 }
13168
13169 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13170 {
13171         u32 val, major, minor;
13172
13173         /* Use native endian representation */
13174         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13175                 return;
13176
13177         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13178                 TG3_NVM_HWSB_CFG1_MAJSFT;
13179         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13180                 TG3_NVM_HWSB_CFG1_MINSFT;
13181
13182         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13183 }
13184
13185 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13186 {
13187         u32 offset, major, minor, build;
13188
13189         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13190
13191         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13192                 return;
13193
13194         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13195         case TG3_EEPROM_SB_REVISION_0:
13196                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13197                 break;
13198         case TG3_EEPROM_SB_REVISION_2:
13199                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13200                 break;
13201         case TG3_EEPROM_SB_REVISION_3:
13202                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13203                 break;
13204         case TG3_EEPROM_SB_REVISION_4:
13205                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13206                 break;
13207         case TG3_EEPROM_SB_REVISION_5:
13208                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13209                 break;
13210         case TG3_EEPROM_SB_REVISION_6:
13211                 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13212                 break;
13213         default:
13214                 return;
13215         }
13216
13217         if (tg3_nvram_read(tp, offset, &val))
13218                 return;
13219
13220         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13221                 TG3_EEPROM_SB_EDH_BLD_SHFT;
13222         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13223                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13224         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
13225
13226         if (minor > 99 || build > 26)
13227                 return;
13228
13229         offset = strlen(tp->fw_ver);
13230         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13231                  " v%d.%02d", major, minor);
13232
13233         if (build > 0) {
13234                 offset = strlen(tp->fw_ver);
13235                 if (offset < TG3_VER_SIZE - 1)
13236                         tp->fw_ver[offset] = 'a' + build - 1;
13237         }
13238 }
13239
13240 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13241 {
13242         u32 val, offset, start;
13243         int i, vlen;
13244
13245         for (offset = TG3_NVM_DIR_START;
13246              offset < TG3_NVM_DIR_END;
13247              offset += TG3_NVM_DIRENT_SIZE) {
13248                 if (tg3_nvram_read(tp, offset, &val))
13249                         return;
13250
13251                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13252                         break;
13253         }
13254
13255         if (offset == TG3_NVM_DIR_END)
13256                 return;
13257
13258         if (!tg3_flag(tp, 5705_PLUS))
13259                 start = 0x08000000;
13260         else if (tg3_nvram_read(tp, offset - 4, &start))
13261                 return;
13262
13263         if (tg3_nvram_read(tp, offset + 4, &offset) ||
13264             !tg3_fw_img_is_valid(tp, offset) ||
13265             tg3_nvram_read(tp, offset + 8, &val))
13266                 return;
13267
13268         offset += val - start;
13269
13270         vlen = strlen(tp->fw_ver);
13271
13272         tp->fw_ver[vlen++] = ',';
13273         tp->fw_ver[vlen++] = ' ';
13274
13275         for (i = 0; i < 4; i++) {
13276                 __be32 v;
13277                 if (tg3_nvram_read_be32(tp, offset, &v))
13278                         return;
13279
13280                 offset += sizeof(v);
13281
13282                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13283                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13284                         break;
13285                 }
13286
13287                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13288                 vlen += sizeof(v);
13289         }
13290 }
13291
13292 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13293 {
13294         int vlen;
13295         u32 apedata;
13296         char *fwtype;
13297
13298         if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF))
13299                 return;
13300
13301         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13302         if (apedata != APE_SEG_SIG_MAGIC)
13303                 return;
13304
13305         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13306         if (!(apedata & APE_FW_STATUS_READY))
13307                 return;
13308
13309         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13310
13311         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13312                 tg3_flag_set(tp, APE_HAS_NCSI);
13313                 fwtype = "NCSI";
13314         } else {
13315                 fwtype = "DASH";
13316         }
13317
13318         vlen = strlen(tp->fw_ver);
13319
13320         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13321                  fwtype,
13322                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13323                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13324                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13325                  (apedata & APE_FW_VERSION_BLDMSK));
13326 }
13327
13328 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13329 {
13330         u32 val;
13331         bool vpd_vers = false;
13332
13333         if (tp->fw_ver[0] != 0)
13334                 vpd_vers = true;
13335
13336         if (tg3_flag(tp, NO_NVRAM)) {
13337                 strcat(tp->fw_ver, "sb");
13338                 return;
13339         }
13340
13341         if (tg3_nvram_read(tp, 0, &val))
13342                 return;
13343
13344         if (val == TG3_EEPROM_MAGIC)
13345                 tg3_read_bc_ver(tp);
13346         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13347                 tg3_read_sb_ver(tp, val);
13348         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13349                 tg3_read_hwsb_ver(tp);
13350         else
13351                 return;
13352
13353         if (!tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || vpd_vers)
13354                 goto done;
13355
13356         tg3_read_mgmtfw_ver(tp);
13357
13358 done:
13359         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13360 }
13361
13362 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13363
13364 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13365 {
13366         if (tg3_flag(tp, LRG_PROD_RING_CAP))
13367                 return TG3_RX_RET_MAX_SIZE_5717;
13368         else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
13369                 return TG3_RX_RET_MAX_SIZE_5700;
13370         else
13371                 return TG3_RX_RET_MAX_SIZE_5705;
13372 }
13373
13374 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13375         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13376         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13377         { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13378         { },
13379 };
13380
13381 static int __devinit tg3_get_invariants(struct tg3 *tp)
13382 {
13383         u32 misc_ctrl_reg;
13384         u32 pci_state_reg, grc_misc_cfg;
13385         u32 val;
13386         u16 pci_cmd;
13387         int err;
13388
13389         /* Force memory write invalidate off.  If we leave it on,
13390          * then on 5700_BX chips we have to enable a workaround.
13391          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13392          * to match the cacheline size.  The Broadcom driver have this
13393          * workaround but turns MWI off all the times so never uses
13394          * it.  This seems to suggest that the workaround is insufficient.
13395          */
13396         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13397         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13398         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13399
13400         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13401          * has the register indirect write enable bit set before
13402          * we try to access any of the MMIO registers.  It is also
13403          * critical that the PCI-X hw workaround situation is decided
13404          * before that as well.
13405          */
13406         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13407                               &misc_ctrl_reg);
13408
13409         tp->pci_chip_rev_id = (misc_ctrl_reg >>
13410                                MISC_HOST_CTRL_CHIPREV_SHIFT);
13411         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13412                 u32 prod_id_asic_rev;
13413
13414                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13415                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13416                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13417                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
13418                         pci_read_config_dword(tp->pdev,
13419                                               TG3PCI_GEN2_PRODID_ASICREV,
13420                                               &prod_id_asic_rev);
13421                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13422                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13423                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13424                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13425                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13426                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13427                         pci_read_config_dword(tp->pdev,
13428                                               TG3PCI_GEN15_PRODID_ASICREV,
13429                                               &prod_id_asic_rev);
13430                 else
13431                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13432                                               &prod_id_asic_rev);
13433
13434                 tp->pci_chip_rev_id = prod_id_asic_rev;
13435         }
13436
13437         /* Wrong chip ID in 5752 A0. This code can be removed later
13438          * as A0 is not in production.
13439          */
13440         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13441                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13442
13443         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13444          * we need to disable memory and use config. cycles
13445          * only to access all registers. The 5702/03 chips
13446          * can mistakenly decode the special cycles from the
13447          * ICH chipsets as memory write cycles, causing corruption
13448          * of register and memory space. Only certain ICH bridges
13449          * will drive special cycles with non-zero data during the
13450          * address phase which can fall within the 5703's address
13451          * range. This is not an ICH bug as the PCI spec allows
13452          * non-zero address during special cycles. However, only
13453          * these ICH bridges are known to drive non-zero addresses
13454          * during special cycles.
13455          *
13456          * Since special cycles do not cross PCI bridges, we only
13457          * enable this workaround if the 5703 is on the secondary
13458          * bus of these ICH bridges.
13459          */
13460         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13461             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13462                 static struct tg3_dev_id {
13463                         u32     vendor;
13464                         u32     device;
13465                         u32     rev;
13466                 } ich_chipsets[] = {
13467                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13468                           PCI_ANY_ID },
13469                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13470                           PCI_ANY_ID },
13471                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13472                           0xa },
13473                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13474                           PCI_ANY_ID },
13475                         { },
13476                 };
13477                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13478                 struct pci_dev *bridge = NULL;
13479
13480                 while (pci_id->vendor != 0) {
13481                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
13482                                                 bridge);
13483                         if (!bridge) {
13484                                 pci_id++;
13485                                 continue;
13486                         }
13487                         if (pci_id->rev != PCI_ANY_ID) {
13488                                 if (bridge->revision > pci_id->rev)
13489                                         continue;
13490                         }
13491                         if (bridge->subordinate &&
13492                             (bridge->subordinate->number ==
13493                              tp->pdev->bus->number)) {
13494                                 tg3_flag_set(tp, ICH_WORKAROUND);
13495                                 pci_dev_put(bridge);
13496                                 break;
13497                         }
13498                 }
13499         }
13500
13501         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13502                 static struct tg3_dev_id {
13503                         u32     vendor;
13504                         u32     device;
13505                 } bridge_chipsets[] = {
13506                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13507                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13508                         { },
13509                 };
13510                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13511                 struct pci_dev *bridge = NULL;
13512
13513                 while (pci_id->vendor != 0) {
13514                         bridge = pci_get_device(pci_id->vendor,
13515                                                 pci_id->device,
13516                                                 bridge);
13517                         if (!bridge) {
13518                                 pci_id++;
13519                                 continue;
13520                         }
13521                         if (bridge->subordinate &&
13522                             (bridge->subordinate->number <=
13523                              tp->pdev->bus->number) &&
13524                             (bridge->subordinate->subordinate >=
13525                              tp->pdev->bus->number)) {
13526                                 tg3_flag_set(tp, 5701_DMA_BUG);
13527                                 pci_dev_put(bridge);
13528                                 break;
13529                         }
13530                 }
13531         }
13532
13533         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13534          * DMA addresses > 40-bit. This bridge may have other additional
13535          * 57xx devices behind it in some 4-port NIC designs for example.
13536          * Any tg3 device found behind the bridge will also need the 40-bit
13537          * DMA workaround.
13538          */
13539         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13540             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13541                 tg3_flag_set(tp, 5780_CLASS);
13542                 tg3_flag_set(tp, 40BIT_DMA_BUG);
13543                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13544         } else {
13545                 struct pci_dev *bridge = NULL;
13546
13547                 do {
13548                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13549                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13550                                                 bridge);
13551                         if (bridge && bridge->subordinate &&
13552                             (bridge->subordinate->number <=
13553                              tp->pdev->bus->number) &&
13554                             (bridge->subordinate->subordinate >=
13555                              tp->pdev->bus->number)) {
13556                                 tg3_flag_set(tp, 40BIT_DMA_BUG);
13557                                 pci_dev_put(bridge);
13558                                 break;
13559                         }
13560                 } while (bridge);
13561         }
13562
13563         /* Initialize misc host control in PCI block. */
13564         tp->misc_host_ctrl |= (misc_ctrl_reg &
13565                                MISC_HOST_CTRL_CHIPREV);
13566         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13567                                tp->misc_host_ctrl);
13568
13569         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13570             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13571             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13572             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13573                 tp->pdev_peer = tg3_find_peer(tp);
13574
13575         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13576             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13577             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13578                 tg3_flag_set(tp, 5717_PLUS);
13579
13580         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
13581             tg3_flag(tp, 5717_PLUS))
13582                 tg3_flag_set(tp, 57765_PLUS);
13583
13584         /* Intentionally exclude ASIC_REV_5906 */
13585         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13586             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13587             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13588             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13589             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13590             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13591             tg3_flag(tp, 57765_PLUS))
13592                 tg3_flag_set(tp, 5755_PLUS);
13593
13594         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13595             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13596             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13597             tg3_flag(tp, 5755_PLUS) ||
13598             tg3_flag(tp, 5780_CLASS))
13599                 tg3_flag_set(tp, 5750_PLUS);
13600
13601         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13602             tg3_flag(tp, 5750_PLUS))
13603                 tg3_flag_set(tp, 5705_PLUS);
13604
13605         /* 5700 B0 chips do not support checksumming correctly due
13606          * to hardware bugs.
13607          */
13608         if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
13609                 u32 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
13610
13611                 if (tg3_flag(tp, 5755_PLUS))
13612                         features |= NETIF_F_IPV6_CSUM;
13613                 tp->dev->features |= features;
13614                 tp->dev->hw_features |= features;
13615                 tp->dev->vlan_features |= features;
13616         }
13617
13618         /* Determine TSO capabilities */
13619         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13620                 ; /* Do nothing. HW bug. */
13621         else if (tg3_flag(tp, 57765_PLUS))
13622                 tg3_flag_set(tp, HW_TSO_3);
13623         else if (tg3_flag(tp, 5755_PLUS) ||
13624                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13625                 tg3_flag_set(tp, HW_TSO_2);
13626         else if (tg3_flag(tp, 5750_PLUS)) {
13627                 tg3_flag_set(tp, HW_TSO_1);
13628                 tg3_flag_set(tp, TSO_BUG);
13629                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13630                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13631                         tg3_flag_clear(tp, TSO_BUG);
13632         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13633                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13634                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13635                         tg3_flag_set(tp, TSO_BUG);
13636                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13637                         tp->fw_needed = FIRMWARE_TG3TSO5;
13638                 else
13639                         tp->fw_needed = FIRMWARE_TG3TSO;
13640         }
13641
13642         tp->irq_max = 1;
13643
13644         if (tg3_flag(tp, 5750_PLUS)) {
13645                 tg3_flag_set(tp, SUPPORT_MSI);
13646                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13647                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13648                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13649                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13650                      tp->pdev_peer == tp->pdev))
13651                         tg3_flag_clear(tp, SUPPORT_MSI);
13652
13653                 if (tg3_flag(tp, 5755_PLUS) ||
13654                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13655                         tg3_flag_set(tp, 1SHOT_MSI);
13656                 }
13657
13658                 if (tg3_flag(tp, 57765_PLUS)) {
13659                         tg3_flag_set(tp, SUPPORT_MSIX);
13660                         tp->irq_max = TG3_IRQ_MAX_VECS;
13661                 }
13662         }
13663
13664         /* All chips can get confused if TX buffers
13665          * straddle the 4GB address boundary.
13666          */
13667         tg3_flag_set(tp, 4G_DMA_BNDRY_BUG);
13668
13669         if (tg3_flag(tp, 5755_PLUS))
13670                 tg3_flag_set(tp, SHORT_DMA_BUG);
13671         else
13672                 tg3_flag_set(tp, 40BIT_DMA_LIMIT_BUG);
13673
13674         if (tg3_flag(tp, 5717_PLUS))
13675                 tg3_flag_set(tp, LRG_PROD_RING_CAP);
13676
13677         if (tg3_flag(tp, 57765_PLUS) &&
13678             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
13679                 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
13680
13681         if (!tg3_flag(tp, 5705_PLUS) ||
13682             tg3_flag(tp, 5780_CLASS) ||
13683             tg3_flag(tp, USE_JUMBO_BDFLAG))
13684                 tg3_flag_set(tp, JUMBO_CAPABLE);
13685
13686         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13687                               &pci_state_reg);
13688
13689         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13690         if (tp->pcie_cap != 0) {
13691                 u16 lnkctl;
13692
13693                 tg3_flag_set(tp, PCI_EXPRESS);
13694
13695                 tp->pcie_readrq = 4096;
13696                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13697                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13698                         tp->pcie_readrq = 2048;
13699
13700                 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
13701
13702                 pci_read_config_word(tp->pdev,
13703                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13704                                      &lnkctl);
13705                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13706                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13707                                 tg3_flag_clear(tp, HW_TSO_2);
13708                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13709                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13710                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13711                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13712                                 tg3_flag_set(tp, CLKREQ_BUG);
13713                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13714                         tg3_flag_set(tp, L1PLLPD_EN);
13715                 }
13716         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13717                 tg3_flag_set(tp, PCI_EXPRESS);
13718         } else if (!tg3_flag(tp, 5705_PLUS) ||
13719                    tg3_flag(tp, 5780_CLASS)) {
13720                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13721                 if (!tp->pcix_cap) {
13722                         dev_err(&tp->pdev->dev,
13723                                 "Cannot find PCI-X capability, aborting\n");
13724                         return -EIO;
13725                 }
13726
13727                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13728                         tg3_flag_set(tp, PCIX_MODE);
13729         }
13730
13731         /* If we have an AMD 762 or VIA K8T800 chipset, write
13732          * reordering to the mailbox registers done by the host
13733          * controller can cause major troubles.  We read back from
13734          * every mailbox register write to force the writes to be
13735          * posted to the chip in order.
13736          */
13737         if (pci_dev_present(tg3_write_reorder_chipsets) &&
13738             !tg3_flag(tp, PCI_EXPRESS))
13739                 tg3_flag_set(tp, MBOX_WRITE_REORDER);
13740
13741         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13742                              &tp->pci_cacheline_sz);
13743         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13744                              &tp->pci_lat_timer);
13745         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13746             tp->pci_lat_timer < 64) {
13747                 tp->pci_lat_timer = 64;
13748                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13749                                       tp->pci_lat_timer);
13750         }
13751
13752         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13753                 /* 5700 BX chips need to have their TX producer index
13754                  * mailboxes written twice to workaround a bug.
13755                  */
13756                 tg3_flag_set(tp, TXD_MBOX_HWBUG);
13757
13758                 /* If we are in PCI-X mode, enable register write workaround.
13759                  *
13760                  * The workaround is to use indirect register accesses
13761                  * for all chip writes not to mailbox registers.
13762                  */
13763                 if (tg3_flag(tp, PCIX_MODE)) {
13764                         u32 pm_reg;
13765
13766                         tg3_flag_set(tp, PCIX_TARGET_HWBUG);
13767
13768                         /* The chip can have it's power management PCI config
13769                          * space registers clobbered due to this bug.
13770                          * So explicitly force the chip into D0 here.
13771                          */
13772                         pci_read_config_dword(tp->pdev,
13773                                               tp->pm_cap + PCI_PM_CTRL,
13774                                               &pm_reg);
13775                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13776                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13777                         pci_write_config_dword(tp->pdev,
13778                                                tp->pm_cap + PCI_PM_CTRL,
13779                                                pm_reg);
13780
13781                         /* Also, force SERR#/PERR# in PCI command. */
13782                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13783                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13784                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13785                 }
13786         }
13787
13788         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13789                 tg3_flag_set(tp, PCI_HIGH_SPEED);
13790         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13791                 tg3_flag_set(tp, PCI_32BIT);
13792
13793         /* Chip-specific fixup from Broadcom driver */
13794         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13795             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13796                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13797                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13798         }
13799
13800         /* Default fast path register access methods */
13801         tp->read32 = tg3_read32;
13802         tp->write32 = tg3_write32;
13803         tp->read32_mbox = tg3_read32;
13804         tp->write32_mbox = tg3_write32;
13805         tp->write32_tx_mbox = tg3_write32;
13806         tp->write32_rx_mbox = tg3_write32;
13807
13808         /* Various workaround register access methods */
13809         if (tg3_flag(tp, PCIX_TARGET_HWBUG))
13810                 tp->write32 = tg3_write_indirect_reg32;
13811         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13812                  (tg3_flag(tp, PCI_EXPRESS) &&
13813                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13814                 /*
13815                  * Back to back register writes can cause problems on these
13816                  * chips, the workaround is to read back all reg writes
13817                  * except those to mailbox regs.
13818                  *
13819                  * See tg3_write_indirect_reg32().
13820                  */
13821                 tp->write32 = tg3_write_flush_reg32;
13822         }
13823
13824         if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
13825                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13826                 if (tg3_flag(tp, MBOX_WRITE_REORDER))
13827                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13828         }
13829
13830         if (tg3_flag(tp, ICH_WORKAROUND)) {
13831                 tp->read32 = tg3_read_indirect_reg32;
13832                 tp->write32 = tg3_write_indirect_reg32;
13833                 tp->read32_mbox = tg3_read_indirect_mbox;
13834                 tp->write32_mbox = tg3_write_indirect_mbox;
13835                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13836                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13837
13838                 iounmap(tp->regs);
13839                 tp->regs = NULL;
13840
13841                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13842                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13843                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13844         }
13845         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13846                 tp->read32_mbox = tg3_read32_mbox_5906;
13847                 tp->write32_mbox = tg3_write32_mbox_5906;
13848                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13849                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13850         }
13851
13852         if (tp->write32 == tg3_write_indirect_reg32 ||
13853             (tg3_flag(tp, PCIX_MODE) &&
13854              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13855               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13856                 tg3_flag_set(tp, SRAM_USE_CONFIG);
13857
13858         /* Get eeprom hw config before calling tg3_set_power_state().
13859          * In particular, the TG3_FLAG_IS_NIC flag must be
13860          * determined before calling tg3_set_power_state() so that
13861          * we know whether or not to switch out of Vaux power.
13862          * When the flag is set, it means that GPIO1 is used for eeprom
13863          * write protect and also implies that it is a LOM where GPIOs
13864          * are not used to switch power.
13865          */
13866         tg3_get_eeprom_hw_cfg(tp);
13867
13868         if (tg3_flag(tp, ENABLE_APE)) {
13869                 /* Allow reads and writes to the
13870                  * APE register and memory space.
13871                  */
13872                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13873                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13874                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13875                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13876                                        pci_state_reg);
13877         }
13878
13879         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13880             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13881             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13882             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13883             tg3_flag(tp, 57765_PLUS))
13884                 tg3_flag_set(tp, CPMU_PRESENT);
13885
13886         /* Set up tp->grc_local_ctrl before calling tg3_power_up().
13887          * GPIO1 driven high will bring 5700's external PHY out of reset.
13888          * It is also used as eeprom write protect on LOMs.
13889          */
13890         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13891         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13892             tg3_flag(tp, EEPROM_WRITE_PROT))
13893                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13894                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13895         /* Unused GPIO3 must be driven as output on 5752 because there
13896          * are no pull-up resistors on unused GPIO pins.
13897          */
13898         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13899                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13900
13901         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13902             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13903             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13904                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13905
13906         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13907             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13908                 /* Turn off the debug UART. */
13909                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13910                 if (tg3_flag(tp, IS_NIC))
13911                         /* Keep VMain power. */
13912                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13913                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13914         }
13915
13916         /* Force the chip into D0. */
13917         err = tg3_power_up(tp);
13918         if (err) {
13919                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13920                 return err;
13921         }
13922
13923         /* Derive initial jumbo mode from MTU assigned in
13924          * ether_setup() via the alloc_etherdev() call
13925          */
13926         if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
13927                 tg3_flag_set(tp, JUMBO_RING_ENABLE);
13928
13929         /* Determine WakeOnLan speed to use. */
13930         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13931             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13932             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13933             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13934                 tg3_flag_clear(tp, WOL_SPEED_100MB);
13935         } else {
13936                 tg3_flag_set(tp, WOL_SPEED_100MB);
13937         }
13938
13939         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13940                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13941
13942         /* A few boards don't want Ethernet@WireSpeed phy feature */
13943         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13944             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13945              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13946              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13947             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13948             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13949                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13950
13951         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13952             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13953                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13954         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13955                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13956
13957         if (tg3_flag(tp, 5705_PLUS) &&
13958             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13959             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13960             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13961             !tg3_flag(tp, 57765_PLUS)) {
13962                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13963                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13964                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13965                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13966                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13967                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13968                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13969                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13970                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13971                 } else
13972                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13973         }
13974
13975         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13976             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13977                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13978                 if (tp->phy_otp == 0)
13979                         tp->phy_otp = TG3_OTP_DEFAULT;
13980         }
13981
13982         if (tg3_flag(tp, CPMU_PRESENT))
13983                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13984         else
13985                 tp->mi_mode = MAC_MI_MODE_BASE;
13986
13987         tp->coalesce_mode = 0;
13988         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13989             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13990                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13991
13992         /* Set these bits to enable statistics workaround. */
13993         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13994             tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
13995             tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
13996                 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
13997                 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
13998         }
13999
14000         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14001             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14002                 tg3_flag_set(tp, USE_PHYLIB);
14003
14004         err = tg3_mdio_init(tp);
14005         if (err)
14006                 return err;
14007
14008         /* Initialize data/descriptor byte/word swapping. */
14009         val = tr32(GRC_MODE);
14010         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14011                 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
14012                         GRC_MODE_WORD_SWAP_B2HRX_DATA |
14013                         GRC_MODE_B2HRX_ENABLE |
14014                         GRC_MODE_HTX2B_ENABLE |
14015                         GRC_MODE_HOST_STACKUP);
14016         else
14017                 val &= GRC_MODE_HOST_STACKUP;
14018
14019         tw32(GRC_MODE, val | tp->grc_mode);
14020
14021         tg3_switch_clocks(tp);
14022
14023         /* Clear this out for sanity. */
14024         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
14025
14026         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14027                               &pci_state_reg);
14028         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
14029             !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
14030                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
14031
14032                 if (chiprevid == CHIPREV_ID_5701_A0 ||
14033                     chiprevid == CHIPREV_ID_5701_B0 ||
14034                     chiprevid == CHIPREV_ID_5701_B2 ||
14035                     chiprevid == CHIPREV_ID_5701_B5) {
14036                         void __iomem *sram_base;
14037
14038                         /* Write some dummy words into the SRAM status block
14039                          * area, see if it reads back correctly.  If the return
14040                          * value is bad, force enable the PCIX workaround.
14041                          */
14042                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
14043
14044                         writel(0x00000000, sram_base);
14045                         writel(0x00000000, sram_base + 4);
14046                         writel(0xffffffff, sram_base + 4);
14047                         if (readl(sram_base) != 0x00000000)
14048                                 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14049                 }
14050         }
14051
14052         udelay(50);
14053         tg3_nvram_init(tp);
14054
14055         grc_misc_cfg = tr32(GRC_MISC_CFG);
14056         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
14057
14058         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14059             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
14060              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
14061                 tg3_flag_set(tp, IS_5788);
14062
14063         if (!tg3_flag(tp, IS_5788) &&
14064             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
14065                 tg3_flag_set(tp, TAGGED_STATUS);
14066         if (tg3_flag(tp, TAGGED_STATUS)) {
14067                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
14068                                       HOSTCC_MODE_CLRTICK_TXBD);
14069
14070                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
14071                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14072                                        tp->misc_host_ctrl);
14073         }
14074
14075         /* Preserve the APE MAC_MODE bits */
14076         if (tg3_flag(tp, ENABLE_APE))
14077                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
14078         else
14079                 tp->mac_mode = TG3_DEF_MAC_MODE;
14080
14081         /* these are limited to 10/100 only */
14082         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14083              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
14084             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14085              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14086              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
14087               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
14088               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
14089             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14090              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
14091               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
14092               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
14093             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
14094             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14095             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14096             (tp->phy_flags & TG3_PHYFLG_IS_FET))
14097                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
14098
14099         err = tg3_phy_probe(tp);
14100         if (err) {
14101                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
14102                 /* ... but do not return immediately ... */
14103                 tg3_mdio_fini(tp);
14104         }
14105
14106         tg3_read_vpd(tp);
14107         tg3_read_fw_ver(tp);
14108
14109         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14110                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14111         } else {
14112                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14113                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14114                 else
14115                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14116         }
14117
14118         /* 5700 {AX,BX} chips have a broken status block link
14119          * change bit implementation, so we must use the
14120          * status register in those cases.
14121          */
14122         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14123                 tg3_flag_set(tp, USE_LINKCHG_REG);
14124         else
14125                 tg3_flag_clear(tp, USE_LINKCHG_REG);
14126
14127         /* The led_ctrl is set during tg3_phy_probe, here we might
14128          * have to force the link status polling mechanism based
14129          * upon subsystem IDs.
14130          */
14131         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
14132             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14133             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14134                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14135                 tg3_flag_set(tp, USE_LINKCHG_REG);
14136         }
14137
14138         /* For all SERDES we poll the MAC status register. */
14139         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14140                 tg3_flag_set(tp, POLL_SERDES);
14141         else
14142                 tg3_flag_clear(tp, POLL_SERDES);
14143
14144         tp->rx_offset = NET_IP_ALIGN;
14145         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
14146         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14147             tg3_flag(tp, PCIX_MODE)) {
14148                 tp->rx_offset = 0;
14149 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14150                 tp->rx_copy_thresh = ~(u16)0;
14151 #endif
14152         }
14153
14154         tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14155         tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
14156         tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14157
14158         tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
14159
14160         /* Increment the rx prod index on the rx std ring by at most
14161          * 8 for these chips to workaround hw errata.
14162          */
14163         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14164             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14165             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14166                 tp->rx_std_max_post = 8;
14167
14168         if (tg3_flag(tp, ASPM_WORKAROUND))
14169                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14170                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
14171
14172         return err;
14173 }
14174
14175 #ifdef CONFIG_SPARC
14176 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14177 {
14178         struct net_device *dev = tp->dev;
14179         struct pci_dev *pdev = tp->pdev;
14180         struct device_node *dp = pci_device_to_OF_node(pdev);
14181         const unsigned char *addr;
14182         int len;
14183
14184         addr = of_get_property(dp, "local-mac-address", &len);
14185         if (addr && len == 6) {
14186                 memcpy(dev->dev_addr, addr, 6);
14187                 memcpy(dev->perm_addr, dev->dev_addr, 6);
14188                 return 0;
14189         }
14190         return -ENODEV;
14191 }
14192
14193 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14194 {
14195         struct net_device *dev = tp->dev;
14196
14197         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
14198         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
14199         return 0;
14200 }
14201 #endif
14202
14203 static int __devinit tg3_get_device_address(struct tg3 *tp)
14204 {
14205         struct net_device *dev = tp->dev;
14206         u32 hi, lo, mac_offset;
14207         int addr_ok = 0;
14208
14209 #ifdef CONFIG_SPARC
14210         if (!tg3_get_macaddr_sparc(tp))
14211                 return 0;
14212 #endif
14213
14214         mac_offset = 0x7c;
14215         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
14216             tg3_flag(tp, 5780_CLASS)) {
14217                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14218                         mac_offset = 0xcc;
14219                 if (tg3_nvram_lock(tp))
14220                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14221                 else
14222                         tg3_nvram_unlock(tp);
14223         } else if (tg3_flag(tp, 5717_PLUS)) {
14224                 if (PCI_FUNC(tp->pdev->devfn) & 1)
14225                         mac_offset = 0xcc;
14226                 if (PCI_FUNC(tp->pdev->devfn) > 1)
14227                         mac_offset += 0x18c;
14228         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14229                 mac_offset = 0x10;
14230
14231         /* First try to get it from MAC address mailbox. */
14232         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14233         if ((hi >> 16) == 0x484b) {
14234                 dev->dev_addr[0] = (hi >>  8) & 0xff;
14235                 dev->dev_addr[1] = (hi >>  0) & 0xff;
14236
14237                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14238                 dev->dev_addr[2] = (lo >> 24) & 0xff;
14239                 dev->dev_addr[3] = (lo >> 16) & 0xff;
14240                 dev->dev_addr[4] = (lo >>  8) & 0xff;
14241                 dev->dev_addr[5] = (lo >>  0) & 0xff;
14242
14243                 /* Some old bootcode may report a 0 MAC address in SRAM */
14244                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14245         }
14246         if (!addr_ok) {
14247                 /* Next, try NVRAM. */
14248                 if (!tg3_flag(tp, NO_NVRAM) &&
14249                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14250                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14251                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14252                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
14253                 }
14254                 /* Finally just fetch it out of the MAC control regs. */
14255                 else {
14256                         hi = tr32(MAC_ADDR_0_HIGH);
14257                         lo = tr32(MAC_ADDR_0_LOW);
14258
14259                         dev->dev_addr[5] = lo & 0xff;
14260                         dev->dev_addr[4] = (lo >> 8) & 0xff;
14261                         dev->dev_addr[3] = (lo >> 16) & 0xff;
14262                         dev->dev_addr[2] = (lo >> 24) & 0xff;
14263                         dev->dev_addr[1] = hi & 0xff;
14264                         dev->dev_addr[0] = (hi >> 8) & 0xff;
14265                 }
14266         }
14267
14268         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14269 #ifdef CONFIG_SPARC
14270                 if (!tg3_get_default_macaddr_sparc(tp))
14271                         return 0;
14272 #endif
14273                 return -EINVAL;
14274         }
14275         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14276         return 0;
14277 }
14278
14279 #define BOUNDARY_SINGLE_CACHELINE       1
14280 #define BOUNDARY_MULTI_CACHELINE        2
14281
14282 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14283 {
14284         int cacheline_size;
14285         u8 byte;
14286         int goal;
14287
14288         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14289         if (byte == 0)
14290                 cacheline_size = 1024;
14291         else
14292                 cacheline_size = (int) byte * 4;
14293
14294         /* On 5703 and later chips, the boundary bits have no
14295          * effect.
14296          */
14297         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14298             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14299             !tg3_flag(tp, PCI_EXPRESS))
14300                 goto out;
14301
14302 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14303         goal = BOUNDARY_MULTI_CACHELINE;
14304 #else
14305 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14306         goal = BOUNDARY_SINGLE_CACHELINE;
14307 #else
14308         goal = 0;
14309 #endif
14310 #endif
14311
14312         if (tg3_flag(tp, 57765_PLUS)) {
14313                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14314                 goto out;
14315         }
14316
14317         if (!goal)
14318                 goto out;
14319
14320         /* PCI controllers on most RISC systems tend to disconnect
14321          * when a device tries to burst across a cache-line boundary.
14322          * Therefore, letting tg3 do so just wastes PCI bandwidth.
14323          *
14324          * Unfortunately, for PCI-E there are only limited
14325          * write-side controls for this, and thus for reads
14326          * we will still get the disconnects.  We'll also waste
14327          * these PCI cycles for both read and write for chips
14328          * other than 5700 and 5701 which do not implement the
14329          * boundary bits.
14330          */
14331         if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
14332                 switch (cacheline_size) {
14333                 case 16:
14334                 case 32:
14335                 case 64:
14336                 case 128:
14337                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14338                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14339                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14340                         } else {
14341                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14342                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14343                         }
14344                         break;
14345
14346                 case 256:
14347                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14348                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14349                         break;
14350
14351                 default:
14352                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14353                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14354                         break;
14355                 }
14356         } else if (tg3_flag(tp, PCI_EXPRESS)) {
14357                 switch (cacheline_size) {
14358                 case 16:
14359                 case 32:
14360                 case 64:
14361                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14362                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14363                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14364                                 break;
14365                         }
14366                         /* fallthrough */
14367                 case 128:
14368                 default:
14369                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14370                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14371                         break;
14372                 }
14373         } else {
14374                 switch (cacheline_size) {
14375                 case 16:
14376                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14377                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14378                                         DMA_RWCTRL_WRITE_BNDRY_16);
14379                                 break;
14380                         }
14381                         /* fallthrough */
14382                 case 32:
14383                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14384                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14385                                         DMA_RWCTRL_WRITE_BNDRY_32);
14386                                 break;
14387                         }
14388                         /* fallthrough */
14389                 case 64:
14390                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14391                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14392                                         DMA_RWCTRL_WRITE_BNDRY_64);
14393                                 break;
14394                         }
14395                         /* fallthrough */
14396                 case 128:
14397                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14398                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14399                                         DMA_RWCTRL_WRITE_BNDRY_128);
14400                                 break;
14401                         }
14402                         /* fallthrough */
14403                 case 256:
14404                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
14405                                 DMA_RWCTRL_WRITE_BNDRY_256);
14406                         break;
14407                 case 512:
14408                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
14409                                 DMA_RWCTRL_WRITE_BNDRY_512);
14410                         break;
14411                 case 1024:
14412                 default:
14413                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14414                                 DMA_RWCTRL_WRITE_BNDRY_1024);
14415                         break;
14416                 }
14417         }
14418
14419 out:
14420         return val;
14421 }
14422
14423 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14424 {
14425         struct tg3_internal_buffer_desc test_desc;
14426         u32 sram_dma_descs;
14427         int i, ret;
14428
14429         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14430
14431         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14432         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14433         tw32(RDMAC_STATUS, 0);
14434         tw32(WDMAC_STATUS, 0);
14435
14436         tw32(BUFMGR_MODE, 0);
14437         tw32(FTQ_RESET, 0);
14438
14439         test_desc.addr_hi = ((u64) buf_dma) >> 32;
14440         test_desc.addr_lo = buf_dma & 0xffffffff;
14441         test_desc.nic_mbuf = 0x00002100;
14442         test_desc.len = size;
14443
14444         /*
14445          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14446          * the *second* time the tg3 driver was getting loaded after an
14447          * initial scan.
14448          *
14449          * Broadcom tells me:
14450          *   ...the DMA engine is connected to the GRC block and a DMA
14451          *   reset may affect the GRC block in some unpredictable way...
14452          *   The behavior of resets to individual blocks has not been tested.
14453          *
14454          * Broadcom noted the GRC reset will also reset all sub-components.
14455          */
14456         if (to_device) {
14457                 test_desc.cqid_sqid = (13 << 8) | 2;
14458
14459                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14460                 udelay(40);
14461         } else {
14462                 test_desc.cqid_sqid = (16 << 8) | 7;
14463
14464                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14465                 udelay(40);
14466         }
14467         test_desc.flags = 0x00000005;
14468
14469         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14470                 u32 val;
14471
14472                 val = *(((u32 *)&test_desc) + i);
14473                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14474                                        sram_dma_descs + (i * sizeof(u32)));
14475                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14476         }
14477         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14478
14479         if (to_device)
14480                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14481         else
14482                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14483
14484         ret = -ENODEV;
14485         for (i = 0; i < 40; i++) {
14486                 u32 val;
14487
14488                 if (to_device)
14489                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14490                 else
14491                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14492                 if ((val & 0xffff) == sram_dma_descs) {
14493                         ret = 0;
14494                         break;
14495                 }
14496
14497                 udelay(100);
14498         }
14499
14500         return ret;
14501 }
14502
14503 #define TEST_BUFFER_SIZE        0x2000
14504
14505 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
14506         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14507         { },
14508 };
14509
14510 static int __devinit tg3_test_dma(struct tg3 *tp)
14511 {
14512         dma_addr_t buf_dma;
14513         u32 *buf, saved_dma_rwctrl;
14514         int ret = 0;
14515
14516         buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14517                                  &buf_dma, GFP_KERNEL);
14518         if (!buf) {
14519                 ret = -ENOMEM;
14520                 goto out_nofree;
14521         }
14522
14523         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14524                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14525
14526         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14527
14528         if (tg3_flag(tp, 57765_PLUS))
14529                 goto out;
14530
14531         if (tg3_flag(tp, PCI_EXPRESS)) {
14532                 /* DMA read watermark not used on PCIE */
14533                 tp->dma_rwctrl |= 0x00180000;
14534         } else if (!tg3_flag(tp, PCIX_MODE)) {
14535                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14536                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14537                         tp->dma_rwctrl |= 0x003f0000;
14538                 else
14539                         tp->dma_rwctrl |= 0x003f000f;
14540         } else {
14541                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14542                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14543                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14544                         u32 read_water = 0x7;
14545
14546                         /* If the 5704 is behind the EPB bridge, we can
14547                          * do the less restrictive ONE_DMA workaround for
14548                          * better performance.
14549                          */
14550                         if (tg3_flag(tp, 40BIT_DMA_BUG) &&
14551                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14552                                 tp->dma_rwctrl |= 0x8000;
14553                         else if (ccval == 0x6 || ccval == 0x7)
14554                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14555
14556                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14557                                 read_water = 4;
14558                         /* Set bit 23 to enable PCIX hw bug fix */
14559                         tp->dma_rwctrl |=
14560                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14561                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14562                                 (1 << 23);
14563                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14564                         /* 5780 always in PCIX mode */
14565                         tp->dma_rwctrl |= 0x00144000;
14566                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14567                         /* 5714 always in PCIX mode */
14568                         tp->dma_rwctrl |= 0x00148000;
14569                 } else {
14570                         tp->dma_rwctrl |= 0x001b000f;
14571                 }
14572         }
14573
14574         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14575             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14576                 tp->dma_rwctrl &= 0xfffffff0;
14577
14578         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14579             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14580                 /* Remove this if it causes problems for some boards. */
14581                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14582
14583                 /* On 5700/5701 chips, we need to set this bit.
14584                  * Otherwise the chip will issue cacheline transactions
14585                  * to streamable DMA memory with not all the byte
14586                  * enables turned on.  This is an error on several
14587                  * RISC PCI controllers, in particular sparc64.
14588                  *
14589                  * On 5703/5704 chips, this bit has been reassigned
14590                  * a different meaning.  In particular, it is used
14591                  * on those chips to enable a PCI-X workaround.
14592                  */
14593                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14594         }
14595
14596         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14597
14598 #if 0
14599         /* Unneeded, already done by tg3_get_invariants.  */
14600         tg3_switch_clocks(tp);
14601 #endif
14602
14603         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14604             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14605                 goto out;
14606
14607         /* It is best to perform DMA test with maximum write burst size
14608          * to expose the 5700/5701 write DMA bug.
14609          */
14610         saved_dma_rwctrl = tp->dma_rwctrl;
14611         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14612         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14613
14614         while (1) {
14615                 u32 *p = buf, i;
14616
14617                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14618                         p[i] = i;
14619
14620                 /* Send the buffer to the chip. */
14621                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14622                 if (ret) {
14623                         dev_err(&tp->pdev->dev,
14624                                 "%s: Buffer write failed. err = %d\n",
14625                                 __func__, ret);
14626                         break;
14627                 }
14628
14629 #if 0
14630                 /* validate data reached card RAM correctly. */
14631                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14632                         u32 val;
14633                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14634                         if (le32_to_cpu(val) != p[i]) {
14635                                 dev_err(&tp->pdev->dev,
14636                                         "%s: Buffer corrupted on device! "
14637                                         "(%d != %d)\n", __func__, val, i);
14638                                 /* ret = -ENODEV here? */
14639                         }
14640                         p[i] = 0;
14641                 }
14642 #endif
14643                 /* Now read it back. */
14644                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14645                 if (ret) {
14646                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14647                                 "err = %d\n", __func__, ret);
14648                         break;
14649                 }
14650
14651                 /* Verify it. */
14652                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14653                         if (p[i] == i)
14654                                 continue;
14655
14656                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14657                             DMA_RWCTRL_WRITE_BNDRY_16) {
14658                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14659                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14660                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14661                                 break;
14662                         } else {
14663                                 dev_err(&tp->pdev->dev,
14664                                         "%s: Buffer corrupted on read back! "
14665                                         "(%d != %d)\n", __func__, p[i], i);
14666                                 ret = -ENODEV;
14667                                 goto out;
14668                         }
14669                 }
14670
14671                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14672                         /* Success. */
14673                         ret = 0;
14674                         break;
14675                 }
14676         }
14677         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14678             DMA_RWCTRL_WRITE_BNDRY_16) {
14679                 /* DMA test passed without adjusting DMA boundary,
14680                  * now look for chipsets that are known to expose the
14681                  * DMA bug without failing the test.
14682                  */
14683                 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
14684                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14685                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14686                 } else {
14687                         /* Safe to use the calculated DMA boundary. */
14688                         tp->dma_rwctrl = saved_dma_rwctrl;
14689                 }
14690
14691                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14692         }
14693
14694 out:
14695         dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
14696 out_nofree:
14697         return ret;
14698 }
14699
14700 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14701 {
14702         if (tg3_flag(tp, 57765_PLUS)) {
14703                 tp->bufmgr_config.mbuf_read_dma_low_water =
14704                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14705                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14706                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14707                 tp->bufmgr_config.mbuf_high_water =
14708                         DEFAULT_MB_HIGH_WATER_57765;
14709
14710                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14711                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14712                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14713                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14714                 tp->bufmgr_config.mbuf_high_water_jumbo =
14715                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14716         } else if (tg3_flag(tp, 5705_PLUS)) {
14717                 tp->bufmgr_config.mbuf_read_dma_low_water =
14718                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14719                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14720                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14721                 tp->bufmgr_config.mbuf_high_water =
14722                         DEFAULT_MB_HIGH_WATER_5705;
14723                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14724                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14725                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14726                         tp->bufmgr_config.mbuf_high_water =
14727                                 DEFAULT_MB_HIGH_WATER_5906;
14728                 }
14729
14730                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14731                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14732                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14733                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14734                 tp->bufmgr_config.mbuf_high_water_jumbo =
14735                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14736         } else {
14737                 tp->bufmgr_config.mbuf_read_dma_low_water =
14738                         DEFAULT_MB_RDMA_LOW_WATER;
14739                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14740                         DEFAULT_MB_MACRX_LOW_WATER;
14741                 tp->bufmgr_config.mbuf_high_water =
14742                         DEFAULT_MB_HIGH_WATER;
14743
14744                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14745                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14746                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14747                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14748                 tp->bufmgr_config.mbuf_high_water_jumbo =
14749                         DEFAULT_MB_HIGH_WATER_JUMBO;
14750         }
14751
14752         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14753         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14754 }
14755
14756 static char * __devinit tg3_phy_string(struct tg3 *tp)
14757 {
14758         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14759         case TG3_PHY_ID_BCM5400:        return "5400";
14760         case TG3_PHY_ID_BCM5401:        return "5401";
14761         case TG3_PHY_ID_BCM5411:        return "5411";
14762         case TG3_PHY_ID_BCM5701:        return "5701";
14763         case TG3_PHY_ID_BCM5703:        return "5703";
14764         case TG3_PHY_ID_BCM5704:        return "5704";
14765         case TG3_PHY_ID_BCM5705:        return "5705";
14766         case TG3_PHY_ID_BCM5750:        return "5750";
14767         case TG3_PHY_ID_BCM5752:        return "5752";
14768         case TG3_PHY_ID_BCM5714:        return "5714";
14769         case TG3_PHY_ID_BCM5780:        return "5780";
14770         case TG3_PHY_ID_BCM5755:        return "5755";
14771         case TG3_PHY_ID_BCM5787:        return "5787";
14772         case TG3_PHY_ID_BCM5784:        return "5784";
14773         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14774         case TG3_PHY_ID_BCM5906:        return "5906";
14775         case TG3_PHY_ID_BCM5761:        return "5761";
14776         case TG3_PHY_ID_BCM5718C:       return "5718C";
14777         case TG3_PHY_ID_BCM5718S:       return "5718S";
14778         case TG3_PHY_ID_BCM57765:       return "57765";
14779         case TG3_PHY_ID_BCM5719C:       return "5719C";
14780         case TG3_PHY_ID_BCM5720C:       return "5720C";
14781         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14782         case 0:                 return "serdes";
14783         default:                return "unknown";
14784         }
14785 }
14786
14787 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14788 {
14789         if (tg3_flag(tp, PCI_EXPRESS)) {
14790                 strcpy(str, "PCI Express");
14791                 return str;
14792         } else if (tg3_flag(tp, PCIX_MODE)) {
14793                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14794
14795                 strcpy(str, "PCIX:");
14796
14797                 if ((clock_ctrl == 7) ||
14798                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14799                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14800                         strcat(str, "133MHz");
14801                 else if (clock_ctrl == 0)
14802                         strcat(str, "33MHz");
14803                 else if (clock_ctrl == 2)
14804                         strcat(str, "50MHz");
14805                 else if (clock_ctrl == 4)
14806                         strcat(str, "66MHz");
14807                 else if (clock_ctrl == 6)
14808                         strcat(str, "100MHz");
14809         } else {
14810                 strcpy(str, "PCI:");
14811                 if (tg3_flag(tp, PCI_HIGH_SPEED))
14812                         strcat(str, "66MHz");
14813                 else
14814                         strcat(str, "33MHz");
14815         }
14816         if (tg3_flag(tp, PCI_32BIT))
14817                 strcat(str, ":32-bit");
14818         else
14819                 strcat(str, ":64-bit");
14820         return str;
14821 }
14822
14823 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14824 {
14825         struct pci_dev *peer;
14826         unsigned int func, devnr = tp->pdev->devfn & ~7;
14827
14828         for (func = 0; func < 8; func++) {
14829                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14830                 if (peer && peer != tp->pdev)
14831                         break;
14832                 pci_dev_put(peer);
14833         }
14834         /* 5704 can be configured in single-port mode, set peer to
14835          * tp->pdev in that case.
14836          */
14837         if (!peer) {
14838                 peer = tp->pdev;
14839                 return peer;
14840         }
14841
14842         /*
14843          * We don't need to keep the refcount elevated; there's no way
14844          * to remove one half of this device without removing the other
14845          */
14846         pci_dev_put(peer);
14847
14848         return peer;
14849 }
14850
14851 static void __devinit tg3_init_coal(struct tg3 *tp)
14852 {
14853         struct ethtool_coalesce *ec = &tp->coal;
14854
14855         memset(ec, 0, sizeof(*ec));
14856         ec->cmd = ETHTOOL_GCOALESCE;
14857         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14858         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14859         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14860         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14861         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14862         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14863         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14864         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14865         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14866
14867         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14868                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14869                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14870                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14871                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14872                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14873         }
14874
14875         if (tg3_flag(tp, 5705_PLUS)) {
14876                 ec->rx_coalesce_usecs_irq = 0;
14877                 ec->tx_coalesce_usecs_irq = 0;
14878                 ec->stats_block_coalesce_usecs = 0;
14879         }
14880 }
14881
14882 static const struct net_device_ops tg3_netdev_ops = {
14883         .ndo_open               = tg3_open,
14884         .ndo_stop               = tg3_close,
14885         .ndo_start_xmit         = tg3_start_xmit,
14886         .ndo_get_stats64        = tg3_get_stats64,
14887         .ndo_validate_addr      = eth_validate_addr,
14888         .ndo_set_multicast_list = tg3_set_rx_mode,
14889         .ndo_set_mac_address    = tg3_set_mac_addr,
14890         .ndo_do_ioctl           = tg3_ioctl,
14891         .ndo_tx_timeout         = tg3_tx_timeout,
14892         .ndo_change_mtu         = tg3_change_mtu,
14893         .ndo_fix_features       = tg3_fix_features,
14894         .ndo_set_features       = tg3_set_features,
14895 #ifdef CONFIG_NET_POLL_CONTROLLER
14896         .ndo_poll_controller    = tg3_poll_controller,
14897 #endif
14898 };
14899
14900 static int __devinit tg3_init_one(struct pci_dev *pdev,
14901                                   const struct pci_device_id *ent)
14902 {
14903         struct net_device *dev;
14904         struct tg3 *tp;
14905         int i, err, pm_cap;
14906         u32 sndmbx, rcvmbx, intmbx;
14907         char str[40];
14908         u64 dma_mask, persist_dma_mask;
14909         u32 hw_features = 0;
14910
14911         printk_once(KERN_INFO "%s\n", version);
14912
14913         err = pci_enable_device(pdev);
14914         if (err) {
14915                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14916                 return err;
14917         }
14918
14919         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14920         if (err) {
14921                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14922                 goto err_out_disable_pdev;
14923         }
14924
14925         pci_set_master(pdev);
14926
14927         /* Find power-management capability. */
14928         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14929         if (pm_cap == 0) {
14930                 dev_err(&pdev->dev,
14931                         "Cannot find Power Management capability, aborting\n");
14932                 err = -EIO;
14933                 goto err_out_free_res;
14934         }
14935
14936         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14937         if (!dev) {
14938                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14939                 err = -ENOMEM;
14940                 goto err_out_free_res;
14941         }
14942
14943         SET_NETDEV_DEV(dev, &pdev->dev);
14944
14945         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14946
14947         tp = netdev_priv(dev);
14948         tp->pdev = pdev;
14949         tp->dev = dev;
14950         tp->pm_cap = pm_cap;
14951         tp->rx_mode = TG3_DEF_RX_MODE;
14952         tp->tx_mode = TG3_DEF_TX_MODE;
14953
14954         if (tg3_debug > 0)
14955                 tp->msg_enable = tg3_debug;
14956         else
14957                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14958
14959         /* The word/byte swap controls here control register access byte
14960          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14961          * setting below.
14962          */
14963         tp->misc_host_ctrl =
14964                 MISC_HOST_CTRL_MASK_PCI_INT |
14965                 MISC_HOST_CTRL_WORD_SWAP |
14966                 MISC_HOST_CTRL_INDIR_ACCESS |
14967                 MISC_HOST_CTRL_PCISTATE_RW;
14968
14969         /* The NONFRM (non-frame) byte/word swap controls take effect
14970          * on descriptor entries, anything which isn't packet data.
14971          *
14972          * The StrongARM chips on the board (one for tx, one for rx)
14973          * are running in big-endian mode.
14974          */
14975         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14976                         GRC_MODE_WSWAP_NONFRM_DATA);
14977 #ifdef __BIG_ENDIAN
14978         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14979 #endif
14980         spin_lock_init(&tp->lock);
14981         spin_lock_init(&tp->indirect_lock);
14982         INIT_WORK(&tp->reset_task, tg3_reset_task);
14983
14984         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14985         if (!tp->regs) {
14986                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14987                 err = -ENOMEM;
14988                 goto err_out_free_dev;
14989         }
14990
14991         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14992         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14993
14994         dev->ethtool_ops = &tg3_ethtool_ops;
14995         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14996         dev->netdev_ops = &tg3_netdev_ops;
14997         dev->irq = pdev->irq;
14998
14999         err = tg3_get_invariants(tp);
15000         if (err) {
15001                 dev_err(&pdev->dev,
15002                         "Problem fetching invariants of chip, aborting\n");
15003                 goto err_out_iounmap;
15004         }
15005
15006         /* The EPB bridge inside 5714, 5715, and 5780 and any
15007          * device behind the EPB cannot support DMA addresses > 40-bit.
15008          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15009          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15010          * do DMA address check in tg3_start_xmit().
15011          */
15012         if (tg3_flag(tp, IS_5788))
15013                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
15014         else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
15015                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
15016 #ifdef CONFIG_HIGHMEM
15017                 dma_mask = DMA_BIT_MASK(64);
15018 #endif
15019         } else
15020                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
15021
15022         /* Configure DMA attributes. */
15023         if (dma_mask > DMA_BIT_MASK(32)) {
15024                 err = pci_set_dma_mask(pdev, dma_mask);
15025                 if (!err) {
15026                         dev->features |= NETIF_F_HIGHDMA;
15027                         err = pci_set_consistent_dma_mask(pdev,
15028                                                           persist_dma_mask);
15029                         if (err < 0) {
15030                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
15031                                         "DMA for consistent allocations\n");
15032                                 goto err_out_iounmap;
15033                         }
15034                 }
15035         }
15036         if (err || dma_mask == DMA_BIT_MASK(32)) {
15037                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
15038                 if (err) {
15039                         dev_err(&pdev->dev,
15040                                 "No usable DMA configuration, aborting\n");
15041                         goto err_out_iounmap;
15042                 }
15043         }
15044
15045         tg3_init_bufmgr_config(tp);
15046
15047         /* Selectively allow TSO based on operating conditions */
15048         if ((tg3_flag(tp, HW_TSO_1) ||
15049              tg3_flag(tp, HW_TSO_2) ||
15050              tg3_flag(tp, HW_TSO_3)) ||
15051             (tp->fw_needed && !tg3_flag(tp, ENABLE_ASF)))
15052                 tg3_flag_set(tp, TSO_CAPABLE);
15053         else {
15054                 tg3_flag_clear(tp, TSO_CAPABLE);
15055                 tg3_flag_clear(tp, TSO_BUG);
15056                 tp->fw_needed = NULL;
15057         }
15058
15059         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
15060                 tp->fw_needed = FIRMWARE_TG3;
15061
15062         /* TSO is on by default on chips that support hardware TSO.
15063          * Firmware TSO on older chips gives lower performance, so it
15064          * is off by default, but can be enabled using ethtool.
15065          */
15066         if ((tg3_flag(tp, HW_TSO_1) ||
15067              tg3_flag(tp, HW_TSO_2) ||
15068              tg3_flag(tp, HW_TSO_3)) &&
15069             (dev->features & NETIF_F_IP_CSUM))
15070                 hw_features |= NETIF_F_TSO;
15071         if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
15072                 if (dev->features & NETIF_F_IPV6_CSUM)
15073                         hw_features |= NETIF_F_TSO6;
15074                 if (tg3_flag(tp, HW_TSO_3) ||
15075                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
15076                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15077                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
15078                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15079                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15080                         hw_features |= NETIF_F_TSO_ECN;
15081         }
15082
15083         dev->hw_features |= hw_features;
15084         dev->features |= hw_features;
15085         dev->vlan_features |= hw_features;
15086
15087         /*
15088          * Add loopback capability only for a subset of devices that support
15089          * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
15090          * loopback for the remaining devices.
15091          */
15092         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
15093             !tg3_flag(tp, CPMU_PRESENT))
15094                 /* Add the loopback capability */
15095                 dev->hw_features |= NETIF_F_LOOPBACK;
15096
15097         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15098             !tg3_flag(tp, TSO_CAPABLE) &&
15099             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15100                 tg3_flag_set(tp, MAX_RXPEND_64);
15101                 tp->rx_pending = 63;
15102         }
15103
15104         err = tg3_get_device_address(tp);
15105         if (err) {
15106                 dev_err(&pdev->dev,
15107                         "Could not obtain valid ethernet address, aborting\n");
15108                 goto err_out_iounmap;
15109         }
15110
15111         if (tg3_flag(tp, ENABLE_APE)) {
15112                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15113                 if (!tp->aperegs) {
15114                         dev_err(&pdev->dev,
15115                                 "Cannot map APE registers, aborting\n");
15116                         err = -ENOMEM;
15117                         goto err_out_iounmap;
15118                 }
15119
15120                 tg3_ape_lock_init(tp);
15121
15122                 if (tg3_flag(tp, ENABLE_ASF))
15123                         tg3_read_dash_ver(tp);
15124         }
15125
15126         /*
15127          * Reset chip in case UNDI or EFI driver did not shutdown
15128          * DMA self test will enable WDMAC and we'll see (spurious)
15129          * pending DMA on the PCI bus at that point.
15130          */
15131         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15132             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15133                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15134                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15135         }
15136
15137         err = tg3_test_dma(tp);
15138         if (err) {
15139                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
15140                 goto err_out_apeunmap;
15141         }
15142
15143         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15144         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15145         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
15146         for (i = 0; i < tp->irq_max; i++) {
15147                 struct tg3_napi *tnapi = &tp->napi[i];
15148
15149                 tnapi->tp = tp;
15150                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15151
15152                 tnapi->int_mbox = intmbx;
15153                 if (i < 4)
15154                         intmbx += 0x8;
15155                 else
15156                         intmbx += 0x4;
15157
15158                 tnapi->consmbox = rcvmbx;
15159                 tnapi->prodmbox = sndmbx;
15160
15161                 if (i)
15162                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
15163                 else
15164                         tnapi->coal_now = HOSTCC_MODE_NOW;
15165
15166                 if (!tg3_flag(tp, SUPPORT_MSIX))
15167                         break;
15168
15169                 /*
15170                  * If we support MSIX, we'll be using RSS.  If we're using
15171                  * RSS, the first vector only handles link interrupts and the
15172                  * remaining vectors handle rx and tx interrupts.  Reuse the
15173                  * mailbox values for the next iteration.  The values we setup
15174                  * above are still useful for the single vectored mode.
15175                  */
15176                 if (!i)
15177                         continue;
15178
15179                 rcvmbx += 0x8;
15180
15181                 if (sndmbx & 0x4)
15182                         sndmbx -= 0x4;
15183                 else
15184                         sndmbx += 0xc;
15185         }
15186
15187         tg3_init_coal(tp);
15188
15189         pci_set_drvdata(pdev, dev);
15190
15191         err = register_netdev(dev);
15192         if (err) {
15193                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
15194                 goto err_out_apeunmap;
15195         }
15196
15197         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15198                     tp->board_part_number,
15199                     tp->pci_chip_rev_id,
15200                     tg3_bus_string(tp, str),
15201                     dev->dev_addr);
15202
15203         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
15204                 struct phy_device *phydev;
15205                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
15206                 netdev_info(dev,
15207                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15208                             phydev->drv->name, dev_name(&phydev->dev));
15209         } else {
15210                 char *ethtype;
15211
15212                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15213                         ethtype = "10/100Base-TX";
15214                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15215                         ethtype = "1000Base-SX";
15216                 else
15217                         ethtype = "10/100/1000Base-T";
15218
15219                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
15220                             "(WireSpeed[%d], EEE[%d])\n",
15221                             tg3_phy_string(tp), ethtype,
15222                             (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
15223                             (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
15224         }
15225
15226         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15227                     (dev->features & NETIF_F_RXCSUM) != 0,
15228                     tg3_flag(tp, USE_LINKCHG_REG) != 0,
15229                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15230                     tg3_flag(tp, ENABLE_ASF) != 0,
15231                     tg3_flag(tp, TSO_CAPABLE) != 0);
15232         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15233                     tp->dma_rwctrl,
15234                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15235                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15236
15237         pci_save_state(pdev);
15238
15239         return 0;
15240
15241 err_out_apeunmap:
15242         if (tp->aperegs) {
15243                 iounmap(tp->aperegs);
15244                 tp->aperegs = NULL;
15245         }
15246
15247 err_out_iounmap:
15248         if (tp->regs) {
15249                 iounmap(tp->regs);
15250                 tp->regs = NULL;
15251         }
15252
15253 err_out_free_dev:
15254         free_netdev(dev);
15255
15256 err_out_free_res:
15257         pci_release_regions(pdev);
15258
15259 err_out_disable_pdev:
15260         pci_disable_device(pdev);
15261         pci_set_drvdata(pdev, NULL);
15262         return err;
15263 }
15264
15265 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15266 {
15267         struct net_device *dev = pci_get_drvdata(pdev);
15268
15269         if (dev) {
15270                 struct tg3 *tp = netdev_priv(dev);
15271
15272                 if (tp->fw)
15273                         release_firmware(tp->fw);
15274
15275                 cancel_work_sync(&tp->reset_task);
15276
15277                 if (!tg3_flag(tp, USE_PHYLIB)) {
15278                         tg3_phy_fini(tp);
15279                         tg3_mdio_fini(tp);
15280                 }
15281
15282                 unregister_netdev(dev);
15283                 if (tp->aperegs) {
15284                         iounmap(tp->aperegs);
15285                         tp->aperegs = NULL;
15286                 }
15287                 if (tp->regs) {
15288                         iounmap(tp->regs);
15289                         tp->regs = NULL;
15290                 }
15291                 free_netdev(dev);
15292                 pci_release_regions(pdev);
15293                 pci_disable_device(pdev);
15294                 pci_set_drvdata(pdev, NULL);
15295         }
15296 }
15297
15298 #ifdef CONFIG_PM_SLEEP
15299 static int tg3_suspend(struct device *device)
15300 {
15301         struct pci_dev *pdev = to_pci_dev(device);
15302         struct net_device *dev = pci_get_drvdata(pdev);
15303         struct tg3 *tp = netdev_priv(dev);
15304         int err;
15305
15306         if (!netif_running(dev))
15307                 return 0;
15308
15309         flush_work_sync(&tp->reset_task);
15310         tg3_phy_stop(tp);
15311         tg3_netif_stop(tp);
15312
15313         del_timer_sync(&tp->timer);
15314
15315         tg3_full_lock(tp, 1);
15316         tg3_disable_ints(tp);
15317         tg3_full_unlock(tp);
15318
15319         netif_device_detach(dev);
15320
15321         tg3_full_lock(tp, 0);
15322         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15323         tg3_flag_clear(tp, INIT_COMPLETE);
15324         tg3_full_unlock(tp);
15325
15326         err = tg3_power_down_prepare(tp);
15327         if (err) {
15328                 int err2;
15329
15330                 tg3_full_lock(tp, 0);
15331
15332                 tg3_flag_set(tp, INIT_COMPLETE);
15333                 err2 = tg3_restart_hw(tp, 1);
15334                 if (err2)
15335                         goto out;
15336
15337                 tp->timer.expires = jiffies + tp->timer_offset;
15338                 add_timer(&tp->timer);
15339
15340                 netif_device_attach(dev);
15341                 tg3_netif_start(tp);
15342
15343 out:
15344                 tg3_full_unlock(tp);
15345
15346                 if (!err2)
15347                         tg3_phy_start(tp);
15348         }
15349
15350         return err;
15351 }
15352
15353 static int tg3_resume(struct device *device)
15354 {
15355         struct pci_dev *pdev = to_pci_dev(device);
15356         struct net_device *dev = pci_get_drvdata(pdev);
15357         struct tg3 *tp = netdev_priv(dev);
15358         int err;
15359
15360         if (!netif_running(dev))
15361                 return 0;
15362
15363         netif_device_attach(dev);
15364
15365         tg3_full_lock(tp, 0);
15366
15367         tg3_flag_set(tp, INIT_COMPLETE);
15368         err = tg3_restart_hw(tp, 1);
15369         if (err)
15370                 goto out;
15371
15372         tp->timer.expires = jiffies + tp->timer_offset;
15373         add_timer(&tp->timer);
15374
15375         tg3_netif_start(tp);
15376
15377 out:
15378         tg3_full_unlock(tp);
15379
15380         if (!err)
15381                 tg3_phy_start(tp);
15382
15383         return err;
15384 }
15385
15386 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15387 #define TG3_PM_OPS (&tg3_pm_ops)
15388
15389 #else
15390
15391 #define TG3_PM_OPS NULL
15392
15393 #endif /* CONFIG_PM_SLEEP */
15394
15395 /**
15396  * tg3_io_error_detected - called when PCI error is detected
15397  * @pdev: Pointer to PCI device
15398  * @state: The current pci connection state
15399  *
15400  * This function is called after a PCI bus error affecting
15401  * this device has been detected.
15402  */
15403 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
15404                                               pci_channel_state_t state)
15405 {
15406         struct net_device *netdev = pci_get_drvdata(pdev);
15407         struct tg3 *tp = netdev_priv(netdev);
15408         pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
15409
15410         netdev_info(netdev, "PCI I/O error detected\n");
15411
15412         rtnl_lock();
15413
15414         if (!netif_running(netdev))
15415                 goto done;
15416
15417         tg3_phy_stop(tp);
15418
15419         tg3_netif_stop(tp);
15420
15421         del_timer_sync(&tp->timer);
15422         tg3_flag_clear(tp, RESTART_TIMER);
15423
15424         /* Want to make sure that the reset task doesn't run */
15425         cancel_work_sync(&tp->reset_task);
15426         tg3_flag_clear(tp, TX_RECOVERY_PENDING);
15427         tg3_flag_clear(tp, RESTART_TIMER);
15428
15429         netif_device_detach(netdev);
15430
15431         /* Clean up software state, even if MMIO is blocked */
15432         tg3_full_lock(tp, 0);
15433         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
15434         tg3_full_unlock(tp);
15435
15436 done:
15437         if (state == pci_channel_io_perm_failure)
15438                 err = PCI_ERS_RESULT_DISCONNECT;
15439         else
15440                 pci_disable_device(pdev);
15441
15442         rtnl_unlock();
15443
15444         return err;
15445 }
15446
15447 /**
15448  * tg3_io_slot_reset - called after the pci bus has been reset.
15449  * @pdev: Pointer to PCI device
15450  *
15451  * Restart the card from scratch, as if from a cold-boot.
15452  * At this point, the card has exprienced a hard reset,
15453  * followed by fixups by BIOS, and has its config space
15454  * set up identically to what it was at cold boot.
15455  */
15456 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
15457 {
15458         struct net_device *netdev = pci_get_drvdata(pdev);
15459         struct tg3 *tp = netdev_priv(netdev);
15460         pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
15461         int err;
15462
15463         rtnl_lock();
15464
15465         if (pci_enable_device(pdev)) {
15466                 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
15467                 goto done;
15468         }
15469
15470         pci_set_master(pdev);
15471         pci_restore_state(pdev);
15472         pci_save_state(pdev);
15473
15474         if (!netif_running(netdev)) {
15475                 rc = PCI_ERS_RESULT_RECOVERED;
15476                 goto done;
15477         }
15478
15479         err = tg3_power_up(tp);
15480         if (err) {
15481                 netdev_err(netdev, "Failed to restore register access.\n");
15482                 goto done;
15483         }
15484
15485         rc = PCI_ERS_RESULT_RECOVERED;
15486
15487 done:
15488         rtnl_unlock();
15489
15490         return rc;
15491 }
15492
15493 /**
15494  * tg3_io_resume - called when traffic can start flowing again.
15495  * @pdev: Pointer to PCI device
15496  *
15497  * This callback is called when the error recovery driver tells
15498  * us that its OK to resume normal operation.
15499  */
15500 static void tg3_io_resume(struct pci_dev *pdev)
15501 {
15502         struct net_device *netdev = pci_get_drvdata(pdev);
15503         struct tg3 *tp = netdev_priv(netdev);
15504         int err;
15505
15506         rtnl_lock();
15507
15508         if (!netif_running(netdev))
15509                 goto done;
15510
15511         tg3_full_lock(tp, 0);
15512         tg3_flag_set(tp, INIT_COMPLETE);
15513         err = tg3_restart_hw(tp, 1);
15514         tg3_full_unlock(tp);
15515         if (err) {
15516                 netdev_err(netdev, "Cannot restart hardware after reset.\n");
15517                 goto done;
15518         }
15519
15520         netif_device_attach(netdev);
15521
15522         tp->timer.expires = jiffies + tp->timer_offset;
15523         add_timer(&tp->timer);
15524
15525         tg3_netif_start(tp);
15526
15527         tg3_phy_start(tp);
15528
15529 done:
15530         rtnl_unlock();
15531 }
15532
15533 static struct pci_error_handlers tg3_err_handler = {
15534         .error_detected = tg3_io_error_detected,
15535         .slot_reset     = tg3_io_slot_reset,
15536         .resume         = tg3_io_resume
15537 };
15538
15539 static struct pci_driver tg3_driver = {
15540         .name           = DRV_MODULE_NAME,
15541         .id_table       = tg3_pci_tbl,
15542         .probe          = tg3_init_one,
15543         .remove         = __devexit_p(tg3_remove_one),
15544         .err_handler    = &tg3_err_handler,
15545         .driver.pm      = TG3_PM_OPS,
15546 };
15547
15548 static int __init tg3_init(void)
15549 {
15550         return pci_register_driver(&tg3_driver);
15551 }
15552
15553 static void __exit tg3_cleanup(void)
15554 {
15555         pci_unregister_driver(&tg3_driver);
15556 }
15557
15558 module_init(tg3_init);
15559 module_exit(tg3_cleanup);