1 // SPDX-License-Identifier: GPL-2.0+
4 * Author: Amit Singh Tomar, amittomer25@gmail.com
6 * Ethernet driver for H3/A64/A83T based SoC's
8 * It is derived from the work done by
9 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
14 #include <asm/arch/clock.h>
15 #include <asm/arch/gpio.h>
18 #include <fdt_support.h>
19 #include <linux/err.h>
23 #include <dt-bindings/pinctrl/sun4i-a10.h>
25 #include <asm-generic/gpio.h>
28 #define MDIO_CMD_MII_BUSY BIT(0)
29 #define MDIO_CMD_MII_WRITE BIT(1)
31 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
32 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
33 #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
34 #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
36 #define CONFIG_TX_DESCR_NUM 32
37 #define CONFIG_RX_DESCR_NUM 32
38 #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
41 * The datasheet says that each descriptor can transfers up to 4096 bytes
42 * But later, the register documentation reduces that value to 2048,
43 * using 2048 cause strange behaviours and even BSP driver use 2047
45 #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
47 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
48 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
50 #define H3_EPHY_DEFAULT_VALUE 0x58000
51 #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
52 #define H3_EPHY_ADDR_SHIFT 20
53 #define REG_PHY_ADDR_MASK GENMASK(4, 0)
54 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
55 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
56 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
58 #define SC_RMII_EN BIT(13)
59 #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
60 #define SC_ETCS_MASK GENMASK(1, 0)
61 #define SC_ETCS_EXT_GMII 0x1
62 #define SC_ETCS_INT_GMII 0x2
64 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
66 #define AHB_GATE_OFFSET_EPHY 0
69 #define SUN8I_IOMUX_H3 2
72 /* H3/A64 EMAC Register's offset */
73 #define EMAC_CTL0 0x00
74 #define EMAC_CTL1 0x04
75 #define EMAC_INT_STA 0x08
76 #define EMAC_INT_EN 0x0c
77 #define EMAC_TX_CTL0 0x10
78 #define EMAC_TX_CTL1 0x14
79 #define EMAC_TX_FLOW_CTL 0x1c
80 #define EMAC_TX_DMA_DESC 0x20
81 #define EMAC_RX_CTL0 0x24
82 #define EMAC_RX_CTL1 0x28
83 #define EMAC_RX_DMA_DESC 0x34
84 #define EMAC_MII_CMD 0x48
85 #define EMAC_MII_DATA 0x4c
86 #define EMAC_ADDR0_HIGH 0x50
87 #define EMAC_ADDR0_LOW 0x54
88 #define EMAC_TX_DMA_STA 0xb0
89 #define EMAC_TX_CUR_DESC 0xb4
90 #define EMAC_TX_CUR_BUF 0xb8
91 #define EMAC_RX_DMA_STA 0xc0
92 #define EMAC_RX_CUR_DESC 0xc4
94 DECLARE_GLOBAL_DATA_PTR;
102 struct emac_dma_desc {
107 } __aligned(ARCH_DMA_MINALIGN);
109 struct emac_eth_dev {
110 struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
111 struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
112 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
113 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
125 bool use_internal_phy;
127 enum emac_variant variant;
129 phys_addr_t sysctl_reg;
130 struct phy_device *phydev;
132 #ifdef CONFIG_DM_GPIO
133 struct gpio_desc reset_gpio;
138 struct sun8i_eth_pdata {
139 struct eth_pdata eth_pdata;
144 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
146 struct udevice *dev = bus->priv;
147 struct emac_eth_dev *priv = dev_get_priv(dev);
150 int timeout = CONFIG_MDIO_TIMEOUT;
152 miiaddr &= ~MDIO_CMD_MII_WRITE;
153 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
154 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
155 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
157 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
159 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
160 MDIO_CMD_MII_PHY_ADDR_MASK;
162 miiaddr |= MDIO_CMD_MII_BUSY;
164 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
166 start = get_timer(0);
167 while (get_timer(start) < timeout) {
168 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
169 return readl(priv->mac_reg + EMAC_MII_DATA);
176 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
179 struct udevice *dev = bus->priv;
180 struct emac_eth_dev *priv = dev_get_priv(dev);
183 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
185 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
186 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
187 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
189 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
190 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
191 MDIO_CMD_MII_PHY_ADDR_MASK;
193 miiaddr |= MDIO_CMD_MII_WRITE;
194 miiaddr |= MDIO_CMD_MII_BUSY;
196 writel(val, priv->mac_reg + EMAC_MII_DATA);
197 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
199 start = get_timer(0);
200 while (get_timer(start) < timeout) {
201 if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
202 MDIO_CMD_MII_BUSY)) {
212 static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
214 u32 macid_lo, macid_hi;
216 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
218 macid_hi = mac_id[4] + (mac_id[5] << 8);
220 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
221 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
226 static void sun8i_adjust_link(struct emac_eth_dev *priv,
227 struct phy_device *phydev)
231 v = readl(priv->mac_reg + EMAC_CTL0);
240 switch (phydev->speed) {
251 writel(v, priv->mac_reg + EMAC_CTL0);
254 static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
256 if (priv->use_internal_phy) {
257 /* H3 based SoC's that has an Internal 100MBit PHY
258 * needs to be configured and powered up before use
260 *reg &= ~H3_EPHY_DEFAULT_MASK;
261 *reg |= H3_EPHY_DEFAULT_VALUE;
262 *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
263 *reg &= ~H3_EPHY_SHUTDOWN;
264 *reg |= H3_EPHY_SELECT;
266 /* This is to select External Gigabit PHY on
267 * the boards with H3 SoC.
269 *reg &= ~H3_EPHY_SELECT;
274 static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
279 reg = readl(priv->sysctl_reg + 0x30);
281 if (priv->variant == H3_EMAC) {
282 ret = sun8i_emac_set_syscon_ephy(priv, ®);
287 reg &= ~(SC_ETCS_MASK | SC_EPIT);
288 if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
291 switch (priv->interface) {
292 case PHY_INTERFACE_MODE_MII:
295 case PHY_INTERFACE_MODE_RGMII:
296 reg |= SC_EPIT | SC_ETCS_INT_GMII;
298 case PHY_INTERFACE_MODE_RMII:
299 if (priv->variant == H3_EMAC ||
300 priv->variant == A64_EMAC) {
301 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
304 /* RMII not supported on A83T */
306 debug("%s: Invalid PHY interface\n", __func__);
310 writel(reg, priv->sysctl_reg + 0x30);
315 static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
317 struct phy_device *phydev;
319 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
323 phy_connect_dev(phydev, dev);
325 priv->phydev = phydev;
326 phy_config(priv->phydev);
331 static void rx_descs_init(struct emac_eth_dev *priv)
333 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
334 char *rxbuffs = &priv->rxbuffer[0];
335 struct emac_dma_desc *desc_p;
338 /* flush Rx buffers */
339 flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
342 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
343 desc_p = &desc_table_p[idx];
344 desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
346 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
347 desc_p->st |= CONFIG_ETH_RXSIZE;
348 desc_p->status = BIT(31);
351 /* Correcting the last pointer of the chain */
352 desc_p->next = (uintptr_t)&desc_table_p[0];
354 flush_dcache_range((uintptr_t)priv->rx_chain,
355 (uintptr_t)priv->rx_chain +
356 sizeof(priv->rx_chain));
358 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
359 priv->rx_currdescnum = 0;
362 static void tx_descs_init(struct emac_eth_dev *priv)
364 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
365 char *txbuffs = &priv->txbuffer[0];
366 struct emac_dma_desc *desc_p;
369 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
370 desc_p = &desc_table_p[idx];
371 desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
373 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
374 desc_p->status = (1 << 31);
378 /* Correcting the last pointer of the chain */
379 desc_p->next = (uintptr_t)&desc_table_p[0];
381 /* Flush all Tx buffer descriptors */
382 flush_dcache_range((uintptr_t)priv->tx_chain,
383 (uintptr_t)priv->tx_chain +
384 sizeof(priv->tx_chain));
386 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
387 priv->tx_currdescnum = 0;
390 static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
395 reg = readl((priv->mac_reg + EMAC_CTL1));
399 setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
401 reg = readl(priv->mac_reg + EMAC_CTL1);
402 } while ((reg & 0x01) != 0 && (--timeout));
404 printf("%s: Timeout\n", __func__);
409 /* Rewrite mac address after reset */
410 _sun8i_write_hwaddr(priv, enetaddr);
412 v = readl(priv->mac_reg + EMAC_TX_CTL1);
413 /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
415 writel(v, priv->mac_reg + EMAC_TX_CTL1);
417 v = readl(priv->mac_reg + EMAC_RX_CTL1);
418 /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
419 * complete frame has been written to RX DMA FIFO
422 writel(v, priv->mac_reg + EMAC_RX_CTL1);
425 writel(8 << 24, priv->mac_reg + EMAC_CTL1);
427 /* Initialize rx/tx descriptors */
432 phy_startup(priv->phydev);
434 sun8i_adjust_link(priv, priv->phydev);
437 v = readl(priv->mac_reg + EMAC_RX_CTL1);
439 writel(v, priv->mac_reg + EMAC_RX_CTL1);
441 v = readl(priv->mac_reg + EMAC_TX_CTL1);
443 writel(v, priv->mac_reg + EMAC_TX_CTL1);
446 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
447 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
452 static int parse_phy_pins(struct udevice *dev)
454 struct emac_eth_dev *priv = dev_get_priv(dev);
456 const char *pin_name;
457 int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
459 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
462 printf("WARNING: emac: cannot find pinctrl-0 node\n");
466 drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
467 "drive-strength", ~0);
470 drive = SUN4I_PINCTRL_10_MA;
471 else if (drive <= 20)
472 drive = SUN4I_PINCTRL_20_MA;
473 else if (drive <= 30)
474 drive = SUN4I_PINCTRL_30_MA;
476 drive = SUN4I_PINCTRL_40_MA;
479 if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
480 pull = SUN4I_PINCTRL_PULL_UP;
481 else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
482 pull = SUN4I_PINCTRL_PULL_DOWN;
487 pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
492 pin = sunxi_name_to_gpio(pin_name);
496 if (priv->variant == H3_EMAC)
497 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3);
499 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX);
502 sunxi_gpio_set_drv(pin, drive);
504 sunxi_gpio_set_pull(pin, pull);
508 printf("WARNING: emac: cannot find pins property\n");
515 static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
517 u32 status, desc_num = priv->rx_currdescnum;
518 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
519 int length = -EAGAIN;
521 uintptr_t desc_start = (uintptr_t)desc_p;
522 uintptr_t desc_end = desc_start +
523 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
525 ulong data_start = (uintptr_t)desc_p->buf_addr;
528 /* Invalidate entire buffer descriptor */
529 invalidate_dcache_range(desc_start, desc_end);
531 status = desc_p->status;
533 /* Check for DMA own bit */
534 if (!(status & BIT(31))) {
535 length = (desc_p->status >> 16) & 0x3FFF;
539 debug("RX: Bad Packet (runt)\n");
542 data_end = data_start + length;
543 /* Invalidate received data */
544 invalidate_dcache_range(rounddown(data_start,
549 if (length > CONFIG_ETH_RXSIZE) {
550 printf("Received packet is too big (len=%d)\n",
554 *packetp = (uchar *)(ulong)desc_p->buf_addr;
562 static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
565 u32 v, desc_num = priv->tx_currdescnum;
566 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
567 uintptr_t desc_start = (uintptr_t)desc_p;
568 uintptr_t desc_end = desc_start +
569 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
571 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
572 uintptr_t data_end = data_start +
573 roundup(len, ARCH_DMA_MINALIGN);
575 /* Invalidate entire buffer descriptor */
576 invalidate_dcache_range(desc_start, desc_end);
579 /* Mandatory undocumented bit */
580 desc_p->st |= BIT(24);
582 memcpy((void *)data_start, packet, len);
584 /* Flush data to be sent */
585 flush_dcache_range(data_start, data_end);
588 desc_p->st |= BIT(30);
589 desc_p->st |= BIT(31);
592 desc_p->st |= BIT(29);
593 desc_p->status = BIT(31);
595 /*Descriptors st and status field has changed, so FLUSH it */
596 flush_dcache_range(desc_start, desc_end);
598 /* Move to next Descriptor and wrap around */
599 if (++desc_num >= CONFIG_TX_DESCR_NUM)
601 priv->tx_currdescnum = desc_num;
604 v = readl(priv->mac_reg + EMAC_TX_CTL1);
605 v |= BIT(31);/* mandatory */
606 v |= BIT(30);/* mandatory */
607 writel(v, priv->mac_reg + EMAC_TX_CTL1);
612 static int sun8i_eth_write_hwaddr(struct udevice *dev)
614 struct eth_pdata *pdata = dev_get_platdata(dev);
615 struct emac_eth_dev *priv = dev_get_priv(dev);
617 return _sun8i_write_hwaddr(priv, pdata->enetaddr);
620 static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
622 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
624 if (priv->variant == H3_EMAC) {
625 /* Only H3/H5 have clock controls for internal EPHY */
626 if (priv->use_internal_phy) {
627 /* Set clock gating for ephy */
628 setbits_le32(&ccm->bus_gate4,
629 BIT(AHB_GATE_OFFSET_EPHY));
632 setbits_le32(&ccm->ahb_reset2_cfg,
633 BIT(AHB_RESET_OFFSET_EPHY));
637 /* Set clock gating for emac */
638 setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
641 setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
644 #if defined(CONFIG_DM_GPIO)
645 static int sun8i_mdio_reset(struct mii_dev *bus)
647 struct udevice *dev = bus->priv;
648 struct emac_eth_dev *priv = dev_get_priv(dev);
649 struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
652 if (!dm_gpio_is_valid(&priv->reset_gpio))
656 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
660 udelay(pdata->reset_delays[0]);
662 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
666 udelay(pdata->reset_delays[1]);
668 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
672 udelay(pdata->reset_delays[2]);
678 static int sun8i_mdio_init(const char *name, struct udevice *priv)
680 struct mii_dev *bus = mdio_alloc();
683 debug("Failed to allocate MDIO bus\n");
687 bus->read = sun8i_mdio_read;
688 bus->write = sun8i_mdio_write;
689 snprintf(bus->name, sizeof(bus->name), name);
690 bus->priv = (void *)priv;
691 #if defined(CONFIG_DM_GPIO)
692 bus->reset = sun8i_mdio_reset;
695 return mdio_register(bus);
698 static int sun8i_emac_eth_start(struct udevice *dev)
700 struct eth_pdata *pdata = dev_get_platdata(dev);
702 return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
705 static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
707 struct emac_eth_dev *priv = dev_get_priv(dev);
709 return _sun8i_emac_eth_send(priv, packet, length);
712 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
714 struct emac_eth_dev *priv = dev_get_priv(dev);
716 return _sun8i_eth_recv(priv, packetp);
719 static int _sun8i_free_pkt(struct emac_eth_dev *priv)
721 u32 desc_num = priv->rx_currdescnum;
722 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
723 uintptr_t desc_start = (uintptr_t)desc_p;
724 uintptr_t desc_end = desc_start +
725 roundup(sizeof(u32), ARCH_DMA_MINALIGN);
727 /* Make the current descriptor valid again */
728 desc_p->status |= BIT(31);
730 /* Flush Status field of descriptor */
731 flush_dcache_range(desc_start, desc_end);
733 /* Move to next desc and wrap-around condition. */
734 if (++desc_num >= CONFIG_RX_DESCR_NUM)
736 priv->rx_currdescnum = desc_num;
741 static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
744 struct emac_eth_dev *priv = dev_get_priv(dev);
746 return _sun8i_free_pkt(priv);
749 static void sun8i_emac_eth_stop(struct udevice *dev)
751 struct emac_eth_dev *priv = dev_get_priv(dev);
753 /* Stop Rx/Tx transmitter */
754 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
755 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
758 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
760 phy_shutdown(priv->phydev);
763 static int sun8i_emac_eth_probe(struct udevice *dev)
765 struct eth_pdata *pdata = dev_get_platdata(dev);
766 struct emac_eth_dev *priv = dev_get_priv(dev);
768 priv->mac_reg = (void *)pdata->iobase;
770 sun8i_emac_board_setup(priv);
771 sun8i_emac_set_syscon(priv);
773 sun8i_mdio_init(dev->name, dev);
774 priv->bus = miiphy_get_dev_by_name(dev->name);
776 return sun8i_phy_init(priv, dev);
779 static const struct eth_ops sun8i_emac_eth_ops = {
780 .start = sun8i_emac_eth_start,
781 .write_hwaddr = sun8i_eth_write_hwaddr,
782 .send = sun8i_emac_eth_send,
783 .recv = sun8i_emac_eth_recv,
784 .free_pkt = sun8i_eth_free_pkt,
785 .stop = sun8i_emac_eth_stop,
788 static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
790 struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
791 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
792 struct emac_eth_dev *priv = dev_get_priv(dev);
793 const char *phy_mode;
795 int node = dev_of_offset(dev);
797 #ifdef CONFIG_DM_GPIO
798 int reset_flags = GPIOD_IS_OUT;
802 pdata->iobase = devfdt_get_addr(dev);
803 if (pdata->iobase == FDT_ADDR_T_NONE) {
804 debug("%s: Cannot find MAC base address\n", __func__);
808 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
810 debug("%s: cannot find syscon node\n", __func__);
813 reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
815 debug("%s: cannot find reg property in syscon node\n",
819 priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
821 if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
822 debug("%s: Cannot find syscon base address\n", __func__);
826 pdata->phy_interface = -1;
828 priv->use_internal_phy = false;
830 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
832 debug("%s: Cannot find PHY address\n", __func__);
835 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
837 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
840 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
841 printf("phy interface%d\n", pdata->phy_interface);
843 if (pdata->phy_interface == -1) {
844 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
848 priv->variant = dev_get_driver_data(dev);
850 if (!priv->variant) {
851 printf("%s: Missing variant\n", __func__);
855 if (priv->variant == H3_EMAC) {
856 int parent = fdt_parent_offset(gd->fdt_blob, offset);
859 !fdt_node_check_compatible(gd->fdt_blob, parent,
860 "allwinner,sun8i-h3-mdio-internal"))
861 priv->use_internal_phy = true;
864 priv->interface = pdata->phy_interface;
866 if (!priv->use_internal_phy)
869 #ifdef CONFIG_DM_GPIO
870 if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
871 "snps,reset-active-low"))
872 reset_flags |= GPIOD_ACTIVE_LOW;
874 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
875 &priv->reset_gpio, reset_flags);
878 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
879 "snps,reset-delays-us",
880 sun8i_pdata->reset_delays, 3);
881 } else if (ret == -ENOENT) {
889 static const struct udevice_id sun8i_emac_eth_ids[] = {
890 {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
891 {.compatible = "allwinner,sun50i-a64-emac",
892 .data = (uintptr_t)A64_EMAC },
893 {.compatible = "allwinner,sun8i-a83t-emac",
894 .data = (uintptr_t)A83T_EMAC },
898 U_BOOT_DRIVER(eth_sun8i_emac) = {
899 .name = "eth_sun8i_emac",
901 .of_match = sun8i_emac_eth_ids,
902 .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
903 .probe = sun8i_emac_eth_probe,
904 .ops = &sun8i_emac_eth_ops,
905 .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
906 .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
907 .flags = DM_FLAG_ALLOC_PRIV_DMA,