1 // SPDX-License-Identifier: GPL-2.0+
4 * Author: Amit Singh Tomar, amittomer25@gmail.com
6 * Ethernet driver for H3/A64/A83T based SoC's
8 * It is derived from the work done by
9 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
15 #include <asm/cache.h>
16 #include <asm/global_data.h>
22 #include <fdt_support.h>
23 #include <dm/device_compat.h>
24 #include <linux/bitops.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
33 #define MDIO_CMD_MII_BUSY BIT(0)
34 #define MDIO_CMD_MII_WRITE BIT(1)
36 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
37 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
38 #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
39 #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
40 #define MDIO_CMD_MII_CLK_CSR_DIV_16 0x0
41 #define MDIO_CMD_MII_CLK_CSR_DIV_32 0x1
42 #define MDIO_CMD_MII_CLK_CSR_DIV_64 0x2
43 #define MDIO_CMD_MII_CLK_CSR_DIV_128 0x3
44 #define MDIO_CMD_MII_CLK_CSR_SHIFT 20
46 #define CFG_TX_DESCR_NUM 32
47 #define CFG_RX_DESCR_NUM 32
48 #define CFG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
51 * The datasheet says that each descriptor can transfers up to 4096 bytes
52 * But later, the register documentation reduces that value to 2048,
53 * using 2048 cause strange behaviours and even BSP driver use 2047
55 #define CFG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
57 #define TX_TOTAL_BUFSIZE (CFG_ETH_BUFSIZE * CFG_TX_DESCR_NUM)
58 #define RX_TOTAL_BUFSIZE (CFG_ETH_BUFSIZE * CFG_RX_DESCR_NUM)
60 #define H3_EPHY_DEFAULT_VALUE 0x58000
61 #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
62 #define H3_EPHY_ADDR_SHIFT 20
63 #define REG_PHY_ADDR_MASK GENMASK(4, 0)
64 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
65 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
66 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
68 #define SC_RMII_EN BIT(13)
69 #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
70 #define SC_ETCS_MASK GENMASK(1, 0)
71 #define SC_ETCS_EXT_GMII 0x1
72 #define SC_ETCS_INT_GMII 0x2
73 #define SC_ETXDC_MASK GENMASK(12, 10)
74 #define SC_ETXDC_OFFSET 10
75 #define SC_ERXDC_MASK GENMASK(9, 5)
76 #define SC_ERXDC_OFFSET 5
78 #define CFG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
80 #define AHB_GATE_OFFSET_EPHY 0
82 /* H3/A64 EMAC Register's offset */
83 #define EMAC_CTL0 0x00
84 #define EMAC_CTL0_FULL_DUPLEX BIT(0)
85 #define EMAC_CTL0_SPEED_MASK GENMASK(3, 2)
86 #define EMAC_CTL0_SPEED_10 (0x2 << 2)
87 #define EMAC_CTL0_SPEED_100 (0x3 << 2)
88 #define EMAC_CTL0_SPEED_1000 (0x0 << 2)
89 #define EMAC_CTL1 0x04
90 #define EMAC_CTL1_SOFT_RST BIT(0)
91 #define EMAC_CTL1_BURST_LEN_SHIFT 24
92 #define EMAC_INT_STA 0x08
93 #define EMAC_INT_EN 0x0c
94 #define EMAC_TX_CTL0 0x10
95 #define EMAC_TX_CTL0_TX_EN BIT(31)
96 #define EMAC_TX_CTL1 0x14
97 #define EMAC_TX_CTL1_TX_MD BIT(1)
98 #define EMAC_TX_CTL1_TX_DMA_EN BIT(30)
99 #define EMAC_TX_CTL1_TX_DMA_START BIT(31)
100 #define EMAC_TX_FLOW_CTL 0x1c
101 #define EMAC_TX_DMA_DESC 0x20
102 #define EMAC_RX_CTL0 0x24
103 #define EMAC_RX_CTL0_RX_EN BIT(31)
104 #define EMAC_RX_CTL1 0x28
105 #define EMAC_RX_CTL1_RX_MD BIT(1)
106 #define EMAC_RX_CTL1_RX_RUNT_FRM BIT(2)
107 #define EMAC_RX_CTL1_RX_ERR_FRM BIT(3)
108 #define EMAC_RX_CTL1_RX_DMA_EN BIT(30)
109 #define EMAC_RX_CTL1_RX_DMA_START BIT(31)
110 #define EMAC_RX_DMA_DESC 0x34
111 #define EMAC_MII_CMD 0x48
112 #define EMAC_MII_DATA 0x4c
113 #define EMAC_ADDR0_HIGH 0x50
114 #define EMAC_ADDR0_LOW 0x54
115 #define EMAC_TX_DMA_STA 0xb0
116 #define EMAC_TX_CUR_DESC 0xb4
117 #define EMAC_TX_CUR_BUF 0xb8
118 #define EMAC_RX_DMA_STA 0xc0
119 #define EMAC_RX_CUR_DESC 0xc4
121 #define EMAC_DESC_OWN_DMA BIT(31)
122 #define EMAC_DESC_LAST_DESC BIT(30)
123 #define EMAC_DESC_FIRST_DESC BIT(29)
124 #define EMAC_DESC_CHAIN_SECOND BIT(24)
126 #define EMAC_DESC_RX_ERROR_MASK 0x400068db
128 DECLARE_GLOBAL_DATA_PTR;
130 struct emac_variant {
132 bool soc_has_internal_phy;
136 struct emac_dma_desc {
141 } __aligned(ARCH_DMA_MINALIGN);
143 struct emac_eth_dev {
144 struct emac_dma_desc rx_chain[CFG_TX_DESCR_NUM];
145 struct emac_dma_desc tx_chain[CFG_RX_DESCR_NUM];
146 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
147 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
159 bool use_internal_phy;
161 const struct emac_variant *variant;
164 struct phy_device *phydev;
168 struct reset_ctl tx_rst;
169 struct reset_ctl ephy_rst;
170 #if CONFIG_IS_ENABLED(DM_GPIO)
171 struct gpio_desc reset_gpio;
176 struct sun8i_eth_pdata {
177 struct eth_pdata eth_pdata;
184 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
186 struct udevice *dev = bus->priv;
187 struct emac_eth_dev *priv = dev_get_priv(dev);
191 mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
192 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
193 mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
194 MDIO_CMD_MII_PHY_ADDR_MASK;
197 * The EMAC clock is either 200 or 300 MHz, so we need a divider
198 * of 128 to get the MDIO frequency below the required 2.5 MHz.
200 if (!priv->use_internal_phy)
201 mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
202 MDIO_CMD_MII_CLK_CSR_SHIFT;
204 mii_cmd |= MDIO_CMD_MII_BUSY;
206 writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
208 ret = wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
209 MDIO_CMD_MII_BUSY, false,
210 CFG_MDIO_TIMEOUT, true);
214 return readl(priv->mac_reg + EMAC_MII_DATA);
217 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
220 struct udevice *dev = bus->priv;
221 struct emac_eth_dev *priv = dev_get_priv(dev);
224 mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
225 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
226 mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
227 MDIO_CMD_MII_PHY_ADDR_MASK;
230 * The EMAC clock is either 200 or 300 MHz, so we need a divider
231 * of 128 to get the MDIO frequency below the required 2.5 MHz.
233 if (!priv->use_internal_phy)
234 mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
235 MDIO_CMD_MII_CLK_CSR_SHIFT;
237 mii_cmd |= MDIO_CMD_MII_WRITE;
238 mii_cmd |= MDIO_CMD_MII_BUSY;
240 writel(val, priv->mac_reg + EMAC_MII_DATA);
241 writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
243 return wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
244 MDIO_CMD_MII_BUSY, false,
245 CFG_MDIO_TIMEOUT, true);
248 static int sun8i_eth_write_hwaddr(struct udevice *dev)
250 struct emac_eth_dev *priv = dev_get_priv(dev);
251 struct eth_pdata *pdata = dev_get_plat(dev);
252 uchar *mac_id = pdata->enetaddr;
253 u32 macid_lo, macid_hi;
255 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
257 macid_hi = mac_id[4] + (mac_id[5] << 8);
259 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
260 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
265 static void sun8i_adjust_link(struct emac_eth_dev *priv,
266 struct phy_device *phydev)
270 v = readl(priv->mac_reg + EMAC_CTL0);
273 v |= EMAC_CTL0_FULL_DUPLEX;
275 v &= ~EMAC_CTL0_FULL_DUPLEX;
277 v &= ~EMAC_CTL0_SPEED_MASK;
279 switch (phydev->speed) {
281 v |= EMAC_CTL0_SPEED_1000;
284 v |= EMAC_CTL0_SPEED_100;
287 v |= EMAC_CTL0_SPEED_10;
290 writel(v, priv->mac_reg + EMAC_CTL0);
293 static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
295 if (priv->use_internal_phy) {
296 /* H3 based SoC's that has an Internal 100MBit PHY
297 * needs to be configured and powered up before use
299 reg &= ~H3_EPHY_DEFAULT_MASK;
300 reg |= H3_EPHY_DEFAULT_VALUE;
301 reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
302 reg &= ~H3_EPHY_SHUTDOWN;
303 return reg | H3_EPHY_SELECT;
306 /* This is to select External Gigabit PHY on those boards with
307 * an internal PHY. Does not hurt on other SoCs. Linux does
310 return reg & ~H3_EPHY_SELECT;
313 static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
314 struct emac_eth_dev *priv)
318 reg = readl(priv->sysctl_reg);
320 reg = sun8i_emac_set_syscon_ephy(priv, reg);
322 reg &= ~(SC_ETCS_MASK | SC_EPIT);
323 if (priv->variant->support_rmii)
326 switch (priv->interface) {
327 case PHY_INTERFACE_MODE_MII:
330 case PHY_INTERFACE_MODE_RGMII:
331 case PHY_INTERFACE_MODE_RGMII_ID:
332 case PHY_INTERFACE_MODE_RGMII_RXID:
333 case PHY_INTERFACE_MODE_RGMII_TXID:
334 reg |= SC_EPIT | SC_ETCS_INT_GMII;
336 case PHY_INTERFACE_MODE_RMII:
337 if (priv->variant->support_rmii) {
338 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
342 debug("%s: Invalid PHY interface\n", __func__);
346 if (pdata->tx_delay_ps)
347 reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
350 if (pdata->rx_delay_ps)
351 reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
354 writel(reg, priv->sysctl_reg);
359 static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
361 struct phy_device *phydev;
363 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
367 priv->phydev = phydev;
368 phy_config(priv->phydev);
373 #define cache_clean_descriptor(desc) \
374 flush_dcache_range((uintptr_t)(desc), \
375 (uintptr_t)(desc) + sizeof(struct emac_dma_desc))
377 #define cache_inv_descriptor(desc) \
378 invalidate_dcache_range((uintptr_t)(desc), \
379 (uintptr_t)(desc) + sizeof(struct emac_dma_desc))
381 static void rx_descs_init(struct emac_eth_dev *priv)
383 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
384 char *rxbuffs = &priv->rxbuffer[0];
385 struct emac_dma_desc *desc_p;
389 * Make sure we don't have dirty cache lines around, which could
390 * be cleaned to DRAM *after* the MAC has already written data to it.
392 invalidate_dcache_range((uintptr_t)desc_table_p,
393 (uintptr_t)desc_table_p + sizeof(priv->rx_chain));
394 invalidate_dcache_range((uintptr_t)rxbuffs,
395 (uintptr_t)rxbuffs + sizeof(priv->rxbuffer));
397 for (i = 0; i < CFG_RX_DESCR_NUM; i++) {
398 desc_p = &desc_table_p[i];
399 desc_p->buf_addr = (uintptr_t)&rxbuffs[i * CFG_ETH_BUFSIZE];
400 desc_p->next = (uintptr_t)&desc_table_p[i + 1];
401 desc_p->ctl_size = CFG_ETH_RXSIZE;
402 desc_p->status = EMAC_DESC_OWN_DMA;
405 /* Correcting the last pointer of the chain */
406 desc_p->next = (uintptr_t)&desc_table_p[0];
408 flush_dcache_range((uintptr_t)priv->rx_chain,
409 (uintptr_t)priv->rx_chain +
410 sizeof(priv->rx_chain));
412 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
413 priv->rx_currdescnum = 0;
416 static void tx_descs_init(struct emac_eth_dev *priv)
418 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
419 char *txbuffs = &priv->txbuffer[0];
420 struct emac_dma_desc *desc_p;
423 for (i = 0; i < CFG_TX_DESCR_NUM; i++) {
424 desc_p = &desc_table_p[i];
425 desc_p->buf_addr = (uintptr_t)&txbuffs[i * CFG_ETH_BUFSIZE];
426 desc_p->next = (uintptr_t)&desc_table_p[i + 1];
427 desc_p->ctl_size = 0;
431 /* Correcting the last pointer of the chain */
432 desc_p->next = (uintptr_t)&desc_table_p[0];
434 /* Flush the first TX buffer descriptor we will tell the MAC about. */
435 cache_clean_descriptor(desc_table_p);
437 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
438 priv->tx_currdescnum = 0;
441 static int sun8i_emac_eth_start(struct udevice *dev)
443 struct emac_eth_dev *priv = dev_get_priv(dev);
447 writel(EMAC_CTL1_SOFT_RST, priv->mac_reg + EMAC_CTL1);
448 ret = wait_for_bit_le32(priv->mac_reg + EMAC_CTL1,
449 EMAC_CTL1_SOFT_RST, false, 10, true);
451 printf("%s: Timeout\n", __func__);
455 /* Rewrite mac address after reset */
456 sun8i_eth_write_hwaddr(dev);
458 /* transmission starts after the full frame arrived in TX DMA FIFO */
459 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_MD);
462 * RX DMA reads data from RX DMA FIFO to host memory after a
463 * complete frame has been written to RX DMA FIFO
465 setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_MD);
467 /* DMA burst length */
468 writel(8 << EMAC_CTL1_BURST_LEN_SHIFT, priv->mac_reg + EMAC_CTL1);
470 /* Initialize rx/tx descriptors */
475 ret = phy_startup(priv->phydev);
479 sun8i_adjust_link(priv, priv->phydev);
481 /* Start RX/TX DMA */
482 setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN |
483 EMAC_RX_CTL1_RX_ERR_FRM | EMAC_RX_CTL1_RX_RUNT_FRM);
484 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
487 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
488 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
493 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
495 struct emac_eth_dev *priv = dev_get_priv(dev);
496 u32 status, desc_num = priv->rx_currdescnum;
497 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
498 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
501 /* Invalidate entire buffer descriptor */
502 cache_inv_descriptor(desc_p);
504 status = desc_p->status;
506 /* Check for DMA own bit */
507 if (status & EMAC_DESC_OWN_DMA)
510 length = (status >> 16) & 0x3fff;
512 /* make sure we read from DRAM, not our cache */
513 invalidate_dcache_range(data_start,
514 data_start + roundup(length, ARCH_DMA_MINALIGN));
516 if (status & EMAC_DESC_RX_ERROR_MASK) {
517 debug("RX: packet error: 0x%x\n",
518 status & EMAC_DESC_RX_ERROR_MASK);
522 debug("RX: Bad Packet (runt)\n");
526 if (length > CFG_ETH_RXSIZE) {
527 debug("RX: Too large packet (%d bytes)\n", length);
531 *packetp = (uchar *)(ulong)desc_p->buf_addr;
536 static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
538 struct emac_eth_dev *priv = dev_get_priv(dev);
539 u32 desc_num = priv->tx_currdescnum;
540 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
541 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
542 uintptr_t data_end = data_start +
543 roundup(length, ARCH_DMA_MINALIGN);
545 desc_p->ctl_size = length | EMAC_DESC_CHAIN_SECOND;
547 memcpy((void *)data_start, packet, length);
549 /* Flush data to be sent */
550 flush_dcache_range(data_start, data_end);
552 /* frame begin and end */
553 desc_p->ctl_size |= EMAC_DESC_LAST_DESC | EMAC_DESC_FIRST_DESC;
554 desc_p->status = EMAC_DESC_OWN_DMA;
556 /* make sure the MAC reads the actual data from DRAM */
557 cache_clean_descriptor(desc_p);
559 /* Move to next Descriptor and wrap around */
560 if (++desc_num >= CFG_TX_DESCR_NUM)
562 priv->tx_currdescnum = desc_num;
565 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_START);
568 * Since we copied the data above, we return here without waiting
569 * for the packet to be actually send out.
575 static int sun8i_emac_board_setup(struct udevice *dev,
576 struct emac_eth_dev *priv)
580 ret = clk_enable(&priv->tx_clk);
582 dev_err(dev, "failed to enable TX clock\n");
586 if (reset_valid(&priv->tx_rst)) {
587 ret = reset_deassert(&priv->tx_rst);
589 dev_err(dev, "failed to deassert TX reset\n");
594 /* Only H3/H5 have clock controls for internal EPHY */
595 if (clk_valid(&priv->ephy_clk)) {
596 ret = clk_enable(&priv->ephy_clk);
598 dev_err(dev, "failed to enable EPHY TX clock\n");
603 if (reset_valid(&priv->ephy_rst)) {
604 ret = reset_deassert(&priv->ephy_rst);
606 dev_err(dev, "failed to deassert EPHY TX clock\n");
614 clk_disable(&priv->tx_clk);
618 #if CONFIG_IS_ENABLED(DM_GPIO)
619 static int sun8i_mdio_reset(struct mii_dev *bus)
621 struct udevice *dev = bus->priv;
622 struct emac_eth_dev *priv = dev_get_priv(dev);
623 struct sun8i_eth_pdata *pdata = dev_get_plat(dev);
626 if (!dm_gpio_is_valid(&priv->reset_gpio))
630 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
634 udelay(pdata->reset_delays[0]);
636 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
640 udelay(pdata->reset_delays[1]);
642 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
646 udelay(pdata->reset_delays[2]);
652 static int sun8i_mdio_init(const char *name, struct udevice *priv)
654 struct mii_dev *bus = mdio_alloc();
657 debug("Failed to allocate MDIO bus\n");
661 bus->read = sun8i_mdio_read;
662 bus->write = sun8i_mdio_write;
663 snprintf(bus->name, sizeof(bus->name), name);
664 bus->priv = (void *)priv;
665 #if CONFIG_IS_ENABLED(DM_GPIO)
666 bus->reset = sun8i_mdio_reset;
669 return mdio_register(bus);
672 static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
675 struct emac_eth_dev *priv = dev_get_priv(dev);
676 u32 desc_num = priv->rx_currdescnum;
677 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
679 /* give the current descriptor back to the MAC */
680 desc_p->status |= EMAC_DESC_OWN_DMA;
682 /* Flush Status field of descriptor */
683 cache_clean_descriptor(desc_p);
685 /* Move to next desc and wrap-around condition. */
686 if (++desc_num >= CFG_RX_DESCR_NUM)
688 priv->rx_currdescnum = desc_num;
693 static void sun8i_emac_eth_stop(struct udevice *dev)
695 struct emac_eth_dev *priv = dev_get_priv(dev);
697 /* Stop Rx/Tx transmitter */
698 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
699 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
702 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
703 clrbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN);
705 phy_shutdown(priv->phydev);
708 static int sun8i_emac_eth_probe(struct udevice *dev)
710 struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
711 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
712 struct emac_eth_dev *priv = dev_get_priv(dev);
715 priv->mac_reg = (void *)pdata->iobase;
717 ret = sun8i_emac_board_setup(dev, priv);
721 sun8i_emac_set_syscon(sun8i_pdata, priv);
723 sun8i_mdio_init(dev->name, dev);
724 priv->bus = miiphy_get_dev_by_name(dev->name);
726 return sun8i_phy_init(priv, dev);
729 static const struct eth_ops sun8i_emac_eth_ops = {
730 .start = sun8i_emac_eth_start,
731 .write_hwaddr = sun8i_eth_write_hwaddr,
732 .send = sun8i_emac_eth_send,
733 .recv = sun8i_emac_eth_recv,
734 .free_pkt = sun8i_eth_free_pkt,
735 .stop = sun8i_emac_eth_stop,
738 static int sun8i_handle_internal_phy(struct udevice *dev, struct emac_eth_dev *priv)
740 struct ofnode_phandle_args phandle;
743 ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle",
744 NULL, 0, 0, &phandle);
748 /* If the PHY node is not a child of the internal MDIO bus, we are
749 * using some external PHY.
751 if (!ofnode_device_is_compatible(ofnode_get_parent(phandle.node),
752 "allwinner,sun8i-h3-mdio-internal"))
755 ret = clk_get_by_index_nodev(phandle.node, 0, &priv->ephy_clk);
757 dev_err(dev, "failed to get EPHY TX clock\n");
761 ret = reset_get_by_index_nodev(phandle.node, 0, &priv->ephy_rst);
763 dev_err(dev, "failed to get EPHY TX reset\n");
767 priv->use_internal_phy = true;
772 static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
774 struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
775 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
776 struct emac_eth_dev *priv = dev_get_priv(dev);
777 phys_addr_t syscon_base;
779 int node = dev_of_offset(dev);
781 #if CONFIG_IS_ENABLED(DM_GPIO)
782 int reset_flags = GPIOD_IS_OUT;
786 pdata->iobase = dev_read_addr(dev);
787 if (pdata->iobase == FDT_ADDR_T_NONE) {
788 debug("%s: Cannot find MAC base address\n", __func__);
792 priv->variant = (const void *)dev_get_driver_data(dev);
794 if (!priv->variant) {
795 printf("%s: Missing variant\n", __func__);
799 ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
801 dev_err(dev, "failed to get TX clock\n");
805 ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
806 if (ret && ret != -ENOENT) {
807 dev_err(dev, "failed to get TX reset\n");
811 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
813 debug("%s: cannot find syscon node\n", __func__);
817 reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
819 debug("%s: cannot find reg property in syscon node\n",
824 syscon_base = fdt_translate_address((void *)gd->fdt_blob, offset, reg);
825 if (syscon_base == FDT_ADDR_T_NONE) {
826 debug("%s: Cannot find syscon base address\n", __func__);
830 priv->sysctl_reg = (void *)syscon_base + priv->variant->syscon_offset;
832 pdata->phy_interface = -1;
834 priv->use_internal_phy = false;
836 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
838 debug("%s: Cannot find PHY address\n", __func__);
841 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
843 pdata->phy_interface = dev_read_phy_mode(dev);
844 debug("phy interface %d\n", pdata->phy_interface);
845 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
848 if (priv->variant->soc_has_internal_phy) {
849 ret = sun8i_handle_internal_phy(dev, priv);
854 priv->interface = pdata->phy_interface;
856 sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
857 "allwinner,tx-delay-ps", 0);
858 if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
859 printf("%s: Invalid TX delay value %d\n", __func__,
860 sun8i_pdata->tx_delay_ps);
862 sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
863 "allwinner,rx-delay-ps", 0);
864 if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
865 printf("%s: Invalid RX delay value %d\n", __func__,
866 sun8i_pdata->rx_delay_ps);
868 #if CONFIG_IS_ENABLED(DM_GPIO)
869 if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
870 "snps,reset-active-low"))
871 reset_flags |= GPIOD_ACTIVE_LOW;
873 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
874 &priv->reset_gpio, reset_flags);
877 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
878 "snps,reset-delays-us",
879 sun8i_pdata->reset_delays, 3);
880 } else if (ret == -ENOENT) {
888 static const struct emac_variant emac_variant_a83t = {
889 .syscon_offset = 0x30,
892 static const struct emac_variant emac_variant_h3 = {
893 .syscon_offset = 0x30,
894 .soc_has_internal_phy = true,
895 .support_rmii = true,
898 static const struct emac_variant emac_variant_r40 = {
899 .syscon_offset = 0x164,
902 static const struct emac_variant emac_variant_a64 = {
903 .syscon_offset = 0x30,
904 .support_rmii = true,
907 static const struct emac_variant emac_variant_h6 = {
908 .syscon_offset = 0x30,
909 .support_rmii = true,
912 static const struct udevice_id sun8i_emac_eth_ids[] = {
913 { .compatible = "allwinner,sun8i-a83t-emac",
914 .data = (ulong)&emac_variant_a83t },
915 { .compatible = "allwinner,sun8i-h3-emac",
916 .data = (ulong)&emac_variant_h3 },
917 { .compatible = "allwinner,sun8i-r40-gmac",
918 .data = (ulong)&emac_variant_r40 },
919 { .compatible = "allwinner,sun50i-a64-emac",
920 .data = (ulong)&emac_variant_a64 },
921 { .compatible = "allwinner,sun50i-h6-emac",
922 .data = (ulong)&emac_variant_h6 },
926 U_BOOT_DRIVER(eth_sun8i_emac) = {
927 .name = "eth_sun8i_emac",
929 .of_match = sun8i_emac_eth_ids,
930 .of_to_plat = sun8i_emac_eth_of_to_plat,
931 .probe = sun8i_emac_eth_probe,
932 .ops = &sun8i_emac_eth_ops,
933 .priv_auto = sizeof(struct emac_eth_dev),
934 .plat_auto = sizeof(struct sun8i_eth_pdata),
935 .flags = DM_FLAG_ALLOC_PRIV_DMA,