1 // SPDX-License-Identifier: GPL-2.0+
4 * Author: Amit Singh Tomar, amittomer25@gmail.com
6 * Ethernet driver for H3/A64/A83T based SoC's
8 * It is derived from the work done by
9 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
15 #include <asm/cache.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/gpio.h>
22 #include <fdt_support.h>
23 #include <dm/device_compat.h>
24 #include <linux/bitops.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
31 #include <dt-bindings/pinctrl/sun4i-a10.h>
32 #if CONFIG_IS_ENABLED(DM_GPIO)
33 #include <asm-generic/gpio.h>
36 #define MDIO_CMD_MII_BUSY BIT(0)
37 #define MDIO_CMD_MII_WRITE BIT(1)
39 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
40 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
41 #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
42 #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
44 #define CONFIG_TX_DESCR_NUM 32
45 #define CONFIG_RX_DESCR_NUM 32
46 #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
49 * The datasheet says that each descriptor can transfers up to 4096 bytes
50 * But later, the register documentation reduces that value to 2048,
51 * using 2048 cause strange behaviours and even BSP driver use 2047
53 #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
55 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
56 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
58 #define H3_EPHY_DEFAULT_VALUE 0x58000
59 #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
60 #define H3_EPHY_ADDR_SHIFT 20
61 #define REG_PHY_ADDR_MASK GENMASK(4, 0)
62 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
63 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
64 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
66 #define SC_RMII_EN BIT(13)
67 #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
68 #define SC_ETCS_MASK GENMASK(1, 0)
69 #define SC_ETCS_EXT_GMII 0x1
70 #define SC_ETCS_INT_GMII 0x2
71 #define SC_ETXDC_MASK GENMASK(12, 10)
72 #define SC_ETXDC_OFFSET 10
73 #define SC_ERXDC_MASK GENMASK(9, 5)
74 #define SC_ERXDC_OFFSET 5
76 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
78 #define AHB_GATE_OFFSET_EPHY 0
81 #define SUN8I_IOMUX_H3 2
82 #define SUN8I_IOMUX_R40 5
85 /* H3/A64 EMAC Register's offset */
86 #define EMAC_CTL0 0x00
87 #define EMAC_CTL1 0x04
88 #define EMAC_INT_STA 0x08
89 #define EMAC_INT_EN 0x0c
90 #define EMAC_TX_CTL0 0x10
91 #define EMAC_TX_CTL1 0x14
92 #define EMAC_TX_FLOW_CTL 0x1c
93 #define EMAC_TX_DMA_DESC 0x20
94 #define EMAC_RX_CTL0 0x24
95 #define EMAC_RX_CTL1 0x28
96 #define EMAC_RX_DMA_DESC 0x34
97 #define EMAC_MII_CMD 0x48
98 #define EMAC_MII_DATA 0x4c
99 #define EMAC_ADDR0_HIGH 0x50
100 #define EMAC_ADDR0_LOW 0x54
101 #define EMAC_TX_DMA_STA 0xb0
102 #define EMAC_TX_CUR_DESC 0xb4
103 #define EMAC_TX_CUR_BUF 0xb8
104 #define EMAC_RX_DMA_STA 0xc0
105 #define EMAC_RX_CUR_DESC 0xc4
107 DECLARE_GLOBAL_DATA_PTR;
117 struct emac_dma_desc {
122 } __aligned(ARCH_DMA_MINALIGN);
124 struct emac_eth_dev {
125 struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
126 struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
127 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
128 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
140 bool use_internal_phy;
142 enum emac_variant variant;
144 phys_addr_t sysctl_reg;
145 struct phy_device *phydev;
149 struct reset_ctl tx_rst;
150 struct reset_ctl ephy_rst;
151 #if CONFIG_IS_ENABLED(DM_GPIO)
152 struct gpio_desc reset_gpio;
157 struct sun8i_eth_pdata {
158 struct eth_pdata eth_pdata;
165 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
167 struct udevice *dev = bus->priv;
168 struct emac_eth_dev *priv = dev_get_priv(dev);
171 int timeout = CONFIG_MDIO_TIMEOUT;
173 miiaddr &= ~MDIO_CMD_MII_WRITE;
174 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
175 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
176 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
178 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
180 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
181 MDIO_CMD_MII_PHY_ADDR_MASK;
183 miiaddr |= MDIO_CMD_MII_BUSY;
185 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
187 start = get_timer(0);
188 while (get_timer(start) < timeout) {
189 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
190 return readl(priv->mac_reg + EMAC_MII_DATA);
197 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
200 struct udevice *dev = bus->priv;
201 struct emac_eth_dev *priv = dev_get_priv(dev);
204 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
206 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
207 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
208 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
210 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
211 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
212 MDIO_CMD_MII_PHY_ADDR_MASK;
214 miiaddr |= MDIO_CMD_MII_WRITE;
215 miiaddr |= MDIO_CMD_MII_BUSY;
217 writel(val, priv->mac_reg + EMAC_MII_DATA);
218 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
220 start = get_timer(0);
221 while (get_timer(start) < timeout) {
222 if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
223 MDIO_CMD_MII_BUSY)) {
233 static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
235 u32 macid_lo, macid_hi;
237 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
239 macid_hi = mac_id[4] + (mac_id[5] << 8);
241 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
242 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
247 static void sun8i_adjust_link(struct emac_eth_dev *priv,
248 struct phy_device *phydev)
252 v = readl(priv->mac_reg + EMAC_CTL0);
261 switch (phydev->speed) {
272 writel(v, priv->mac_reg + EMAC_CTL0);
275 static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
277 if (priv->use_internal_phy) {
278 /* H3 based SoC's that has an Internal 100MBit PHY
279 * needs to be configured and powered up before use
281 *reg &= ~H3_EPHY_DEFAULT_MASK;
282 *reg |= H3_EPHY_DEFAULT_VALUE;
283 *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
284 *reg &= ~H3_EPHY_SHUTDOWN;
285 *reg |= H3_EPHY_SELECT;
287 /* This is to select External Gigabit PHY on
288 * the boards with H3 SoC.
290 *reg &= ~H3_EPHY_SELECT;
295 static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
296 struct emac_eth_dev *priv)
301 if (priv->variant == R40_GMAC) {
302 /* Select RGMII for R40 */
303 reg = readl(priv->sysctl_reg + 0x164);
304 reg |= SC_ETCS_INT_GMII |
306 (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
308 writel(reg, priv->sysctl_reg + 0x164);
312 reg = readl(priv->sysctl_reg + 0x30);
314 if (priv->variant == H3_EMAC || priv->variant == H6_EMAC) {
315 ret = sun8i_emac_set_syscon_ephy(priv, ®);
320 reg &= ~(SC_ETCS_MASK | SC_EPIT);
321 if (priv->variant == H3_EMAC ||
322 priv->variant == A64_EMAC ||
323 priv->variant == H6_EMAC)
326 switch (priv->interface) {
327 case PHY_INTERFACE_MODE_MII:
330 case PHY_INTERFACE_MODE_RGMII:
331 reg |= SC_EPIT | SC_ETCS_INT_GMII;
333 case PHY_INTERFACE_MODE_RMII:
334 if (priv->variant == H3_EMAC ||
335 priv->variant == A64_EMAC ||
336 priv->variant == H6_EMAC) {
337 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
340 /* RMII not supported on A83T */
342 debug("%s: Invalid PHY interface\n", __func__);
346 if (pdata->tx_delay_ps)
347 reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
350 if (pdata->rx_delay_ps)
351 reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
354 writel(reg, priv->sysctl_reg + 0x30);
359 static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
361 struct phy_device *phydev;
363 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
367 phy_connect_dev(phydev, dev);
369 priv->phydev = phydev;
370 phy_config(priv->phydev);
375 static void rx_descs_init(struct emac_eth_dev *priv)
377 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
378 char *rxbuffs = &priv->rxbuffer[0];
379 struct emac_dma_desc *desc_p;
382 /* flush Rx buffers */
383 flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
386 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
387 desc_p = &desc_table_p[idx];
388 desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
390 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
391 desc_p->st |= CONFIG_ETH_RXSIZE;
392 desc_p->status = BIT(31);
395 /* Correcting the last pointer of the chain */
396 desc_p->next = (uintptr_t)&desc_table_p[0];
398 flush_dcache_range((uintptr_t)priv->rx_chain,
399 (uintptr_t)priv->rx_chain +
400 sizeof(priv->rx_chain));
402 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
403 priv->rx_currdescnum = 0;
406 static void tx_descs_init(struct emac_eth_dev *priv)
408 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
409 char *txbuffs = &priv->txbuffer[0];
410 struct emac_dma_desc *desc_p;
413 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
414 desc_p = &desc_table_p[idx];
415 desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
417 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
418 desc_p->status = (1 << 31);
422 /* Correcting the last pointer of the chain */
423 desc_p->next = (uintptr_t)&desc_table_p[0];
425 /* Flush all Tx buffer descriptors */
426 flush_dcache_range((uintptr_t)priv->tx_chain,
427 (uintptr_t)priv->tx_chain +
428 sizeof(priv->tx_chain));
430 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
431 priv->tx_currdescnum = 0;
434 static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
439 reg = readl((priv->mac_reg + EMAC_CTL1));
443 setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
445 reg = readl(priv->mac_reg + EMAC_CTL1);
446 } while ((reg & 0x01) != 0 && (--timeout));
448 printf("%s: Timeout\n", __func__);
453 /* Rewrite mac address after reset */
454 _sun8i_write_hwaddr(priv, enetaddr);
456 v = readl(priv->mac_reg + EMAC_TX_CTL1);
457 /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
459 writel(v, priv->mac_reg + EMAC_TX_CTL1);
461 v = readl(priv->mac_reg + EMAC_RX_CTL1);
462 /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
463 * complete frame has been written to RX DMA FIFO
466 writel(v, priv->mac_reg + EMAC_RX_CTL1);
469 writel(8 << 24, priv->mac_reg + EMAC_CTL1);
471 /* Initialize rx/tx descriptors */
476 phy_startup(priv->phydev);
478 sun8i_adjust_link(priv, priv->phydev);
481 v = readl(priv->mac_reg + EMAC_RX_CTL1);
483 writel(v, priv->mac_reg + EMAC_RX_CTL1);
485 v = readl(priv->mac_reg + EMAC_TX_CTL1);
487 writel(v, priv->mac_reg + EMAC_TX_CTL1);
490 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
491 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
496 static int parse_phy_pins(struct udevice *dev)
498 struct emac_eth_dev *priv = dev_get_priv(dev);
500 const char *pin_name;
501 int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
503 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
506 printf("WARNING: emac: cannot find pinctrl-0 node\n");
510 drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
511 "drive-strength", ~0);
514 drive = SUN4I_PINCTRL_10_MA;
515 else if (drive <= 20)
516 drive = SUN4I_PINCTRL_20_MA;
517 else if (drive <= 30)
518 drive = SUN4I_PINCTRL_30_MA;
520 drive = SUN4I_PINCTRL_40_MA;
523 if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
524 pull = SUN4I_PINCTRL_PULL_UP;
525 else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
526 pull = SUN4I_PINCTRL_PULL_DOWN;
531 pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
536 pin = sunxi_name_to_gpio(pin_name);
540 if (priv->variant == H3_EMAC)
541 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3);
542 else if (priv->variant == R40_GMAC || priv->variant == H6_EMAC)
543 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_R40);
545 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX);
548 sunxi_gpio_set_drv(pin, drive);
550 sunxi_gpio_set_pull(pin, pull);
554 printf("WARNING: emac: cannot find pins property\n");
561 static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
563 u32 status, desc_num = priv->rx_currdescnum;
564 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
565 int length = -EAGAIN;
567 uintptr_t desc_start = (uintptr_t)desc_p;
568 uintptr_t desc_end = desc_start +
569 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
571 ulong data_start = (uintptr_t)desc_p->buf_addr;
574 /* Invalidate entire buffer descriptor */
575 invalidate_dcache_range(desc_start, desc_end);
577 status = desc_p->status;
579 /* Check for DMA own bit */
580 if (!(status & BIT(31))) {
581 length = (desc_p->status >> 16) & 0x3FFF;
585 debug("RX: Bad Packet (runt)\n");
588 data_end = data_start + length;
589 /* Invalidate received data */
590 invalidate_dcache_range(rounddown(data_start,
595 if (length > CONFIG_ETH_RXSIZE) {
596 printf("Received packet is too big (len=%d)\n",
600 *packetp = (uchar *)(ulong)desc_p->buf_addr;
608 static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
611 u32 v, desc_num = priv->tx_currdescnum;
612 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
613 uintptr_t desc_start = (uintptr_t)desc_p;
614 uintptr_t desc_end = desc_start +
615 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
617 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
618 uintptr_t data_end = data_start +
619 roundup(len, ARCH_DMA_MINALIGN);
621 /* Invalidate entire buffer descriptor */
622 invalidate_dcache_range(desc_start, desc_end);
625 /* Mandatory undocumented bit */
626 desc_p->st |= BIT(24);
628 memcpy((void *)data_start, packet, len);
630 /* Flush data to be sent */
631 flush_dcache_range(data_start, data_end);
634 desc_p->st |= BIT(30);
635 desc_p->st |= BIT(31);
638 desc_p->st |= BIT(29);
639 desc_p->status = BIT(31);
641 /*Descriptors st and status field has changed, so FLUSH it */
642 flush_dcache_range(desc_start, desc_end);
644 /* Move to next Descriptor and wrap around */
645 if (++desc_num >= CONFIG_TX_DESCR_NUM)
647 priv->tx_currdescnum = desc_num;
650 v = readl(priv->mac_reg + EMAC_TX_CTL1);
651 v |= BIT(31);/* mandatory */
652 v |= BIT(30);/* mandatory */
653 writel(v, priv->mac_reg + EMAC_TX_CTL1);
658 static int sun8i_eth_write_hwaddr(struct udevice *dev)
660 struct eth_pdata *pdata = dev_get_platdata(dev);
661 struct emac_eth_dev *priv = dev_get_priv(dev);
663 return _sun8i_write_hwaddr(priv, pdata->enetaddr);
666 static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
670 ret = clk_enable(&priv->tx_clk);
672 dev_err(dev, "failed to enable TX clock\n");
676 if (reset_valid(&priv->tx_rst)) {
677 ret = reset_deassert(&priv->tx_rst);
679 dev_err(dev, "failed to deassert TX reset\n");
684 /* Only H3/H5 have clock controls for internal EPHY */
685 if (clk_valid(&priv->ephy_clk)) {
686 ret = clk_enable(&priv->ephy_clk);
688 dev_err(dev, "failed to enable EPHY TX clock\n");
693 if (reset_valid(&priv->ephy_rst)) {
694 ret = reset_deassert(&priv->ephy_rst);
696 dev_err(dev, "failed to deassert EPHY TX clock\n");
704 clk_disable(&priv->tx_clk);
708 #if CONFIG_IS_ENABLED(DM_GPIO)
709 static int sun8i_mdio_reset(struct mii_dev *bus)
711 struct udevice *dev = bus->priv;
712 struct emac_eth_dev *priv = dev_get_priv(dev);
713 struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
716 if (!dm_gpio_is_valid(&priv->reset_gpio))
720 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
724 udelay(pdata->reset_delays[0]);
726 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
730 udelay(pdata->reset_delays[1]);
732 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
736 udelay(pdata->reset_delays[2]);
742 static int sun8i_mdio_init(const char *name, struct udevice *priv)
744 struct mii_dev *bus = mdio_alloc();
747 debug("Failed to allocate MDIO bus\n");
751 bus->read = sun8i_mdio_read;
752 bus->write = sun8i_mdio_write;
753 snprintf(bus->name, sizeof(bus->name), name);
754 bus->priv = (void *)priv;
755 #if CONFIG_IS_ENABLED(DM_GPIO)
756 bus->reset = sun8i_mdio_reset;
759 return mdio_register(bus);
762 static int sun8i_emac_eth_start(struct udevice *dev)
764 struct eth_pdata *pdata = dev_get_platdata(dev);
766 return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
769 static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
771 struct emac_eth_dev *priv = dev_get_priv(dev);
773 return _sun8i_emac_eth_send(priv, packet, length);
776 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
778 struct emac_eth_dev *priv = dev_get_priv(dev);
780 return _sun8i_eth_recv(priv, packetp);
783 static int _sun8i_free_pkt(struct emac_eth_dev *priv)
785 u32 desc_num = priv->rx_currdescnum;
786 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
787 uintptr_t desc_start = (uintptr_t)desc_p;
788 uintptr_t desc_end = desc_start +
789 roundup(sizeof(u32), ARCH_DMA_MINALIGN);
791 /* Make the current descriptor valid again */
792 desc_p->status |= BIT(31);
794 /* Flush Status field of descriptor */
795 flush_dcache_range(desc_start, desc_end);
797 /* Move to next desc and wrap-around condition. */
798 if (++desc_num >= CONFIG_RX_DESCR_NUM)
800 priv->rx_currdescnum = desc_num;
805 static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
808 struct emac_eth_dev *priv = dev_get_priv(dev);
810 return _sun8i_free_pkt(priv);
813 static void sun8i_emac_eth_stop(struct udevice *dev)
815 struct emac_eth_dev *priv = dev_get_priv(dev);
817 /* Stop Rx/Tx transmitter */
818 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
819 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
822 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
824 phy_shutdown(priv->phydev);
827 static int sun8i_emac_eth_probe(struct udevice *dev)
829 struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
830 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
831 struct emac_eth_dev *priv = dev_get_priv(dev);
834 priv->mac_reg = (void *)pdata->iobase;
836 ret = sun8i_emac_board_setup(priv);
840 sun8i_emac_set_syscon(sun8i_pdata, priv);
842 sun8i_mdio_init(dev->name, dev);
843 priv->bus = miiphy_get_dev_by_name(dev->name);
845 return sun8i_phy_init(priv, dev);
848 static const struct eth_ops sun8i_emac_eth_ops = {
849 .start = sun8i_emac_eth_start,
850 .write_hwaddr = sun8i_eth_write_hwaddr,
851 .send = sun8i_emac_eth_send,
852 .recv = sun8i_emac_eth_recv,
853 .free_pkt = sun8i_eth_free_pkt,
854 .stop = sun8i_emac_eth_stop,
857 static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv)
859 int emac_node, ephy_node, ret, ephy_handle;
861 emac_node = fdt_path_offset(gd->fdt_blob,
862 "/soc/ethernet@1c30000");
864 debug("failed to get emac node\n");
867 ephy_handle = fdtdec_lookup_phandle(gd->fdt_blob,
868 emac_node, "phy-handle");
870 /* look for mdio-mux node for internal PHY node */
871 ephy_node = fdt_path_offset(gd->fdt_blob,
872 "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1");
874 debug("failed to get mdio-mux with internal PHY\n");
878 /* This is not the phy we are looking for */
879 if (ephy_node != ephy_handle)
882 ret = fdt_node_check_compatible(gd->fdt_blob, ephy_node,
883 "allwinner,sun8i-h3-mdio-internal");
885 debug("failed to find mdio-internal node\n");
889 ret = clk_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
892 dev_err(dev, "failed to get EPHY TX clock\n");
896 ret = reset_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
899 dev_err(dev, "failed to get EPHY TX reset\n");
903 priv->use_internal_phy = true;
908 static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
910 struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
911 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
912 struct emac_eth_dev *priv = dev_get_priv(dev);
913 const char *phy_mode;
915 int node = dev_of_offset(dev);
917 #if CONFIG_IS_ENABLED(DM_GPIO)
918 int reset_flags = GPIOD_IS_OUT;
922 pdata->iobase = dev_read_addr(dev);
923 if (pdata->iobase == FDT_ADDR_T_NONE) {
924 debug("%s: Cannot find MAC base address\n", __func__);
928 priv->variant = dev_get_driver_data(dev);
930 if (!priv->variant) {
931 printf("%s: Missing variant\n", __func__);
935 ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
937 dev_err(dev, "failed to get TX clock\n");
941 ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
942 if (ret && ret != -ENOENT) {
943 dev_err(dev, "failed to get TX reset\n");
947 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
949 debug("%s: cannot find syscon node\n", __func__);
953 reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
955 debug("%s: cannot find reg property in syscon node\n",
959 priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
961 if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
962 debug("%s: Cannot find syscon base address\n", __func__);
966 pdata->phy_interface = -1;
968 priv->use_internal_phy = false;
970 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
972 debug("%s: Cannot find PHY address\n", __func__);
975 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
977 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
980 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
981 printf("phy interface%d\n", pdata->phy_interface);
983 if (pdata->phy_interface == -1) {
984 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
988 if (priv->variant == H3_EMAC) {
989 ret = sun8i_get_ephy_nodes(priv);
994 priv->interface = pdata->phy_interface;
996 if (!priv->use_internal_phy)
999 sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
1000 "allwinner,tx-delay-ps", 0);
1001 if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
1002 printf("%s: Invalid TX delay value %d\n", __func__,
1003 sun8i_pdata->tx_delay_ps);
1005 sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
1006 "allwinner,rx-delay-ps", 0);
1007 if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
1008 printf("%s: Invalid RX delay value %d\n", __func__,
1009 sun8i_pdata->rx_delay_ps);
1011 #if CONFIG_IS_ENABLED(DM_GPIO)
1012 if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
1013 "snps,reset-active-low"))
1014 reset_flags |= GPIOD_ACTIVE_LOW;
1016 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
1017 &priv->reset_gpio, reset_flags);
1020 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
1021 "snps,reset-delays-us",
1022 sun8i_pdata->reset_delays, 3);
1023 } else if (ret == -ENOENT) {
1031 static const struct udevice_id sun8i_emac_eth_ids[] = {
1032 {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
1033 {.compatible = "allwinner,sun50i-a64-emac",
1034 .data = (uintptr_t)A64_EMAC },
1035 {.compatible = "allwinner,sun8i-a83t-emac",
1036 .data = (uintptr_t)A83T_EMAC },
1037 {.compatible = "allwinner,sun8i-r40-gmac",
1038 .data = (uintptr_t)R40_GMAC },
1039 {.compatible = "allwinner,sun50i-h6-emac",
1040 .data = (uintptr_t)H6_EMAC },
1044 U_BOOT_DRIVER(eth_sun8i_emac) = {
1045 .name = "eth_sun8i_emac",
1047 .of_match = sun8i_emac_eth_ids,
1048 .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
1049 .probe = sun8i_emac_eth_probe,
1050 .ops = &sun8i_emac_eth_ops,
1051 .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
1052 .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
1053 .flags = DM_FLAG_ALLOC_PRIV_DMA,