1 // SPDX-License-Identifier: GPL-2.0+
3 * netsec.c - Socionext Synquacer Netsec driver
4 * Copyright 2021 Linaro Ltd.
10 #include <fdt_support.h>
18 #include <asm/cache.h>
19 #include <asm/global_data.h>
20 #include <dm/device_compat.h>
21 #include <linux/bitops.h>
22 #include <linux/delay.h>
23 #include <linux/err.h>
25 #include <linux/iopoll.h>
27 #include <spi_flash.h>
29 #define NETSEC_REG_SOFT_RST 0x104
30 #define NETSEC_REG_COM_INIT 0x120
32 #define NETSEC_REG_TOP_STATUS 0x200
33 #define NETSEC_IRQ_RX BIT(1)
34 #define NETSEC_IRQ_TX BIT(0)
36 #define NETSEC_REG_TOP_INTEN 0x204
37 #define NETSEC_REG_INTEN_SET 0x234
38 #define NETSEC_REG_INTEN_CLR 0x238
40 #define NETSEC_REG_NRM_TX_STATUS 0x400
41 #define NETSEC_REG_NRM_TX_INTEN 0x404
42 #define NETSEC_REG_NRM_TX_INTEN_SET 0x428
43 #define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c
44 #define NRM_TX_ST_NTOWNR BIT(17)
45 #define NRM_TX_ST_TR_ERR BIT(16)
46 #define NRM_TX_ST_TXDONE BIT(15)
47 #define NRM_TX_ST_TMREXP BIT(14)
49 #define NETSEC_REG_NRM_RX_STATUS 0x440
50 #define NETSEC_REG_NRM_RX_INTEN 0x444
51 #define NETSEC_REG_NRM_RX_INTEN_SET 0x468
52 #define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c
53 #define NRM_RX_ST_RC_ERR BIT(16)
54 #define NRM_RX_ST_PKTCNT BIT(15)
55 #define NRM_RX_ST_TMREXP BIT(14)
57 #define NETSEC_REG_PKT_CMD_BUF 0xd0
59 #define NETSEC_REG_CLK_EN 0x100
61 #define NETSEC_REG_PKT_CTRL 0x140
63 #define NETSEC_REG_DMA_TMR_CTRL 0x20c
64 #define NETSEC_REG_F_TAIKI_MC_VER 0x22c
65 #define NETSEC_REG_F_TAIKI_VER 0x230
66 #define NETSEC_REG_DMA_HM_CTRL 0x214
67 #define NETSEC_REG_DMA_MH_CTRL 0x220
68 #define NETSEC_REG_ADDR_DIS_CORE 0x218
69 #define NETSEC_REG_DMAC_HM_CMD_BUF 0x210
70 #define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c
72 #define NETSEC_REG_NRM_TX_PKTCNT 0x410
74 #define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414
75 #define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418
77 #define NETSEC_REG_NRM_TX_TMR 0x41c
79 #define NETSEC_REG_NRM_RX_PKTCNT 0x454
80 #define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458
81 #define NETSEC_REG_NRM_TX_TXINT_TMR 0x420
82 #define NETSEC_REG_NRM_RX_RXINT_TMR 0x460
84 #define NETSEC_REG_NRM_RX_TMR 0x45c
86 #define NETSEC_REG_NRM_TX_DESC_START_UP 0x434
87 #define NETSEC_REG_NRM_TX_DESC_START_LW 0x408
88 #define NETSEC_REG_NRM_RX_DESC_START_UP 0x474
89 #define NETSEC_REG_NRM_RX_DESC_START_LW 0x448
91 #define NETSEC_REG_NRM_TX_CONFIG 0x430
92 #define NETSEC_REG_NRM_RX_CONFIG 0x470
94 #define MAC_REG_STATUS 0x1024
95 #define MAC_REG_DATA 0x11c0
96 #define MAC_REG_CMD 0x11c4
97 #define MAC_REG_FLOW_TH 0x11cc
98 #define MAC_REG_INTF_SEL 0x11d4
99 #define MAC_REG_DESC_INIT 0x11fc
100 #define MAC_REG_DESC_SOFT_RST 0x1204
101 #define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500
103 #define GMAC_REG_MCR 0x0000
104 #define GMAC_REG_MFFR 0x0004
105 #define GMAC_REG_GAR 0x0010
106 #define GMAC_REG_GDR 0x0014
107 #define GMAC_REG_FCR 0x0018
108 #define GMAC_REG_BMR 0x1000
109 #define GMAC_REG_RDLAR 0x100c
110 #define GMAC_REG_TDLAR 0x1010
111 #define GMAC_REG_OMR 0x1018
113 #define MHZ(n) ((n) * 1000 * 1000)
115 #define NETSEC_TX_SHIFT_OWN_FIELD 31
116 #define NETSEC_TX_SHIFT_LD_FIELD 30
117 #define NETSEC_TX_SHIFT_DRID_FIELD 24
118 #define NETSEC_TX_SHIFT_PT_FIELD 21
119 #define NETSEC_TX_SHIFT_TDRID_FIELD 16
120 #define NETSEC_TX_SHIFT_CC_FIELD 15
121 #define NETSEC_TX_SHIFT_FS_FIELD 9
122 #define NETSEC_TX_LAST 8
123 #define NETSEC_TX_SHIFT_CO 7
124 #define NETSEC_TX_SHIFT_SO 6
125 #define NETSEC_TX_SHIFT_TRS_FIELD 4
127 #define NETSEC_RX_PKT_OWN_FIELD 31
128 #define NETSEC_RX_PKT_LD_FIELD 30
129 #define NETSEC_RX_PKT_SDRID_FIELD 24
130 #define NETSEC_RX_PKT_FR_FIELD 23
131 #define NETSEC_RX_PKT_ER_FIELD 21
132 #define NETSEC_RX_PKT_ERR_FIELD 16
133 #define NETSEC_RX_PKT_TDRID_FIELD 12
134 #define NETSEC_RX_PKT_FS_FIELD 9
135 #define NETSEC_RX_PKT_LS_FIELD 8
136 #define NETSEC_RX_PKT_CO_FIELD 6
138 #define NETSEC_RX_PKT_ERR_MASK 3
140 #define NETSEC_MAX_TX_PKT_LEN 1518
141 #define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018
143 #define NETSEC_RING_GMAC 15
144 #define NETSEC_RING_MAX 2
146 #define NETSEC_TCP_SEG_LEN_MAX 1460
147 #define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960
149 #define NETSEC_RX_CKSUM_NOTAVAIL 0
150 #define NETSEC_RX_CKSUM_OK 1
151 #define NETSEC_RX_CKSUM_NG 2
153 #define NETSEC_TOP_IRQ_REG_ME_START BIT(20)
154 #define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4)
156 #define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20)
157 #define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19)
159 #define NETSEC_INT_PKTCNT_MAX 2047
161 #define NETSEC_FLOW_START_TH_MAX 95
162 #define NETSEC_FLOW_STOP_TH_MAX 95
163 #define NETSEC_FLOW_PAUSE_TIME_MIN 5
165 #define NETSEC_CLK_EN_REG_DOM_ALL 0x3f
167 #define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28)
168 #define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27)
169 #define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3)
170 #define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2)
171 #define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1)
172 #define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0)
174 #define NETSEC_CLK_EN_REG_DOM_G BIT(5)
175 #define NETSEC_CLK_EN_REG_DOM_C BIT(1)
176 #define NETSEC_CLK_EN_REG_DOM_D BIT(0)
178 #define NETSEC_COM_INIT_REG_DB BIT(2)
179 #define NETSEC_COM_INIT_REG_CLS BIT(1)
180 #define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \
181 NETSEC_COM_INIT_REG_DB)
183 #define NETSEC_SOFT_RST_REG_RESET 0
184 #define NETSEC_SOFT_RST_REG_RUN BIT(31)
186 #define NETSEC_DMA_CTRL_REG_STOP 1
187 #define MH_CTRL__MODE_TRANS BIT(20)
189 #define NETSEC_GMAC_CMD_ST_READ 0
190 #define NETSEC_GMAC_CMD_ST_WRITE BIT(28)
191 #define NETSEC_GMAC_CMD_ST_BUSY BIT(31)
193 #define NETSEC_GMAC_BMR_REG_COMMON 0x00412080
194 #define NETSEC_GMAC_BMR_REG_RESET 0x00020181
195 #define NETSEC_GMAC_BMR_REG_SWR 0x00000001
197 #define NETSEC_GMAC_OMR_REG_ST BIT(13)
198 #define NETSEC_GMAC_OMR_REG_SR BIT(1)
200 #define NETSEC_GMAC_MCR_REG_IBN BIT(30)
201 #define NETSEC_GMAC_MCR_REG_CST BIT(25)
202 #define NETSEC_GMAC_MCR_REG_JE BIT(20)
203 #define NETSEC_MCR_PS BIT(15)
204 #define NETSEC_GMAC_MCR_REG_FES BIT(14)
205 #define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c
206 #define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c
208 #define NETSEC_FCR_RFE BIT(2)
209 #define NETSEC_FCR_TFE BIT(1)
211 #define NETSEC_GMAC_GAR_REG_GW BIT(1)
212 #define NETSEC_GMAC_GAR_REG_GB BIT(0)
214 #define NETSEC_GMAC_GAR_REG_SHIFT_PA 11
215 #define NETSEC_GMAC_GAR_REG_SHIFT_GR 6
216 #define GMAC_REG_SHIFT_CR_GAR 2
218 #define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2
219 #define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3
220 #define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0
221 #define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1
222 #define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4
223 #define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5
225 #define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000
226 #define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000
228 #define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000
230 #define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31)
231 #define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30)
232 #define NETSEC_REG_DESC_TMR_MODE 4
233 #define NETSEC_REG_DESC_ENDIAN 0
235 #define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1
236 #define NETSEC_MAC_DESC_INIT_REG_INIT 1
238 #define NETSEC_EEPROM_MAC_ADDRESS 0x00
239 #define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08
240 #define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C
241 #define NETSEC_EEPROM_HM_ME_SIZE 0x10
242 #define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14
243 #define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18
244 #define NETSEC_EEPROM_MH_ME_SIZE 0x1C
245 #define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20
246 #define NETSEC_EEPROM_PKT_ME_SIZE 0x24
248 #define DESC_SZ sizeof(struct netsec_de)
250 #define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000)
252 #define EERPROM_MAP_OFFSET 0x8000000
253 #define NOR_BLOCK 1024
255 struct netsec_de { /* Netsec Descriptor layout */
257 u32 data_buf_addr_up;
258 u32 data_buf_addr_lw;
263 struct netsec_de rxde[PKTBUFSRX];
264 struct netsec_de txde[1];
267 phys_addr_t eeprom_base;
271 struct phy_device *phydev;
277 struct netsec_tx_pkt_ctrl {
279 bool tcp_seg_offload_flag;
280 bool cksum_offload_flag;
283 struct netsec_rx_pkt_info {
289 static void netsec_write_reg(struct netsec_priv *priv, u32 reg_addr, u32 val)
291 writel(val, priv->ioaddr + reg_addr);
294 static u32 netsec_read_reg(struct netsec_priv *priv, u32 reg_addr)
296 return readl(priv->ioaddr + reg_addr);
299 /************* MDIO BUS OPS FOLLOW *************/
301 #define TIMEOUT_SPINS_MAC 1000
302 #define TIMEOUT_SECONDARY_MS_MAC 100
304 static u32 netsec_clk_type(u32 freq)
307 return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ;
309 return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ;
311 return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ;
313 return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ;
315 return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ;
317 return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ;
320 static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask)
322 u32 timeout = TIMEOUT_SPINS_MAC;
324 while (--timeout && netsec_read_reg(priv, addr) & mask)
329 timeout = TIMEOUT_SECONDARY_MS_MAC;
330 while (--timeout && netsec_read_reg(priv, addr) & mask)
336 pr_err("%s: timeout\n", __func__);
341 static int netsec_set_mac_reg(struct netsec_priv *priv, u32 addr, u32 value)
343 netsec_write_reg(priv, MAC_REG_DATA, value);
344 netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);
345 return netsec_wait_while_busy(priv,
346 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
349 static int netsec_get_mac_reg(struct netsec_priv *priv, u32 addr, u32 *read)
353 netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);
354 ret = netsec_wait_while_busy(priv,
355 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
359 *read = netsec_read_reg(priv, MAC_REG_DATA);
364 static int netsec_mac_wait_while_busy(struct netsec_priv *priv,
367 u32 timeout = TIMEOUT_SPINS_MAC;
372 ret = netsec_get_mac_reg(priv, addr, &data);
376 } while (--timeout && (data & mask));
381 timeout = TIMEOUT_SECONDARY_MS_MAC;
385 ret = netsec_get_mac_reg(priv, addr, &data);
389 } while (--timeout && (data & mask));
397 static void netsec_cache_invalidate(uintptr_t vaddr, int len)
399 invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
400 roundup(vaddr + len, ARCH_DMA_MINALIGN));
403 static void netsec_cache_flush(uintptr_t vaddr, int len)
405 flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
406 roundup(vaddr + len, ARCH_DMA_MINALIGN));
409 static void netsec_set_rx_de(struct netsec_priv *priv, u16 idx, void *addr)
411 struct netsec_de *de = &priv->rxde[idx];
412 u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) |
413 (1 << NETSEC_RX_PKT_FS_FIELD) |
414 (1 << NETSEC_RX_PKT_LS_FIELD);
416 if (idx == PKTBUFSRX - 1)
417 attr |= (1 << NETSEC_RX_PKT_LD_FIELD);
419 de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr);
420 de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr);
421 de->buf_len_info = PKTSIZE;
424 netsec_cache_flush((uintptr_t)de, sizeof(*de));
427 static void netsec_set_tx_de(struct netsec_priv *priv, void *addr, int len)
429 struct netsec_de *de = &priv->txde[0];
432 attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) |
433 (1 << NETSEC_TX_SHIFT_PT_FIELD) |
434 (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) |
435 (1 << NETSEC_TX_SHIFT_FS_FIELD) |
436 (1 << NETSEC_TX_LAST) |
437 (1 << NETSEC_TX_SHIFT_TRS_FIELD) |
438 (1 << NETSEC_TX_SHIFT_LD_FIELD);
440 de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr);
441 de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr);
442 de->buf_len_info = len;
445 netsec_cache_flush((uintptr_t)de, sizeof(*de));
448 static int netsec_get_phy_reg(struct netsec_priv *priv,
449 int phy_addr, int reg_addr)
457 if (netsec_set_mac_reg(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB |
458 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
459 reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
460 (netsec_clk_type(priv->freq) <<
461 GMAC_REG_SHIFT_CR_GAR)))
464 ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
465 NETSEC_GMAC_GAR_REG_GB);
469 ret = netsec_get_mac_reg(priv, GMAC_REG_GDR, &data);
476 static int netsec_set_phy_reg(struct netsec_priv *priv,
477 int phy_addr, int reg_addr, u16 val)
483 if (netsec_set_mac_reg(priv, GMAC_REG_GDR, val))
486 if (netsec_set_mac_reg(priv, GMAC_REG_GAR,
487 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
488 reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
489 NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB |
490 (netsec_clk_type(priv->freq) <<
491 GMAC_REG_SHIFT_CR_GAR)))
494 ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
495 NETSEC_GMAC_GAR_REG_GB);
497 /* Developerbox implements RTL8211E PHY and there is
498 * a compatibility problem with F_GMAC4.
499 * RTL8211E expects MDC clock must be kept toggling for several
500 * clock cycle with MDIO high before entering the IDLE state.
501 * To meet this requirement, netsec driver needs to issue dummy
502 * read(e.g. read PHYID1(offset 0x2) register) right after write.
504 netsec_get_phy_reg(priv, phy_addr, MII_PHYSID1);
509 static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
511 struct phy_device *phydev = priv->phydev;
514 value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON :
515 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON;
517 if (phydev->speed != SPEED_1000)
518 value |= NETSEC_MCR_PS;
520 if (phydev->interface != PHY_INTERFACE_MODE_GMII &&
521 phydev->speed == SPEED_100)
522 value |= NETSEC_GMAC_MCR_REG_FES;
524 value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE;
526 if (phy_interface_is_rgmii(phydev))
527 value |= NETSEC_GMAC_MCR_REG_IBN;
529 if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value))
535 static int netsec_start_gmac(struct netsec_priv *priv)
540 if (priv->max_speed != SPEED_1000)
541 value = (NETSEC_GMAC_MCR_REG_CST |
542 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON);
544 if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value))
547 if (netsec_set_mac_reg(priv, GMAC_REG_BMR,
548 NETSEC_GMAC_BMR_REG_RESET))
551 /* Wait soft reset */
554 ret = netsec_get_mac_reg(priv, GMAC_REG_BMR, &value);
558 if (value & NETSEC_GMAC_BMR_REG_SWR)
561 netsec_write_reg(priv, MAC_REG_DESC_SOFT_RST, 1);
562 if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1))
565 netsec_write_reg(priv, MAC_REG_DESC_INIT, 1);
566 if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1))
569 if (netsec_set_mac_reg(priv, GMAC_REG_BMR,
570 NETSEC_GMAC_BMR_REG_COMMON))
573 if (netsec_set_mac_reg(priv, GMAC_REG_RDLAR,
574 NETSEC_GMAC_RDLAR_REG_COMMON))
577 if (netsec_set_mac_reg(priv, GMAC_REG_TDLAR,
578 NETSEC_GMAC_TDLAR_REG_COMMON))
581 if (netsec_set_mac_reg(priv, GMAC_REG_MFFR, 0x80000001))
584 ret = netsec_mac_update_to_phy_state(priv);
588 ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value);
592 value |= NETSEC_GMAC_OMR_REG_SR;
593 value |= NETSEC_GMAC_OMR_REG_ST;
595 netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
596 netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
598 if (netsec_set_mac_reg(priv, GMAC_REG_OMR, value))
604 static int netsec_stop_gmac(struct netsec_priv *priv)
609 ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value);
612 value &= ~NETSEC_GMAC_OMR_REG_SR;
613 value &= ~NETSEC_GMAC_OMR_REG_ST;
615 /* disable all interrupts */
616 netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
617 netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
619 return netsec_set_mac_reg(priv, GMAC_REG_OMR, value);
622 static void netsec_spi_read(char *buf, loff_t len, loff_t offset)
625 struct spi_flash *flash;
627 spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
628 CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE, &new);
629 flash = dev_get_uclass_priv(new);
631 spi_flash_read(flash, offset, len, buf);
634 static int netsec_read_rom_hwaddr(struct udevice *dev)
636 struct netsec_priv *priv = dev_get_priv(dev);
637 struct eth_pdata *pdata = dev_get_plat(dev);
638 char macp[NOR_BLOCK];
640 netsec_spi_read(macp, sizeof(macp), priv->eeprom_base);
642 pdata->enetaddr[0] = readb(macp + 3);
643 pdata->enetaddr[1] = readb(macp + 2);
644 pdata->enetaddr[2] = readb(macp + 1);
645 pdata->enetaddr[3] = readb(macp + 0);
646 pdata->enetaddr[4] = readb(macp + 7);
647 pdata->enetaddr[5] = readb(macp + 6);
651 static int netsec_send(struct udevice *dev, void *packet, int length)
653 struct netsec_priv *priv = dev_get_priv(dev);
656 val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_STATUS);
657 netsec_cache_flush((uintptr_t)packet, length);
658 netsec_set_tx_de(priv, packet, length);
659 netsec_write_reg(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */
661 val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT);
665 val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT);
667 } while (--tout && !val);
670 val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT);
671 pr_err("%s: ETIMEDOUT: %dpackets\n", __func__, val);
678 static int netsec_free_packet(struct udevice *dev, uchar *packet, int length)
680 struct netsec_priv *priv = dev_get_priv(dev);
682 netsec_set_rx_de(priv, priv->rxat, net_rx_packets[priv->rxat]);
685 if (priv->rxat == PKTBUFSRX)
691 static int netsec_recv(struct udevice *dev, int flags, uchar **packetp)
693 struct netsec_priv *priv = dev_get_priv(dev);
694 int idx = priv->rxat;
695 uchar *ptr = net_rx_packets[idx];
696 struct netsec_de *de = &priv->rxde[idx];
699 netsec_cache_invalidate((uintptr_t)de, sizeof(*de));
701 if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD))
704 length = de->buf_len_info >> 16;
706 /* invalidate after DMA is done */
707 netsec_cache_invalidate((uintptr_t)ptr, length);
713 static int _netsec_get_phy_reg(struct mii_dev *bus,
714 int phy_addr, int devad, int reg_addr)
716 return netsec_get_phy_reg(bus->priv, phy_addr, reg_addr);
719 static int _netsec_set_phy_reg(struct mii_dev *bus,
720 int phy_addr, int devad, int reg_addr, u16 val)
722 return netsec_set_phy_reg(bus->priv, phy_addr, reg_addr, val);
725 static int netsec_mdiobus_init(struct netsec_priv *priv, const char *name)
727 struct mii_dev *bus = mdio_alloc();
732 bus->read = _netsec_get_phy_reg;
733 bus->write = _netsec_set_phy_reg;
734 snprintf(bus->name, sizeof(bus->name), "%s", name);
737 return mdio_register(bus);
740 static int netsec_phy_init(struct netsec_priv *priv, void *dev)
742 struct phy_device *phydev;
745 phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
747 phydev->supported &= PHY_GBIT_FEATURES;
748 if (priv->max_speed) {
749 ret = phy_set_supported(phydev, priv->max_speed);
753 phydev->advertising = phydev->supported;
755 priv->phydev = phydev;
761 static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg,
762 u32 addr_h, u32 addr_l, u32 size)
764 u64 base = ((u64)addr_h << 32 | addr_l) - EERPROM_MAP_OFFSET;
768 u32 *ucode = (u32 *)buf;
772 off = base % NOR_BLOCK;
774 netsec_spi_read(buf, sizeof(buf), base);
776 for (i = off / 4; i < sizeof(buf) / 4 && size > 0; i++, size--)
777 netsec_write_reg(priv, reg, ucode[i]);
784 static int netsec_netdev_load_microcode(struct netsec_priv *priv)
786 u32 addr_h, addr_l, size;
788 u32 *ucinfo = (u32 *)buf;
791 netsec_spi_read(buf, sizeof(buf), priv->eeprom_base);
793 addr_h = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_H >> 2];
794 addr_l = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_L >> 2];
795 size = ucinfo[NETSEC_EEPROM_HM_ME_SIZE >> 2];
797 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF,
798 addr_h, addr_l, size);
802 addr_h = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_H >> 2];
803 addr_l = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_L >> 2];
804 size = ucinfo[NETSEC_EEPROM_MH_ME_SIZE >> 2];
806 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF,
807 addr_h, addr_l, size);
812 addr_l = ucinfo[NETSEC_EEPROM_PKT_ME_ADDRESS >> 2];
813 size = ucinfo[NETSEC_EEPROM_PKT_ME_SIZE >> 2];
815 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF,
816 addr_h, addr_l, size);
823 void netsec_pre_init_microengine(struct netsec_priv *priv)
827 /* Remove dormant settings */
828 data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR);
830 data |= BMCR_ISOLATE;
831 netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
834 /* Put phy in loopback mode to guarantee RXCLK input */
835 data |= BMCR_LOOPBACK;
836 netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
840 void netsec_post_init_microengine(struct netsec_priv *priv)
844 /* Get phy back to normal operation */
845 data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR);
846 data &= ~BMCR_LOOPBACK;
847 netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
850 /* Apply software reset */
852 netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data);
856 static int netsec_reset_hardware(struct netsec_priv *priv, bool load_ucode)
861 netsec_write_reg(priv, NETSEC_REG_CLK_EN, 0x24);
863 /* stop DMA engines */
864 if (!netsec_read_reg(priv, NETSEC_REG_ADDR_DIS_CORE)) {
865 netsec_write_reg(priv, NETSEC_REG_DMA_HM_CTRL,
866 NETSEC_DMA_CTRL_REG_STOP);
867 netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL,
868 NETSEC_DMA_CTRL_REG_STOP);
871 while (netsec_read_reg(priv, NETSEC_REG_DMA_HM_CTRL) &
872 NETSEC_DMA_CTRL_REG_STOP) {
875 pr_err("%s:%d timeout!\n", __func__, __LINE__);
881 while (netsec_read_reg(priv, NETSEC_REG_DMA_MH_CTRL) &
882 NETSEC_DMA_CTRL_REG_STOP) {
885 pr_err("%s:%d timeout!\n", __func__, __LINE__);
891 netsec_set_mac_reg(priv, GMAC_REG_BMR, NETSEC_GMAC_BMR_REG_RESET);
893 netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET);
894 netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);
895 netsec_write_reg(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);
898 while (netsec_read_reg(priv, NETSEC_REG_COM_INIT) != 0) {
901 pr_err("%s:%d COM_INIT timeout!\n", __func__, __LINE__);
907 netsec_write_reg(priv, MAC_REG_DESC_INIT, 1);
908 netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1);
909 /* set MAC_INTF_SEL */
910 netsec_write_reg(priv, MAC_REG_INTF_SEL, 1);
912 netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
914 /* set desc_start addr */
915 netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
916 upper_32_bits((dma_addr_t)priv->rxde));
917 netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
918 lower_32_bits((dma_addr_t)priv->rxde));
920 netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
921 upper_32_bits((dma_addr_t)priv->txde));
922 netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
923 lower_32_bits((dma_addr_t)priv->txde));
925 /* set normal tx dring ring config */
926 netsec_write_reg(priv, NETSEC_REG_NRM_TX_CONFIG,
927 1 << NETSEC_REG_DESC_ENDIAN);
928 netsec_write_reg(priv, NETSEC_REG_NRM_RX_CONFIG,
929 1 << NETSEC_REG_DESC_ENDIAN);
932 err = netsec_netdev_load_microcode(priv);
934 pr_err("%s: failed to load microcode (%d)\n",
940 /* set desc_start addr */
941 netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
942 upper_32_bits((dma_addr_t)priv->rxde));
943 netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
944 lower_32_bits((dma_addr_t)priv->rxde));
946 netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
947 upper_32_bits((dma_addr_t)priv->txde));
948 netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
949 lower_32_bits((dma_addr_t)priv->txde));
951 netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
953 /* start DMA engines */
954 netsec_write_reg(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1);
956 netsec_pre_init_microengine(priv);
958 netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 0);
962 if (!(netsec_read_reg(priv, NETSEC_REG_TOP_STATUS) &
963 NETSEC_TOP_IRQ_REG_ME_START)) {
964 pr_err("microengine start failed\n");
968 netsec_post_init_microengine(priv);
970 /* clear microcode load end status */
971 netsec_write_reg(priv, NETSEC_REG_TOP_STATUS,
972 NETSEC_TOP_IRQ_REG_ME_START);
974 netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5);
976 value = netsec_read_reg(priv, NETSEC_REG_PKT_CTRL);
977 value |= NETSEC_PKT_CTRL_REG_MODE_NRM;
978 /* change to normal mode */
979 netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);
980 netsec_write_reg(priv, NETSEC_REG_PKT_CTRL, value);
983 while ((netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) &
984 NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) {
987 value = netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS);
988 pr_err("%s:%d timeout! val=%x\n", __func__, __LINE__, value);
993 /* clear any pending EMPTY/ERR irq status */
994 netsec_write_reg(priv, NETSEC_REG_NRM_TX_STATUS, ~0);
996 /* Disable TX & RX intr */
997 netsec_write_reg(priv, NETSEC_REG_INTEN_CLR, ~0);
1002 static void netsec_stop(struct udevice *dev)
1004 struct netsec_priv *priv = dev_get_priv(dev);
1006 netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 7);
1007 netsec_stop_gmac(priv);
1008 phy_shutdown(priv->phydev);
1009 netsec_reset_hardware(priv, false);
1012 static int netsec_start(struct udevice *dev)
1014 struct netsec_priv *priv = dev_get_priv(dev);
1017 phy_startup(priv->phydev);
1018 netsec_start_gmac(priv);
1021 for (i = 0; i < PKTBUFSRX; i++)
1022 netsec_set_rx_de(priv, i, net_rx_packets[i]);
1027 static int netsec_of_to_plat(struct udevice *dev)
1029 struct eth_pdata *pdata = dev_get_plat(dev);
1030 struct netsec_priv *priv = dev_get_priv(dev);
1031 struct ofnode_phandle_args phandle_args;
1032 const char *phy_mode;
1034 pdata->iobase = dev_read_addr_index(dev, 0);
1035 priv->eeprom_base = dev_read_addr_index(dev, 1) - EERPROM_MAP_OFFSET;
1037 pdata->phy_interface = -1;
1038 phy_mode = dev_read_prop(dev, "phy-mode", NULL);
1040 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1041 if (pdata->phy_interface == -1) {
1042 pr_err("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1046 if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1048 priv->phy_addr = ofnode_read_u32_default(phandle_args.node, "reg", 7);
1052 pdata->max_speed = dev_read_u32_default(dev, "max-speed", SPEED_1000);
1054 priv->ioaddr = pdata->iobase;
1055 priv->phy_mode = pdata->phy_interface;
1056 priv->max_speed = pdata->max_speed;
1057 priv->freq = 250000000UL;
1062 static int netsec_probe(struct udevice *dev)
1064 struct netsec_priv *priv = dev_get_priv(dev);
1067 netsec_reset_hardware(priv, true);
1069 ret = netsec_mdiobus_init(priv, dev->name);
1071 pr_err("Failed to initialize mdiobus: %d\n", ret);
1075 priv->bus = miiphy_get_dev_by_name(dev->name);
1077 ret = netsec_phy_init(priv, dev);
1079 pr_err("Failed to initialize phy: %d\n", ret);
1080 goto out_mdiobus_release;
1084 out_mdiobus_release:
1085 mdio_unregister(priv->bus);
1086 mdio_free(priv->bus);
1090 static int netsec_remove(struct udevice *dev)
1092 struct netsec_priv *priv = dev_get_priv(dev);
1095 mdio_unregister(priv->bus);
1096 mdio_free(priv->bus);
1101 static const struct eth_ops netsec_ops = {
1102 .start = netsec_start,
1103 .stop = netsec_stop,
1104 .send = netsec_send,
1105 .recv = netsec_recv,
1106 .free_pkt = netsec_free_packet,
1107 .read_rom_hwaddr = netsec_read_rom_hwaddr,
1110 static const struct udevice_id netsec_ids[] = {
1112 .compatible = "socionext,synquacer-netsec",
1117 U_BOOT_DRIVER(ave) = {
1118 .name = "synquacer_netsec",
1120 .of_match = netsec_ids,
1121 .probe = netsec_probe,
1122 .remove = netsec_remove,
1123 .of_to_plat = netsec_of_to_plat,
1125 .priv_auto = sizeof(struct netsec_priv),
1126 .plat_auto = sizeof(struct eth_pdata),