2 * SMSC LAN9[12]1[567] Network driver
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #if defined (CONFIG_DRIVER_SMC911X_32_BIT) && \
31 defined (CONFIG_DRIVER_SMC911X_16_BIT)
32 #error "SMC911X: Only one of CONFIG_DRIVER_SMC911X_32_BIT and \
33 CONFIG_DRIVER_SMC911X_16_BIT shall be set"
36 #if defined (CONFIG_DRIVER_SMC911X_32_BIT)
37 static inline u32 reg_read(u32 addr)
39 return *(volatile u32*)addr;
41 static inline void reg_write(u32 addr, u32 val)
43 *(volatile u32*)addr = val;
45 #elif defined (CONFIG_DRIVER_SMC911X_16_BIT)
46 static inline u32 reg_read(u32 addr)
48 volatile u16 *addr_16 = (u16 *)addr;
49 return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
51 static inline void reg_write(u32 addr, u32 val)
53 *(volatile u16*)addr = (u16)val;
54 *(volatile u16*)(addr + 2) = (u16)(val >> 16);
57 #error "SMC911X: undefined bus width"
58 #endif /* CONFIG_DRIVER_SMC911X_16_BIT */
60 #define mdelay(n) udelay((n)*1000)
62 /* Below are the register offsets and bit definitions
63 * of the Lan911x memory space
65 #define RX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x00)
67 #define TX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x20)
68 #define TX_CMD_A_INT_ON_COMP 0x80000000
69 #define TX_CMD_A_INT_BUF_END_ALGN 0x03000000
70 #define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000
71 #define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000
72 #define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000
73 #define TX_CMD_A_INT_DATA_OFFSET 0x001F0000
74 #define TX_CMD_A_INT_FIRST_SEG 0x00002000
75 #define TX_CMD_A_INT_LAST_SEG 0x00001000
76 #define TX_CMD_A_BUF_SIZE 0x000007FF
77 #define TX_CMD_B_PKT_TAG 0xFFFF0000
78 #define TX_CMD_B_ADD_CRC_DISABLE 0x00002000
79 #define TX_CMD_B_DISABLE_PADDING 0x00001000
80 #define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF
82 #define RX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x40)
83 #define RX_STS_PKT_LEN 0x3FFF0000
84 #define RX_STS_ES 0x00008000
85 #define RX_STS_BCST 0x00002000
86 #define RX_STS_LEN_ERR 0x00001000
87 #define RX_STS_RUNT_ERR 0x00000800
88 #define RX_STS_MCAST 0x00000400
89 #define RX_STS_TOO_LONG 0x00000080
90 #define RX_STS_COLL 0x00000040
91 #define RX_STS_ETH_TYPE 0x00000020
92 #define RX_STS_WDOG_TMT 0x00000010
93 #define RX_STS_MII_ERR 0x00000008
94 #define RX_STS_DRIBBLING 0x00000004
95 #define RX_STS_CRC_ERR 0x00000002
96 #define RX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x44)
97 #define TX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x48)
98 #define TX_STS_TAG 0xFFFF0000
99 #define TX_STS_ES 0x00008000
100 #define TX_STS_LOC 0x00000800
101 #define TX_STS_NO_CARR 0x00000400
102 #define TX_STS_LATE_COLL 0x00000200
103 #define TX_STS_MANY_COLL 0x00000100
104 #define TX_STS_COLL_CNT 0x00000078
105 #define TX_STS_MANY_DEFER 0x00000004
106 #define TX_STS_UNDERRUN 0x00000002
107 #define TX_STS_DEFERRED 0x00000001
108 #define TX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x4C)
109 #define ID_REV (CONFIG_DRIVER_SMC911X_BASE + 0x50)
110 #define ID_REV_CHIP_ID 0xFFFF0000 /* RO */
111 #define ID_REV_REV_ID 0x0000FFFF /* RO */
113 #define INT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x54)
114 #define INT_CFG_INT_DEAS 0xFF000000 /* R/W */
115 #define INT_CFG_INT_DEAS_CLR 0x00004000
116 #define INT_CFG_INT_DEAS_STS 0x00002000
117 #define INT_CFG_IRQ_INT 0x00001000 /* RO */
118 #define INT_CFG_IRQ_EN 0x00000100 /* R/W */
119 #define INT_CFG_IRQ_POL 0x00000010 /* R/W Not Affected by SW Reset */
120 #define INT_CFG_IRQ_TYPE 0x00000001 /* R/W Not Affected by SW Reset */
122 #define INT_STS (CONFIG_DRIVER_SMC911X_BASE + 0x58)
123 #define INT_STS_SW_INT 0x80000000 /* R/WC */
124 #define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */
125 #define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */
126 #define INT_STS_RXDFH_INT 0x00800000 /* R/WC */
127 #define INT_STS_RXDF_INT 0x00400000 /* R/WC */
128 #define INT_STS_TX_IOC 0x00200000 /* R/WC */
129 #define INT_STS_RXD_INT 0x00100000 /* R/WC */
130 #define INT_STS_GPT_INT 0x00080000 /* R/WC */
131 #define INT_STS_PHY_INT 0x00040000 /* RO */
132 #define INT_STS_PME_INT 0x00020000 /* R/WC */
133 #define INT_STS_TXSO 0x00010000 /* R/WC */
134 #define INT_STS_RWT 0x00008000 /* R/WC */
135 #define INT_STS_RXE 0x00004000 /* R/WC */
136 #define INT_STS_TXE 0x00002000 /* R/WC */
137 /*#define INT_STS_ERX 0x00001000*/ /* R/WC */
138 #define INT_STS_TDFU 0x00000800 /* R/WC */
139 #define INT_STS_TDFO 0x00000400 /* R/WC */
140 #define INT_STS_TDFA 0x00000200 /* R/WC */
141 #define INT_STS_TSFF 0x00000100 /* R/WC */
142 #define INT_STS_TSFL 0x00000080 /* R/WC */
143 /*#define INT_STS_RXDF 0x00000040*/ /* R/WC */
144 #define INT_STS_RDFO 0x00000040 /* R/WC */
145 #define INT_STS_RDFL 0x00000020 /* R/WC */
146 #define INT_STS_RSFF 0x00000010 /* R/WC */
147 #define INT_STS_RSFL 0x00000008 /* R/WC */
148 #define INT_STS_GPIO2_INT 0x00000004 /* R/WC */
149 #define INT_STS_GPIO1_INT 0x00000002 /* R/WC */
150 #define INT_STS_GPIO0_INT 0x00000001 /* R/WC */
151 #define INT_EN (CONFIG_DRIVER_SMC911X_BASE + 0x5C)
152 #define INT_EN_SW_INT_EN 0x80000000 /* R/W */
153 #define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */
154 #define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */
155 #define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */
156 /*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */
157 #define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */
158 #define INT_EN_RXD_INT_EN 0x00100000 /* R/W */
159 #define INT_EN_GPT_INT_EN 0x00080000 /* R/W */
160 #define INT_EN_PHY_INT_EN 0x00040000 /* R/W */
161 #define INT_EN_PME_INT_EN 0x00020000 /* R/W */
162 #define INT_EN_TXSO_EN 0x00010000 /* R/W */
163 #define INT_EN_RWT_EN 0x00008000 /* R/W */
164 #define INT_EN_RXE_EN 0x00004000 /* R/W */
165 #define INT_EN_TXE_EN 0x00002000 /* R/W */
166 /*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */
167 #define INT_EN_TDFU_EN 0x00000800 /* R/W */
168 #define INT_EN_TDFO_EN 0x00000400 /* R/W */
169 #define INT_EN_TDFA_EN 0x00000200 /* R/W */
170 #define INT_EN_TSFF_EN 0x00000100 /* R/W */
171 #define INT_EN_TSFL_EN 0x00000080 /* R/W */
172 /*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */
173 #define INT_EN_RDFO_EN 0x00000040 /* R/W */
174 #define INT_EN_RDFL_EN 0x00000020 /* R/W */
175 #define INT_EN_RSFF_EN 0x00000010 /* R/W */
176 #define INT_EN_RSFL_EN 0x00000008 /* R/W */
177 #define INT_EN_GPIO2_INT 0x00000004 /* R/W */
178 #define INT_EN_GPIO1_INT 0x00000002 /* R/W */
179 #define INT_EN_GPIO0_INT 0x00000001 /* R/W */
181 #define BYTE_TEST (CONFIG_DRIVER_SMC911X_BASE + 0x64)
182 #define FIFO_INT (CONFIG_DRIVER_SMC911X_BASE + 0x68)
183 #define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */
184 #define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */
185 #define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */
186 #define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */
188 #define RX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x6C)
189 #define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */
190 #define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */
191 #define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */
192 #define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */
193 #define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */
194 #define RX_CFG_RX_DUMP 0x00008000 /* R/W */
195 #define RX_CFG_RXDOFF 0x00001F00 /* R/W */
196 /*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */
198 #define TX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x70)
199 /*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */
200 /*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/ /* R/W Self Clearing */
201 #define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */
202 #define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */
203 #define TX_CFG_TXSAO 0x00000004 /* R/W */
204 #define TX_CFG_TX_ON 0x00000002 /* R/W */
205 #define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */
207 #define HW_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x74)
208 #define HW_CFG_TTM 0x00200000 /* R/W */
209 #define HW_CFG_SF 0x00100000 /* R/W */
210 #define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */
211 #define HW_CFG_TR 0x00003000 /* R/W */
212 #define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */
213 #define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */
214 #define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */
215 #define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */
216 #define HW_CFG_SMI_SEL 0x00000010 /* R/W */
217 #define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */
218 #define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */
219 #define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */
220 #define HW_CFG_SRST_TO 0x00000002 /* RO */
221 #define HW_CFG_SRST 0x00000001 /* Self Clearing */
223 #define RX_DP_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x78)
224 #define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */
225 #define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */
227 #define RX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x7C)
228 #define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */
229 #define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */
231 #define TX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x80)
232 #define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */
233 #define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */
235 #define PMT_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x84)
236 #define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */
237 #define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */
238 #define PMT_CTRL_WOL_EN 0x00000200 /* R/W */
239 #define PMT_CTRL_ED_EN 0x00000100 /* R/W */
240 #define PMT_CTRL_PME_TYPE 0x00000040 /* R/W Not Affected by SW Reset */
241 #define PMT_CTRL_WUPS 0x00000030 /* R/WC */
242 #define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */
243 #define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */
244 #define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */
245 #define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */
246 #define PMT_CTRL_PME_IND 0x00000008 /* R/W */
247 #define PMT_CTRL_PME_POL 0x00000004 /* R/W */
248 #define PMT_CTRL_PME_EN 0x00000002 /* R/W Not Affected by SW Reset */
249 #define PMT_CTRL_READY 0x00000001 /* RO */
251 #define GPIO_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x88)
252 #define GPIO_CFG_LED3_EN 0x40000000 /* R/W */
253 #define GPIO_CFG_LED2_EN 0x20000000 /* R/W */
254 #define GPIO_CFG_LED1_EN 0x10000000 /* R/W */
255 #define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */
256 #define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */
257 #define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */
258 #define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */
259 #define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */
260 #define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */
261 #define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */
262 #define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */
263 #define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */
264 #define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */
265 #define GPIO_CFG_GPIOD4 0x00000010 /* R/W */
266 #define GPIO_CFG_GPIOD3 0x00000008 /* R/W */
267 #define GPIO_CFG_GPIOD2 0x00000004 /* R/W */
268 #define GPIO_CFG_GPIOD1 0x00000002 /* R/W */
269 #define GPIO_CFG_GPIOD0 0x00000001 /* R/W */
271 #define GPT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x8C)
272 #define GPT_CFG_TIMER_EN 0x20000000 /* R/W */
273 #define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */
275 #define GPT_CNT (CONFIG_DRIVER_SMC911X_BASE + 0x90)
276 #define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */
278 #define ENDIAN (CONFIG_DRIVER_SMC911X_BASE + 0x98)
279 #define FREE_RUN (CONFIG_DRIVER_SMC911X_BASE + 0x9C)
280 #define RX_DROP (CONFIG_DRIVER_SMC911X_BASE + 0xA0)
281 #define MAC_CSR_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xA4)
282 #define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */
283 #define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */
284 #define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */
286 #define MAC_CSR_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xA8)
287 #define AFC_CFG (CONFIG_DRIVER_SMC911X_BASE + 0xAC)
288 #define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */
289 #define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */
290 #define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */
291 #define AFC_CFG_FCMULT 0x00000008 /* R/W */
292 #define AFC_CFG_FCBRD 0x00000004 /* R/W */
293 #define AFC_CFG_FCADD 0x00000002 /* R/W */
294 #define AFC_CFG_FCANY 0x00000001 /* R/W */
296 #define E2P_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xB0)
297 #define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */
298 #define E2P_CMD_EPC_CMD 0x70000000 /* R/W */
299 #define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */
300 #define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */
301 #define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */
302 #define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */
303 #define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */
304 #define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */
305 #define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */
306 #define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */
307 #define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */
308 #define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */
309 #define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */
311 #define E2P_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xB4)
312 #define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */
313 /* end of LAN register offsets and bit definitions */
315 /* MAC Control and Status registers */
316 #define MAC_CR 0x01 /* R/W */
318 /* MAC_CR - MAC Control Register */
319 #define MAC_CR_RXALL 0x80000000
320 /* TODO: delete this bit? It is not described in the data sheet. */
321 #define MAC_CR_HBDIS 0x10000000
322 #define MAC_CR_RCVOWN 0x00800000
323 #define MAC_CR_LOOPBK 0x00200000
324 #define MAC_CR_FDPX 0x00100000
325 #define MAC_CR_MCPAS 0x00080000
326 #define MAC_CR_PRMS 0x00040000
327 #define MAC_CR_INVFILT 0x00020000
328 #define MAC_CR_PASSBAD 0x00010000
329 #define MAC_CR_HFILT 0x00008000
330 #define MAC_CR_HPFILT 0x00002000
331 #define MAC_CR_LCOLL 0x00001000
332 #define MAC_CR_BCAST 0x00000800
333 #define MAC_CR_DISRTY 0x00000400
334 #define MAC_CR_PADSTR 0x00000100
335 #define MAC_CR_BOLMT_MASK 0x000000C0
336 #define MAC_CR_DFCHK 0x00000020
337 #define MAC_CR_TXEN 0x00000008
338 #define MAC_CR_RXEN 0x00000004
340 #define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */
341 #define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */
342 #define HASHH 0x04 /* R/W */
343 #define HASHL 0x05 /* R/W */
345 #define MII_ACC 0x06 /* R/W */
346 #define MII_ACC_PHY_ADDR 0x0000F800
347 #define MII_ACC_MIIRINDA 0x000007C0
348 #define MII_ACC_MII_WRITE 0x00000002
349 #define MII_ACC_MII_BUSY 0x00000001
351 #define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */
353 #define FLOW 0x08 /* R/W */
354 #define FLOW_FCPT 0xFFFF0000
355 #define FLOW_FCPASS 0x00000004
356 #define FLOW_FCEN 0x00000002
357 #define FLOW_FCBSY 0x00000001
359 #define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */
360 #define VLAN1_VTI1 0x0000ffff
362 #define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */
363 #define VLAN2_VTI2 0x0000ffff
365 #define WUFF 0x0B /* WO */
367 #define WUCSR 0x0C /* R/W */
368 #define WUCSR_GUE 0x00000200
369 #define WUCSR_WUFR 0x00000040
370 #define WUCSR_MPR 0x00000020
371 #define WUCSR_WAKE_EN 0x00000004
372 #define WUCSR_MPEN 0x00000002
375 #define CHIP_9115 0x115
376 #define CHIP_9116 0x116
377 #define CHIP_9117 0x117
378 #define CHIP_9118 0x118
379 #define CHIP_9215 0x115a
380 #define CHIP_9216 0x116a
381 #define CHIP_9217 0x117a
382 #define CHIP_9218 0x118a
389 static const struct chip_id chip_ids[] = {
390 { CHIP_9115, "LAN9115" },
391 { CHIP_9116, "LAN9116" },
392 { CHIP_9117, "LAN9117" },
393 { CHIP_9118, "LAN9118" },
394 { CHIP_9215, "LAN9215" },
395 { CHIP_9216, "LAN9216" },
396 { CHIP_9217, "LAN9217" },
397 { CHIP_9218, "LAN9218" },
401 #define DRIVERNAME "smc911x"
403 u32 smc911x_get_mac_csr(u8 reg)
405 while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
407 reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
408 while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
411 return reg_read(MAC_CSR_DATA);
414 void smc911x_set_mac_csr(u8 reg, u32 data)
416 while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
418 reg_write(MAC_CSR_DATA, data);
419 reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
420 while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
424 static int smx911x_handle_mac_address(bd_t *bd)
426 unsigned long addrh, addrl;
427 unsigned char *m = bd->bi_enetaddr;
429 /* if the environment has a valid mac address then use it */
430 if ((m[0] | m[1] | m[2] | m[3] | m[4] | m[5])) {
431 addrl = m[0] | m[1] << 8 | m[2] << 16 | m[3] << 24;
432 addrh = m[4] | m[5] << 8;
433 smc911x_set_mac_csr(ADDRH, addrh);
434 smc911x_set_mac_csr(ADDRL, addrl);
436 /* if not, try to get one from the eeprom */
437 addrh = smc911x_get_mac_csr(ADDRH);
438 addrl = smc911x_get_mac_csr(ADDRL);
440 m[0] = (addrl ) & 0xff;
441 m[1] = (addrl >> 8 ) & 0xff;
442 m[2] = (addrl >> 16 ) & 0xff;
443 m[3] = (addrl >> 24 ) & 0xff;
444 m[4] = (addrh ) & 0xff;
445 m[5] = (addrh >> 8 ) & 0xff;
447 /* we get 0xff when there is no eeprom connected */
448 if ((m[0] & m[1] & m[2] & m[3] & m[4] & m[5]) == 0xff) {
449 printf(DRIVERNAME ": no valid mac address in environment "
450 "and no eeprom found\n");
455 printf(DRIVERNAME ": MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
456 m[0], m[1], m[2], m[3], m[4], m[5]);
461 static int smc911x_miiphy_read(u8 phy, u8 reg, u16 *val)
463 while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY)
466 smc911x_set_mac_csr(MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY);
468 while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY)
471 *val = smc911x_get_mac_csr(MII_DATA);
476 static int smc911x_miiphy_write(u8 phy, u8 reg, u16 val)
478 while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY)
481 smc911x_set_mac_csr(MII_DATA, val);
482 smc911x_set_mac_csr(MII_ACC,
483 phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
485 while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY)
490 static int smc911x_phy_reset(void)
494 reg = reg_read(PMT_CTRL);
496 reg |= PMT_CTRL_PHY_RST;
497 reg_write(PMT_CTRL, reg);
504 static void smc911x_phy_configure(void)
511 smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_RESET);
513 smc911x_miiphy_write(1, PHY_ANAR, 0x01e1);
514 smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
519 if ((timeout--) == 0)
522 if (smc911x_miiphy_read(1, PHY_BMSR, &status) != 0)
524 } while (!(status & PHY_BMSR_LS));
526 printf(DRIVERNAME ": phy initialized\n");
531 printf(DRIVERNAME ": autonegotiation timed out\n");
534 static void smc911x_reset(void)
538 /* Take out of PM setting first */
539 if (reg_read(PMT_CTRL) & PMT_CTRL_READY) {
540 /* Write to the bytetest will take out of powerdown */
541 reg_write(BYTE_TEST, 0x0);
545 while (timeout-- && !(reg_read(PMT_CTRL) & PMT_CTRL_READY))
549 ": timeout waiting for PM restore\n");
554 /* Disable interrupts */
555 reg_write(INT_EN, 0);
557 reg_write(HW_CFG, HW_CFG_SRST);
560 while (timeout-- && reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
564 printf(DRIVERNAME ": reset timeout\n");
568 /* Reset the FIFO level and flow control settings */
569 smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN);
570 reg_write(AFC_CFG, 0x0050287F);
572 /* Set to LED outputs */
573 reg_write(GPIO_CFG, 0x70070000);
576 static void smc911x_enable(void)
579 reg_write(HW_CFG, 8 << 16 | HW_CFG_SF);
581 reg_write(GPT_CFG, GPT_CFG_TIMER_EN | 10000);
583 reg_write(TX_CFG, TX_CFG_TX_ON);
585 /* no padding to start of packets */
586 reg_write(RX_CFG, 0);
588 smc911x_set_mac_csr(MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS);
592 int eth_init(bd_t *bd)
594 unsigned long val, i;
596 printf(DRIVERNAME ": initializing\n");
598 val = reg_read(BYTE_TEST);
599 if (val != 0x87654321) {
600 printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
604 val = reg_read(ID_REV) >> 16;
605 for (i = 0; chip_ids[i].id != 0; i++) {
606 if (chip_ids[i].id == val) break;
608 if (!chip_ids[i].id) {
609 printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
613 printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name);
617 /* Configure the PHY, initialize the link state */
618 smc911x_phy_configure();
620 if (smx911x_handle_mac_address(bd))
623 /* Turn on Tx + Rx */
632 int eth_send(volatile void *packet, int length)
634 u32 *data = (u32*)packet;
638 reg_write(TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length);
639 reg_write(TX_DATA_FIFO, length);
641 tmplen = (length + 3) / 4;
644 reg_write(TX_DATA_FIFO, *data++);
646 /* wait for transmission */
647 while (!((reg_read(TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16));
649 /* get status. Ignore 'no carrier' error, it has no meaning for
650 * full duplex operation
652 status = reg_read(TX_STATUS_FIFO) & (TX_STS_LOC | TX_STS_LATE_COLL |
653 TX_STS_MANY_COLL | TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
658 printf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
659 status & TX_STS_LOC ? "TX_STS_LOC " : "",
660 status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "",
661 status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "",
662 status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "",
663 status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : "");
675 u32 *data = (u32 *)NetRxPackets[0];
679 if ((reg_read(RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) {
680 status = reg_read(RX_STATUS_FIFO);
681 pktlen = (status & RX_STS_PKT_LEN) >> 16;
683 reg_write(RX_CFG, 0);
685 tmplen = (pktlen + 2+ 3) / 4;
687 *data++ = reg_read(RX_DATA_FIFO);
689 if (status & RX_STS_ES)
691 ": dropped bad packet. Status: 0x%08x\n",
694 NetReceive(NetRxPackets[0], pktlen);