1 /*------------------------------------------------------------------------
3 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 . Rolf Offermanns <rof@sysgo.de>
9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
10 . Developed by Simple Network Magic Corporation (SNMC)
11 . Copyright (C) 1996 by Erik Stahlman (ES)
13 . This program is free software; you can redistribute it and/or modify
14 . it under the terms of the GNU General Public License as published by
15 . the Free Software Foundation; either version 2 of the License, or
16 . (at your option) any later version.
18 . This program is distributed in the hope that it will be useful,
19 . but WITHOUT ANY WARRANTY; without even the implied warranty of
20 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 . GNU General Public License for more details.
23 . You should have received a copy of the GNU General Public License
24 . along with this program; if not, write to the Free Software
25 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 . Information contained in this file was obtained from the LAN91C111
28 . manual from SMC. To get a copy, if you really want one, you can find
29 . information under www.smsc.com.
32 . "Features" of the SMC chip:
33 . Integrated PHY/MAC for 10/100BaseT Operation
34 . Supports internal and external MII
35 . Integrated 8K packet memory
36 . EEPROM interface for configuration
39 . io = for the base address
43 . Erik Stahlman ( erik@vt.edu )
44 . Daris A Nevil ( dnevil@snmc.com )
47 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
50 . o SMSC LAN91C111 databook (www.smsc.com)
51 . o smc9194.c by Erik Stahlman
52 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
55 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
56 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
57 . 07/25/01 Woojung Huh Modify for ADS Bitsy
58 . 04/25/01 Daris A Nevil Initial public release through SMSC
59 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
60 ----------------------------------------------------------------------------*/
69 /* Use power-down feature of the chip */
77 static const char version[] =
78 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
81 /* Autonegotiation timeout in seconds */
82 #ifndef CONFIG_SMC_AUTONEG_TIMEOUT
83 #define CONFIG_SMC_AUTONEG_TIMEOUT 10
86 /*------------------------------------------------------------------------
88 . Configuration options, for the experienced user to change.
90 -------------------------------------------------------------------------*/
93 . Wait time for memory to be free. This probably shouldn't be
94 . tuned that much, as waiting for this means nothing else happens
97 #define MEMORY_WAIT_TIME 16
101 #define PRINTK3(args...) printf(args)
103 #define PRINTK3(args...)
107 #define PRINTK2(args...) printf(args)
109 #define PRINTK2(args...)
113 #define PRINTK(args...) printf(args)
115 #define PRINTK(args...)
119 /*------------------------------------------------------------------------
121 . The internal workings of the driver. If you are changing anything
122 . here with the SMC stuff, you should have the datasheet and know
123 . what you are doing.
125 -------------------------------------------------------------------------*/
127 /* Memory sizing constant */
128 #define LAN91C111_MEMORY_MULTIPLIER (1024*2)
130 #ifndef CONFIG_SMC91111_BASE
131 #error "SMC91111 Base address must be passed to initialization funciton"
132 /* #define CONFIG_SMC91111_BASE 0x20000300 */
135 #define SMC_DEV_NAME "SMC91111"
136 #define SMC_PHY_ADDR 0x0000
137 #define SMC_ALLOC_MAX_TRY 5
138 #define SMC_TX_TIMEOUT 30
140 #define SMC_PHY_CLOCK_DELAY 1000
144 #ifdef CONFIG_SMC_USE_32_BIT
150 #ifdef SHARED_RESOURCES
151 extern void swap_to(int device_id);
156 #ifndef CONFIG_SMC91111_EXT_PHY
157 static void smc_phy_configure(struct eth_device *dev);
158 #endif /* !CONFIG_SMC91111_EXT_PHY */
161 ------------------------------------------------------------
165 ------------------------------------------------------------
168 #ifdef CONFIG_SMC_USE_IOFUNCS
170 * input and output functions
172 * Implemented due to inx,outx macros accessing the device improperly
173 * and putting the device into an unkown state.
175 * For instance, on Sharp LPD7A400 SDK, affects were chip memory
176 * could not be free'd (hence the alloc failures), duplicate packets,
177 * packets being corrupt (shifted) on the wire, etc. Switching to the
178 * inx,outx functions fixed this problem.
181 #define barrier() __asm__ __volatile__("": : :"memory")
183 static inline word SMC_inw(struct eth_device *dev, dword offset)
186 v = *((volatile word*)(dev->iobase + offset));
187 barrier(); *(volatile u32*)(0xc0000000);
191 static inline void SMC_outw(struct eth_device *dev, word value, dword offset)
193 *((volatile word*)(dev->iobase + offset)) = value;
194 barrier(); *(volatile u32*)(0xc0000000);
197 static inline byte SMC_inb(struct eth_device *dev, dword offset)
201 _w = SMC_inw(dev, offset & ~((dword)1));
202 return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
205 static inline void SMC_outb(struct eth_device *dev, byte value, dword offset)
209 _w = SMC_inw(dev, offset & ~((dword)1));
211 *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
212 (value<<8) | (_w & 0x00ff);
214 *((volatile word*)(dev->iobase + offset)) =
215 value | (_w & 0xff00);
218 static inline void SMC_insw(struct eth_device *dev, dword offset,
219 volatile uchar* buf, dword len)
221 volatile word *p = (volatile word *)buf;
224 *p++ = SMC_inw(dev, offset);
226 *((volatile u32*)(0xc0000000));
230 static inline void SMC_outsw(struct eth_device *dev, dword offset,
231 uchar* buf, dword len)
233 volatile word *p = (volatile word *)buf;
236 SMC_outw(dev, *p++, offset);
238 *(volatile u32*)(0xc0000000);
241 #endif /* CONFIG_SMC_USE_IOFUNCS */
244 . A rather simple routine to print out a packet for debugging purposes.
247 static void print_packet( byte *, int );
250 #define tx_done(dev) 1
252 static int poll4int (struct eth_device *dev, byte mask, int timeout)
254 int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
256 word old_bank = SMC_inw (dev, BSR_REG);
258 PRINTK2 ("Polling...\n");
259 SMC_SELECT_BANK (dev, 2);
260 while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
261 if (get_timer (0) >= tmo) {
267 /* restore old bank selection */
268 SMC_SELECT_BANK (dev, old_bank);
276 /* Only one release command at a time, please */
277 static inline void smc_wait_mmu_release_complete (struct eth_device *dev)
281 /* assume bank 2 selected */
282 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
283 udelay (1); /* Wait until not busy */
290 . Function: smc_reset( void )
292 . This sets the SMC91111 chip to its normal state, hopefully from whatever
293 . mess that any other DOS driver has put it in.
295 . Maybe I should reset more registers to defaults in here? SOFTRST should
299 . 1. send a SOFT RESET
300 . 2. wait for it to finish
301 . 3. enable autorelease mode
302 . 4. reset the memory management unit
303 . 5. clear all interrupts
306 static void smc_reset (struct eth_device *dev)
308 PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
310 /* This resets the registers mostly to defaults, but doesn't
311 affect EEPROM. That seems unnecessary */
312 SMC_SELECT_BANK (dev, 0);
313 SMC_outw (dev, RCR_SOFTRST, RCR_REG);
315 /* Setup the Configuration Register */
316 /* This is necessary because the CONFIG_REG is not affected */
317 /* by a soft reset */
319 SMC_SELECT_BANK (dev, 1);
320 #if defined(CONFIG_SMC91111_EXT_PHY)
321 SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
323 SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
327 /* Release from possible power-down state */
328 /* Configuration register is not affected by Soft Reset */
329 SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
332 SMC_SELECT_BANK (dev, 0);
334 /* this should pause enough for the chip to be happy */
337 /* Disable transmit and receive functionality */
338 SMC_outw (dev, RCR_CLEAR, RCR_REG);
339 SMC_outw (dev, TCR_CLEAR, TCR_REG);
341 /* set the control register */
342 SMC_SELECT_BANK (dev, 1);
343 SMC_outw (dev, CTL_DEFAULT, CTL_REG);
346 SMC_SELECT_BANK (dev, 2);
347 smc_wait_mmu_release_complete (dev);
348 SMC_outw (dev, MC_RESET, MMU_CMD_REG);
349 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
350 udelay (1); /* Wait until not busy */
352 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
353 but this is a place where future chipsets _COULD_ break. Be wary
354 of issuing another MMU command right after this */
356 /* Disable all interrupts */
357 SMC_outb (dev, 0, IM_REG);
361 . Function: smc_enable
362 . Purpose: let the chip talk to the outside work
364 . 1. Enable the transmitter
365 . 2. Enable the receiver
366 . 3. Enable interrupts
368 static void smc_enable(struct eth_device *dev)
370 PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
371 SMC_SELECT_BANK( dev, 0 );
372 /* see the header file for options in TCR/RCR DEFAULT*/
373 SMC_outw( dev, TCR_DEFAULT, TCR_REG );
374 SMC_outw( dev, RCR_DEFAULT, RCR_REG );
377 /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
382 . Purpose: closes down the SMC91xxx chip.
384 . 1. zero the interrupt mask
385 . 2. clear the enable receive flag
386 . 3. clear the enable xmit flags
389 . (1) maybe utilize power down mode.
390 . Why not yet? Because while the chip will go into power down mode,
391 . the manual says that it will wake up in response to any I/O requests
392 . in the register space. Empirical results do not show this working.
394 static void smc_halt(struct eth_device *dev)
396 PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
398 /* no more interrupts for me */
399 SMC_SELECT_BANK( dev, 2 );
400 SMC_outb( dev, 0, IM_REG );
402 /* and tell the card to stay away from that nasty outside world */
403 SMC_SELECT_BANK( dev, 0 );
404 SMC_outb( dev, RCR_CLEAR, RCR_REG );
405 SMC_outb( dev, TCR_CLEAR, TCR_REG );
412 . Function: smc_send(struct net_device * )
414 . This sends the actual packet to the SMC9xxx chip.
417 . First, see if a saved_skb is available.
418 . ( this should NOT be called if there is no 'saved_skb'
419 . Now, find the packet number that the chip allocated
420 . Point the data pointers at it in memory
421 . Set the length word in the chip's memory
422 . Dump the packet to chip memory
423 . Check if a last byte is needed ( odd length packet )
424 . if so, set the control flag right
425 . Tell the card to send it
426 . Enable the transmit interrupt, so I know if it failed
427 . Free the kernel data if I actually sent it.
429 static int smc_send(struct eth_device *dev, volatile void *packet,
442 /* save PTR and PNR registers before manipulation */
443 SMC_SELECT_BANK (dev, 2);
444 saved_pnr = SMC_inb( dev, PN_REG );
445 saved_ptr = SMC_inw( dev, PTR_REG );
447 PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
449 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
452 ** The MMU wants the number of pages to be the number of 256 bytes
453 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
455 ** The 91C111 ignores the size bits, but the code is left intact
456 ** for backwards and future compatibility.
458 ** Pkt size for allocating is data length +6 (for additional status
459 ** words, length and ctl!)
461 ** If odd size then last byte is included in this header.
463 numPages = ((length & 0xfffe) + 6);
464 numPages >>= 8; /* Divide by 256 */
467 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
471 /* now, try to allocate the memory */
472 SMC_SELECT_BANK (dev, 2);
473 SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
475 /* FIXME: the ALLOC_INT bit never gets set *
476 * so the following will always give a *
477 * memory allocation error. *
478 * same code works in armboot though *
484 time_out = MEMORY_WAIT_TIME;
486 status = SMC_inb (dev, SMC91111_INT_REG);
487 if (status & IM_ALLOC_INT) {
488 /* acknowledge the interrupt */
489 SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
492 } while (--time_out);
495 PRINTK2 ("%s: memory allocation, try %d failed ...\n",
497 if (try < SMC_ALLOC_MAX_TRY)
503 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
506 buf = (byte *) packet;
508 /* If I get here, I _know_ there is a packet slot waiting for me */
509 packet_no = SMC_inb (dev, AR_REG);
510 if (packet_no & AR_FAILED) {
511 /* or isn't there? BAD CHIP! */
512 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
516 /* we have a packet address, so tell the card to use it */
517 #ifndef CONFIG_XAENIAX
518 SMC_outb (dev, packet_no, PN_REG);
520 /* On Xaeniax board, we can't use SMC_outb here because that way
521 * the Allocate MMU command will end up written to the command register
522 * as well, which will lead to a problem.
524 SMC_outl (dev, packet_no << 16, 0);
526 /* do not write new ptr value if Write data fifo not empty */
527 while ( saved_ptr & PTR_NOTEMPTY )
528 printf ("Write data fifo not empty!\n");
530 /* point to the beginning of the packet */
531 SMC_outw (dev, PTR_AUTOINC, PTR_REG);
533 PRINTK3 ("%s: Trying to xmit packet of length %x\n",
534 SMC_DEV_NAME, length);
537 printf ("Transmitting Packet\n");
538 print_packet (buf, length);
541 /* send the packet length ( +6 for status, length and ctl byte )
542 and the status word ( set to zeros ) */
544 SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
546 SMC_outw (dev, 0, SMC91111_DATA_REG);
547 /* send the packet length ( +6 for status words, length, and ctl */
548 SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
551 /* send the actual data
552 . I _think_ it's faster to send the longs first, and then
553 . mop up by sending the last word. It depends heavily
554 . on alignment, at least on the 486. Maybe it would be
555 . a good idea to check which is optimal? But that could take
556 . almost as much time as is saved?
559 SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
560 #ifndef CONFIG_XAENIAX
562 SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
565 /* On XANEIAX, we can only use 32-bit writes, so we need to handle
566 * unaligned tail part specially. The standard code doesn't work.
568 if ((length & 3) == 3) {
569 u16 * ptr = (u16*) &buf[length-3];
570 SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16),
572 } else if ((length & 2) == 2) {
573 u16 * ptr = (u16*) &buf[length-2];
574 SMC_outl(dev, *ptr, SMC91111_DATA_REG);
575 } else if (length & 1) {
576 SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG);
578 SMC_outl(dev, 0, SMC91111_DATA_REG);
582 SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
583 #endif /* USE_32_BIT */
585 #ifndef CONFIG_XAENIAX
586 /* Send the last byte, if there is one. */
587 if ((length & 1) == 0) {
588 SMC_outw (dev, 0, SMC91111_DATA_REG);
590 SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
594 /* and let the chipset deal with it */
595 SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
597 /* poll for TX INT */
598 /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
599 /* poll for TX_EMPTY INT - autorelease enabled */
600 if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
602 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
605 /* no need to release, MMU does that now */
606 #ifdef CONFIG_XAENIAX
607 SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
610 /* wait for MMU getting ready (low) */
611 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
615 PRINTK2 ("MMU ready\n");
621 SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
622 /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
623 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
627 /* no need to release, MMU does that now */
628 #ifdef CONFIG_XAENIAX
629 SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
632 /* wait for MMU getting ready (low) */
633 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
637 PRINTK2 ("MMU ready\n");
642 /* restore previously saved registers */
643 #ifndef CONFIG_XAENIAX
644 SMC_outb( dev, saved_pnr, PN_REG );
646 /* On Xaeniax board, we can't use SMC_outb here because that way
647 * the Allocate MMU command will end up written to the command register
648 * as well, which will lead to a problem.
650 SMC_outl(dev, saved_pnr << 16, 0);
652 SMC_outw( dev, saved_ptr, PTR_REG );
657 static int smc_write_hwaddr(struct eth_device *dev)
662 SMC_SELECT_BANK (dev, 1);
664 for (i = 0; i < 6; i += 2) {
667 address = dev->enetaddr[i + 1] << 8;
668 address |= dev->enetaddr[i];
669 SMC_outw(dev, address, (ADDR0_REG + i));
672 for (i = 0; i < 6; i++)
673 SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
680 * Open and Initialize the board
682 * Set up everything, reset the card, etc ..
685 static int smc_init(struct eth_device *dev, bd_t *bd)
689 PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
691 /* reset the hardware */
695 /* Configure the PHY */
696 #ifndef CONFIG_SMC91111_EXT_PHY
697 smc_phy_configure (dev);
700 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
701 /* SMC_SELECT_BANK(dev, 0); */
702 /* SMC_outw(dev, 0, RPC_REG); */
704 printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
709 /*-------------------------------------------------------------
711 . smc_rcv - receive a packet from the card
713 . There is ( at least ) a packet waiting to be read from
717 . o If an error, record it
718 . o otherwise, read in the packet
719 --------------------------------------------------------------
721 static int smc_rcv(struct eth_device *dev)
733 SMC_SELECT_BANK(dev, 2);
734 /* save PTR and PTR registers */
735 saved_pnr = SMC_inb( dev, PN_REG );
736 saved_ptr = SMC_inw( dev, PTR_REG );
738 packet_number = SMC_inw( dev, RXFIFO_REG );
740 if ( packet_number & RXFIFO_REMPTY ) {
745 PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
746 /* start reading from the start of the packet */
747 SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
749 /* First two words are status and packet_length */
751 stat_len = SMC_inl(dev, SMC91111_DATA_REG);
752 status = stat_len & 0xffff;
753 packet_length = stat_len >> 16;
755 status = SMC_inw( dev, SMC91111_DATA_REG );
756 packet_length = SMC_inw( dev, SMC91111_DATA_REG );
759 packet_length &= 0x07ff; /* mask off top bits */
761 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
763 if ( !(status & RS_ERRORS ) ){
764 /* Adjust for having already read the first two words */
765 packet_length -= 4; /*4; */
768 /* set odd length for bug in LAN91C111, */
769 /* which never sets RS_ODDFRAME */
774 PRINTK3(" Reading %d dwords (and %d bytes) \n",
775 packet_length >> 2, packet_length & 3 );
776 /* QUESTION: Like in the TX routine, do I want
777 to send the DWORDs or the bytes first, or some
778 mixture. A mixture might improve already slow PIO
780 SMC_insl( dev, SMC91111_DATA_REG, NetRxPackets[0],
781 packet_length >> 2 );
782 /* read the left over bytes */
783 if (packet_length & 3) {
786 byte *tail = (byte *)(NetRxPackets[0] +
787 (packet_length & ~3));
788 dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
789 for (i=0; i<(packet_length & 3); i++)
790 *tail++ = (byte) (leftover >> (8*i)) & 0xff;
793 PRINTK3(" Reading %d words and %d byte(s) \n",
794 (packet_length >> 1 ), packet_length & 1 );
795 SMC_insw(dev, SMC91111_DATA_REG , NetRxPackets[0],
798 #endif /* USE_32_BIT */
801 printf("Receiving Packet\n");
802 print_packet( NetRxPackets[0], packet_length );
810 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
811 udelay(1); /* Wait until not busy */
813 /* error or good, tell the card to get rid of this packet */
814 SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
816 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
817 udelay(1); /* Wait until not busy */
819 /* restore saved registers */
820 #ifndef CONFIG_XAENIAX
821 SMC_outb( dev, saved_pnr, PN_REG );
823 /* On Xaeniax board, we can't use SMC_outb here because that way
824 * the Allocate MMU command will end up written to the command register
825 * as well, which will lead to a problem.
827 SMC_outl( dev, saved_pnr << 16, 0);
829 SMC_outw( dev, saved_ptr, PTR_REG );
832 /* Pass the packet up to the protocol layers. */
833 NetReceive(NetRxPackets[0], packet_length);
834 return packet_length;
843 /*------------------------------------------------------------
844 . Modify a bit in the LAN91C111 register set
845 .-------------------------------------------------------------*/
846 static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
847 unsigned int bit, int val)
851 SMC_SELECT_BANK( dev, bank );
853 regval = SMC_inw( dev, reg );
859 SMC_outw( dev, regval, 0 );
864 /*------------------------------------------------------------
865 . Retrieve a bit in the LAN91C111 register set
866 .-------------------------------------------------------------*/
867 static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit)
869 SMC_SELECT_BANK( dev, bank );
870 if ( SMC_inw( dev, reg ) & bit)
877 /*------------------------------------------------------------
878 . Modify a LAN91C111 register (word access only)
879 .-------------------------------------------------------------*/
880 static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val)
882 SMC_SELECT_BANK( dev, bank );
883 SMC_outw( dev, val, reg );
887 /*------------------------------------------------------------
888 . Retrieve a LAN91C111 register (word access only)
889 .-------------------------------------------------------------*/
890 static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg)
892 SMC_SELECT_BANK( dev, bank );
893 return(SMC_inw( dev, reg ));
898 /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
902 /*------------------------------------------------------------
903 . Debugging function for viewing MII Management serial bitstream
904 .-------------------------------------------------------------*/
905 static void smc_dump_mii_stream (byte * bits, int size)
910 for (i = 0; i < size; ++i) {
911 printf ("%d", i % 10);
915 for (i = 0; i < size; ++i) {
916 if (bits[i] & MII_MDOE)
923 for (i = 0; i < size; ++i) {
924 if (bits[i] & MII_MDO)
931 for (i = 0; i < size; ++i) {
932 if (bits[i] & MII_MDI)
942 /*------------------------------------------------------------
943 . Reads a register from the MII Management serial interface
944 .-------------------------------------------------------------*/
945 #ifndef CONFIG_SMC91111_EXT_PHY
946 static word smc_read_phy_register (struct eth_device *dev, byte phyreg)
956 byte phyaddr = SMC_PHY_ADDR;
958 /* 32 consecutive ones on MDO to establish sync */
959 for (i = 0; i < 32; ++i)
960 bits[clk_idx++] = MII_MDOE | MII_MDO;
962 /* Start code <01> */
963 bits[clk_idx++] = MII_MDOE;
964 bits[clk_idx++] = MII_MDOE | MII_MDO;
966 /* Read command <10> */
967 bits[clk_idx++] = MII_MDOE | MII_MDO;
968 bits[clk_idx++] = MII_MDOE;
970 /* Output the PHY address, msb first */
972 for (i = 0; i < 5; ++i) {
974 bits[clk_idx++] = MII_MDOE | MII_MDO;
976 bits[clk_idx++] = MII_MDOE;
978 /* Shift to next lowest bit */
982 /* Output the phy register number, msb first */
984 for (i = 0; i < 5; ++i) {
986 bits[clk_idx++] = MII_MDOE | MII_MDO;
988 bits[clk_idx++] = MII_MDOE;
990 /* Shift to next lowest bit */
994 /* Tristate and turnaround (2 bit times) */
996 /*bits[clk_idx++] = 0; */
998 /* Input starts at this bit time */
1001 /* Will input 16 bits */
1002 for (i = 0; i < 16; ++i)
1003 bits[clk_idx++] = 0;
1005 /* Final clock bit */
1006 bits[clk_idx++] = 0;
1008 /* Save the current bank */
1009 oldBank = SMC_inw (dev, BANK_SELECT);
1012 SMC_SELECT_BANK (dev, 3);
1014 /* Get the current MII register value */
1015 mii_reg = SMC_inw (dev, MII_REG);
1017 /* Turn off all MII Interface bits */
1018 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
1020 /* Clock all 64 cycles */
1021 for (i = 0; i < sizeof bits; ++i) {
1022 /* Clock Low - output data */
1023 SMC_outw (dev, mii_reg | bits[i], MII_REG);
1024 udelay (SMC_PHY_CLOCK_DELAY);
1027 /* Clock Hi - input data */
1028 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
1029 udelay (SMC_PHY_CLOCK_DELAY);
1030 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
1033 /* Return to idle state */
1034 /* Set clock to low, data to low, and output tristated */
1035 SMC_outw (dev, mii_reg, MII_REG);
1036 udelay (SMC_PHY_CLOCK_DELAY);
1038 /* Restore original bank select */
1039 SMC_SELECT_BANK (dev, oldBank);
1041 /* Recover input data */
1043 for (i = 0; i < 16; ++i) {
1046 if (bits[input_idx++] & MII_MDI)
1050 #if (SMC_DEBUG > 2 )
1051 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1052 phyaddr, phyreg, phydata);
1053 smc_dump_mii_stream (bits, sizeof bits);
1060 /*------------------------------------------------------------
1061 . Writes a register to the MII Management serial interface
1062 .-------------------------------------------------------------*/
1063 static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
1072 byte phyaddr = SMC_PHY_ADDR;
1074 /* 32 consecutive ones on MDO to establish sync */
1075 for (i = 0; i < 32; ++i)
1076 bits[clk_idx++] = MII_MDOE | MII_MDO;
1078 /* Start code <01> */
1079 bits[clk_idx++] = MII_MDOE;
1080 bits[clk_idx++] = MII_MDOE | MII_MDO;
1082 /* Write command <01> */
1083 bits[clk_idx++] = MII_MDOE;
1084 bits[clk_idx++] = MII_MDOE | MII_MDO;
1086 /* Output the PHY address, msb first */
1088 for (i = 0; i < 5; ++i) {
1090 bits[clk_idx++] = MII_MDOE | MII_MDO;
1092 bits[clk_idx++] = MII_MDOE;
1094 /* Shift to next lowest bit */
1098 /* Output the phy register number, msb first */
1100 for (i = 0; i < 5; ++i) {
1102 bits[clk_idx++] = MII_MDOE | MII_MDO;
1104 bits[clk_idx++] = MII_MDOE;
1106 /* Shift to next lowest bit */
1110 /* Tristate and turnaround (2 bit times) */
1111 bits[clk_idx++] = 0;
1112 bits[clk_idx++] = 0;
1114 /* Write out 16 bits of data, msb first */
1116 for (i = 0; i < 16; ++i) {
1118 bits[clk_idx++] = MII_MDOE | MII_MDO;
1120 bits[clk_idx++] = MII_MDOE;
1122 /* Shift to next lowest bit */
1126 /* Final clock bit (tristate) */
1127 bits[clk_idx++] = 0;
1129 /* Save the current bank */
1130 oldBank = SMC_inw (dev, BANK_SELECT);
1133 SMC_SELECT_BANK (dev, 3);
1135 /* Get the current MII register value */
1136 mii_reg = SMC_inw (dev, MII_REG);
1138 /* Turn off all MII Interface bits */
1139 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
1141 /* Clock all cycles */
1142 for (i = 0; i < sizeof bits; ++i) {
1143 /* Clock Low - output data */
1144 SMC_outw (dev, mii_reg | bits[i], MII_REG);
1145 udelay (SMC_PHY_CLOCK_DELAY);
1148 /* Clock Hi - input data */
1149 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
1150 udelay (SMC_PHY_CLOCK_DELAY);
1151 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
1154 /* Return to idle state */
1155 /* Set clock to low, data to low, and output tristated */
1156 SMC_outw (dev, mii_reg, MII_REG);
1157 udelay (SMC_PHY_CLOCK_DELAY);
1159 /* Restore original bank select */
1160 SMC_SELECT_BANK (dev, oldBank);
1162 #if (SMC_DEBUG > 2 )
1163 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1164 phyaddr, phyreg, phydata);
1165 smc_dump_mii_stream (bits, sizeof bits);
1168 #endif /* !CONFIG_SMC91111_EXT_PHY */
1171 /*------------------------------------------------------------
1172 . Waits the specified number of milliseconds - kernel friendly
1173 .-------------------------------------------------------------*/
1174 #ifndef CONFIG_SMC91111_EXT_PHY
1175 static void smc_wait_ms(unsigned int ms)
1179 #endif /* !CONFIG_SMC91111_EXT_PHY */
1182 /*------------------------------------------------------------
1183 . Configures the specified PHY using Autonegotiation. Calls
1184 . smc_phy_fixed() if the user has requested a certain config.
1185 .-------------------------------------------------------------*/
1186 #ifndef CONFIG_SMC91111_EXT_PHY
1187 static void smc_phy_configure (struct eth_device *dev)
1191 word my_phy_caps; /* My PHY capabilities */
1192 word my_ad_caps; /* My Advertised capabilities */
1193 word status = 0; /*;my status = 0 */
1196 PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
1199 /* Get the detected phy address */
1200 phyaddr = SMC_PHY_ADDR;
1202 /* Reset the PHY, setting all other bits to zero */
1203 smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
1205 /* Wait for the reset to complete, or time out */
1206 timeout = 6; /* Wait up to 3 seconds */
1208 if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
1210 /* reset complete */
1214 smc_wait_ms (500); /* wait 500 millisecs */
1218 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
1219 goto smc_phy_configure_exit;
1222 /* Read PHY Register 18, Status Output */
1223 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1225 /* Enable PHY Interrupts (for register 18) */
1226 /* Interrupts listed here are disabled */
1227 smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
1229 /* Configure the Receive/Phy Control register */
1230 SMC_SELECT_BANK (dev, 0);
1231 SMC_outw (dev, RPC_DEFAULT, RPC_REG);
1233 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
1234 my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
1235 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
1237 if (my_phy_caps & PHY_STAT_CAP_T4)
1238 my_ad_caps |= PHY_AD_T4;
1240 if (my_phy_caps & PHY_STAT_CAP_TXF)
1241 my_ad_caps |= PHY_AD_TX_FDX;
1243 if (my_phy_caps & PHY_STAT_CAP_TXH)
1244 my_ad_caps |= PHY_AD_TX_HDX;
1246 if (my_phy_caps & PHY_STAT_CAP_TF)
1247 my_ad_caps |= PHY_AD_10_FDX;
1249 if (my_phy_caps & PHY_STAT_CAP_TH)
1250 my_ad_caps |= PHY_AD_10_HDX;
1252 /* Update our Auto-Neg Advertisement Register */
1253 smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
1255 /* Read the register back. Without this, it appears that when */
1256 /* auto-negotiation is restarted, sometimes it isn't ready and */
1257 /* the link does not come up. */
1258 smc_read_phy_register(dev, PHY_AD_REG);
1260 PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1261 PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
1263 /* Restart auto-negotiation process in order to advertise my caps */
1264 smc_write_phy_register (dev, PHY_CNTL_REG,
1265 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
1267 /* Wait for the auto-negotiation to complete. This may take from */
1268 /* 2 to 3 seconds. */
1269 /* Wait for the reset to complete, or time out */
1270 timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
1273 status = smc_read_phy_register (dev, PHY_STAT_REG);
1274 if (status & PHY_STAT_ANEG_ACK) {
1275 /* auto-negotiate complete */
1279 smc_wait_ms (500); /* wait 500 millisecs */
1281 /* Restart auto-negotiation if remote fault */
1282 if (status & PHY_STAT_REM_FLT) {
1283 printf ("%s: PHY remote fault detected\n",
1286 /* Restart auto-negotiation */
1287 printf ("%s: PHY restarting auto-negotiation\n",
1289 smc_write_phy_register (dev, PHY_CNTL_REG,
1298 printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
1302 /* Fail if we detected an auto-negotiate remote fault */
1303 if (status & PHY_STAT_REM_FLT) {
1304 printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
1308 /* Re-Configure the Receive/Phy Control register */
1309 SMC_outw (dev, RPC_DEFAULT, RPC_REG);
1311 smc_phy_configure_exit: ;
1314 #endif /* !CONFIG_SMC91111_EXT_PHY */
1318 static void print_packet( byte * buf, int length )
1324 printf("Packet of length %d \n", length );
1327 lines = length / 16;
1328 remainder = length % 16;
1330 for ( i = 0; i < lines ; i ++ ) {
1333 for ( cur = 0; cur < 8; cur ++ ) {
1338 printf("%02x%02x ", a, b );
1342 for ( i = 0; i < remainder/2 ; i++ ) {
1347 printf("%02x%02x ", a, b );
1354 int smc91111_initialize(u8 dev_num, int base_addr)
1356 struct smc91111_priv *priv;
1357 struct eth_device *dev;
1360 priv = malloc(sizeof(*priv));
1363 dev = malloc(sizeof(*dev));
1369 memset(dev, 0, sizeof(*dev));
1370 priv->dev_num = dev_num;
1372 dev->iobase = base_addr;
1375 SMC_SELECT_BANK(dev, 1);
1376 for (i = 0; i < 6; ++i)
1377 dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
1380 dev->init = smc_init;
1381 dev->halt = smc_halt;
1382 dev->send = smc_send;
1383 dev->recv = smc_rcv;
1384 dev->write_hwaddr = smc_write_hwaddr;
1385 sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);