1 /*------------------------------------------------------------------------
3 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 . Rolf Offermanns <rof@sysgo.de>
9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
10 . Developed by Simple Network Magic Corporation (SNMC)
11 . Copyright (C) 1996 by Erik Stahlman (ES)
13 . This program is free software; you can redistribute it and/or modify
14 . it under the terms of the GNU General Public License as published by
15 . the Free Software Foundation; either version 2 of the License, or
16 . (at your option) any later version.
18 . This program is distributed in the hope that it will be useful,
19 . but WITHOUT ANY WARRANTY; without even the implied warranty of
20 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 . GNU General Public License for more details.
23 . You should have received a copy of the GNU General Public License
24 . along with this program; if not, write to the Free Software
25 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 . Information contained in this file was obtained from the LAN91C111
28 . manual from SMC. To get a copy, if you really want one, you can find
29 . information under www.smsc.com.
32 . "Features" of the SMC chip:
33 . Integrated PHY/MAC for 10/100BaseT Operation
34 . Supports internal and external MII
35 . Integrated 8K packet memory
36 . EEPROM interface for configuration
39 . io = for the base address
43 . Erik Stahlman ( erik@vt.edu )
44 . Daris A Nevil ( dnevil@snmc.com )
47 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
50 . o SMSC LAN91C111 databook (www.smsc.com)
51 . o smc9194.c by Erik Stahlman
52 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
55 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
56 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
57 . 07/25/01 Woojung Huh Modify for ADS Bitsy
58 . 04/25/01 Daris A Nevil Initial public release through SMSC
59 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
60 ----------------------------------------------------------------------------*/
69 /* Use power-down feature of the chip */
77 static const char version[] =
78 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
81 /* Autonegotiation timeout in seconds */
82 #ifndef CONFIG_SMC_AUTONEG_TIMEOUT
83 #define CONFIG_SMC_AUTONEG_TIMEOUT 10
86 /*------------------------------------------------------------------------
88 . Configuration options, for the experienced user to change.
90 -------------------------------------------------------------------------*/
93 . Wait time for memory to be free. This probably shouldn't be
94 . tuned that much, as waiting for this means nothing else happens
97 #define MEMORY_WAIT_TIME 16
101 #define PRINTK3(args...) printf(args)
103 #define PRINTK3(args...)
107 #define PRINTK2(args...) printf(args)
109 #define PRINTK2(args...)
113 #define PRINTK(args...) printf(args)
115 #define PRINTK(args...)
119 /*------------------------------------------------------------------------
121 . The internal workings of the driver. If you are changing anything
122 . here with the SMC stuff, you should have the datasheet and know
123 . what you are doing.
125 -------------------------------------------------------------------------*/
127 /* Memory sizing constant */
128 #define LAN91C111_MEMORY_MULTIPLIER (1024*2)
130 #ifndef CONFIG_SMC91111_BASE
131 #error "SMC91111 Base address must be passed to initialization funciton"
132 /* #define CONFIG_SMC91111_BASE 0x20000300 */
135 #define SMC_DEV_NAME "SMC91111"
136 #define SMC_PHY_ADDR 0x0000
137 #define SMC_ALLOC_MAX_TRY 5
138 #define SMC_TX_TIMEOUT 30
140 #define SMC_PHY_CLOCK_DELAY 1000
144 #ifdef CONFIG_SMC_USE_32_BIT
150 #ifdef SHARED_RESOURCES
151 extern void swap_to(int device_id);
156 #ifndef CONFIG_SMC91111_EXT_PHY
157 static void smc_phy_configure(struct eth_device *dev);
158 #endif /* !CONFIG_SMC91111_EXT_PHY */
161 ------------------------------------------------------------
165 ------------------------------------------------------------
168 #ifdef CONFIG_SMC_USE_IOFUNCS
170 * input and output functions
172 * Implemented due to inx,outx macros accessing the device improperly
173 * and putting the device into an unkown state.
175 * For instance, on Sharp LPD7A400 SDK, affects were chip memory
176 * could not be free'd (hence the alloc failures), duplicate packets,
177 * packets being corrupt (shifted) on the wire, etc. Switching to the
178 * inx,outx functions fixed this problem.
181 #define barrier() __asm__ __volatile__("": : :"memory")
183 static inline word SMC_inw(struct eth_device *dev, dword offset)
186 v = *((volatile word*)(dev->iobase + offset));
187 barrier(); *(volatile u32*)(0xc0000000);
191 static inline void SMC_outw(struct eth_device *dev, word value, dword offset)
193 *((volatile word*)(dev->iobase + offset)) = value;
194 barrier(); *(volatile u32*)(0xc0000000);
197 static inline byte SMC_inb(struct eth_device *dev, dword offset)
201 _w = SMC_inw(dev, offset & ~((dword)1));
202 return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
205 static inline void SMC_outb(struct eth_device *dev, byte value, dword offset)
209 _w = SMC_inw(dev, offset & ~((dword)1));
211 *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
212 (value<<8) | (_w & 0x00ff);
214 *((volatile word*)(dev->iobase + offset)) =
215 value | (_w & 0xff00);
218 static inline void SMC_insw(struct eth_device *dev, dword offset,
219 volatile uchar* buf, dword len)
221 volatile word *p = (volatile word *)buf;
224 *p++ = SMC_inw(dev, offset);
226 *((volatile u32*)(0xc0000000));
230 static inline void SMC_outsw(struct eth_device *dev, dword offset,
231 uchar* buf, dword len)
233 volatile word *p = (volatile word *)buf;
236 SMC_outw(dev, *p++, offset);
238 *(volatile u32*)(0xc0000000);
241 #endif /* CONFIG_SMC_USE_IOFUNCS */
244 . A rather simple routine to print out a packet for debugging purposes.
247 static void print_packet( byte *, int );
250 #define tx_done(dev) 1
252 static int poll4int (struct eth_device *dev, byte mask, int timeout)
254 int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
256 word old_bank = SMC_inw (dev, BSR_REG);
258 PRINTK2 ("Polling...\n");
259 SMC_SELECT_BANK (dev, 2);
260 while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
261 if (get_timer (0) >= tmo) {
267 /* restore old bank selection */
268 SMC_SELECT_BANK (dev, old_bank);
276 /* Only one release command at a time, please */
277 static inline void smc_wait_mmu_release_complete (struct eth_device *dev)
281 /* assume bank 2 selected */
282 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
283 udelay (1); /* Wait until not busy */
290 . Function: smc_reset( void )
292 . This sets the SMC91111 chip to its normal state, hopefully from whatever
293 . mess that any other DOS driver has put it in.
295 . Maybe I should reset more registers to defaults in here? SOFTRST should
299 . 1. send a SOFT RESET
300 . 2. wait for it to finish
301 . 3. enable autorelease mode
302 . 4. reset the memory management unit
303 . 5. clear all interrupts
306 static void smc_reset (struct eth_device *dev)
308 PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
310 /* This resets the registers mostly to defaults, but doesn't
311 affect EEPROM. That seems unnecessary */
312 SMC_SELECT_BANK (dev, 0);
313 SMC_outw (dev, RCR_SOFTRST, RCR_REG);
315 /* Setup the Configuration Register */
316 /* This is necessary because the CONFIG_REG is not affected */
317 /* by a soft reset */
319 SMC_SELECT_BANK (dev, 1);
320 #if defined(CONFIG_SMC91111_EXT_PHY)
321 SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
323 SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
327 /* Release from possible power-down state */
328 /* Configuration register is not affected by Soft Reset */
329 SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
332 SMC_SELECT_BANK (dev, 0);
334 /* this should pause enough for the chip to be happy */
337 /* Disable transmit and receive functionality */
338 SMC_outw (dev, RCR_CLEAR, RCR_REG);
339 SMC_outw (dev, TCR_CLEAR, TCR_REG);
341 /* set the control register */
342 SMC_SELECT_BANK (dev, 1);
343 SMC_outw (dev, CTL_DEFAULT, CTL_REG);
346 SMC_SELECT_BANK (dev, 2);
347 smc_wait_mmu_release_complete (dev);
348 SMC_outw (dev, MC_RESET, MMU_CMD_REG);
349 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
350 udelay (1); /* Wait until not busy */
352 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
353 but this is a place where future chipsets _COULD_ break. Be wary
354 of issuing another MMU command right after this */
356 /* Disable all interrupts */
357 SMC_outb (dev, 0, IM_REG);
361 . Function: smc_enable
362 . Purpose: let the chip talk to the outside work
364 . 1. Enable the transmitter
365 . 2. Enable the receiver
366 . 3. Enable interrupts
368 static void smc_enable(struct eth_device *dev)
370 PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
371 SMC_SELECT_BANK( dev, 0 );
372 /* see the header file for options in TCR/RCR DEFAULT*/
373 SMC_outw( dev, TCR_DEFAULT, TCR_REG );
374 SMC_outw( dev, RCR_DEFAULT, RCR_REG );
377 /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
382 . Purpose: closes down the SMC91xxx chip.
384 . 1. zero the interrupt mask
385 . 2. clear the enable receive flag
386 . 3. clear the enable xmit flags
389 . (1) maybe utilize power down mode.
390 . Why not yet? Because while the chip will go into power down mode,
391 . the manual says that it will wake up in response to any I/O requests
392 . in the register space. Empirical results do not show this working.
394 static void smc_halt(struct eth_device *dev)
396 PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
398 /* no more interrupts for me */
399 SMC_SELECT_BANK( dev, 2 );
400 SMC_outb( dev, 0, IM_REG );
402 /* and tell the card to stay away from that nasty outside world */
403 SMC_SELECT_BANK( dev, 0 );
404 SMC_outb( dev, RCR_CLEAR, RCR_REG );
405 SMC_outb( dev, TCR_CLEAR, TCR_REG );
412 . Function: smc_send(struct net_device * )
414 . This sends the actual packet to the SMC9xxx chip.
417 . First, see if a saved_skb is available.
418 . ( this should NOT be called if there is no 'saved_skb'
419 . Now, find the packet number that the chip allocated
420 . Point the data pointers at it in memory
421 . Set the length word in the chip's memory
422 . Dump the packet to chip memory
423 . Check if a last byte is needed ( odd length packet )
424 . if so, set the control flag right
425 . Tell the card to send it
426 . Enable the transmit interrupt, so I know if it failed
427 . Free the kernel data if I actually sent it.
429 static int smc_send(struct eth_device *dev, void *packet, int packet_length)
441 /* save PTR and PNR registers before manipulation */
442 SMC_SELECT_BANK (dev, 2);
443 saved_pnr = SMC_inb( dev, PN_REG );
444 saved_ptr = SMC_inw( dev, PTR_REG );
446 PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
448 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
451 ** The MMU wants the number of pages to be the number of 256 bytes
452 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
454 ** The 91C111 ignores the size bits, but the code is left intact
455 ** for backwards and future compatibility.
457 ** Pkt size for allocating is data length +6 (for additional status
458 ** words, length and ctl!)
460 ** If odd size then last byte is included in this header.
462 numPages = ((length & 0xfffe) + 6);
463 numPages >>= 8; /* Divide by 256 */
466 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
470 /* now, try to allocate the memory */
471 SMC_SELECT_BANK (dev, 2);
472 SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
474 /* FIXME: the ALLOC_INT bit never gets set *
475 * so the following will always give a *
476 * memory allocation error. *
477 * same code works in armboot though *
483 time_out = MEMORY_WAIT_TIME;
485 status = SMC_inb (dev, SMC91111_INT_REG);
486 if (status & IM_ALLOC_INT) {
487 /* acknowledge the interrupt */
488 SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
491 } while (--time_out);
494 PRINTK2 ("%s: memory allocation, try %d failed ...\n",
496 if (try < SMC_ALLOC_MAX_TRY)
502 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
505 buf = (byte *) packet;
507 /* If I get here, I _know_ there is a packet slot waiting for me */
508 packet_no = SMC_inb (dev, AR_REG);
509 if (packet_no & AR_FAILED) {
510 /* or isn't there? BAD CHIP! */
511 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
515 /* we have a packet address, so tell the card to use it */
516 #ifndef CONFIG_XAENIAX
517 SMC_outb (dev, packet_no, PN_REG);
519 /* On Xaeniax board, we can't use SMC_outb here because that way
520 * the Allocate MMU command will end up written to the command register
521 * as well, which will lead to a problem.
523 SMC_outl (dev, packet_no << 16, 0);
525 /* do not write new ptr value if Write data fifo not empty */
526 while ( saved_ptr & PTR_NOTEMPTY )
527 printf ("Write data fifo not empty!\n");
529 /* point to the beginning of the packet */
530 SMC_outw (dev, PTR_AUTOINC, PTR_REG);
532 PRINTK3 ("%s: Trying to xmit packet of length %x\n",
533 SMC_DEV_NAME, length);
536 printf ("Transmitting Packet\n");
537 print_packet (buf, length);
540 /* send the packet length ( +6 for status, length and ctl byte )
541 and the status word ( set to zeros ) */
543 SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
545 SMC_outw (dev, 0, SMC91111_DATA_REG);
546 /* send the packet length ( +6 for status words, length, and ctl */
547 SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
550 /* send the actual data
551 . I _think_ it's faster to send the longs first, and then
552 . mop up by sending the last word. It depends heavily
553 . on alignment, at least on the 486. Maybe it would be
554 . a good idea to check which is optimal? But that could take
555 . almost as much time as is saved?
558 SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
559 #ifndef CONFIG_XAENIAX
561 SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
564 /* On XANEIAX, we can only use 32-bit writes, so we need to handle
565 * unaligned tail part specially. The standard code doesn't work.
567 if ((length & 3) == 3) {
568 u16 * ptr = (u16*) &buf[length-3];
569 SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16),
571 } else if ((length & 2) == 2) {
572 u16 * ptr = (u16*) &buf[length-2];
573 SMC_outl(dev, *ptr, SMC91111_DATA_REG);
574 } else if (length & 1) {
575 SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG);
577 SMC_outl(dev, 0, SMC91111_DATA_REG);
581 SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
582 #endif /* USE_32_BIT */
584 #ifndef CONFIG_XAENIAX
585 /* Send the last byte, if there is one. */
586 if ((length & 1) == 0) {
587 SMC_outw (dev, 0, SMC91111_DATA_REG);
589 SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
593 /* and let the chipset deal with it */
594 SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
596 /* poll for TX INT */
597 /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
598 /* poll for TX_EMPTY INT - autorelease enabled */
599 if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
601 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
604 /* no need to release, MMU does that now */
605 #ifdef CONFIG_XAENIAX
606 SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
609 /* wait for MMU getting ready (low) */
610 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
614 PRINTK2 ("MMU ready\n");
620 SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
621 /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
622 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
626 /* no need to release, MMU does that now */
627 #ifdef CONFIG_XAENIAX
628 SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
631 /* wait for MMU getting ready (low) */
632 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
636 PRINTK2 ("MMU ready\n");
641 /* restore previously saved registers */
642 #ifndef CONFIG_XAENIAX
643 SMC_outb( dev, saved_pnr, PN_REG );
645 /* On Xaeniax board, we can't use SMC_outb here because that way
646 * the Allocate MMU command will end up written to the command register
647 * as well, which will lead to a problem.
649 SMC_outl(dev, saved_pnr << 16, 0);
651 SMC_outw( dev, saved_ptr, PTR_REG );
656 static int smc_write_hwaddr(struct eth_device *dev)
661 SMC_SELECT_BANK (dev, 1);
663 for (i = 0; i < 6; i += 2) {
666 address = dev->enetaddr[i + 1] << 8;
667 address |= dev->enetaddr[i];
668 SMC_outw(dev, address, (ADDR0_REG + i));
671 for (i = 0; i < 6; i++)
672 SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
679 * Open and Initialize the board
681 * Set up everything, reset the card, etc ..
684 static int smc_init(struct eth_device *dev, bd_t *bd)
688 PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
690 /* reset the hardware */
694 /* Configure the PHY */
695 #ifndef CONFIG_SMC91111_EXT_PHY
696 smc_phy_configure (dev);
699 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
700 /* SMC_SELECT_BANK(dev, 0); */
701 /* SMC_outw(dev, 0, RPC_REG); */
703 printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
708 /*-------------------------------------------------------------
710 . smc_rcv - receive a packet from the card
712 . There is ( at least ) a packet waiting to be read from
716 . o If an error, record it
717 . o otherwise, read in the packet
718 --------------------------------------------------------------
720 static int smc_rcv(struct eth_device *dev)
732 SMC_SELECT_BANK(dev, 2);
733 /* save PTR and PTR registers */
734 saved_pnr = SMC_inb( dev, PN_REG );
735 saved_ptr = SMC_inw( dev, PTR_REG );
737 packet_number = SMC_inw( dev, RXFIFO_REG );
739 if ( packet_number & RXFIFO_REMPTY ) {
744 PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
745 /* start reading from the start of the packet */
746 SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
748 /* First two words are status and packet_length */
750 stat_len = SMC_inl(dev, SMC91111_DATA_REG);
751 status = stat_len & 0xffff;
752 packet_length = stat_len >> 16;
754 status = SMC_inw( dev, SMC91111_DATA_REG );
755 packet_length = SMC_inw( dev, SMC91111_DATA_REG );
758 packet_length &= 0x07ff; /* mask off top bits */
760 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
762 if ( !(status & RS_ERRORS ) ){
763 /* Adjust for having already read the first two words */
764 packet_length -= 4; /*4; */
767 /* set odd length for bug in LAN91C111, */
768 /* which never sets RS_ODDFRAME */
773 PRINTK3(" Reading %d dwords (and %d bytes) \n",
774 packet_length >> 2, packet_length & 3 );
775 /* QUESTION: Like in the TX routine, do I want
776 to send the DWORDs or the bytes first, or some
777 mixture. A mixture might improve already slow PIO
779 SMC_insl( dev, SMC91111_DATA_REG, NetRxPackets[0],
780 packet_length >> 2 );
781 /* read the left over bytes */
782 if (packet_length & 3) {
785 byte *tail = (byte *)(NetRxPackets[0] +
786 (packet_length & ~3));
787 dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
788 for (i=0; i<(packet_length & 3); i++)
789 *tail++ = (byte) (leftover >> (8*i)) & 0xff;
792 PRINTK3(" Reading %d words and %d byte(s) \n",
793 (packet_length >> 1 ), packet_length & 1 );
794 SMC_insw(dev, SMC91111_DATA_REG , NetRxPackets[0],
797 #endif /* USE_32_BIT */
800 printf("Receiving Packet\n");
801 print_packet( NetRxPackets[0], packet_length );
809 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
810 udelay(1); /* Wait until not busy */
812 /* error or good, tell the card to get rid of this packet */
813 SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
815 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
816 udelay(1); /* Wait until not busy */
818 /* restore saved registers */
819 #ifndef CONFIG_XAENIAX
820 SMC_outb( dev, saved_pnr, PN_REG );
822 /* On Xaeniax board, we can't use SMC_outb here because that way
823 * the Allocate MMU command will end up written to the command register
824 * as well, which will lead to a problem.
826 SMC_outl( dev, saved_pnr << 16, 0);
828 SMC_outw( dev, saved_ptr, PTR_REG );
831 /* Pass the packet up to the protocol layers. */
832 NetReceive(NetRxPackets[0], packet_length);
833 return packet_length;
842 /*------------------------------------------------------------
843 . Modify a bit in the LAN91C111 register set
844 .-------------------------------------------------------------*/
845 static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
846 unsigned int bit, int val)
850 SMC_SELECT_BANK( dev, bank );
852 regval = SMC_inw( dev, reg );
858 SMC_outw( dev, regval, 0 );
863 /*------------------------------------------------------------
864 . Retrieve a bit in the LAN91C111 register set
865 .-------------------------------------------------------------*/
866 static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit)
868 SMC_SELECT_BANK( dev, bank );
869 if ( SMC_inw( dev, reg ) & bit)
876 /*------------------------------------------------------------
877 . Modify a LAN91C111 register (word access only)
878 .-------------------------------------------------------------*/
879 static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val)
881 SMC_SELECT_BANK( dev, bank );
882 SMC_outw( dev, val, reg );
886 /*------------------------------------------------------------
887 . Retrieve a LAN91C111 register (word access only)
888 .-------------------------------------------------------------*/
889 static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg)
891 SMC_SELECT_BANK( dev, bank );
892 return(SMC_inw( dev, reg ));
897 /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
901 /*------------------------------------------------------------
902 . Debugging function for viewing MII Management serial bitstream
903 .-------------------------------------------------------------*/
904 static void smc_dump_mii_stream (byte * bits, int size)
909 for (i = 0; i < size; ++i) {
910 printf ("%d", i % 10);
914 for (i = 0; i < size; ++i) {
915 if (bits[i] & MII_MDOE)
922 for (i = 0; i < size; ++i) {
923 if (bits[i] & MII_MDO)
930 for (i = 0; i < size; ++i) {
931 if (bits[i] & MII_MDI)
941 /*------------------------------------------------------------
942 . Reads a register from the MII Management serial interface
943 .-------------------------------------------------------------*/
944 #ifndef CONFIG_SMC91111_EXT_PHY
945 static word smc_read_phy_register (struct eth_device *dev, byte phyreg)
955 byte phyaddr = SMC_PHY_ADDR;
957 /* 32 consecutive ones on MDO to establish sync */
958 for (i = 0; i < 32; ++i)
959 bits[clk_idx++] = MII_MDOE | MII_MDO;
961 /* Start code <01> */
962 bits[clk_idx++] = MII_MDOE;
963 bits[clk_idx++] = MII_MDOE | MII_MDO;
965 /* Read command <10> */
966 bits[clk_idx++] = MII_MDOE | MII_MDO;
967 bits[clk_idx++] = MII_MDOE;
969 /* Output the PHY address, msb first */
971 for (i = 0; i < 5; ++i) {
973 bits[clk_idx++] = MII_MDOE | MII_MDO;
975 bits[clk_idx++] = MII_MDOE;
977 /* Shift to next lowest bit */
981 /* Output the phy register number, msb first */
983 for (i = 0; i < 5; ++i) {
985 bits[clk_idx++] = MII_MDOE | MII_MDO;
987 bits[clk_idx++] = MII_MDOE;
989 /* Shift to next lowest bit */
993 /* Tristate and turnaround (2 bit times) */
995 /*bits[clk_idx++] = 0; */
997 /* Input starts at this bit time */
1000 /* Will input 16 bits */
1001 for (i = 0; i < 16; ++i)
1002 bits[clk_idx++] = 0;
1004 /* Final clock bit */
1005 bits[clk_idx++] = 0;
1007 /* Save the current bank */
1008 oldBank = SMC_inw (dev, BANK_SELECT);
1011 SMC_SELECT_BANK (dev, 3);
1013 /* Get the current MII register value */
1014 mii_reg = SMC_inw (dev, MII_REG);
1016 /* Turn off all MII Interface bits */
1017 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
1019 /* Clock all 64 cycles */
1020 for (i = 0; i < sizeof bits; ++i) {
1021 /* Clock Low - output data */
1022 SMC_outw (dev, mii_reg | bits[i], MII_REG);
1023 udelay (SMC_PHY_CLOCK_DELAY);
1026 /* Clock Hi - input data */
1027 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
1028 udelay (SMC_PHY_CLOCK_DELAY);
1029 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
1032 /* Return to idle state */
1033 /* Set clock to low, data to low, and output tristated */
1034 SMC_outw (dev, mii_reg, MII_REG);
1035 udelay (SMC_PHY_CLOCK_DELAY);
1037 /* Restore original bank select */
1038 SMC_SELECT_BANK (dev, oldBank);
1040 /* Recover input data */
1042 for (i = 0; i < 16; ++i) {
1045 if (bits[input_idx++] & MII_MDI)
1049 #if (SMC_DEBUG > 2 )
1050 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1051 phyaddr, phyreg, phydata);
1052 smc_dump_mii_stream (bits, sizeof bits);
1059 /*------------------------------------------------------------
1060 . Writes a register to the MII Management serial interface
1061 .-------------------------------------------------------------*/
1062 static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
1071 byte phyaddr = SMC_PHY_ADDR;
1073 /* 32 consecutive ones on MDO to establish sync */
1074 for (i = 0; i < 32; ++i)
1075 bits[clk_idx++] = MII_MDOE | MII_MDO;
1077 /* Start code <01> */
1078 bits[clk_idx++] = MII_MDOE;
1079 bits[clk_idx++] = MII_MDOE | MII_MDO;
1081 /* Write command <01> */
1082 bits[clk_idx++] = MII_MDOE;
1083 bits[clk_idx++] = MII_MDOE | MII_MDO;
1085 /* Output the PHY address, msb first */
1087 for (i = 0; i < 5; ++i) {
1089 bits[clk_idx++] = MII_MDOE | MII_MDO;
1091 bits[clk_idx++] = MII_MDOE;
1093 /* Shift to next lowest bit */
1097 /* Output the phy register number, msb first */
1099 for (i = 0; i < 5; ++i) {
1101 bits[clk_idx++] = MII_MDOE | MII_MDO;
1103 bits[clk_idx++] = MII_MDOE;
1105 /* Shift to next lowest bit */
1109 /* Tristate and turnaround (2 bit times) */
1110 bits[clk_idx++] = 0;
1111 bits[clk_idx++] = 0;
1113 /* Write out 16 bits of data, msb first */
1115 for (i = 0; i < 16; ++i) {
1117 bits[clk_idx++] = MII_MDOE | MII_MDO;
1119 bits[clk_idx++] = MII_MDOE;
1121 /* Shift to next lowest bit */
1125 /* Final clock bit (tristate) */
1126 bits[clk_idx++] = 0;
1128 /* Save the current bank */
1129 oldBank = SMC_inw (dev, BANK_SELECT);
1132 SMC_SELECT_BANK (dev, 3);
1134 /* Get the current MII register value */
1135 mii_reg = SMC_inw (dev, MII_REG);
1137 /* Turn off all MII Interface bits */
1138 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
1140 /* Clock all cycles */
1141 for (i = 0; i < sizeof bits; ++i) {
1142 /* Clock Low - output data */
1143 SMC_outw (dev, mii_reg | bits[i], MII_REG);
1144 udelay (SMC_PHY_CLOCK_DELAY);
1147 /* Clock Hi - input data */
1148 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
1149 udelay (SMC_PHY_CLOCK_DELAY);
1150 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
1153 /* Return to idle state */
1154 /* Set clock to low, data to low, and output tristated */
1155 SMC_outw (dev, mii_reg, MII_REG);
1156 udelay (SMC_PHY_CLOCK_DELAY);
1158 /* Restore original bank select */
1159 SMC_SELECT_BANK (dev, oldBank);
1161 #if (SMC_DEBUG > 2 )
1162 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1163 phyaddr, phyreg, phydata);
1164 smc_dump_mii_stream (bits, sizeof bits);
1167 #endif /* !CONFIG_SMC91111_EXT_PHY */
1170 /*------------------------------------------------------------
1171 . Configures the specified PHY using Autonegotiation. Calls
1172 . smc_phy_fixed() if the user has requested a certain config.
1173 .-------------------------------------------------------------*/
1174 #ifndef CONFIG_SMC91111_EXT_PHY
1175 static void smc_phy_configure (struct eth_device *dev)
1178 word my_phy_caps; /* My PHY capabilities */
1179 word my_ad_caps; /* My Advertised capabilities */
1180 word status = 0; /*;my status = 0 */
1182 PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
1184 /* Reset the PHY, setting all other bits to zero */
1185 smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
1187 /* Wait for the reset to complete, or time out */
1188 timeout = 6; /* Wait up to 3 seconds */
1190 if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
1192 /* reset complete */
1196 mdelay(500); /* wait 500 millisecs */
1200 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
1201 goto smc_phy_configure_exit;
1204 /* Read PHY Register 18, Status Output */
1205 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1207 /* Enable PHY Interrupts (for register 18) */
1208 /* Interrupts listed here are disabled */
1209 smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
1211 /* Configure the Receive/Phy Control register */
1212 SMC_SELECT_BANK (dev, 0);
1213 SMC_outw (dev, RPC_DEFAULT, RPC_REG);
1215 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
1216 my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
1217 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
1219 if (my_phy_caps & PHY_STAT_CAP_T4)
1220 my_ad_caps |= PHY_AD_T4;
1222 if (my_phy_caps & PHY_STAT_CAP_TXF)
1223 my_ad_caps |= PHY_AD_TX_FDX;
1225 if (my_phy_caps & PHY_STAT_CAP_TXH)
1226 my_ad_caps |= PHY_AD_TX_HDX;
1228 if (my_phy_caps & PHY_STAT_CAP_TF)
1229 my_ad_caps |= PHY_AD_10_FDX;
1231 if (my_phy_caps & PHY_STAT_CAP_TH)
1232 my_ad_caps |= PHY_AD_10_HDX;
1234 /* Update our Auto-Neg Advertisement Register */
1235 smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
1237 /* Read the register back. Without this, it appears that when */
1238 /* auto-negotiation is restarted, sometimes it isn't ready and */
1239 /* the link does not come up. */
1240 smc_read_phy_register(dev, PHY_AD_REG);
1242 PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1243 PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
1245 /* Restart auto-negotiation process in order to advertise my caps */
1246 smc_write_phy_register (dev, PHY_CNTL_REG,
1247 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
1249 /* Wait for the auto-negotiation to complete. This may take from */
1250 /* 2 to 3 seconds. */
1251 /* Wait for the reset to complete, or time out */
1252 timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
1255 status = smc_read_phy_register (dev, PHY_STAT_REG);
1256 if (status & PHY_STAT_ANEG_ACK) {
1257 /* auto-negotiate complete */
1261 mdelay(500); /* wait 500 millisecs */
1263 /* Restart auto-negotiation if remote fault */
1264 if (status & PHY_STAT_REM_FLT) {
1265 printf ("%s: PHY remote fault detected\n",
1268 /* Restart auto-negotiation */
1269 printf ("%s: PHY restarting auto-negotiation\n",
1271 smc_write_phy_register (dev, PHY_CNTL_REG,
1280 printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
1283 /* Fail if we detected an auto-negotiate remote fault */
1284 if (status & PHY_STAT_REM_FLT) {
1285 printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
1288 /* Re-Configure the Receive/Phy Control register */
1289 SMC_outw (dev, RPC_DEFAULT, RPC_REG);
1291 smc_phy_configure_exit: ;
1294 #endif /* !CONFIG_SMC91111_EXT_PHY */
1298 static void print_packet( byte * buf, int length )
1304 printf("Packet of length %d \n", length );
1307 lines = length / 16;
1308 remainder = length % 16;
1310 for ( i = 0; i < lines ; i ++ ) {
1313 for ( cur = 0; cur < 8; cur ++ ) {
1318 printf("%02x%02x ", a, b );
1322 for ( i = 0; i < remainder/2 ; i++ ) {
1327 printf("%02x%02x ", a, b );
1334 int smc91111_initialize(u8 dev_num, int base_addr)
1336 struct smc91111_priv *priv;
1337 struct eth_device *dev;
1340 priv = malloc(sizeof(*priv));
1343 dev = malloc(sizeof(*dev));
1349 memset(dev, 0, sizeof(*dev));
1350 priv->dev_num = dev_num;
1352 dev->iobase = base_addr;
1355 SMC_SELECT_BANK(dev, 1);
1356 for (i = 0; i < 6; ++i)
1357 dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
1360 dev->init = smc_init;
1361 dev->halt = smc_halt;
1362 dev->send = smc_send;
1363 dev->recv = smc_rcv;
1364 dev->write_hwaddr = smc_write_hwaddr;
1365 sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);