2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.26"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
67 /* This is the worst case number of transmit list elements for a single skb:
68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71 #define TX_MAX_PENDING 4096
72 #define TX_DEF_PENDING 127
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
147 MODULE_DEVICE_TABLE(pci, sky2_id_table);
149 /* Avoid conditionals by using array */
150 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
152 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
154 static void sky2_set_multicast(struct net_device *dev);
156 /* Access to PHY via serial interconnect */
157 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
165 for (i = 0; i < PHY_RETRIES; i++) {
166 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
170 if (!(ctrl & GM_SMI_CT_BUSY))
176 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
180 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
184 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
188 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
189 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
191 for (i = 0; i < PHY_RETRIES; i++) {
192 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
196 if (ctrl & GM_SMI_CT_RD_VAL) {
197 *val = gma_read16(hw, port, GM_SMI_DATA);
204 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
207 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
211 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
214 __gm_phy_read(hw, port, reg, &v);
219 static void sky2_power_on(struct sky2_hw *hw)
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw, B0_POWER_CTRL,
223 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
225 /* disable Core Clock Division, */
226 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
229 /* enable bits are inverted */
230 sky2_write8(hw, B2_Y2_CLK_GATE,
231 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
232 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
233 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
237 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
242 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg &= P_ASPM_CONTROL_MSK;
245 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
247 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
248 /* set all bits to 0 except bits 28 & 27 */
249 reg &= P_CTL_TIM_VMAIN_AV_MSK;
250 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
252 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
254 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
256 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
257 reg = sky2_read32(hw, B2_GP_IO);
258 reg |= GLB_GPIO_STAT_RACE_DIS;
259 sky2_write32(hw, B2_GP_IO, reg);
261 sky2_read32(hw, B2_GP_IO);
264 /* Turn on "driver loaded" LED */
265 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
268 static void sky2_power_aux(struct sky2_hw *hw)
270 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
271 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
273 /* enable bits are inverted */
274 sky2_write8(hw, B2_Y2_CLK_GATE,
275 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
276 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
277 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
279 /* switch power to VAUX if supported and PME from D3cold */
280 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
281 pci_pme_capable(hw->pdev, PCI_D3cold))
282 sky2_write8(hw, B0_POWER_CTRL,
283 (PC_VAUX_ENA | PC_VCC_ENA |
284 PC_VAUX_ON | PC_VCC_OFF));
286 /* turn off "driver loaded LED" */
287 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
290 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
294 /* disable all GMAC IRQ's */
295 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
297 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
298 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
299 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
300 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
302 reg = gma_read16(hw, port, GM_RX_CTRL);
303 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
304 gma_write16(hw, port, GM_RX_CTRL, reg);
307 /* flow control to advertise bits */
308 static const u16 copper_fc_adv[] = {
310 [FC_TX] = PHY_M_AN_ASP,
311 [FC_RX] = PHY_M_AN_PC,
312 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
315 /* flow control to advertise bits when using 1000BaseX */
316 static const u16 fiber_fc_adv[] = {
317 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
318 [FC_TX] = PHY_M_P_ASYM_MD_X,
319 [FC_RX] = PHY_M_P_SYM_MD_X,
320 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
323 /* flow control to GMA disable bits */
324 static const u16 gm_fc_disable[] = {
325 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
326 [FC_TX] = GM_GPCR_FC_RX_DIS,
327 [FC_RX] = GM_GPCR_FC_TX_DIS,
332 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
334 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
335 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
337 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
338 !(hw->flags & SKY2_HW_NEWER_PHY)) {
339 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
341 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
343 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
345 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
346 if (hw->chip_id == CHIP_ID_YUKON_EC)
347 /* set downshift counter to 3x and enable downshift */
348 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
350 /* set master & slave downshift counter to 1x */
351 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
353 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
356 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
357 if (sky2_is_copper(hw)) {
358 if (!(hw->flags & SKY2_HW_GIGABIT)) {
359 /* enable automatic crossover */
360 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
362 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
363 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
366 /* Enable Class A driver for FE+ A0 */
367 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
368 spec |= PHY_M_FESC_SEL_CL_A;
369 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
372 /* disable energy detect */
373 ctrl &= ~PHY_M_PC_EN_DET_MSK;
375 /* enable automatic crossover */
376 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
378 /* downshift on PHY 88E1112 and 88E1149 is changed */
379 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
380 (hw->flags & SKY2_HW_NEWER_PHY)) {
381 /* set downshift counter to 3x and enable downshift */
382 ctrl &= ~PHY_M_PC_DSC_MSK;
383 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
387 /* workaround for deviation #4.88 (CRC errors) */
388 /* disable Automatic Crossover */
390 ctrl &= ~PHY_M_PC_MDIX_MSK;
393 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
395 /* special setup for PHY 88E1112 Fiber */
396 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
397 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
399 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
400 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
401 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
402 ctrl &= ~PHY_M_MAC_MD_MSK;
403 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
404 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
406 if (hw->pmd_type == 'P') {
407 /* select page 1 to access Fiber registers */
408 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
410 /* for SFP-module set SIGDET polarity to low */
411 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
412 ctrl |= PHY_M_FIB_SIGD_POL;
413 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
416 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
424 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
425 if (sky2_is_copper(hw)) {
426 if (sky2->advertising & ADVERTISED_1000baseT_Full)
427 ct1000 |= PHY_M_1000C_AFD;
428 if (sky2->advertising & ADVERTISED_1000baseT_Half)
429 ct1000 |= PHY_M_1000C_AHD;
430 if (sky2->advertising & ADVERTISED_100baseT_Full)
431 adv |= PHY_M_AN_100_FD;
432 if (sky2->advertising & ADVERTISED_100baseT_Half)
433 adv |= PHY_M_AN_100_HD;
434 if (sky2->advertising & ADVERTISED_10baseT_Full)
435 adv |= PHY_M_AN_10_FD;
436 if (sky2->advertising & ADVERTISED_10baseT_Half)
437 adv |= PHY_M_AN_10_HD;
439 } else { /* special defines for FIBER (88E1040S only) */
440 if (sky2->advertising & ADVERTISED_1000baseT_Full)
441 adv |= PHY_M_AN_1000X_AFD;
442 if (sky2->advertising & ADVERTISED_1000baseT_Half)
443 adv |= PHY_M_AN_1000X_AHD;
446 /* Restart Auto-negotiation */
447 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
449 /* forced speed/duplex settings */
450 ct1000 = PHY_M_1000C_MSE;
452 /* Disable auto update for duplex flow control and duplex */
453 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
455 switch (sky2->speed) {
457 ctrl |= PHY_CT_SP1000;
458 reg |= GM_GPCR_SPEED_1000;
461 ctrl |= PHY_CT_SP100;
462 reg |= GM_GPCR_SPEED_100;
466 if (sky2->duplex == DUPLEX_FULL) {
467 reg |= GM_GPCR_DUP_FULL;
468 ctrl |= PHY_CT_DUP_MD;
469 } else if (sky2->speed < SPEED_1000)
470 sky2->flow_mode = FC_NONE;
473 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
474 if (sky2_is_copper(hw))
475 adv |= copper_fc_adv[sky2->flow_mode];
477 adv |= fiber_fc_adv[sky2->flow_mode];
479 reg |= GM_GPCR_AU_FCT_DIS;
480 reg |= gm_fc_disable[sky2->flow_mode];
482 /* Forward pause packets to GMAC? */
483 if (sky2->flow_mode & FC_RX)
484 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
486 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
489 gma_write16(hw, port, GM_GP_CTRL, reg);
491 if (hw->flags & SKY2_HW_GIGABIT)
492 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
494 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
495 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
497 /* Setup Phy LED's */
498 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
501 switch (hw->chip_id) {
502 case CHIP_ID_YUKON_FE:
503 /* on 88E3082 these bits are at 11..9 (shifted left) */
504 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
506 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
508 /* delete ACT LED control bits */
509 ctrl &= ~PHY_M_FELP_LED1_MSK;
510 /* change ACT LED control to blink mode */
511 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
515 case CHIP_ID_YUKON_FE_P:
516 /* Enable Link Partner Next Page */
517 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
518 ctrl |= PHY_M_PC_ENA_LIP_NP;
520 /* disable Energy Detect and enable scrambler */
521 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
524 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
525 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
526 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
527 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
529 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
532 case CHIP_ID_YUKON_XL:
533 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
535 /* select page 3 to access LED control register */
536 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
538 /* set LED Function Control register */
539 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
540 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
541 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
542 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
543 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
545 /* set Polarity Control register */
546 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
547 (PHY_M_POLC_LS1_P_MIX(4) |
548 PHY_M_POLC_IS0_P_MIX(4) |
549 PHY_M_POLC_LOS_CTRL(2) |
550 PHY_M_POLC_INIT_CTRL(2) |
551 PHY_M_POLC_STA1_CTRL(2) |
552 PHY_M_POLC_STA0_CTRL(2)));
554 /* restore page register */
555 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
558 case CHIP_ID_YUKON_EC_U:
559 case CHIP_ID_YUKON_EX:
560 case CHIP_ID_YUKON_SUPR:
561 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
563 /* select page 3 to access LED control register */
564 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
566 /* set LED Function Control register */
567 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
568 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
569 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
570 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
571 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
573 /* set Blink Rate in LED Timer Control Register */
574 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
575 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
576 /* restore page register */
577 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
581 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
582 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
584 /* turn off the Rx LED (LED_RX) */
585 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
588 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
589 /* apply fixes in PHY AFE */
590 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
592 /* increase differential signal amplitude in 10BASE-T */
593 gm_phy_write(hw, port, 0x18, 0xaa99);
594 gm_phy_write(hw, port, 0x17, 0x2011);
596 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
597 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
598 gm_phy_write(hw, port, 0x18, 0xa204);
599 gm_phy_write(hw, port, 0x17, 0x2002);
602 /* set page register to 0 */
603 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
604 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
605 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
606 /* apply workaround for integrated resistors calibration */
607 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
608 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
609 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
610 /* apply fixes in PHY AFE */
611 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
613 /* apply RDAC termination workaround */
614 gm_phy_write(hw, port, 24, 0x2800);
615 gm_phy_write(hw, port, 23, 0x2001);
617 /* set page register back to 0 */
618 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
619 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
620 hw->chip_id < CHIP_ID_YUKON_SUPR) {
621 /* no effect on Yukon-XL */
622 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
624 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
625 sky2->speed == SPEED_100) {
626 /* turn on 100 Mbps LED (LED_LINK100) */
627 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
631 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
635 /* Enable phy interrupt on auto-negotiation complete (or link up) */
636 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
637 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
639 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
642 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
643 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
645 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
649 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
650 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
651 reg1 &= ~phy_power[port];
653 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
654 reg1 |= coma_mode[port];
656 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
657 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
658 sky2_pci_read32(hw, PCI_DEV_REG1);
660 if (hw->chip_id == CHIP_ID_YUKON_FE)
661 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
662 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
663 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
666 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
671 /* release GPHY Control reset */
672 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
674 /* release GMAC reset */
675 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
677 if (hw->flags & SKY2_HW_NEWER_PHY) {
678 /* select page 2 to access MAC control register */
679 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
681 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
682 /* allow GMII Power Down */
683 ctrl &= ~PHY_M_MAC_GMIF_PUP;
684 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
686 /* set page register back to 0 */
687 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
690 /* setup General Purpose Control Register */
691 gma_write16(hw, port, GM_GP_CTRL,
692 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
693 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
696 if (hw->chip_id != CHIP_ID_YUKON_EC) {
697 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
698 /* select page 2 to access MAC control register */
699 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
701 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
702 /* enable Power Down */
703 ctrl |= PHY_M_PC_POW_D_ENA;
704 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
706 /* set page register back to 0 */
707 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
710 /* set IEEE compatible Power Down Mode (dev. #4.99) */
711 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
714 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
715 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
716 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
717 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
718 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
721 /* Force a renegotiation */
722 static void sky2_phy_reinit(struct sky2_port *sky2)
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_init(sky2->hw, sky2->port);
726 spin_unlock_bh(&sky2->phy_lock);
729 /* Put device in state to listen for Wake On Lan */
730 static void sky2_wol_init(struct sky2_port *sky2)
732 struct sky2_hw *hw = sky2->hw;
733 unsigned port = sky2->port;
734 enum flow_control save_mode;
738 /* Bring hardware out of reset */
739 sky2_write16(hw, B0_CTST, CS_RST_CLR);
740 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
742 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
743 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
746 * sky2_reset will re-enable on resume
748 save_mode = sky2->flow_mode;
749 ctrl = sky2->advertising;
751 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
752 sky2->flow_mode = FC_NONE;
754 spin_lock_bh(&sky2->phy_lock);
755 sky2_phy_power_up(hw, port);
756 sky2_phy_init(hw, port);
757 spin_unlock_bh(&sky2->phy_lock);
759 sky2->flow_mode = save_mode;
760 sky2->advertising = ctrl;
762 /* Set GMAC to no flow control and auto update for speed/duplex */
763 gma_write16(hw, port, GM_GP_CTRL,
764 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
765 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
767 /* Set WOL address */
768 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
769 sky2->netdev->dev_addr, ETH_ALEN);
771 /* Turn on appropriate WOL control bits */
772 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
774 if (sky2->wol & WAKE_PHY)
775 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
777 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
779 if (sky2->wol & WAKE_MAGIC)
780 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
782 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
784 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
785 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
787 /* Disable PiG firmware */
788 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
790 /* Turn on legacy PCI-Express PME mode */
791 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
792 reg1 |= PCI_Y2_PME_LEGACY;
793 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
796 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
799 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
801 struct net_device *dev = hw->dev[port];
803 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
804 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
805 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
806 /* Yukon-Extreme B0 and further Extreme devices */
807 /* enable Store & Forward mode for TX */
809 if (dev->mtu <= ETH_DATA_LEN)
810 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
811 TX_JUMBO_DIS | TX_STFW_ENA);
814 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
815 TX_JUMBO_ENA| TX_STFW_ENA);
817 if (dev->mtu <= ETH_DATA_LEN)
818 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
820 /* set Tx GMAC FIFO Almost Empty Threshold */
821 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
822 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
824 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
826 /* Can't do offload because of lack of store/forward */
827 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
832 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
834 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
838 const u8 *addr = hw->dev[port]->dev_addr;
840 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
841 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
843 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
845 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
846 /* WA DEV_472 -- looks like crossed wires on port 2 */
847 /* clear GMAC 1 Control reset */
848 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
850 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
851 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
852 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
853 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
854 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
857 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
859 /* Enable Transmit FIFO Underrun */
860 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
862 spin_lock_bh(&sky2->phy_lock);
863 sky2_phy_power_up(hw, port);
864 sky2_phy_init(hw, port);
865 spin_unlock_bh(&sky2->phy_lock);
868 reg = gma_read16(hw, port, GM_PHY_ADDR);
869 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
871 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
872 gma_read16(hw, port, i);
873 gma_write16(hw, port, GM_PHY_ADDR, reg);
875 /* transmit control */
876 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
878 /* receive control reg: unicast + multicast + no FCS */
879 gma_write16(hw, port, GM_RX_CTRL,
880 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
882 /* transmit flow control */
883 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
885 /* transmit parameter */
886 gma_write16(hw, port, GM_TX_PARAM,
887 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
888 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
889 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
890 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
892 /* serial mode register */
893 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
894 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
896 if (hw->dev[port]->mtu > ETH_DATA_LEN)
897 reg |= GM_SMOD_JUMBO_ENA;
899 gma_write16(hw, port, GM_SERIAL_MODE, reg);
901 /* virtual address for data */
902 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
904 /* physical address: used for pause frames */
905 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
907 /* ignore counter overflows */
908 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
909 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
910 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
912 /* Configure Rx MAC FIFO */
913 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
914 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
915 if (hw->chip_id == CHIP_ID_YUKON_EX ||
916 hw->chip_id == CHIP_ID_YUKON_FE_P)
917 rx_reg |= GMF_RX_OVER_ON;
919 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
921 if (hw->chip_id == CHIP_ID_YUKON_XL) {
922 /* Hardware errata - clear flush mask */
923 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
925 /* Flush Rx MAC FIFO on any flow control or error */
926 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
929 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
930 reg = RX_GMF_FL_THR_DEF + 1;
931 /* Another magic mystery workaround from sk98lin */
932 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
933 hw->chip_rev == CHIP_REV_YU_FE2_A0)
935 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
937 /* Configure Tx MAC FIFO */
938 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
939 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
941 /* On chips without ram buffer, pause is controled by MAC level */
942 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
943 /* Pause threshold is scaled by 8 in bytes */
944 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
945 hw->chip_rev == CHIP_REV_YU_FE2_A0)
949 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
950 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
952 sky2_set_tx_stfwd(hw, port);
955 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
956 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
957 /* disable dynamic watermark */
958 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
959 reg &= ~TX_DYN_WM_ENA;
960 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
964 /* Assign Ram Buffer allocation to queue */
965 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
969 /* convert from K bytes to qwords used for hw register */
972 end = start + space - 1;
974 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
975 sky2_write32(hw, RB_ADDR(q, RB_START), start);
976 sky2_write32(hw, RB_ADDR(q, RB_END), end);
977 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
978 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
980 if (q == Q_R1 || q == Q_R2) {
981 u32 tp = space - space/4;
983 /* On receive queue's set the thresholds
984 * give receiver priority when > 3/4 full
985 * send pause when down to 2K
987 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
988 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
991 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
992 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
994 /* Enable store & forward on Tx queue's because
995 * Tx FIFO is only 1K on Yukon
997 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1000 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1001 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1004 /* Setup Bus Memory Interface */
1005 static void sky2_qset(struct sky2_hw *hw, u16 q)
1007 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1008 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1009 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1010 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1013 /* Setup prefetch unit registers. This is the interface between
1014 * hardware and driver list elements
1016 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1017 dma_addr_t addr, u32 last)
1019 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1020 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1021 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1022 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1023 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1024 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1026 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1029 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1031 struct sky2_tx_le *le = sky2->tx_le + *slot;
1033 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1038 static void tx_init(struct sky2_port *sky2)
1040 struct sky2_tx_le *le;
1042 sky2->tx_prod = sky2->tx_cons = 0;
1043 sky2->tx_tcpsum = 0;
1044 sky2->tx_last_mss = 0;
1046 le = get_tx_le(sky2, &sky2->tx_prod);
1048 le->opcode = OP_ADDR64 | HW_OWNER;
1049 sky2->tx_last_upper = 0;
1052 /* Update chip's next pointer */
1053 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1055 /* Make sure write' to descriptors are complete before we tell hardware */
1057 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1059 /* Synchronize I/O on since next processor may write to tail */
1064 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1066 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1067 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1072 /* Build description to hardware for one receive segment */
1073 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1074 dma_addr_t map, unsigned len)
1076 struct sky2_rx_le *le;
1078 if (sizeof(dma_addr_t) > sizeof(u32)) {
1079 le = sky2_next_rx(sky2);
1080 le->addr = cpu_to_le32(upper_32_bits(map));
1081 le->opcode = OP_ADDR64 | HW_OWNER;
1084 le = sky2_next_rx(sky2);
1085 le->addr = cpu_to_le32(lower_32_bits(map));
1086 le->length = cpu_to_le16(len);
1087 le->opcode = op | HW_OWNER;
1090 /* Build description to hardware for one possibly fragmented skb */
1091 static void sky2_rx_submit(struct sky2_port *sky2,
1092 const struct rx_ring_info *re)
1096 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1098 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1099 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1103 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1106 struct sk_buff *skb = re->skb;
1109 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1110 if (pci_dma_mapping_error(pdev, re->data_addr))
1113 pci_unmap_len_set(re, data_size, size);
1115 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1116 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1118 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1121 PCI_DMA_FROMDEVICE);
1123 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1124 goto map_page_error;
1130 pci_unmap_page(pdev, re->frag_addr[i],
1131 skb_shinfo(skb)->frags[i].size,
1132 PCI_DMA_FROMDEVICE);
1135 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1136 PCI_DMA_FROMDEVICE);
1139 if (net_ratelimit())
1140 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1145 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1147 struct sk_buff *skb = re->skb;
1150 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1151 PCI_DMA_FROMDEVICE);
1153 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1154 pci_unmap_page(pdev, re->frag_addr[i],
1155 skb_shinfo(skb)->frags[i].size,
1156 PCI_DMA_FROMDEVICE);
1159 /* Tell chip where to start receive checksum.
1160 * Actually has two checksums, but set both same to avoid possible byte
1163 static void rx_set_checksum(struct sky2_port *sky2)
1165 struct sky2_rx_le *le = sky2_next_rx(sky2);
1167 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1169 le->opcode = OP_TCPSTART | HW_OWNER;
1171 sky2_write32(sky2->hw,
1172 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1173 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1174 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1178 * The RX Stop command will not work for Yukon-2 if the BMU does not
1179 * reach the end of packet and since we can't make sure that we have
1180 * incoming data, we must reset the BMU while it is not doing a DMA
1181 * transfer. Since it is possible that the RX path is still active,
1182 * the RX RAM buffer will be stopped first, so any possible incoming
1183 * data will not trigger a DMA. After the RAM buffer is stopped, the
1184 * BMU is polled until any DMA in progress is ended and only then it
1187 static void sky2_rx_stop(struct sky2_port *sky2)
1189 struct sky2_hw *hw = sky2->hw;
1190 unsigned rxq = rxqaddr[sky2->port];
1193 /* disable the RAM Buffer receive queue */
1194 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1196 for (i = 0; i < 0xffff; i++)
1197 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1198 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1201 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1202 sky2->netdev->name);
1204 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1206 /* reset the Rx prefetch unit */
1207 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1211 /* Clean out receive buffer area, assumes receiver hardware stopped */
1212 static void sky2_rx_clean(struct sky2_port *sky2)
1216 memset(sky2->rx_le, 0, RX_LE_BYTES);
1217 for (i = 0; i < sky2->rx_pending; i++) {
1218 struct rx_ring_info *re = sky2->rx_ring + i;
1221 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1228 /* Basic MII support */
1229 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1231 struct mii_ioctl_data *data = if_mii(ifr);
1232 struct sky2_port *sky2 = netdev_priv(dev);
1233 struct sky2_hw *hw = sky2->hw;
1234 int err = -EOPNOTSUPP;
1236 if (!netif_running(dev))
1237 return -ENODEV; /* Phy still in reset */
1241 data->phy_id = PHY_ADDR_MARV;
1247 spin_lock_bh(&sky2->phy_lock);
1248 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1249 spin_unlock_bh(&sky2->phy_lock);
1251 data->val_out = val;
1256 spin_lock_bh(&sky2->phy_lock);
1257 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1259 spin_unlock_bh(&sky2->phy_lock);
1265 #ifdef SKY2_VLAN_TAG_USED
1266 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1269 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1271 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1274 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1276 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1281 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1283 struct sky2_port *sky2 = netdev_priv(dev);
1284 struct sky2_hw *hw = sky2->hw;
1285 u16 port = sky2->port;
1287 netif_tx_lock_bh(dev);
1288 napi_disable(&hw->napi);
1291 sky2_set_vlan_mode(hw, port, grp != NULL);
1293 sky2_read32(hw, B0_Y2_SP_LISR);
1294 napi_enable(&hw->napi);
1295 netif_tx_unlock_bh(dev);
1299 /* Amount of required worst case padding in rx buffer */
1300 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1302 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1306 * Allocate an skb for receiving. If the MTU is large enough
1307 * make the skb non-linear with a fragment list of pages.
1309 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1311 struct sk_buff *skb;
1314 skb = netdev_alloc_skb(sky2->netdev,
1315 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
1319 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1320 unsigned char *start;
1322 * Workaround for a bug in FIFO that cause hang
1323 * if the FIFO if the receive buffer is not 64 byte aligned.
1324 * The buffer returned from netdev_alloc_skb is
1325 * aligned except if slab debugging is enabled.
1327 start = PTR_ALIGN(skb->data, 8);
1328 skb_reserve(skb, start - skb->data);
1330 skb_reserve(skb, NET_IP_ALIGN);
1332 for (i = 0; i < sky2->rx_nfrags; i++) {
1333 struct page *page = alloc_page(GFP_ATOMIC);
1337 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1347 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1349 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1353 * Allocate and setup receiver buffer pool.
1354 * Normal case this ends up creating one list element for skb
1355 * in the receive ring. Worst case if using large MTU and each
1356 * allocation falls on a different 64 bit region, that results
1357 * in 6 list elements per ring entry.
1358 * One element is used for checksum enable/disable, and one
1359 * extra to avoid wrap.
1361 static int sky2_rx_start(struct sky2_port *sky2)
1363 struct sky2_hw *hw = sky2->hw;
1364 struct rx_ring_info *re;
1365 unsigned rxq = rxqaddr[sky2->port];
1366 unsigned i, size, thresh;
1368 sky2->rx_put = sky2->rx_next = 0;
1371 /* On PCI express lowering the watermark gives better performance */
1372 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1373 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1375 /* These chips have no ram buffer?
1376 * MAC Rx RAM Read is controlled by hardware */
1377 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1378 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1379 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1380 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1382 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1384 if (!(hw->flags & SKY2_HW_NEW_LE))
1385 rx_set_checksum(sky2);
1387 /* Space needed for frame data + headers rounded up */
1388 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1390 /* Stopping point for hardware truncation */
1391 thresh = (size - 8) / sizeof(u32);
1393 sky2->rx_nfrags = size >> PAGE_SHIFT;
1394 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1396 /* Compute residue after pages */
1397 size -= sky2->rx_nfrags << PAGE_SHIFT;
1399 /* Optimize to handle small packets and headers */
1400 if (size < copybreak)
1402 if (size < ETH_HLEN)
1405 sky2->rx_data_size = size;
1408 for (i = 0; i < sky2->rx_pending; i++) {
1409 re = sky2->rx_ring + i;
1411 re->skb = sky2_rx_alloc(sky2);
1415 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1416 dev_kfree_skb(re->skb);
1421 sky2_rx_submit(sky2, re);
1425 * The receiver hangs if it receives frames larger than the
1426 * packet buffer. As a workaround, truncate oversize frames, but
1427 * the register is limited to 9 bits, so if you do frames > 2052
1428 * you better get the MTU right!
1431 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1433 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1434 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1437 /* Tell chip about available buffers */
1438 sky2_rx_update(sky2, rxq);
1440 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1441 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1443 * Disable flushing of non ASF packets;
1444 * must be done after initializing the BMUs;
1445 * drivers without ASF support should do this too, otherwise
1446 * it may happen that they cannot run on ASF devices;
1447 * remember that the MAC FIFO isn't reset during initialization.
1449 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1452 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1453 /* Enable RX Home Address & Routing Header checksum fix */
1454 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1455 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1457 /* Enable TX Home Address & Routing Header checksum fix */
1458 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1459 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1466 sky2_rx_clean(sky2);
1470 static int sky2_alloc_buffers(struct sky2_port *sky2)
1472 struct sky2_hw *hw = sky2->hw;
1474 /* must be power of 2 */
1475 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1476 sky2->tx_ring_size *
1477 sizeof(struct sky2_tx_le),
1482 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1487 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1491 memset(sky2->rx_le, 0, RX_LE_BYTES);
1493 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1503 static void sky2_free_buffers(struct sky2_port *sky2)
1505 struct sky2_hw *hw = sky2->hw;
1508 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1509 sky2->rx_le, sky2->rx_le_map);
1513 pci_free_consistent(hw->pdev,
1514 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1515 sky2->tx_le, sky2->tx_le_map);
1518 kfree(sky2->tx_ring);
1519 kfree(sky2->rx_ring);
1521 sky2->tx_ring = NULL;
1522 sky2->rx_ring = NULL;
1525 /* Bring up network interface. */
1526 static int sky2_up(struct net_device *dev)
1528 struct sky2_port *sky2 = netdev_priv(dev);
1529 struct sky2_hw *hw = sky2->hw;
1530 unsigned port = sky2->port;
1533 struct net_device *otherdev = hw->dev[sky2->port^1];
1536 * On dual port PCI-X card, there is an problem where status
1537 * can be received out of order due to split transactions
1539 if (otherdev && netif_running(otherdev) &&
1540 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1543 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1544 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1545 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1549 netif_carrier_off(dev);
1551 err = sky2_alloc_buffers(sky2);
1557 sky2_mac_init(hw, port);
1559 /* Register is number of 4K blocks on internal RAM buffer. */
1560 ramsize = sky2_read8(hw, B2_E_0) * 4;
1564 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1566 rxspace = ramsize / 2;
1568 rxspace = 8 + (2*(ramsize - 16))/3;
1570 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1571 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1573 /* Make sure SyncQ is disabled */
1574 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1578 sky2_qset(hw, txqaddr[port]);
1580 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1581 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1582 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1584 /* Set almost empty threshold */
1585 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1586 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1587 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1589 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1590 sky2->tx_ring_size - 1);
1592 #ifdef SKY2_VLAN_TAG_USED
1593 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1596 err = sky2_rx_start(sky2);
1600 /* Enable interrupts from phy/mac for port */
1601 imask = sky2_read32(hw, B0_IMSK);
1602 imask |= portirq_msk[port];
1603 sky2_write32(hw, B0_IMSK, imask);
1604 sky2_read32(hw, B0_IMSK);
1606 if (netif_msg_ifup(sky2))
1607 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1612 sky2_free_buffers(sky2);
1616 /* Modular subtraction in ring */
1617 static inline int tx_inuse(const struct sky2_port *sky2)
1619 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1622 /* Number of list elements available for next tx */
1623 static inline int tx_avail(const struct sky2_port *sky2)
1625 return sky2->tx_pending - tx_inuse(sky2);
1628 /* Estimate of number of transmit list elements required */
1629 static unsigned tx_le_req(const struct sk_buff *skb)
1633 count = (skb_shinfo(skb)->nr_frags + 1)
1634 * (sizeof(dma_addr_t) / sizeof(u32));
1636 if (skb_is_gso(skb))
1638 else if (sizeof(dma_addr_t) == sizeof(u32))
1639 ++count; /* possible vlan */
1641 if (skb->ip_summed == CHECKSUM_PARTIAL)
1647 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1649 if (re->flags & TX_MAP_SINGLE)
1650 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1651 pci_unmap_len(re, maplen),
1653 else if (re->flags & TX_MAP_PAGE)
1654 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1655 pci_unmap_len(re, maplen),
1661 * Put one packet in ring for transmit.
1662 * A single packet can generate multiple list elements, and
1663 * the number of ring elements will probably be less than the number
1664 * of list elements used.
1666 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1667 struct net_device *dev)
1669 struct sky2_port *sky2 = netdev_priv(dev);
1670 struct sky2_hw *hw = sky2->hw;
1671 struct sky2_tx_le *le = NULL;
1672 struct tx_ring_info *re;
1680 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1681 return NETDEV_TX_BUSY;
1683 len = skb_headlen(skb);
1684 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1686 if (pci_dma_mapping_error(hw->pdev, mapping))
1689 slot = sky2->tx_prod;
1690 if (unlikely(netif_msg_tx_queued(sky2)))
1691 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1692 dev->name, slot, skb->len);
1694 /* Send high bits if needed */
1695 upper = upper_32_bits(mapping);
1696 if (upper != sky2->tx_last_upper) {
1697 le = get_tx_le(sky2, &slot);
1698 le->addr = cpu_to_le32(upper);
1699 sky2->tx_last_upper = upper;
1700 le->opcode = OP_ADDR64 | HW_OWNER;
1703 /* Check for TCP Segmentation Offload */
1704 mss = skb_shinfo(skb)->gso_size;
1707 if (!(hw->flags & SKY2_HW_NEW_LE))
1708 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1710 if (mss != sky2->tx_last_mss) {
1711 le = get_tx_le(sky2, &slot);
1712 le->addr = cpu_to_le32(mss);
1714 if (hw->flags & SKY2_HW_NEW_LE)
1715 le->opcode = OP_MSS | HW_OWNER;
1717 le->opcode = OP_LRGLEN | HW_OWNER;
1718 sky2->tx_last_mss = mss;
1723 #ifdef SKY2_VLAN_TAG_USED
1724 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1725 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1727 le = get_tx_le(sky2, &slot);
1729 le->opcode = OP_VLAN|HW_OWNER;
1731 le->opcode |= OP_VLAN;
1732 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1737 /* Handle TCP checksum offload */
1738 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1739 /* On Yukon EX (some versions) encoding change. */
1740 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1741 ctrl |= CALSUM; /* auto checksum */
1743 const unsigned offset = skb_transport_offset(skb);
1746 tcpsum = offset << 16; /* sum start */
1747 tcpsum |= offset + skb->csum_offset; /* sum write */
1749 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1750 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1753 if (tcpsum != sky2->tx_tcpsum) {
1754 sky2->tx_tcpsum = tcpsum;
1756 le = get_tx_le(sky2, &slot);
1757 le->addr = cpu_to_le32(tcpsum);
1758 le->length = 0; /* initial checksum value */
1759 le->ctrl = 1; /* one packet */
1760 le->opcode = OP_TCPLISW | HW_OWNER;
1765 re = sky2->tx_ring + slot;
1766 re->flags = TX_MAP_SINGLE;
1767 pci_unmap_addr_set(re, mapaddr, mapping);
1768 pci_unmap_len_set(re, maplen, len);
1770 le = get_tx_le(sky2, &slot);
1771 le->addr = cpu_to_le32(lower_32_bits(mapping));
1772 le->length = cpu_to_le16(len);
1774 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1777 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1778 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1780 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1781 frag->size, PCI_DMA_TODEVICE);
1783 if (pci_dma_mapping_error(hw->pdev, mapping))
1784 goto mapping_unwind;
1786 upper = upper_32_bits(mapping);
1787 if (upper != sky2->tx_last_upper) {
1788 le = get_tx_le(sky2, &slot);
1789 le->addr = cpu_to_le32(upper);
1790 sky2->tx_last_upper = upper;
1791 le->opcode = OP_ADDR64 | HW_OWNER;
1794 re = sky2->tx_ring + slot;
1795 re->flags = TX_MAP_PAGE;
1796 pci_unmap_addr_set(re, mapaddr, mapping);
1797 pci_unmap_len_set(re, maplen, frag->size);
1799 le = get_tx_le(sky2, &slot);
1800 le->addr = cpu_to_le32(lower_32_bits(mapping));
1801 le->length = cpu_to_le16(frag->size);
1803 le->opcode = OP_BUFFER | HW_OWNER;
1809 sky2->tx_prod = slot;
1811 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1812 netif_stop_queue(dev);
1814 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1816 return NETDEV_TX_OK;
1819 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1820 re = sky2->tx_ring + i;
1822 sky2_tx_unmap(hw->pdev, re);
1826 if (net_ratelimit())
1827 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1829 return NETDEV_TX_OK;
1833 * Free ring elements from starting at tx_cons until "done"
1836 * 1. The hardware will tell us about partial completion of multi-part
1837 * buffers so make sure not to free skb to early.
1838 * 2. This may run in parallel start_xmit because the it only
1839 * looks at the tail of the queue of FIFO (tx_cons), not
1840 * the head (tx_prod)
1842 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1844 struct net_device *dev = sky2->netdev;
1847 BUG_ON(done >= sky2->tx_ring_size);
1849 for (idx = sky2->tx_cons; idx != done;
1850 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1851 struct tx_ring_info *re = sky2->tx_ring + idx;
1852 struct sk_buff *skb = re->skb;
1854 sky2_tx_unmap(sky2->hw->pdev, re);
1857 if (unlikely(netif_msg_tx_done(sky2)))
1858 printk(KERN_DEBUG "%s: tx done %u\n",
1861 dev->stats.tx_packets++;
1862 dev->stats.tx_bytes += skb->len;
1865 dev_kfree_skb_any(skb);
1867 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1871 sky2->tx_cons = idx;
1874 /* Wake unless it's detached, and called e.g. from sky2_down() */
1875 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4 && netif_device_present(dev))
1876 netif_wake_queue(dev);
1879 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1881 /* Disable Force Sync bit and Enable Alloc bit */
1882 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1883 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1885 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1886 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1887 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1889 /* Reset the PCI FIFO of the async Tx queue */
1890 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1891 BMU_RST_SET | BMU_FIFO_RST);
1893 /* Reset the Tx prefetch units */
1894 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1897 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1898 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1901 /* Network shutdown */
1902 static int sky2_down(struct net_device *dev)
1904 struct sky2_port *sky2 = netdev_priv(dev);
1905 struct sky2_hw *hw = sky2->hw;
1906 unsigned port = sky2->port;
1910 /* Never really got started! */
1914 if (netif_msg_ifdown(sky2))
1915 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1917 /* Force flow control off */
1918 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1920 /* Stop transmitter */
1921 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1922 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1924 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1925 RB_RST_SET | RB_DIS_OP_MD);
1927 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1928 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1929 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1931 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1933 /* Workaround shared GMAC reset */
1934 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1935 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1936 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1938 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1940 /* Force any delayed status interrrupt and NAPI */
1941 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1942 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1943 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1944 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1948 /* Disable port IRQ */
1949 imask = sky2_read32(hw, B0_IMSK);
1950 imask &= ~portirq_msk[port];
1951 sky2_write32(hw, B0_IMSK, imask);
1952 sky2_read32(hw, B0_IMSK);
1954 synchronize_irq(hw->pdev->irq);
1955 napi_synchronize(&hw->napi);
1957 spin_lock_bh(&sky2->phy_lock);
1958 sky2_phy_power_down(hw, port);
1959 spin_unlock_bh(&sky2->phy_lock);
1961 sky2_tx_reset(hw, port);
1963 /* Free any pending frames stuck in HW queue */
1964 sky2_tx_complete(sky2, sky2->tx_prod);
1966 sky2_rx_clean(sky2);
1968 sky2_free_buffers(sky2);
1973 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1975 if (hw->flags & SKY2_HW_FIBRE_PHY)
1978 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1979 if (aux & PHY_M_PS_SPEED_100)
1985 switch (aux & PHY_M_PS_SPEED_MSK) {
1986 case PHY_M_PS_SPEED_1000:
1988 case PHY_M_PS_SPEED_100:
1995 static void sky2_link_up(struct sky2_port *sky2)
1997 struct sky2_hw *hw = sky2->hw;
1998 unsigned port = sky2->port;
2000 static const char *fc_name[] = {
2008 reg = gma_read16(hw, port, GM_GP_CTRL);
2009 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2010 gma_write16(hw, port, GM_GP_CTRL, reg);
2012 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2014 netif_carrier_on(sky2->netdev);
2016 mod_timer(&hw->watchdog_timer, jiffies + 1);
2018 /* Turn on link LED */
2019 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2020 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2022 if (netif_msg_link(sky2))
2023 printk(KERN_INFO PFX
2024 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
2025 sky2->netdev->name, sky2->speed,
2026 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2027 fc_name[sky2->flow_status]);
2030 static void sky2_link_down(struct sky2_port *sky2)
2032 struct sky2_hw *hw = sky2->hw;
2033 unsigned port = sky2->port;
2036 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2038 reg = gma_read16(hw, port, GM_GP_CTRL);
2039 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2040 gma_write16(hw, port, GM_GP_CTRL, reg);
2042 netif_carrier_off(sky2->netdev);
2044 /* Turn off link LED */
2045 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2047 if (netif_msg_link(sky2))
2048 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2050 sky2_phy_init(hw, port);
2053 static enum flow_control sky2_flow(int rx, int tx)
2056 return tx ? FC_BOTH : FC_RX;
2058 return tx ? FC_TX : FC_NONE;
2061 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2063 struct sky2_hw *hw = sky2->hw;
2064 unsigned port = sky2->port;
2067 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2068 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2069 if (lpa & PHY_M_AN_RF) {
2070 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2074 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2075 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2076 sky2->netdev->name);
2080 sky2->speed = sky2_phy_speed(hw, aux);
2081 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2083 /* Since the pause result bits seem to in different positions on
2084 * different chips. look at registers.
2086 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2087 /* Shift for bits in fiber PHY */
2088 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2089 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2091 if (advert & ADVERTISE_1000XPAUSE)
2092 advert |= ADVERTISE_PAUSE_CAP;
2093 if (advert & ADVERTISE_1000XPSE_ASYM)
2094 advert |= ADVERTISE_PAUSE_ASYM;
2095 if (lpa & LPA_1000XPAUSE)
2096 lpa |= LPA_PAUSE_CAP;
2097 if (lpa & LPA_1000XPAUSE_ASYM)
2098 lpa |= LPA_PAUSE_ASYM;
2101 sky2->flow_status = FC_NONE;
2102 if (advert & ADVERTISE_PAUSE_CAP) {
2103 if (lpa & LPA_PAUSE_CAP)
2104 sky2->flow_status = FC_BOTH;
2105 else if (advert & ADVERTISE_PAUSE_ASYM)
2106 sky2->flow_status = FC_RX;
2107 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2108 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2109 sky2->flow_status = FC_TX;
2112 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2113 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2114 sky2->flow_status = FC_NONE;
2116 if (sky2->flow_status & FC_TX)
2117 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2119 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2124 /* Interrupt from PHY */
2125 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2127 struct net_device *dev = hw->dev[port];
2128 struct sky2_port *sky2 = netdev_priv(dev);
2129 u16 istatus, phystat;
2131 if (!netif_running(dev))
2134 spin_lock(&sky2->phy_lock);
2135 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2136 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2138 if (netif_msg_intr(sky2))
2139 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2140 sky2->netdev->name, istatus, phystat);
2142 if (istatus & PHY_M_IS_AN_COMPL) {
2143 if (sky2_autoneg_done(sky2, phystat) == 0)
2148 if (istatus & PHY_M_IS_LSP_CHANGE)
2149 sky2->speed = sky2_phy_speed(hw, phystat);
2151 if (istatus & PHY_M_IS_DUP_CHANGE)
2153 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2155 if (istatus & PHY_M_IS_LST_CHANGE) {
2156 if (phystat & PHY_M_PS_LINK_UP)
2159 sky2_link_down(sky2);
2162 spin_unlock(&sky2->phy_lock);
2165 /* Special quick link interrupt (Yukon-2 Optima only) */
2166 static void sky2_qlink_intr(struct sky2_hw *hw)
2168 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2173 imask = sky2_read32(hw, B0_IMSK);
2174 imask &= ~Y2_IS_PHY_QLNK;
2175 sky2_write32(hw, B0_IMSK, imask);
2177 /* reset PHY Link Detect */
2178 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2179 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2180 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2181 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2186 /* Transmit timeout is only called if we are running, carrier is up
2187 * and tx queue is full (stopped).
2189 static void sky2_tx_timeout(struct net_device *dev)
2191 struct sky2_port *sky2 = netdev_priv(dev);
2192 struct sky2_hw *hw = sky2->hw;
2194 if (netif_msg_timer(sky2))
2195 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2197 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2198 dev->name, sky2->tx_cons, sky2->tx_prod,
2199 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2200 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2202 /* can't restart safely under softirq */
2203 schedule_work(&hw->restart_work);
2206 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2208 struct sky2_port *sky2 = netdev_priv(dev);
2209 struct sky2_hw *hw = sky2->hw;
2210 unsigned port = sky2->port;
2215 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2218 if (new_mtu > ETH_DATA_LEN &&
2219 (hw->chip_id == CHIP_ID_YUKON_FE ||
2220 hw->chip_id == CHIP_ID_YUKON_FE_P))
2223 if (!netif_running(dev)) {
2228 imask = sky2_read32(hw, B0_IMSK);
2229 sky2_write32(hw, B0_IMSK, 0);
2231 dev->trans_start = jiffies; /* prevent tx timeout */
2232 netif_stop_queue(dev);
2233 napi_disable(&hw->napi);
2235 synchronize_irq(hw->pdev->irq);
2237 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2238 sky2_set_tx_stfwd(hw, port);
2240 ctl = gma_read16(hw, port, GM_GP_CTRL);
2241 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2243 sky2_rx_clean(sky2);
2247 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2248 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2250 if (dev->mtu > ETH_DATA_LEN)
2251 mode |= GM_SMOD_JUMBO_ENA;
2253 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2255 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2257 err = sky2_rx_start(sky2);
2258 sky2_write32(hw, B0_IMSK, imask);
2260 sky2_read32(hw, B0_Y2_SP_LISR);
2261 napi_enable(&hw->napi);
2266 gma_write16(hw, port, GM_GP_CTRL, ctl);
2268 netif_wake_queue(dev);
2274 /* For small just reuse existing skb for next receive */
2275 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2276 const struct rx_ring_info *re,
2279 struct sk_buff *skb;
2281 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2283 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2284 length, PCI_DMA_FROMDEVICE);
2285 skb_copy_from_linear_data(re->skb, skb->data, length);
2286 skb->ip_summed = re->skb->ip_summed;
2287 skb->csum = re->skb->csum;
2288 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2289 length, PCI_DMA_FROMDEVICE);
2290 re->skb->ip_summed = CHECKSUM_NONE;
2291 skb_put(skb, length);
2296 /* Adjust length of skb with fragments to match received data */
2297 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2298 unsigned int length)
2303 /* put header into skb */
2304 size = min(length, hdr_space);
2309 num_frags = skb_shinfo(skb)->nr_frags;
2310 for (i = 0; i < num_frags; i++) {
2311 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2314 /* don't need this page */
2315 __free_page(frag->page);
2316 --skb_shinfo(skb)->nr_frags;
2318 size = min(length, (unsigned) PAGE_SIZE);
2321 skb->data_len += size;
2322 skb->truesize += size;
2329 /* Normal packet - take skb from ring element and put in a new one */
2330 static struct sk_buff *receive_new(struct sky2_port *sky2,
2331 struct rx_ring_info *re,
2332 unsigned int length)
2334 struct sk_buff *skb;
2335 struct rx_ring_info nre;
2336 unsigned hdr_space = sky2->rx_data_size;
2338 nre.skb = sky2_rx_alloc(sky2);
2339 if (unlikely(!nre.skb))
2342 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2346 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2347 prefetch(skb->data);
2350 if (skb_shinfo(skb)->nr_frags)
2351 skb_put_frags(skb, hdr_space, length);
2353 skb_put(skb, length);
2357 dev_kfree_skb(nre.skb);
2363 * Receive one packet.
2364 * For larger packets, get new buffer.
2366 static struct sk_buff *sky2_receive(struct net_device *dev,
2367 u16 length, u32 status)
2369 struct sky2_port *sky2 = netdev_priv(dev);
2370 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2371 struct sk_buff *skb = NULL;
2372 u16 count = (status & GMR_FS_LEN) >> 16;
2374 #ifdef SKY2_VLAN_TAG_USED
2375 /* Account for vlan tag */
2376 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2380 if (unlikely(netif_msg_rx_status(sky2)))
2381 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2382 dev->name, sky2->rx_next, status, length);
2384 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2385 prefetch(sky2->rx_ring + sky2->rx_next);
2387 /* This chip has hardware problems that generates bogus status.
2388 * So do only marginal checking and expect higher level protocols
2389 * to handle crap frames.
2391 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2392 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2396 if (status & GMR_FS_ANY_ERR)
2399 if (!(status & GMR_FS_RX_OK))
2402 /* if length reported by DMA does not match PHY, packet was truncated */
2403 if (length != count)
2407 if (length < copybreak)
2408 skb = receive_copy(sky2, re, length);
2410 skb = receive_new(sky2, re, length);
2412 dev->stats.rx_dropped += (skb == NULL);
2415 sky2_rx_submit(sky2, re);
2420 /* Truncation of overlength packets
2421 causes PHY length to not match MAC length */
2422 ++dev->stats.rx_length_errors;
2423 if (netif_msg_rx_err(sky2) && net_ratelimit())
2424 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2425 dev->name, status, length);
2429 ++dev->stats.rx_errors;
2430 if (status & GMR_FS_RX_FF_OV) {
2431 dev->stats.rx_over_errors++;
2435 if (netif_msg_rx_err(sky2) && net_ratelimit())
2436 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2437 dev->name, status, length);
2439 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2440 dev->stats.rx_length_errors++;
2441 if (status & GMR_FS_FRAGMENT)
2442 dev->stats.rx_frame_errors++;
2443 if (status & GMR_FS_CRC_ERR)
2444 dev->stats.rx_crc_errors++;
2449 /* Transmit complete */
2450 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2452 struct sky2_port *sky2 = netdev_priv(dev);
2454 if (netif_running(dev))
2455 sky2_tx_complete(sky2, last);
2458 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2459 u32 status, struct sk_buff *skb)
2461 #ifdef SKY2_VLAN_TAG_USED
2462 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2463 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2464 if (skb->ip_summed == CHECKSUM_NONE)
2465 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2467 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2472 if (skb->ip_summed == CHECKSUM_NONE)
2473 netif_receive_skb(skb);
2475 napi_gro_receive(&sky2->hw->napi, skb);
2478 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2479 unsigned packets, unsigned bytes)
2482 struct net_device *dev = hw->dev[port];
2484 dev->stats.rx_packets += packets;
2485 dev->stats.rx_bytes += bytes;
2486 dev->last_rx = jiffies;
2487 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2491 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2493 /* If this happens then driver assuming wrong format for chip type */
2494 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2496 /* Both checksum counters are programmed to start at
2497 * the same offset, so unless there is a problem they
2498 * should match. This failure is an early indication that
2499 * hardware receive checksumming won't work.
2501 if (likely((u16)(status >> 16) == (u16)status)) {
2502 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2503 skb->ip_summed = CHECKSUM_COMPLETE;
2504 skb->csum = le16_to_cpu(status);
2506 dev_notice(&sky2->hw->pdev->dev,
2507 "%s: receive checksum problem (status = %#x)\n",
2508 sky2->netdev->name, status);
2510 /* Disable checksum offload */
2511 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2512 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2517 /* Process status response ring */
2518 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2521 unsigned int total_bytes[2] = { 0 };
2522 unsigned int total_packets[2] = { 0 };
2526 struct sky2_port *sky2;
2527 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2529 struct net_device *dev;
2530 struct sk_buff *skb;
2533 u8 opcode = le->opcode;
2535 if (!(opcode & HW_OWNER))
2538 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2540 port = le->css & CSS_LINK_BIT;
2541 dev = hw->dev[port];
2542 sky2 = netdev_priv(dev);
2543 length = le16_to_cpu(le->length);
2544 status = le32_to_cpu(le->status);
2547 switch (opcode & ~HW_OWNER) {
2549 total_packets[port]++;
2550 total_bytes[port] += length;
2552 skb = sky2_receive(dev, length, status);
2556 /* This chip reports checksum status differently */
2557 if (hw->flags & SKY2_HW_NEW_LE) {
2558 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
2559 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2560 (le->css & CSS_TCPUDPCSOK))
2561 skb->ip_summed = CHECKSUM_UNNECESSARY;
2563 skb->ip_summed = CHECKSUM_NONE;
2566 skb->protocol = eth_type_trans(skb, dev);
2568 sky2_skb_rx(sky2, status, skb);
2570 /* Stop after net poll weight */
2571 if (++work_done >= to_do)
2575 #ifdef SKY2_VLAN_TAG_USED
2577 sky2->rx_tag = length;
2581 sky2->rx_tag = length;
2585 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2586 sky2_rx_checksum(sky2, status);
2590 /* TX index reports status for both ports */
2591 sky2_tx_done(hw->dev[0], status & 0xfff);
2593 sky2_tx_done(hw->dev[1],
2594 ((status >> 24) & 0xff)
2595 | (u16)(length & 0xf) << 8);
2599 if (net_ratelimit())
2600 printk(KERN_WARNING PFX
2601 "unknown status opcode 0x%x\n", opcode);
2603 } while (hw->st_idx != idx);
2605 /* Fully processed status ring so clear irq */
2606 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2609 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2610 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2615 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2617 struct net_device *dev = hw->dev[port];
2619 if (net_ratelimit())
2620 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2623 if (status & Y2_IS_PAR_RD1) {
2624 if (net_ratelimit())
2625 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2628 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2631 if (status & Y2_IS_PAR_WR1) {
2632 if (net_ratelimit())
2633 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2636 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2639 if (status & Y2_IS_PAR_MAC1) {
2640 if (net_ratelimit())
2641 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2642 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2645 if (status & Y2_IS_PAR_RX1) {
2646 if (net_ratelimit())
2647 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2648 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2651 if (status & Y2_IS_TCP_TXA1) {
2652 if (net_ratelimit())
2653 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2655 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2659 static void sky2_hw_intr(struct sky2_hw *hw)
2661 struct pci_dev *pdev = hw->pdev;
2662 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2663 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2667 if (status & Y2_IS_TIST_OV)
2668 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2670 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2673 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2674 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2675 if (net_ratelimit())
2676 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2679 sky2_pci_write16(hw, PCI_STATUS,
2680 pci_err | PCI_STATUS_ERROR_BITS);
2681 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2684 if (status & Y2_IS_PCI_EXP) {
2685 /* PCI-Express uncorrectable Error occurred */
2688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2689 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2690 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2692 if (net_ratelimit())
2693 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2695 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2696 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2699 if (status & Y2_HWE_L1_MASK)
2700 sky2_hw_error(hw, 0, status);
2702 if (status & Y2_HWE_L1_MASK)
2703 sky2_hw_error(hw, 1, status);
2706 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2708 struct net_device *dev = hw->dev[port];
2709 struct sky2_port *sky2 = netdev_priv(dev);
2710 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2712 if (netif_msg_intr(sky2))
2713 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2716 if (status & GM_IS_RX_CO_OV)
2717 gma_read16(hw, port, GM_RX_IRQ_SRC);
2719 if (status & GM_IS_TX_CO_OV)
2720 gma_read16(hw, port, GM_TX_IRQ_SRC);
2722 if (status & GM_IS_RX_FF_OR) {
2723 ++dev->stats.rx_fifo_errors;
2724 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2727 if (status & GM_IS_TX_FF_UR) {
2728 ++dev->stats.tx_fifo_errors;
2729 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2733 /* This should never happen it is a bug. */
2734 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2736 struct net_device *dev = hw->dev[port];
2737 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2739 dev_err(&hw->pdev->dev, PFX
2740 "%s: descriptor error q=%#x get=%u put=%u\n",
2741 dev->name, (unsigned) q, (unsigned) idx,
2742 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2744 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2747 static int sky2_rx_hung(struct net_device *dev)
2749 struct sky2_port *sky2 = netdev_priv(dev);
2750 struct sky2_hw *hw = sky2->hw;
2751 unsigned port = sky2->port;
2752 unsigned rxq = rxqaddr[port];
2753 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2754 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2755 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2756 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2758 /* If idle and MAC or PCI is stuck */
2759 if (sky2->check.last == dev->last_rx &&
2760 ((mac_rp == sky2->check.mac_rp &&
2761 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2762 /* Check if the PCI RX hang */
2763 (fifo_rp == sky2->check.fifo_rp &&
2764 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2765 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2766 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2767 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2770 sky2->check.last = dev->last_rx;
2771 sky2->check.mac_rp = mac_rp;
2772 sky2->check.mac_lev = mac_lev;
2773 sky2->check.fifo_rp = fifo_rp;
2774 sky2->check.fifo_lev = fifo_lev;
2779 static void sky2_watchdog(unsigned long arg)
2781 struct sky2_hw *hw = (struct sky2_hw *) arg;
2783 /* Check for lost IRQ once a second */
2784 if (sky2_read32(hw, B0_ISRC)) {
2785 napi_schedule(&hw->napi);
2789 for (i = 0; i < hw->ports; i++) {
2790 struct net_device *dev = hw->dev[i];
2791 if (!netif_running(dev))
2795 /* For chips with Rx FIFO, check if stuck */
2796 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2797 sky2_rx_hung(dev)) {
2798 pr_info(PFX "%s: receiver hang detected\n",
2800 schedule_work(&hw->restart_work);
2809 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2812 /* Hardware/software error handling */
2813 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2815 if (net_ratelimit())
2816 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2818 if (status & Y2_IS_HW_ERR)
2821 if (status & Y2_IS_IRQ_MAC1)
2822 sky2_mac_intr(hw, 0);
2824 if (status & Y2_IS_IRQ_MAC2)
2825 sky2_mac_intr(hw, 1);
2827 if (status & Y2_IS_CHK_RX1)
2828 sky2_le_error(hw, 0, Q_R1);
2830 if (status & Y2_IS_CHK_RX2)
2831 sky2_le_error(hw, 1, Q_R2);
2833 if (status & Y2_IS_CHK_TXA1)
2834 sky2_le_error(hw, 0, Q_XA1);
2836 if (status & Y2_IS_CHK_TXA2)
2837 sky2_le_error(hw, 1, Q_XA2);
2840 static int sky2_poll(struct napi_struct *napi, int work_limit)
2842 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2843 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2847 if (unlikely(status & Y2_IS_ERROR))
2848 sky2_err_intr(hw, status);
2850 if (status & Y2_IS_IRQ_PHY1)
2851 sky2_phy_intr(hw, 0);
2853 if (status & Y2_IS_IRQ_PHY2)
2854 sky2_phy_intr(hw, 1);
2856 if (status & Y2_IS_PHY_QLNK)
2857 sky2_qlink_intr(hw);
2859 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2860 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2862 if (work_done >= work_limit)
2866 napi_complete(napi);
2867 sky2_read32(hw, B0_Y2_SP_LISR);
2873 static irqreturn_t sky2_intr(int irq, void *dev_id)
2875 struct sky2_hw *hw = dev_id;
2878 /* Reading this mask interrupts as side effect */
2879 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2880 if (status == 0 || status == ~0)
2883 prefetch(&hw->st_le[hw->st_idx]);
2885 napi_schedule(&hw->napi);
2890 #ifdef CONFIG_NET_POLL_CONTROLLER
2891 static void sky2_netpoll(struct net_device *dev)
2893 struct sky2_port *sky2 = netdev_priv(dev);
2895 napi_schedule(&sky2->hw->napi);
2899 /* Chip internal frequency for clock calculations */
2900 static u32 sky2_mhz(const struct sky2_hw *hw)
2902 switch (hw->chip_id) {
2903 case CHIP_ID_YUKON_EC:
2904 case CHIP_ID_YUKON_EC_U:
2905 case CHIP_ID_YUKON_EX:
2906 case CHIP_ID_YUKON_SUPR:
2907 case CHIP_ID_YUKON_UL_2:
2908 case CHIP_ID_YUKON_OPT:
2911 case CHIP_ID_YUKON_FE:
2914 case CHIP_ID_YUKON_FE_P:
2917 case CHIP_ID_YUKON_XL:
2925 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2927 return sky2_mhz(hw) * us;
2930 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2932 return clk / sky2_mhz(hw);
2936 static int __devinit sky2_init(struct sky2_hw *hw)
2940 /* Enable all clocks and check for bad PCI access */
2941 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2943 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2945 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2946 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2948 switch(hw->chip_id) {
2949 case CHIP_ID_YUKON_XL:
2950 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2953 case CHIP_ID_YUKON_EC_U:
2954 hw->flags = SKY2_HW_GIGABIT
2956 | SKY2_HW_ADV_POWER_CTL;
2959 case CHIP_ID_YUKON_EX:
2960 hw->flags = SKY2_HW_GIGABIT
2963 | SKY2_HW_ADV_POWER_CTL;
2965 /* New transmit checksum */
2966 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2967 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2970 case CHIP_ID_YUKON_EC:
2971 /* This rev is really old, and requires untested workarounds */
2972 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2973 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2976 hw->flags = SKY2_HW_GIGABIT;
2979 case CHIP_ID_YUKON_FE:
2982 case CHIP_ID_YUKON_FE_P:
2983 hw->flags = SKY2_HW_NEWER_PHY
2985 | SKY2_HW_AUTO_TX_SUM
2986 | SKY2_HW_ADV_POWER_CTL;
2989 case CHIP_ID_YUKON_SUPR:
2990 hw->flags = SKY2_HW_GIGABIT
2993 | SKY2_HW_AUTO_TX_SUM
2994 | SKY2_HW_ADV_POWER_CTL;
2997 case CHIP_ID_YUKON_UL_2:
2998 hw->flags = SKY2_HW_GIGABIT
2999 | SKY2_HW_ADV_POWER_CTL;
3002 case CHIP_ID_YUKON_OPT:
3003 hw->flags = SKY2_HW_GIGABIT
3005 | SKY2_HW_ADV_POWER_CTL;
3009 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3014 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3015 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3016 hw->flags |= SKY2_HW_FIBRE_PHY;
3019 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3020 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3021 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3025 if (sky2_read8(hw, B2_E_0))
3026 hw->flags |= SKY2_HW_RAM_BUFFER;
3031 static void sky2_reset(struct sky2_hw *hw)
3033 struct pci_dev *pdev = hw->pdev;
3036 u32 hwe_mask = Y2_HWE_ALL_MASK;
3039 if (hw->chip_id == CHIP_ID_YUKON_EX
3040 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3041 sky2_write32(hw, CPU_WDOG, 0);
3042 status = sky2_read16(hw, HCU_CCSR);
3043 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3044 HCU_CCSR_UC_STATE_MSK);
3046 * CPU clock divider shouldn't be used because
3047 * - ASF firmware may malfunction
3048 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3050 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3051 sky2_write16(hw, HCU_CCSR, status);
3052 sky2_write32(hw, CPU_WDOG, 0);
3054 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3055 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3058 sky2_write8(hw, B0_CTST, CS_RST_SET);
3059 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3061 /* allow writes to PCI config */
3062 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3064 /* clear PCI errors, if any */
3065 status = sky2_pci_read16(hw, PCI_STATUS);
3066 status |= PCI_STATUS_ERROR_BITS;
3067 sky2_pci_write16(hw, PCI_STATUS, status);
3069 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3071 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3073 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3076 /* If error bit is stuck on ignore it */
3077 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3078 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3080 hwe_mask |= Y2_IS_PCI_EXP;
3084 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3086 for (i = 0; i < hw->ports; i++) {
3087 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3088 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3090 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3091 hw->chip_id == CHIP_ID_YUKON_SUPR)
3092 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3093 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3098 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3099 /* enable MACSec clock gating */
3100 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3103 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3107 if (hw->chip_rev == 0) {
3108 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3109 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3111 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3114 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3118 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3120 /* reset PHY Link Detect */
3121 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3122 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3123 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3124 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3127 /* enable PHY Quick Link */
3128 msk = sky2_read32(hw, B0_IMSK);
3129 msk |= Y2_IS_PHY_QLNK;
3130 sky2_write32(hw, B0_IMSK, msk);
3132 /* check if PSMv2 was running before */
3133 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3134 if (reg & PCI_EXP_LNKCTL_ASPMC) {
3135 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3136 /* restore the PCIe Link Control register */
3137 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3139 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3141 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3142 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3145 /* Clear I2C IRQ noise */
3146 sky2_write32(hw, B2_I2C_IRQ, 1);
3148 /* turn off hardware timer (unused) */
3149 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3150 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3152 /* Turn off descriptor polling */
3153 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3155 /* Turn off receive timestamp */
3156 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3157 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3159 /* enable the Tx Arbiters */
3160 for (i = 0; i < hw->ports; i++)
3161 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3163 /* Initialize ram interface */
3164 for (i = 0; i < hw->ports; i++) {
3165 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3167 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3168 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3169 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3170 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3171 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3172 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3173 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3174 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3175 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3176 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3177 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3178 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3181 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3183 for (i = 0; i < hw->ports; i++)
3184 sky2_gmac_reset(hw, i);
3186 memset(hw->st_le, 0, STATUS_LE_BYTES);
3189 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3190 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3192 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3193 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3195 /* Set the list last index */
3196 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3198 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3199 sky2_write8(hw, STAT_FIFO_WM, 16);
3201 /* set Status-FIFO ISR watermark */
3202 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3203 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3205 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3207 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3208 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3209 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3211 /* enable status unit */
3212 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3214 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3215 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3216 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3219 /* Take device down (offline).
3220 * Equivalent to doing dev_stop() but this does not
3221 * inform upper layers of the transistion.
3223 static void sky2_detach(struct net_device *dev)
3225 if (netif_running(dev)) {
3227 netif_device_detach(dev); /* stop txq */
3228 netif_tx_unlock(dev);
3233 /* Bring device back after doing sky2_detach */
3234 static int sky2_reattach(struct net_device *dev)
3238 if (netif_running(dev)) {
3241 printk(KERN_INFO PFX "%s: could not restart %d\n",
3245 netif_device_attach(dev);
3246 sky2_set_multicast(dev);
3253 static void sky2_restart(struct work_struct *work)
3255 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3259 for (i = 0; i < hw->ports; i++)
3260 sky2_detach(hw->dev[i]);
3262 napi_disable(&hw->napi);
3263 sky2_write32(hw, B0_IMSK, 0);
3265 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3266 napi_enable(&hw->napi);
3268 for (i = 0; i < hw->ports; i++)
3269 sky2_reattach(hw->dev[i]);
3274 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3276 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3279 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3281 const struct sky2_port *sky2 = netdev_priv(dev);
3283 wol->supported = sky2_wol_supported(sky2->hw);
3284 wol->wolopts = sky2->wol;
3287 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3289 struct sky2_port *sky2 = netdev_priv(dev);
3290 struct sky2_hw *hw = sky2->hw;
3292 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3293 !device_can_wakeup(&hw->pdev->dev))
3296 sky2->wol = wol->wolopts;
3300 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3302 if (sky2_is_copper(hw)) {
3303 u32 modes = SUPPORTED_10baseT_Half
3304 | SUPPORTED_10baseT_Full
3305 | SUPPORTED_100baseT_Half
3306 | SUPPORTED_100baseT_Full
3307 | SUPPORTED_Autoneg | SUPPORTED_TP;
3309 if (hw->flags & SKY2_HW_GIGABIT)
3310 modes |= SUPPORTED_1000baseT_Half
3311 | SUPPORTED_1000baseT_Full;
3314 return SUPPORTED_1000baseT_Half
3315 | SUPPORTED_1000baseT_Full
3320 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3322 struct sky2_port *sky2 = netdev_priv(dev);
3323 struct sky2_hw *hw = sky2->hw;
3325 ecmd->transceiver = XCVR_INTERNAL;
3326 ecmd->supported = sky2_supported_modes(hw);
3327 ecmd->phy_address = PHY_ADDR_MARV;
3328 if (sky2_is_copper(hw)) {
3329 ecmd->port = PORT_TP;
3330 ecmd->speed = sky2->speed;
3332 ecmd->speed = SPEED_1000;
3333 ecmd->port = PORT_FIBRE;
3336 ecmd->advertising = sky2->advertising;
3337 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3338 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3339 ecmd->duplex = sky2->duplex;
3343 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3345 struct sky2_port *sky2 = netdev_priv(dev);
3346 const struct sky2_hw *hw = sky2->hw;
3347 u32 supported = sky2_supported_modes(hw);
3349 if (ecmd->autoneg == AUTONEG_ENABLE) {
3350 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3351 ecmd->advertising = supported;
3357 switch (ecmd->speed) {
3359 if (ecmd->duplex == DUPLEX_FULL)
3360 setting = SUPPORTED_1000baseT_Full;
3361 else if (ecmd->duplex == DUPLEX_HALF)
3362 setting = SUPPORTED_1000baseT_Half;
3367 if (ecmd->duplex == DUPLEX_FULL)
3368 setting = SUPPORTED_100baseT_Full;
3369 else if (ecmd->duplex == DUPLEX_HALF)
3370 setting = SUPPORTED_100baseT_Half;
3376 if (ecmd->duplex == DUPLEX_FULL)
3377 setting = SUPPORTED_10baseT_Full;
3378 else if (ecmd->duplex == DUPLEX_HALF)
3379 setting = SUPPORTED_10baseT_Half;
3387 if ((setting & supported) == 0)
3390 sky2->speed = ecmd->speed;
3391 sky2->duplex = ecmd->duplex;
3392 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3395 sky2->advertising = ecmd->advertising;
3397 if (netif_running(dev)) {
3398 sky2_phy_reinit(sky2);
3399 sky2_set_multicast(dev);
3405 static void sky2_get_drvinfo(struct net_device *dev,
3406 struct ethtool_drvinfo *info)
3408 struct sky2_port *sky2 = netdev_priv(dev);
3410 strcpy(info->driver, DRV_NAME);
3411 strcpy(info->version, DRV_VERSION);
3412 strcpy(info->fw_version, "N/A");
3413 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3416 static const struct sky2_stat {
3417 char name[ETH_GSTRING_LEN];
3420 { "tx_bytes", GM_TXO_OK_HI },
3421 { "rx_bytes", GM_RXO_OK_HI },
3422 { "tx_broadcast", GM_TXF_BC_OK },
3423 { "rx_broadcast", GM_RXF_BC_OK },
3424 { "tx_multicast", GM_TXF_MC_OK },
3425 { "rx_multicast", GM_RXF_MC_OK },
3426 { "tx_unicast", GM_TXF_UC_OK },
3427 { "rx_unicast", GM_RXF_UC_OK },
3428 { "tx_mac_pause", GM_TXF_MPAUSE },
3429 { "rx_mac_pause", GM_RXF_MPAUSE },
3430 { "collisions", GM_TXF_COL },
3431 { "late_collision",GM_TXF_LAT_COL },
3432 { "aborted", GM_TXF_ABO_COL },
3433 { "single_collisions", GM_TXF_SNG_COL },
3434 { "multi_collisions", GM_TXF_MUL_COL },
3436 { "rx_short", GM_RXF_SHT },
3437 { "rx_runt", GM_RXE_FRAG },
3438 { "rx_64_byte_packets", GM_RXF_64B },
3439 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3440 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3441 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3442 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3443 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3444 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3445 { "rx_too_long", GM_RXF_LNG_ERR },
3446 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3447 { "rx_jabber", GM_RXF_JAB_PKT },
3448 { "rx_fcs_error", GM_RXF_FCS_ERR },
3450 { "tx_64_byte_packets", GM_TXF_64B },
3451 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3452 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3453 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3454 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3455 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3456 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3457 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3460 static u32 sky2_get_rx_csum(struct net_device *dev)
3462 struct sky2_port *sky2 = netdev_priv(dev);
3464 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
3467 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3469 struct sky2_port *sky2 = netdev_priv(dev);
3472 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3474 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
3476 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3477 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3482 static u32 sky2_get_msglevel(struct net_device *netdev)
3484 struct sky2_port *sky2 = netdev_priv(netdev);
3485 return sky2->msg_enable;
3488 static int sky2_nway_reset(struct net_device *dev)
3490 struct sky2_port *sky2 = netdev_priv(dev);
3492 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3495 sky2_phy_reinit(sky2);
3496 sky2_set_multicast(dev);
3501 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3503 struct sky2_hw *hw = sky2->hw;
3504 unsigned port = sky2->port;
3507 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3508 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3509 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3510 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3512 for (i = 2; i < count; i++)
3513 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3516 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3518 struct sky2_port *sky2 = netdev_priv(netdev);
3519 sky2->msg_enable = value;
3522 static int sky2_get_sset_count(struct net_device *dev, int sset)
3526 return ARRAY_SIZE(sky2_stats);
3532 static void sky2_get_ethtool_stats(struct net_device *dev,
3533 struct ethtool_stats *stats, u64 * data)
3535 struct sky2_port *sky2 = netdev_priv(dev);
3537 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3540 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3544 switch (stringset) {
3546 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3547 memcpy(data + i * ETH_GSTRING_LEN,
3548 sky2_stats[i].name, ETH_GSTRING_LEN);
3553 static int sky2_set_mac_address(struct net_device *dev, void *p)
3555 struct sky2_port *sky2 = netdev_priv(dev);
3556 struct sky2_hw *hw = sky2->hw;
3557 unsigned port = sky2->port;
3558 const struct sockaddr *addr = p;
3560 if (!is_valid_ether_addr(addr->sa_data))
3561 return -EADDRNOTAVAIL;
3563 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3564 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3565 dev->dev_addr, ETH_ALEN);
3566 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3567 dev->dev_addr, ETH_ALEN);
3569 /* virtual address for data */
3570 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3572 /* physical address: used for pause frames */
3573 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3578 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3582 bit = ether_crc(ETH_ALEN, addr) & 63;
3583 filter[bit >> 3] |= 1 << (bit & 7);
3586 static void sky2_set_multicast(struct net_device *dev)
3588 struct sky2_port *sky2 = netdev_priv(dev);
3589 struct sky2_hw *hw = sky2->hw;
3590 unsigned port = sky2->port;
3591 struct dev_mc_list *list = dev->mc_list;
3595 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3597 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3598 memset(filter, 0, sizeof(filter));
3600 reg = gma_read16(hw, port, GM_RX_CTRL);
3601 reg |= GM_RXCR_UCF_ENA;
3603 if (dev->flags & IFF_PROMISC) /* promiscuous */
3604 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3605 else if (dev->flags & IFF_ALLMULTI)
3606 memset(filter, 0xff, sizeof(filter));
3607 else if (netdev_mc_empty(dev) && !rx_pause)
3608 reg &= ~GM_RXCR_MCF_ENA;
3611 reg |= GM_RXCR_MCF_ENA;
3614 sky2_add_filter(filter, pause_mc_addr);
3616 for (i = 0; list && i < netdev_mc_count(dev); i++, list = list->next)
3617 sky2_add_filter(filter, list->dmi_addr);
3620 gma_write16(hw, port, GM_MC_ADDR_H1,
3621 (u16) filter[0] | ((u16) filter[1] << 8));
3622 gma_write16(hw, port, GM_MC_ADDR_H2,
3623 (u16) filter[2] | ((u16) filter[3] << 8));
3624 gma_write16(hw, port, GM_MC_ADDR_H3,
3625 (u16) filter[4] | ((u16) filter[5] << 8));
3626 gma_write16(hw, port, GM_MC_ADDR_H4,
3627 (u16) filter[6] | ((u16) filter[7] << 8));
3629 gma_write16(hw, port, GM_RX_CTRL, reg);
3632 /* Can have one global because blinking is controlled by
3633 * ethtool and that is always under RTNL mutex
3635 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3637 struct sky2_hw *hw = sky2->hw;
3638 unsigned port = sky2->port;
3640 spin_lock_bh(&sky2->phy_lock);
3641 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3642 hw->chip_id == CHIP_ID_YUKON_EX ||
3643 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3645 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3646 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3650 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3651 PHY_M_LEDC_LOS_CTRL(8) |
3652 PHY_M_LEDC_INIT_CTRL(8) |
3653 PHY_M_LEDC_STA1_CTRL(8) |
3654 PHY_M_LEDC_STA0_CTRL(8));
3657 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3658 PHY_M_LEDC_LOS_CTRL(9) |
3659 PHY_M_LEDC_INIT_CTRL(9) |
3660 PHY_M_LEDC_STA1_CTRL(9) |
3661 PHY_M_LEDC_STA0_CTRL(9));
3664 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3665 PHY_M_LEDC_LOS_CTRL(0xa) |
3666 PHY_M_LEDC_INIT_CTRL(0xa) |
3667 PHY_M_LEDC_STA1_CTRL(0xa) |
3668 PHY_M_LEDC_STA0_CTRL(0xa));
3671 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3672 PHY_M_LEDC_LOS_CTRL(1) |
3673 PHY_M_LEDC_INIT_CTRL(8) |
3674 PHY_M_LEDC_STA1_CTRL(7) |
3675 PHY_M_LEDC_STA0_CTRL(7));
3678 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3680 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3681 PHY_M_LED_MO_DUP(mode) |
3682 PHY_M_LED_MO_10(mode) |
3683 PHY_M_LED_MO_100(mode) |
3684 PHY_M_LED_MO_1000(mode) |
3685 PHY_M_LED_MO_RX(mode) |
3686 PHY_M_LED_MO_TX(mode));
3688 spin_unlock_bh(&sky2->phy_lock);
3691 /* blink LED's for finding board */
3692 static int sky2_phys_id(struct net_device *dev, u32 data)
3694 struct sky2_port *sky2 = netdev_priv(dev);
3700 for (i = 0; i < data; i++) {
3701 sky2_led(sky2, MO_LED_ON);
3702 if (msleep_interruptible(500))
3704 sky2_led(sky2, MO_LED_OFF);
3705 if (msleep_interruptible(500))
3708 sky2_led(sky2, MO_LED_NORM);
3713 static void sky2_get_pauseparam(struct net_device *dev,
3714 struct ethtool_pauseparam *ecmd)
3716 struct sky2_port *sky2 = netdev_priv(dev);
3718 switch (sky2->flow_mode) {
3720 ecmd->tx_pause = ecmd->rx_pause = 0;
3723 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3726 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3729 ecmd->tx_pause = ecmd->rx_pause = 1;
3732 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3733 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3736 static int sky2_set_pauseparam(struct net_device *dev,
3737 struct ethtool_pauseparam *ecmd)
3739 struct sky2_port *sky2 = netdev_priv(dev);
3741 if (ecmd->autoneg == AUTONEG_ENABLE)
3742 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3744 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3746 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3748 if (netif_running(dev))
3749 sky2_phy_reinit(sky2);
3754 static int sky2_get_coalesce(struct net_device *dev,
3755 struct ethtool_coalesce *ecmd)
3757 struct sky2_port *sky2 = netdev_priv(dev);
3758 struct sky2_hw *hw = sky2->hw;
3760 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3761 ecmd->tx_coalesce_usecs = 0;
3763 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3764 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3766 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3768 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3769 ecmd->rx_coalesce_usecs = 0;
3771 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3772 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3774 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3776 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3777 ecmd->rx_coalesce_usecs_irq = 0;
3779 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3780 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3783 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3788 /* Note: this affect both ports */
3789 static int sky2_set_coalesce(struct net_device *dev,
3790 struct ethtool_coalesce *ecmd)
3792 struct sky2_port *sky2 = netdev_priv(dev);
3793 struct sky2_hw *hw = sky2->hw;
3794 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3796 if (ecmd->tx_coalesce_usecs > tmax ||
3797 ecmd->rx_coalesce_usecs > tmax ||
3798 ecmd->rx_coalesce_usecs_irq > tmax)
3801 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3803 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3805 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3808 if (ecmd->tx_coalesce_usecs == 0)
3809 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3811 sky2_write32(hw, STAT_TX_TIMER_INI,
3812 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3813 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3815 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3817 if (ecmd->rx_coalesce_usecs == 0)
3818 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3820 sky2_write32(hw, STAT_LEV_TIMER_INI,
3821 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3822 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3824 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3826 if (ecmd->rx_coalesce_usecs_irq == 0)
3827 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3829 sky2_write32(hw, STAT_ISR_TIMER_INI,
3830 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3831 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3833 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3837 static void sky2_get_ringparam(struct net_device *dev,
3838 struct ethtool_ringparam *ering)
3840 struct sky2_port *sky2 = netdev_priv(dev);
3842 ering->rx_max_pending = RX_MAX_PENDING;
3843 ering->rx_mini_max_pending = 0;
3844 ering->rx_jumbo_max_pending = 0;
3845 ering->tx_max_pending = TX_MAX_PENDING;
3847 ering->rx_pending = sky2->rx_pending;
3848 ering->rx_mini_pending = 0;
3849 ering->rx_jumbo_pending = 0;
3850 ering->tx_pending = sky2->tx_pending;
3853 static int sky2_set_ringparam(struct net_device *dev,
3854 struct ethtool_ringparam *ering)
3856 struct sky2_port *sky2 = netdev_priv(dev);
3858 if (ering->rx_pending > RX_MAX_PENDING ||
3859 ering->rx_pending < 8 ||
3860 ering->tx_pending < TX_MIN_PENDING ||
3861 ering->tx_pending > TX_MAX_PENDING)
3866 sky2->rx_pending = ering->rx_pending;
3867 sky2->tx_pending = ering->tx_pending;
3868 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
3870 return sky2_reattach(dev);
3873 static int sky2_get_regs_len(struct net_device *dev)
3878 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3880 /* This complicated switch statement is to make sure and
3881 * only access regions that are unreserved.
3882 * Some blocks are only valid on dual port cards.
3886 case 5: /* Tx Arbiter 2 */
3888 case 14 ... 15: /* TX2 */
3889 case 17: case 19: /* Ram Buffer 2 */
3890 case 22 ... 23: /* Tx Ram Buffer 2 */
3891 case 25: /* Rx MAC Fifo 1 */
3892 case 27: /* Tx MAC Fifo 2 */
3893 case 31: /* GPHY 2 */
3894 case 40 ... 47: /* Pattern Ram 2 */
3895 case 52: case 54: /* TCP Segmentation 2 */
3896 case 112 ... 116: /* GMAC 2 */
3897 return hw->ports > 1;
3899 case 0: /* Control */
3900 case 2: /* Mac address */
3901 case 4: /* Tx Arbiter 1 */
3902 case 7: /* PCI express reg */
3904 case 12 ... 13: /* TX1 */
3905 case 16: case 18:/* Rx Ram Buffer 1 */
3906 case 20 ... 21: /* Tx Ram Buffer 1 */
3907 case 24: /* Rx MAC Fifo 1 */
3908 case 26: /* Tx MAC Fifo 1 */
3909 case 28 ... 29: /* Descriptor and status unit */
3910 case 30: /* GPHY 1*/
3911 case 32 ... 39: /* Pattern Ram 1 */
3912 case 48: case 50: /* TCP Segmentation 1 */
3913 case 56 ... 60: /* PCI space */
3914 case 80 ... 84: /* GMAC 1 */
3923 * Returns copy of control register region
3924 * Note: ethtool_get_regs always provides full size (16k) buffer
3926 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3929 const struct sky2_port *sky2 = netdev_priv(dev);
3930 const void __iomem *io = sky2->hw->regs;
3935 for (b = 0; b < 128; b++) {
3936 /* skip poisonous diagnostic ram region in block 3 */
3938 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3939 else if (sky2_reg_access_ok(sky2->hw, b))
3940 memcpy_fromio(p, io, 128);
3949 /* In order to do Jumbo packets on these chips, need to turn off the
3950 * transmit store/forward. Therefore checksum offload won't work.
3952 static int no_tx_offload(struct net_device *dev)
3954 const struct sky2_port *sky2 = netdev_priv(dev);
3955 const struct sky2_hw *hw = sky2->hw;
3957 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3960 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3962 if (data && no_tx_offload(dev))
3965 return ethtool_op_set_tx_csum(dev, data);
3969 static int sky2_set_tso(struct net_device *dev, u32 data)
3971 if (data && no_tx_offload(dev))
3974 return ethtool_op_set_tso(dev, data);
3977 static int sky2_get_eeprom_len(struct net_device *dev)
3979 struct sky2_port *sky2 = netdev_priv(dev);
3980 struct sky2_hw *hw = sky2->hw;
3983 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3984 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3987 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
3989 unsigned long start = jiffies;
3991 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3992 /* Can take up to 10.6 ms for write */
3993 if (time_after(jiffies, start + HZ/4)) {
3994 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
4003 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4004 u16 offset, size_t length)
4008 while (length > 0) {
4011 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4012 rc = sky2_vpd_wait(hw, cap, 0);
4016 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4018 memcpy(data, &val, min(sizeof(val), length));
4019 offset += sizeof(u32);
4020 data += sizeof(u32);
4021 length -= sizeof(u32);
4027 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4028 u16 offset, unsigned int length)
4033 for (i = 0; i < length; i += sizeof(u32)) {
4034 u32 val = *(u32 *)(data + i);
4036 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4037 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4039 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4046 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4049 struct sky2_port *sky2 = netdev_priv(dev);
4050 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4055 eeprom->magic = SKY2_EEPROM_MAGIC;
4057 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4060 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4063 struct sky2_port *sky2 = netdev_priv(dev);
4064 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4069 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4072 /* Partial writes not supported */
4073 if ((eeprom->offset & 3) || (eeprom->len & 3))
4076 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4080 static const struct ethtool_ops sky2_ethtool_ops = {
4081 .get_settings = sky2_get_settings,
4082 .set_settings = sky2_set_settings,
4083 .get_drvinfo = sky2_get_drvinfo,
4084 .get_wol = sky2_get_wol,
4085 .set_wol = sky2_set_wol,
4086 .get_msglevel = sky2_get_msglevel,
4087 .set_msglevel = sky2_set_msglevel,
4088 .nway_reset = sky2_nway_reset,
4089 .get_regs_len = sky2_get_regs_len,
4090 .get_regs = sky2_get_regs,
4091 .get_link = ethtool_op_get_link,
4092 .get_eeprom_len = sky2_get_eeprom_len,
4093 .get_eeprom = sky2_get_eeprom,
4094 .set_eeprom = sky2_set_eeprom,
4095 .set_sg = ethtool_op_set_sg,
4096 .set_tx_csum = sky2_set_tx_csum,
4097 .set_tso = sky2_set_tso,
4098 .get_rx_csum = sky2_get_rx_csum,
4099 .set_rx_csum = sky2_set_rx_csum,
4100 .get_strings = sky2_get_strings,
4101 .get_coalesce = sky2_get_coalesce,
4102 .set_coalesce = sky2_set_coalesce,
4103 .get_ringparam = sky2_get_ringparam,
4104 .set_ringparam = sky2_set_ringparam,
4105 .get_pauseparam = sky2_get_pauseparam,
4106 .set_pauseparam = sky2_set_pauseparam,
4107 .phys_id = sky2_phys_id,
4108 .get_sset_count = sky2_get_sset_count,
4109 .get_ethtool_stats = sky2_get_ethtool_stats,
4112 #ifdef CONFIG_SKY2_DEBUG
4114 static struct dentry *sky2_debug;
4118 * Read and parse the first part of Vital Product Data
4120 #define VPD_SIZE 128
4121 #define VPD_MAGIC 0x82
4123 static const struct vpd_tag {
4127 { "PN", "Part Number" },
4128 { "EC", "Engineering Level" },
4129 { "MN", "Manufacturer" },
4130 { "SN", "Serial Number" },
4131 { "YA", "Asset Tag" },
4132 { "VL", "First Error Log Message" },
4133 { "VF", "Second Error Log Message" },
4134 { "VB", "Boot Agent ROM Configuration" },
4135 { "VE", "EFI UNDI Configuration" },
4138 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4146 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4147 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4149 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4150 buf = kmalloc(vpd_size, GFP_KERNEL);
4152 seq_puts(seq, "no memory!\n");
4156 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4157 seq_puts(seq, "VPD read failed\n");
4161 if (buf[0] != VPD_MAGIC) {
4162 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4166 if (len == 0 || len > vpd_size - 4) {
4167 seq_printf(seq, "Invalid id length: %d\n", len);
4171 seq_printf(seq, "%.*s\n", len, buf + 3);
4174 while (offs < vpd_size - 4) {
4177 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4179 len = buf[offs + 2];
4180 if (offs + len + 3 >= vpd_size)
4183 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4184 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4185 seq_printf(seq, " %s: %.*s\n",
4186 vpd_tags[i].label, len, buf + offs + 3);
4196 static int sky2_debug_show(struct seq_file *seq, void *v)
4198 struct net_device *dev = seq->private;
4199 const struct sky2_port *sky2 = netdev_priv(dev);
4200 struct sky2_hw *hw = sky2->hw;
4201 unsigned port = sky2->port;
4205 sky2_show_vpd(seq, hw);
4207 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4208 sky2_read32(hw, B0_ISRC),
4209 sky2_read32(hw, B0_IMSK),
4210 sky2_read32(hw, B0_Y2_SP_ICR));
4212 if (!netif_running(dev)) {
4213 seq_printf(seq, "network not running\n");
4217 napi_disable(&hw->napi);
4218 last = sky2_read16(hw, STAT_PUT_IDX);
4220 if (hw->st_idx == last)
4221 seq_puts(seq, "Status ring (empty)\n");
4223 seq_puts(seq, "Status ring\n");
4224 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4225 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4226 const struct sky2_status_le *le = hw->st_le + idx;
4227 seq_printf(seq, "[%d] %#x %d %#x\n",
4228 idx, le->opcode, le->length, le->status);
4230 seq_puts(seq, "\n");
4233 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4234 sky2->tx_cons, sky2->tx_prod,
4235 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4236 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4238 /* Dump contents of tx ring */
4240 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4241 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4242 const struct sky2_tx_le *le = sky2->tx_le + idx;
4243 u32 a = le32_to_cpu(le->addr);
4246 seq_printf(seq, "%u:", idx);
4249 switch(le->opcode & ~HW_OWNER) {
4251 seq_printf(seq, " %#x:", a);
4254 seq_printf(seq, " mtu=%d", a);
4257 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4260 seq_printf(seq, " csum=%#x", a);
4263 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4266 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4269 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4272 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4273 a, le16_to_cpu(le->length));
4276 if (le->ctrl & EOP) {
4277 seq_putc(seq, '\n');
4282 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4283 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4284 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4285 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4287 sky2_read32(hw, B0_Y2_SP_LISR);
4288 napi_enable(&hw->napi);
4292 static int sky2_debug_open(struct inode *inode, struct file *file)
4294 return single_open(file, sky2_debug_show, inode->i_private);
4297 static const struct file_operations sky2_debug_fops = {
4298 .owner = THIS_MODULE,
4299 .open = sky2_debug_open,
4301 .llseek = seq_lseek,
4302 .release = single_release,
4306 * Use network device events to create/remove/rename
4307 * debugfs file entries
4309 static int sky2_device_event(struct notifier_block *unused,
4310 unsigned long event, void *ptr)
4312 struct net_device *dev = ptr;
4313 struct sky2_port *sky2 = netdev_priv(dev);
4315 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4319 case NETDEV_CHANGENAME:
4320 if (sky2->debugfs) {
4321 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4322 sky2_debug, dev->name);
4326 case NETDEV_GOING_DOWN:
4327 if (sky2->debugfs) {
4328 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4330 debugfs_remove(sky2->debugfs);
4331 sky2->debugfs = NULL;
4336 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4339 if (IS_ERR(sky2->debugfs))
4340 sky2->debugfs = NULL;
4346 static struct notifier_block sky2_notifier = {
4347 .notifier_call = sky2_device_event,
4351 static __init void sky2_debug_init(void)
4355 ent = debugfs_create_dir("sky2", NULL);
4356 if (!ent || IS_ERR(ent))
4360 register_netdevice_notifier(&sky2_notifier);
4363 static __exit void sky2_debug_cleanup(void)
4366 unregister_netdevice_notifier(&sky2_notifier);
4367 debugfs_remove(sky2_debug);
4373 #define sky2_debug_init()
4374 #define sky2_debug_cleanup()
4377 /* Two copies of network device operations to handle special case of
4378 not allowing netpoll on second port */
4379 static const struct net_device_ops sky2_netdev_ops[2] = {
4381 .ndo_open = sky2_up,
4382 .ndo_stop = sky2_down,
4383 .ndo_start_xmit = sky2_xmit_frame,
4384 .ndo_do_ioctl = sky2_ioctl,
4385 .ndo_validate_addr = eth_validate_addr,
4386 .ndo_set_mac_address = sky2_set_mac_address,
4387 .ndo_set_multicast_list = sky2_set_multicast,
4388 .ndo_change_mtu = sky2_change_mtu,
4389 .ndo_tx_timeout = sky2_tx_timeout,
4390 #ifdef SKY2_VLAN_TAG_USED
4391 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4393 #ifdef CONFIG_NET_POLL_CONTROLLER
4394 .ndo_poll_controller = sky2_netpoll,
4398 .ndo_open = sky2_up,
4399 .ndo_stop = sky2_down,
4400 .ndo_start_xmit = sky2_xmit_frame,
4401 .ndo_do_ioctl = sky2_ioctl,
4402 .ndo_validate_addr = eth_validate_addr,
4403 .ndo_set_mac_address = sky2_set_mac_address,
4404 .ndo_set_multicast_list = sky2_set_multicast,
4405 .ndo_change_mtu = sky2_change_mtu,
4406 .ndo_tx_timeout = sky2_tx_timeout,
4407 #ifdef SKY2_VLAN_TAG_USED
4408 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4413 /* Initialize network device */
4414 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4416 int highmem, int wol)
4418 struct sky2_port *sky2;
4419 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4422 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4426 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4427 dev->irq = hw->pdev->irq;
4428 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4429 dev->watchdog_timeo = TX_WATCHDOG;
4430 dev->netdev_ops = &sky2_netdev_ops[port];
4432 sky2 = netdev_priv(dev);
4435 sky2->msg_enable = netif_msg_init(debug, default_msg);
4437 /* Auto speed and flow control */
4438 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4439 if (hw->chip_id != CHIP_ID_YUKON_XL)
4440 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4442 sky2->flow_mode = FC_BOTH;
4446 sky2->advertising = sky2_supported_modes(hw);
4449 spin_lock_init(&sky2->phy_lock);
4451 sky2->tx_pending = TX_DEF_PENDING;
4452 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4453 sky2->rx_pending = RX_DEF_PENDING;
4455 hw->dev[port] = dev;
4459 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4461 dev->features |= NETIF_F_HIGHDMA;
4463 #ifdef SKY2_VLAN_TAG_USED
4464 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4465 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4466 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4467 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4471 /* read the mac address */
4472 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4473 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4478 static void __devinit sky2_show_addr(struct net_device *dev)
4480 const struct sky2_port *sky2 = netdev_priv(dev);
4482 if (netif_msg_probe(sky2))
4483 printk(KERN_INFO PFX "%s: addr %pM\n",
4484 dev->name, dev->dev_addr);
4487 /* Handle software interrupt used during MSI test */
4488 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4490 struct sky2_hw *hw = dev_id;
4491 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4496 if (status & Y2_IS_IRQ_SW) {
4497 hw->flags |= SKY2_HW_USE_MSI;
4498 wake_up(&hw->msi_wait);
4499 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4501 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4506 /* Test interrupt path by forcing a a software IRQ */
4507 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4509 struct pci_dev *pdev = hw->pdev;
4512 init_waitqueue_head (&hw->msi_wait);
4514 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4516 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4518 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4522 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4523 sky2_read8(hw, B0_CTST);
4525 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4527 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4528 /* MSI test failed, go back to INTx mode */
4529 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4530 "switching to INTx mode.\n");
4533 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4536 sky2_write32(hw, B0_IMSK, 0);
4537 sky2_read32(hw, B0_IMSK);
4539 free_irq(pdev->irq, hw);
4544 /* This driver supports yukon2 chipset only */
4545 static const char *sky2_name(u8 chipid, char *buf, int sz)
4547 const char *name[] = {
4549 "EC Ultra", /* 0xb4 */
4550 "Extreme", /* 0xb5 */
4554 "Supreme", /* 0xb9 */
4556 "Unknown", /* 0xbb */
4557 "Optima", /* 0xbc */
4560 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
4561 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4563 snprintf(buf, sz, "(chip %#x)", chipid);
4567 static int __devinit sky2_probe(struct pci_dev *pdev,
4568 const struct pci_device_id *ent)
4570 struct net_device *dev;
4572 int err, using_dac = 0, wol_default;
4576 err = pci_enable_device(pdev);
4578 dev_err(&pdev->dev, "cannot enable PCI device\n");
4582 /* Get configuration information
4583 * Note: only regular PCI config access once to test for HW issues
4584 * other PCI access through shared memory for speed and to
4585 * avoid MMCONFIG problems.
4587 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4589 dev_err(&pdev->dev, "PCI read config failed\n");
4594 dev_err(&pdev->dev, "PCI configuration read error\n");
4598 err = pci_request_regions(pdev, DRV_NAME);
4600 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4601 goto err_out_disable;
4604 pci_set_master(pdev);
4606 if (sizeof(dma_addr_t) > sizeof(u32) &&
4607 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4609 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4611 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4612 "for consistent allocations\n");
4613 goto err_out_free_regions;
4616 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4618 dev_err(&pdev->dev, "no usable DMA configuration\n");
4619 goto err_out_free_regions;
4625 /* The sk98lin vendor driver uses hardware byte swapping but
4626 * this driver uses software swapping.
4628 reg &= ~PCI_REV_DESC;
4629 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4631 dev_err(&pdev->dev, "PCI write config failed\n");
4632 goto err_out_free_regions;
4636 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4640 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4641 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4643 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4644 goto err_out_free_regions;
4648 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4650 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4652 dev_err(&pdev->dev, "cannot map device registers\n");
4653 goto err_out_free_hw;
4656 /* ring for status responses */
4657 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4659 goto err_out_iounmap;
4661 err = sky2_init(hw);
4663 goto err_out_iounmap;
4665 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4666 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4670 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4673 goto err_out_free_pci;
4676 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4677 err = sky2_test_msi(hw);
4678 if (err == -EOPNOTSUPP)
4679 pci_disable_msi(pdev);
4681 goto err_out_free_netdev;
4684 err = register_netdev(dev);
4686 dev_err(&pdev->dev, "cannot register net device\n");
4687 goto err_out_free_netdev;
4690 netif_carrier_off(dev);
4692 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4694 err = request_irq(pdev->irq, sky2_intr,
4695 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4698 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4699 goto err_out_unregister;
4701 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4702 napi_enable(&hw->napi);
4704 sky2_show_addr(dev);
4706 if (hw->ports > 1) {
4707 struct net_device *dev1;
4710 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4711 if (dev1 && (err = register_netdev(dev1)) == 0)
4712 sky2_show_addr(dev1);
4714 dev_warn(&pdev->dev,
4715 "register of second port failed (%d)\n", err);
4723 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4724 INIT_WORK(&hw->restart_work, sky2_restart);
4726 pci_set_drvdata(pdev, hw);
4727 pdev->d3_delay = 150;
4732 if (hw->flags & SKY2_HW_USE_MSI)
4733 pci_disable_msi(pdev);
4734 unregister_netdev(dev);
4735 err_out_free_netdev:
4738 sky2_write8(hw, B0_CTST, CS_RST_SET);
4739 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4744 err_out_free_regions:
4745 pci_release_regions(pdev);
4747 pci_disable_device(pdev);
4749 pci_set_drvdata(pdev, NULL);
4753 static void __devexit sky2_remove(struct pci_dev *pdev)
4755 struct sky2_hw *hw = pci_get_drvdata(pdev);
4761 del_timer_sync(&hw->watchdog_timer);
4762 cancel_work_sync(&hw->restart_work);
4764 for (i = hw->ports-1; i >= 0; --i)
4765 unregister_netdev(hw->dev[i]);
4767 sky2_write32(hw, B0_IMSK, 0);
4771 sky2_write8(hw, B0_CTST, CS_RST_SET);
4772 sky2_read8(hw, B0_CTST);
4774 free_irq(pdev->irq, hw);
4775 if (hw->flags & SKY2_HW_USE_MSI)
4776 pci_disable_msi(pdev);
4777 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4778 pci_release_regions(pdev);
4779 pci_disable_device(pdev);
4781 for (i = hw->ports-1; i >= 0; --i)
4782 free_netdev(hw->dev[i]);
4787 pci_set_drvdata(pdev, NULL);
4790 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4792 struct sky2_hw *hw = pci_get_drvdata(pdev);
4798 del_timer_sync(&hw->watchdog_timer);
4799 cancel_work_sync(&hw->restart_work);
4802 for (i = 0; i < hw->ports; i++) {
4803 struct net_device *dev = hw->dev[i];
4804 struct sky2_port *sky2 = netdev_priv(dev);
4809 sky2_wol_init(sky2);
4814 device_set_wakeup_enable(&pdev->dev, wol != 0);
4816 sky2_write32(hw, B0_IMSK, 0);
4817 napi_disable(&hw->napi);
4821 pci_save_state(pdev);
4822 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4823 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4829 static int sky2_resume(struct pci_dev *pdev)
4831 struct sky2_hw *hw = pci_get_drvdata(pdev);
4837 err = pci_set_power_state(pdev, PCI_D0);
4841 err = pci_restore_state(pdev);
4845 pci_enable_wake(pdev, PCI_D0, 0);
4847 /* Re-enable all clocks */
4848 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4850 dev_err(&pdev->dev, "PCI write config failed\n");
4855 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4856 napi_enable(&hw->napi);
4859 for (i = 0; i < hw->ports; i++) {
4860 err = sky2_reattach(hw->dev[i]);
4870 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4871 pci_disable_device(pdev);
4876 static void sky2_shutdown(struct pci_dev *pdev)
4878 sky2_suspend(pdev, PMSG_SUSPEND);
4881 static struct pci_driver sky2_driver = {
4883 .id_table = sky2_id_table,
4884 .probe = sky2_probe,
4885 .remove = __devexit_p(sky2_remove),
4887 .suspend = sky2_suspend,
4888 .resume = sky2_resume,
4890 .shutdown = sky2_shutdown,
4893 static int __init sky2_init_module(void)
4895 pr_info(PFX "driver version " DRV_VERSION "\n");
4898 return pci_register_driver(&sky2_driver);
4901 static void __exit sky2_cleanup_module(void)
4903 pci_unregister_driver(&sky2_driver);
4904 sky2_debug_cleanup();
4907 module_init(sky2_init_module);
4908 module_exit(sky2_cleanup_module);
4910 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4911 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4912 MODULE_LICENSE("GPL");
4913 MODULE_VERSION(DRV_VERSION);