1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * sh_eth.h - Driver for Renesas SuperH ethernet controller.
5 * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
6 * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
7 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
11 #include <asm/types.h>
13 #define SHETHER_NAME "sh_eth"
15 #if defined(CONFIG_SH)
16 /* Malloc returns addresses in the P1 area (cacheable). However we need to
17 use area P2 (non-cacheable) */
18 #define ADDR_TO_P2(addr) ((((uintptr_t)(addr) & ~0xe0000000) | 0xa0000000))
20 /* The ethernet controller needs to use physical addresses */
21 #define ADDR_TO_PHY(addr) ((uintptr_t)(addr) & ~0xe0000000)
22 #elif defined(CONFIG_ARM)
27 #define ADDR_TO_PHY(addr) ((uintptr_t)(addr))
28 #define ADDR_TO_P2(addr) (addr)
29 #endif /* defined(CONFIG_SH) */
31 /* base padding size is 16 */
32 #ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
33 #define CONFIG_SH_ETHER_ALIGNE_SIZE 16
36 /* Number of supported ports */
37 #define MAX_PORT_NUM 2
39 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx
40 buffers must be a multiple of 32 bytes */
41 #define MAX_BUF_SIZE (48 * 32)
43 /* The number of tx descriptors must be large enough to point to 5 or more
44 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
45 We use one descriptor per frame */
48 /* The size of the tx descriptor is determined by how much padding is used.
49 4, 20, or 52 bytes of padding can be used */
50 #define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
52 /* Tx descriptor. We always use 3 bytes of padding */
56 u32 td2; /* Buffer start */
57 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
60 /* There is no limitation in the number of rx descriptors */
63 /* The size of the rx descriptor is determined by how much padding is used.
64 4, 20, or 52 bytes of padding can be used */
65 #define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
66 /* aligned cache line size */
67 #define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
69 /* Rx descriptor. We always use 4 bytes of padding */
73 u32 rd2; /* Buffer start */
74 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
78 struct tx_desc_s *tx_desc_alloc;
79 struct tx_desc_s *tx_desc_base;
80 struct tx_desc_s *tx_desc_cur;
81 struct rx_desc_s *rx_desc_alloc;
82 struct rx_desc_s *rx_desc_base;
83 struct rx_desc_s *rx_desc_cur;
88 struct eth_device *dev;
89 struct phy_device *phydev;
95 struct sh_eth_info port_info[MAX_PORT_NUM];
98 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */
100 /* E-DMAC registers */
129 /* Ether registers */
163 RMIIMR, /* R8A7790 */
169 /* This value must be written at last. */
170 SH_ETH_MAX_REGISTER_OFFSET,
173 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
227 static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
281 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
334 /* Register Address */
335 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
336 #define SH_ETH_TYPE_GETHER
337 #define BASE_IO_ADDR 0xfee00000
338 #elif defined(CONFIG_CPU_SH7757) || \
339 defined(CONFIG_CPU_SH7752) || \
340 defined(CONFIG_CPU_SH7753)
341 #if defined(CONFIG_SH_ETHER_USE_GETHER)
342 #define SH_ETH_TYPE_GETHER
343 #define BASE_IO_ADDR 0xfee00000
345 #define SH_ETH_TYPE_ETHER
346 #define BASE_IO_ADDR 0xfef00000
348 #elif defined(CONFIG_R8A7740)
349 #define SH_ETH_TYPE_GETHER
350 #define BASE_IO_ADDR 0xE9A00000
351 #elif defined(CONFIG_RCAR_GEN2)
352 #define SH_ETH_TYPE_ETHER
353 #define BASE_IO_ADDR 0xEE700200
354 #elif defined(CONFIG_R7S72100)
355 #define SH_ETH_TYPE_RZ
356 #define BASE_IO_ADDR 0xE8203000
357 #elif defined(CONFIG_R8A77980)
358 #define SH_ETH_TYPE_GETHER
359 #define BASE_IO_ADDR 0xE7400000
364 * Copy from Linux driver source code
366 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
369 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
371 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
376 EDMR_NBST = 0x80, /* DMA transfer burst mode */
377 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
378 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
379 EDMR_SRST = 0x03, /* Receive/Send reset */
380 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
381 EDMR_EL = 0x40, /* Litte endian */
382 #elif defined(SH_ETH_TYPE_ETHER)
384 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
385 EDMR_EL = 0x40, /* Litte endian */
391 #if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
392 # define EMDR_DESC EDMR_DL1
393 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
394 # define EMDR_DESC EDMR_DL0
395 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
400 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
404 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
413 #if defined(CONFIG_CPU_SH7757) || \
414 defined(CONFIG_CPU_SH7752) || \
415 defined(CONFIG_CPU_SH7753)
416 GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
418 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
429 TPAUSER_TPAUSE = 0x0000ffff,
430 TPAUSER_UNLIMITED = 0,
435 BCFR_RPAUSE = 0x0000ffff,
441 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
445 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
449 #if defined(SH_ETH_TYPE_ETHER)
450 EESR_TWB = 0x40000000,
452 EESR_TWB = 0xC0000000,
453 EESR_TC1 = 0x20000000,
454 EESR_TUC = 0x10000000,
455 EESR_ROC = 0x80000000,
457 EESR_TABT = 0x04000000,
458 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
459 #if defined(SH_ETH_TYPE_ETHER)
460 EESR_ADE = 0x00800000,
462 EESR_ECI = 0x00400000,
463 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
464 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
465 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
466 #if defined(SH_ETH_TYPE_ETHER)
467 EESR_CND = 0x00000800,
469 EESR_DLC = 0x00000400,
470 EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
471 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
472 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
473 EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
474 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
478 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
479 # define TX_CHECK (EESR_TC1 | EESR_FTC)
480 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
481 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
482 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
485 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
486 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
487 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
488 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
493 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
494 DMAC_M_RABT = 0x02000000,
495 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
496 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
497 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
498 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
499 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
500 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
501 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
502 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
503 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
504 DMAC_M_RINT1 = 0x00000001,
507 /* Receive descriptor bit */
509 RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
510 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
511 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
512 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
513 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
514 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
515 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
516 RD_RFS1 = 0x00000001,
518 #define RDF1ST RD_RFP1
519 #define RDFEND RD_RFP0
520 #define RD_RFP (RD_RFP1|RD_RFP0)
529 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
530 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
531 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
533 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
534 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
536 /* Transfer descriptor bit */
538 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
539 defined(SH_ETH_TYPE_RZ)
540 TD_TACT = 0x80000000,
542 TD_TACT = 0x7fffffff,
544 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
545 TD_TFP0 = 0x10000000,
547 #define TDF1ST TD_TFP1
548 #define TDFEND TD_TFP0
549 #define TD_TFP (TD_TFP1|TD_TFP0)
552 enum RECV_RST_BIT { RMCR_RST = 0x01, };
554 enum FELIC_MODE_BIT {
555 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
556 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
557 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
559 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
560 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
561 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
562 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
563 ECMR_PRM = 0x00000001,
564 #ifdef CONFIG_CPU_SH7724
565 ECMR_RTM = 0x00000010,
566 #elif defined(CONFIG_RCAR_GEN2) || defined (CONFIG_R8A77980)
567 ECMR_RTM = 0x00000004,
572 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
573 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
574 ECMR_RXF | ECMR_TXF | ECMR_MCT)
575 #elif defined(SH_ETH_TYPE_ETHER)
576 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
578 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
582 enum ECSR_STATUS_BIT {
583 #if defined(SH_ETH_TYPE_ETHER)
584 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
587 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
590 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
591 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
593 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
594 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
598 enum ECSIPR_STATUS_MASK_BIT {
599 #if defined(SH_ETH_TYPE_ETHER)
600 ECSIPR_BRCRXIP = 0x20,
601 ECSIPR_PSRTOIP = 0x10,
602 #elif defined(SH_ETY_TYPE_GETHER)
603 ECSIPR_PSRTOIP = 0x10,
606 ECSIPR_LCHNGIP = 0x04,
611 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
612 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
614 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
615 ECSIPR_ICDIP | ECSIPR_MPDIP)
630 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
631 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
632 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
633 DESC_I_RINT1 = 0x0001,
638 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
639 RPADIR_PADR = 0x0003f,
642 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
643 # define RPADIR_INIT (0x00)
645 # define RPADIR_INIT (RPADIR_PADS1)
650 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
653 static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
656 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
657 const u16 *reg_offset = sh_eth_offset_gigabit;
658 #elif defined(SH_ETH_TYPE_ETHER)
659 const u16 *reg_offset = sh_eth_offset_fast_sh4;
660 #elif defined(SH_ETH_TYPE_RZ)
661 const u16 *reg_offset = sh_eth_offset_rz;
665 return (unsigned long)port->iobase + reg_offset[enum_index];
668 static inline void sh_eth_write(struct sh_eth_info *port, unsigned long data,
671 outl(data, sh_eth_reg_addr(port, enum_index));
674 static inline unsigned long sh_eth_read(struct sh_eth_info *port,
677 return inl(sh_eth_reg_addr(port, enum_index));