drivers/net/sh_eth.c

   1 /*
   2  * sh_eth.c - Driver for Renesas ethernet controller.
   3  *
   4  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
   5  * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
   6  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   7  * Copyright (C) 2013, 2014 Renesas Electronics Corporation
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <config.h>
  13 #include <common.h>
  14 #include <malloc.h>
  15 #include <net.h>
  16 #include <netdev.h>
  17 #include <miiphy.h>
  18 #include <linux/errno.h>
  19 #include <asm/io.h>
  20
  21 #include "sh_eth.h"
  22
  23 #ifndef CONFIG_SH_ETHER_USE_PORT
  24 # error "Please define CONFIG_SH_ETHER_USE_PORT"
  25 #endif
  26 #ifndef CONFIG_SH_ETHER_PHY_ADDR
  27 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
  28 #endif
  29
  30 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
  31 #define flush_cache_wback(addr, len)    \
  32                 flush_dcache_range((u32)addr, (u32)(addr + len - 1))
  33 #else
  34 #define flush_cache_wback(...)
  35 #endif
  36
  37 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
  38 #define invalidate_cache(addr, len)             \
  39         {       \
  40                 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;    \
  41                 u32 start, end; \
  42                 \
  43                 start = (u32)addr;      \
  44                 end = start + len;      \
  45                 start &= ~(line_size - 1);      \
  46                 end = ((end + line_size - 1) & ~(line_size - 1));       \
  47                 \
  48                 invalidate_dcache_range(start, end);    \
  49         }
  50 #else
  51 #define invalidate_cache(...)
  52 #endif
  53
  54 #define TIMEOUT_CNT 1000
  55
  56 int sh_eth_send(struct eth_device *dev, void *packet, int len)
  57 {
  58         struct sh_eth_dev *eth = dev->priv;
  59         int port = eth->port, ret = 0, timeout;
  60         struct sh_eth_info *port_info = &eth->port_info[port];
  61
  62         if (!packet || len > 0xffff) {
  63                 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
  64                 ret = -EINVAL;
  65                 goto err;
  66         }
  67
  68         /* packet must be a 4 byte boundary */
  69         if ((int)packet & 3) {
  70                 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
  71                                 , __func__);
  72                 ret = -EFAULT;
  73                 goto err;
  74         }
  75
  76         /* Update tx descriptor */
  77         flush_cache_wback(packet, len);
  78         port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
  79         port_info->tx_desc_cur->td1 = len << 16;
  80         /* Must preserve the end of descriptor list indication */
  81         if (port_info->tx_desc_cur->td0 & TD_TDLE)
  82                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
  83         else
  84                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
  85
  86         flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
  87
  88         /* Restart the transmitter if disabled */
  89         if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
  90                 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
  91
  92         /* Wait until packet is transmitted */
  93         timeout = TIMEOUT_CNT;
  94         do {
  95                 invalidate_cache(port_info->tx_desc_cur,
  96                                  sizeof(struct tx_desc_s));
  97                 udelay(100);
  98         } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
  99
 100         if (timeout < 0) {
 101                 printf(SHETHER_NAME ": transmit timeout\n");
 102                 ret = -ETIMEDOUT;
 103                 goto err;
 104         }
 105
 106         port_info->tx_desc_cur++;
 107         if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
 108                 port_info->tx_desc_cur = port_info->tx_desc_base;
 109
 110 err:
 111         return ret;
 112 }
 113
 114 int sh_eth_recv(struct eth_device *dev)
 115 {
 116         struct sh_eth_dev *eth = dev->priv;
 117         int port = eth->port, len = 0;
 118         struct sh_eth_info *port_info = &eth->port_info[port];
 119         uchar *packet;
 120
 121         /* Check if the rx descriptor is ready */
 122         invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
 123         if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
 124                 /* Check for errors */
 125                 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
 126                         len = port_info->rx_desc_cur->rd1 & 0xffff;
 127                         packet = (uchar *)
 128                                 ADDR_TO_P2(port_info->rx_desc_cur->rd2);
 129                         invalidate_cache(packet, len);
 130                         net_process_received_packet(packet, len);
 131                 }
 132
 133                 /* Make current descriptor available again */
 134                 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
 135                         port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
 136                 else
 137                         port_info->rx_desc_cur->rd0 = RD_RACT;
 138
 139                 flush_cache_wback(port_info->rx_desc_cur,
 140                                   sizeof(struct rx_desc_s));
 141
 142                 /* Point to the next descriptor */
 143                 port_info->rx_desc_cur++;
 144                 if (port_info->rx_desc_cur >=
 145                     port_info->rx_desc_base + NUM_RX_DESC)
 146                         port_info->rx_desc_cur = port_info->rx_desc_base;
 147         }
 148
 149         /* Restart the receiver if disabled */
 150         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 151                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 152
 153         return len;
 154 }
 155
 156 static int sh_eth_reset(struct sh_eth_dev *eth)
 157 {
 158         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 159 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 160         int ret = 0, i;
 161
 162         /* Start e-dmac transmitter and receiver */
 163         sh_eth_write(port_info, EDSR_ENALL, EDSR);
 164
 165         /* Perform a software reset and wait for it to complete */
 166         sh_eth_write(port_info, EDMR_SRST, EDMR);
 167         for (i = 0; i < TIMEOUT_CNT; i++) {
 168                 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
 169                         break;
 170                 udelay(1000);
 171         }
 172
 173         if (i == TIMEOUT_CNT) {
 174                 printf(SHETHER_NAME  ": Software reset timeout\n");
 175                 ret = -EIO;
 176         }
 177
 178         return ret;
 179 #else
 180         sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
 181         udelay(3000);
 182         sh_eth_write(port_info,
 183                      sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
 184
 185         return 0;
 186 #endif
 187 }
 188
 189 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 190 {
 191         int port = eth->port, i, ret = 0;
 192         u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
 193         struct sh_eth_info *port_info = &eth->port_info[port];
 194         struct tx_desc_s *cur_tx_desc;
 195
 196         /*
 197          * Allocate rx descriptors. They must be aligned to size of struct
 198          * tx_desc_s.
 199          */
 200         port_info->tx_desc_alloc =
 201                 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
 202         if (!port_info->tx_desc_alloc) {
 203                 printf(SHETHER_NAME ": memalign failed\n");
 204                 ret = -ENOMEM;
 205                 goto err;
 206         }
 207
 208         flush_cache_wback((u32)port_info->tx_desc_alloc, alloc_desc_size);
 209
 210         /* Make sure we use a P2 address (non-cacheable) */
 211         port_info->tx_desc_base =
 212                 (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
 213         port_info->tx_desc_cur = port_info->tx_desc_base;
 214
 215         /* Initialize all descriptors */
 216         for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
 217              cur_tx_desc++, i++) {
 218                 cur_tx_desc->td0 = 0x00;
 219                 cur_tx_desc->td1 = 0x00;
 220                 cur_tx_desc->td2 = 0x00;
 221         }
 222
 223         /* Mark the end of the descriptors */
 224         cur_tx_desc--;
 225         cur_tx_desc->td0 |= TD_TDLE;
 226
 227         /*
 228          * Point the controller to the tx descriptor list. Must use physical
 229          * addresses
 230          */
 231         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
 232 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 233         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
 234         sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
 235         sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
 236 #endif
 237
 238 err:
 239         return ret;
 240 }
 241
 242 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 243 {
 244         int port = eth->port, i, ret = 0;
 245         u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
 246         struct sh_eth_info *port_info = &eth->port_info[port];
 247         struct rx_desc_s *cur_rx_desc;
 248         u8 *rx_buf;
 249
 250         /*
 251          * Allocate rx descriptors. They must be aligned to size of struct
 252          * rx_desc_s.
 253          */
 254         port_info->rx_desc_alloc =
 255                 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
 256         if (!port_info->rx_desc_alloc) {
 257                 printf(SHETHER_NAME ": memalign failed\n");
 258                 ret = -ENOMEM;
 259                 goto err;
 260         }
 261
 262         flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
 263
 264         /* Make sure we use a P2 address (non-cacheable) */
 265         port_info->rx_desc_base =
 266                 (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
 267
 268         port_info->rx_desc_cur = port_info->rx_desc_base;
 269
 270         /*
 271          * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
 272          * aligned and in P2 area.
 273          */
 274         port_info->rx_buf_alloc =
 275                 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
 276         if (!port_info->rx_buf_alloc) {
 277                 printf(SHETHER_NAME ": alloc failed\n");
 278                 ret = -ENOMEM;
 279                 goto err_buf_alloc;
 280         }
 281
 282         port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
 283
 284         /* Initialize all descriptors */
 285         for (cur_rx_desc = port_info->rx_desc_base,
 286              rx_buf = port_info->rx_buf_base, i = 0;
 287              i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
 288                 cur_rx_desc->rd0 = RD_RACT;
 289                 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
 290                 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
 291         }
 292
 293         /* Mark the end of the descriptors */
 294         cur_rx_desc--;
 295         cur_rx_desc->rd0 |= RD_RDLE;
 296
 297         /* Point the controller to the rx descriptor list */
 298         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
 299 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 300         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
 301         sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
 302         sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
 303 #endif
 304
 305         return ret;
 306
 307 err_buf_alloc:
 308         free(port_info->rx_desc_alloc);
 309         port_info->rx_desc_alloc = NULL;
 310
 311 err:
 312         return ret;
 313 }
 314
 315 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
 316 {
 317         int port = eth->port;
 318         struct sh_eth_info *port_info = &eth->port_info[port];
 319
 320         if (port_info->tx_desc_alloc) {
 321                 free(port_info->tx_desc_alloc);
 322                 port_info->tx_desc_alloc = NULL;
 323         }
 324 }
 325
 326 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
 327 {
 328         int port = eth->port;
 329         struct sh_eth_info *port_info = &eth->port_info[port];
 330
 331         if (port_info->rx_desc_alloc) {
 332                 free(port_info->rx_desc_alloc);
 333                 port_info->rx_desc_alloc = NULL;
 334         }
 335
 336         if (port_info->rx_buf_alloc) {
 337                 free(port_info->rx_buf_alloc);
 338                 port_info->rx_buf_alloc = NULL;
 339         }
 340 }
 341
 342 static int sh_eth_desc_init(struct sh_eth_dev *eth)
 343 {
 344         int ret = 0;
 345
 346         ret = sh_eth_tx_desc_init(eth);
 347         if (ret)
 348                 goto err_tx_init;
 349
 350         ret = sh_eth_rx_desc_init(eth);
 351         if (ret)
 352                 goto err_rx_init;
 353
 354         return ret;
 355 err_rx_init:
 356         sh_eth_tx_desc_free(eth);
 357
 358 err_tx_init:
 359         return ret;
 360 }
 361
 362 static int sh_eth_phy_config(struct sh_eth_dev *eth)
 363 {
 364         int port = eth->port, ret = 0;
 365         struct sh_eth_info *port_info = &eth->port_info[port];
 366         struct eth_device *dev = port_info->dev;
 367         struct phy_device *phydev;
 368
 369         phydev = phy_connect(
 370                         miiphy_get_dev_by_name(dev->name),
 371                         port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
 372         port_info->phydev = phydev;
 373         phy_config(phydev);
 374
 375         return ret;
 376 }
 377
 378 static int sh_eth_config(struct sh_eth_dev *eth)
 379 {
 380         int port = eth->port, ret = 0;
 381         u32 val;
 382         struct sh_eth_info *port_info = &eth->port_info[port];
 383         struct eth_device *dev = port_info->dev;
 384         struct phy_device *phy;
 385
 386         /* Configure e-dmac registers */
 387         sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
 388                         (EMDR_DESC | EDMR_EL), EDMR);
 389
 390         sh_eth_write(port_info, 0, EESIPR);
 391         sh_eth_write(port_info, 0, TRSCER);
 392         sh_eth_write(port_info, 0, TFTR);
 393         sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
 394         sh_eth_write(port_info, RMCR_RST, RMCR);
 395 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 396         sh_eth_write(port_info, 0, RPADIR);
 397 #endif
 398         sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
 399
 400         /* Configure e-mac registers */
 401         sh_eth_write(port_info, 0, ECSIPR);
 402
 403         /* Set Mac address */
 404         val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
 405             dev->enetaddr[2] << 8 | dev->enetaddr[3];
 406         sh_eth_write(port_info, val, MAHR);
 407
 408         val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
 409         sh_eth_write(port_info, val, MALR);
 410
 411         sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
 412 #if defined(SH_ETH_TYPE_GETHER)
 413         sh_eth_write(port_info, 0, PIPR);
 414 #endif
 415 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 416         sh_eth_write(port_info, APR_AP, APR);
 417         sh_eth_write(port_info, MPR_MP, MPR);
 418         sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
 419 #endif
 420
 421 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 422         sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 423 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
 424         defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 425         sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
 426 #endif
 427         /* Configure phy */
 428         ret = sh_eth_phy_config(eth);
 429         if (ret) {
 430                 printf(SHETHER_NAME ": phy config timeout\n");
 431                 goto err_phy_cfg;
 432         }
 433         phy = port_info->phydev;
 434         ret = phy_startup(phy);
 435         if (ret) {
 436                 printf(SHETHER_NAME ": phy startup failure\n");
 437                 return ret;
 438         }
 439
 440         val = 0;
 441
 442         /* Set the transfer speed */
 443         if (phy->speed == 100) {
 444                 printf(SHETHER_NAME ": 100Base/");
 445 #if defined(SH_ETH_TYPE_GETHER)
 446                 sh_eth_write(port_info, GECMR_100B, GECMR);
 447 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 448                 sh_eth_write(port_info, 1, RTRATE);
 449 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
 450                 defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
 451                 defined(CONFIG_R8A7794)
 452                 val = ECMR_RTM;
 453 #endif
 454         } else if (phy->speed == 10) {
 455                 printf(SHETHER_NAME ": 10Base/");
 456 #if defined(SH_ETH_TYPE_GETHER)
 457                 sh_eth_write(port_info, GECMR_10B, GECMR);
 458 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 459                 sh_eth_write(port_info, 0, RTRATE);
 460 #endif
 461         }
 462 #if defined(SH_ETH_TYPE_GETHER)
 463         else if (phy->speed == 1000) {
 464                 printf(SHETHER_NAME ": 1000Base/");
 465                 sh_eth_write(port_info, GECMR_1000B, GECMR);
 466         }
 467 #endif
 468
 469         /* Check if full duplex mode is supported by the phy */
 470         if (phy->duplex) {
 471                 printf("Full\n");
 472                 sh_eth_write(port_info,
 473                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
 474                              ECMR);
 475         } else {
 476                 printf("Half\n");
 477                 sh_eth_write(port_info,
 478                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
 479                              ECMR);
 480         }
 481
 482         return ret;
 483
 484 err_phy_cfg:
 485         return ret;
 486 }
 487
 488 static void sh_eth_start(struct sh_eth_dev *eth)
 489 {
 490         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 491
 492         /*
 493          * Enable the e-dmac receiver only. The transmitter will be enabled when
 494          * we have something to transmit
 495          */
 496         sh_eth_write(port_info, EDRRR_R, EDRRR);
 497 }
 498
 499 static void sh_eth_stop(struct sh_eth_dev *eth)
 500 {
 501         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 502
 503         sh_eth_write(port_info, ~EDRRR_R, EDRRR);
 504 }
 505
 506 int sh_eth_init(struct eth_device *dev, bd_t *bd)
 507 {
 508         int ret = 0;
 509         struct sh_eth_dev *eth = dev->priv;
 510
 511         ret = sh_eth_reset(eth);
 512         if (ret)
 513                 goto err;
 514
 515         ret = sh_eth_desc_init(eth);
 516         if (ret)
 517                 goto err;
 518
 519         ret = sh_eth_config(eth);
 520         if (ret)
 521                 goto err_config;
 522
 523         sh_eth_start(eth);
 524
 525         return ret;
 526
 527 err_config:
 528         sh_eth_tx_desc_free(eth);
 529         sh_eth_rx_desc_free(eth);
 530
 531 err:
 532         return ret;
 533 }
 534
 535 void sh_eth_halt(struct eth_device *dev)
 536 {
 537         struct sh_eth_dev *eth = dev->priv;
 538
 539         sh_eth_stop(eth);
 540 }
 541
 542 int sh_eth_initialize(bd_t *bd)
 543 {
 544         int ret = 0;
 545         struct sh_eth_dev *eth = NULL;
 546         struct eth_device *dev = NULL;
 547         struct mii_dev *mdiodev;
 548
 549         eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
 550         if (!eth) {
 551                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 552                 ret = -ENOMEM;
 553                 goto err;
 554         }
 555
 556         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
 557         if (!dev) {
 558                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 559                 ret = -ENOMEM;
 560                 goto err;
 561         }
 562         memset(dev, 0, sizeof(struct eth_device));
 563         memset(eth, 0, sizeof(struct sh_eth_dev));
 564
 565         eth->port = CONFIG_SH_ETHER_USE_PORT;
 566         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 567         eth->port_info[eth->port].iobase =
 568                 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
 569
 570         dev->priv = (void *)eth;
 571         dev->iobase = 0;
 572         dev->init = sh_eth_init;
 573         dev->halt = sh_eth_halt;
 574         dev->send = sh_eth_send;
 575         dev->recv = sh_eth_recv;
 576         eth->port_info[eth->port].dev = dev;
 577
 578         strcpy(dev->name, SHETHER_NAME);
 579
 580         /* Register Device to EtherNet subsystem  */
 581         eth_register(dev);
 582
 583         bb_miiphy_buses[0].priv = eth;
 584         mdiodev = mdio_alloc();
 585         if (!mdiodev)
 586                 return -ENOMEM;
 587         strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 588         mdiodev->read = bb_miiphy_read;
 589         mdiodev->write = bb_miiphy_write;
 590
 591         ret = mdio_register(mdiodev);
 592         if (ret < 0)
 593                 return ret;
 594
 595         if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
 596                 puts("Please set MAC address\n");
 597
 598         return ret;
 599
 600 err:
 601         if (dev)
 602                 free(dev);
 603
 604         if (eth)
 605                 free(eth);
 606
 607         printf(SHETHER_NAME ": Failed\n");
 608         return ret;
 609 }
 610
 611 /******* for bb_miiphy *******/
 612 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 613 {
 614         return 0;
 615 }
 616
 617 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 618 {
 619         struct sh_eth_dev *eth = bus->priv;
 620         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 621
 622         sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
 623
 624         return 0;
 625 }
 626
 627 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 628 {
 629         struct sh_eth_dev *eth = bus->priv;
 630         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 631
 632         sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
 633
 634         return 0;
 635 }
 636
 637 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 638 {
 639         struct sh_eth_dev *eth = bus->priv;
 640         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 641
 642         if (v)
 643                 sh_eth_write(port_info,
 644                              sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
 645         else
 646                 sh_eth_write(port_info,
 647                              sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
 648
 649         return 0;
 650 }
 651
 652 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
 653 {
 654         struct sh_eth_dev *eth = bus->priv;
 655         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 656
 657         *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
 658
 659         return 0;
 660 }
 661
 662 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
 663 {
 664         struct sh_eth_dev *eth = bus->priv;
 665         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 666
 667         if (v)
 668                 sh_eth_write(port_info,
 669                              sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
 670         else
 671                 sh_eth_write(port_info,
 672                              sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
 673
 674         return 0;
 675 }
 676
 677 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
 678 {
 679         udelay(10);
 680
 681         return 0;
 682 }
 683
 684 struct bb_miiphy_bus bb_miiphy_buses[] = {
 685         {
 686                 .name           = "sh_eth",
 687                 .init           = sh_eth_bb_init,
 688                 .mdio_active    = sh_eth_bb_mdio_active,
 689                 .mdio_tristate  = sh_eth_bb_mdio_tristate,
 690                 .set_mdio       = sh_eth_bb_set_mdio,
 691                 .get_mdio       = sh_eth_bb_get_mdio,
 692                 .set_mdc        = sh_eth_bb_set_mdc,
 693                 .delay          = sh_eth_bb_delay,
 694         }
 695 };
 696
 697 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);