2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
23 #include <linux/init.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/mdio-bitbang.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/cache.h>
33 #include <linux/pm_runtime.h>
36 /* There is CPU dependent code */
37 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
38 #define SH_ETH_RESET_DEFAULT 1
39 static void sh_eth_set_duplex(struct net_device *ndev)
41 struct sh_eth_private *mdp = netdev_priv(ndev);
42 u32 ioaddr = ndev->base_addr;
44 if (mdp->duplex) /* Full */
45 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
47 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
50 static void sh_eth_set_rate(struct net_device *ndev)
52 struct sh_eth_private *mdp = netdev_priv(ndev);
53 u32 ioaddr = ndev->base_addr;
57 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_RTM, ioaddr + ECMR);
59 case 100:/* 100BASE */
60 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_RTM, ioaddr + ECMR);
68 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
69 .set_duplex = sh_eth_set_duplex,
70 .set_rate = sh_eth_set_rate,
72 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
73 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
74 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
76 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
77 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
78 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
79 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
87 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
88 #define SH_ETH_HAS_TSU 1
89 static void sh_eth_chip_reset(struct net_device *ndev)
92 ctrl_outl(ARSTR_ARSTR, ARSTR);
96 static void sh_eth_reset(struct net_device *ndev)
98 u32 ioaddr = ndev->base_addr;
101 ctrl_outl(EDSR_ENALL, ioaddr + EDSR);
102 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
104 if (!(ctrl_inl(ioaddr + EDMR) & 0x3))
110 printk(KERN_ERR "Device reset fail\n");
113 ctrl_outl(0x0, ioaddr + TDLAR);
114 ctrl_outl(0x0, ioaddr + TDFAR);
115 ctrl_outl(0x0, ioaddr + TDFXR);
116 ctrl_outl(0x0, ioaddr + TDFFR);
117 ctrl_outl(0x0, ioaddr + RDLAR);
118 ctrl_outl(0x0, ioaddr + RDFAR);
119 ctrl_outl(0x0, ioaddr + RDFXR);
120 ctrl_outl(0x0, ioaddr + RDFFR);
123 static void sh_eth_set_duplex(struct net_device *ndev)
125 struct sh_eth_private *mdp = netdev_priv(ndev);
126 u32 ioaddr = ndev->base_addr;
128 if (mdp->duplex) /* Full */
129 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
131 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
134 static void sh_eth_set_rate(struct net_device *ndev)
136 struct sh_eth_private *mdp = netdev_priv(ndev);
137 u32 ioaddr = ndev->base_addr;
139 switch (mdp->speed) {
140 case 10: /* 10BASE */
141 ctrl_outl(GECMR_10, ioaddr + GECMR);
143 case 100:/* 100BASE */
144 ctrl_outl(GECMR_100, ioaddr + GECMR);
146 case 1000: /* 1000BASE */
147 ctrl_outl(GECMR_1000, ioaddr + GECMR);
155 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
156 .chip_reset = sh_eth_chip_reset,
157 .set_duplex = sh_eth_set_duplex,
158 .set_rate = sh_eth_set_rate,
160 .ecsr_value = ECSR_ICD | ECSR_MPD,
161 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
162 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
164 .tx_check = EESR_TC1 | EESR_FTC,
165 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
166 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
168 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
181 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
182 #define SH_ETH_RESET_DEFAULT 1
183 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
184 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
191 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
192 #define SH_ETH_RESET_DEFAULT 1
193 #define SH_ETH_HAS_TSU 1
194 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
195 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
199 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
202 cd->ecsr_value = DEFAULT_ECSR_INIT;
204 if (!cd->ecsipr_value)
205 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
207 if (!cd->fcftr_value)
208 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
209 DEFAULT_FIFO_F_D_RFD;
212 cd->fdr_value = DEFAULT_FDR_INIT;
215 cd->rmcr_value = DEFAULT_RMCR_VALUE;
218 cd->tx_check = DEFAULT_TX_CHECK;
220 if (!cd->eesr_err_check)
221 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
223 if (!cd->tx_error_check)
224 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
227 #if defined(SH_ETH_RESET_DEFAULT)
229 static void sh_eth_reset(struct net_device *ndev)
231 u32 ioaddr = ndev->base_addr;
233 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
235 ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR);
239 #if defined(CONFIG_CPU_SH4)
240 static void sh_eth_set_receive_align(struct sk_buff *skb)
244 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
246 skb_reserve(skb, reserve);
249 static void sh_eth_set_receive_align(struct sk_buff *skb)
251 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
256 /* CPU <-> EDMAC endian convert */
257 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
259 switch (mdp->edmac_endian) {
260 case EDMAC_LITTLE_ENDIAN:
261 return cpu_to_le32(x);
262 case EDMAC_BIG_ENDIAN:
263 return cpu_to_be32(x);
268 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
270 switch (mdp->edmac_endian) {
271 case EDMAC_LITTLE_ENDIAN:
272 return le32_to_cpu(x);
273 case EDMAC_BIG_ENDIAN:
274 return be32_to_cpu(x);
280 * Program the hardware MAC address from dev->dev_addr.
282 static void update_mac_address(struct net_device *ndev)
284 u32 ioaddr = ndev->base_addr;
286 ctrl_outl((ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
287 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]),
289 ctrl_outl((ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]),
294 * Get MAC address from SuperH MAC address register
296 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
297 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
298 * When you want use this device, you must set MAC address in bootloader.
301 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
303 u32 ioaddr = ndev->base_addr;
305 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
306 memcpy(ndev->dev_addr, mac, 6);
308 ndev->dev_addr[0] = (ctrl_inl(ioaddr + MAHR) >> 24);
309 ndev->dev_addr[1] = (ctrl_inl(ioaddr + MAHR) >> 16) & 0xFF;
310 ndev->dev_addr[2] = (ctrl_inl(ioaddr + MAHR) >> 8) & 0xFF;
311 ndev->dev_addr[3] = (ctrl_inl(ioaddr + MAHR) & 0xFF);
312 ndev->dev_addr[4] = (ctrl_inl(ioaddr + MALR) >> 8) & 0xFF;
313 ndev->dev_addr[5] = (ctrl_inl(ioaddr + MALR) & 0xFF);
318 struct mdiobb_ctrl ctrl;
320 u32 mmd_msk;/* MMD */
327 static void bb_set(u32 addr, u32 msk)
329 ctrl_outl(ctrl_inl(addr) | msk, addr);
333 static void bb_clr(u32 addr, u32 msk)
335 ctrl_outl((ctrl_inl(addr) & ~msk), addr);
339 static int bb_read(u32 addr, u32 msk)
341 return (ctrl_inl(addr) & msk) != 0;
344 /* Data I/O pin control */
345 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
347 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
349 bb_set(bitbang->addr, bitbang->mmd_msk);
351 bb_clr(bitbang->addr, bitbang->mmd_msk);
355 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
357 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
360 bb_set(bitbang->addr, bitbang->mdo_msk);
362 bb_clr(bitbang->addr, bitbang->mdo_msk);
366 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
368 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
369 return bb_read(bitbang->addr, bitbang->mdi_msk);
372 /* MDC pin control */
373 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
375 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
378 bb_set(bitbang->addr, bitbang->mdc_msk);
380 bb_clr(bitbang->addr, bitbang->mdc_msk);
383 /* mdio bus control struct */
384 static struct mdiobb_ops bb_ops = {
385 .owner = THIS_MODULE,
386 .set_mdc = sh_mdc_ctrl,
387 .set_mdio_dir = sh_mmd_ctrl,
388 .set_mdio_data = sh_set_mdio,
389 .get_mdio_data = sh_get_mdio,
392 /* free skb and descriptor buffer */
393 static void sh_eth_ring_free(struct net_device *ndev)
395 struct sh_eth_private *mdp = netdev_priv(ndev);
398 /* Free Rx skb ringbuffer */
399 if (mdp->rx_skbuff) {
400 for (i = 0; i < RX_RING_SIZE; i++) {
401 if (mdp->rx_skbuff[i])
402 dev_kfree_skb(mdp->rx_skbuff[i]);
405 kfree(mdp->rx_skbuff);
407 /* Free Tx skb ringbuffer */
408 if (mdp->tx_skbuff) {
409 for (i = 0; i < TX_RING_SIZE; i++) {
410 if (mdp->tx_skbuff[i])
411 dev_kfree_skb(mdp->tx_skbuff[i]);
414 kfree(mdp->tx_skbuff);
417 /* format skb and descriptor buffer */
418 static void sh_eth_ring_format(struct net_device *ndev)
420 u32 ioaddr = ndev->base_addr;
421 struct sh_eth_private *mdp = netdev_priv(ndev);
424 struct sh_eth_rxdesc *rxdesc = NULL;
425 struct sh_eth_txdesc *txdesc = NULL;
426 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
427 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
429 mdp->cur_rx = mdp->cur_tx = 0;
430 mdp->dirty_rx = mdp->dirty_tx = 0;
432 memset(mdp->rx_ring, 0, rx_ringsize);
434 /* build Rx ring buffer */
435 for (i = 0; i < RX_RING_SIZE; i++) {
437 mdp->rx_skbuff[i] = NULL;
438 skb = dev_alloc_skb(mdp->rx_buf_sz);
439 mdp->rx_skbuff[i] = skb;
442 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
444 skb->dev = ndev; /* Mark as being used by this device. */
445 sh_eth_set_receive_align(skb);
448 rxdesc = &mdp->rx_ring[i];
449 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
450 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
452 /* The size of the buffer is 16 byte boundary. */
453 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
454 /* Rx descriptor address set */
456 ctrl_outl(mdp->rx_desc_dma, ioaddr + RDLAR);
457 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
458 ctrl_outl(mdp->rx_desc_dma, ioaddr + RDFAR);
463 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
465 /* Mark the last entry as wrapping the ring. */
466 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
468 memset(mdp->tx_ring, 0, tx_ringsize);
470 /* build Tx ring buffer */
471 for (i = 0; i < TX_RING_SIZE; i++) {
472 mdp->tx_skbuff[i] = NULL;
473 txdesc = &mdp->tx_ring[i];
474 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
475 txdesc->buffer_length = 0;
477 /* Tx descriptor address set */
478 ctrl_outl(mdp->tx_desc_dma, ioaddr + TDLAR);
479 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
480 ctrl_outl(mdp->tx_desc_dma, ioaddr + TDFAR);
485 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
488 /* Get skb and descriptor buffer */
489 static int sh_eth_ring_init(struct net_device *ndev)
491 struct sh_eth_private *mdp = netdev_priv(ndev);
492 int rx_ringsize, tx_ringsize, ret = 0;
495 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
496 * card needs room to do 8 byte alignment, +2 so we can reserve
497 * the first 2 bytes, and +16 gets room for the status word from the
500 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
501 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503 /* Allocate RX and TX skb rings */
504 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
506 if (!mdp->rx_skbuff) {
507 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
512 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
514 if (!mdp->tx_skbuff) {
515 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
520 /* Allocate all Rx descriptors. */
521 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
522 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
526 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
534 /* Allocate all Tx descriptors. */
535 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
536 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
539 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
547 /* free DMA buffer */
548 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
551 /* Free Rx and Tx skb ring buffer */
552 sh_eth_ring_free(ndev);
557 static int sh_eth_dev_init(struct net_device *ndev)
560 struct sh_eth_private *mdp = netdev_priv(ndev);
561 u32 ioaddr = ndev->base_addr;
562 u_int32_t rx_int_var, tx_int_var;
568 /* Descriptor format */
569 sh_eth_ring_format(ndev);
571 ctrl_outl(mdp->cd->rpadir_value, ioaddr + RPADIR);
573 /* all sh_eth int mask */
574 ctrl_outl(0, ioaddr + EESIPR);
576 #if defined(__LITTLE_ENDIAN__)
577 if (mdp->cd->hw_swap)
578 ctrl_outl(EDMR_EL, ioaddr + EDMR);
581 ctrl_outl(0, ioaddr + EDMR);
584 ctrl_outl(mdp->cd->fdr_value, ioaddr + FDR);
585 ctrl_outl(0, ioaddr + TFTR);
587 /* Frame recv control */
588 ctrl_outl(mdp->cd->rmcr_value, ioaddr + RMCR);
590 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
591 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
592 ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER);
595 ctrl_outl(0x800, ioaddr + BCULR); /* Burst sycle set */
597 ctrl_outl(mdp->cd->fcftr_value, ioaddr + FCFTR);
599 if (!mdp->cd->no_trimd)
600 ctrl_outl(0, ioaddr + TRIMD);
602 /* Recv frame limit set register */
603 ctrl_outl(RFLR_VALUE, ioaddr + RFLR);
605 ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR);
606 ctrl_outl(mdp->cd->eesipr_value, ioaddr + EESIPR);
608 /* PAUSE Prohibition */
609 val = (ctrl_inl(ioaddr + ECMR) & ECMR_DM) |
610 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
612 ctrl_outl(val, ioaddr + ECMR);
614 if (mdp->cd->set_rate)
615 mdp->cd->set_rate(ndev);
617 /* E-MAC Status Register clear */
618 ctrl_outl(mdp->cd->ecsr_value, ioaddr + ECSR);
620 /* E-MAC Interrupt Enable register */
621 ctrl_outl(mdp->cd->ecsipr_value, ioaddr + ECSIPR);
623 /* Set MAC address */
624 update_mac_address(ndev);
628 ctrl_outl(APR_AP, ioaddr + APR);
630 ctrl_outl(MPR_MP, ioaddr + MPR);
631 if (mdp->cd->tpauser)
632 ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER);
634 /* Setting the Rx mode will start the Rx process. */
635 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
637 netif_start_queue(ndev);
642 /* free Tx skb function */
643 static int sh_eth_txfree(struct net_device *ndev)
645 struct sh_eth_private *mdp = netdev_priv(ndev);
646 struct sh_eth_txdesc *txdesc;
650 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
651 entry = mdp->dirty_tx % TX_RING_SIZE;
652 txdesc = &mdp->tx_ring[entry];
653 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
655 /* Free the original skb. */
656 if (mdp->tx_skbuff[entry]) {
657 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
658 mdp->tx_skbuff[entry] = NULL;
661 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
662 if (entry >= TX_RING_SIZE - 1)
663 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
665 mdp->stats.tx_packets++;
666 mdp->stats.tx_bytes += txdesc->buffer_length;
671 /* Packet receive function */
672 static int sh_eth_rx(struct net_device *ndev)
674 struct sh_eth_private *mdp = netdev_priv(ndev);
675 struct sh_eth_rxdesc *rxdesc;
677 int entry = mdp->cur_rx % RX_RING_SIZE;
678 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
683 rxdesc = &mdp->rx_ring[entry];
684 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
685 desc_status = edmac_to_cpu(mdp, rxdesc->status);
686 pkt_len = rxdesc->frame_length;
691 if (!(desc_status & RDFEND))
692 mdp->stats.rx_length_errors++;
694 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
695 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
696 mdp->stats.rx_errors++;
697 if (desc_status & RD_RFS1)
698 mdp->stats.rx_crc_errors++;
699 if (desc_status & RD_RFS2)
700 mdp->stats.rx_frame_errors++;
701 if (desc_status & RD_RFS3)
702 mdp->stats.rx_length_errors++;
703 if (desc_status & RD_RFS4)
704 mdp->stats.rx_length_errors++;
705 if (desc_status & RD_RFS6)
706 mdp->stats.rx_missed_errors++;
707 if (desc_status & RD_RFS10)
708 mdp->stats.rx_over_errors++;
710 if (!mdp->cd->hw_swap)
712 phys_to_virt(ALIGN(rxdesc->addr, 4)),
714 skb = mdp->rx_skbuff[entry];
715 mdp->rx_skbuff[entry] = NULL;
716 skb_put(skb, pkt_len);
717 skb->protocol = eth_type_trans(skb, ndev);
719 mdp->stats.rx_packets++;
720 mdp->stats.rx_bytes += pkt_len;
722 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
723 entry = (++mdp->cur_rx) % RX_RING_SIZE;
724 rxdesc = &mdp->rx_ring[entry];
727 /* Refill the Rx ring buffers. */
728 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
729 entry = mdp->dirty_rx % RX_RING_SIZE;
730 rxdesc = &mdp->rx_ring[entry];
731 /* The size of the buffer is 16 byte boundary. */
732 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
734 if (mdp->rx_skbuff[entry] == NULL) {
735 skb = dev_alloc_skb(mdp->rx_buf_sz);
736 mdp->rx_skbuff[entry] = skb;
738 break; /* Better luck next round. */
739 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
742 sh_eth_set_receive_align(skb);
744 skb->ip_summed = CHECKSUM_NONE;
745 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
747 if (entry >= RX_RING_SIZE - 1)
749 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
752 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
755 /* Restart Rx engine if stopped. */
756 /* If we don't need to check status, don't. -KDU */
757 if (!(ctrl_inl(ndev->base_addr + EDRRR) & EDRRR_R))
758 ctrl_outl(EDRRR_R, ndev->base_addr + EDRRR);
763 /* error control function */
764 static void sh_eth_error(struct net_device *ndev, int intr_status)
766 struct sh_eth_private *mdp = netdev_priv(ndev);
767 u32 ioaddr = ndev->base_addr;
772 if (intr_status & EESR_ECI) {
773 felic_stat = ctrl_inl(ioaddr + ECSR);
774 ctrl_outl(felic_stat, ioaddr + ECSR); /* clear int */
775 if (felic_stat & ECSR_ICD)
776 mdp->stats.tx_carrier_errors++;
777 if (felic_stat & ECSR_LCHNG) {
779 if (mdp->cd->no_psr || mdp->no_ether_link) {
780 if (mdp->link == PHY_DOWN)
783 link_stat = PHY_ST_LINK;
785 link_stat = (ctrl_inl(ioaddr + PSR));
786 if (mdp->ether_link_active_low)
787 link_stat = ~link_stat;
789 if (!(link_stat & PHY_ST_LINK)) {
790 /* Link Down : disable tx and rx */
791 ctrl_outl(ctrl_inl(ioaddr + ECMR) &
792 ~(ECMR_RE | ECMR_TE), ioaddr + ECMR);
795 ctrl_outl(ctrl_inl(ioaddr + EESIPR) &
796 ~DMAC_M_ECI, ioaddr + EESIPR);
798 ctrl_outl(ctrl_inl(ioaddr + ECSR),
800 ctrl_outl(ctrl_inl(ioaddr + EESIPR) |
801 DMAC_M_ECI, ioaddr + EESIPR);
802 /* enable tx and rx */
803 ctrl_outl(ctrl_inl(ioaddr + ECMR) |
804 (ECMR_RE | ECMR_TE), ioaddr + ECMR);
809 if (intr_status & EESR_TWB) {
810 /* Write buck end. unused write back interrupt */
811 if (intr_status & EESR_TABT) /* Transmit Abort int */
812 mdp->stats.tx_aborted_errors++;
815 if (intr_status & EESR_RABT) {
816 /* Receive Abort int */
817 if (intr_status & EESR_RFRMER) {
818 /* Receive Frame Overflow int */
819 mdp->stats.rx_frame_errors++;
820 dev_err(&ndev->dev, "Receive Frame Overflow\n");
824 if (!mdp->cd->no_ade) {
825 if (intr_status & EESR_ADE && intr_status & EESR_TDE &&
826 intr_status & EESR_TFE)
827 mdp->stats.tx_fifo_errors++;
830 if (intr_status & EESR_RDE) {
831 /* Receive Descriptor Empty int */
832 mdp->stats.rx_over_errors++;
834 if (ctrl_inl(ioaddr + EDRRR) ^ EDRRR_R)
835 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
836 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
838 if (intr_status & EESR_RFE) {
839 /* Receive FIFO Overflow int */
840 mdp->stats.rx_fifo_errors++;
841 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
844 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
847 if (intr_status & mask) {
849 u32 edtrr = ctrl_inl(ndev->base_addr + EDTRR);
851 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
852 intr_status, mdp->cur_tx);
853 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
854 mdp->dirty_tx, (u32) ndev->state, edtrr);
855 /* dirty buffer free */
859 if (edtrr ^ EDTRR_TRNS) {
861 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
864 netif_wake_queue(ndev);
868 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
870 struct net_device *ndev = netdev;
871 struct sh_eth_private *mdp = netdev_priv(ndev);
872 struct sh_eth_cpu_data *cd = mdp->cd;
873 irqreturn_t ret = IRQ_NONE;
874 u32 ioaddr, intr_status = 0;
876 ioaddr = ndev->base_addr;
877 spin_lock(&mdp->lock);
879 /* Get interrpt stat */
880 intr_status = ctrl_inl(ioaddr + EESR);
881 /* Clear interrupt */
882 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
883 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
884 cd->tx_check | cd->eesr_err_check)) {
885 ctrl_outl(intr_status, ioaddr + EESR);
890 if (intr_status & (EESR_FRC | /* Frame recv*/
891 EESR_RMAF | /* Multi cast address recv*/
892 EESR_RRF | /* Bit frame recv */
893 EESR_RTLF | /* Long frame recv*/
894 EESR_RTSF | /* short frame recv */
895 EESR_PRE | /* PHY-LSI recv error */
896 EESR_CERF)){ /* recv frame CRC error */
901 if (intr_status & cd->tx_check) {
903 netif_wake_queue(ndev);
906 if (intr_status & cd->eesr_err_check)
907 sh_eth_error(ndev, intr_status);
910 spin_unlock(&mdp->lock);
915 static void sh_eth_timer(unsigned long data)
917 struct net_device *ndev = (struct net_device *)data;
918 struct sh_eth_private *mdp = netdev_priv(ndev);
920 mod_timer(&mdp->timer, jiffies + (10 * HZ));
923 /* PHY state control function */
924 static void sh_eth_adjust_link(struct net_device *ndev)
926 struct sh_eth_private *mdp = netdev_priv(ndev);
927 struct phy_device *phydev = mdp->phydev;
928 u32 ioaddr = ndev->base_addr;
931 if (phydev->link != PHY_DOWN) {
932 if (phydev->duplex != mdp->duplex) {
934 mdp->duplex = phydev->duplex;
935 if (mdp->cd->set_duplex)
936 mdp->cd->set_duplex(ndev);
939 if (phydev->speed != mdp->speed) {
941 mdp->speed = phydev->speed;
942 if (mdp->cd->set_rate)
943 mdp->cd->set_rate(ndev);
945 if (mdp->link == PHY_DOWN) {
946 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF)
947 | ECMR_DM, ioaddr + ECMR);
949 mdp->link = phydev->link;
951 } else if (mdp->link) {
953 mdp->link = PHY_DOWN;
959 phy_print_status(phydev);
962 /* PHY init function */
963 static int sh_eth_phy_init(struct net_device *ndev)
965 struct sh_eth_private *mdp = netdev_priv(ndev);
966 char phy_id[MII_BUS_ID_SIZE + 3];
967 struct phy_device *phydev = NULL;
969 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
970 mdp->mii_bus->id , mdp->phy_id);
972 mdp->link = PHY_DOWN;
976 /* Try connect to PHY */
977 phydev = phy_connect(ndev, phy_id, &sh_eth_adjust_link,
978 0, PHY_INTERFACE_MODE_MII);
979 if (IS_ERR(phydev)) {
980 dev_err(&ndev->dev, "phy_connect failed\n");
981 return PTR_ERR(phydev);
984 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
985 phydev->addr, phydev->drv->name);
987 mdp->phydev = phydev;
992 /* PHY control start function */
993 static int sh_eth_phy_start(struct net_device *ndev)
995 struct sh_eth_private *mdp = netdev_priv(ndev);
998 ret = sh_eth_phy_init(ndev);
1002 /* reset phy - this also wakes it from PDOWN */
1003 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1004 phy_start(mdp->phydev);
1009 /* network device open function */
1010 static int sh_eth_open(struct net_device *ndev)
1013 struct sh_eth_private *mdp = netdev_priv(ndev);
1015 pm_runtime_get_sync(&mdp->pdev->dev);
1017 ret = request_irq(ndev->irq, &sh_eth_interrupt,
1018 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || defined(CONFIG_CPU_SUBTYPE_SH7764)
1025 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1029 /* Descriptor set */
1030 ret = sh_eth_ring_init(ndev);
1035 ret = sh_eth_dev_init(ndev);
1039 /* PHY control start*/
1040 ret = sh_eth_phy_start(ndev);
1044 /* Set the timer to check for link beat. */
1045 init_timer(&mdp->timer);
1046 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1047 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
1052 free_irq(ndev->irq, ndev);
1053 pm_runtime_put_sync(&mdp->pdev->dev);
1057 /* Timeout function */
1058 static void sh_eth_tx_timeout(struct net_device *ndev)
1060 struct sh_eth_private *mdp = netdev_priv(ndev);
1061 u32 ioaddr = ndev->base_addr;
1062 struct sh_eth_rxdesc *rxdesc;
1065 netif_stop_queue(ndev);
1067 /* worning message out. */
1068 printk(KERN_WARNING "%s: transmit timed out, status %8.8x,"
1069 " resetting...\n", ndev->name, (int)ctrl_inl(ioaddr + EESR));
1071 /* tx_errors count up */
1072 mdp->stats.tx_errors++;
1075 del_timer_sync(&mdp->timer);
1077 /* Free all the skbuffs in the Rx queue. */
1078 for (i = 0; i < RX_RING_SIZE; i++) {
1079 rxdesc = &mdp->rx_ring[i];
1081 rxdesc->addr = 0xBADF00D0;
1082 if (mdp->rx_skbuff[i])
1083 dev_kfree_skb(mdp->rx_skbuff[i]);
1084 mdp->rx_skbuff[i] = NULL;
1086 for (i = 0; i < TX_RING_SIZE; i++) {
1087 if (mdp->tx_skbuff[i])
1088 dev_kfree_skb(mdp->tx_skbuff[i]);
1089 mdp->tx_skbuff[i] = NULL;
1093 sh_eth_dev_init(ndev);
1096 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1097 add_timer(&mdp->timer);
1100 /* Packet transmit function */
1101 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1103 struct sh_eth_private *mdp = netdev_priv(ndev);
1104 struct sh_eth_txdesc *txdesc;
1106 unsigned long flags;
1108 spin_lock_irqsave(&mdp->lock, flags);
1109 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1110 if (!sh_eth_txfree(ndev)) {
1111 netif_stop_queue(ndev);
1112 spin_unlock_irqrestore(&mdp->lock, flags);
1113 return NETDEV_TX_BUSY;
1116 spin_unlock_irqrestore(&mdp->lock, flags);
1118 entry = mdp->cur_tx % TX_RING_SIZE;
1119 mdp->tx_skbuff[entry] = skb;
1120 txdesc = &mdp->tx_ring[entry];
1121 txdesc->addr = virt_to_phys(skb->data);
1123 if (!mdp->cd->hw_swap)
1124 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1127 __flush_purge_region(skb->data, skb->len);
1128 if (skb->len < ETHERSMALL)
1129 txdesc->buffer_length = ETHERSMALL;
1131 txdesc->buffer_length = skb->len;
1133 if (entry >= TX_RING_SIZE - 1)
1134 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1136 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1140 if (!(ctrl_inl(ndev->base_addr + EDTRR) & EDTRR_TRNS))
1141 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
1143 ndev->trans_start = jiffies;
1145 return NETDEV_TX_OK;
1148 /* device close function */
1149 static int sh_eth_close(struct net_device *ndev)
1151 struct sh_eth_private *mdp = netdev_priv(ndev);
1152 u32 ioaddr = ndev->base_addr;
1155 netif_stop_queue(ndev);
1157 /* Disable interrupts by clearing the interrupt mask. */
1158 ctrl_outl(0x0000, ioaddr + EESIPR);
1160 /* Stop the chip's Tx and Rx processes. */
1161 ctrl_outl(0, ioaddr + EDTRR);
1162 ctrl_outl(0, ioaddr + EDRRR);
1164 /* PHY Disconnect */
1166 phy_stop(mdp->phydev);
1167 phy_disconnect(mdp->phydev);
1170 free_irq(ndev->irq, ndev);
1172 del_timer_sync(&mdp->timer);
1174 /* Free all the skbuffs in the Rx queue. */
1175 sh_eth_ring_free(ndev);
1177 /* free DMA buffer */
1178 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1179 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1181 /* free DMA buffer */
1182 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1183 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1185 pm_runtime_put_sync(&mdp->pdev->dev);
1190 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1192 struct sh_eth_private *mdp = netdev_priv(ndev);
1193 u32 ioaddr = ndev->base_addr;
1195 pm_runtime_get_sync(&mdp->pdev->dev);
1197 mdp->stats.tx_dropped += ctrl_inl(ioaddr + TROCR);
1198 ctrl_outl(0, ioaddr + TROCR); /* (write clear) */
1199 mdp->stats.collisions += ctrl_inl(ioaddr + CDCR);
1200 ctrl_outl(0, ioaddr + CDCR); /* (write clear) */
1201 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + LCCR);
1202 ctrl_outl(0, ioaddr + LCCR); /* (write clear) */
1203 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
1204 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CERCR);/* CERCR */
1205 ctrl_outl(0, ioaddr + CERCR); /* (write clear) */
1206 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CEECR);/* CEECR */
1207 ctrl_outl(0, ioaddr + CEECR); /* (write clear) */
1209 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CNDCR);
1210 ctrl_outl(0, ioaddr + CNDCR); /* (write clear) */
1212 pm_runtime_put_sync(&mdp->pdev->dev);
1217 /* ioctl to device funciotn*/
1218 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1221 struct sh_eth_private *mdp = netdev_priv(ndev);
1222 struct phy_device *phydev = mdp->phydev;
1224 if (!netif_running(ndev))
1230 return phy_mii_ioctl(phydev, if_mii(rq), cmd);
1233 #if defined(SH_ETH_HAS_TSU)
1234 /* Multicast reception directions set */
1235 static void sh_eth_set_multicast_list(struct net_device *ndev)
1237 u32 ioaddr = ndev->base_addr;
1239 if (ndev->flags & IFF_PROMISC) {
1240 /* Set promiscuous. */
1241 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_MCT) | ECMR_PRM,
1244 /* Normal, unicast/broadcast-only mode. */
1245 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_PRM) | ECMR_MCT,
1250 /* SuperH's TSU register init function */
1251 static void sh_eth_tsu_init(u32 ioaddr)
1253 ctrl_outl(0, ioaddr + TSU_FWEN0); /* Disable forward(0->1) */
1254 ctrl_outl(0, ioaddr + TSU_FWEN1); /* Disable forward(1->0) */
1255 ctrl_outl(0, ioaddr + TSU_FCM); /* forward fifo 3k-3k */
1256 ctrl_outl(0xc, ioaddr + TSU_BSYSL0);
1257 ctrl_outl(0xc, ioaddr + TSU_BSYSL1);
1258 ctrl_outl(0, ioaddr + TSU_PRISL0);
1259 ctrl_outl(0, ioaddr + TSU_PRISL1);
1260 ctrl_outl(0, ioaddr + TSU_FWSL0);
1261 ctrl_outl(0, ioaddr + TSU_FWSL1);
1262 ctrl_outl(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC);
1263 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
1264 ctrl_outl(0, ioaddr + TSU_QTAG0); /* Disable QTAG(0->1) */
1265 ctrl_outl(0, ioaddr + TSU_QTAG1); /* Disable QTAG(1->0) */
1267 ctrl_outl(0, ioaddr + TSU_QTAGM0); /* Disable QTAG(0->1) */
1268 ctrl_outl(0, ioaddr + TSU_QTAGM1); /* Disable QTAG(1->0) */
1270 ctrl_outl(0, ioaddr + TSU_FWSR); /* all interrupt status clear */
1271 ctrl_outl(0, ioaddr + TSU_FWINMK); /* Disable all interrupt */
1272 ctrl_outl(0, ioaddr + TSU_TEN); /* Disable all CAM entry */
1273 ctrl_outl(0, ioaddr + TSU_POST1); /* Disable CAM entry [ 0- 7] */
1274 ctrl_outl(0, ioaddr + TSU_POST2); /* Disable CAM entry [ 8-15] */
1275 ctrl_outl(0, ioaddr + TSU_POST3); /* Disable CAM entry [16-23] */
1276 ctrl_outl(0, ioaddr + TSU_POST4); /* Disable CAM entry [24-31] */
1278 #endif /* SH_ETH_HAS_TSU */
1280 /* MDIO bus release function */
1281 static int sh_mdio_release(struct net_device *ndev)
1283 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1285 /* unregister mdio bus */
1286 mdiobus_unregister(bus);
1288 /* remove mdio bus info from net_device */
1289 dev_set_drvdata(&ndev->dev, NULL);
1291 /* free bitbang info */
1292 free_mdio_bitbang(bus);
1297 /* MDIO bus init function */
1298 static int sh_mdio_init(struct net_device *ndev, int id)
1301 struct bb_info *bitbang;
1302 struct sh_eth_private *mdp = netdev_priv(ndev);
1304 /* create bit control struct for PHY */
1305 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1312 bitbang->addr = ndev->base_addr + PIR;
1313 bitbang->mdi_msk = 0x08;
1314 bitbang->mdo_msk = 0x04;
1315 bitbang->mmd_msk = 0x02;/* MMD */
1316 bitbang->mdc_msk = 0x01;
1317 bitbang->ctrl.ops = &bb_ops;
1319 /* MII contorller setting */
1320 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1321 if (!mdp->mii_bus) {
1323 goto out_free_bitbang;
1326 /* Hook up MII support for ethtool */
1327 mdp->mii_bus->name = "sh_mii";
1328 mdp->mii_bus->parent = &ndev->dev;
1329 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
1332 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1333 if (!mdp->mii_bus->irq) {
1338 for (i = 0; i < PHY_MAX_ADDR; i++)
1339 mdp->mii_bus->irq[i] = PHY_POLL;
1341 /* regist mdio bus */
1342 ret = mdiobus_register(mdp->mii_bus);
1346 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1351 kfree(mdp->mii_bus->irq);
1354 free_mdio_bitbang(mdp->mii_bus);
1363 static const struct net_device_ops sh_eth_netdev_ops = {
1364 .ndo_open = sh_eth_open,
1365 .ndo_stop = sh_eth_close,
1366 .ndo_start_xmit = sh_eth_start_xmit,
1367 .ndo_get_stats = sh_eth_get_stats,
1368 #if defined(SH_ETH_HAS_TSU)
1369 .ndo_set_multicast_list = sh_eth_set_multicast_list,
1371 .ndo_tx_timeout = sh_eth_tx_timeout,
1372 .ndo_do_ioctl = sh_eth_do_ioctl,
1373 .ndo_validate_addr = eth_validate_addr,
1374 .ndo_set_mac_address = eth_mac_addr,
1375 .ndo_change_mtu = eth_change_mtu,
1378 static int sh_eth_drv_probe(struct platform_device *pdev)
1380 int ret, i, devno = 0;
1381 struct resource *res;
1382 struct net_device *ndev = NULL;
1383 struct sh_eth_private *mdp;
1384 struct sh_eth_plat_data *pd;
1387 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1388 if (unlikely(res == NULL)) {
1389 dev_err(&pdev->dev, "invalid resource\n");
1394 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1396 dev_err(&pdev->dev, "Could not allocate device.\n");
1401 /* The sh Ether-specific entries in the device structure. */
1402 ndev->base_addr = res->start;
1408 ret = platform_get_irq(pdev, 0);
1415 SET_NETDEV_DEV(ndev, &pdev->dev);
1417 /* Fill in the fields of the device structure with ethernet values. */
1420 mdp = netdev_priv(ndev);
1421 spin_lock_init(&mdp->lock);
1423 pm_runtime_enable(&pdev->dev);
1424 pm_runtime_resume(&pdev->dev);
1426 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
1428 mdp->phy_id = pd->phy;
1430 mdp->edmac_endian = pd->edmac_endian;
1431 mdp->no_ether_link = pd->no_ether_link;
1432 mdp->ether_link_active_low = pd->ether_link_active_low;
1435 mdp->cd = &sh_eth_my_cpu_data;
1436 sh_eth_set_default_cpu_data(mdp->cd);
1439 ndev->netdev_ops = &sh_eth_netdev_ops;
1440 ndev->watchdog_timeo = TX_TIMEOUT;
1442 mdp->post_rx = POST_RX >> (devno << 1);
1443 mdp->post_fw = POST_FW >> (devno << 1);
1445 /* read and set MAC address */
1446 read_mac_address(ndev, pd->mac_addr);
1448 /* First device only init */
1450 if (mdp->cd->chip_reset)
1451 mdp->cd->chip_reset(ndev);
1453 #if defined(SH_ETH_HAS_TSU)
1454 /* TSU init (Init only)*/
1455 sh_eth_tsu_init(SH_TSU_ADDR);
1459 /* network device register */
1460 ret = register_netdev(ndev);
1465 ret = sh_mdio_init(ndev, pdev->id);
1467 goto out_unregister;
1469 /* pritnt device infomation */
1470 pr_info("Base address at 0x%x, ",
1471 (u32)ndev->base_addr);
1473 for (i = 0; i < 5; i++)
1474 printk("%02X:", ndev->dev_addr[i]);
1475 printk("%02X, IRQ %d.\n", ndev->dev_addr[i], ndev->irq);
1477 platform_set_drvdata(pdev, ndev);
1482 unregister_netdev(ndev);
1493 static int sh_eth_drv_remove(struct platform_device *pdev)
1495 struct net_device *ndev = platform_get_drvdata(pdev);
1497 sh_mdio_release(ndev);
1498 unregister_netdev(ndev);
1499 flush_scheduled_work();
1500 pm_runtime_disable(&pdev->dev);
1502 platform_set_drvdata(pdev, NULL);
1507 static int sh_eth_runtime_nop(struct device *dev)
1510 * Runtime PM callback shared between ->runtime_suspend()
1511 * and ->runtime_resume(). Simply returns success.
1513 * This driver re-initializes all registers after
1514 * pm_runtime_get_sync() anyway so there is no need
1515 * to save and restore registers here.
1520 static struct dev_pm_ops sh_eth_dev_pm_ops = {
1521 .runtime_suspend = sh_eth_runtime_nop,
1522 .runtime_resume = sh_eth_runtime_nop,
1525 static struct platform_driver sh_eth_driver = {
1526 .probe = sh_eth_drv_probe,
1527 .remove = sh_eth_drv_remove,
1530 .pm = &sh_eth_dev_pm_ops,
1534 static int __init sh_eth_init(void)
1536 return platform_driver_register(&sh_eth_driver);
1539 static void __exit sh_eth_cleanup(void)
1541 platform_driver_unregister(&sh_eth_driver);
1544 module_init(sh_eth_init);
1545 module_exit(sh_eth_cleanup);
1547 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1548 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1549 MODULE_LICENSE("GPL v2");