drivers/net/sh_eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * sh_eth.c - Driver for Renesas ethernet controller.
   4  *
   5  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
   6  * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
   7  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   8  * Copyright (C) 2013, 2014 Renesas Electronics Corporation
   9  */
  10
  11 #include <config.h>
  12 #include <cpu_func.h>
  13 #include <env.h>
  14 #include <log.h>
  15 #include <malloc.h>
  16 #include <net.h>
  17 #include <netdev.h>
  18 #include <miiphy.h>
  19 #include <asm/cache.h>
  20 #include <linux/delay.h>
  21 #include <linux/errno.h>
  22 #include <asm/global_data.h>
  23 #include <asm/io.h>
  24
  25 #include <clk.h>
  26 #include <dm.h>
  27 #include <linux/mii.h>
  28 #include <asm/gpio.h>
  29
  30 #include "sh_eth.h"
  31
  32 #ifndef CFG_SH_ETHER_USE_PORT
  33 # error "Please define CFG_SH_ETHER_USE_PORT"
  34 #endif
  35 #ifndef CFG_SH_ETHER_PHY_ADDR
  36 # error "Please define CFG_SH_ETHER_PHY_ADDR"
  37 #endif
  38
  39 #if defined(CFG_SH_ETHER_CACHE_WRITEBACK) && \
  40         !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  41 #define flush_cache_wback(addr, len)    \
  42                 flush_dcache_range((unsigned long)addr, \
  43                 (unsigned long)(addr + ALIGN(len, CFG_SH_ETHER_ALIGNE_SIZE)))
  44 #else
  45 #define flush_cache_wback(...)
  46 #endif
  47
  48 #if defined(CFG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
  49 #define invalidate_cache(addr, len)             \
  50         {       \
  51                 unsigned long line_size = CFG_SH_ETHER_ALIGNE_SIZE;     \
  52                 unsigned long start, end;       \
  53                 \
  54                 start = (unsigned long)addr;    \
  55                 end = start + len;              \
  56                 start &= ~(line_size - 1);      \
  57                 end = ((end + line_size - 1) & ~(line_size - 1));       \
  58                 \
  59                 invalidate_dcache_range(start, end);    \
  60         }
  61 #else
  62 #define invalidate_cache(...)
  63 #endif
  64
  65 #define TIMEOUT_CNT 1000
  66
  67 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
  68 {
  69         int ret = 0, timeout;
  70         struct sh_eth_info *port_info = &eth->port_info[eth->port];
  71
  72         if (!packet || len > 0xffff) {
  73                 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
  74                 ret = -EINVAL;
  75                 goto err;
  76         }
  77
  78         /* packet must be a 4 byte boundary */
  79         if ((uintptr_t)packet & 3) {
  80                 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
  81                                 , __func__);
  82                 ret = -EFAULT;
  83                 goto err;
  84         }
  85
  86         /* Update tx descriptor */
  87         flush_cache_wback(packet, len);
  88         port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
  89         port_info->tx_desc_cur->td1 = len << 16;
  90         /* Must preserve the end of descriptor list indication */
  91         if (port_info->tx_desc_cur->td0 & TD_TDLE)
  92                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
  93         else
  94                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
  95
  96         flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
  97
  98         /* Restart the transmitter if disabled */
  99         if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
 100                 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
 101
 102         /* Wait until packet is transmitted */
 103         timeout = TIMEOUT_CNT;
 104         do {
 105                 invalidate_cache(port_info->tx_desc_cur,
 106                                  sizeof(struct tx_desc_s));
 107                 udelay(100);
 108         } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
 109
 110         if (timeout < 0) {
 111                 printf(SHETHER_NAME ": transmit timeout\n");
 112                 ret = -ETIMEDOUT;
 113                 goto err;
 114         }
 115
 116         port_info->tx_desc_cur++;
 117         if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
 118                 port_info->tx_desc_cur = port_info->tx_desc_base;
 119
 120 err:
 121         return ret;
 122 }
 123
 124 static int sh_eth_recv_start(struct sh_eth_dev *eth)
 125 {
 126         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 127
 128         /* Check if the rx descriptor is ready */
 129         invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
 130         if (port_info->rx_desc_cur->rd0 & RD_RACT)
 131                 return -EAGAIN;
 132
 133         /* Check for errors */
 134         if (port_info->rx_desc_cur->rd0 & RD_RFE)
 135                 return 0;
 136
 137         return port_info->rx_desc_cur->rd1 & 0xffff;
 138 }
 139
 140 static void sh_eth_recv_finish(struct sh_eth_dev *eth)
 141 {
 142         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 143
 144         invalidate_cache(ADDR_TO_P2(port_info->rx_desc_cur->rd2), MAX_BUF_SIZE);
 145
 146         /* Make current descriptor available again */
 147         if (port_info->rx_desc_cur->rd0 & RD_RDLE)
 148                 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
 149         else
 150                 port_info->rx_desc_cur->rd0 = RD_RACT;
 151
 152         flush_cache_wback(port_info->rx_desc_cur,
 153                           sizeof(struct rx_desc_s));
 154
 155         /* Point to the next descriptor */
 156         port_info->rx_desc_cur++;
 157         if (port_info->rx_desc_cur >=
 158             port_info->rx_desc_base + NUM_RX_DESC)
 159                 port_info->rx_desc_cur = port_info->rx_desc_base;
 160 }
 161
 162 static int sh_eth_reset(struct sh_eth_dev *eth)
 163 {
 164         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 165 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 166         int ret = 0, i;
 167
 168         /* Start e-dmac transmitter and receiver */
 169         sh_eth_write(port_info, EDSR_ENALL, EDSR);
 170
 171         /* Perform a software reset and wait for it to complete */
 172         sh_eth_write(port_info, EDMR_SRST, EDMR);
 173         for (i = 0; i < TIMEOUT_CNT; i++) {
 174                 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
 175                         break;
 176                 udelay(1000);
 177         }
 178
 179         if (i == TIMEOUT_CNT) {
 180                 printf(SHETHER_NAME  ": Software reset timeout\n");
 181                 ret = -EIO;
 182         }
 183
 184         return ret;
 185 #else
 186         sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
 187         mdelay(3);
 188         sh_eth_write(port_info,
 189                      sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
 190
 191         return 0;
 192 #endif
 193 }
 194
 195 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 196 {
 197         int i, ret = 0;
 198         u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
 199         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 200         struct tx_desc_s *cur_tx_desc;
 201
 202         /*
 203          * Allocate rx descriptors. They must be aligned to size of struct
 204          * tx_desc_s.
 205          */
 206         port_info->tx_desc_alloc =
 207                 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
 208         if (!port_info->tx_desc_alloc) {
 209                 printf(SHETHER_NAME ": memalign failed\n");
 210                 ret = -ENOMEM;
 211                 goto err;
 212         }
 213
 214         /* Make sure we use a P2 address (non-cacheable) */
 215         port_info->tx_desc_base =
 216                 (struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
 217         port_info->tx_desc_cur = port_info->tx_desc_base;
 218
 219         /* Initialize all descriptors */
 220         for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
 221              cur_tx_desc++, i++) {
 222                 cur_tx_desc->td0 = 0x00;
 223                 cur_tx_desc->td1 = 0x00;
 224                 cur_tx_desc->td2 = 0x00;
 225         }
 226
 227         /* Mark the end of the descriptors */
 228         cur_tx_desc--;
 229         cur_tx_desc->td0 |= TD_TDLE;
 230
 231         flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
 232         /*
 233          * Point the controller to the tx descriptor list. Must use physical
 234          * addresses
 235          */
 236         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
 237 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 238         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
 239         sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
 240         sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
 241 #endif
 242
 243 err:
 244         return ret;
 245 }
 246
 247 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 248 {
 249         int i, ret = 0;
 250         u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
 251         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 252         struct rx_desc_s *cur_rx_desc;
 253         u8 *rx_buf;
 254
 255         /*
 256          * Allocate rx descriptors. They must be aligned to size of struct
 257          * rx_desc_s.
 258          */
 259         port_info->rx_desc_alloc =
 260                 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
 261         if (!port_info->rx_desc_alloc) {
 262                 printf(SHETHER_NAME ": memalign failed\n");
 263                 ret = -ENOMEM;
 264                 goto err;
 265         }
 266
 267         /* Make sure we use a P2 address (non-cacheable) */
 268         port_info->rx_desc_base =
 269                 (struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
 270
 271         port_info->rx_desc_cur = port_info->rx_desc_base;
 272
 273         /*
 274          * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
 275          * aligned and in P2 area.
 276          */
 277         port_info->rx_buf_alloc =
 278                 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
 279         if (!port_info->rx_buf_alloc) {
 280                 printf(SHETHER_NAME ": alloc failed\n");
 281                 ret = -ENOMEM;
 282                 goto err_buf_alloc;
 283         }
 284
 285         port_info->rx_buf_base = (u8 *)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
 286
 287         /* Initialize all descriptors */
 288         for (cur_rx_desc = port_info->rx_desc_base,
 289              rx_buf = port_info->rx_buf_base, i = 0;
 290              i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
 291                 cur_rx_desc->rd0 = RD_RACT;
 292                 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
 293                 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
 294         }
 295
 296         /* Mark the end of the descriptors */
 297         cur_rx_desc--;
 298         cur_rx_desc->rd0 |= RD_RDLE;
 299
 300         invalidate_cache(port_info->rx_buf_alloc, NUM_RX_DESC * MAX_BUF_SIZE);
 301         flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
 302
 303         /* Point the controller to the rx descriptor list */
 304         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
 305 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 306         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
 307         sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
 308         sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
 309 #endif
 310
 311         return ret;
 312
 313 err_buf_alloc:
 314         free(port_info->rx_desc_alloc);
 315         port_info->rx_desc_alloc = NULL;
 316
 317 err:
 318         return ret;
 319 }
 320
 321 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
 322 {
 323         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 324
 325         if (port_info->tx_desc_alloc) {
 326                 free(port_info->tx_desc_alloc);
 327                 port_info->tx_desc_alloc = NULL;
 328         }
 329 }
 330
 331 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
 332 {
 333         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 334
 335         if (port_info->rx_desc_alloc) {
 336                 free(port_info->rx_desc_alloc);
 337                 port_info->rx_desc_alloc = NULL;
 338         }
 339
 340         if (port_info->rx_buf_alloc) {
 341                 free(port_info->rx_buf_alloc);
 342                 port_info->rx_buf_alloc = NULL;
 343         }
 344 }
 345
 346 static int sh_eth_desc_init(struct sh_eth_dev *eth)
 347 {
 348         int ret = 0;
 349
 350         ret = sh_eth_tx_desc_init(eth);
 351         if (ret)
 352                 goto err_tx_init;
 353
 354         ret = sh_eth_rx_desc_init(eth);
 355         if (ret)
 356                 goto err_rx_init;
 357
 358         return ret;
 359 err_rx_init:
 360         sh_eth_tx_desc_free(eth);
 361
 362 err_tx_init:
 363         return ret;
 364 }
 365
 366 static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
 367                                 unsigned char *mac)
 368 {
 369         u32 val;
 370
 371         val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
 372         sh_eth_write(port_info, val, MAHR);
 373
 374         val = (mac[4] << 8) | mac[5];
 375         sh_eth_write(port_info, val, MALR);
 376 }
 377
 378 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
 379 {
 380         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 381         unsigned long edmr;
 382
 383         /* Configure e-dmac registers */
 384         edmr = sh_eth_read(port_info, EDMR);
 385         edmr &= ~EMDR_DESC_R;
 386         edmr |= EMDR_DESC | EDMR_EL;
 387 #if defined(CONFIG_R8A77980)
 388         edmr |= EDMR_NBST;
 389 #endif
 390         sh_eth_write(port_info, edmr, EDMR);
 391
 392         sh_eth_write(port_info, 0, EESIPR);
 393         sh_eth_write(port_info, 0, TRSCER);
 394         sh_eth_write(port_info, 0, TFTR);
 395         sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
 396         sh_eth_write(port_info, RMCR_RST, RMCR);
 397 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 398         sh_eth_write(port_info, 0, RPADIR);
 399 #endif
 400         sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
 401
 402         /* Configure e-mac registers */
 403         sh_eth_write(port_info, 0, ECSIPR);
 404
 405         /* Set Mac address */
 406         sh_eth_write_hwaddr(port_info, mac);
 407
 408         sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
 409 #if defined(SH_ETH_TYPE_GETHER)
 410         sh_eth_write(port_info, 0, PIPR);
 411 #endif
 412 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 413         sh_eth_write(port_info, APR_AP, APR);
 414         sh_eth_write(port_info, MPR_MP, MPR);
 415         sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
 416 #endif
 417
 418 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 419         sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 420 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
 421         sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
 422 #endif
 423 }
 424
 425 static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
 426 {
 427         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 428         struct phy_device *phy = port_info->phydev;
 429         int ret = 0;
 430         u32 val = 0;
 431
 432         /* Set the transfer speed */
 433         if (phy->speed == 100) {
 434                 printf(SHETHER_NAME ": 100Base/");
 435 #if defined(SH_ETH_TYPE_GETHER)
 436                 sh_eth_write(port_info, GECMR_100B, GECMR);
 437 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 438                 sh_eth_write(port_info, 1, RTRATE);
 439 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
 440                 val = ECMR_RTM;
 441 #endif
 442         } else if (phy->speed == 10) {
 443                 printf(SHETHER_NAME ": 10Base/");
 444 #if defined(SH_ETH_TYPE_GETHER)
 445                 sh_eth_write(port_info, GECMR_10B, GECMR);
 446 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 447                 sh_eth_write(port_info, 0, RTRATE);
 448 #endif
 449         }
 450 #if defined(SH_ETH_TYPE_GETHER)
 451         else if (phy->speed == 1000) {
 452                 printf(SHETHER_NAME ": 1000Base/");
 453                 sh_eth_write(port_info, GECMR_1000B, GECMR);
 454         }
 455 #endif
 456
 457         /* Check if full duplex mode is supported by the phy */
 458         if (phy->duplex) {
 459                 printf("Full\n");
 460                 sh_eth_write(port_info,
 461                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
 462                              ECMR);
 463         } else {
 464                 printf("Half\n");
 465                 sh_eth_write(port_info,
 466                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
 467                              ECMR);
 468         }
 469
 470         return ret;
 471 }
 472
 473 static void sh_eth_start(struct sh_eth_dev *eth)
 474 {
 475         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 476
 477         /*
 478          * Enable the e-dmac receiver only. The transmitter will be enabled when
 479          * we have something to transmit
 480          */
 481         sh_eth_write(port_info, EDRRR_R, EDRRR);
 482 }
 483
 484 static void sh_eth_stop(struct sh_eth_dev *eth)
 485 {
 486         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 487
 488         sh_eth_write(port_info, ~EDRRR_R, EDRRR);
 489 }
 490
 491 static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
 492 {
 493         int ret = 0;
 494
 495         ret = sh_eth_reset(eth);
 496         if (ret)
 497                 return ret;
 498
 499         ret = sh_eth_desc_init(eth);
 500         if (ret)
 501                 return ret;
 502
 503         sh_eth_mac_regs_config(eth, mac);
 504
 505         return 0;
 506 }
 507
 508 static int sh_eth_start_common(struct sh_eth_dev *eth)
 509 {
 510         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 511         int ret;
 512
 513         ret = phy_startup(port_info->phydev);
 514         if (ret) {
 515                 printf(SHETHER_NAME ": phy startup failure\n");
 516                 return ret;
 517         }
 518
 519         ret = sh_eth_phy_regs_config(eth);
 520         if (ret)
 521                 return ret;
 522
 523         sh_eth_start(eth);
 524
 525         return 0;
 526 }
 527
 528 struct sh_ether_priv {
 529         struct sh_eth_dev       shdev;
 530
 531         struct mii_dev          *bus;
 532         phys_addr_t             iobase;
 533         struct clk              clk;
 534 };
 535
 536 static int sh_ether_send(struct udevice *dev, void *packet, int len)
 537 {
 538         struct sh_ether_priv *priv = dev_get_priv(dev);
 539         struct sh_eth_dev *eth = &priv->shdev;
 540
 541         return sh_eth_send_common(eth, packet, len);
 542 }
 543
 544 static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
 545 {
 546         struct sh_ether_priv *priv = dev_get_priv(dev);
 547         struct sh_eth_dev *eth = &priv->shdev;
 548         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 549         uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
 550         int len;
 551
 552         len = sh_eth_recv_start(eth);
 553         if (len > 0) {
 554                 invalidate_cache(packet, len);
 555                 *packetp = packet;
 556
 557                 return len;
 558         }
 559
 560         /* Restart the receiver if disabled */
 561         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 562                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 563
 564         return len;
 565 }
 566
 567 static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
 568 {
 569         struct sh_ether_priv *priv = dev_get_priv(dev);
 570         struct sh_eth_dev *eth = &priv->shdev;
 571         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 572
 573         sh_eth_recv_finish(eth);
 574
 575         /* Restart the receiver if disabled */
 576         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 577                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 578
 579         return 0;
 580 }
 581
 582 static int sh_ether_write_hwaddr(struct udevice *dev)
 583 {
 584         struct sh_ether_priv *priv = dev_get_priv(dev);
 585         struct sh_eth_dev *eth = &priv->shdev;
 586         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 587         struct eth_pdata *pdata = dev_get_plat(dev);
 588
 589         sh_eth_write_hwaddr(port_info, pdata->enetaddr);
 590
 591         return 0;
 592 }
 593
 594 static int sh_eth_phy_config(struct udevice *dev)
 595 {
 596         struct sh_ether_priv *priv = dev_get_priv(dev);
 597         struct eth_pdata *pdata = dev_get_plat(dev);
 598         struct sh_eth_dev *eth = &priv->shdev;
 599         int ret = 0;
 600         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 601         struct phy_device *phydev;
 602
 603         phydev = phy_connect(priv->bus, -1, dev, pdata->phy_interface);
 604         if (!phydev)
 605                 return -ENODEV;
 606
 607         port_info->phydev = phydev;
 608         phy_config(phydev);
 609
 610         return ret;
 611 }
 612
 613 static int sh_ether_start(struct udevice *dev)
 614 {
 615         struct sh_ether_priv *priv = dev_get_priv(dev);
 616         struct eth_pdata *pdata = dev_get_plat(dev);
 617         struct sh_eth_dev *eth = &priv->shdev;
 618         int ret;
 619
 620         ret = sh_eth_init_common(eth, pdata->enetaddr);
 621         if (ret)
 622                 return ret;
 623
 624         ret = sh_eth_start_common(eth);
 625         if (ret)
 626                 goto err_start;
 627
 628         return 0;
 629
 630 err_start:
 631         sh_eth_tx_desc_free(eth);
 632         sh_eth_rx_desc_free(eth);
 633         return ret;
 634 }
 635
 636 static void sh_ether_stop(struct udevice *dev)
 637 {
 638         struct sh_ether_priv *priv = dev_get_priv(dev);
 639         struct sh_eth_dev *eth = &priv->shdev;
 640         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 641
 642         phy_shutdown(port_info->phydev);
 643         sh_eth_stop(&priv->shdev);
 644 }
 645
 646 static int sh_ether_probe(struct udevice *udev)
 647 {
 648         struct eth_pdata *pdata = dev_get_plat(udev);
 649         struct sh_ether_priv *priv = dev_get_priv(udev);
 650         struct sh_eth_dev *eth = &priv->shdev;
 651         struct mii_dev *mdiodev;
 652         int ret;
 653
 654         priv->iobase = pdata->iobase;
 655
 656 #if CONFIG_IS_ENABLED(CLK)
 657         ret = clk_get_by_index(udev, 0, &priv->clk);
 658         if (ret < 0)
 659                 return ret;
 660 #endif
 661         mdiodev = mdio_alloc();
 662         if (!mdiodev) {
 663                 ret = -ENOMEM;
 664                 return ret;
 665         }
 666
 667         mdiodev->read = bb_miiphy_read;
 668         mdiodev->write = bb_miiphy_write;
 669         bb_miiphy_buses[0].priv = eth;
 670         snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
 671
 672         ret = mdio_register(mdiodev);
 673         if (ret < 0)
 674                 goto err_mdio_register;
 675
 676         priv->bus = miiphy_get_dev_by_name(udev->name);
 677
 678         eth->port = CFG_SH_ETHER_USE_PORT;
 679         eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR;
 680         eth->port_info[eth->port].iobase =
 681                 (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
 682
 683 #if CONFIG_IS_ENABLED(CLK)
 684         ret = clk_enable(&priv->clk);
 685         if (ret)
 686                 goto err_mdio_register;
 687 #endif
 688
 689         ret = sh_eth_init_common(eth, pdata->enetaddr);
 690         if (ret)
 691                 goto err_phy_config;
 692
 693         ret = sh_eth_phy_config(udev);
 694         if (ret) {
 695                 printf(SHETHER_NAME ": phy config timeout\n");
 696                 goto err_phy_config;
 697         }
 698
 699         return 0;
 700
 701 err_phy_config:
 702 #if CONFIG_IS_ENABLED(CLK)
 703         clk_disable(&priv->clk);
 704 #endif
 705 err_mdio_register:
 706         mdio_free(mdiodev);
 707         return ret;
 708 }
 709
 710 static int sh_ether_remove(struct udevice *udev)
 711 {
 712         struct sh_ether_priv *priv = dev_get_priv(udev);
 713         struct sh_eth_dev *eth = &priv->shdev;
 714         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 715
 716 #if CONFIG_IS_ENABLED(CLK)
 717         clk_disable(&priv->clk);
 718 #endif
 719         free(port_info->phydev);
 720         mdio_unregister(priv->bus);
 721         mdio_free(priv->bus);
 722
 723         return 0;
 724 }
 725
 726 static const struct eth_ops sh_ether_ops = {
 727         .start                  = sh_ether_start,
 728         .send                   = sh_ether_send,
 729         .recv                   = sh_ether_recv,
 730         .free_pkt               = sh_ether_free_pkt,
 731         .stop                   = sh_ether_stop,
 732         .write_hwaddr           = sh_ether_write_hwaddr,
 733 };
 734
 735 int sh_ether_of_to_plat(struct udevice *dev)
 736 {
 737         struct eth_pdata *pdata = dev_get_plat(dev);
 738         const fdt32_t *cell;
 739
 740         pdata->iobase = dev_read_addr(dev);
 741
 742         pdata->phy_interface = dev_read_phy_mode(dev);
 743         if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
 744                 return -EINVAL;
 745
 746         pdata->max_speed = 1000;
 747         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
 748         if (cell)
 749                 pdata->max_speed = fdt32_to_cpu(*cell);
 750
 751         sprintf(bb_miiphy_buses[0].name, dev->name);
 752
 753         return 0;
 754 }
 755
 756 static const struct udevice_id sh_ether_ids[] = {
 757         { .compatible = "renesas,ether-r7s72100" },
 758         { .compatible = "renesas,ether-r8a7790" },
 759         { .compatible = "renesas,ether-r8a7791" },
 760         { .compatible = "renesas,ether-r8a7793" },
 761         { .compatible = "renesas,ether-r8a7794" },
 762         { .compatible = "renesas,gether-r8a77980" },
 763         { }
 764 };
 765
 766 U_BOOT_DRIVER(eth_sh_ether) = {
 767         .name           = "sh_ether",
 768         .id             = UCLASS_ETH,
 769         .of_match       = sh_ether_ids,
 770         .of_to_plat = sh_ether_of_to_plat,
 771         .probe          = sh_ether_probe,
 772         .remove         = sh_ether_remove,
 773         .ops            = &sh_ether_ops,
 774         .priv_auto      = sizeof(struct sh_ether_priv),
 775         .plat_auto      = sizeof(struct eth_pdata),
 776         .flags          = DM_FLAG_ALLOC_PRIV_DMA,
 777 };
 778
 779 /******* for bb_miiphy *******/
 780 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 781 {
 782         return 0;
 783 }
 784
 785 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 786 {
 787         struct sh_eth_dev *eth = bus->priv;
 788         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 789
 790         sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
 791
 792         return 0;
 793 }
 794
 795 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 796 {
 797         struct sh_eth_dev *eth = bus->priv;
 798         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 799
 800         sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
 801
 802         return 0;
 803 }
 804
 805 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 806 {
 807         struct sh_eth_dev *eth = bus->priv;
 808         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 809
 810         if (v)
 811                 sh_eth_write(port_info,
 812                              sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
 813         else
 814                 sh_eth_write(port_info,
 815                              sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
 816
 817         return 0;
 818 }
 819
 820 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
 821 {
 822         struct sh_eth_dev *eth = bus->priv;
 823         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 824
 825         *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
 826
 827         return 0;
 828 }
 829
 830 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
 831 {
 832         struct sh_eth_dev *eth = bus->priv;
 833         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 834
 835         if (v)
 836                 sh_eth_write(port_info,
 837                              sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
 838         else
 839                 sh_eth_write(port_info,
 840                              sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
 841
 842         return 0;
 843 }
 844
 845 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
 846 {
 847         udelay(10);
 848
 849         return 0;
 850 }
 851
 852 struct bb_miiphy_bus bb_miiphy_buses[] = {
 853         {
 854                 .name           = "sh_eth",
 855                 .init           = sh_eth_bb_init,
 856                 .mdio_active    = sh_eth_bb_mdio_active,
 857                 .mdio_tristate  = sh_eth_bb_mdio_tristate,
 858                 .set_mdio       = sh_eth_bb_set_mdio,
 859                 .get_mdio       = sh_eth_bb_get_mdio,
 860                 .set_mdc        = sh_eth_bb_set_mdc,
 861                 .delay          = sh_eth_bb_delay,
 862         }
 863 };
 864
 865 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);