drivers/net/sh_eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * sh_eth.c - Driver for Renesas ethernet controller.
   4  *
   5  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
   6  * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
   7  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   8  * Copyright (C) 2013, 2014 Renesas Electronics Corporation
   9  */
  10
  11 #include <config.h>
  12 #include <common.h>
  13 #include <cpu_func.h>
  14 #include <env.h>
  15 #include <log.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <netdev.h>
  19 #include <miiphy.h>
  20 #include <asm/cache.h>
  21 #include <linux/delay.h>
  22 #include <linux/errno.h>
  23 #include <asm/global_data.h>
  24 #include <asm/io.h>
  25
  26 #include <clk.h>
  27 #include <dm.h>
  28 #include <linux/mii.h>
  29 #include <asm/gpio.h>
  30
  31 #include "sh_eth.h"
  32
  33 #ifndef CFG_SH_ETHER_USE_PORT
  34 # error "Please define CFG_SH_ETHER_USE_PORT"
  35 #endif
  36 #ifndef CFG_SH_ETHER_PHY_ADDR
  37 # error "Please define CFG_SH_ETHER_PHY_ADDR"
  38 #endif
  39
  40 #if defined(CFG_SH_ETHER_CACHE_WRITEBACK) && \
  41         !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  42 #define flush_cache_wback(addr, len)    \
  43                 flush_dcache_range((unsigned long)addr, \
  44                 (unsigned long)(addr + ALIGN(len, CFG_SH_ETHER_ALIGNE_SIZE)))
  45 #else
  46 #define flush_cache_wback(...)
  47 #endif
  48
  49 #if defined(CFG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
  50 #define invalidate_cache(addr, len)             \
  51         {       \
  52                 unsigned long line_size = CFG_SH_ETHER_ALIGNE_SIZE;     \
  53                 unsigned long start, end;       \
  54                 \
  55                 start = (unsigned long)addr;    \
  56                 end = start + len;              \
  57                 start &= ~(line_size - 1);      \
  58                 end = ((end + line_size - 1) & ~(line_size - 1));       \
  59                 \
  60                 invalidate_dcache_range(start, end);    \
  61         }
  62 #else
  63 #define invalidate_cache(...)
  64 #endif
  65
  66 #define TIMEOUT_CNT 1000
  67
  68 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
  69 {
  70         int ret = 0, timeout;
  71         struct sh_eth_info *port_info = &eth->port_info[eth->port];
  72
  73         if (!packet || len > 0xffff) {
  74                 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
  75                 ret = -EINVAL;
  76                 goto err;
  77         }
  78
  79         /* packet must be a 4 byte boundary */
  80         if ((uintptr_t)packet & 3) {
  81                 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
  82                                 , __func__);
  83                 ret = -EFAULT;
  84                 goto err;
  85         }
  86
  87         /* Update tx descriptor */
  88         flush_cache_wback(packet, len);
  89         port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
  90         port_info->tx_desc_cur->td1 = len << 16;
  91         /* Must preserve the end of descriptor list indication */
  92         if (port_info->tx_desc_cur->td0 & TD_TDLE)
  93                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
  94         else
  95                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
  96
  97         flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
  98
  99         /* Restart the transmitter if disabled */
 100         if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
 101                 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
 102
 103         /* Wait until packet is transmitted */
 104         timeout = TIMEOUT_CNT;
 105         do {
 106                 invalidate_cache(port_info->tx_desc_cur,
 107                                  sizeof(struct tx_desc_s));
 108                 udelay(100);
 109         } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
 110
 111         if (timeout < 0) {
 112                 printf(SHETHER_NAME ": transmit timeout\n");
 113                 ret = -ETIMEDOUT;
 114                 goto err;
 115         }
 116
 117         port_info->tx_desc_cur++;
 118         if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
 119                 port_info->tx_desc_cur = port_info->tx_desc_base;
 120
 121 err:
 122         return ret;
 123 }
 124
 125 static int sh_eth_recv_start(struct sh_eth_dev *eth)
 126 {
 127         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 128
 129         /* Check if the rx descriptor is ready */
 130         invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
 131         if (port_info->rx_desc_cur->rd0 & RD_RACT)
 132                 return -EAGAIN;
 133
 134         /* Check for errors */
 135         if (port_info->rx_desc_cur->rd0 & RD_RFE)
 136                 return 0;
 137
 138         return port_info->rx_desc_cur->rd1 & 0xffff;
 139 }
 140
 141 static void sh_eth_recv_finish(struct sh_eth_dev *eth)
 142 {
 143         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 144
 145         invalidate_cache(ADDR_TO_P2(port_info->rx_desc_cur->rd2), MAX_BUF_SIZE);
 146
 147         /* Make current descriptor available again */
 148         if (port_info->rx_desc_cur->rd0 & RD_RDLE)
 149                 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
 150         else
 151                 port_info->rx_desc_cur->rd0 = RD_RACT;
 152
 153         flush_cache_wback(port_info->rx_desc_cur,
 154                           sizeof(struct rx_desc_s));
 155
 156         /* Point to the next descriptor */
 157         port_info->rx_desc_cur++;
 158         if (port_info->rx_desc_cur >=
 159             port_info->rx_desc_base + NUM_RX_DESC)
 160                 port_info->rx_desc_cur = port_info->rx_desc_base;
 161 }
 162
 163 static int sh_eth_reset(struct sh_eth_dev *eth)
 164 {
 165         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 166 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 167         int ret = 0, i;
 168
 169         /* Start e-dmac transmitter and receiver */
 170         sh_eth_write(port_info, EDSR_ENALL, EDSR);
 171
 172         /* Perform a software reset and wait for it to complete */
 173         sh_eth_write(port_info, EDMR_SRST, EDMR);
 174         for (i = 0; i < TIMEOUT_CNT; i++) {
 175                 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
 176                         break;
 177                 udelay(1000);
 178         }
 179
 180         if (i == TIMEOUT_CNT) {
 181                 printf(SHETHER_NAME  ": Software reset timeout\n");
 182                 ret = -EIO;
 183         }
 184
 185         return ret;
 186 #else
 187         sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
 188         mdelay(3);
 189         sh_eth_write(port_info,
 190                      sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
 191
 192         return 0;
 193 #endif
 194 }
 195
 196 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 197 {
 198         int i, ret = 0;
 199         u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
 200         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 201         struct tx_desc_s *cur_tx_desc;
 202
 203         /*
 204          * Allocate rx descriptors. They must be aligned to size of struct
 205          * tx_desc_s.
 206          */
 207         port_info->tx_desc_alloc =
 208                 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
 209         if (!port_info->tx_desc_alloc) {
 210                 printf(SHETHER_NAME ": memalign failed\n");
 211                 ret = -ENOMEM;
 212                 goto err;
 213         }
 214
 215         /* Make sure we use a P2 address (non-cacheable) */
 216         port_info->tx_desc_base =
 217                 (struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
 218         port_info->tx_desc_cur = port_info->tx_desc_base;
 219
 220         /* Initialize all descriptors */
 221         for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
 222              cur_tx_desc++, i++) {
 223                 cur_tx_desc->td0 = 0x00;
 224                 cur_tx_desc->td1 = 0x00;
 225                 cur_tx_desc->td2 = 0x00;
 226         }
 227
 228         /* Mark the end of the descriptors */
 229         cur_tx_desc--;
 230         cur_tx_desc->td0 |= TD_TDLE;
 231
 232         flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
 233         /*
 234          * Point the controller to the tx descriptor list. Must use physical
 235          * addresses
 236          */
 237         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
 238 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 239         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
 240         sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
 241         sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
 242 #endif
 243
 244 err:
 245         return ret;
 246 }
 247
 248 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 249 {
 250         int i, ret = 0;
 251         u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
 252         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 253         struct rx_desc_s *cur_rx_desc;
 254         u8 *rx_buf;
 255
 256         /*
 257          * Allocate rx descriptors. They must be aligned to size of struct
 258          * rx_desc_s.
 259          */
 260         port_info->rx_desc_alloc =
 261                 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
 262         if (!port_info->rx_desc_alloc) {
 263                 printf(SHETHER_NAME ": memalign failed\n");
 264                 ret = -ENOMEM;
 265                 goto err;
 266         }
 267
 268         /* Make sure we use a P2 address (non-cacheable) */
 269         port_info->rx_desc_base =
 270                 (struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
 271
 272         port_info->rx_desc_cur = port_info->rx_desc_base;
 273
 274         /*
 275          * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
 276          * aligned and in P2 area.
 277          */
 278         port_info->rx_buf_alloc =
 279                 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
 280         if (!port_info->rx_buf_alloc) {
 281                 printf(SHETHER_NAME ": alloc failed\n");
 282                 ret = -ENOMEM;
 283                 goto err_buf_alloc;
 284         }
 285
 286         port_info->rx_buf_base = (u8 *)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
 287
 288         /* Initialize all descriptors */
 289         for (cur_rx_desc = port_info->rx_desc_base,
 290              rx_buf = port_info->rx_buf_base, i = 0;
 291              i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
 292                 cur_rx_desc->rd0 = RD_RACT;
 293                 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
 294                 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
 295         }
 296
 297         /* Mark the end of the descriptors */
 298         cur_rx_desc--;
 299         cur_rx_desc->rd0 |= RD_RDLE;
 300
 301         invalidate_cache(port_info->rx_buf_alloc, NUM_RX_DESC * MAX_BUF_SIZE);
 302         flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
 303
 304         /* Point the controller to the rx descriptor list */
 305         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
 306 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 307         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
 308         sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
 309         sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
 310 #endif
 311
 312         return ret;
 313
 314 err_buf_alloc:
 315         free(port_info->rx_desc_alloc);
 316         port_info->rx_desc_alloc = NULL;
 317
 318 err:
 319         return ret;
 320 }
 321
 322 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
 323 {
 324         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 325
 326         if (port_info->tx_desc_alloc) {
 327                 free(port_info->tx_desc_alloc);
 328                 port_info->tx_desc_alloc = NULL;
 329         }
 330 }
 331
 332 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
 333 {
 334         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 335
 336         if (port_info->rx_desc_alloc) {
 337                 free(port_info->rx_desc_alloc);
 338                 port_info->rx_desc_alloc = NULL;
 339         }
 340
 341         if (port_info->rx_buf_alloc) {
 342                 free(port_info->rx_buf_alloc);
 343                 port_info->rx_buf_alloc = NULL;
 344         }
 345 }
 346
 347 static int sh_eth_desc_init(struct sh_eth_dev *eth)
 348 {
 349         int ret = 0;
 350
 351         ret = sh_eth_tx_desc_init(eth);
 352         if (ret)
 353                 goto err_tx_init;
 354
 355         ret = sh_eth_rx_desc_init(eth);
 356         if (ret)
 357                 goto err_rx_init;
 358
 359         return ret;
 360 err_rx_init:
 361         sh_eth_tx_desc_free(eth);
 362
 363 err_tx_init:
 364         return ret;
 365 }
 366
 367 static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
 368                                 unsigned char *mac)
 369 {
 370         u32 val;
 371
 372         val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
 373         sh_eth_write(port_info, val, MAHR);
 374
 375         val = (mac[4] << 8) | mac[5];
 376         sh_eth_write(port_info, val, MALR);
 377 }
 378
 379 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
 380 {
 381         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 382         unsigned long edmr;
 383
 384         /* Configure e-dmac registers */
 385         edmr = sh_eth_read(port_info, EDMR);
 386         edmr &= ~EMDR_DESC_R;
 387         edmr |= EMDR_DESC | EDMR_EL;
 388 #if defined(CONFIG_R8A77980)
 389         edmr |= EDMR_NBST;
 390 #endif
 391         sh_eth_write(port_info, edmr, EDMR);
 392
 393         sh_eth_write(port_info, 0, EESIPR);
 394         sh_eth_write(port_info, 0, TRSCER);
 395         sh_eth_write(port_info, 0, TFTR);
 396         sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
 397         sh_eth_write(port_info, RMCR_RST, RMCR);
 398 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 399         sh_eth_write(port_info, 0, RPADIR);
 400 #endif
 401         sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
 402
 403         /* Configure e-mac registers */
 404         sh_eth_write(port_info, 0, ECSIPR);
 405
 406         /* Set Mac address */
 407         sh_eth_write_hwaddr(port_info, mac);
 408
 409         sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
 410 #if defined(SH_ETH_TYPE_GETHER)
 411         sh_eth_write(port_info, 0, PIPR);
 412 #endif
 413 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 414         sh_eth_write(port_info, APR_AP, APR);
 415         sh_eth_write(port_info, MPR_MP, MPR);
 416         sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
 417 #endif
 418
 419 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 420         sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 421 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
 422         sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
 423 #endif
 424 }
 425
 426 static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
 427 {
 428         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 429         struct phy_device *phy = port_info->phydev;
 430         int ret = 0;
 431         u32 val = 0;
 432
 433         /* Set the transfer speed */
 434         if (phy->speed == 100) {
 435                 printf(SHETHER_NAME ": 100Base/");
 436 #if defined(SH_ETH_TYPE_GETHER)
 437                 sh_eth_write(port_info, GECMR_100B, GECMR);
 438 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 439                 sh_eth_write(port_info, 1, RTRATE);
 440 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
 441                 val = ECMR_RTM;
 442 #endif
 443         } else if (phy->speed == 10) {
 444                 printf(SHETHER_NAME ": 10Base/");
 445 #if defined(SH_ETH_TYPE_GETHER)
 446                 sh_eth_write(port_info, GECMR_10B, GECMR);
 447 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 448                 sh_eth_write(port_info, 0, RTRATE);
 449 #endif
 450         }
 451 #if defined(SH_ETH_TYPE_GETHER)
 452         else if (phy->speed == 1000) {
 453                 printf(SHETHER_NAME ": 1000Base/");
 454                 sh_eth_write(port_info, GECMR_1000B, GECMR);
 455         }
 456 #endif
 457
 458         /* Check if full duplex mode is supported by the phy */
 459         if (phy->duplex) {
 460                 printf("Full\n");
 461                 sh_eth_write(port_info,
 462                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
 463                              ECMR);
 464         } else {
 465                 printf("Half\n");
 466                 sh_eth_write(port_info,
 467                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
 468                              ECMR);
 469         }
 470
 471         return ret;
 472 }
 473
 474 static void sh_eth_start(struct sh_eth_dev *eth)
 475 {
 476         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 477
 478         /*
 479          * Enable the e-dmac receiver only. The transmitter will be enabled when
 480          * we have something to transmit
 481          */
 482         sh_eth_write(port_info, EDRRR_R, EDRRR);
 483 }
 484
 485 static void sh_eth_stop(struct sh_eth_dev *eth)
 486 {
 487         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 488
 489         sh_eth_write(port_info, ~EDRRR_R, EDRRR);
 490 }
 491
 492 static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
 493 {
 494         int ret = 0;
 495
 496         ret = sh_eth_reset(eth);
 497         if (ret)
 498                 return ret;
 499
 500         ret = sh_eth_desc_init(eth);
 501         if (ret)
 502                 return ret;
 503
 504         sh_eth_mac_regs_config(eth, mac);
 505
 506         return 0;
 507 }
 508
 509 static int sh_eth_start_common(struct sh_eth_dev *eth)
 510 {
 511         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 512         int ret;
 513
 514         ret = phy_startup(port_info->phydev);
 515         if (ret) {
 516                 printf(SHETHER_NAME ": phy startup failure\n");
 517                 return ret;
 518         }
 519
 520         ret = sh_eth_phy_regs_config(eth);
 521         if (ret)
 522                 return ret;
 523
 524         sh_eth_start(eth);
 525
 526         return 0;
 527 }
 528
 529 struct sh_ether_priv {
 530         struct sh_eth_dev       shdev;
 531
 532         struct mii_dev          *bus;
 533         phys_addr_t             iobase;
 534         struct clk              clk;
 535 };
 536
 537 static int sh_ether_send(struct udevice *dev, void *packet, int len)
 538 {
 539         struct sh_ether_priv *priv = dev_get_priv(dev);
 540         struct sh_eth_dev *eth = &priv->shdev;
 541
 542         return sh_eth_send_common(eth, packet, len);
 543 }
 544
 545 static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
 546 {
 547         struct sh_ether_priv *priv = dev_get_priv(dev);
 548         struct sh_eth_dev *eth = &priv->shdev;
 549         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 550         uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
 551         int len;
 552
 553         len = sh_eth_recv_start(eth);
 554         if (len > 0) {
 555                 invalidate_cache(packet, len);
 556                 *packetp = packet;
 557
 558                 return len;
 559         }
 560
 561         /* Restart the receiver if disabled */
 562         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 563                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 564
 565         return len;
 566 }
 567
 568 static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
 569 {
 570         struct sh_ether_priv *priv = dev_get_priv(dev);
 571         struct sh_eth_dev *eth = &priv->shdev;
 572         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 573
 574         sh_eth_recv_finish(eth);
 575
 576         /* Restart the receiver if disabled */
 577         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 578                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 579
 580         return 0;
 581 }
 582
 583 static int sh_ether_write_hwaddr(struct udevice *dev)
 584 {
 585         struct sh_ether_priv *priv = dev_get_priv(dev);
 586         struct sh_eth_dev *eth = &priv->shdev;
 587         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 588         struct eth_pdata *pdata = dev_get_plat(dev);
 589
 590         sh_eth_write_hwaddr(port_info, pdata->enetaddr);
 591
 592         return 0;
 593 }
 594
 595 static int sh_eth_phy_config(struct udevice *dev)
 596 {
 597         struct sh_ether_priv *priv = dev_get_priv(dev);
 598         struct eth_pdata *pdata = dev_get_plat(dev);
 599         struct sh_eth_dev *eth = &priv->shdev;
 600         int ret = 0;
 601         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 602         struct phy_device *phydev;
 603
 604         phydev = phy_connect(priv->bus, -1, dev, pdata->phy_interface);
 605         if (!phydev)
 606                 return -ENODEV;
 607
 608         port_info->phydev = phydev;
 609         phy_config(phydev);
 610
 611         return ret;
 612 }
 613
 614 static int sh_ether_start(struct udevice *dev)
 615 {
 616         struct sh_ether_priv *priv = dev_get_priv(dev);
 617         struct eth_pdata *pdata = dev_get_plat(dev);
 618         struct sh_eth_dev *eth = &priv->shdev;
 619         int ret;
 620
 621         ret = sh_eth_init_common(eth, pdata->enetaddr);
 622         if (ret)
 623                 return ret;
 624
 625         ret = sh_eth_start_common(eth);
 626         if (ret)
 627                 goto err_start;
 628
 629         return 0;
 630
 631 err_start:
 632         sh_eth_tx_desc_free(eth);
 633         sh_eth_rx_desc_free(eth);
 634         return ret;
 635 }
 636
 637 static void sh_ether_stop(struct udevice *dev)
 638 {
 639         struct sh_ether_priv *priv = dev_get_priv(dev);
 640         struct sh_eth_dev *eth = &priv->shdev;
 641         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 642
 643         phy_shutdown(port_info->phydev);
 644         sh_eth_stop(&priv->shdev);
 645 }
 646
 647 static int sh_ether_probe(struct udevice *udev)
 648 {
 649         struct eth_pdata *pdata = dev_get_plat(udev);
 650         struct sh_ether_priv *priv = dev_get_priv(udev);
 651         struct sh_eth_dev *eth = &priv->shdev;
 652         struct mii_dev *mdiodev;
 653         int ret;
 654
 655         priv->iobase = pdata->iobase;
 656
 657 #if CONFIG_IS_ENABLED(CLK)
 658         ret = clk_get_by_index(udev, 0, &priv->clk);
 659         if (ret < 0)
 660                 return ret;
 661 #endif
 662         mdiodev = mdio_alloc();
 663         if (!mdiodev) {
 664                 ret = -ENOMEM;
 665                 return ret;
 666         }
 667
 668         mdiodev->read = bb_miiphy_read;
 669         mdiodev->write = bb_miiphy_write;
 670         bb_miiphy_buses[0].priv = eth;
 671         snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
 672
 673         ret = mdio_register(mdiodev);
 674         if (ret < 0)
 675                 goto err_mdio_register;
 676
 677         priv->bus = miiphy_get_dev_by_name(udev->name);
 678
 679         eth->port = CFG_SH_ETHER_USE_PORT;
 680         eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR;
 681         eth->port_info[eth->port].iobase =
 682                 (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
 683
 684 #if CONFIG_IS_ENABLED(CLK)
 685         ret = clk_enable(&priv->clk);
 686         if (ret)
 687                 goto err_mdio_register;
 688 #endif
 689
 690         ret = sh_eth_init_common(eth, pdata->enetaddr);
 691         if (ret)
 692                 goto err_phy_config;
 693
 694         ret = sh_eth_phy_config(udev);
 695         if (ret) {
 696                 printf(SHETHER_NAME ": phy config timeout\n");
 697                 goto err_phy_config;
 698         }
 699
 700         return 0;
 701
 702 err_phy_config:
 703 #if CONFIG_IS_ENABLED(CLK)
 704         clk_disable(&priv->clk);
 705 #endif
 706 err_mdio_register:
 707         mdio_free(mdiodev);
 708         return ret;
 709 }
 710
 711 static int sh_ether_remove(struct udevice *udev)
 712 {
 713         struct sh_ether_priv *priv = dev_get_priv(udev);
 714         struct sh_eth_dev *eth = &priv->shdev;
 715         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 716
 717 #if CONFIG_IS_ENABLED(CLK)
 718         clk_disable(&priv->clk);
 719 #endif
 720         free(port_info->phydev);
 721         mdio_unregister(priv->bus);
 722         mdio_free(priv->bus);
 723
 724         return 0;
 725 }
 726
 727 static const struct eth_ops sh_ether_ops = {
 728         .start                  = sh_ether_start,
 729         .send                   = sh_ether_send,
 730         .recv                   = sh_ether_recv,
 731         .free_pkt               = sh_ether_free_pkt,
 732         .stop                   = sh_ether_stop,
 733         .write_hwaddr           = sh_ether_write_hwaddr,
 734 };
 735
 736 int sh_ether_of_to_plat(struct udevice *dev)
 737 {
 738         struct eth_pdata *pdata = dev_get_plat(dev);
 739         const fdt32_t *cell;
 740
 741         pdata->iobase = dev_read_addr(dev);
 742
 743         pdata->phy_interface = dev_read_phy_mode(dev);
 744         if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
 745                 return -EINVAL;
 746
 747         pdata->max_speed = 1000;
 748         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
 749         if (cell)
 750                 pdata->max_speed = fdt32_to_cpu(*cell);
 751
 752         sprintf(bb_miiphy_buses[0].name, dev->name);
 753
 754         return 0;
 755 }
 756
 757 static const struct udevice_id sh_ether_ids[] = {
 758         { .compatible = "renesas,ether-r7s72100" },
 759         { .compatible = "renesas,ether-r8a7790" },
 760         { .compatible = "renesas,ether-r8a7791" },
 761         { .compatible = "renesas,ether-r8a7793" },
 762         { .compatible = "renesas,ether-r8a7794" },
 763         { .compatible = "renesas,gether-r8a77980" },
 764         { }
 765 };
 766
 767 U_BOOT_DRIVER(eth_sh_ether) = {
 768         .name           = "sh_ether",
 769         .id             = UCLASS_ETH,
 770         .of_match       = sh_ether_ids,
 771         .of_to_plat = sh_ether_of_to_plat,
 772         .probe          = sh_ether_probe,
 773         .remove         = sh_ether_remove,
 774         .ops            = &sh_ether_ops,
 775         .priv_auto      = sizeof(struct sh_ether_priv),
 776         .plat_auto      = sizeof(struct eth_pdata),
 777         .flags          = DM_FLAG_ALLOC_PRIV_DMA,
 778 };
 779
 780 /******* for bb_miiphy *******/
 781 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 782 {
 783         return 0;
 784 }
 785
 786 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 787 {
 788         struct sh_eth_dev *eth = bus->priv;
 789         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 790
 791         sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
 792
 793         return 0;
 794 }
 795
 796 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 797 {
 798         struct sh_eth_dev *eth = bus->priv;
 799         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 800
 801         sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
 802
 803         return 0;
 804 }
 805
 806 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 807 {
 808         struct sh_eth_dev *eth = bus->priv;
 809         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 810
 811         if (v)
 812                 sh_eth_write(port_info,
 813                              sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
 814         else
 815                 sh_eth_write(port_info,
 816                              sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
 817
 818         return 0;
 819 }
 820
 821 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
 822 {
 823         struct sh_eth_dev *eth = bus->priv;
 824         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 825
 826         *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
 827
 828         return 0;
 829 }
 830
 831 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
 832 {
 833         struct sh_eth_dev *eth = bus->priv;
 834         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 835
 836         if (v)
 837                 sh_eth_write(port_info,
 838                              sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
 839         else
 840                 sh_eth_write(port_info,
 841                              sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
 842
 843         return 0;
 844 }
 845
 846 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
 847 {
 848         udelay(10);
 849
 850         return 0;
 851 }
 852
 853 struct bb_miiphy_bus bb_miiphy_buses[] = {
 854         {
 855                 .name           = "sh_eth",
 856                 .init           = sh_eth_bb_init,
 857                 .mdio_active    = sh_eth_bb_mdio_active,
 858                 .mdio_tristate  = sh_eth_bb_mdio_tristate,
 859                 .set_mdio       = sh_eth_bb_set_mdio,
 860                 .get_mdio       = sh_eth_bb_get_mdio,
 861                 .set_mdc        = sh_eth_bb_set_mdc,
 862                 .delay          = sh_eth_bb_delay,
 863         }
 864 };
 865
 866 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);