1 // SPDX-License-Identifier: GPL-2.0+
3 * sh_eth.c - Driver for Renesas ethernet controller.
5 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
6 * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
7 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
8 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
18 #include <linux/errno.h>
24 #include <linux/mii.h>
30 #ifndef CONFIG_SH_ETHER_USE_PORT
31 # error "Please define CONFIG_SH_ETHER_USE_PORT"
33 #ifndef CONFIG_SH_ETHER_PHY_ADDR
34 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
37 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
38 !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
39 #define flush_cache_wback(addr, len) \
40 flush_dcache_range((unsigned long)addr, \
41 (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
43 #define flush_cache_wback(...)
46 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
47 #define invalidate_cache(addr, len) \
49 unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
50 unsigned long start, end; \
52 start = (unsigned long)addr; \
54 start &= ~(line_size - 1); \
55 end = ((end + line_size - 1) & ~(line_size - 1)); \
57 invalidate_dcache_range(start, end); \
60 #define invalidate_cache(...)
63 #define TIMEOUT_CNT 1000
65 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
68 struct sh_eth_info *port_info = ð->port_info[eth->port];
70 if (!packet || len > 0xffff) {
71 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
76 /* packet must be a 4 byte boundary */
77 if ((uintptr_t)packet & 3) {
78 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
84 /* Update tx descriptor */
85 flush_cache_wback(packet, len);
86 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
87 port_info->tx_desc_cur->td1 = len << 16;
88 /* Must preserve the end of descriptor list indication */
89 if (port_info->tx_desc_cur->td0 & TD_TDLE)
90 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
92 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
94 flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
96 /* Restart the transmitter if disabled */
97 if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
98 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
100 /* Wait until packet is transmitted */
101 timeout = TIMEOUT_CNT;
103 invalidate_cache(port_info->tx_desc_cur,
104 sizeof(struct tx_desc_s));
106 } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
109 printf(SHETHER_NAME ": transmit timeout\n");
114 port_info->tx_desc_cur++;
115 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
116 port_info->tx_desc_cur = port_info->tx_desc_base;
122 static int sh_eth_recv_start(struct sh_eth_dev *eth)
124 struct sh_eth_info *port_info = ð->port_info[eth->port];
126 /* Check if the rx descriptor is ready */
127 invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
128 if (port_info->rx_desc_cur->rd0 & RD_RACT)
131 /* Check for errors */
132 if (port_info->rx_desc_cur->rd0 & RD_RFE)
135 return port_info->rx_desc_cur->rd1 & 0xffff;
138 static void sh_eth_recv_finish(struct sh_eth_dev *eth)
140 struct sh_eth_info *port_info = ð->port_info[eth->port];
142 /* Make current descriptor available again */
143 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
144 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
146 port_info->rx_desc_cur->rd0 = RD_RACT;
148 flush_cache_wback(port_info->rx_desc_cur,
149 sizeof(struct rx_desc_s));
151 /* Point to the next descriptor */
152 port_info->rx_desc_cur++;
153 if (port_info->rx_desc_cur >=
154 port_info->rx_desc_base + NUM_RX_DESC)
155 port_info->rx_desc_cur = port_info->rx_desc_base;
158 static int sh_eth_reset(struct sh_eth_dev *eth)
160 struct sh_eth_info *port_info = ð->port_info[eth->port];
161 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
164 /* Start e-dmac transmitter and receiver */
165 sh_eth_write(port_info, EDSR_ENALL, EDSR);
167 /* Perform a software reset and wait for it to complete */
168 sh_eth_write(port_info, EDMR_SRST, EDMR);
169 for (i = 0; i < TIMEOUT_CNT; i++) {
170 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
175 if (i == TIMEOUT_CNT) {
176 printf(SHETHER_NAME ": Software reset timeout\n");
182 sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
184 sh_eth_write(port_info,
185 sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
191 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
194 u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
195 struct sh_eth_info *port_info = ð->port_info[eth->port];
196 struct tx_desc_s *cur_tx_desc;
199 * Allocate rx descriptors. They must be aligned to size of struct
202 port_info->tx_desc_alloc =
203 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
204 if (!port_info->tx_desc_alloc) {
205 printf(SHETHER_NAME ": memalign failed\n");
210 flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
212 /* Make sure we use a P2 address (non-cacheable) */
213 port_info->tx_desc_base =
214 (struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
215 port_info->tx_desc_cur = port_info->tx_desc_base;
217 /* Initialize all descriptors */
218 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
219 cur_tx_desc++, i++) {
220 cur_tx_desc->td0 = 0x00;
221 cur_tx_desc->td1 = 0x00;
222 cur_tx_desc->td2 = 0x00;
225 /* Mark the end of the descriptors */
227 cur_tx_desc->td0 |= TD_TDLE;
230 * Point the controller to the tx descriptor list. Must use physical
233 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
234 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
235 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
236 sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
237 sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
244 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
247 u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
248 struct sh_eth_info *port_info = ð->port_info[eth->port];
249 struct rx_desc_s *cur_rx_desc;
253 * Allocate rx descriptors. They must be aligned to size of struct
256 port_info->rx_desc_alloc =
257 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
258 if (!port_info->rx_desc_alloc) {
259 printf(SHETHER_NAME ": memalign failed\n");
264 flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
266 /* Make sure we use a P2 address (non-cacheable) */
267 port_info->rx_desc_base =
268 (struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
270 port_info->rx_desc_cur = port_info->rx_desc_base;
273 * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
274 * aligned and in P2 area.
276 port_info->rx_buf_alloc =
277 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
278 if (!port_info->rx_buf_alloc) {
279 printf(SHETHER_NAME ": alloc failed\n");
284 port_info->rx_buf_base = (u8 *)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
286 /* Initialize all descriptors */
287 for (cur_rx_desc = port_info->rx_desc_base,
288 rx_buf = port_info->rx_buf_base, i = 0;
289 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
290 cur_rx_desc->rd0 = RD_RACT;
291 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
292 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
295 /* Mark the end of the descriptors */
297 cur_rx_desc->rd0 |= RD_RDLE;
299 /* Point the controller to the rx descriptor list */
300 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
301 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
302 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
303 sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
304 sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
310 free(port_info->rx_desc_alloc);
311 port_info->rx_desc_alloc = NULL;
317 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
319 struct sh_eth_info *port_info = ð->port_info[eth->port];
321 if (port_info->tx_desc_alloc) {
322 free(port_info->tx_desc_alloc);
323 port_info->tx_desc_alloc = NULL;
327 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
329 struct sh_eth_info *port_info = ð->port_info[eth->port];
331 if (port_info->rx_desc_alloc) {
332 free(port_info->rx_desc_alloc);
333 port_info->rx_desc_alloc = NULL;
336 if (port_info->rx_buf_alloc) {
337 free(port_info->rx_buf_alloc);
338 port_info->rx_buf_alloc = NULL;
342 static int sh_eth_desc_init(struct sh_eth_dev *eth)
346 ret = sh_eth_tx_desc_init(eth);
350 ret = sh_eth_rx_desc_init(eth);
356 sh_eth_tx_desc_free(eth);
362 static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
367 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
368 sh_eth_write(port_info, val, MAHR);
370 val = (mac[4] << 8) | mac[5];
371 sh_eth_write(port_info, val, MALR);
374 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
376 struct sh_eth_info *port_info = ð->port_info[eth->port];
379 /* Configure e-dmac registers */
380 edmr = sh_eth_read(port_info, EDMR);
381 edmr &= ~EMDR_DESC_R;
382 edmr |= EMDR_DESC | EDMR_EL;
383 #if defined(CONFIG_R8A77980)
386 sh_eth_write(port_info, edmr, EDMR);
388 sh_eth_write(port_info, 0, EESIPR);
389 sh_eth_write(port_info, 0, TRSCER);
390 sh_eth_write(port_info, 0, TFTR);
391 sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
392 sh_eth_write(port_info, RMCR_RST, RMCR);
393 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
394 sh_eth_write(port_info, 0, RPADIR);
396 sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
398 /* Configure e-mac registers */
399 sh_eth_write(port_info, 0, ECSIPR);
401 /* Set Mac address */
402 sh_eth_write_hwaddr(port_info, mac);
404 sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
405 #if defined(SH_ETH_TYPE_GETHER)
406 sh_eth_write(port_info, 0, PIPR);
408 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
409 sh_eth_write(port_info, APR_AP, APR);
410 sh_eth_write(port_info, MPR_MP, MPR);
411 sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
414 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
415 sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
416 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
417 sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
421 static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
423 struct sh_eth_info *port_info = ð->port_info[eth->port];
424 struct phy_device *phy = port_info->phydev;
428 /* Set the transfer speed */
429 if (phy->speed == 100) {
430 printf(SHETHER_NAME ": 100Base/");
431 #if defined(SH_ETH_TYPE_GETHER)
432 sh_eth_write(port_info, GECMR_100B, GECMR);
433 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
434 sh_eth_write(port_info, 1, RTRATE);
435 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
438 } else if (phy->speed == 10) {
439 printf(SHETHER_NAME ": 10Base/");
440 #if defined(SH_ETH_TYPE_GETHER)
441 sh_eth_write(port_info, GECMR_10B, GECMR);
442 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
443 sh_eth_write(port_info, 0, RTRATE);
446 #if defined(SH_ETH_TYPE_GETHER)
447 else if (phy->speed == 1000) {
448 printf(SHETHER_NAME ": 1000Base/");
449 sh_eth_write(port_info, GECMR_1000B, GECMR);
453 /* Check if full duplex mode is supported by the phy */
456 sh_eth_write(port_info,
457 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
461 sh_eth_write(port_info,
462 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
469 static void sh_eth_start(struct sh_eth_dev *eth)
471 struct sh_eth_info *port_info = ð->port_info[eth->port];
474 * Enable the e-dmac receiver only. The transmitter will be enabled when
475 * we have something to transmit
477 sh_eth_write(port_info, EDRRR_R, EDRRR);
480 static void sh_eth_stop(struct sh_eth_dev *eth)
482 struct sh_eth_info *port_info = ð->port_info[eth->port];
484 sh_eth_write(port_info, ~EDRRR_R, EDRRR);
487 static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
491 ret = sh_eth_reset(eth);
495 ret = sh_eth_desc_init(eth);
499 sh_eth_mac_regs_config(eth, mac);
504 static int sh_eth_start_common(struct sh_eth_dev *eth)
506 struct sh_eth_info *port_info = ð->port_info[eth->port];
509 ret = phy_startup(port_info->phydev);
511 printf(SHETHER_NAME ": phy startup failure\n");
515 ret = sh_eth_phy_regs_config(eth);
524 #ifndef CONFIG_DM_ETH
525 static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
528 struct sh_eth_info *port_info = ð->port_info[eth->port];
529 struct eth_device *dev = port_info->dev;
530 struct phy_device *phydev;
532 phydev = phy_connect(
533 miiphy_get_dev_by_name(dev->name),
534 port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
535 port_info->phydev = phydev;
541 static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
543 struct sh_eth_dev *eth = dev->priv;
545 return sh_eth_send_common(eth, packet, len);
548 static int sh_eth_recv_common(struct sh_eth_dev *eth)
551 struct sh_eth_info *port_info = ð->port_info[eth->port];
552 uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
554 len = sh_eth_recv_start(eth);
556 invalidate_cache(packet, len);
557 net_process_received_packet(packet, len);
558 sh_eth_recv_finish(eth);
562 /* Restart the receiver if disabled */
563 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
564 sh_eth_write(port_info, EDRRR_R, EDRRR);
569 static int sh_eth_recv_legacy(struct eth_device *dev)
571 struct sh_eth_dev *eth = dev->priv;
573 return sh_eth_recv_common(eth);
576 static int sh_eth_init_legacy(struct eth_device *dev, bd_t *bd)
578 struct sh_eth_dev *eth = dev->priv;
581 ret = sh_eth_init_common(eth, dev->enetaddr);
585 ret = sh_eth_phy_config_legacy(eth);
587 printf(SHETHER_NAME ": phy config timeout\n");
591 ret = sh_eth_start_common(eth);
598 sh_eth_tx_desc_free(eth);
599 sh_eth_rx_desc_free(eth);
603 void sh_eth_halt_legacy(struct eth_device *dev)
605 struct sh_eth_dev *eth = dev->priv;
610 int sh_eth_initialize(bd_t *bd)
613 struct sh_eth_dev *eth = NULL;
614 struct eth_device *dev = NULL;
615 struct mii_dev *mdiodev;
617 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
619 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
624 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
626 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
630 memset(dev, 0, sizeof(struct eth_device));
631 memset(eth, 0, sizeof(struct sh_eth_dev));
633 eth->port = CONFIG_SH_ETHER_USE_PORT;
634 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
635 eth->port_info[eth->port].iobase =
636 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
638 dev->priv = (void *)eth;
640 dev->init = sh_eth_init_legacy;
641 dev->halt = sh_eth_halt_legacy;
642 dev->send = sh_eth_send_legacy;
643 dev->recv = sh_eth_recv_legacy;
644 eth->port_info[eth->port].dev = dev;
646 strcpy(dev->name, SHETHER_NAME);
648 /* Register Device to EtherNet subsystem */
651 bb_miiphy_buses[0].priv = eth;
652 mdiodev = mdio_alloc();
655 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
656 mdiodev->read = bb_miiphy_read;
657 mdiodev->write = bb_miiphy_write;
659 ret = mdio_register(mdiodev);
663 if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
664 puts("Please set MAC address\n");
675 printf(SHETHER_NAME ": Failed\n");
679 #else /* CONFIG_DM_ETH */
681 struct sh_ether_priv {
682 struct sh_eth_dev shdev;
687 struct gpio_desc reset_gpio;
690 static int sh_ether_send(struct udevice *dev, void *packet, int len)
692 struct sh_ether_priv *priv = dev_get_priv(dev);
693 struct sh_eth_dev *eth = &priv->shdev;
695 return sh_eth_send_common(eth, packet, len);
698 static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
700 struct sh_ether_priv *priv = dev_get_priv(dev);
701 struct sh_eth_dev *eth = &priv->shdev;
702 struct sh_eth_info *port_info = ð->port_info[eth->port];
703 uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
706 len = sh_eth_recv_start(eth);
708 invalidate_cache(packet, len);
715 /* Restart the receiver if disabled */
716 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
717 sh_eth_write(port_info, EDRRR_R, EDRRR);
723 static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
725 struct sh_ether_priv *priv = dev_get_priv(dev);
726 struct sh_eth_dev *eth = &priv->shdev;
727 struct sh_eth_info *port_info = ð->port_info[eth->port];
729 sh_eth_recv_finish(eth);
731 /* Restart the receiver if disabled */
732 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
733 sh_eth_write(port_info, EDRRR_R, EDRRR);
738 static int sh_ether_write_hwaddr(struct udevice *dev)
740 struct sh_ether_priv *priv = dev_get_priv(dev);
741 struct sh_eth_dev *eth = &priv->shdev;
742 struct sh_eth_info *port_info = ð->port_info[eth->port];
743 struct eth_pdata *pdata = dev_get_platdata(dev);
745 sh_eth_write_hwaddr(port_info, pdata->enetaddr);
750 static int sh_eth_phy_config(struct udevice *dev)
752 struct sh_ether_priv *priv = dev_get_priv(dev);
753 struct eth_pdata *pdata = dev_get_platdata(dev);
754 struct sh_eth_dev *eth = &priv->shdev;
756 struct sh_eth_info *port_info = ð->port_info[eth->port];
757 struct phy_device *phydev;
758 int mask = 0xffffffff;
760 phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface);
764 phy_connect_dev(phydev, dev);
766 port_info->phydev = phydev;
772 static int sh_ether_start(struct udevice *dev)
774 struct sh_ether_priv *priv = dev_get_priv(dev);
775 struct eth_pdata *pdata = dev_get_platdata(dev);
776 struct sh_eth_dev *eth = &priv->shdev;
779 ret = sh_eth_init_common(eth, pdata->enetaddr);
783 ret = sh_eth_start_common(eth);
790 sh_eth_tx_desc_free(eth);
791 sh_eth_rx_desc_free(eth);
795 static void sh_ether_stop(struct udevice *dev)
797 struct sh_ether_priv *priv = dev_get_priv(dev);
798 struct sh_eth_dev *eth = &priv->shdev;
799 struct sh_eth_info *port_info = ð->port_info[eth->port];
801 phy_shutdown(port_info->phydev);
802 sh_eth_stop(&priv->shdev);
805 static int sh_ether_probe(struct udevice *udev)
807 struct eth_pdata *pdata = dev_get_platdata(udev);
808 struct sh_ether_priv *priv = dev_get_priv(udev);
809 struct sh_eth_dev *eth = &priv->shdev;
810 struct ofnode_phandle_args phandle_args;
811 struct mii_dev *mdiodev;
814 priv->iobase = pdata->iobase;
816 #if CONFIG_IS_ENABLED(CLK)
817 ret = clk_get_by_index(udev, 0, &priv->clk);
822 ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
824 gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
825 &priv->reset_gpio, GPIOD_IS_OUT);
828 if (!dm_gpio_is_valid(&priv->reset_gpio)) {
829 gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
833 mdiodev = mdio_alloc();
839 mdiodev->read = bb_miiphy_read;
840 mdiodev->write = bb_miiphy_write;
841 bb_miiphy_buses[0].priv = eth;
842 snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
844 ret = mdio_register(mdiodev);
846 goto err_mdio_register;
848 priv->bus = miiphy_get_dev_by_name(udev->name);
850 eth->port = CONFIG_SH_ETHER_USE_PORT;
851 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
852 eth->port_info[eth->port].iobase =
853 (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
855 #if CONFIG_IS_ENABLED(CLK)
856 ret = clk_enable(&priv->clk);
858 goto err_mdio_register;
861 ret = sh_eth_phy_config(udev);
863 printf(SHETHER_NAME ": phy config timeout\n");
870 #if CONFIG_IS_ENABLED(CLK)
871 clk_disable(&priv->clk);
878 static int sh_ether_remove(struct udevice *udev)
880 struct sh_ether_priv *priv = dev_get_priv(udev);
881 struct sh_eth_dev *eth = &priv->shdev;
882 struct sh_eth_info *port_info = ð->port_info[eth->port];
884 #if CONFIG_IS_ENABLED(CLK)
885 clk_disable(&priv->clk);
887 free(port_info->phydev);
888 mdio_unregister(priv->bus);
889 mdio_free(priv->bus);
891 if (dm_gpio_is_valid(&priv->reset_gpio))
892 dm_gpio_free(udev, &priv->reset_gpio);
897 static const struct eth_ops sh_ether_ops = {
898 .start = sh_ether_start,
899 .send = sh_ether_send,
900 .recv = sh_ether_recv,
901 .free_pkt = sh_ether_free_pkt,
902 .stop = sh_ether_stop,
903 .write_hwaddr = sh_ether_write_hwaddr,
906 int sh_ether_ofdata_to_platdata(struct udevice *dev)
908 struct eth_pdata *pdata = dev_get_platdata(dev);
909 const char *phy_mode;
913 pdata->iobase = devfdt_get_addr(dev);
914 pdata->phy_interface = -1;
915 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
918 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
919 if (pdata->phy_interface == -1) {
920 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
924 pdata->max_speed = 1000;
925 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
927 pdata->max_speed = fdt32_to_cpu(*cell);
929 sprintf(bb_miiphy_buses[0].name, dev->name);
934 static const struct udevice_id sh_ether_ids[] = {
935 { .compatible = "renesas,ether-r7s72100" },
936 { .compatible = "renesas,ether-r8a7790" },
937 { .compatible = "renesas,ether-r8a7791" },
938 { .compatible = "renesas,ether-r8a7793" },
939 { .compatible = "renesas,ether-r8a7794" },
940 { .compatible = "renesas,gether-r8a77980" },
944 U_BOOT_DRIVER(eth_sh_ether) = {
947 .of_match = sh_ether_ids,
948 .ofdata_to_platdata = sh_ether_ofdata_to_platdata,
949 .probe = sh_ether_probe,
950 .remove = sh_ether_remove,
951 .ops = &sh_ether_ops,
952 .priv_auto_alloc_size = sizeof(struct sh_ether_priv),
953 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
954 .flags = DM_FLAG_ALLOC_PRIV_DMA,
958 /******* for bb_miiphy *******/
959 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
964 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
966 struct sh_eth_dev *eth = bus->priv;
967 struct sh_eth_info *port_info = ð->port_info[eth->port];
969 sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
974 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
976 struct sh_eth_dev *eth = bus->priv;
977 struct sh_eth_info *port_info = ð->port_info[eth->port];
979 sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
984 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
986 struct sh_eth_dev *eth = bus->priv;
987 struct sh_eth_info *port_info = ð->port_info[eth->port];
990 sh_eth_write(port_info,
991 sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
993 sh_eth_write(port_info,
994 sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
999 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
1001 struct sh_eth_dev *eth = bus->priv;
1002 struct sh_eth_info *port_info = ð->port_info[eth->port];
1004 *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
1009 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
1011 struct sh_eth_dev *eth = bus->priv;
1012 struct sh_eth_info *port_info = ð->port_info[eth->port];
1015 sh_eth_write(port_info,
1016 sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
1018 sh_eth_write(port_info,
1019 sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
1024 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
1031 struct bb_miiphy_bus bb_miiphy_buses[] = {
1034 .init = sh_eth_bb_init,
1035 .mdio_active = sh_eth_bb_mdio_active,
1036 .mdio_tristate = sh_eth_bb_mdio_tristate,
1037 .set_mdio = sh_eth_bb_set_mdio,
1038 .get_mdio = sh_eth_bb_get_mdio,
1039 .set_mdc = sh_eth_bb_set_mdc,
1040 .delay = sh_eth_bb_delay,
1044 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);