drivers/net/sh_eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * sh_eth.c - Driver for Renesas ethernet controller.
   4  *
   5  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
   6  * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
   7  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   8  * Copyright (C) 2013, 2014 Renesas Electronics Corporation
   9  */
  10
  11 #include <config.h>
  12 #include <common.h>
  13 #include <environment.h>
  14 #include <malloc.h>
  15 #include <net.h>
  16 #include <netdev.h>
  17 #include <miiphy.h>
  18 #include <linux/errno.h>
  19 #include <asm/io.h>
  20
  21 #ifdef CONFIG_DM_ETH
  22 #include <clk.h>
  23 #include <dm.h>
  24 #include <linux/mii.h>
  25 #include <asm/gpio.h>
  26 #endif
  27
  28 #include "sh_eth.h"
  29
  30 #ifndef CONFIG_SH_ETHER_USE_PORT
  31 # error "Please define CONFIG_SH_ETHER_USE_PORT"
  32 #endif
  33 #ifndef CONFIG_SH_ETHER_PHY_ADDR
  34 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
  35 #endif
  36
  37 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
  38         !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  39 #define flush_cache_wback(addr, len)    \
  40                 flush_dcache_range((u32)addr, \
  41                 (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
  42 #else
  43 #define flush_cache_wback(...)
  44 #endif
  45
  46 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
  47 #define invalidate_cache(addr, len)             \
  48         {       \
  49                 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;    \
  50                 u32 start, end; \
  51                 \
  52                 start = (u32)addr;      \
  53                 end = start + len;      \
  54                 start &= ~(line_size - 1);      \
  55                 end = ((end + line_size - 1) & ~(line_size - 1));       \
  56                 \
  57                 invalidate_dcache_range(start, end);    \
  58         }
  59 #else
  60 #define invalidate_cache(...)
  61 #endif
  62
  63 #define TIMEOUT_CNT 1000
  64
  65 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
  66 {
  67         int ret = 0, timeout;
  68         struct sh_eth_info *port_info = &eth->port_info[eth->port];
  69
  70         if (!packet || len > 0xffff) {
  71                 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
  72                 ret = -EINVAL;
  73                 goto err;
  74         }
  75
  76         /* packet must be a 4 byte boundary */
  77         if ((int)packet & 3) {
  78                 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
  79                                 , __func__);
  80                 ret = -EFAULT;
  81                 goto err;
  82         }
  83
  84         /* Update tx descriptor */
  85         flush_cache_wback(packet, len);
  86         port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
  87         port_info->tx_desc_cur->td1 = len << 16;
  88         /* Must preserve the end of descriptor list indication */
  89         if (port_info->tx_desc_cur->td0 & TD_TDLE)
  90                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
  91         else
  92                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
  93
  94         flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
  95
  96         /* Restart the transmitter if disabled */
  97         if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
  98                 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
  99
 100         /* Wait until packet is transmitted */
 101         timeout = TIMEOUT_CNT;
 102         do {
 103                 invalidate_cache(port_info->tx_desc_cur,
 104                                  sizeof(struct tx_desc_s));
 105                 udelay(100);
 106         } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
 107
 108         if (timeout < 0) {
 109                 printf(SHETHER_NAME ": transmit timeout\n");
 110                 ret = -ETIMEDOUT;
 111                 goto err;
 112         }
 113
 114         port_info->tx_desc_cur++;
 115         if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
 116                 port_info->tx_desc_cur = port_info->tx_desc_base;
 117
 118 err:
 119         return ret;
 120 }
 121
 122 static int sh_eth_recv_start(struct sh_eth_dev *eth)
 123 {
 124         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 125
 126         /* Check if the rx descriptor is ready */
 127         invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
 128         if (port_info->rx_desc_cur->rd0 & RD_RACT)
 129                 return -EINVAL;
 130
 131         /* Check for errors */
 132         if (port_info->rx_desc_cur->rd0 & RD_RFE)
 133                 return -EINVAL;
 134
 135         return port_info->rx_desc_cur->rd1 & 0xffff;
 136 }
 137
 138 static void sh_eth_recv_finish(struct sh_eth_dev *eth)
 139 {
 140         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 141
 142         /* Make current descriptor available again */
 143         if (port_info->rx_desc_cur->rd0 & RD_RDLE)
 144                 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
 145         else
 146                 port_info->rx_desc_cur->rd0 = RD_RACT;
 147
 148         flush_cache_wback(port_info->rx_desc_cur,
 149                           sizeof(struct rx_desc_s));
 150
 151         /* Point to the next descriptor */
 152         port_info->rx_desc_cur++;
 153         if (port_info->rx_desc_cur >=
 154             port_info->rx_desc_base + NUM_RX_DESC)
 155                 port_info->rx_desc_cur = port_info->rx_desc_base;
 156 }
 157
 158 static int sh_eth_reset(struct sh_eth_dev *eth)
 159 {
 160         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 161 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 162         int ret = 0, i;
 163
 164         /* Start e-dmac transmitter and receiver */
 165         sh_eth_write(port_info, EDSR_ENALL, EDSR);
 166
 167         /* Perform a software reset and wait for it to complete */
 168         sh_eth_write(port_info, EDMR_SRST, EDMR);
 169         for (i = 0; i < TIMEOUT_CNT; i++) {
 170                 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
 171                         break;
 172                 udelay(1000);
 173         }
 174
 175         if (i == TIMEOUT_CNT) {
 176                 printf(SHETHER_NAME  ": Software reset timeout\n");
 177                 ret = -EIO;
 178         }
 179
 180         return ret;
 181 #else
 182         sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
 183         mdelay(3);
 184         sh_eth_write(port_info,
 185                      sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
 186
 187         return 0;
 188 #endif
 189 }
 190
 191 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 192 {
 193         int i, ret = 0;
 194         u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
 195         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 196         struct tx_desc_s *cur_tx_desc;
 197
 198         /*
 199          * Allocate rx descriptors. They must be aligned to size of struct
 200          * tx_desc_s.
 201          */
 202         port_info->tx_desc_alloc =
 203                 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
 204         if (!port_info->tx_desc_alloc) {
 205                 printf(SHETHER_NAME ": memalign failed\n");
 206                 ret = -ENOMEM;
 207                 goto err;
 208         }
 209
 210         flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
 211
 212         /* Make sure we use a P2 address (non-cacheable) */
 213         port_info->tx_desc_base =
 214                 (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
 215         port_info->tx_desc_cur = port_info->tx_desc_base;
 216
 217         /* Initialize all descriptors */
 218         for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
 219              cur_tx_desc++, i++) {
 220                 cur_tx_desc->td0 = 0x00;
 221                 cur_tx_desc->td1 = 0x00;
 222                 cur_tx_desc->td2 = 0x00;
 223         }
 224
 225         /* Mark the end of the descriptors */
 226         cur_tx_desc--;
 227         cur_tx_desc->td0 |= TD_TDLE;
 228
 229         /*
 230          * Point the controller to the tx descriptor list. Must use physical
 231          * addresses
 232          */
 233         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
 234 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 235         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
 236         sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
 237         sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
 238 #endif
 239
 240 err:
 241         return ret;
 242 }
 243
 244 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 245 {
 246         int i, ret = 0;
 247         u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
 248         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 249         struct rx_desc_s *cur_rx_desc;
 250         u8 *rx_buf;
 251
 252         /*
 253          * Allocate rx descriptors. They must be aligned to size of struct
 254          * rx_desc_s.
 255          */
 256         port_info->rx_desc_alloc =
 257                 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
 258         if (!port_info->rx_desc_alloc) {
 259                 printf(SHETHER_NAME ": memalign failed\n");
 260                 ret = -ENOMEM;
 261                 goto err;
 262         }
 263
 264         flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
 265
 266         /* Make sure we use a P2 address (non-cacheable) */
 267         port_info->rx_desc_base =
 268                 (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
 269
 270         port_info->rx_desc_cur = port_info->rx_desc_base;
 271
 272         /*
 273          * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
 274          * aligned and in P2 area.
 275          */
 276         port_info->rx_buf_alloc =
 277                 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
 278         if (!port_info->rx_buf_alloc) {
 279                 printf(SHETHER_NAME ": alloc failed\n");
 280                 ret = -ENOMEM;
 281                 goto err_buf_alloc;
 282         }
 283
 284         port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
 285
 286         /* Initialize all descriptors */
 287         for (cur_rx_desc = port_info->rx_desc_base,
 288              rx_buf = port_info->rx_buf_base, i = 0;
 289              i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
 290                 cur_rx_desc->rd0 = RD_RACT;
 291                 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
 292                 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
 293         }
 294
 295         /* Mark the end of the descriptors */
 296         cur_rx_desc--;
 297         cur_rx_desc->rd0 |= RD_RDLE;
 298
 299         /* Point the controller to the rx descriptor list */
 300         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
 301 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 302         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
 303         sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
 304         sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
 305 #endif
 306
 307         return ret;
 308
 309 err_buf_alloc:
 310         free(port_info->rx_desc_alloc);
 311         port_info->rx_desc_alloc = NULL;
 312
 313 err:
 314         return ret;
 315 }
 316
 317 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
 318 {
 319         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 320
 321         if (port_info->tx_desc_alloc) {
 322                 free(port_info->tx_desc_alloc);
 323                 port_info->tx_desc_alloc = NULL;
 324         }
 325 }
 326
 327 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
 328 {
 329         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 330
 331         if (port_info->rx_desc_alloc) {
 332                 free(port_info->rx_desc_alloc);
 333                 port_info->rx_desc_alloc = NULL;
 334         }
 335
 336         if (port_info->rx_buf_alloc) {
 337                 free(port_info->rx_buf_alloc);
 338                 port_info->rx_buf_alloc = NULL;
 339         }
 340 }
 341
 342 static int sh_eth_desc_init(struct sh_eth_dev *eth)
 343 {
 344         int ret = 0;
 345
 346         ret = sh_eth_tx_desc_init(eth);
 347         if (ret)
 348                 goto err_tx_init;
 349
 350         ret = sh_eth_rx_desc_init(eth);
 351         if (ret)
 352                 goto err_rx_init;
 353
 354         return ret;
 355 err_rx_init:
 356         sh_eth_tx_desc_free(eth);
 357
 358 err_tx_init:
 359         return ret;
 360 }
 361
 362 static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
 363                                 unsigned char *mac)
 364 {
 365         u32 val;
 366
 367         val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
 368         sh_eth_write(port_info, val, MAHR);
 369
 370         val = (mac[4] << 8) | mac[5];
 371         sh_eth_write(port_info, val, MALR);
 372 }
 373
 374 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
 375 {
 376         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 377
 378         /* Configure e-dmac registers */
 379         sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
 380                         (EMDR_DESC | EDMR_EL), EDMR);
 381
 382         sh_eth_write(port_info, 0, EESIPR);
 383         sh_eth_write(port_info, 0, TRSCER);
 384         sh_eth_write(port_info, 0, TFTR);
 385         sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
 386         sh_eth_write(port_info, RMCR_RST, RMCR);
 387 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 388         sh_eth_write(port_info, 0, RPADIR);
 389 #endif
 390         sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
 391
 392         /* Configure e-mac registers */
 393         sh_eth_write(port_info, 0, ECSIPR);
 394
 395         /* Set Mac address */
 396         sh_eth_write_hwaddr(port_info, mac);
 397
 398         sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
 399 #if defined(SH_ETH_TYPE_GETHER)
 400         sh_eth_write(port_info, 0, PIPR);
 401 #endif
 402 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 403         sh_eth_write(port_info, APR_AP, APR);
 404         sh_eth_write(port_info, MPR_MP, MPR);
 405         sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
 406 #endif
 407
 408 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 409         sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 410 #elif defined(CONFIG_RCAR_GEN2)
 411         sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
 412 #endif
 413 }
 414
 415 static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
 416 {
 417         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 418         struct phy_device *phy = port_info->phydev;
 419         int ret = 0;
 420         u32 val = 0;
 421
 422         /* Set the transfer speed */
 423         if (phy->speed == 100) {
 424                 printf(SHETHER_NAME ": 100Base/");
 425 #if defined(SH_ETH_TYPE_GETHER)
 426                 sh_eth_write(port_info, GECMR_100B, GECMR);
 427 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 428                 sh_eth_write(port_info, 1, RTRATE);
 429 #elif defined(CONFIG_RCAR_GEN2)
 430                 val = ECMR_RTM;
 431 #endif
 432         } else if (phy->speed == 10) {
 433                 printf(SHETHER_NAME ": 10Base/");
 434 #if defined(SH_ETH_TYPE_GETHER)
 435                 sh_eth_write(port_info, GECMR_10B, GECMR);
 436 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 437                 sh_eth_write(port_info, 0, RTRATE);
 438 #endif
 439         }
 440 #if defined(SH_ETH_TYPE_GETHER)
 441         else if (phy->speed == 1000) {
 442                 printf(SHETHER_NAME ": 1000Base/");
 443                 sh_eth_write(port_info, GECMR_1000B, GECMR);
 444         }
 445 #endif
 446
 447         /* Check if full duplex mode is supported by the phy */
 448         if (phy->duplex) {
 449                 printf("Full\n");
 450                 sh_eth_write(port_info,
 451                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
 452                              ECMR);
 453         } else {
 454                 printf("Half\n");
 455                 sh_eth_write(port_info,
 456                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
 457                              ECMR);
 458         }
 459
 460         return ret;
 461 }
 462
 463 static void sh_eth_start(struct sh_eth_dev *eth)
 464 {
 465         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 466
 467         /*
 468          * Enable the e-dmac receiver only. The transmitter will be enabled when
 469          * we have something to transmit
 470          */
 471         sh_eth_write(port_info, EDRRR_R, EDRRR);
 472 }
 473
 474 static void sh_eth_stop(struct sh_eth_dev *eth)
 475 {
 476         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 477
 478         sh_eth_write(port_info, ~EDRRR_R, EDRRR);
 479 }
 480
 481 static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
 482 {
 483         int ret = 0;
 484
 485         ret = sh_eth_reset(eth);
 486         if (ret)
 487                 return ret;
 488
 489         ret = sh_eth_desc_init(eth);
 490         if (ret)
 491                 return ret;
 492
 493         sh_eth_mac_regs_config(eth, mac);
 494
 495         return 0;
 496 }
 497
 498 static int sh_eth_start_common(struct sh_eth_dev *eth)
 499 {
 500         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 501         int ret;
 502
 503         ret = phy_startup(port_info->phydev);
 504         if (ret) {
 505                 printf(SHETHER_NAME ": phy startup failure\n");
 506                 return ret;
 507         }
 508
 509         ret = sh_eth_phy_regs_config(eth);
 510         if (ret)
 511                 return ret;
 512
 513         sh_eth_start(eth);
 514
 515         return 0;
 516 }
 517
 518 #ifndef CONFIG_DM_ETH
 519 static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
 520 {
 521         int ret = 0;
 522         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 523         struct eth_device *dev = port_info->dev;
 524         struct phy_device *phydev;
 525
 526         phydev = phy_connect(
 527                         miiphy_get_dev_by_name(dev->name),
 528                         port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
 529         port_info->phydev = phydev;
 530         phy_config(phydev);
 531
 532         return ret;
 533 }
 534
 535 static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
 536 {
 537         struct sh_eth_dev *eth = dev->priv;
 538
 539         return sh_eth_send_common(eth, packet, len);
 540 }
 541
 542 static int sh_eth_recv_common(struct sh_eth_dev *eth)
 543 {
 544         int len = 0;
 545         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 546         uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
 547
 548         len = sh_eth_recv_start(eth);
 549         if (len > 0) {
 550                 invalidate_cache(packet, len);
 551                 net_process_received_packet(packet, len);
 552                 sh_eth_recv_finish(eth);
 553         } else
 554                 len = 0;
 555
 556         /* Restart the receiver if disabled */
 557         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 558                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 559
 560         return len;
 561 }
 562
 563 static int sh_eth_recv_legacy(struct eth_device *dev)
 564 {
 565         struct sh_eth_dev *eth = dev->priv;
 566
 567         return sh_eth_recv_common(eth);
 568 }
 569
 570 static int sh_eth_init_legacy(struct eth_device *dev, bd_t *bd)
 571 {
 572         struct sh_eth_dev *eth = dev->priv;
 573         int ret;
 574
 575         ret = sh_eth_init_common(eth, dev->enetaddr);
 576         if (ret)
 577                 return ret;
 578
 579         ret = sh_eth_phy_config_legacy(eth);
 580         if (ret) {
 581                 printf(SHETHER_NAME ": phy config timeout\n");
 582                 goto err_start;
 583         }
 584
 585         ret = sh_eth_start_common(eth);
 586         if (ret)
 587                 goto err_start;
 588
 589         return 0;
 590
 591 err_start:
 592         sh_eth_tx_desc_free(eth);
 593         sh_eth_rx_desc_free(eth);
 594         return ret;
 595 }
 596
 597 void sh_eth_halt_legacy(struct eth_device *dev)
 598 {
 599         struct sh_eth_dev *eth = dev->priv;
 600
 601         sh_eth_stop(eth);
 602 }
 603
 604 int sh_eth_initialize(bd_t *bd)
 605 {
 606         int ret = 0;
 607         struct sh_eth_dev *eth = NULL;
 608         struct eth_device *dev = NULL;
 609         struct mii_dev *mdiodev;
 610
 611         eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
 612         if (!eth) {
 613                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 614                 ret = -ENOMEM;
 615                 goto err;
 616         }
 617
 618         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
 619         if (!dev) {
 620                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 621                 ret = -ENOMEM;
 622                 goto err;
 623         }
 624         memset(dev, 0, sizeof(struct eth_device));
 625         memset(eth, 0, sizeof(struct sh_eth_dev));
 626
 627         eth->port = CONFIG_SH_ETHER_USE_PORT;
 628         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 629         eth->port_info[eth->port].iobase =
 630                 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
 631
 632         dev->priv = (void *)eth;
 633         dev->iobase = 0;
 634         dev->init = sh_eth_init_legacy;
 635         dev->halt = sh_eth_halt_legacy;
 636         dev->send = sh_eth_send_legacy;
 637         dev->recv = sh_eth_recv_legacy;
 638         eth->port_info[eth->port].dev = dev;
 639
 640         strcpy(dev->name, SHETHER_NAME);
 641
 642         /* Register Device to EtherNet subsystem  */
 643         eth_register(dev);
 644
 645         bb_miiphy_buses[0].priv = eth;
 646         mdiodev = mdio_alloc();
 647         if (!mdiodev)
 648                 return -ENOMEM;
 649         strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 650         mdiodev->read = bb_miiphy_read;
 651         mdiodev->write = bb_miiphy_write;
 652
 653         ret = mdio_register(mdiodev);
 654         if (ret < 0)
 655                 return ret;
 656
 657         if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
 658                 puts("Please set MAC address\n");
 659
 660         return ret;
 661
 662 err:
 663         if (dev)
 664                 free(dev);
 665
 666         if (eth)
 667                 free(eth);
 668
 669         printf(SHETHER_NAME ": Failed\n");
 670         return ret;
 671 }
 672
 673 #else /* CONFIG_DM_ETH */
 674
 675 struct sh_ether_priv {
 676         struct sh_eth_dev       shdev;
 677
 678         struct mii_dev          *bus;
 679         phys_addr_t             iobase;
 680         struct clk              clk;
 681         struct gpio_desc        reset_gpio;
 682 };
 683
 684 static int sh_ether_send(struct udevice *dev, void *packet, int len)
 685 {
 686         struct sh_ether_priv *priv = dev_get_priv(dev);
 687         struct sh_eth_dev *eth = &priv->shdev;
 688
 689         return sh_eth_send_common(eth, packet, len);
 690 }
 691
 692 static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
 693 {
 694         struct sh_ether_priv *priv = dev_get_priv(dev);
 695         struct sh_eth_dev *eth = &priv->shdev;
 696         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 697         uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
 698         int len;
 699
 700         len = sh_eth_recv_start(eth);
 701         if (len > 0) {
 702                 invalidate_cache(packet, len);
 703                 *packetp = packet;
 704
 705                 return len;
 706         } else {
 707                 len = 0;
 708
 709                 /* Restart the receiver if disabled */
 710                 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 711                         sh_eth_write(port_info, EDRRR_R, EDRRR);
 712
 713                 return -EAGAIN;
 714         }
 715 }
 716
 717 static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
 718 {
 719         struct sh_ether_priv *priv = dev_get_priv(dev);
 720         struct sh_eth_dev *eth = &priv->shdev;
 721         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 722
 723         sh_eth_recv_finish(eth);
 724
 725         /* Restart the receiver if disabled */
 726         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 727                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 728
 729         return 0;
 730 }
 731
 732 static int sh_ether_write_hwaddr(struct udevice *dev)
 733 {
 734         struct sh_ether_priv *priv = dev_get_priv(dev);
 735         struct sh_eth_dev *eth = &priv->shdev;
 736         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 737         struct eth_pdata *pdata = dev_get_platdata(dev);
 738
 739         sh_eth_write_hwaddr(port_info, pdata->enetaddr);
 740
 741         return 0;
 742 }
 743
 744 static int sh_eth_phy_config(struct udevice *dev)
 745 {
 746         struct sh_ether_priv *priv = dev_get_priv(dev);
 747         struct eth_pdata *pdata = dev_get_platdata(dev);
 748         struct sh_eth_dev *eth = &priv->shdev;
 749         int ret = 0;
 750         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 751         struct phy_device *phydev;
 752         int mask = 0xffffffff;
 753
 754         phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface);
 755         if (!phydev)
 756                 return -ENODEV;
 757
 758         phy_connect_dev(phydev, dev);
 759
 760         port_info->phydev = phydev;
 761         phy_config(phydev);
 762
 763         return ret;
 764 }
 765
 766 static int sh_ether_start(struct udevice *dev)
 767 {
 768         struct sh_ether_priv *priv = dev_get_priv(dev);
 769         struct eth_pdata *pdata = dev_get_platdata(dev);
 770         struct sh_eth_dev *eth = &priv->shdev;
 771         int ret;
 772
 773         ret = sh_eth_init_common(eth, pdata->enetaddr);
 774         if (ret)
 775                 return ret;
 776
 777         ret = sh_eth_start_common(eth);
 778         if (ret)
 779                 goto err_start;
 780
 781         return 0;
 782
 783 err_start:
 784         sh_eth_tx_desc_free(eth);
 785         sh_eth_rx_desc_free(eth);
 786         return ret;
 787 }
 788
 789 static void sh_ether_stop(struct udevice *dev)
 790 {
 791         struct sh_ether_priv *priv = dev_get_priv(dev);
 792         struct sh_eth_dev *eth = &priv->shdev;
 793         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 794
 795         phy_shutdown(port_info->phydev);
 796         sh_eth_stop(&priv->shdev);
 797 }
 798
 799 static int sh_ether_probe(struct udevice *udev)
 800 {
 801         struct eth_pdata *pdata = dev_get_platdata(udev);
 802         struct sh_ether_priv *priv = dev_get_priv(udev);
 803         struct sh_eth_dev *eth = &priv->shdev;
 804         struct ofnode_phandle_args phandle_args;
 805         struct mii_dev *mdiodev;
 806         int ret;
 807
 808         priv->iobase = pdata->iobase;
 809
 810 #if CONFIG_IS_ENABLED(CLK)
 811         ret = clk_get_by_index(udev, 0, &priv->clk);
 812         if (ret < 0)
 813                 return ret;
 814 #endif
 815
 816         ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
 817         if (!ret) {
 818                 gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
 819                                            &priv->reset_gpio, GPIOD_IS_OUT);
 820         }
 821
 822         if (!dm_gpio_is_valid(&priv->reset_gpio)) {
 823                 gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
 824                                      GPIOD_IS_OUT);
 825         }
 826
 827         mdiodev = mdio_alloc();
 828         if (!mdiodev) {
 829                 ret = -ENOMEM;
 830                 return ret;
 831         }
 832
 833         mdiodev->read = bb_miiphy_read;
 834         mdiodev->write = bb_miiphy_write;
 835         bb_miiphy_buses[0].priv = eth;
 836         snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
 837
 838         ret = mdio_register(mdiodev);
 839         if (ret < 0)
 840                 goto err_mdio_register;
 841
 842         priv->bus = miiphy_get_dev_by_name(udev->name);
 843
 844         eth->port = CONFIG_SH_ETHER_USE_PORT;
 845         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 846         eth->port_info[eth->port].iobase =
 847                 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
 848
 849 #if CONFIG_IS_ENABLED(CLK)
 850         ret = clk_enable(&priv->clk);
 851         if (ret)
 852                 goto err_mdio_register;
 853 #endif
 854
 855         ret = sh_eth_phy_config(udev);
 856         if (ret) {
 857                 printf(SHETHER_NAME ": phy config timeout\n");
 858                 goto err_phy_config;
 859         }
 860
 861         return 0;
 862
 863 err_phy_config:
 864 #if CONFIG_IS_ENABLED(CLK)
 865         clk_disable(&priv->clk);
 866 #endif
 867 err_mdio_register:
 868         mdio_free(mdiodev);
 869         return ret;
 870 }
 871
 872 static int sh_ether_remove(struct udevice *udev)
 873 {
 874         struct sh_ether_priv *priv = dev_get_priv(udev);
 875         struct sh_eth_dev *eth = &priv->shdev;
 876         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 877
 878 #if CONFIG_IS_ENABLED(CLK)
 879         clk_disable(&priv->clk);
 880 #endif
 881         free(port_info->phydev);
 882         mdio_unregister(priv->bus);
 883         mdio_free(priv->bus);
 884
 885         if (dm_gpio_is_valid(&priv->reset_gpio))
 886                 dm_gpio_free(udev, &priv->reset_gpio);
 887
 888         return 0;
 889 }
 890
 891 static const struct eth_ops sh_ether_ops = {
 892         .start                  = sh_ether_start,
 893         .send                   = sh_ether_send,
 894         .recv                   = sh_ether_recv,
 895         .free_pkt               = sh_ether_free_pkt,
 896         .stop                   = sh_ether_stop,
 897         .write_hwaddr           = sh_ether_write_hwaddr,
 898 };
 899
 900 int sh_ether_ofdata_to_platdata(struct udevice *dev)
 901 {
 902         struct eth_pdata *pdata = dev_get_platdata(dev);
 903         const char *phy_mode;
 904         const fdt32_t *cell;
 905         int ret = 0;
 906
 907         pdata->iobase = devfdt_get_addr(dev);
 908         pdata->phy_interface = -1;
 909         phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
 910                                NULL);
 911         if (phy_mode)
 912                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 913         if (pdata->phy_interface == -1) {
 914                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 915                 return -EINVAL;
 916         }
 917
 918         pdata->max_speed = 1000;
 919         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
 920         if (cell)
 921                 pdata->max_speed = fdt32_to_cpu(*cell);
 922
 923         sprintf(bb_miiphy_buses[0].name, dev->name);
 924
 925         return ret;
 926 }
 927
 928 static const struct udevice_id sh_ether_ids[] = {
 929         { .compatible = "renesas,ether-r7s72100" },
 930         { .compatible = "renesas,ether-r8a7790" },
 931         { .compatible = "renesas,ether-r8a7791" },
 932         { .compatible = "renesas,ether-r8a7793" },
 933         { .compatible = "renesas,ether-r8a7794" },
 934         { }
 935 };
 936
 937 U_BOOT_DRIVER(eth_sh_ether) = {
 938         .name           = "sh_ether",
 939         .id             = UCLASS_ETH,
 940         .of_match       = sh_ether_ids,
 941         .ofdata_to_platdata = sh_ether_ofdata_to_platdata,
 942         .probe          = sh_ether_probe,
 943         .remove         = sh_ether_remove,
 944         .ops            = &sh_ether_ops,
 945         .priv_auto_alloc_size = sizeof(struct sh_ether_priv),
 946         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 947         .flags          = DM_FLAG_ALLOC_PRIV_DMA,
 948 };
 949 #endif
 950
 951 /******* for bb_miiphy *******/
 952 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 953 {
 954         return 0;
 955 }
 956
 957 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 958 {
 959         struct sh_eth_dev *eth = bus->priv;
 960         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 961
 962         sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
 963
 964         return 0;
 965 }
 966
 967 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 968 {
 969         struct sh_eth_dev *eth = bus->priv;
 970         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 971
 972         sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
 973
 974         return 0;
 975 }
 976
 977 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 978 {
 979         struct sh_eth_dev *eth = bus->priv;
 980         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 981
 982         if (v)
 983                 sh_eth_write(port_info,
 984                              sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
 985         else
 986                 sh_eth_write(port_info,
 987                              sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
 988
 989         return 0;
 990 }
 991
 992 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
 993 {
 994         struct sh_eth_dev *eth = bus->priv;
 995         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 996
 997         *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
 998
 999         return 0;
1000 }
1001
1002 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
1003 {
1004         struct sh_eth_dev *eth = bus->priv;
1005         struct sh_eth_info *port_info = &eth->port_info[eth->port];
1006
1007         if (v)
1008                 sh_eth_write(port_info,
1009                              sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
1010         else
1011                 sh_eth_write(port_info,
1012                              sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
1013
1014         return 0;
1015 }
1016
1017 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
1018 {
1019         udelay(10);
1020
1021         return 0;
1022 }
1023
1024 struct bb_miiphy_bus bb_miiphy_buses[] = {
1025         {
1026                 .name           = "sh_eth",
1027                 .init           = sh_eth_bb_init,
1028                 .mdio_active    = sh_eth_bb_mdio_active,
1029                 .mdio_tristate  = sh_eth_bb_mdio_tristate,
1030                 .set_mdio       = sh_eth_bb_set_mdio,
1031                 .get_mdio       = sh_eth_bb_get_mdio,
1032                 .set_mdc        = sh_eth_bb_set_mdc,
1033                 .delay          = sh_eth_bb_delay,
1034         }
1035 };
1036
1037 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);