1 // SPDX-License-Identifier: GPL-2.0+
3 * sh_eth.c - Driver for Renesas ethernet controller.
5 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
6 * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
7 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
8 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
20 #include <asm/cache.h>
21 #include <linux/delay.h>
22 #include <linux/errno.h>
28 #include <linux/mii.h>
34 #ifndef CONFIG_SH_ETHER_USE_PORT
35 # error "Please define CONFIG_SH_ETHER_USE_PORT"
37 #ifndef CONFIG_SH_ETHER_PHY_ADDR
38 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
41 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
42 !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
43 #define flush_cache_wback(addr, len) \
44 flush_dcache_range((unsigned long)addr, \
45 (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
47 #define flush_cache_wback(...)
50 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
51 #define invalidate_cache(addr, len) \
53 unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
54 unsigned long start, end; \
56 start = (unsigned long)addr; \
58 start &= ~(line_size - 1); \
59 end = ((end + line_size - 1) & ~(line_size - 1)); \
61 invalidate_dcache_range(start, end); \
64 #define invalidate_cache(...)
67 #define TIMEOUT_CNT 1000
69 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
72 struct sh_eth_info *port_info = ð->port_info[eth->port];
74 if (!packet || len > 0xffff) {
75 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
80 /* packet must be a 4 byte boundary */
81 if ((uintptr_t)packet & 3) {
82 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
88 /* Update tx descriptor */
89 flush_cache_wback(packet, len);
90 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
91 port_info->tx_desc_cur->td1 = len << 16;
92 /* Must preserve the end of descriptor list indication */
93 if (port_info->tx_desc_cur->td0 & TD_TDLE)
94 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
96 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
98 flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
100 /* Restart the transmitter if disabled */
101 if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
102 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
104 /* Wait until packet is transmitted */
105 timeout = TIMEOUT_CNT;
107 invalidate_cache(port_info->tx_desc_cur,
108 sizeof(struct tx_desc_s));
110 } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
113 printf(SHETHER_NAME ": transmit timeout\n");
118 port_info->tx_desc_cur++;
119 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
120 port_info->tx_desc_cur = port_info->tx_desc_base;
126 static int sh_eth_recv_start(struct sh_eth_dev *eth)
128 struct sh_eth_info *port_info = ð->port_info[eth->port];
130 /* Check if the rx descriptor is ready */
131 invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
132 if (port_info->rx_desc_cur->rd0 & RD_RACT)
135 /* Check for errors */
136 if (port_info->rx_desc_cur->rd0 & RD_RFE)
139 return port_info->rx_desc_cur->rd1 & 0xffff;
142 static void sh_eth_recv_finish(struct sh_eth_dev *eth)
144 struct sh_eth_info *port_info = ð->port_info[eth->port];
146 /* Make current descriptor available again */
147 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
148 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
150 port_info->rx_desc_cur->rd0 = RD_RACT;
152 flush_cache_wback(port_info->rx_desc_cur,
153 sizeof(struct rx_desc_s));
155 /* Point to the next descriptor */
156 port_info->rx_desc_cur++;
157 if (port_info->rx_desc_cur >=
158 port_info->rx_desc_base + NUM_RX_DESC)
159 port_info->rx_desc_cur = port_info->rx_desc_base;
162 static int sh_eth_reset(struct sh_eth_dev *eth)
164 struct sh_eth_info *port_info = ð->port_info[eth->port];
165 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
168 /* Start e-dmac transmitter and receiver */
169 sh_eth_write(port_info, EDSR_ENALL, EDSR);
171 /* Perform a software reset and wait for it to complete */
172 sh_eth_write(port_info, EDMR_SRST, EDMR);
173 for (i = 0; i < TIMEOUT_CNT; i++) {
174 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
179 if (i == TIMEOUT_CNT) {
180 printf(SHETHER_NAME ": Software reset timeout\n");
186 sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
188 sh_eth_write(port_info,
189 sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
195 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
198 u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
199 struct sh_eth_info *port_info = ð->port_info[eth->port];
200 struct tx_desc_s *cur_tx_desc;
203 * Allocate rx descriptors. They must be aligned to size of struct
206 port_info->tx_desc_alloc =
207 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
208 if (!port_info->tx_desc_alloc) {
209 printf(SHETHER_NAME ": memalign failed\n");
214 flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
216 /* Make sure we use a P2 address (non-cacheable) */
217 port_info->tx_desc_base =
218 (struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
219 port_info->tx_desc_cur = port_info->tx_desc_base;
221 /* Initialize all descriptors */
222 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
223 cur_tx_desc++, i++) {
224 cur_tx_desc->td0 = 0x00;
225 cur_tx_desc->td1 = 0x00;
226 cur_tx_desc->td2 = 0x00;
229 /* Mark the end of the descriptors */
231 cur_tx_desc->td0 |= TD_TDLE;
234 * Point the controller to the tx descriptor list. Must use physical
237 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
238 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
239 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
240 sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
241 sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
248 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
251 u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
252 struct sh_eth_info *port_info = ð->port_info[eth->port];
253 struct rx_desc_s *cur_rx_desc;
257 * Allocate rx descriptors. They must be aligned to size of struct
260 port_info->rx_desc_alloc =
261 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
262 if (!port_info->rx_desc_alloc) {
263 printf(SHETHER_NAME ": memalign failed\n");
268 flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
270 /* Make sure we use a P2 address (non-cacheable) */
271 port_info->rx_desc_base =
272 (struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
274 port_info->rx_desc_cur = port_info->rx_desc_base;
277 * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
278 * aligned and in P2 area.
280 port_info->rx_buf_alloc =
281 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
282 if (!port_info->rx_buf_alloc) {
283 printf(SHETHER_NAME ": alloc failed\n");
288 port_info->rx_buf_base = (u8 *)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
290 /* Initialize all descriptors */
291 for (cur_rx_desc = port_info->rx_desc_base,
292 rx_buf = port_info->rx_buf_base, i = 0;
293 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
294 cur_rx_desc->rd0 = RD_RACT;
295 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
296 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
299 /* Mark the end of the descriptors */
301 cur_rx_desc->rd0 |= RD_RDLE;
303 /* Point the controller to the rx descriptor list */
304 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
305 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
306 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
307 sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
308 sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
314 free(port_info->rx_desc_alloc);
315 port_info->rx_desc_alloc = NULL;
321 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
323 struct sh_eth_info *port_info = ð->port_info[eth->port];
325 if (port_info->tx_desc_alloc) {
326 free(port_info->tx_desc_alloc);
327 port_info->tx_desc_alloc = NULL;
331 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
333 struct sh_eth_info *port_info = ð->port_info[eth->port];
335 if (port_info->rx_desc_alloc) {
336 free(port_info->rx_desc_alloc);
337 port_info->rx_desc_alloc = NULL;
340 if (port_info->rx_buf_alloc) {
341 free(port_info->rx_buf_alloc);
342 port_info->rx_buf_alloc = NULL;
346 static int sh_eth_desc_init(struct sh_eth_dev *eth)
350 ret = sh_eth_tx_desc_init(eth);
354 ret = sh_eth_rx_desc_init(eth);
360 sh_eth_tx_desc_free(eth);
366 static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
371 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
372 sh_eth_write(port_info, val, MAHR);
374 val = (mac[4] << 8) | mac[5];
375 sh_eth_write(port_info, val, MALR);
378 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
380 struct sh_eth_info *port_info = ð->port_info[eth->port];
383 /* Configure e-dmac registers */
384 edmr = sh_eth_read(port_info, EDMR);
385 edmr &= ~EMDR_DESC_R;
386 edmr |= EMDR_DESC | EDMR_EL;
387 #if defined(CONFIG_R8A77980)
390 sh_eth_write(port_info, edmr, EDMR);
392 sh_eth_write(port_info, 0, EESIPR);
393 sh_eth_write(port_info, 0, TRSCER);
394 sh_eth_write(port_info, 0, TFTR);
395 sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
396 sh_eth_write(port_info, RMCR_RST, RMCR);
397 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
398 sh_eth_write(port_info, 0, RPADIR);
400 sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
402 /* Configure e-mac registers */
403 sh_eth_write(port_info, 0, ECSIPR);
405 /* Set Mac address */
406 sh_eth_write_hwaddr(port_info, mac);
408 sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
409 #if defined(SH_ETH_TYPE_GETHER)
410 sh_eth_write(port_info, 0, PIPR);
412 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
413 sh_eth_write(port_info, APR_AP, APR);
414 sh_eth_write(port_info, MPR_MP, MPR);
415 sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
418 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
419 sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
420 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
421 sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
425 static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
427 struct sh_eth_info *port_info = ð->port_info[eth->port];
428 struct phy_device *phy = port_info->phydev;
432 /* Set the transfer speed */
433 if (phy->speed == 100) {
434 printf(SHETHER_NAME ": 100Base/");
435 #if defined(SH_ETH_TYPE_GETHER)
436 sh_eth_write(port_info, GECMR_100B, GECMR);
437 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
438 sh_eth_write(port_info, 1, RTRATE);
439 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
442 } else if (phy->speed == 10) {
443 printf(SHETHER_NAME ": 10Base/");
444 #if defined(SH_ETH_TYPE_GETHER)
445 sh_eth_write(port_info, GECMR_10B, GECMR);
446 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
447 sh_eth_write(port_info, 0, RTRATE);
450 #if defined(SH_ETH_TYPE_GETHER)
451 else if (phy->speed == 1000) {
452 printf(SHETHER_NAME ": 1000Base/");
453 sh_eth_write(port_info, GECMR_1000B, GECMR);
457 /* Check if full duplex mode is supported by the phy */
460 sh_eth_write(port_info,
461 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
465 sh_eth_write(port_info,
466 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
473 static void sh_eth_start(struct sh_eth_dev *eth)
475 struct sh_eth_info *port_info = ð->port_info[eth->port];
478 * Enable the e-dmac receiver only. The transmitter will be enabled when
479 * we have something to transmit
481 sh_eth_write(port_info, EDRRR_R, EDRRR);
484 static void sh_eth_stop(struct sh_eth_dev *eth)
486 struct sh_eth_info *port_info = ð->port_info[eth->port];
488 sh_eth_write(port_info, ~EDRRR_R, EDRRR);
491 static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
495 ret = sh_eth_reset(eth);
499 ret = sh_eth_desc_init(eth);
503 sh_eth_mac_regs_config(eth, mac);
508 static int sh_eth_start_common(struct sh_eth_dev *eth)
510 struct sh_eth_info *port_info = ð->port_info[eth->port];
513 ret = phy_startup(port_info->phydev);
515 printf(SHETHER_NAME ": phy startup failure\n");
519 ret = sh_eth_phy_regs_config(eth);
528 #ifndef CONFIG_DM_ETH
529 static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
532 struct sh_eth_info *port_info = ð->port_info[eth->port];
533 struct eth_device *dev = port_info->dev;
534 struct phy_device *phydev;
536 phydev = phy_connect(
537 miiphy_get_dev_by_name(dev->name),
538 port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
539 port_info->phydev = phydev;
545 static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
547 struct sh_eth_dev *eth = dev->priv;
549 return sh_eth_send_common(eth, packet, len);
552 static int sh_eth_recv_common(struct sh_eth_dev *eth)
555 struct sh_eth_info *port_info = ð->port_info[eth->port];
556 uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
558 len = sh_eth_recv_start(eth);
560 invalidate_cache(packet, len);
561 net_process_received_packet(packet, len);
562 sh_eth_recv_finish(eth);
566 /* Restart the receiver if disabled */
567 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
568 sh_eth_write(port_info, EDRRR_R, EDRRR);
573 static int sh_eth_recv_legacy(struct eth_device *dev)
575 struct sh_eth_dev *eth = dev->priv;
577 return sh_eth_recv_common(eth);
580 static int sh_eth_init_legacy(struct eth_device *dev, struct bd_info *bd)
582 struct sh_eth_dev *eth = dev->priv;
585 ret = sh_eth_init_common(eth, dev->enetaddr);
589 ret = sh_eth_phy_config_legacy(eth);
591 printf(SHETHER_NAME ": phy config timeout\n");
595 ret = sh_eth_start_common(eth);
602 sh_eth_tx_desc_free(eth);
603 sh_eth_rx_desc_free(eth);
607 void sh_eth_halt_legacy(struct eth_device *dev)
609 struct sh_eth_dev *eth = dev->priv;
614 int sh_eth_initialize(struct bd_info *bd)
617 struct sh_eth_dev *eth = NULL;
618 struct eth_device *dev = NULL;
619 struct mii_dev *mdiodev;
621 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
623 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
628 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
630 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
634 memset(dev, 0, sizeof(struct eth_device));
635 memset(eth, 0, sizeof(struct sh_eth_dev));
637 eth->port = CONFIG_SH_ETHER_USE_PORT;
638 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
639 eth->port_info[eth->port].iobase =
640 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
642 dev->priv = (void *)eth;
644 dev->init = sh_eth_init_legacy;
645 dev->halt = sh_eth_halt_legacy;
646 dev->send = sh_eth_send_legacy;
647 dev->recv = sh_eth_recv_legacy;
648 eth->port_info[eth->port].dev = dev;
650 strcpy(dev->name, SHETHER_NAME);
652 /* Register Device to EtherNet subsystem */
655 bb_miiphy_buses[0].priv = eth;
656 mdiodev = mdio_alloc();
659 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
660 mdiodev->read = bb_miiphy_read;
661 mdiodev->write = bb_miiphy_write;
663 ret = mdio_register(mdiodev);
667 if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
668 puts("Please set MAC address\n");
679 printf(SHETHER_NAME ": Failed\n");
683 #else /* CONFIG_DM_ETH */
685 struct sh_ether_priv {
686 struct sh_eth_dev shdev;
691 struct gpio_desc reset_gpio;
694 static int sh_ether_send(struct udevice *dev, void *packet, int len)
696 struct sh_ether_priv *priv = dev_get_priv(dev);
697 struct sh_eth_dev *eth = &priv->shdev;
699 return sh_eth_send_common(eth, packet, len);
702 static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
704 struct sh_ether_priv *priv = dev_get_priv(dev);
705 struct sh_eth_dev *eth = &priv->shdev;
706 struct sh_eth_info *port_info = ð->port_info[eth->port];
707 uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
710 len = sh_eth_recv_start(eth);
712 invalidate_cache(packet, len);
719 /* Restart the receiver if disabled */
720 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
721 sh_eth_write(port_info, EDRRR_R, EDRRR);
727 static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
729 struct sh_ether_priv *priv = dev_get_priv(dev);
730 struct sh_eth_dev *eth = &priv->shdev;
731 struct sh_eth_info *port_info = ð->port_info[eth->port];
733 sh_eth_recv_finish(eth);
735 /* Restart the receiver if disabled */
736 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
737 sh_eth_write(port_info, EDRRR_R, EDRRR);
742 static int sh_ether_write_hwaddr(struct udevice *dev)
744 struct sh_ether_priv *priv = dev_get_priv(dev);
745 struct sh_eth_dev *eth = &priv->shdev;
746 struct sh_eth_info *port_info = ð->port_info[eth->port];
747 struct eth_pdata *pdata = dev_get_platdata(dev);
749 sh_eth_write_hwaddr(port_info, pdata->enetaddr);
754 static int sh_eth_phy_config(struct udevice *dev)
756 struct sh_ether_priv *priv = dev_get_priv(dev);
757 struct eth_pdata *pdata = dev_get_platdata(dev);
758 struct sh_eth_dev *eth = &priv->shdev;
760 struct sh_eth_info *port_info = ð->port_info[eth->port];
761 struct phy_device *phydev;
762 int mask = 0xffffffff;
764 phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface);
768 phy_connect_dev(phydev, dev);
770 port_info->phydev = phydev;
776 static int sh_ether_start(struct udevice *dev)
778 struct sh_ether_priv *priv = dev_get_priv(dev);
779 struct eth_pdata *pdata = dev_get_platdata(dev);
780 struct sh_eth_dev *eth = &priv->shdev;
783 ret = sh_eth_init_common(eth, pdata->enetaddr);
787 ret = sh_eth_start_common(eth);
794 sh_eth_tx_desc_free(eth);
795 sh_eth_rx_desc_free(eth);
799 static void sh_ether_stop(struct udevice *dev)
801 struct sh_ether_priv *priv = dev_get_priv(dev);
802 struct sh_eth_dev *eth = &priv->shdev;
803 struct sh_eth_info *port_info = ð->port_info[eth->port];
805 phy_shutdown(port_info->phydev);
806 sh_eth_stop(&priv->shdev);
809 static int sh_ether_probe(struct udevice *udev)
811 struct eth_pdata *pdata = dev_get_platdata(udev);
812 struct sh_ether_priv *priv = dev_get_priv(udev);
813 struct sh_eth_dev *eth = &priv->shdev;
814 struct ofnode_phandle_args phandle_args;
815 struct mii_dev *mdiodev;
818 priv->iobase = pdata->iobase;
820 #if CONFIG_IS_ENABLED(CLK)
821 ret = clk_get_by_index(udev, 0, &priv->clk);
826 ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
828 gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
829 &priv->reset_gpio, GPIOD_IS_OUT);
832 if (!dm_gpio_is_valid(&priv->reset_gpio)) {
833 gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
837 mdiodev = mdio_alloc();
843 mdiodev->read = bb_miiphy_read;
844 mdiodev->write = bb_miiphy_write;
845 bb_miiphy_buses[0].priv = eth;
846 snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
848 ret = mdio_register(mdiodev);
850 goto err_mdio_register;
852 priv->bus = miiphy_get_dev_by_name(udev->name);
854 eth->port = CONFIG_SH_ETHER_USE_PORT;
855 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
856 eth->port_info[eth->port].iobase =
857 (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
859 #if CONFIG_IS_ENABLED(CLK)
860 ret = clk_enable(&priv->clk);
862 goto err_mdio_register;
865 ret = sh_eth_init_common(eth, pdata->enetaddr);
869 ret = sh_eth_phy_config(udev);
871 printf(SHETHER_NAME ": phy config timeout\n");
878 #if CONFIG_IS_ENABLED(CLK)
879 clk_disable(&priv->clk);
886 static int sh_ether_remove(struct udevice *udev)
888 struct sh_ether_priv *priv = dev_get_priv(udev);
889 struct sh_eth_dev *eth = &priv->shdev;
890 struct sh_eth_info *port_info = ð->port_info[eth->port];
892 #if CONFIG_IS_ENABLED(CLK)
893 clk_disable(&priv->clk);
895 free(port_info->phydev);
896 mdio_unregister(priv->bus);
897 mdio_free(priv->bus);
899 if (dm_gpio_is_valid(&priv->reset_gpio))
900 dm_gpio_free(udev, &priv->reset_gpio);
905 static const struct eth_ops sh_ether_ops = {
906 .start = sh_ether_start,
907 .send = sh_ether_send,
908 .recv = sh_ether_recv,
909 .free_pkt = sh_ether_free_pkt,
910 .stop = sh_ether_stop,
911 .write_hwaddr = sh_ether_write_hwaddr,
914 int sh_ether_ofdata_to_platdata(struct udevice *dev)
916 struct eth_pdata *pdata = dev_get_platdata(dev);
917 const char *phy_mode;
921 pdata->iobase = dev_read_addr(dev);
922 pdata->phy_interface = -1;
923 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
926 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
927 if (pdata->phy_interface == -1) {
928 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
932 pdata->max_speed = 1000;
933 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
935 pdata->max_speed = fdt32_to_cpu(*cell);
937 sprintf(bb_miiphy_buses[0].name, dev->name);
942 static const struct udevice_id sh_ether_ids[] = {
943 { .compatible = "renesas,ether-r7s72100" },
944 { .compatible = "renesas,ether-r8a7790" },
945 { .compatible = "renesas,ether-r8a7791" },
946 { .compatible = "renesas,ether-r8a7793" },
947 { .compatible = "renesas,ether-r8a7794" },
948 { .compatible = "renesas,gether-r8a77980" },
952 U_BOOT_DRIVER(eth_sh_ether) = {
955 .of_match = sh_ether_ids,
956 .ofdata_to_platdata = sh_ether_ofdata_to_platdata,
957 .probe = sh_ether_probe,
958 .remove = sh_ether_remove,
959 .ops = &sh_ether_ops,
960 .priv_auto = sizeof(struct sh_ether_priv),
961 .platdata_auto = sizeof(struct eth_pdata),
962 .flags = DM_FLAG_ALLOC_PRIV_DMA,
966 /******* for bb_miiphy *******/
967 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
972 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
974 struct sh_eth_dev *eth = bus->priv;
975 struct sh_eth_info *port_info = ð->port_info[eth->port];
977 sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
982 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
984 struct sh_eth_dev *eth = bus->priv;
985 struct sh_eth_info *port_info = ð->port_info[eth->port];
987 sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
992 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
994 struct sh_eth_dev *eth = bus->priv;
995 struct sh_eth_info *port_info = ð->port_info[eth->port];
998 sh_eth_write(port_info,
999 sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
1001 sh_eth_write(port_info,
1002 sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
1007 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
1009 struct sh_eth_dev *eth = bus->priv;
1010 struct sh_eth_info *port_info = ð->port_info[eth->port];
1012 *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
1017 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
1019 struct sh_eth_dev *eth = bus->priv;
1020 struct sh_eth_info *port_info = ð->port_info[eth->port];
1023 sh_eth_write(port_info,
1024 sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
1026 sh_eth_write(port_info,
1027 sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
1032 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
1039 struct bb_miiphy_bus bb_miiphy_buses[] = {
1042 .init = sh_eth_bb_init,
1043 .mdio_active = sh_eth_bb_mdio_active,
1044 .mdio_tristate = sh_eth_bb_mdio_tristate,
1045 .set_mdio = sh_eth_bb_set_mdio,
1046 .get_mdio = sh_eth_bb_get_mdio,
1047 .set_mdc = sh_eth_bb_set_mdc,
1048 .delay = sh_eth_bb_delay,
1052 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);